xref: /openbmc/linux/drivers/net/ethernet/sun/cassini.c (revision add48ba4)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
3  *
4  * Copyright (C) 2004 Sun Microsystems Inc.
5  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
6  *
7  * This driver uses the sungem driver (c) David Miller
8  * (davem@redhat.com) as its basis.
9  *
10  * The cassini chip has a number of features that distinguish it from
11  * the gem chip:
12  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
13  *      load balancing (non-VLAN mode)
14  *  batching of multiple packets
15  *  multiple CPU dispatching
16  *  page-based RX descriptor engine with separate completion rings
17  *  Gigabit support (GMII and PCS interface)
18  *  MIF link up/down detection works
19  *
20  * RX is handled by page sized buffers that are attached as fragments to
21  * the skb. here's what's done:
22  *  -- driver allocates pages at a time and keeps reference counts
23  *     on them.
24  *  -- the upper protocol layers assume that the header is in the skb
25  *     itself. as a result, cassini will copy a small amount (64 bytes)
26  *     to make them happy.
27  *  -- driver appends the rest of the data pages as frags to skbuffs
28  *     and increments the reference count
29  *  -- on page reclamation, the driver swaps the page with a spare page.
30  *     if that page is still in use, it frees its reference to that page,
31  *     and allocates a new page for use. otherwise, it just recycles the
32  *     the page.
33  *
34  * NOTE: cassini can parse the header. however, it's not worth it
35  *       as long as the network stack requires a header copy.
36  *
37  * TX has 4 queues. currently these queues are used in a round-robin
38  * fashion for load balancing. They can also be used for QoS. for that
39  * to work, however, QoS information needs to be exposed down to the driver
40  * level so that subqueues get targeted to particular transmit rings.
41  * alternatively, the queues can be configured via use of the all-purpose
42  * ioctl.
43  *
44  * RX DATA: the rx completion ring has all the info, but the rx desc
45  * ring has all of the data. RX can conceivably come in under multiple
46  * interrupts, but the INT# assignment needs to be set up properly by
47  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
48  * that. also, the two descriptor rings are designed to distinguish between
49  * encrypted and non-encrypted packets, but we use them for buffering
50  * instead.
51  *
52  * by default, the selective clear mask is set up to process rx packets.
53  */
54 
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 
57 #include <linux/module.h>
58 #include <linux/kernel.h>
59 #include <linux/types.h>
60 #include <linux/compiler.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/init.h>
64 #include <linux/interrupt.h>
65 #include <linux/vmalloc.h>
66 #include <linux/ioport.h>
67 #include <linux/pci.h>
68 #include <linux/mm.h>
69 #include <linux/highmem.h>
70 #include <linux/list.h>
71 #include <linux/dma-mapping.h>
72 
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/ethtool.h>
77 #include <linux/crc32.h>
78 #include <linux/random.h>
79 #include <linux/mii.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/mutex.h>
83 #include <linux/firmware.h>
84 
85 #include <net/checksum.h>
86 
87 #include <linux/atomic.h>
88 #include <asm/io.h>
89 #include <asm/byteorder.h>
90 #include <linux/uaccess.h>
91 
92 #define cas_page_map(x)      kmap_atomic((x))
93 #define cas_page_unmap(x)    kunmap_atomic((x))
94 #define CAS_NCPUS            num_online_cpus()
95 
96 #define cas_skb_release(x)  netif_rx(x)
97 
98 /* select which firmware to use */
99 #define USE_HP_WORKAROUND
100 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
101 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
102 
103 #include "cassini.h"
104 
105 #define USE_TX_COMPWB      /* use completion writeback registers */
106 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
107 #define USE_RX_BLANK       /* hw interrupt mitigation */
108 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
109 
110 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
111  * also, we need to make cp->lock finer-grained.
112  */
113 #undef  USE_PCI_INTB
114 #undef  USE_PCI_INTC
115 #undef  USE_PCI_INTD
116 #undef  USE_QOS
117 
118 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
119 
120 /* rx processing options */
121 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
122 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
123 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
124 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
125 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
126 
127 #define DRV_MODULE_NAME		"cassini"
128 #define DRV_MODULE_VERSION	"1.6"
129 #define DRV_MODULE_RELDATE	"21 May 2008"
130 
131 #define CAS_DEF_MSG_ENABLE	  \
132 	(NETIF_MSG_DRV		| \
133 	 NETIF_MSG_PROBE	| \
134 	 NETIF_MSG_LINK		| \
135 	 NETIF_MSG_TIMER	| \
136 	 NETIF_MSG_IFDOWN	| \
137 	 NETIF_MSG_IFUP		| \
138 	 NETIF_MSG_RX_ERR	| \
139 	 NETIF_MSG_TX_ERR)
140 
141 /* length of time before we decide the hardware is borked,
142  * and dev->tx_timeout() should be called to fix the problem
143  */
144 #define CAS_TX_TIMEOUT			(HZ)
145 #define CAS_LINK_TIMEOUT                (22*HZ/10)
146 #define CAS_LINK_FAST_TIMEOUT           (1)
147 
148 /* timeout values for state changing. these specify the number
149  * of 10us delays to be used before giving up.
150  */
151 #define STOP_TRIES_PHY 1000
152 #define STOP_TRIES     5000
153 
154 /* specify a minimum frame size to deal with some fifo issues
155  * max mtu == 2 * page size - ethernet header - 64 - swivel =
156  *            2 * page_size - 0x50
157  */
158 #define CAS_MIN_FRAME			97
159 #define CAS_1000MB_MIN_FRAME            255
160 #define CAS_MIN_MTU                     60
161 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
162 
163 #if 1
164 /*
165  * Eliminate these and use separate atomic counters for each, to
166  * avoid a race condition.
167  */
168 #else
169 #define CAS_RESET_MTU                   1
170 #define CAS_RESET_ALL                   2
171 #define CAS_RESET_SPARE                 3
172 #endif
173 
174 static char version[] =
175 	DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
176 
177 static int cassini_debug = -1;	/* -1 == use CAS_DEF_MSG_ENABLE as value */
178 static int link_mode;
179 
180 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
181 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
182 MODULE_LICENSE("GPL");
183 MODULE_FIRMWARE("sun/cassini.bin");
184 module_param(cassini_debug, int, 0);
185 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
186 module_param(link_mode, int, 0);
187 MODULE_PARM_DESC(link_mode, "default link mode");
188 
189 /*
190  * Work around for a PCS bug in which the link goes down due to the chip
191  * being confused and never showing a link status of "up."
192  */
193 #define DEFAULT_LINKDOWN_TIMEOUT 5
194 /*
195  * Value in seconds, for user input.
196  */
197 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
198 module_param(linkdown_timeout, int, 0);
199 MODULE_PARM_DESC(linkdown_timeout,
200 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
201 
202 /*
203  * value in 'ticks' (units used by jiffies). Set when we init the
204  * module because 'HZ' in actually a function call on some flavors of
205  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
206  */
207 static int link_transition_timeout;
208 
209 
210 
211 static u16 link_modes[] = {
212 	BMCR_ANENABLE,			 /* 0 : autoneg */
213 	0,				 /* 1 : 10bt half duplex */
214 	BMCR_SPEED100,			 /* 2 : 100bt half duplex */
215 	BMCR_FULLDPLX,			 /* 3 : 10bt full duplex */
216 	BMCR_SPEED100|BMCR_FULLDPLX,	 /* 4 : 100bt full duplex */
217 	CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
218 };
219 
220 static const struct pci_device_id cas_pci_tbl[] = {
221 	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
222 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
224 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 	{ 0, }
226 };
227 
228 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
229 
230 static void cas_set_link_modes(struct cas *cp);
231 
232 static inline void cas_lock_tx(struct cas *cp)
233 {
234 	int i;
235 
236 	for (i = 0; i < N_TX_RINGS; i++)
237 		spin_lock_nested(&cp->tx_lock[i], i);
238 }
239 
240 /* WTZ: QA was finding deadlock problems with the previous
241  * versions after long test runs with multiple cards per machine.
242  * See if replacing cas_lock_all with safer versions helps. The
243  * symptoms QA is reporting match those we'd expect if interrupts
244  * aren't being properly restored, and we fixed a previous deadlock
245  * with similar symptoms by using save/restore versions in other
246  * places.
247  */
248 #define cas_lock_all_save(cp, flags) \
249 do { \
250 	struct cas *xxxcp = (cp); \
251 	spin_lock_irqsave(&xxxcp->lock, flags); \
252 	cas_lock_tx(xxxcp); \
253 } while (0)
254 
255 static inline void cas_unlock_tx(struct cas *cp)
256 {
257 	int i;
258 
259 	for (i = N_TX_RINGS; i > 0; i--)
260 		spin_unlock(&cp->tx_lock[i - 1]);
261 }
262 
263 #define cas_unlock_all_restore(cp, flags) \
264 do { \
265 	struct cas *xxxcp = (cp); \
266 	cas_unlock_tx(xxxcp); \
267 	spin_unlock_irqrestore(&xxxcp->lock, flags); \
268 } while (0)
269 
270 static void cas_disable_irq(struct cas *cp, const int ring)
271 {
272 	/* Make sure we won't get any more interrupts */
273 	if (ring == 0) {
274 		writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
275 		return;
276 	}
277 
278 	/* disable completion interrupts and selectively mask */
279 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
280 		switch (ring) {
281 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
282 #ifdef USE_PCI_INTB
283 		case 1:
284 #endif
285 #ifdef USE_PCI_INTC
286 		case 2:
287 #endif
288 #ifdef USE_PCI_INTD
289 		case 3:
290 #endif
291 			writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
292 			       cp->regs + REG_PLUS_INTRN_MASK(ring));
293 			break;
294 #endif
295 		default:
296 			writel(INTRN_MASK_CLEAR_ALL, cp->regs +
297 			       REG_PLUS_INTRN_MASK(ring));
298 			break;
299 		}
300 	}
301 }
302 
303 static inline void cas_mask_intr(struct cas *cp)
304 {
305 	int i;
306 
307 	for (i = 0; i < N_RX_COMP_RINGS; i++)
308 		cas_disable_irq(cp, i);
309 }
310 
311 static void cas_enable_irq(struct cas *cp, const int ring)
312 {
313 	if (ring == 0) { /* all but TX_DONE */
314 		writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
315 		return;
316 	}
317 
318 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
319 		switch (ring) {
320 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
321 #ifdef USE_PCI_INTB
322 		case 1:
323 #endif
324 #ifdef USE_PCI_INTC
325 		case 2:
326 #endif
327 #ifdef USE_PCI_INTD
328 		case 3:
329 #endif
330 			writel(INTRN_MASK_RX_EN, cp->regs +
331 			       REG_PLUS_INTRN_MASK(ring));
332 			break;
333 #endif
334 		default:
335 			break;
336 		}
337 	}
338 }
339 
340 static inline void cas_unmask_intr(struct cas *cp)
341 {
342 	int i;
343 
344 	for (i = 0; i < N_RX_COMP_RINGS; i++)
345 		cas_enable_irq(cp, i);
346 }
347 
348 static inline void cas_entropy_gather(struct cas *cp)
349 {
350 #ifdef USE_ENTROPY_DEV
351 	if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
352 		return;
353 
354 	batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
355 			    readl(cp->regs + REG_ENTROPY_IV),
356 			    sizeof(uint64_t)*8);
357 #endif
358 }
359 
360 static inline void cas_entropy_reset(struct cas *cp)
361 {
362 #ifdef USE_ENTROPY_DEV
363 	if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
364 		return;
365 
366 	writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
367 	       cp->regs + REG_BIM_LOCAL_DEV_EN);
368 	writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
369 	writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
370 
371 	/* if we read back 0x0, we don't have an entropy device */
372 	if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
373 		cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
374 #endif
375 }
376 
377 /* access to the phy. the following assumes that we've initialized the MIF to
378  * be in frame rather than bit-bang mode
379  */
380 static u16 cas_phy_read(struct cas *cp, int reg)
381 {
382 	u32 cmd;
383 	int limit = STOP_TRIES_PHY;
384 
385 	cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
386 	cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
387 	cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
388 	cmd |= MIF_FRAME_TURN_AROUND_MSB;
389 	writel(cmd, cp->regs + REG_MIF_FRAME);
390 
391 	/* poll for completion */
392 	while (limit-- > 0) {
393 		udelay(10);
394 		cmd = readl(cp->regs + REG_MIF_FRAME);
395 		if (cmd & MIF_FRAME_TURN_AROUND_LSB)
396 			return cmd & MIF_FRAME_DATA_MASK;
397 	}
398 	return 0xFFFF; /* -1 */
399 }
400 
401 static int cas_phy_write(struct cas *cp, int reg, u16 val)
402 {
403 	int limit = STOP_TRIES_PHY;
404 	u32 cmd;
405 
406 	cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
407 	cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
408 	cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
409 	cmd |= MIF_FRAME_TURN_AROUND_MSB;
410 	cmd |= val & MIF_FRAME_DATA_MASK;
411 	writel(cmd, cp->regs + REG_MIF_FRAME);
412 
413 	/* poll for completion */
414 	while (limit-- > 0) {
415 		udelay(10);
416 		cmd = readl(cp->regs + REG_MIF_FRAME);
417 		if (cmd & MIF_FRAME_TURN_AROUND_LSB)
418 			return 0;
419 	}
420 	return -1;
421 }
422 
423 static void cas_phy_powerup(struct cas *cp)
424 {
425 	u16 ctl = cas_phy_read(cp, MII_BMCR);
426 
427 	if ((ctl & BMCR_PDOWN) == 0)
428 		return;
429 	ctl &= ~BMCR_PDOWN;
430 	cas_phy_write(cp, MII_BMCR, ctl);
431 }
432 
433 static void cas_phy_powerdown(struct cas *cp)
434 {
435 	u16 ctl = cas_phy_read(cp, MII_BMCR);
436 
437 	if (ctl & BMCR_PDOWN)
438 		return;
439 	ctl |= BMCR_PDOWN;
440 	cas_phy_write(cp, MII_BMCR, ctl);
441 }
442 
443 /* cp->lock held. note: the last put_page will free the buffer */
444 static int cas_page_free(struct cas *cp, cas_page_t *page)
445 {
446 	pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
447 		       PCI_DMA_FROMDEVICE);
448 	__free_pages(page->buffer, cp->page_order);
449 	kfree(page);
450 	return 0;
451 }
452 
453 #ifdef RX_COUNT_BUFFERS
454 #define RX_USED_ADD(x, y)       ((x)->used += (y))
455 #define RX_USED_SET(x, y)       ((x)->used  = (y))
456 #else
457 #define RX_USED_ADD(x, y)
458 #define RX_USED_SET(x, y)
459 #endif
460 
461 /* local page allocation routines for the receive buffers. jumbo pages
462  * require at least 8K contiguous and 8K aligned buffers.
463  */
464 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
465 {
466 	cas_page_t *page;
467 
468 	page = kmalloc(sizeof(cas_page_t), flags);
469 	if (!page)
470 		return NULL;
471 
472 	INIT_LIST_HEAD(&page->list);
473 	RX_USED_SET(page, 0);
474 	page->buffer = alloc_pages(flags, cp->page_order);
475 	if (!page->buffer)
476 		goto page_err;
477 	page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
478 				      cp->page_size, PCI_DMA_FROMDEVICE);
479 	return page;
480 
481 page_err:
482 	kfree(page);
483 	return NULL;
484 }
485 
486 /* initialize spare pool of rx buffers, but allocate during the open */
487 static void cas_spare_init(struct cas *cp)
488 {
489   	spin_lock(&cp->rx_inuse_lock);
490 	INIT_LIST_HEAD(&cp->rx_inuse_list);
491 	spin_unlock(&cp->rx_inuse_lock);
492 
493 	spin_lock(&cp->rx_spare_lock);
494 	INIT_LIST_HEAD(&cp->rx_spare_list);
495 	cp->rx_spares_needed = RX_SPARE_COUNT;
496 	spin_unlock(&cp->rx_spare_lock);
497 }
498 
499 /* used on close. free all the spare buffers. */
500 static void cas_spare_free(struct cas *cp)
501 {
502 	struct list_head list, *elem, *tmp;
503 
504 	/* free spare buffers */
505 	INIT_LIST_HEAD(&list);
506 	spin_lock(&cp->rx_spare_lock);
507 	list_splice_init(&cp->rx_spare_list, &list);
508 	spin_unlock(&cp->rx_spare_lock);
509 	list_for_each_safe(elem, tmp, &list) {
510 		cas_page_free(cp, list_entry(elem, cas_page_t, list));
511 	}
512 
513 	INIT_LIST_HEAD(&list);
514 #if 1
515 	/*
516 	 * Looks like Adrian had protected this with a different
517 	 * lock than used everywhere else to manipulate this list.
518 	 */
519 	spin_lock(&cp->rx_inuse_lock);
520 	list_splice_init(&cp->rx_inuse_list, &list);
521 	spin_unlock(&cp->rx_inuse_lock);
522 #else
523 	spin_lock(&cp->rx_spare_lock);
524 	list_splice_init(&cp->rx_inuse_list, &list);
525 	spin_unlock(&cp->rx_spare_lock);
526 #endif
527 	list_for_each_safe(elem, tmp, &list) {
528 		cas_page_free(cp, list_entry(elem, cas_page_t, list));
529 	}
530 }
531 
532 /* replenish spares if needed */
533 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
534 {
535 	struct list_head list, *elem, *tmp;
536 	int needed, i;
537 
538 	/* check inuse list. if we don't need any more free buffers,
539 	 * just free it
540 	 */
541 
542 	/* make a local copy of the list */
543 	INIT_LIST_HEAD(&list);
544 	spin_lock(&cp->rx_inuse_lock);
545 	list_splice_init(&cp->rx_inuse_list, &list);
546 	spin_unlock(&cp->rx_inuse_lock);
547 
548 	list_for_each_safe(elem, tmp, &list) {
549 		cas_page_t *page = list_entry(elem, cas_page_t, list);
550 
551 		/*
552 		 * With the lockless pagecache, cassini buffering scheme gets
553 		 * slightly less accurate: we might find that a page has an
554 		 * elevated reference count here, due to a speculative ref,
555 		 * and skip it as in-use. Ideally we would be able to reclaim
556 		 * it. However this would be such a rare case, it doesn't
557 		 * matter too much as we should pick it up the next time round.
558 		 *
559 		 * Importantly, if we find that the page has a refcount of 1
560 		 * here (our refcount), then we know it is definitely not inuse
561 		 * so we can reuse it.
562 		 */
563 		if (page_count(page->buffer) > 1)
564 			continue;
565 
566 		list_del(elem);
567 		spin_lock(&cp->rx_spare_lock);
568 		if (cp->rx_spares_needed > 0) {
569 			list_add(elem, &cp->rx_spare_list);
570 			cp->rx_spares_needed--;
571 			spin_unlock(&cp->rx_spare_lock);
572 		} else {
573 			spin_unlock(&cp->rx_spare_lock);
574 			cas_page_free(cp, page);
575 		}
576 	}
577 
578 	/* put any inuse buffers back on the list */
579 	if (!list_empty(&list)) {
580 		spin_lock(&cp->rx_inuse_lock);
581 		list_splice(&list, &cp->rx_inuse_list);
582 		spin_unlock(&cp->rx_inuse_lock);
583 	}
584 
585 	spin_lock(&cp->rx_spare_lock);
586 	needed = cp->rx_spares_needed;
587 	spin_unlock(&cp->rx_spare_lock);
588 	if (!needed)
589 		return;
590 
591 	/* we still need spares, so try to allocate some */
592 	INIT_LIST_HEAD(&list);
593 	i = 0;
594 	while (i < needed) {
595 		cas_page_t *spare = cas_page_alloc(cp, flags);
596 		if (!spare)
597 			break;
598 		list_add(&spare->list, &list);
599 		i++;
600 	}
601 
602 	spin_lock(&cp->rx_spare_lock);
603 	list_splice(&list, &cp->rx_spare_list);
604 	cp->rx_spares_needed -= i;
605 	spin_unlock(&cp->rx_spare_lock);
606 }
607 
608 /* pull a page from the list. */
609 static cas_page_t *cas_page_dequeue(struct cas *cp)
610 {
611 	struct list_head *entry;
612 	int recover;
613 
614 	spin_lock(&cp->rx_spare_lock);
615 	if (list_empty(&cp->rx_spare_list)) {
616 		/* try to do a quick recovery */
617 		spin_unlock(&cp->rx_spare_lock);
618 		cas_spare_recover(cp, GFP_ATOMIC);
619 		spin_lock(&cp->rx_spare_lock);
620 		if (list_empty(&cp->rx_spare_list)) {
621 			netif_err(cp, rx_err, cp->dev,
622 				  "no spare buffers available\n");
623 			spin_unlock(&cp->rx_spare_lock);
624 			return NULL;
625 		}
626 	}
627 
628 	entry = cp->rx_spare_list.next;
629 	list_del(entry);
630 	recover = ++cp->rx_spares_needed;
631 	spin_unlock(&cp->rx_spare_lock);
632 
633 	/* trigger the timer to do the recovery */
634 	if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
635 #if 1
636 		atomic_inc(&cp->reset_task_pending);
637 		atomic_inc(&cp->reset_task_pending_spare);
638 		schedule_work(&cp->reset_task);
639 #else
640 		atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
641 		schedule_work(&cp->reset_task);
642 #endif
643 	}
644 	return list_entry(entry, cas_page_t, list);
645 }
646 
647 
648 static void cas_mif_poll(struct cas *cp, const int enable)
649 {
650 	u32 cfg;
651 
652 	cfg  = readl(cp->regs + REG_MIF_CFG);
653 	cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
654 
655 	if (cp->phy_type & CAS_PHY_MII_MDIO1)
656 		cfg |= MIF_CFG_PHY_SELECT;
657 
658 	/* poll and interrupt on link status change. */
659 	if (enable) {
660 		cfg |= MIF_CFG_POLL_EN;
661 		cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
662 		cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
663 	}
664 	writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
665 	       cp->regs + REG_MIF_MASK);
666 	writel(cfg, cp->regs + REG_MIF_CFG);
667 }
668 
669 /* Must be invoked under cp->lock */
670 static void cas_begin_auto_negotiation(struct cas *cp,
671 				       const struct ethtool_link_ksettings *ep)
672 {
673 	u16 ctl;
674 #if 1
675 	int lcntl;
676 	int changed = 0;
677 	int oldstate = cp->lstate;
678 	int link_was_not_down = !(oldstate == link_down);
679 #endif
680 	/* Setup link parameters */
681 	if (!ep)
682 		goto start_aneg;
683 	lcntl = cp->link_cntl;
684 	if (ep->base.autoneg == AUTONEG_ENABLE) {
685 		cp->link_cntl = BMCR_ANENABLE;
686 	} else {
687 		u32 speed = ep->base.speed;
688 		cp->link_cntl = 0;
689 		if (speed == SPEED_100)
690 			cp->link_cntl |= BMCR_SPEED100;
691 		else if (speed == SPEED_1000)
692 			cp->link_cntl |= CAS_BMCR_SPEED1000;
693 		if (ep->base.duplex == DUPLEX_FULL)
694 			cp->link_cntl |= BMCR_FULLDPLX;
695 	}
696 #if 1
697 	changed = (lcntl != cp->link_cntl);
698 #endif
699 start_aneg:
700 	if (cp->lstate == link_up) {
701 		netdev_info(cp->dev, "PCS link down\n");
702 	} else {
703 		if (changed) {
704 			netdev_info(cp->dev, "link configuration changed\n");
705 		}
706 	}
707 	cp->lstate = link_down;
708 	cp->link_transition = LINK_TRANSITION_LINK_DOWN;
709 	if (!cp->hw_running)
710 		return;
711 #if 1
712 	/*
713 	 * WTZ: If the old state was link_up, we turn off the carrier
714 	 * to replicate everything we do elsewhere on a link-down
715 	 * event when we were already in a link-up state..
716 	 */
717 	if (oldstate == link_up)
718 		netif_carrier_off(cp->dev);
719 	if (changed  && link_was_not_down) {
720 		/*
721 		 * WTZ: This branch will simply schedule a full reset after
722 		 * we explicitly changed link modes in an ioctl. See if this
723 		 * fixes the link-problems we were having for forced mode.
724 		 */
725 		atomic_inc(&cp->reset_task_pending);
726 		atomic_inc(&cp->reset_task_pending_all);
727 		schedule_work(&cp->reset_task);
728 		cp->timer_ticks = 0;
729 		mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
730 		return;
731 	}
732 #endif
733 	if (cp->phy_type & CAS_PHY_SERDES) {
734 		u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
735 
736 		if (cp->link_cntl & BMCR_ANENABLE) {
737 			val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
738 			cp->lstate = link_aneg;
739 		} else {
740 			if (cp->link_cntl & BMCR_FULLDPLX)
741 				val |= PCS_MII_CTRL_DUPLEX;
742 			val &= ~PCS_MII_AUTONEG_EN;
743 			cp->lstate = link_force_ok;
744 		}
745 		cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
746 		writel(val, cp->regs + REG_PCS_MII_CTRL);
747 
748 	} else {
749 		cas_mif_poll(cp, 0);
750 		ctl = cas_phy_read(cp, MII_BMCR);
751 		ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
752 			 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
753 		ctl |= cp->link_cntl;
754 		if (ctl & BMCR_ANENABLE) {
755 			ctl |= BMCR_ANRESTART;
756 			cp->lstate = link_aneg;
757 		} else {
758 			cp->lstate = link_force_ok;
759 		}
760 		cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
761 		cas_phy_write(cp, MII_BMCR, ctl);
762 		cas_mif_poll(cp, 1);
763 	}
764 
765 	cp->timer_ticks = 0;
766 	mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
767 }
768 
769 /* Must be invoked under cp->lock. */
770 static int cas_reset_mii_phy(struct cas *cp)
771 {
772 	int limit = STOP_TRIES_PHY;
773 	u16 val;
774 
775 	cas_phy_write(cp, MII_BMCR, BMCR_RESET);
776 	udelay(100);
777 	while (--limit) {
778 		val = cas_phy_read(cp, MII_BMCR);
779 		if ((val & BMCR_RESET) == 0)
780 			break;
781 		udelay(10);
782 	}
783 	return limit <= 0;
784 }
785 
786 static void cas_saturn_firmware_init(struct cas *cp)
787 {
788 	const struct firmware *fw;
789 	const char fw_name[] = "sun/cassini.bin";
790 	int err;
791 
792 	if (PHY_NS_DP83065 != cp->phy_id)
793 		return;
794 
795 	err = request_firmware(&fw, fw_name, &cp->pdev->dev);
796 	if (err) {
797 		pr_err("Failed to load firmware \"%s\"\n",
798 		       fw_name);
799 		return;
800 	}
801 	if (fw->size < 2) {
802 		pr_err("bogus length %zu in \"%s\"\n",
803 		       fw->size, fw_name);
804 		goto out;
805 	}
806 	cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
807 	cp->fw_size = fw->size - 2;
808 	cp->fw_data = vmalloc(cp->fw_size);
809 	if (!cp->fw_data)
810 		goto out;
811 	memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
812 out:
813 	release_firmware(fw);
814 }
815 
816 static void cas_saturn_firmware_load(struct cas *cp)
817 {
818 	int i;
819 
820 	if (!cp->fw_data)
821 		return;
822 
823 	cas_phy_powerdown(cp);
824 
825 	/* expanded memory access mode */
826 	cas_phy_write(cp, DP83065_MII_MEM, 0x0);
827 
828 	/* pointer configuration for new firmware */
829 	cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
830 	cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
831 	cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
832 	cas_phy_write(cp, DP83065_MII_REGD, 0x82);
833 	cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
834 	cas_phy_write(cp, DP83065_MII_REGD, 0x0);
835 	cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
836 	cas_phy_write(cp, DP83065_MII_REGD, 0x39);
837 
838 	/* download new firmware */
839 	cas_phy_write(cp, DP83065_MII_MEM, 0x1);
840 	cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
841 	for (i = 0; i < cp->fw_size; i++)
842 		cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
843 
844 	/* enable firmware */
845 	cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
846 	cas_phy_write(cp, DP83065_MII_REGD, 0x1);
847 }
848 
849 
850 /* phy initialization */
851 static void cas_phy_init(struct cas *cp)
852 {
853 	u16 val;
854 
855 	/* if we're in MII/GMII mode, set up phy */
856 	if (CAS_PHY_MII(cp->phy_type)) {
857 		writel(PCS_DATAPATH_MODE_MII,
858 		       cp->regs + REG_PCS_DATAPATH_MODE);
859 
860 		cas_mif_poll(cp, 0);
861 		cas_reset_mii_phy(cp); /* take out of isolate mode */
862 
863 		if (PHY_LUCENT_B0 == cp->phy_id) {
864 			/* workaround link up/down issue with lucent */
865 			cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
866 			cas_phy_write(cp, MII_BMCR, 0x00f1);
867 			cas_phy_write(cp, LUCENT_MII_REG, 0x0);
868 
869 		} else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
870 			/* workarounds for broadcom phy */
871 			cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
872 			cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
873 			cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
874 			cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
875 			cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
876 			cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
877 			cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
878 			cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
879 			cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
880 			cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
881 			cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
882 
883 		} else if (PHY_BROADCOM_5411 == cp->phy_id) {
884 			val = cas_phy_read(cp, BROADCOM_MII_REG4);
885 			val = cas_phy_read(cp, BROADCOM_MII_REG4);
886 			if (val & 0x0080) {
887 				/* link workaround */
888 				cas_phy_write(cp, BROADCOM_MII_REG4,
889 					      val & ~0x0080);
890 			}
891 
892 		} else if (cp->cas_flags & CAS_FLAG_SATURN) {
893 			writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
894 			       SATURN_PCFG_FSI : 0x0,
895 			       cp->regs + REG_SATURN_PCFG);
896 
897 			/* load firmware to address 10Mbps auto-negotiation
898 			 * issue. NOTE: this will need to be changed if the
899 			 * default firmware gets fixed.
900 			 */
901 			if (PHY_NS_DP83065 == cp->phy_id) {
902 				cas_saturn_firmware_load(cp);
903 			}
904 			cas_phy_powerup(cp);
905 		}
906 
907 		/* advertise capabilities */
908 		val = cas_phy_read(cp, MII_BMCR);
909 		val &= ~BMCR_ANENABLE;
910 		cas_phy_write(cp, MII_BMCR, val);
911 		udelay(10);
912 
913 		cas_phy_write(cp, MII_ADVERTISE,
914 			      cas_phy_read(cp, MII_ADVERTISE) |
915 			      (ADVERTISE_10HALF | ADVERTISE_10FULL |
916 			       ADVERTISE_100HALF | ADVERTISE_100FULL |
917 			       CAS_ADVERTISE_PAUSE |
918 			       CAS_ADVERTISE_ASYM_PAUSE));
919 
920 		if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
921 			/* make sure that we don't advertise half
922 			 * duplex to avoid a chip issue
923 			 */
924 			val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
925 			val &= ~CAS_ADVERTISE_1000HALF;
926 			val |= CAS_ADVERTISE_1000FULL;
927 			cas_phy_write(cp, CAS_MII_1000_CTRL, val);
928 		}
929 
930 	} else {
931 		/* reset pcs for serdes */
932 		u32 val;
933 		int limit;
934 
935 		writel(PCS_DATAPATH_MODE_SERDES,
936 		       cp->regs + REG_PCS_DATAPATH_MODE);
937 
938 		/* enable serdes pins on saturn */
939 		if (cp->cas_flags & CAS_FLAG_SATURN)
940 			writel(0, cp->regs + REG_SATURN_PCFG);
941 
942 		/* Reset PCS unit. */
943 		val = readl(cp->regs + REG_PCS_MII_CTRL);
944 		val |= PCS_MII_RESET;
945 		writel(val, cp->regs + REG_PCS_MII_CTRL);
946 
947 		limit = STOP_TRIES;
948 		while (--limit > 0) {
949 			udelay(10);
950 			if ((readl(cp->regs + REG_PCS_MII_CTRL) &
951 			     PCS_MII_RESET) == 0)
952 				break;
953 		}
954 		if (limit <= 0)
955 			netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
956 				    readl(cp->regs + REG_PCS_STATE_MACHINE));
957 
958 		/* Make sure PCS is disabled while changing advertisement
959 		 * configuration.
960 		 */
961 		writel(0x0, cp->regs + REG_PCS_CFG);
962 
963 		/* Advertise all capabilities except half-duplex. */
964 		val  = readl(cp->regs + REG_PCS_MII_ADVERT);
965 		val &= ~PCS_MII_ADVERT_HD;
966 		val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
967 			PCS_MII_ADVERT_ASYM_PAUSE);
968 		writel(val, cp->regs + REG_PCS_MII_ADVERT);
969 
970 		/* enable PCS */
971 		writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
972 
973 		/* pcs workaround: enable sync detect */
974 		writel(PCS_SERDES_CTRL_SYNCD_EN,
975 		       cp->regs + REG_PCS_SERDES_CTRL);
976 	}
977 }
978 
979 
980 static int cas_pcs_link_check(struct cas *cp)
981 {
982 	u32 stat, state_machine;
983 	int retval = 0;
984 
985 	/* The link status bit latches on zero, so you must
986 	 * read it twice in such a case to see a transition
987 	 * to the link being up.
988 	 */
989 	stat = readl(cp->regs + REG_PCS_MII_STATUS);
990 	if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
991 		stat = readl(cp->regs + REG_PCS_MII_STATUS);
992 
993 	/* The remote-fault indication is only valid
994 	 * when autoneg has completed.
995 	 */
996 	if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
997 		     PCS_MII_STATUS_REMOTE_FAULT)) ==
998 	    (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
999 		netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1000 
1001 	/* work around link detection issue by querying the PCS state
1002 	 * machine directly.
1003 	 */
1004 	state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1005 	if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1006 		stat &= ~PCS_MII_STATUS_LINK_STATUS;
1007 	} else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1008 		stat |= PCS_MII_STATUS_LINK_STATUS;
1009 	}
1010 
1011 	if (stat & PCS_MII_STATUS_LINK_STATUS) {
1012 		if (cp->lstate != link_up) {
1013 			if (cp->opened) {
1014 				cp->lstate = link_up;
1015 				cp->link_transition = LINK_TRANSITION_LINK_UP;
1016 
1017 				cas_set_link_modes(cp);
1018 				netif_carrier_on(cp->dev);
1019 			}
1020 		}
1021 	} else if (cp->lstate == link_up) {
1022 		cp->lstate = link_down;
1023 		if (link_transition_timeout != 0 &&
1024 		    cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1025 		    !cp->link_transition_jiffies_valid) {
1026 			/*
1027 			 * force a reset, as a workaround for the
1028 			 * link-failure problem. May want to move this to a
1029 			 * point a bit earlier in the sequence. If we had
1030 			 * generated a reset a short time ago, we'll wait for
1031 			 * the link timer to check the status until a
1032 			 * timer expires (link_transistion_jiffies_valid is
1033 			 * true when the timer is running.)  Instead of using
1034 			 * a system timer, we just do a check whenever the
1035 			 * link timer is running - this clears the flag after
1036 			 * a suitable delay.
1037 			 */
1038 			retval = 1;
1039 			cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1040 			cp->link_transition_jiffies = jiffies;
1041 			cp->link_transition_jiffies_valid = 1;
1042 		} else {
1043 			cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1044 		}
1045 		netif_carrier_off(cp->dev);
1046 		if (cp->opened)
1047 			netif_info(cp, link, cp->dev, "PCS link down\n");
1048 
1049 		/* Cassini only: if you force a mode, there can be
1050 		 * sync problems on link down. to fix that, the following
1051 		 * things need to be checked:
1052 		 * 1) read serialink state register
1053 		 * 2) read pcs status register to verify link down.
1054 		 * 3) if link down and serial link == 0x03, then you need
1055 		 *    to global reset the chip.
1056 		 */
1057 		if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1058 			/* should check to see if we're in a forced mode */
1059 			stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1060 			if (stat == 0x03)
1061 				return 1;
1062 		}
1063 	} else if (cp->lstate == link_down) {
1064 		if (link_transition_timeout != 0 &&
1065 		    cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1066 		    !cp->link_transition_jiffies_valid) {
1067 			/* force a reset, as a workaround for the
1068 			 * link-failure problem.  May want to move
1069 			 * this to a point a bit earlier in the
1070 			 * sequence.
1071 			 */
1072 			retval = 1;
1073 			cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1074 			cp->link_transition_jiffies = jiffies;
1075 			cp->link_transition_jiffies_valid = 1;
1076 		} else {
1077 			cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1078 		}
1079 	}
1080 
1081 	return retval;
1082 }
1083 
1084 static int cas_pcs_interrupt(struct net_device *dev,
1085 			     struct cas *cp, u32 status)
1086 {
1087 	u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1088 
1089 	if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1090 		return 0;
1091 	return cas_pcs_link_check(cp);
1092 }
1093 
1094 static int cas_txmac_interrupt(struct net_device *dev,
1095 			       struct cas *cp, u32 status)
1096 {
1097 	u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1098 
1099 	if (!txmac_stat)
1100 		return 0;
1101 
1102 	netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1103 		     "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1104 
1105 	/* Defer timer expiration is quite normal,
1106 	 * don't even log the event.
1107 	 */
1108 	if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1109 	    !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1110 		return 0;
1111 
1112 	spin_lock(&cp->stat_lock[0]);
1113 	if (txmac_stat & MAC_TX_UNDERRUN) {
1114 		netdev_err(dev, "TX MAC xmit underrun\n");
1115 		cp->net_stats[0].tx_fifo_errors++;
1116 	}
1117 
1118 	if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1119 		netdev_err(dev, "TX MAC max packet size error\n");
1120 		cp->net_stats[0].tx_errors++;
1121 	}
1122 
1123 	/* The rest are all cases of one of the 16-bit TX
1124 	 * counters expiring.
1125 	 */
1126 	if (txmac_stat & MAC_TX_COLL_NORMAL)
1127 		cp->net_stats[0].collisions += 0x10000;
1128 
1129 	if (txmac_stat & MAC_TX_COLL_EXCESS) {
1130 		cp->net_stats[0].tx_aborted_errors += 0x10000;
1131 		cp->net_stats[0].collisions += 0x10000;
1132 	}
1133 
1134 	if (txmac_stat & MAC_TX_COLL_LATE) {
1135 		cp->net_stats[0].tx_aborted_errors += 0x10000;
1136 		cp->net_stats[0].collisions += 0x10000;
1137 	}
1138 	spin_unlock(&cp->stat_lock[0]);
1139 
1140 	/* We do not keep track of MAC_TX_COLL_FIRST and
1141 	 * MAC_TX_PEAK_ATTEMPTS events.
1142 	 */
1143 	return 0;
1144 }
1145 
1146 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1147 {
1148 	cas_hp_inst_t *inst;
1149 	u32 val;
1150 	int i;
1151 
1152 	i = 0;
1153 	while ((inst = firmware) && inst->note) {
1154 		writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1155 
1156 		val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1157 		val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1158 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1159 
1160 		val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1161 		val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1162 		val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1163 		val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1164 		val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1165 		val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1166 		val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1167 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1168 
1169 		val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1170 		val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1171 		val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1172 		val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1173 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1174 		++firmware;
1175 		++i;
1176 	}
1177 }
1178 
1179 static void cas_init_rx_dma(struct cas *cp)
1180 {
1181 	u64 desc_dma = cp->block_dvma;
1182 	u32 val;
1183 	int i, size;
1184 
1185 	/* rx free descriptors */
1186 	val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1187 	val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1188 	val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1189 	if ((N_RX_DESC_RINGS > 1) &&
1190 	    (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1191 		val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1192 	writel(val, cp->regs + REG_RX_CFG);
1193 
1194 	val = (unsigned long) cp->init_rxds[0] -
1195 		(unsigned long) cp->init_block;
1196 	writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1197 	writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1198 	writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1199 
1200 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1201 		/* rx desc 2 is for IPSEC packets. however,
1202 		 * we don't it that for that purpose.
1203 		 */
1204 		val = (unsigned long) cp->init_rxds[1] -
1205 			(unsigned long) cp->init_block;
1206 		writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1207 		writel((desc_dma + val) & 0xffffffff, cp->regs +
1208 		       REG_PLUS_RX_DB1_LOW);
1209 		writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1210 		       REG_PLUS_RX_KICK1);
1211 	}
1212 
1213 	/* rx completion registers */
1214 	val = (unsigned long) cp->init_rxcs[0] -
1215 		(unsigned long) cp->init_block;
1216 	writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1217 	writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1218 
1219 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1220 		/* rx comp 2-4 */
1221 		for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1222 			val = (unsigned long) cp->init_rxcs[i] -
1223 				(unsigned long) cp->init_block;
1224 			writel((desc_dma + val) >> 32, cp->regs +
1225 			       REG_PLUS_RX_CBN_HI(i));
1226 			writel((desc_dma + val) & 0xffffffff, cp->regs +
1227 			       REG_PLUS_RX_CBN_LOW(i));
1228 		}
1229 	}
1230 
1231 	/* read selective clear regs to prevent spurious interrupts
1232 	 * on reset because complete == kick.
1233 	 * selective clear set up to prevent interrupts on resets
1234 	 */
1235 	readl(cp->regs + REG_INTR_STATUS_ALIAS);
1236 	writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1237 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1238 		for (i = 1; i < N_RX_COMP_RINGS; i++)
1239 			readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1240 
1241 		/* 2 is different from 3 and 4 */
1242 		if (N_RX_COMP_RINGS > 1)
1243 			writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1244 			       cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1245 
1246 		for (i = 2; i < N_RX_COMP_RINGS; i++)
1247 			writel(INTR_RX_DONE_ALT,
1248 			       cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1249 	}
1250 
1251 	/* set up pause thresholds */
1252 	val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1253 			cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1254 	val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1255 			cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1256 	writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1257 
1258 	/* zero out dma reassembly buffers */
1259 	for (i = 0; i < 64; i++) {
1260 		writel(i, cp->regs + REG_RX_TABLE_ADDR);
1261 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1262 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1263 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1264 	}
1265 
1266 	/* make sure address register is 0 for normal operation */
1267 	writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1268 	writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1269 
1270 	/* interrupt mitigation */
1271 #ifdef USE_RX_BLANK
1272 	val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1273 	val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1274 	writel(val, cp->regs + REG_RX_BLANK);
1275 #else
1276 	writel(0x0, cp->regs + REG_RX_BLANK);
1277 #endif
1278 
1279 	/* interrupt generation as a function of low water marks for
1280 	 * free desc and completion entries. these are used to trigger
1281 	 * housekeeping for rx descs. we don't use the free interrupt
1282 	 * as it's not very useful
1283 	 */
1284 	/* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1285 	val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1286 	writel(val, cp->regs + REG_RX_AE_THRESH);
1287 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1288 		val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1289 		writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1290 	}
1291 
1292 	/* Random early detect registers. useful for congestion avoidance.
1293 	 * this should be tunable.
1294 	 */
1295 	writel(0x0, cp->regs + REG_RX_RED);
1296 
1297 	/* receive page sizes. default == 2K (0x800) */
1298 	val = 0;
1299 	if (cp->page_size == 0x1000)
1300 		val = 0x1;
1301 	else if (cp->page_size == 0x2000)
1302 		val = 0x2;
1303 	else if (cp->page_size == 0x4000)
1304 		val = 0x3;
1305 
1306 	/* round mtu + offset. constrain to page size. */
1307 	size = cp->dev->mtu + 64;
1308 	if (size > cp->page_size)
1309 		size = cp->page_size;
1310 
1311 	if (size <= 0x400)
1312 		i = 0x0;
1313 	else if (size <= 0x800)
1314 		i = 0x1;
1315 	else if (size <= 0x1000)
1316 		i = 0x2;
1317 	else
1318 		i = 0x3;
1319 
1320 	cp->mtu_stride = 1 << (i + 10);
1321 	val  = CAS_BASE(RX_PAGE_SIZE, val);
1322 	val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1323 	val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1324 	val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1325 	writel(val, cp->regs + REG_RX_PAGE_SIZE);
1326 
1327 	/* enable the header parser if desired */
1328 	if (CAS_HP_FIRMWARE == cas_prog_null)
1329 		return;
1330 
1331 	val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1332 	val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1333 	val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1334 	writel(val, cp->regs + REG_HP_CFG);
1335 }
1336 
1337 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1338 {
1339 	memset(rxc, 0, sizeof(*rxc));
1340 	rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1341 }
1342 
1343 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1344  * flipping is protected by the fact that the chip will not
1345  * hand back the same page index while it's being processed.
1346  */
1347 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1348 {
1349 	cas_page_t *page = cp->rx_pages[1][index];
1350 	cas_page_t *new;
1351 
1352 	if (page_count(page->buffer) == 1)
1353 		return page;
1354 
1355 	new = cas_page_dequeue(cp);
1356 	if (new) {
1357 		spin_lock(&cp->rx_inuse_lock);
1358 		list_add(&page->list, &cp->rx_inuse_list);
1359 		spin_unlock(&cp->rx_inuse_lock);
1360 	}
1361 	return new;
1362 }
1363 
1364 /* this needs to be changed if we actually use the ENC RX DESC ring */
1365 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1366 				 const int index)
1367 {
1368 	cas_page_t **page0 = cp->rx_pages[0];
1369 	cas_page_t **page1 = cp->rx_pages[1];
1370 
1371 	/* swap if buffer is in use */
1372 	if (page_count(page0[index]->buffer) > 1) {
1373 		cas_page_t *new = cas_page_spare(cp, index);
1374 		if (new) {
1375 			page1[index] = page0[index];
1376 			page0[index] = new;
1377 		}
1378 	}
1379 	RX_USED_SET(page0[index], 0);
1380 	return page0[index];
1381 }
1382 
1383 static void cas_clean_rxds(struct cas *cp)
1384 {
1385 	/* only clean ring 0 as ring 1 is used for spare buffers */
1386         struct cas_rx_desc *rxd = cp->init_rxds[0];
1387 	int i, size;
1388 
1389 	/* release all rx flows */
1390 	for (i = 0; i < N_RX_FLOWS; i++) {
1391 		struct sk_buff *skb;
1392 		while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1393 			cas_skb_release(skb);
1394 		}
1395 	}
1396 
1397 	/* initialize descriptors */
1398 	size = RX_DESC_RINGN_SIZE(0);
1399 	for (i = 0; i < size; i++) {
1400 		cas_page_t *page = cas_page_swap(cp, 0, i);
1401 		rxd[i].buffer = cpu_to_le64(page->dma_addr);
1402 		rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1403 					    CAS_BASE(RX_INDEX_RING, 0));
1404 	}
1405 
1406 	cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1407 	cp->rx_last[0] = 0;
1408 	cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1409 }
1410 
1411 static void cas_clean_rxcs(struct cas *cp)
1412 {
1413 	int i, j;
1414 
1415 	/* take ownership of rx comp descriptors */
1416 	memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1417 	memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1418 	for (i = 0; i < N_RX_COMP_RINGS; i++) {
1419 		struct cas_rx_comp *rxc = cp->init_rxcs[i];
1420 		for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1421 			cas_rxc_init(rxc + j);
1422 		}
1423 	}
1424 }
1425 
1426 #if 0
1427 /* When we get a RX fifo overflow, the RX unit is probably hung
1428  * so we do the following.
1429  *
1430  * If any part of the reset goes wrong, we return 1 and that causes the
1431  * whole chip to be reset.
1432  */
1433 static int cas_rxmac_reset(struct cas *cp)
1434 {
1435 	struct net_device *dev = cp->dev;
1436 	int limit;
1437 	u32 val;
1438 
1439 	/* First, reset MAC RX. */
1440 	writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1441 	for (limit = 0; limit < STOP_TRIES; limit++) {
1442 		if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1443 			break;
1444 		udelay(10);
1445 	}
1446 	if (limit == STOP_TRIES) {
1447 		netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1448 		return 1;
1449 	}
1450 
1451 	/* Second, disable RX DMA. */
1452 	writel(0, cp->regs + REG_RX_CFG);
1453 	for (limit = 0; limit < STOP_TRIES; limit++) {
1454 		if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1455 			break;
1456 		udelay(10);
1457 	}
1458 	if (limit == STOP_TRIES) {
1459 		netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1460 		return 1;
1461 	}
1462 
1463 	mdelay(5);
1464 
1465 	/* Execute RX reset command. */
1466 	writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1467 	for (limit = 0; limit < STOP_TRIES; limit++) {
1468 		if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1469 			break;
1470 		udelay(10);
1471 	}
1472 	if (limit == STOP_TRIES) {
1473 		netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1474 		return 1;
1475 	}
1476 
1477 	/* reset driver rx state */
1478 	cas_clean_rxds(cp);
1479 	cas_clean_rxcs(cp);
1480 
1481 	/* Now, reprogram the rest of RX unit. */
1482 	cas_init_rx_dma(cp);
1483 
1484 	/* re-enable */
1485 	val = readl(cp->regs + REG_RX_CFG);
1486 	writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1487 	writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1488 	val = readl(cp->regs + REG_MAC_RX_CFG);
1489 	writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1490 	return 0;
1491 }
1492 #endif
1493 
1494 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1495 			       u32 status)
1496 {
1497 	u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1498 
1499 	if (!stat)
1500 		return 0;
1501 
1502 	netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1503 
1504 	/* these are all rollovers */
1505 	spin_lock(&cp->stat_lock[0]);
1506 	if (stat & MAC_RX_ALIGN_ERR)
1507 		cp->net_stats[0].rx_frame_errors += 0x10000;
1508 
1509 	if (stat & MAC_RX_CRC_ERR)
1510 		cp->net_stats[0].rx_crc_errors += 0x10000;
1511 
1512 	if (stat & MAC_RX_LEN_ERR)
1513 		cp->net_stats[0].rx_length_errors += 0x10000;
1514 
1515 	if (stat & MAC_RX_OVERFLOW) {
1516 		cp->net_stats[0].rx_over_errors++;
1517 		cp->net_stats[0].rx_fifo_errors++;
1518 	}
1519 
1520 	/* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1521 	 * events.
1522 	 */
1523 	spin_unlock(&cp->stat_lock[0]);
1524 	return 0;
1525 }
1526 
1527 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1528 			     u32 status)
1529 {
1530 	u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1531 
1532 	if (!stat)
1533 		return 0;
1534 
1535 	netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1536 		     "mac interrupt, stat: 0x%x\n", stat);
1537 
1538 	/* This interrupt is just for pause frame and pause
1539 	 * tracking.  It is useful for diagnostics and debug
1540 	 * but probably by default we will mask these events.
1541 	 */
1542 	if (stat & MAC_CTRL_PAUSE_STATE)
1543 		cp->pause_entered++;
1544 
1545 	if (stat & MAC_CTRL_PAUSE_RECEIVED)
1546 		cp->pause_last_time_recvd = (stat >> 16);
1547 
1548 	return 0;
1549 }
1550 
1551 
1552 /* Must be invoked under cp->lock. */
1553 static inline int cas_mdio_link_not_up(struct cas *cp)
1554 {
1555 	u16 val;
1556 
1557 	switch (cp->lstate) {
1558 	case link_force_ret:
1559 		netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1560 		cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1561 		cp->timer_ticks = 5;
1562 		cp->lstate = link_force_ok;
1563 		cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1564 		break;
1565 
1566 	case link_aneg:
1567 		val = cas_phy_read(cp, MII_BMCR);
1568 
1569 		/* Try forced modes. we try things in the following order:
1570 		 * 1000 full -> 100 full/half -> 10 half
1571 		 */
1572 		val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1573 		val |= BMCR_FULLDPLX;
1574 		val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1575 			CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1576 		cas_phy_write(cp, MII_BMCR, val);
1577 		cp->timer_ticks = 5;
1578 		cp->lstate = link_force_try;
1579 		cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1580 		break;
1581 
1582 	case link_force_try:
1583 		/* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1584 		val = cas_phy_read(cp, MII_BMCR);
1585 		cp->timer_ticks = 5;
1586 		if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1587 			val &= ~CAS_BMCR_SPEED1000;
1588 			val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1589 			cas_phy_write(cp, MII_BMCR, val);
1590 			break;
1591 		}
1592 
1593 		if (val & BMCR_SPEED100) {
1594 			if (val & BMCR_FULLDPLX) /* fd failed */
1595 				val &= ~BMCR_FULLDPLX;
1596 			else { /* 100Mbps failed */
1597 				val &= ~BMCR_SPEED100;
1598 			}
1599 			cas_phy_write(cp, MII_BMCR, val);
1600 			break;
1601 		}
1602 	default:
1603 		break;
1604 	}
1605 	return 0;
1606 }
1607 
1608 
1609 /* must be invoked with cp->lock held */
1610 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1611 {
1612 	int restart;
1613 
1614 	if (bmsr & BMSR_LSTATUS) {
1615 		/* Ok, here we got a link. If we had it due to a forced
1616 		 * fallback, and we were configured for autoneg, we
1617 		 * retry a short autoneg pass. If you know your hub is
1618 		 * broken, use ethtool ;)
1619 		 */
1620 		if ((cp->lstate == link_force_try) &&
1621 		    (cp->link_cntl & BMCR_ANENABLE)) {
1622 			cp->lstate = link_force_ret;
1623 			cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1624 			cas_mif_poll(cp, 0);
1625 			cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1626 			cp->timer_ticks = 5;
1627 			if (cp->opened)
1628 				netif_info(cp, link, cp->dev,
1629 					   "Got link after fallback, retrying autoneg once...\n");
1630 			cas_phy_write(cp, MII_BMCR,
1631 				      cp->link_fcntl | BMCR_ANENABLE |
1632 				      BMCR_ANRESTART);
1633 			cas_mif_poll(cp, 1);
1634 
1635 		} else if (cp->lstate != link_up) {
1636 			cp->lstate = link_up;
1637 			cp->link_transition = LINK_TRANSITION_LINK_UP;
1638 
1639 			if (cp->opened) {
1640 				cas_set_link_modes(cp);
1641 				netif_carrier_on(cp->dev);
1642 			}
1643 		}
1644 		return 0;
1645 	}
1646 
1647 	/* link not up. if the link was previously up, we restart the
1648 	 * whole process
1649 	 */
1650 	restart = 0;
1651 	if (cp->lstate == link_up) {
1652 		cp->lstate = link_down;
1653 		cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1654 
1655 		netif_carrier_off(cp->dev);
1656 		if (cp->opened)
1657 			netif_info(cp, link, cp->dev, "Link down\n");
1658 		restart = 1;
1659 
1660 	} else if (++cp->timer_ticks > 10)
1661 		cas_mdio_link_not_up(cp);
1662 
1663 	return restart;
1664 }
1665 
1666 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1667 			     u32 status)
1668 {
1669 	u32 stat = readl(cp->regs + REG_MIF_STATUS);
1670 	u16 bmsr;
1671 
1672 	/* check for a link change */
1673 	if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1674 		return 0;
1675 
1676 	bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1677 	return cas_mii_link_check(cp, bmsr);
1678 }
1679 
1680 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1681 			     u32 status)
1682 {
1683 	u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1684 
1685 	if (!stat)
1686 		return 0;
1687 
1688 	netdev_err(dev, "PCI error [%04x:%04x]",
1689 		   stat, readl(cp->regs + REG_BIM_DIAG));
1690 
1691 	/* cassini+ has this reserved */
1692 	if ((stat & PCI_ERR_BADACK) &&
1693 	    ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1694 		pr_cont(" <No ACK64# during ABS64 cycle>");
1695 
1696 	if (stat & PCI_ERR_DTRTO)
1697 		pr_cont(" <Delayed transaction timeout>");
1698 	if (stat & PCI_ERR_OTHER)
1699 		pr_cont(" <other>");
1700 	if (stat & PCI_ERR_BIM_DMA_WRITE)
1701 		pr_cont(" <BIM DMA 0 write req>");
1702 	if (stat & PCI_ERR_BIM_DMA_READ)
1703 		pr_cont(" <BIM DMA 0 read req>");
1704 	pr_cont("\n");
1705 
1706 	if (stat & PCI_ERR_OTHER) {
1707 		int pci_errs;
1708 
1709 		/* Interrogate PCI config space for the
1710 		 * true cause.
1711 		 */
1712 		pci_errs = pci_status_get_and_clear_errors(cp->pdev);
1713 
1714 		netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
1715 		if (pci_errs & PCI_STATUS_PARITY)
1716 			netdev_err(dev, "PCI parity error detected\n");
1717 		if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
1718 			netdev_err(dev, "PCI target abort\n");
1719 		if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
1720 			netdev_err(dev, "PCI master acks target abort\n");
1721 		if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
1722 			netdev_err(dev, "PCI master abort\n");
1723 		if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
1724 			netdev_err(dev, "PCI system error SERR#\n");
1725 		if (pci_errs & PCI_STATUS_DETECTED_PARITY)
1726 			netdev_err(dev, "PCI parity error\n");
1727 	}
1728 
1729 	/* For all PCI errors, we should reset the chip. */
1730 	return 1;
1731 }
1732 
1733 /* All non-normal interrupt conditions get serviced here.
1734  * Returns non-zero if we should just exit the interrupt
1735  * handler right now (ie. if we reset the card which invalidates
1736  * all of the other original irq status bits).
1737  */
1738 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1739 			    u32 status)
1740 {
1741 	if (status & INTR_RX_TAG_ERROR) {
1742 		/* corrupt RX tag framing */
1743 		netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1744 			     "corrupt rx tag framing\n");
1745 		spin_lock(&cp->stat_lock[0]);
1746 		cp->net_stats[0].rx_errors++;
1747 		spin_unlock(&cp->stat_lock[0]);
1748 		goto do_reset;
1749 	}
1750 
1751 	if (status & INTR_RX_LEN_MISMATCH) {
1752 		/* length mismatch. */
1753 		netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1754 			     "length mismatch for rx frame\n");
1755 		spin_lock(&cp->stat_lock[0]);
1756 		cp->net_stats[0].rx_errors++;
1757 		spin_unlock(&cp->stat_lock[0]);
1758 		goto do_reset;
1759 	}
1760 
1761 	if (status & INTR_PCS_STATUS) {
1762 		if (cas_pcs_interrupt(dev, cp, status))
1763 			goto do_reset;
1764 	}
1765 
1766 	if (status & INTR_TX_MAC_STATUS) {
1767 		if (cas_txmac_interrupt(dev, cp, status))
1768 			goto do_reset;
1769 	}
1770 
1771 	if (status & INTR_RX_MAC_STATUS) {
1772 		if (cas_rxmac_interrupt(dev, cp, status))
1773 			goto do_reset;
1774 	}
1775 
1776 	if (status & INTR_MAC_CTRL_STATUS) {
1777 		if (cas_mac_interrupt(dev, cp, status))
1778 			goto do_reset;
1779 	}
1780 
1781 	if (status & INTR_MIF_STATUS) {
1782 		if (cas_mif_interrupt(dev, cp, status))
1783 			goto do_reset;
1784 	}
1785 
1786 	if (status & INTR_PCI_ERROR_STATUS) {
1787 		if (cas_pci_interrupt(dev, cp, status))
1788 			goto do_reset;
1789 	}
1790 	return 0;
1791 
1792 do_reset:
1793 #if 1
1794 	atomic_inc(&cp->reset_task_pending);
1795 	atomic_inc(&cp->reset_task_pending_all);
1796 	netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1797 	schedule_work(&cp->reset_task);
1798 #else
1799 	atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1800 	netdev_err(dev, "reset called in cas_abnormal_irq\n");
1801 	schedule_work(&cp->reset_task);
1802 #endif
1803 	return 1;
1804 }
1805 
1806 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1807  *       determining whether to do a netif_stop/wakeup
1808  */
1809 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1810 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1811 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1812 				  const int len)
1813 {
1814 	unsigned long off = addr + len;
1815 
1816 	if (CAS_TABORT(cp) == 1)
1817 		return 0;
1818 	if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1819 		return 0;
1820 	return TX_TARGET_ABORT_LEN;
1821 }
1822 
1823 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1824 {
1825 	struct cas_tx_desc *txds;
1826 	struct sk_buff **skbs;
1827 	struct net_device *dev = cp->dev;
1828 	int entry, count;
1829 
1830 	spin_lock(&cp->tx_lock[ring]);
1831 	txds = cp->init_txds[ring];
1832 	skbs = cp->tx_skbs[ring];
1833 	entry = cp->tx_old[ring];
1834 
1835 	count = TX_BUFF_COUNT(ring, entry, limit);
1836 	while (entry != limit) {
1837 		struct sk_buff *skb = skbs[entry];
1838 		dma_addr_t daddr;
1839 		u32 dlen;
1840 		int frag;
1841 
1842 		if (!skb) {
1843 			/* this should never occur */
1844 			entry = TX_DESC_NEXT(ring, entry);
1845 			continue;
1846 		}
1847 
1848 		/* however, we might get only a partial skb release. */
1849 		count -= skb_shinfo(skb)->nr_frags +
1850 			+ cp->tx_tiny_use[ring][entry].nbufs + 1;
1851 		if (count < 0)
1852 			break;
1853 
1854 		netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1855 			     "tx[%d] done, slot %d\n", ring, entry);
1856 
1857 		skbs[entry] = NULL;
1858 		cp->tx_tiny_use[ring][entry].nbufs = 0;
1859 
1860 		for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1861 			struct cas_tx_desc *txd = txds + entry;
1862 
1863 			daddr = le64_to_cpu(txd->buffer);
1864 			dlen = CAS_VAL(TX_DESC_BUFLEN,
1865 				       le64_to_cpu(txd->control));
1866 			pci_unmap_page(cp->pdev, daddr, dlen,
1867 				       PCI_DMA_TODEVICE);
1868 			entry = TX_DESC_NEXT(ring, entry);
1869 
1870 			/* tiny buffer may follow */
1871 			if (cp->tx_tiny_use[ring][entry].used) {
1872 				cp->tx_tiny_use[ring][entry].used = 0;
1873 				entry = TX_DESC_NEXT(ring, entry);
1874 			}
1875 		}
1876 
1877 		spin_lock(&cp->stat_lock[ring]);
1878 		cp->net_stats[ring].tx_packets++;
1879 		cp->net_stats[ring].tx_bytes += skb->len;
1880 		spin_unlock(&cp->stat_lock[ring]);
1881 		dev_consume_skb_irq(skb);
1882 	}
1883 	cp->tx_old[ring] = entry;
1884 
1885 	/* this is wrong for multiple tx rings. the net device needs
1886 	 * multiple queues for this to do the right thing.  we wait
1887 	 * for 2*packets to be available when using tiny buffers
1888 	 */
1889 	if (netif_queue_stopped(dev) &&
1890 	    (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1891 		netif_wake_queue(dev);
1892 	spin_unlock(&cp->tx_lock[ring]);
1893 }
1894 
1895 static void cas_tx(struct net_device *dev, struct cas *cp,
1896 		   u32 status)
1897 {
1898         int limit, ring;
1899 #ifdef USE_TX_COMPWB
1900 	u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1901 #endif
1902 	netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1903 		     "tx interrupt, status: 0x%x, %llx\n",
1904 		     status, (unsigned long long)compwb);
1905 	/* process all the rings */
1906 	for (ring = 0; ring < N_TX_RINGS; ring++) {
1907 #ifdef USE_TX_COMPWB
1908 		/* use the completion writeback registers */
1909 		limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1910 			CAS_VAL(TX_COMPWB_LSB, compwb);
1911 		compwb = TX_COMPWB_NEXT(compwb);
1912 #else
1913 		limit = readl(cp->regs + REG_TX_COMPN(ring));
1914 #endif
1915 		if (cp->tx_old[ring] != limit)
1916 			cas_tx_ringN(cp, ring, limit);
1917 	}
1918 }
1919 
1920 
1921 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1922 			      int entry, const u64 *words,
1923 			      struct sk_buff **skbref)
1924 {
1925 	int dlen, hlen, len, i, alloclen;
1926 	int off, swivel = RX_SWIVEL_OFF_VAL;
1927 	struct cas_page *page;
1928 	struct sk_buff *skb;
1929 	void *addr, *crcaddr;
1930 	__sum16 csum;
1931 	char *p;
1932 
1933 	hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1934 	dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1935 	len  = hlen + dlen;
1936 
1937 	if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1938 		alloclen = len;
1939 	else
1940 		alloclen = max(hlen, RX_COPY_MIN);
1941 
1942 	skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1943 	if (skb == NULL)
1944 		return -1;
1945 
1946 	*skbref = skb;
1947 	skb_reserve(skb, swivel);
1948 
1949 	p = skb->data;
1950 	addr = crcaddr = NULL;
1951 	if (hlen) { /* always copy header pages */
1952 		i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1953 		page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1954 		off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1955 			swivel;
1956 
1957 		i = hlen;
1958 		if (!dlen) /* attach FCS */
1959 			i += cp->crc_size;
1960 		pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1961 				    PCI_DMA_FROMDEVICE);
1962 		addr = cas_page_map(page->buffer);
1963 		memcpy(p, addr + off, i);
1964 		pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1965 				    PCI_DMA_FROMDEVICE);
1966 		cas_page_unmap(addr);
1967 		RX_USED_ADD(page, 0x100);
1968 		p += hlen;
1969 		swivel = 0;
1970 	}
1971 
1972 
1973 	if (alloclen < (hlen + dlen)) {
1974 		skb_frag_t *frag = skb_shinfo(skb)->frags;
1975 
1976 		/* normal or jumbo packets. we use frags */
1977 		i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
1978 		page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1979 		off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
1980 
1981 		hlen = min(cp->page_size - off, dlen);
1982 		if (hlen < 0) {
1983 			netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1984 				     "rx page overflow: %d\n", hlen);
1985 			dev_kfree_skb_irq(skb);
1986 			return -1;
1987 		}
1988 		i = hlen;
1989 		if (i == dlen)  /* attach FCS */
1990 			i += cp->crc_size;
1991 		pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1992 				    PCI_DMA_FROMDEVICE);
1993 
1994 		/* make sure we always copy a header */
1995 		swivel = 0;
1996 		if (p == (char *) skb->data) { /* not split */
1997 			addr = cas_page_map(page->buffer);
1998 			memcpy(p, addr + off, RX_COPY_MIN);
1999 			pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2000 					PCI_DMA_FROMDEVICE);
2001 			cas_page_unmap(addr);
2002 			off += RX_COPY_MIN;
2003 			swivel = RX_COPY_MIN;
2004 			RX_USED_ADD(page, cp->mtu_stride);
2005 		} else {
2006 			RX_USED_ADD(page, hlen);
2007 		}
2008 		skb_put(skb, alloclen);
2009 
2010 		skb_shinfo(skb)->nr_frags++;
2011 		skb->data_len += hlen - swivel;
2012 		skb->truesize += hlen - swivel;
2013 		skb->len      += hlen - swivel;
2014 
2015 		__skb_frag_set_page(frag, page->buffer);
2016 		__skb_frag_ref(frag);
2017 		skb_frag_off_set(frag, off);
2018 		skb_frag_size_set(frag, hlen - swivel);
2019 
2020 		/* any more data? */
2021 		if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2022 			hlen = dlen;
2023 			off = 0;
2024 
2025 			i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2026 			page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2027 			pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2028 					    hlen + cp->crc_size,
2029 					    PCI_DMA_FROMDEVICE);
2030 			pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2031 					    hlen + cp->crc_size,
2032 					    PCI_DMA_FROMDEVICE);
2033 
2034 			skb_shinfo(skb)->nr_frags++;
2035 			skb->data_len += hlen;
2036 			skb->len      += hlen;
2037 			frag++;
2038 
2039 			__skb_frag_set_page(frag, page->buffer);
2040 			__skb_frag_ref(frag);
2041 			skb_frag_off_set(frag, 0);
2042 			skb_frag_size_set(frag, hlen);
2043 			RX_USED_ADD(page, hlen + cp->crc_size);
2044 		}
2045 
2046 		if (cp->crc_size) {
2047 			addr = cas_page_map(page->buffer);
2048 			crcaddr  = addr + off + hlen;
2049 		}
2050 
2051 	} else {
2052 		/* copying packet */
2053 		if (!dlen)
2054 			goto end_copy_pkt;
2055 
2056 		i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2057 		page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2058 		off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2059 		hlen = min(cp->page_size - off, dlen);
2060 		if (hlen < 0) {
2061 			netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2062 				     "rx page overflow: %d\n", hlen);
2063 			dev_kfree_skb_irq(skb);
2064 			return -1;
2065 		}
2066 		i = hlen;
2067 		if (i == dlen) /* attach FCS */
2068 			i += cp->crc_size;
2069 		pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2070 				    PCI_DMA_FROMDEVICE);
2071 		addr = cas_page_map(page->buffer);
2072 		memcpy(p, addr + off, i);
2073 		pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2074 				    PCI_DMA_FROMDEVICE);
2075 		cas_page_unmap(addr);
2076 		if (p == (char *) skb->data) /* not split */
2077 			RX_USED_ADD(page, cp->mtu_stride);
2078 		else
2079 			RX_USED_ADD(page, i);
2080 
2081 		/* any more data? */
2082 		if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2083 			p += hlen;
2084 			i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2085 			page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2086 			pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2087 					    dlen + cp->crc_size,
2088 					    PCI_DMA_FROMDEVICE);
2089 			addr = cas_page_map(page->buffer);
2090 			memcpy(p, addr, dlen + cp->crc_size);
2091 			pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2092 					    dlen + cp->crc_size,
2093 					    PCI_DMA_FROMDEVICE);
2094 			cas_page_unmap(addr);
2095 			RX_USED_ADD(page, dlen + cp->crc_size);
2096 		}
2097 end_copy_pkt:
2098 		if (cp->crc_size) {
2099 			addr    = NULL;
2100 			crcaddr = skb->data + alloclen;
2101 		}
2102 		skb_put(skb, alloclen);
2103 	}
2104 
2105 	csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2106 	if (cp->crc_size) {
2107 		/* checksum includes FCS. strip it out. */
2108 		csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2109 					      csum_unfold(csum)));
2110 		if (addr)
2111 			cas_page_unmap(addr);
2112 	}
2113 	skb->protocol = eth_type_trans(skb, cp->dev);
2114 	if (skb->protocol == htons(ETH_P_IP)) {
2115 		skb->csum = csum_unfold(~csum);
2116 		skb->ip_summed = CHECKSUM_COMPLETE;
2117 	} else
2118 		skb_checksum_none_assert(skb);
2119 	return len;
2120 }
2121 
2122 
2123 /* we can handle up to 64 rx flows at a time. we do the same thing
2124  * as nonreassm except that we batch up the buffers.
2125  * NOTE: we currently just treat each flow as a bunch of packets that
2126  *       we pass up. a better way would be to coalesce the packets
2127  *       into a jumbo packet. to do that, we need to do the following:
2128  *       1) the first packet will have a clean split between header and
2129  *          data. save both.
2130  *       2) each time the next flow packet comes in, extend the
2131  *          data length and merge the checksums.
2132  *       3) on flow release, fix up the header.
2133  *       4) make sure the higher layer doesn't care.
2134  * because packets get coalesced, we shouldn't run into fragment count
2135  * issues.
2136  */
2137 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2138 				   struct sk_buff *skb)
2139 {
2140 	int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2141 	struct sk_buff_head *flow = &cp->rx_flows[flowid];
2142 
2143 	/* this is protected at a higher layer, so no need to
2144 	 * do any additional locking here. stick the buffer
2145 	 * at the end.
2146 	 */
2147 	__skb_queue_tail(flow, skb);
2148 	if (words[0] & RX_COMP1_RELEASE_FLOW) {
2149 		while ((skb = __skb_dequeue(flow))) {
2150 			cas_skb_release(skb);
2151 		}
2152 	}
2153 }
2154 
2155 /* put rx descriptor back on ring. if a buffer is in use by a higher
2156  * layer, this will need to put in a replacement.
2157  */
2158 static void cas_post_page(struct cas *cp, const int ring, const int index)
2159 {
2160 	cas_page_t *new;
2161 	int entry;
2162 
2163 	entry = cp->rx_old[ring];
2164 
2165 	new = cas_page_swap(cp, ring, index);
2166 	cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2167 	cp->init_rxds[ring][entry].index  =
2168 		cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2169 			    CAS_BASE(RX_INDEX_RING, ring));
2170 
2171 	entry = RX_DESC_ENTRY(ring, entry + 1);
2172 	cp->rx_old[ring] = entry;
2173 
2174 	if (entry % 4)
2175 		return;
2176 
2177 	if (ring == 0)
2178 		writel(entry, cp->regs + REG_RX_KICK);
2179 	else if ((N_RX_DESC_RINGS > 1) &&
2180 		 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2181 		writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2182 }
2183 
2184 
2185 /* only when things are bad */
2186 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2187 {
2188 	unsigned int entry, last, count, released;
2189 	int cluster;
2190 	cas_page_t **page = cp->rx_pages[ring];
2191 
2192 	entry = cp->rx_old[ring];
2193 
2194 	netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2195 		     "rxd[%d] interrupt, done: %d\n", ring, entry);
2196 
2197 	cluster = -1;
2198 	count = entry & 0x3;
2199 	last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2200 	released = 0;
2201 	while (entry != last) {
2202 		/* make a new buffer if it's still in use */
2203 		if (page_count(page[entry]->buffer) > 1) {
2204 			cas_page_t *new = cas_page_dequeue(cp);
2205 			if (!new) {
2206 				/* let the timer know that we need to
2207 				 * do this again
2208 				 */
2209 				cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2210 				if (!timer_pending(&cp->link_timer))
2211 					mod_timer(&cp->link_timer, jiffies +
2212 						  CAS_LINK_FAST_TIMEOUT);
2213 				cp->rx_old[ring]  = entry;
2214 				cp->rx_last[ring] = num ? num - released : 0;
2215 				return -ENOMEM;
2216 			}
2217 			spin_lock(&cp->rx_inuse_lock);
2218 			list_add(&page[entry]->list, &cp->rx_inuse_list);
2219 			spin_unlock(&cp->rx_inuse_lock);
2220 			cp->init_rxds[ring][entry].buffer =
2221 				cpu_to_le64(new->dma_addr);
2222 			page[entry] = new;
2223 
2224 		}
2225 
2226 		if (++count == 4) {
2227 			cluster = entry;
2228 			count = 0;
2229 		}
2230 		released++;
2231 		entry = RX_DESC_ENTRY(ring, entry + 1);
2232 	}
2233 	cp->rx_old[ring] = entry;
2234 
2235 	if (cluster < 0)
2236 		return 0;
2237 
2238 	if (ring == 0)
2239 		writel(cluster, cp->regs + REG_RX_KICK);
2240 	else if ((N_RX_DESC_RINGS > 1) &&
2241 		 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2242 		writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2243 	return 0;
2244 }
2245 
2246 
2247 /* process a completion ring. packets are set up in three basic ways:
2248  * small packets: should be copied header + data in single buffer.
2249  * large packets: header and data in a single buffer.
2250  * split packets: header in a separate buffer from data.
2251  *                data may be in multiple pages. data may be > 256
2252  *                bytes but in a single page.
2253  *
2254  * NOTE: RX page posting is done in this routine as well. while there's
2255  *       the capability of using multiple RX completion rings, it isn't
2256  *       really worthwhile due to the fact that the page posting will
2257  *       force serialization on the single descriptor ring.
2258  */
2259 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2260 {
2261 	struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2262 	int entry, drops;
2263 	int npackets = 0;
2264 
2265 	netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2266 		     "rx[%d] interrupt, done: %d/%d\n",
2267 		     ring,
2268 		     readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2269 
2270 	entry = cp->rx_new[ring];
2271 	drops = 0;
2272 	while (1) {
2273 		struct cas_rx_comp *rxc = rxcs + entry;
2274 		struct sk_buff *uninitialized_var(skb);
2275 		int type, len;
2276 		u64 words[4];
2277 		int i, dring;
2278 
2279 		words[0] = le64_to_cpu(rxc->word1);
2280 		words[1] = le64_to_cpu(rxc->word2);
2281 		words[2] = le64_to_cpu(rxc->word3);
2282 		words[3] = le64_to_cpu(rxc->word4);
2283 
2284 		/* don't touch if still owned by hw */
2285 		type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2286 		if (type == 0)
2287 			break;
2288 
2289 		/* hw hasn't cleared the zero bit yet */
2290 		if (words[3] & RX_COMP4_ZERO) {
2291 			break;
2292 		}
2293 
2294 		/* get info on the packet */
2295 		if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2296 			spin_lock(&cp->stat_lock[ring]);
2297 			cp->net_stats[ring].rx_errors++;
2298 			if (words[3] & RX_COMP4_LEN_MISMATCH)
2299 				cp->net_stats[ring].rx_length_errors++;
2300 			if (words[3] & RX_COMP4_BAD)
2301 				cp->net_stats[ring].rx_crc_errors++;
2302 			spin_unlock(&cp->stat_lock[ring]);
2303 
2304 			/* We'll just return it to Cassini. */
2305 		drop_it:
2306 			spin_lock(&cp->stat_lock[ring]);
2307 			++cp->net_stats[ring].rx_dropped;
2308 			spin_unlock(&cp->stat_lock[ring]);
2309 			goto next;
2310 		}
2311 
2312 		len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2313 		if (len < 0) {
2314 			++drops;
2315 			goto drop_it;
2316 		}
2317 
2318 		/* see if it's a flow re-assembly or not. the driver
2319 		 * itself handles release back up.
2320 		 */
2321 		if (RX_DONT_BATCH || (type == 0x2)) {
2322 			/* non-reassm: these always get released */
2323 			cas_skb_release(skb);
2324 		} else {
2325 			cas_rx_flow_pkt(cp, words, skb);
2326 		}
2327 
2328 		spin_lock(&cp->stat_lock[ring]);
2329 		cp->net_stats[ring].rx_packets++;
2330 		cp->net_stats[ring].rx_bytes += len;
2331 		spin_unlock(&cp->stat_lock[ring]);
2332 
2333 	next:
2334 		npackets++;
2335 
2336 		/* should it be released? */
2337 		if (words[0] & RX_COMP1_RELEASE_HDR) {
2338 			i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2339 			dring = CAS_VAL(RX_INDEX_RING, i);
2340 			i = CAS_VAL(RX_INDEX_NUM, i);
2341 			cas_post_page(cp, dring, i);
2342 		}
2343 
2344 		if (words[0] & RX_COMP1_RELEASE_DATA) {
2345 			i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2346 			dring = CAS_VAL(RX_INDEX_RING, i);
2347 			i = CAS_VAL(RX_INDEX_NUM, i);
2348 			cas_post_page(cp, dring, i);
2349 		}
2350 
2351 		if (words[0] & RX_COMP1_RELEASE_NEXT) {
2352 			i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2353 			dring = CAS_VAL(RX_INDEX_RING, i);
2354 			i = CAS_VAL(RX_INDEX_NUM, i);
2355 			cas_post_page(cp, dring, i);
2356 		}
2357 
2358 		/* skip to the next entry */
2359 		entry = RX_COMP_ENTRY(ring, entry + 1 +
2360 				      CAS_VAL(RX_COMP1_SKIP, words[0]));
2361 #ifdef USE_NAPI
2362 		if (budget && (npackets >= budget))
2363 			break;
2364 #endif
2365 	}
2366 	cp->rx_new[ring] = entry;
2367 
2368 	if (drops)
2369 		netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2370 	return npackets;
2371 }
2372 
2373 
2374 /* put completion entries back on the ring */
2375 static void cas_post_rxcs_ringN(struct net_device *dev,
2376 				struct cas *cp, int ring)
2377 {
2378 	struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2379 	int last, entry;
2380 
2381 	last = cp->rx_cur[ring];
2382 	entry = cp->rx_new[ring];
2383 	netif_printk(cp, intr, KERN_DEBUG, dev,
2384 		     "rxc[%d] interrupt, done: %d/%d\n",
2385 		     ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2386 
2387 	/* zero and re-mark descriptors */
2388 	while (last != entry) {
2389 		cas_rxc_init(rxc + last);
2390 		last = RX_COMP_ENTRY(ring, last + 1);
2391 	}
2392 	cp->rx_cur[ring] = last;
2393 
2394 	if (ring == 0)
2395 		writel(last, cp->regs + REG_RX_COMP_TAIL);
2396 	else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2397 		writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2398 }
2399 
2400 
2401 
2402 /* cassini can use all four PCI interrupts for the completion ring.
2403  * rings 3 and 4 are identical
2404  */
2405 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2406 static inline void cas_handle_irqN(struct net_device *dev,
2407 				   struct cas *cp, const u32 status,
2408 				   const int ring)
2409 {
2410 	if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2411 		cas_post_rxcs_ringN(dev, cp, ring);
2412 }
2413 
2414 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2415 {
2416 	struct net_device *dev = dev_id;
2417 	struct cas *cp = netdev_priv(dev);
2418 	unsigned long flags;
2419 	int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2420 	u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2421 
2422 	/* check for shared irq */
2423 	if (status == 0)
2424 		return IRQ_NONE;
2425 
2426 	spin_lock_irqsave(&cp->lock, flags);
2427 	if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2428 #ifdef USE_NAPI
2429 		cas_mask_intr(cp);
2430 		napi_schedule(&cp->napi);
2431 #else
2432 		cas_rx_ringN(cp, ring, 0);
2433 #endif
2434 		status &= ~INTR_RX_DONE_ALT;
2435 	}
2436 
2437 	if (status)
2438 		cas_handle_irqN(dev, cp, status, ring);
2439 	spin_unlock_irqrestore(&cp->lock, flags);
2440 	return IRQ_HANDLED;
2441 }
2442 #endif
2443 
2444 #ifdef USE_PCI_INTB
2445 /* everything but rx packets */
2446 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2447 {
2448 	if (status & INTR_RX_BUF_UNAVAIL_1) {
2449 		/* Frame arrived, no free RX buffers available.
2450 		 * NOTE: we can get this on a link transition. */
2451 		cas_post_rxds_ringN(cp, 1, 0);
2452 		spin_lock(&cp->stat_lock[1]);
2453 		cp->net_stats[1].rx_dropped++;
2454 		spin_unlock(&cp->stat_lock[1]);
2455 	}
2456 
2457 	if (status & INTR_RX_BUF_AE_1)
2458 		cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2459 				    RX_AE_FREEN_VAL(1));
2460 
2461 	if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2462 		cas_post_rxcs_ringN(cp, 1);
2463 }
2464 
2465 /* ring 2 handles a few more events than 3 and 4 */
2466 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2467 {
2468 	struct net_device *dev = dev_id;
2469 	struct cas *cp = netdev_priv(dev);
2470 	unsigned long flags;
2471 	u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2472 
2473 	/* check for shared interrupt */
2474 	if (status == 0)
2475 		return IRQ_NONE;
2476 
2477 	spin_lock_irqsave(&cp->lock, flags);
2478 	if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2479 #ifdef USE_NAPI
2480 		cas_mask_intr(cp);
2481 		napi_schedule(&cp->napi);
2482 #else
2483 		cas_rx_ringN(cp, 1, 0);
2484 #endif
2485 		status &= ~INTR_RX_DONE_ALT;
2486 	}
2487 	if (status)
2488 		cas_handle_irq1(cp, status);
2489 	spin_unlock_irqrestore(&cp->lock, flags);
2490 	return IRQ_HANDLED;
2491 }
2492 #endif
2493 
2494 static inline void cas_handle_irq(struct net_device *dev,
2495 				  struct cas *cp, const u32 status)
2496 {
2497 	/* housekeeping interrupts */
2498 	if (status & INTR_ERROR_MASK)
2499 		cas_abnormal_irq(dev, cp, status);
2500 
2501 	if (status & INTR_RX_BUF_UNAVAIL) {
2502 		/* Frame arrived, no free RX buffers available.
2503 		 * NOTE: we can get this on a link transition.
2504 		 */
2505 		cas_post_rxds_ringN(cp, 0, 0);
2506 		spin_lock(&cp->stat_lock[0]);
2507 		cp->net_stats[0].rx_dropped++;
2508 		spin_unlock(&cp->stat_lock[0]);
2509 	} else if (status & INTR_RX_BUF_AE) {
2510 		cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2511 				    RX_AE_FREEN_VAL(0));
2512 	}
2513 
2514 	if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2515 		cas_post_rxcs_ringN(dev, cp, 0);
2516 }
2517 
2518 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2519 {
2520 	struct net_device *dev = dev_id;
2521 	struct cas *cp = netdev_priv(dev);
2522 	unsigned long flags;
2523 	u32 status = readl(cp->regs + REG_INTR_STATUS);
2524 
2525 	if (status == 0)
2526 		return IRQ_NONE;
2527 
2528 	spin_lock_irqsave(&cp->lock, flags);
2529 	if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2530 		cas_tx(dev, cp, status);
2531 		status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2532 	}
2533 
2534 	if (status & INTR_RX_DONE) {
2535 #ifdef USE_NAPI
2536 		cas_mask_intr(cp);
2537 		napi_schedule(&cp->napi);
2538 #else
2539 		cas_rx_ringN(cp, 0, 0);
2540 #endif
2541 		status &= ~INTR_RX_DONE;
2542 	}
2543 
2544 	if (status)
2545 		cas_handle_irq(dev, cp, status);
2546 	spin_unlock_irqrestore(&cp->lock, flags);
2547 	return IRQ_HANDLED;
2548 }
2549 
2550 
2551 #ifdef USE_NAPI
2552 static int cas_poll(struct napi_struct *napi, int budget)
2553 {
2554 	struct cas *cp = container_of(napi, struct cas, napi);
2555 	struct net_device *dev = cp->dev;
2556 	int i, enable_intr, credits;
2557 	u32 status = readl(cp->regs + REG_INTR_STATUS);
2558 	unsigned long flags;
2559 
2560 	spin_lock_irqsave(&cp->lock, flags);
2561 	cas_tx(dev, cp, status);
2562 	spin_unlock_irqrestore(&cp->lock, flags);
2563 
2564 	/* NAPI rx packets. we spread the credits across all of the
2565 	 * rxc rings
2566 	 *
2567 	 * to make sure we're fair with the work we loop through each
2568 	 * ring N_RX_COMP_RING times with a request of
2569 	 * budget / N_RX_COMP_RINGS
2570 	 */
2571 	enable_intr = 1;
2572 	credits = 0;
2573 	for (i = 0; i < N_RX_COMP_RINGS; i++) {
2574 		int j;
2575 		for (j = 0; j < N_RX_COMP_RINGS; j++) {
2576 			credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2577 			if (credits >= budget) {
2578 				enable_intr = 0;
2579 				goto rx_comp;
2580 			}
2581 		}
2582 	}
2583 
2584 rx_comp:
2585 	/* final rx completion */
2586 	spin_lock_irqsave(&cp->lock, flags);
2587 	if (status)
2588 		cas_handle_irq(dev, cp, status);
2589 
2590 #ifdef USE_PCI_INTB
2591 	if (N_RX_COMP_RINGS > 1) {
2592 		status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2593 		if (status)
2594 			cas_handle_irq1(dev, cp, status);
2595 	}
2596 #endif
2597 
2598 #ifdef USE_PCI_INTC
2599 	if (N_RX_COMP_RINGS > 2) {
2600 		status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2601 		if (status)
2602 			cas_handle_irqN(dev, cp, status, 2);
2603 	}
2604 #endif
2605 
2606 #ifdef USE_PCI_INTD
2607 	if (N_RX_COMP_RINGS > 3) {
2608 		status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2609 		if (status)
2610 			cas_handle_irqN(dev, cp, status, 3);
2611 	}
2612 #endif
2613 	spin_unlock_irqrestore(&cp->lock, flags);
2614 	if (enable_intr) {
2615 		napi_complete(napi);
2616 		cas_unmask_intr(cp);
2617 	}
2618 	return credits;
2619 }
2620 #endif
2621 
2622 #ifdef CONFIG_NET_POLL_CONTROLLER
2623 static void cas_netpoll(struct net_device *dev)
2624 {
2625 	struct cas *cp = netdev_priv(dev);
2626 
2627 	cas_disable_irq(cp, 0);
2628 	cas_interrupt(cp->pdev->irq, dev);
2629 	cas_enable_irq(cp, 0);
2630 
2631 #ifdef USE_PCI_INTB
2632 	if (N_RX_COMP_RINGS > 1) {
2633 		/* cas_interrupt1(); */
2634 	}
2635 #endif
2636 #ifdef USE_PCI_INTC
2637 	if (N_RX_COMP_RINGS > 2) {
2638 		/* cas_interruptN(); */
2639 	}
2640 #endif
2641 #ifdef USE_PCI_INTD
2642 	if (N_RX_COMP_RINGS > 3) {
2643 		/* cas_interruptN(); */
2644 	}
2645 #endif
2646 }
2647 #endif
2648 
2649 static void cas_tx_timeout(struct net_device *dev, unsigned int txqueue)
2650 {
2651 	struct cas *cp = netdev_priv(dev);
2652 
2653 	netdev_err(dev, "transmit timed out, resetting\n");
2654 	if (!cp->hw_running) {
2655 		netdev_err(dev, "hrm.. hw not running!\n");
2656 		return;
2657 	}
2658 
2659 	netdev_err(dev, "MIF_STATE[%08x]\n",
2660 		   readl(cp->regs + REG_MIF_STATE_MACHINE));
2661 
2662 	netdev_err(dev, "MAC_STATE[%08x]\n",
2663 		   readl(cp->regs + REG_MAC_STATE_MACHINE));
2664 
2665 	netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2666 		   readl(cp->regs + REG_TX_CFG),
2667 		   readl(cp->regs + REG_MAC_TX_STATUS),
2668 		   readl(cp->regs + REG_MAC_TX_CFG),
2669 		   readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2670 		   readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2671 		   readl(cp->regs + REG_TX_FIFO_READ_PTR),
2672 		   readl(cp->regs + REG_TX_SM_1),
2673 		   readl(cp->regs + REG_TX_SM_2));
2674 
2675 	netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2676 		   readl(cp->regs + REG_RX_CFG),
2677 		   readl(cp->regs + REG_MAC_RX_STATUS),
2678 		   readl(cp->regs + REG_MAC_RX_CFG));
2679 
2680 	netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2681 		   readl(cp->regs + REG_HP_STATE_MACHINE),
2682 		   readl(cp->regs + REG_HP_STATUS0),
2683 		   readl(cp->regs + REG_HP_STATUS1),
2684 		   readl(cp->regs + REG_HP_STATUS2));
2685 
2686 #if 1
2687 	atomic_inc(&cp->reset_task_pending);
2688 	atomic_inc(&cp->reset_task_pending_all);
2689 	schedule_work(&cp->reset_task);
2690 #else
2691 	atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2692 	schedule_work(&cp->reset_task);
2693 #endif
2694 }
2695 
2696 static inline int cas_intme(int ring, int entry)
2697 {
2698 	/* Algorithm: IRQ every 1/2 of descriptors. */
2699 	if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2700 		return 1;
2701 	return 0;
2702 }
2703 
2704 
2705 static void cas_write_txd(struct cas *cp, int ring, int entry,
2706 			  dma_addr_t mapping, int len, u64 ctrl, int last)
2707 {
2708 	struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2709 
2710 	ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2711 	if (cas_intme(ring, entry))
2712 		ctrl |= TX_DESC_INTME;
2713 	if (last)
2714 		ctrl |= TX_DESC_EOF;
2715 	txd->control = cpu_to_le64(ctrl);
2716 	txd->buffer = cpu_to_le64(mapping);
2717 }
2718 
2719 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2720 				const int entry)
2721 {
2722 	return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2723 }
2724 
2725 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2726 				     const int entry, const int tentry)
2727 {
2728 	cp->tx_tiny_use[ring][tentry].nbufs++;
2729 	cp->tx_tiny_use[ring][entry].used = 1;
2730 	return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2731 }
2732 
2733 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2734 				    struct sk_buff *skb)
2735 {
2736 	struct net_device *dev = cp->dev;
2737 	int entry, nr_frags, frag, tabort, tentry;
2738 	dma_addr_t mapping;
2739 	unsigned long flags;
2740 	u64 ctrl;
2741 	u32 len;
2742 
2743 	spin_lock_irqsave(&cp->tx_lock[ring], flags);
2744 
2745 	/* This is a hard error, log it. */
2746 	if (TX_BUFFS_AVAIL(cp, ring) <=
2747 	    CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2748 		netif_stop_queue(dev);
2749 		spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2750 		netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2751 		return 1;
2752 	}
2753 
2754 	ctrl = 0;
2755 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
2756 		const u64 csum_start_off = skb_checksum_start_offset(skb);
2757 		const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2758 
2759 		ctrl =  TX_DESC_CSUM_EN |
2760 			CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2761 			CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2762 	}
2763 
2764 	entry = cp->tx_new[ring];
2765 	cp->tx_skbs[ring][entry] = skb;
2766 
2767 	nr_frags = skb_shinfo(skb)->nr_frags;
2768 	len = skb_headlen(skb);
2769 	mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2770 			       offset_in_page(skb->data), len,
2771 			       PCI_DMA_TODEVICE);
2772 
2773 	tentry = entry;
2774 	tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2775 	if (unlikely(tabort)) {
2776 		/* NOTE: len is always >  tabort */
2777 		cas_write_txd(cp, ring, entry, mapping, len - tabort,
2778 			      ctrl | TX_DESC_SOF, 0);
2779 		entry = TX_DESC_NEXT(ring, entry);
2780 
2781 		skb_copy_from_linear_data_offset(skb, len - tabort,
2782 			      tx_tiny_buf(cp, ring, entry), tabort);
2783 		mapping = tx_tiny_map(cp, ring, entry, tentry);
2784 		cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2785 			      (nr_frags == 0));
2786 	} else {
2787 		cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2788 			      TX_DESC_SOF, (nr_frags == 0));
2789 	}
2790 	entry = TX_DESC_NEXT(ring, entry);
2791 
2792 	for (frag = 0; frag < nr_frags; frag++) {
2793 		const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2794 
2795 		len = skb_frag_size(fragp);
2796 		mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2797 					   DMA_TO_DEVICE);
2798 
2799 		tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len);
2800 		if (unlikely(tabort)) {
2801 			void *addr;
2802 
2803 			/* NOTE: len is always > tabort */
2804 			cas_write_txd(cp, ring, entry, mapping, len - tabort,
2805 				      ctrl, 0);
2806 			entry = TX_DESC_NEXT(ring, entry);
2807 
2808 			addr = cas_page_map(skb_frag_page(fragp));
2809 			memcpy(tx_tiny_buf(cp, ring, entry),
2810 			       addr + skb_frag_off(fragp) + len - tabort,
2811 			       tabort);
2812 			cas_page_unmap(addr);
2813 			mapping = tx_tiny_map(cp, ring, entry, tentry);
2814 			len     = tabort;
2815 		}
2816 
2817 		cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2818 			      (frag + 1 == nr_frags));
2819 		entry = TX_DESC_NEXT(ring, entry);
2820 	}
2821 
2822 	cp->tx_new[ring] = entry;
2823 	if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2824 		netif_stop_queue(dev);
2825 
2826 	netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2827 		     "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2828 		     ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2829 	writel(entry, cp->regs + REG_TX_KICKN(ring));
2830 	spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2831 	return 0;
2832 }
2833 
2834 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2835 {
2836 	struct cas *cp = netdev_priv(dev);
2837 
2838 	/* this is only used as a load-balancing hint, so it doesn't
2839 	 * need to be SMP safe
2840 	 */
2841 	static int ring;
2842 
2843 	if (skb_padto(skb, cp->min_frame_size))
2844 		return NETDEV_TX_OK;
2845 
2846 	/* XXX: we need some higher-level QoS hooks to steer packets to
2847 	 *      individual queues.
2848 	 */
2849 	if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2850 		return NETDEV_TX_BUSY;
2851 	return NETDEV_TX_OK;
2852 }
2853 
2854 static void cas_init_tx_dma(struct cas *cp)
2855 {
2856 	u64 desc_dma = cp->block_dvma;
2857 	unsigned long off;
2858 	u32 val;
2859 	int i;
2860 
2861 	/* set up tx completion writeback registers. must be 8-byte aligned */
2862 #ifdef USE_TX_COMPWB
2863 	off = offsetof(struct cas_init_block, tx_compwb);
2864 	writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2865 	writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2866 #endif
2867 
2868 	/* enable completion writebacks, enable paced mode,
2869 	 * disable read pipe, and disable pre-interrupt compwbs
2870 	 */
2871 	val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2872 		TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2873 		TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2874 		TX_CFG_INTR_COMPWB_DIS;
2875 
2876 	/* write out tx ring info and tx desc bases */
2877 	for (i = 0; i < MAX_TX_RINGS; i++) {
2878 		off = (unsigned long) cp->init_txds[i] -
2879 			(unsigned long) cp->init_block;
2880 
2881 		val |= CAS_TX_RINGN_BASE(i);
2882 		writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2883 		writel((desc_dma + off) & 0xffffffff, cp->regs +
2884 		       REG_TX_DBN_LOW(i));
2885 		/* don't zero out the kick register here as the system
2886 		 * will wedge
2887 		 */
2888 	}
2889 	writel(val, cp->regs + REG_TX_CFG);
2890 
2891 	/* program max burst sizes. these numbers should be different
2892 	 * if doing QoS.
2893 	 */
2894 #ifdef USE_QOS
2895 	writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2896 	writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2897 	writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2898 	writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2899 #else
2900 	writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2901 	writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2902 	writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2903 	writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2904 #endif
2905 }
2906 
2907 /* Must be invoked under cp->lock. */
2908 static inline void cas_init_dma(struct cas *cp)
2909 {
2910 	cas_init_tx_dma(cp);
2911 	cas_init_rx_dma(cp);
2912 }
2913 
2914 static void cas_process_mc_list(struct cas *cp)
2915 {
2916 	u16 hash_table[16];
2917 	u32 crc;
2918 	struct netdev_hw_addr *ha;
2919 	int i = 1;
2920 
2921 	memset(hash_table, 0, sizeof(hash_table));
2922 	netdev_for_each_mc_addr(ha, cp->dev) {
2923 		if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2924 			/* use the alternate mac address registers for the
2925 			 * first 15 multicast addresses
2926 			 */
2927 			writel((ha->addr[4] << 8) | ha->addr[5],
2928 			       cp->regs + REG_MAC_ADDRN(i*3 + 0));
2929 			writel((ha->addr[2] << 8) | ha->addr[3],
2930 			       cp->regs + REG_MAC_ADDRN(i*3 + 1));
2931 			writel((ha->addr[0] << 8) | ha->addr[1],
2932 			       cp->regs + REG_MAC_ADDRN(i*3 + 2));
2933 			i++;
2934 		}
2935 		else {
2936 			/* use hw hash table for the next series of
2937 			 * multicast addresses
2938 			 */
2939 			crc = ether_crc_le(ETH_ALEN, ha->addr);
2940 			crc >>= 24;
2941 			hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2942 		}
2943 	}
2944 	for (i = 0; i < 16; i++)
2945 		writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2946 }
2947 
2948 /* Must be invoked under cp->lock. */
2949 static u32 cas_setup_multicast(struct cas *cp)
2950 {
2951 	u32 rxcfg = 0;
2952 	int i;
2953 
2954 	if (cp->dev->flags & IFF_PROMISC) {
2955 		rxcfg |= MAC_RX_CFG_PROMISC_EN;
2956 
2957 	} else if (cp->dev->flags & IFF_ALLMULTI) {
2958 	    	for (i=0; i < 16; i++)
2959 			writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2960 		rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2961 
2962 	} else {
2963 		cas_process_mc_list(cp);
2964 		rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2965 	}
2966 
2967 	return rxcfg;
2968 }
2969 
2970 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
2971 static void cas_clear_mac_err(struct cas *cp)
2972 {
2973 	writel(0, cp->regs + REG_MAC_COLL_NORMAL);
2974 	writel(0, cp->regs + REG_MAC_COLL_FIRST);
2975 	writel(0, cp->regs + REG_MAC_COLL_EXCESS);
2976 	writel(0, cp->regs + REG_MAC_COLL_LATE);
2977 	writel(0, cp->regs + REG_MAC_TIMER_DEFER);
2978 	writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
2979 	writel(0, cp->regs + REG_MAC_RECV_FRAME);
2980 	writel(0, cp->regs + REG_MAC_LEN_ERR);
2981 	writel(0, cp->regs + REG_MAC_ALIGN_ERR);
2982 	writel(0, cp->regs + REG_MAC_FCS_ERR);
2983 	writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
2984 }
2985 
2986 
2987 static void cas_mac_reset(struct cas *cp)
2988 {
2989 	int i;
2990 
2991 	/* do both TX and RX reset */
2992 	writel(0x1, cp->regs + REG_MAC_TX_RESET);
2993 	writel(0x1, cp->regs + REG_MAC_RX_RESET);
2994 
2995 	/* wait for TX */
2996 	i = STOP_TRIES;
2997 	while (i-- > 0) {
2998 		if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
2999 			break;
3000 		udelay(10);
3001 	}
3002 
3003 	/* wait for RX */
3004 	i = STOP_TRIES;
3005 	while (i-- > 0) {
3006 		if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3007 			break;
3008 		udelay(10);
3009 	}
3010 
3011 	if (readl(cp->regs + REG_MAC_TX_RESET) |
3012 	    readl(cp->regs + REG_MAC_RX_RESET))
3013 		netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3014 			   readl(cp->regs + REG_MAC_TX_RESET),
3015 			   readl(cp->regs + REG_MAC_RX_RESET),
3016 			   readl(cp->regs + REG_MAC_STATE_MACHINE));
3017 }
3018 
3019 
3020 /* Must be invoked under cp->lock. */
3021 static void cas_init_mac(struct cas *cp)
3022 {
3023 	unsigned char *e = &cp->dev->dev_addr[0];
3024 	int i;
3025 	cas_mac_reset(cp);
3026 
3027 	/* setup core arbitration weight register */
3028 	writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3029 
3030 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3031 	/* set the infinite burst register for chips that don't have
3032 	 * pci issues.
3033 	 */
3034 	if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3035 		writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3036 #endif
3037 
3038 	writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3039 
3040 	writel(0x00, cp->regs + REG_MAC_IPG0);
3041 	writel(0x08, cp->regs + REG_MAC_IPG1);
3042 	writel(0x04, cp->regs + REG_MAC_IPG2);
3043 
3044 	/* change later for 802.3z */
3045 	writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3046 
3047 	/* min frame + FCS */
3048 	writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3049 
3050 	/* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3051 	 * specify the maximum frame size to prevent RX tag errors on
3052 	 * oversized frames.
3053 	 */
3054 	writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3055 	       CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3056 			(CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3057 	       cp->regs + REG_MAC_FRAMESIZE_MAX);
3058 
3059 	/* NOTE: crc_size is used as a surrogate for half-duplex.
3060 	 * workaround saturn half-duplex issue by increasing preamble
3061 	 * size to 65 bytes.
3062 	 */
3063 	if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3064 		writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3065 	else
3066 		writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3067 	writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3068 	writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3069 	writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3070 
3071 	writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3072 
3073 	writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3074 	writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3075 	writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3076 	writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3077 	writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3078 
3079 	/* setup mac address in perfect filter array */
3080 	for (i = 0; i < 45; i++)
3081 		writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3082 
3083 	writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3084 	writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3085 	writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3086 
3087 	writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3088 	writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3089 	writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3090 
3091 	cp->mac_rx_cfg = cas_setup_multicast(cp);
3092 
3093 	spin_lock(&cp->stat_lock[N_TX_RINGS]);
3094 	cas_clear_mac_err(cp);
3095 	spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3096 
3097 	/* Setup MAC interrupts.  We want to get all of the interesting
3098 	 * counter expiration events, but we do not want to hear about
3099 	 * normal rx/tx as the DMA engine tells us that.
3100 	 */
3101 	writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3102 	writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3103 
3104 	/* Don't enable even the PAUSE interrupts for now, we
3105 	 * make no use of those events other than to record them.
3106 	 */
3107 	writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3108 }
3109 
3110 /* Must be invoked under cp->lock. */
3111 static void cas_init_pause_thresholds(struct cas *cp)
3112 {
3113 	/* Calculate pause thresholds.  Setting the OFF threshold to the
3114 	 * full RX fifo size effectively disables PAUSE generation
3115 	 */
3116 	if (cp->rx_fifo_size <= (2 * 1024)) {
3117 		cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3118 	} else {
3119 		int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3120 		if (max_frame * 3 > cp->rx_fifo_size) {
3121 			cp->rx_pause_off = 7104;
3122 			cp->rx_pause_on  = 960;
3123 		} else {
3124 			int off = (cp->rx_fifo_size - (max_frame * 2));
3125 			int on = off - max_frame;
3126 			cp->rx_pause_off = off;
3127 			cp->rx_pause_on = on;
3128 		}
3129 	}
3130 }
3131 
3132 static int cas_vpd_match(const void __iomem *p, const char *str)
3133 {
3134 	int len = strlen(str) + 1;
3135 	int i;
3136 
3137 	for (i = 0; i < len; i++) {
3138 		if (readb(p + i) != str[i])
3139 			return 0;
3140 	}
3141 	return 1;
3142 }
3143 
3144 
3145 /* get the mac address by reading the vpd information in the rom.
3146  * also get the phy type and determine if there's an entropy generator.
3147  * NOTE: this is a bit convoluted for the following reasons:
3148  *  1) vpd info has order-dependent mac addresses for multinic cards
3149  *  2) the only way to determine the nic order is to use the slot
3150  *     number.
3151  *  3) fiber cards don't have bridges, so their slot numbers don't
3152  *     mean anything.
3153  *  4) we don't actually know we have a fiber card until after
3154  *     the mac addresses are parsed.
3155  */
3156 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3157 			    const int offset)
3158 {
3159 	void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3160 	void __iomem *base, *kstart;
3161 	int i, len;
3162 	int found = 0;
3163 #define VPD_FOUND_MAC        0x01
3164 #define VPD_FOUND_PHY        0x02
3165 
3166 	int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3167 	int mac_off  = 0;
3168 
3169 #if defined(CONFIG_SPARC)
3170 	const unsigned char *addr;
3171 #endif
3172 
3173 	/* give us access to the PROM */
3174 	writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3175 	       cp->regs + REG_BIM_LOCAL_DEV_EN);
3176 
3177 	/* check for an expansion rom */
3178 	if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3179 		goto use_random_mac_addr;
3180 
3181 	/* search for beginning of vpd */
3182 	base = NULL;
3183 	for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3184 		/* check for PCIR */
3185 		if ((readb(p + i + 0) == 0x50) &&
3186 		    (readb(p + i + 1) == 0x43) &&
3187 		    (readb(p + i + 2) == 0x49) &&
3188 		    (readb(p + i + 3) == 0x52)) {
3189 			base = p + (readb(p + i + 8) |
3190 				    (readb(p + i + 9) << 8));
3191 			break;
3192 		}
3193 	}
3194 
3195 	if (!base || (readb(base) != 0x82))
3196 		goto use_random_mac_addr;
3197 
3198 	i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3199 	while (i < EXPANSION_ROM_SIZE) {
3200 		if (readb(base + i) != 0x90) /* no vpd found */
3201 			goto use_random_mac_addr;
3202 
3203 		/* found a vpd field */
3204 		len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3205 
3206 		/* extract keywords */
3207 		kstart = base + i + 3;
3208 		p = kstart;
3209 		while ((p - kstart) < len) {
3210 			int klen = readb(p + 2);
3211 			int j;
3212 			char type;
3213 
3214 			p += 3;
3215 
3216 			/* look for the following things:
3217 			 * -- correct length == 29
3218 			 * 3 (type) + 2 (size) +
3219 			 * 18 (strlen("local-mac-address") + 1) +
3220 			 * 6 (mac addr)
3221 			 * -- VPD Instance 'I'
3222 			 * -- VPD Type Bytes 'B'
3223 			 * -- VPD data length == 6
3224 			 * -- property string == local-mac-address
3225 			 *
3226 			 * -- correct length == 24
3227 			 * 3 (type) + 2 (size) +
3228 			 * 12 (strlen("entropy-dev") + 1) +
3229 			 * 7 (strlen("vms110") + 1)
3230 			 * -- VPD Instance 'I'
3231 			 * -- VPD Type String 'B'
3232 			 * -- VPD data length == 7
3233 			 * -- property string == entropy-dev
3234 			 *
3235 			 * -- correct length == 18
3236 			 * 3 (type) + 2 (size) +
3237 			 * 9 (strlen("phy-type") + 1) +
3238 			 * 4 (strlen("pcs") + 1)
3239 			 * -- VPD Instance 'I'
3240 			 * -- VPD Type String 'S'
3241 			 * -- VPD data length == 4
3242 			 * -- property string == phy-type
3243 			 *
3244 			 * -- correct length == 23
3245 			 * 3 (type) + 2 (size) +
3246 			 * 14 (strlen("phy-interface") + 1) +
3247 			 * 4 (strlen("pcs") + 1)
3248 			 * -- VPD Instance 'I'
3249 			 * -- VPD Type String 'S'
3250 			 * -- VPD data length == 4
3251 			 * -- property string == phy-interface
3252 			 */
3253 			if (readb(p) != 'I')
3254 				goto next;
3255 
3256 			/* finally, check string and length */
3257 			type = readb(p + 3);
3258 			if (type == 'B') {
3259 				if ((klen == 29) && readb(p + 4) == 6 &&
3260 				    cas_vpd_match(p + 5,
3261 						  "local-mac-address")) {
3262 					if (mac_off++ > offset)
3263 						goto next;
3264 
3265 					/* set mac address */
3266 					for (j = 0; j < 6; j++)
3267 						dev_addr[j] =
3268 							readb(p + 23 + j);
3269 					goto found_mac;
3270 				}
3271 			}
3272 
3273 			if (type != 'S')
3274 				goto next;
3275 
3276 #ifdef USE_ENTROPY_DEV
3277 			if ((klen == 24) &&
3278 			    cas_vpd_match(p + 5, "entropy-dev") &&
3279 			    cas_vpd_match(p + 17, "vms110")) {
3280 				cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3281 				goto next;
3282 			}
3283 #endif
3284 
3285 			if (found & VPD_FOUND_PHY)
3286 				goto next;
3287 
3288 			if ((klen == 18) && readb(p + 4) == 4 &&
3289 			    cas_vpd_match(p + 5, "phy-type")) {
3290 				if (cas_vpd_match(p + 14, "pcs")) {
3291 					phy_type = CAS_PHY_SERDES;
3292 					goto found_phy;
3293 				}
3294 			}
3295 
3296 			if ((klen == 23) && readb(p + 4) == 4 &&
3297 			    cas_vpd_match(p + 5, "phy-interface")) {
3298 				if (cas_vpd_match(p + 19, "pcs")) {
3299 					phy_type = CAS_PHY_SERDES;
3300 					goto found_phy;
3301 				}
3302 			}
3303 found_mac:
3304 			found |= VPD_FOUND_MAC;
3305 			goto next;
3306 
3307 found_phy:
3308 			found |= VPD_FOUND_PHY;
3309 
3310 next:
3311 			p += klen;
3312 		}
3313 		i += len + 3;
3314 	}
3315 
3316 use_random_mac_addr:
3317 	if (found & VPD_FOUND_MAC)
3318 		goto done;
3319 
3320 #if defined(CONFIG_SPARC)
3321 	addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3322 	if (addr != NULL) {
3323 		memcpy(dev_addr, addr, ETH_ALEN);
3324 		goto done;
3325 	}
3326 #endif
3327 
3328 	/* Sun MAC prefix then 3 random bytes. */
3329 	pr_info("MAC address not found in ROM VPD\n");
3330 	dev_addr[0] = 0x08;
3331 	dev_addr[1] = 0x00;
3332 	dev_addr[2] = 0x20;
3333 	get_random_bytes(dev_addr + 3, 3);
3334 
3335 done:
3336 	writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3337 	return phy_type;
3338 }
3339 
3340 /* check pci invariants */
3341 static void cas_check_pci_invariants(struct cas *cp)
3342 {
3343 	struct pci_dev *pdev = cp->pdev;
3344 
3345 	cp->cas_flags = 0;
3346 	if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3347 	    (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3348 		if (pdev->revision >= CAS_ID_REVPLUS)
3349 			cp->cas_flags |= CAS_FLAG_REG_PLUS;
3350 		if (pdev->revision < CAS_ID_REVPLUS02u)
3351 			cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3352 
3353 		/* Original Cassini supports HW CSUM, but it's not
3354 		 * enabled by default as it can trigger TX hangs.
3355 		 */
3356 		if (pdev->revision < CAS_ID_REV2)
3357 			cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3358 	} else {
3359 		/* Only sun has original cassini chips.  */
3360 		cp->cas_flags |= CAS_FLAG_REG_PLUS;
3361 
3362 		/* We use a flag because the same phy might be externally
3363 		 * connected.
3364 		 */
3365 		if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3366 		    (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3367 			cp->cas_flags |= CAS_FLAG_SATURN;
3368 	}
3369 }
3370 
3371 
3372 static int cas_check_invariants(struct cas *cp)
3373 {
3374 	struct pci_dev *pdev = cp->pdev;
3375 	u32 cfg;
3376 	int i;
3377 
3378 	/* get page size for rx buffers. */
3379 	cp->page_order = 0;
3380 #ifdef USE_PAGE_ORDER
3381 	if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3382 		/* see if we can allocate larger pages */
3383 		struct page *page = alloc_pages(GFP_ATOMIC,
3384 						CAS_JUMBO_PAGE_SHIFT -
3385 						PAGE_SHIFT);
3386 		if (page) {
3387 			__free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3388 			cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3389 		} else {
3390 			printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3391 		}
3392 	}
3393 #endif
3394 	cp->page_size = (PAGE_SIZE << cp->page_order);
3395 
3396 	/* Fetch the FIFO configurations. */
3397 	cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3398 	cp->rx_fifo_size = RX_FIFO_SIZE;
3399 
3400 	/* finish phy determination. MDIO1 takes precedence over MDIO0 if
3401 	 * they're both connected.
3402 	 */
3403 	cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3404 					PCI_SLOT(pdev->devfn));
3405 	if (cp->phy_type & CAS_PHY_SERDES) {
3406 		cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3407 		return 0; /* no more checking needed */
3408 	}
3409 
3410 	/* MII */
3411 	cfg = readl(cp->regs + REG_MIF_CFG);
3412 	if (cfg & MIF_CFG_MDIO_1) {
3413 		cp->phy_type = CAS_PHY_MII_MDIO1;
3414 	} else if (cfg & MIF_CFG_MDIO_0) {
3415 		cp->phy_type = CAS_PHY_MII_MDIO0;
3416 	}
3417 
3418 	cas_mif_poll(cp, 0);
3419 	writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3420 
3421 	for (i = 0; i < 32; i++) {
3422 		u32 phy_id;
3423 		int j;
3424 
3425 		for (j = 0; j < 3; j++) {
3426 			cp->phy_addr = i;
3427 			phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3428 			phy_id |= cas_phy_read(cp, MII_PHYSID2);
3429 			if (phy_id && (phy_id != 0xFFFFFFFF)) {
3430 				cp->phy_id = phy_id;
3431 				goto done;
3432 			}
3433 		}
3434 	}
3435 	pr_err("MII phy did not respond [%08x]\n",
3436 	       readl(cp->regs + REG_MIF_STATE_MACHINE));
3437 	return -1;
3438 
3439 done:
3440 	/* see if we can do gigabit */
3441 	cfg = cas_phy_read(cp, MII_BMSR);
3442 	if ((cfg & CAS_BMSR_1000_EXTEND) &&
3443 	    cas_phy_read(cp, CAS_MII_1000_EXTEND))
3444 		cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3445 	return 0;
3446 }
3447 
3448 /* Must be invoked under cp->lock. */
3449 static inline void cas_start_dma(struct cas *cp)
3450 {
3451 	int i;
3452 	u32 val;
3453 	int txfailed = 0;
3454 
3455 	/* enable dma */
3456 	val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3457 	writel(val, cp->regs + REG_TX_CFG);
3458 	val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3459 	writel(val, cp->regs + REG_RX_CFG);
3460 
3461 	/* enable the mac */
3462 	val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3463 	writel(val, cp->regs + REG_MAC_TX_CFG);
3464 	val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3465 	writel(val, cp->regs + REG_MAC_RX_CFG);
3466 
3467 	i = STOP_TRIES;
3468 	while (i-- > 0) {
3469 		val = readl(cp->regs + REG_MAC_TX_CFG);
3470 		if ((val & MAC_TX_CFG_EN))
3471 			break;
3472 		udelay(10);
3473 	}
3474 	if (i < 0) txfailed = 1;
3475 	i = STOP_TRIES;
3476 	while (i-- > 0) {
3477 		val = readl(cp->regs + REG_MAC_RX_CFG);
3478 		if ((val & MAC_RX_CFG_EN)) {
3479 			if (txfailed) {
3480 				netdev_err(cp->dev,
3481 					   "enabling mac failed [tx:%08x:%08x]\n",
3482 					   readl(cp->regs + REG_MIF_STATE_MACHINE),
3483 					   readl(cp->regs + REG_MAC_STATE_MACHINE));
3484 			}
3485 			goto enable_rx_done;
3486 		}
3487 		udelay(10);
3488 	}
3489 	netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3490 		   (txfailed ? "tx,rx" : "rx"),
3491 		   readl(cp->regs + REG_MIF_STATE_MACHINE),
3492 		   readl(cp->regs + REG_MAC_STATE_MACHINE));
3493 
3494 enable_rx_done:
3495 	cas_unmask_intr(cp); /* enable interrupts */
3496 	writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3497 	writel(0, cp->regs + REG_RX_COMP_TAIL);
3498 
3499 	if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3500 		if (N_RX_DESC_RINGS > 1)
3501 			writel(RX_DESC_RINGN_SIZE(1) - 4,
3502 			       cp->regs + REG_PLUS_RX_KICK1);
3503 
3504 		for (i = 1; i < N_RX_COMP_RINGS; i++)
3505 			writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3506 	}
3507 }
3508 
3509 /* Must be invoked under cp->lock. */
3510 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3511 				   int *pause)
3512 {
3513 	u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3514 	*fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3515 	*pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3516 	if (val & PCS_MII_LPA_ASYM_PAUSE)
3517 		*pause |= 0x10;
3518 	*spd = 1000;
3519 }
3520 
3521 /* Must be invoked under cp->lock. */
3522 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3523 				   int *pause)
3524 {
3525 	u32 val;
3526 
3527 	*fd = 0;
3528 	*spd = 10;
3529 	*pause = 0;
3530 
3531 	/* use GMII registers */
3532 	val = cas_phy_read(cp, MII_LPA);
3533 	if (val & CAS_LPA_PAUSE)
3534 		*pause = 0x01;
3535 
3536 	if (val & CAS_LPA_ASYM_PAUSE)
3537 		*pause |= 0x10;
3538 
3539 	if (val & LPA_DUPLEX)
3540 		*fd = 1;
3541 	if (val & LPA_100)
3542 		*spd = 100;
3543 
3544 	if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3545 		val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3546 		if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3547 			*spd = 1000;
3548 		if (val & CAS_LPA_1000FULL)
3549 			*fd = 1;
3550 	}
3551 }
3552 
3553 /* A link-up condition has occurred, initialize and enable the
3554  * rest of the chip.
3555  *
3556  * Must be invoked under cp->lock.
3557  */
3558 static void cas_set_link_modes(struct cas *cp)
3559 {
3560 	u32 val;
3561 	int full_duplex, speed, pause;
3562 
3563 	full_duplex = 0;
3564 	speed = 10;
3565 	pause = 0;
3566 
3567 	if (CAS_PHY_MII(cp->phy_type)) {
3568 		cas_mif_poll(cp, 0);
3569 		val = cas_phy_read(cp, MII_BMCR);
3570 		if (val & BMCR_ANENABLE) {
3571 			cas_read_mii_link_mode(cp, &full_duplex, &speed,
3572 					       &pause);
3573 		} else {
3574 			if (val & BMCR_FULLDPLX)
3575 				full_duplex = 1;
3576 
3577 			if (val & BMCR_SPEED100)
3578 				speed = 100;
3579 			else if (val & CAS_BMCR_SPEED1000)
3580 				speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3581 					1000 : 100;
3582 		}
3583 		cas_mif_poll(cp, 1);
3584 
3585 	} else {
3586 		val = readl(cp->regs + REG_PCS_MII_CTRL);
3587 		cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3588 		if ((val & PCS_MII_AUTONEG_EN) == 0) {
3589 			if (val & PCS_MII_CTRL_DUPLEX)
3590 				full_duplex = 1;
3591 		}
3592 	}
3593 
3594 	netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3595 		   speed, full_duplex ? "full" : "half");
3596 
3597 	val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3598 	if (CAS_PHY_MII(cp->phy_type)) {
3599 		val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3600 		if (!full_duplex)
3601 			val |= MAC_XIF_DISABLE_ECHO;
3602 	}
3603 	if (full_duplex)
3604 		val |= MAC_XIF_FDPLX_LED;
3605 	if (speed == 1000)
3606 		val |= MAC_XIF_GMII_MODE;
3607 	writel(val, cp->regs + REG_MAC_XIF_CFG);
3608 
3609 	/* deal with carrier and collision detect. */
3610 	val = MAC_TX_CFG_IPG_EN;
3611 	if (full_duplex) {
3612 		val |= MAC_TX_CFG_IGNORE_CARRIER;
3613 		val |= MAC_TX_CFG_IGNORE_COLL;
3614 	} else {
3615 #ifndef USE_CSMA_CD_PROTO
3616 		val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3617 		val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3618 #endif
3619 	}
3620 	/* val now set up for REG_MAC_TX_CFG */
3621 
3622 	/* If gigabit and half-duplex, enable carrier extension
3623 	 * mode.  increase slot time to 512 bytes as well.
3624 	 * else, disable it and make sure slot time is 64 bytes.
3625 	 * also activate checksum bug workaround
3626 	 */
3627 	if ((speed == 1000) && !full_duplex) {
3628 		writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3629 		       cp->regs + REG_MAC_TX_CFG);
3630 
3631 		val = readl(cp->regs + REG_MAC_RX_CFG);
3632 		val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3633 		writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3634 		       cp->regs + REG_MAC_RX_CFG);
3635 
3636 		writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3637 
3638 		cp->crc_size = 4;
3639 		/* minimum size gigabit frame at half duplex */
3640 		cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3641 
3642 	} else {
3643 		writel(val, cp->regs + REG_MAC_TX_CFG);
3644 
3645 		/* checksum bug workaround. don't strip FCS when in
3646 		 * half-duplex mode
3647 		 */
3648 		val = readl(cp->regs + REG_MAC_RX_CFG);
3649 		if (full_duplex) {
3650 			val |= MAC_RX_CFG_STRIP_FCS;
3651 			cp->crc_size = 0;
3652 			cp->min_frame_size = CAS_MIN_MTU;
3653 		} else {
3654 			val &= ~MAC_RX_CFG_STRIP_FCS;
3655 			cp->crc_size = 4;
3656 			cp->min_frame_size = CAS_MIN_FRAME;
3657 		}
3658 		writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3659 		       cp->regs + REG_MAC_RX_CFG);
3660 		writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3661 	}
3662 
3663 	if (netif_msg_link(cp)) {
3664 		if (pause & 0x01) {
3665 			netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3666 				    cp->rx_fifo_size,
3667 				    cp->rx_pause_off,
3668 				    cp->rx_pause_on);
3669 		} else if (pause & 0x10) {
3670 			netdev_info(cp->dev, "TX pause enabled\n");
3671 		} else {
3672 			netdev_info(cp->dev, "Pause is disabled\n");
3673 		}
3674 	}
3675 
3676 	val = readl(cp->regs + REG_MAC_CTRL_CFG);
3677 	val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3678 	if (pause) { /* symmetric or asymmetric pause */
3679 		val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3680 		if (pause & 0x01) { /* symmetric pause */
3681 			val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3682 		}
3683 	}
3684 	writel(val, cp->regs + REG_MAC_CTRL_CFG);
3685 	cas_start_dma(cp);
3686 }
3687 
3688 /* Must be invoked under cp->lock. */
3689 static void cas_init_hw(struct cas *cp, int restart_link)
3690 {
3691 	if (restart_link)
3692 		cas_phy_init(cp);
3693 
3694 	cas_init_pause_thresholds(cp);
3695 	cas_init_mac(cp);
3696 	cas_init_dma(cp);
3697 
3698 	if (restart_link) {
3699 		/* Default aneg parameters */
3700 		cp->timer_ticks = 0;
3701 		cas_begin_auto_negotiation(cp, NULL);
3702 	} else if (cp->lstate == link_up) {
3703 		cas_set_link_modes(cp);
3704 		netif_carrier_on(cp->dev);
3705 	}
3706 }
3707 
3708 /* Must be invoked under cp->lock. on earlier cassini boards,
3709  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3710  * let it settle out, and then restore pci state.
3711  */
3712 static void cas_hard_reset(struct cas *cp)
3713 {
3714 	writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3715 	udelay(20);
3716 	pci_restore_state(cp->pdev);
3717 }
3718 
3719 
3720 static void cas_global_reset(struct cas *cp, int blkflag)
3721 {
3722 	int limit;
3723 
3724 	/* issue a global reset. don't use RSTOUT. */
3725 	if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3726 		/* For PCS, when the blkflag is set, we should set the
3727 		 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3728 		 * the last autonegotiation from being cleared.  We'll
3729 		 * need some special handling if the chip is set into a
3730 		 * loopback mode.
3731 		 */
3732 		writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3733 		       cp->regs + REG_SW_RESET);
3734 	} else {
3735 		writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3736 	}
3737 
3738 	/* need to wait at least 3ms before polling register */
3739 	mdelay(3);
3740 
3741 	limit = STOP_TRIES;
3742 	while (limit-- > 0) {
3743 		u32 val = readl(cp->regs + REG_SW_RESET);
3744 		if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3745 			goto done;
3746 		udelay(10);
3747 	}
3748 	netdev_err(cp->dev, "sw reset failed\n");
3749 
3750 done:
3751 	/* enable various BIM interrupts */
3752 	writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3753 	       BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3754 
3755 	/* clear out pci error status mask for handled errors.
3756 	 * we don't deal with DMA counter overflows as they happen
3757 	 * all the time.
3758 	 */
3759 	writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3760 			       PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3761 			       PCI_ERR_BIM_DMA_READ), cp->regs +
3762 	       REG_PCI_ERR_STATUS_MASK);
3763 
3764 	/* set up for MII by default to address mac rx reset timeout
3765 	 * issue
3766 	 */
3767 	writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3768 }
3769 
3770 static void cas_reset(struct cas *cp, int blkflag)
3771 {
3772 	u32 val;
3773 
3774 	cas_mask_intr(cp);
3775 	cas_global_reset(cp, blkflag);
3776 	cas_mac_reset(cp);
3777 	cas_entropy_reset(cp);
3778 
3779 	/* disable dma engines. */
3780 	val = readl(cp->regs + REG_TX_CFG);
3781 	val &= ~TX_CFG_DMA_EN;
3782 	writel(val, cp->regs + REG_TX_CFG);
3783 
3784 	val = readl(cp->regs + REG_RX_CFG);
3785 	val &= ~RX_CFG_DMA_EN;
3786 	writel(val, cp->regs + REG_RX_CFG);
3787 
3788 	/* program header parser */
3789 	if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3790 	    (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3791 		cas_load_firmware(cp, CAS_HP_FIRMWARE);
3792 	} else {
3793 		cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3794 	}
3795 
3796 	/* clear out error registers */
3797 	spin_lock(&cp->stat_lock[N_TX_RINGS]);
3798 	cas_clear_mac_err(cp);
3799 	spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3800 }
3801 
3802 /* Shut down the chip, must be called with pm_mutex held.  */
3803 static void cas_shutdown(struct cas *cp)
3804 {
3805 	unsigned long flags;
3806 
3807 	/* Make us not-running to avoid timers respawning */
3808 	cp->hw_running = 0;
3809 
3810 	del_timer_sync(&cp->link_timer);
3811 
3812 	/* Stop the reset task */
3813 #if 0
3814 	while (atomic_read(&cp->reset_task_pending_mtu) ||
3815 	       atomic_read(&cp->reset_task_pending_spare) ||
3816 	       atomic_read(&cp->reset_task_pending_all))
3817 		schedule();
3818 
3819 #else
3820 	while (atomic_read(&cp->reset_task_pending))
3821 		schedule();
3822 #endif
3823 	/* Actually stop the chip */
3824 	cas_lock_all_save(cp, flags);
3825 	cas_reset(cp, 0);
3826 	if (cp->cas_flags & CAS_FLAG_SATURN)
3827 		cas_phy_powerdown(cp);
3828 	cas_unlock_all_restore(cp, flags);
3829 }
3830 
3831 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3832 {
3833 	struct cas *cp = netdev_priv(dev);
3834 
3835 	dev->mtu = new_mtu;
3836 	if (!netif_running(dev) || !netif_device_present(dev))
3837 		return 0;
3838 
3839 	/* let the reset task handle it */
3840 #if 1
3841 	atomic_inc(&cp->reset_task_pending);
3842 	if ((cp->phy_type & CAS_PHY_SERDES)) {
3843 		atomic_inc(&cp->reset_task_pending_all);
3844 	} else {
3845 		atomic_inc(&cp->reset_task_pending_mtu);
3846 	}
3847 	schedule_work(&cp->reset_task);
3848 #else
3849 	atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3850 		   CAS_RESET_ALL : CAS_RESET_MTU);
3851 	pr_err("reset called in cas_change_mtu\n");
3852 	schedule_work(&cp->reset_task);
3853 #endif
3854 
3855 	flush_work(&cp->reset_task);
3856 	return 0;
3857 }
3858 
3859 static void cas_clean_txd(struct cas *cp, int ring)
3860 {
3861 	struct cas_tx_desc *txd = cp->init_txds[ring];
3862 	struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3863 	u64 daddr, dlen;
3864 	int i, size;
3865 
3866 	size = TX_DESC_RINGN_SIZE(ring);
3867 	for (i = 0; i < size; i++) {
3868 		int frag;
3869 
3870 		if (skbs[i] == NULL)
3871 			continue;
3872 
3873 		skb = skbs[i];
3874 		skbs[i] = NULL;
3875 
3876 		for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3877 			int ent = i & (size - 1);
3878 
3879 			/* first buffer is never a tiny buffer and so
3880 			 * needs to be unmapped.
3881 			 */
3882 			daddr = le64_to_cpu(txd[ent].buffer);
3883 			dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3884 					 le64_to_cpu(txd[ent].control));
3885 			pci_unmap_page(cp->pdev, daddr, dlen,
3886 				       PCI_DMA_TODEVICE);
3887 
3888 			if (frag != skb_shinfo(skb)->nr_frags) {
3889 				i++;
3890 
3891 				/* next buffer might by a tiny buffer.
3892 				 * skip past it.
3893 				 */
3894 				ent = i & (size - 1);
3895 				if (cp->tx_tiny_use[ring][ent].used)
3896 					i++;
3897 			}
3898 		}
3899 		dev_kfree_skb_any(skb);
3900 	}
3901 
3902 	/* zero out tiny buf usage */
3903 	memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3904 }
3905 
3906 /* freed on close */
3907 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3908 {
3909 	cas_page_t **page = cp->rx_pages[ring];
3910 	int i, size;
3911 
3912 	size = RX_DESC_RINGN_SIZE(ring);
3913 	for (i = 0; i < size; i++) {
3914 		if (page[i]) {
3915 			cas_page_free(cp, page[i]);
3916 			page[i] = NULL;
3917 		}
3918 	}
3919 }
3920 
3921 static void cas_free_rxds(struct cas *cp)
3922 {
3923 	int i;
3924 
3925 	for (i = 0; i < N_RX_DESC_RINGS; i++)
3926 		cas_free_rx_desc(cp, i);
3927 }
3928 
3929 /* Must be invoked under cp->lock. */
3930 static void cas_clean_rings(struct cas *cp)
3931 {
3932 	int i;
3933 
3934 	/* need to clean all tx rings */
3935 	memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3936 	memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3937 	for (i = 0; i < N_TX_RINGS; i++)
3938 		cas_clean_txd(cp, i);
3939 
3940 	/* zero out init block */
3941 	memset(cp->init_block, 0, sizeof(struct cas_init_block));
3942 	cas_clean_rxds(cp);
3943 	cas_clean_rxcs(cp);
3944 }
3945 
3946 /* allocated on open */
3947 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3948 {
3949 	cas_page_t **page = cp->rx_pages[ring];
3950 	int size, i = 0;
3951 
3952 	size = RX_DESC_RINGN_SIZE(ring);
3953 	for (i = 0; i < size; i++) {
3954 		if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3955 			return -1;
3956 	}
3957 	return 0;
3958 }
3959 
3960 static int cas_alloc_rxds(struct cas *cp)
3961 {
3962 	int i;
3963 
3964 	for (i = 0; i < N_RX_DESC_RINGS; i++) {
3965 		if (cas_alloc_rx_desc(cp, i) < 0) {
3966 			cas_free_rxds(cp);
3967 			return -1;
3968 		}
3969 	}
3970 	return 0;
3971 }
3972 
3973 static void cas_reset_task(struct work_struct *work)
3974 {
3975 	struct cas *cp = container_of(work, struct cas, reset_task);
3976 #if 0
3977 	int pending = atomic_read(&cp->reset_task_pending);
3978 #else
3979 	int pending_all = atomic_read(&cp->reset_task_pending_all);
3980 	int pending_spare = atomic_read(&cp->reset_task_pending_spare);
3981 	int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
3982 
3983 	if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
3984 		/* We can have more tasks scheduled than actually
3985 		 * needed.
3986 		 */
3987 		atomic_dec(&cp->reset_task_pending);
3988 		return;
3989 	}
3990 #endif
3991 	/* The link went down, we reset the ring, but keep
3992 	 * DMA stopped. Use this function for reset
3993 	 * on error as well.
3994 	 */
3995 	if (cp->hw_running) {
3996 		unsigned long flags;
3997 
3998 		/* Make sure we don't get interrupts or tx packets */
3999 		netif_device_detach(cp->dev);
4000 		cas_lock_all_save(cp, flags);
4001 
4002 		if (cp->opened) {
4003 			/* We call cas_spare_recover when we call cas_open.
4004 			 * but we do not initialize the lists cas_spare_recover
4005 			 * uses until cas_open is called.
4006 			 */
4007 			cas_spare_recover(cp, GFP_ATOMIC);
4008 		}
4009 #if 1
4010 		/* test => only pending_spare set */
4011 		if (!pending_all && !pending_mtu)
4012 			goto done;
4013 #else
4014 		if (pending == CAS_RESET_SPARE)
4015 			goto done;
4016 #endif
4017 		/* when pending == CAS_RESET_ALL, the following
4018 		 * call to cas_init_hw will restart auto negotiation.
4019 		 * Setting the second argument of cas_reset to
4020 		 * !(pending == CAS_RESET_ALL) will set this argument
4021 		 * to 1 (avoiding reinitializing the PHY for the normal
4022 		 * PCS case) when auto negotiation is not restarted.
4023 		 */
4024 #if 1
4025 		cas_reset(cp, !(pending_all > 0));
4026 		if (cp->opened)
4027 			cas_clean_rings(cp);
4028 		cas_init_hw(cp, (pending_all > 0));
4029 #else
4030 		cas_reset(cp, !(pending == CAS_RESET_ALL));
4031 		if (cp->opened)
4032 			cas_clean_rings(cp);
4033 		cas_init_hw(cp, pending == CAS_RESET_ALL);
4034 #endif
4035 
4036 done:
4037 		cas_unlock_all_restore(cp, flags);
4038 		netif_device_attach(cp->dev);
4039 	}
4040 #if 1
4041 	atomic_sub(pending_all, &cp->reset_task_pending_all);
4042 	atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4043 	atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4044 	atomic_dec(&cp->reset_task_pending);
4045 #else
4046 	atomic_set(&cp->reset_task_pending, 0);
4047 #endif
4048 }
4049 
4050 static void cas_link_timer(struct timer_list *t)
4051 {
4052 	struct cas *cp = from_timer(cp, t, link_timer);
4053 	int mask, pending = 0, reset = 0;
4054 	unsigned long flags;
4055 
4056 	if (link_transition_timeout != 0 &&
4057 	    cp->link_transition_jiffies_valid &&
4058 	    ((jiffies - cp->link_transition_jiffies) >
4059 	      (link_transition_timeout))) {
4060 		/* One-second counter so link-down workaround doesn't
4061 		 * cause resets to occur so fast as to fool the switch
4062 		 * into thinking the link is down.
4063 		 */
4064 		cp->link_transition_jiffies_valid = 0;
4065 	}
4066 
4067 	if (!cp->hw_running)
4068 		return;
4069 
4070 	spin_lock_irqsave(&cp->lock, flags);
4071 	cas_lock_tx(cp);
4072 	cas_entropy_gather(cp);
4073 
4074 	/* If the link task is still pending, we just
4075 	 * reschedule the link timer
4076 	 */
4077 #if 1
4078 	if (atomic_read(&cp->reset_task_pending_all) ||
4079 	    atomic_read(&cp->reset_task_pending_spare) ||
4080 	    atomic_read(&cp->reset_task_pending_mtu))
4081 		goto done;
4082 #else
4083 	if (atomic_read(&cp->reset_task_pending))
4084 		goto done;
4085 #endif
4086 
4087 	/* check for rx cleaning */
4088 	if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4089 		int i, rmask;
4090 
4091 		for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4092 			rmask = CAS_FLAG_RXD_POST(i);
4093 			if ((mask & rmask) == 0)
4094 				continue;
4095 
4096 			/* post_rxds will do a mod_timer */
4097 			if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4098 				pending = 1;
4099 				continue;
4100 			}
4101 			cp->cas_flags &= ~rmask;
4102 		}
4103 	}
4104 
4105 	if (CAS_PHY_MII(cp->phy_type)) {
4106 		u16 bmsr;
4107 		cas_mif_poll(cp, 0);
4108 		bmsr = cas_phy_read(cp, MII_BMSR);
4109 		/* WTZ: Solaris driver reads this twice, but that
4110 		 * may be due to the PCS case and the use of a
4111 		 * common implementation. Read it twice here to be
4112 		 * safe.
4113 		 */
4114 		bmsr = cas_phy_read(cp, MII_BMSR);
4115 		cas_mif_poll(cp, 1);
4116 		readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4117 		reset = cas_mii_link_check(cp, bmsr);
4118 	} else {
4119 		reset = cas_pcs_link_check(cp);
4120 	}
4121 
4122 	if (reset)
4123 		goto done;
4124 
4125 	/* check for tx state machine confusion */
4126 	if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4127 		u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4128 		u32 wptr, rptr;
4129 		int tlm  = CAS_VAL(MAC_SM_TLM, val);
4130 
4131 		if (((tlm == 0x5) || (tlm == 0x3)) &&
4132 		    (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4133 			netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4134 				     "tx err: MAC_STATE[%08x]\n", val);
4135 			reset = 1;
4136 			goto done;
4137 		}
4138 
4139 		val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4140 		wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4141 		rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4142 		if ((val == 0) && (wptr != rptr)) {
4143 			netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4144 				     "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4145 				     val, wptr, rptr);
4146 			reset = 1;
4147 		}
4148 
4149 		if (reset)
4150 			cas_hard_reset(cp);
4151 	}
4152 
4153 done:
4154 	if (reset) {
4155 #if 1
4156 		atomic_inc(&cp->reset_task_pending);
4157 		atomic_inc(&cp->reset_task_pending_all);
4158 		schedule_work(&cp->reset_task);
4159 #else
4160 		atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4161 		pr_err("reset called in cas_link_timer\n");
4162 		schedule_work(&cp->reset_task);
4163 #endif
4164 	}
4165 
4166 	if (!pending)
4167 		mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4168 	cas_unlock_tx(cp);
4169 	spin_unlock_irqrestore(&cp->lock, flags);
4170 }
4171 
4172 /* tiny buffers are used to avoid target abort issues with
4173  * older cassini's
4174  */
4175 static void cas_tx_tiny_free(struct cas *cp)
4176 {
4177 	struct pci_dev *pdev = cp->pdev;
4178 	int i;
4179 
4180 	for (i = 0; i < N_TX_RINGS; i++) {
4181 		if (!cp->tx_tiny_bufs[i])
4182 			continue;
4183 
4184 		pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4185 				    cp->tx_tiny_bufs[i],
4186 				    cp->tx_tiny_dvma[i]);
4187 		cp->tx_tiny_bufs[i] = NULL;
4188 	}
4189 }
4190 
4191 static int cas_tx_tiny_alloc(struct cas *cp)
4192 {
4193 	struct pci_dev *pdev = cp->pdev;
4194 	int i;
4195 
4196 	for (i = 0; i < N_TX_RINGS; i++) {
4197 		cp->tx_tiny_bufs[i] =
4198 			pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4199 					     &cp->tx_tiny_dvma[i]);
4200 		if (!cp->tx_tiny_bufs[i]) {
4201 			cas_tx_tiny_free(cp);
4202 			return -1;
4203 		}
4204 	}
4205 	return 0;
4206 }
4207 
4208 
4209 static int cas_open(struct net_device *dev)
4210 {
4211 	struct cas *cp = netdev_priv(dev);
4212 	int hw_was_up, err;
4213 	unsigned long flags;
4214 
4215 	mutex_lock(&cp->pm_mutex);
4216 
4217 	hw_was_up = cp->hw_running;
4218 
4219 	/* The power-management mutex protects the hw_running
4220 	 * etc. state so it is safe to do this bit without cp->lock
4221 	 */
4222 	if (!cp->hw_running) {
4223 		/* Reset the chip */
4224 		cas_lock_all_save(cp, flags);
4225 		/* We set the second arg to cas_reset to zero
4226 		 * because cas_init_hw below will have its second
4227 		 * argument set to non-zero, which will force
4228 		 * autonegotiation to start.
4229 		 */
4230 		cas_reset(cp, 0);
4231 		cp->hw_running = 1;
4232 		cas_unlock_all_restore(cp, flags);
4233 	}
4234 
4235 	err = -ENOMEM;
4236 	if (cas_tx_tiny_alloc(cp) < 0)
4237 		goto err_unlock;
4238 
4239 	/* alloc rx descriptors */
4240 	if (cas_alloc_rxds(cp) < 0)
4241 		goto err_tx_tiny;
4242 
4243 	/* allocate spares */
4244 	cas_spare_init(cp);
4245 	cas_spare_recover(cp, GFP_KERNEL);
4246 
4247 	/* We can now request the interrupt as we know it's masked
4248 	 * on the controller. cassini+ has up to 4 interrupts
4249 	 * that can be used, but you need to do explicit pci interrupt
4250 	 * mapping to expose them
4251 	 */
4252 	if (request_irq(cp->pdev->irq, cas_interrupt,
4253 			IRQF_SHARED, dev->name, (void *) dev)) {
4254 		netdev_err(cp->dev, "failed to request irq !\n");
4255 		err = -EAGAIN;
4256 		goto err_spare;
4257 	}
4258 
4259 #ifdef USE_NAPI
4260 	napi_enable(&cp->napi);
4261 #endif
4262 	/* init hw */
4263 	cas_lock_all_save(cp, flags);
4264 	cas_clean_rings(cp);
4265 	cas_init_hw(cp, !hw_was_up);
4266 	cp->opened = 1;
4267 	cas_unlock_all_restore(cp, flags);
4268 
4269 	netif_start_queue(dev);
4270 	mutex_unlock(&cp->pm_mutex);
4271 	return 0;
4272 
4273 err_spare:
4274 	cas_spare_free(cp);
4275 	cas_free_rxds(cp);
4276 err_tx_tiny:
4277 	cas_tx_tiny_free(cp);
4278 err_unlock:
4279 	mutex_unlock(&cp->pm_mutex);
4280 	return err;
4281 }
4282 
4283 static int cas_close(struct net_device *dev)
4284 {
4285 	unsigned long flags;
4286 	struct cas *cp = netdev_priv(dev);
4287 
4288 #ifdef USE_NAPI
4289 	napi_disable(&cp->napi);
4290 #endif
4291 	/* Make sure we don't get distracted by suspend/resume */
4292 	mutex_lock(&cp->pm_mutex);
4293 
4294 	netif_stop_queue(dev);
4295 
4296 	/* Stop traffic, mark us closed */
4297 	cas_lock_all_save(cp, flags);
4298 	cp->opened = 0;
4299 	cas_reset(cp, 0);
4300 	cas_phy_init(cp);
4301 	cas_begin_auto_negotiation(cp, NULL);
4302 	cas_clean_rings(cp);
4303 	cas_unlock_all_restore(cp, flags);
4304 
4305 	free_irq(cp->pdev->irq, (void *) dev);
4306 	cas_spare_free(cp);
4307 	cas_free_rxds(cp);
4308 	cas_tx_tiny_free(cp);
4309 	mutex_unlock(&cp->pm_mutex);
4310 	return 0;
4311 }
4312 
4313 static struct {
4314 	const char name[ETH_GSTRING_LEN];
4315 } ethtool_cassini_statnames[] = {
4316 	{"collisions"},
4317 	{"rx_bytes"},
4318 	{"rx_crc_errors"},
4319 	{"rx_dropped"},
4320 	{"rx_errors"},
4321 	{"rx_fifo_errors"},
4322 	{"rx_frame_errors"},
4323 	{"rx_length_errors"},
4324 	{"rx_over_errors"},
4325 	{"rx_packets"},
4326 	{"tx_aborted_errors"},
4327 	{"tx_bytes"},
4328 	{"tx_dropped"},
4329 	{"tx_errors"},
4330 	{"tx_fifo_errors"},
4331 	{"tx_packets"}
4332 };
4333 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4334 
4335 static struct {
4336 	const int offsets;	/* neg. values for 2nd arg to cas_read_phy */
4337 } ethtool_register_table[] = {
4338 	{-MII_BMSR},
4339 	{-MII_BMCR},
4340 	{REG_CAWR},
4341 	{REG_INF_BURST},
4342 	{REG_BIM_CFG},
4343 	{REG_RX_CFG},
4344 	{REG_HP_CFG},
4345 	{REG_MAC_TX_CFG},
4346 	{REG_MAC_RX_CFG},
4347 	{REG_MAC_CTRL_CFG},
4348 	{REG_MAC_XIF_CFG},
4349 	{REG_MIF_CFG},
4350 	{REG_PCS_CFG},
4351 	{REG_SATURN_PCFG},
4352 	{REG_PCS_MII_STATUS},
4353 	{REG_PCS_STATE_MACHINE},
4354 	{REG_MAC_COLL_EXCESS},
4355 	{REG_MAC_COLL_LATE}
4356 };
4357 #define CAS_REG_LEN 	ARRAY_SIZE(ethtool_register_table)
4358 #define CAS_MAX_REGS 	(sizeof (u32)*CAS_REG_LEN)
4359 
4360 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4361 {
4362 	u8 *p;
4363 	int i;
4364 	unsigned long flags;
4365 
4366 	spin_lock_irqsave(&cp->lock, flags);
4367 	for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4368 		u16 hval;
4369 		u32 val;
4370 		if (ethtool_register_table[i].offsets < 0) {
4371 			hval = cas_phy_read(cp,
4372 				    -ethtool_register_table[i].offsets);
4373 			val = hval;
4374 		} else {
4375 			val= readl(cp->regs+ethtool_register_table[i].offsets);
4376 		}
4377 		memcpy(p, (u8 *)&val, sizeof(u32));
4378 	}
4379 	spin_unlock_irqrestore(&cp->lock, flags);
4380 }
4381 
4382 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4383 {
4384 	struct cas *cp = netdev_priv(dev);
4385 	struct net_device_stats *stats = cp->net_stats;
4386 	unsigned long flags;
4387 	int i;
4388 	unsigned long tmp;
4389 
4390 	/* we collate all of the stats into net_stats[N_TX_RING] */
4391 	if (!cp->hw_running)
4392 		return stats + N_TX_RINGS;
4393 
4394 	/* collect outstanding stats */
4395 	/* WTZ: the Cassini spec gives these as 16 bit counters but
4396 	 * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4397 	 * in case the chip somehow puts any garbage in the other bits.
4398 	 * Also, counter usage didn't seem to mach what Adrian did
4399 	 * in the parts of the code that set these quantities. Made
4400 	 * that consistent.
4401 	 */
4402 	spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4403 	stats[N_TX_RINGS].rx_crc_errors +=
4404 	  readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4405 	stats[N_TX_RINGS].rx_frame_errors +=
4406 		readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4407 	stats[N_TX_RINGS].rx_length_errors +=
4408 		readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4409 #if 1
4410 	tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4411 		(readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4412 	stats[N_TX_RINGS].tx_aborted_errors += tmp;
4413 	stats[N_TX_RINGS].collisions +=
4414 	  tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4415 #else
4416 	stats[N_TX_RINGS].tx_aborted_errors +=
4417 		readl(cp->regs + REG_MAC_COLL_EXCESS);
4418 	stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4419 		readl(cp->regs + REG_MAC_COLL_LATE);
4420 #endif
4421 	cas_clear_mac_err(cp);
4422 
4423 	/* saved bits that are unique to ring 0 */
4424 	spin_lock(&cp->stat_lock[0]);
4425 	stats[N_TX_RINGS].collisions        += stats[0].collisions;
4426 	stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4427 	stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4428 	stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4429 	stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4430 	stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4431 	spin_unlock(&cp->stat_lock[0]);
4432 
4433 	for (i = 0; i < N_TX_RINGS; i++) {
4434 		spin_lock(&cp->stat_lock[i]);
4435 		stats[N_TX_RINGS].rx_length_errors +=
4436 			stats[i].rx_length_errors;
4437 		stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4438 		stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4439 		stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4440 		stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4441 		stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4442 		stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4443 		stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4444 		stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4445 		stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4446 		memset(stats + i, 0, sizeof(struct net_device_stats));
4447 		spin_unlock(&cp->stat_lock[i]);
4448 	}
4449 	spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4450 	return stats + N_TX_RINGS;
4451 }
4452 
4453 
4454 static void cas_set_multicast(struct net_device *dev)
4455 {
4456 	struct cas *cp = netdev_priv(dev);
4457 	u32 rxcfg, rxcfg_new;
4458 	unsigned long flags;
4459 	int limit = STOP_TRIES;
4460 
4461 	if (!cp->hw_running)
4462 		return;
4463 
4464 	spin_lock_irqsave(&cp->lock, flags);
4465 	rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4466 
4467 	/* disable RX MAC and wait for completion */
4468 	writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4469 	while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4470 		if (!limit--)
4471 			break;
4472 		udelay(10);
4473 	}
4474 
4475 	/* disable hash filter and wait for completion */
4476 	limit = STOP_TRIES;
4477 	rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4478 	writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4479 	while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4480 		if (!limit--)
4481 			break;
4482 		udelay(10);
4483 	}
4484 
4485 	/* program hash filters */
4486 	cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4487 	rxcfg |= rxcfg_new;
4488 	writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4489 	spin_unlock_irqrestore(&cp->lock, flags);
4490 }
4491 
4492 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4493 {
4494 	struct cas *cp = netdev_priv(dev);
4495 	strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4496 	strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4497 	strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4498 }
4499 
4500 static int cas_get_link_ksettings(struct net_device *dev,
4501 				  struct ethtool_link_ksettings *cmd)
4502 {
4503 	struct cas *cp = netdev_priv(dev);
4504 	u16 bmcr;
4505 	int full_duplex, speed, pause;
4506 	unsigned long flags;
4507 	enum link_state linkstate = link_up;
4508 	u32 supported, advertising;
4509 
4510 	advertising = 0;
4511 	supported = SUPPORTED_Autoneg;
4512 	if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4513 		supported |= SUPPORTED_1000baseT_Full;
4514 		advertising |= ADVERTISED_1000baseT_Full;
4515 	}
4516 
4517 	/* Record PHY settings if HW is on. */
4518 	spin_lock_irqsave(&cp->lock, flags);
4519 	bmcr = 0;
4520 	linkstate = cp->lstate;
4521 	if (CAS_PHY_MII(cp->phy_type)) {
4522 		cmd->base.port = PORT_MII;
4523 		cmd->base.phy_address = cp->phy_addr;
4524 		advertising |= ADVERTISED_TP | ADVERTISED_MII |
4525 			ADVERTISED_10baseT_Half |
4526 			ADVERTISED_10baseT_Full |
4527 			ADVERTISED_100baseT_Half |
4528 			ADVERTISED_100baseT_Full;
4529 
4530 		supported |=
4531 			(SUPPORTED_10baseT_Half |
4532 			 SUPPORTED_10baseT_Full |
4533 			 SUPPORTED_100baseT_Half |
4534 			 SUPPORTED_100baseT_Full |
4535 			 SUPPORTED_TP | SUPPORTED_MII);
4536 
4537 		if (cp->hw_running) {
4538 			cas_mif_poll(cp, 0);
4539 			bmcr = cas_phy_read(cp, MII_BMCR);
4540 			cas_read_mii_link_mode(cp, &full_duplex,
4541 					       &speed, &pause);
4542 			cas_mif_poll(cp, 1);
4543 		}
4544 
4545 	} else {
4546 		cmd->base.port = PORT_FIBRE;
4547 		cmd->base.phy_address = 0;
4548 		supported   |= SUPPORTED_FIBRE;
4549 		advertising |= ADVERTISED_FIBRE;
4550 
4551 		if (cp->hw_running) {
4552 			/* pcs uses the same bits as mii */
4553 			bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4554 			cas_read_pcs_link_mode(cp, &full_duplex,
4555 					       &speed, &pause);
4556 		}
4557 	}
4558 	spin_unlock_irqrestore(&cp->lock, flags);
4559 
4560 	if (bmcr & BMCR_ANENABLE) {
4561 		advertising |= ADVERTISED_Autoneg;
4562 		cmd->base.autoneg = AUTONEG_ENABLE;
4563 		cmd->base.speed =  ((speed == 10) ?
4564 					    SPEED_10 :
4565 					    ((speed == 1000) ?
4566 					     SPEED_1000 : SPEED_100));
4567 		cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4568 	} else {
4569 		cmd->base.autoneg = AUTONEG_DISABLE;
4570 		cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ?
4571 					    SPEED_1000 :
4572 					    ((bmcr & BMCR_SPEED100) ?
4573 					     SPEED_100 : SPEED_10));
4574 		cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ?
4575 			DUPLEX_FULL : DUPLEX_HALF;
4576 	}
4577 	if (linkstate != link_up) {
4578 		/* Force these to "unknown" if the link is not up and
4579 		 * autonogotiation in enabled. We can set the link
4580 		 * speed to 0, but not cmd->duplex,
4581 		 * because its legal values are 0 and 1.  Ethtool will
4582 		 * print the value reported in parentheses after the
4583 		 * word "Unknown" for unrecognized values.
4584 		 *
4585 		 * If in forced mode, we report the speed and duplex
4586 		 * settings that we configured.
4587 		 */
4588 		if (cp->link_cntl & BMCR_ANENABLE) {
4589 			cmd->base.speed = 0;
4590 			cmd->base.duplex = 0xff;
4591 		} else {
4592 			cmd->base.speed = SPEED_10;
4593 			if (cp->link_cntl & BMCR_SPEED100) {
4594 				cmd->base.speed = SPEED_100;
4595 			} else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4596 				cmd->base.speed = SPEED_1000;
4597 			}
4598 			cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ?
4599 				DUPLEX_FULL : DUPLEX_HALF;
4600 		}
4601 	}
4602 
4603 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4604 						supported);
4605 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4606 						advertising);
4607 
4608 	return 0;
4609 }
4610 
4611 static int cas_set_link_ksettings(struct net_device *dev,
4612 				  const struct ethtool_link_ksettings *cmd)
4613 {
4614 	struct cas *cp = netdev_priv(dev);
4615 	unsigned long flags;
4616 	u32 speed = cmd->base.speed;
4617 
4618 	/* Verify the settings we care about. */
4619 	if (cmd->base.autoneg != AUTONEG_ENABLE &&
4620 	    cmd->base.autoneg != AUTONEG_DISABLE)
4621 		return -EINVAL;
4622 
4623 	if (cmd->base.autoneg == AUTONEG_DISABLE &&
4624 	    ((speed != SPEED_1000 &&
4625 	      speed != SPEED_100 &&
4626 	      speed != SPEED_10) ||
4627 	     (cmd->base.duplex != DUPLEX_HALF &&
4628 	      cmd->base.duplex != DUPLEX_FULL)))
4629 		return -EINVAL;
4630 
4631 	/* Apply settings and restart link process. */
4632 	spin_lock_irqsave(&cp->lock, flags);
4633 	cas_begin_auto_negotiation(cp, cmd);
4634 	spin_unlock_irqrestore(&cp->lock, flags);
4635 	return 0;
4636 }
4637 
4638 static int cas_nway_reset(struct net_device *dev)
4639 {
4640 	struct cas *cp = netdev_priv(dev);
4641 	unsigned long flags;
4642 
4643 	if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4644 		return -EINVAL;
4645 
4646 	/* Restart link process. */
4647 	spin_lock_irqsave(&cp->lock, flags);
4648 	cas_begin_auto_negotiation(cp, NULL);
4649 	spin_unlock_irqrestore(&cp->lock, flags);
4650 
4651 	return 0;
4652 }
4653 
4654 static u32 cas_get_link(struct net_device *dev)
4655 {
4656 	struct cas *cp = netdev_priv(dev);
4657 	return cp->lstate == link_up;
4658 }
4659 
4660 static u32 cas_get_msglevel(struct net_device *dev)
4661 {
4662 	struct cas *cp = netdev_priv(dev);
4663 	return cp->msg_enable;
4664 }
4665 
4666 static void cas_set_msglevel(struct net_device *dev, u32 value)
4667 {
4668 	struct cas *cp = netdev_priv(dev);
4669 	cp->msg_enable = value;
4670 }
4671 
4672 static int cas_get_regs_len(struct net_device *dev)
4673 {
4674 	struct cas *cp = netdev_priv(dev);
4675 	return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4676 }
4677 
4678 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4679 			     void *p)
4680 {
4681 	struct cas *cp = netdev_priv(dev);
4682 	regs->version = 0;
4683 	/* cas_read_regs handles locks (cp->lock).  */
4684 	cas_read_regs(cp, p, regs->len / sizeof(u32));
4685 }
4686 
4687 static int cas_get_sset_count(struct net_device *dev, int sset)
4688 {
4689 	switch (sset) {
4690 	case ETH_SS_STATS:
4691 		return CAS_NUM_STAT_KEYS;
4692 	default:
4693 		return -EOPNOTSUPP;
4694 	}
4695 }
4696 
4697 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4698 {
4699 	 memcpy(data, &ethtool_cassini_statnames,
4700 					 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4701 }
4702 
4703 static void cas_get_ethtool_stats(struct net_device *dev,
4704 				      struct ethtool_stats *estats, u64 *data)
4705 {
4706 	struct cas *cp = netdev_priv(dev);
4707 	struct net_device_stats *stats = cas_get_stats(cp->dev);
4708 	int i = 0;
4709 	data[i++] = stats->collisions;
4710 	data[i++] = stats->rx_bytes;
4711 	data[i++] = stats->rx_crc_errors;
4712 	data[i++] = stats->rx_dropped;
4713 	data[i++] = stats->rx_errors;
4714 	data[i++] = stats->rx_fifo_errors;
4715 	data[i++] = stats->rx_frame_errors;
4716 	data[i++] = stats->rx_length_errors;
4717 	data[i++] = stats->rx_over_errors;
4718 	data[i++] = stats->rx_packets;
4719 	data[i++] = stats->tx_aborted_errors;
4720 	data[i++] = stats->tx_bytes;
4721 	data[i++] = stats->tx_dropped;
4722 	data[i++] = stats->tx_errors;
4723 	data[i++] = stats->tx_fifo_errors;
4724 	data[i++] = stats->tx_packets;
4725 	BUG_ON(i != CAS_NUM_STAT_KEYS);
4726 }
4727 
4728 static const struct ethtool_ops cas_ethtool_ops = {
4729 	.get_drvinfo		= cas_get_drvinfo,
4730 	.nway_reset		= cas_nway_reset,
4731 	.get_link		= cas_get_link,
4732 	.get_msglevel		= cas_get_msglevel,
4733 	.set_msglevel		= cas_set_msglevel,
4734 	.get_regs_len		= cas_get_regs_len,
4735 	.get_regs		= cas_get_regs,
4736 	.get_sset_count		= cas_get_sset_count,
4737 	.get_strings		= cas_get_strings,
4738 	.get_ethtool_stats	= cas_get_ethtool_stats,
4739 	.get_link_ksettings	= cas_get_link_ksettings,
4740 	.set_link_ksettings	= cas_set_link_ksettings,
4741 };
4742 
4743 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4744 {
4745 	struct cas *cp = netdev_priv(dev);
4746 	struct mii_ioctl_data *data = if_mii(ifr);
4747 	unsigned long flags;
4748 	int rc = -EOPNOTSUPP;
4749 
4750 	/* Hold the PM mutex while doing ioctl's or we may collide
4751 	 * with open/close and power management and oops.
4752 	 */
4753 	mutex_lock(&cp->pm_mutex);
4754 	switch (cmd) {
4755 	case SIOCGMIIPHY:		/* Get address of MII PHY in use. */
4756 		data->phy_id = cp->phy_addr;
4757 		/* Fallthrough... */
4758 
4759 	case SIOCGMIIREG:		/* Read MII PHY register. */
4760 		spin_lock_irqsave(&cp->lock, flags);
4761 		cas_mif_poll(cp, 0);
4762 		data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4763 		cas_mif_poll(cp, 1);
4764 		spin_unlock_irqrestore(&cp->lock, flags);
4765 		rc = 0;
4766 		break;
4767 
4768 	case SIOCSMIIREG:		/* Write MII PHY register. */
4769 		spin_lock_irqsave(&cp->lock, flags);
4770 		cas_mif_poll(cp, 0);
4771 		rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4772 		cas_mif_poll(cp, 1);
4773 		spin_unlock_irqrestore(&cp->lock, flags);
4774 		break;
4775 	default:
4776 		break;
4777 	}
4778 
4779 	mutex_unlock(&cp->pm_mutex);
4780 	return rc;
4781 }
4782 
4783 /* When this chip sits underneath an Intel 31154 bridge, it is the
4784  * only subordinate device and we can tweak the bridge settings to
4785  * reflect that fact.
4786  */
4787 static void cas_program_bridge(struct pci_dev *cas_pdev)
4788 {
4789 	struct pci_dev *pdev = cas_pdev->bus->self;
4790 	u32 val;
4791 
4792 	if (!pdev)
4793 		return;
4794 
4795 	if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4796 		return;
4797 
4798 	/* Clear bit 10 (Bus Parking Control) in the Secondary
4799 	 * Arbiter Control/Status Register which lives at offset
4800 	 * 0x41.  Using a 32-bit word read/modify/write at 0x40
4801 	 * is much simpler so that's how we do this.
4802 	 */
4803 	pci_read_config_dword(pdev, 0x40, &val);
4804 	val &= ~0x00040000;
4805 	pci_write_config_dword(pdev, 0x40, val);
4806 
4807 	/* Max out the Multi-Transaction Timer settings since
4808 	 * Cassini is the only device present.
4809 	 *
4810 	 * The register is 16-bit and lives at 0x50.  When the
4811 	 * settings are enabled, it extends the GRANT# signal
4812 	 * for a requestor after a transaction is complete.  This
4813 	 * allows the next request to run without first needing
4814 	 * to negotiate the GRANT# signal back.
4815 	 *
4816 	 * Bits 12:10 define the grant duration:
4817 	 *
4818 	 *	1	--	16 clocks
4819 	 *	2	--	32 clocks
4820 	 *	3	--	64 clocks
4821 	 *	4	--	128 clocks
4822 	 *	5	--	256 clocks
4823 	 *
4824 	 * All other values are illegal.
4825 	 *
4826 	 * Bits 09:00 define which REQ/GNT signal pairs get the
4827 	 * GRANT# signal treatment.  We set them all.
4828 	 */
4829 	pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4830 
4831 	/* The Read Prefecth Policy register is 16-bit and sits at
4832 	 * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4833 	 * enable it and max out all of the settings since only one
4834 	 * device is sitting underneath and thus bandwidth sharing is
4835 	 * not an issue.
4836 	 *
4837 	 * The register has several 3 bit fields, which indicates a
4838 	 * multiplier applied to the base amount of prefetching the
4839 	 * chip would do.  These fields are at:
4840 	 *
4841 	 *	15:13	---	ReRead Primary Bus
4842 	 *	12:10	---	FirstRead Primary Bus
4843 	 *	09:07	---	ReRead Secondary Bus
4844 	 *	06:04	---	FirstRead Secondary Bus
4845 	 *
4846 	 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4847 	 * get enabled on.  Bit 3 is a grouped enabler which controls
4848 	 * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4849 	 * the individual REQ/GNT pairs [2:0].
4850 	 */
4851 	pci_write_config_word(pdev, 0x52,
4852 			      (0x7 << 13) |
4853 			      (0x7 << 10) |
4854 			      (0x7 <<  7) |
4855 			      (0x7 <<  4) |
4856 			      (0xf <<  0));
4857 
4858 	/* Force cacheline size to 0x8 */
4859 	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4860 
4861 	/* Force latency timer to maximum setting so Cassini can
4862 	 * sit on the bus as long as it likes.
4863 	 */
4864 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4865 }
4866 
4867 static const struct net_device_ops cas_netdev_ops = {
4868 	.ndo_open		= cas_open,
4869 	.ndo_stop		= cas_close,
4870 	.ndo_start_xmit		= cas_start_xmit,
4871 	.ndo_get_stats 		= cas_get_stats,
4872 	.ndo_set_rx_mode	= cas_set_multicast,
4873 	.ndo_do_ioctl		= cas_ioctl,
4874 	.ndo_tx_timeout		= cas_tx_timeout,
4875 	.ndo_change_mtu		= cas_change_mtu,
4876 	.ndo_set_mac_address	= eth_mac_addr,
4877 	.ndo_validate_addr	= eth_validate_addr,
4878 #ifdef CONFIG_NET_POLL_CONTROLLER
4879 	.ndo_poll_controller	= cas_netpoll,
4880 #endif
4881 };
4882 
4883 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4884 {
4885 	static int cas_version_printed = 0;
4886 	unsigned long casreg_len;
4887 	struct net_device *dev;
4888 	struct cas *cp;
4889 	int i, err, pci_using_dac;
4890 	u16 pci_cmd;
4891 	u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4892 
4893 	if (cas_version_printed++ == 0)
4894 		pr_info("%s", version);
4895 
4896 	err = pci_enable_device(pdev);
4897 	if (err) {
4898 		dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4899 		return err;
4900 	}
4901 
4902 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4903 		dev_err(&pdev->dev, "Cannot find proper PCI device "
4904 		       "base address, aborting\n");
4905 		err = -ENODEV;
4906 		goto err_out_disable_pdev;
4907 	}
4908 
4909 	dev = alloc_etherdev(sizeof(*cp));
4910 	if (!dev) {
4911 		err = -ENOMEM;
4912 		goto err_out_disable_pdev;
4913 	}
4914 	SET_NETDEV_DEV(dev, &pdev->dev);
4915 
4916 	err = pci_request_regions(pdev, dev->name);
4917 	if (err) {
4918 		dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4919 		goto err_out_free_netdev;
4920 	}
4921 	pci_set_master(pdev);
4922 
4923 	/* we must always turn on parity response or else parity
4924 	 * doesn't get generated properly. disable SERR/PERR as well.
4925 	 * in addition, we want to turn MWI on.
4926 	 */
4927 	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4928 	pci_cmd &= ~PCI_COMMAND_SERR;
4929 	pci_cmd |= PCI_COMMAND_PARITY;
4930 	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4931 	if (pci_try_set_mwi(pdev))
4932 		pr_warn("Could not enable MWI for %s\n", pci_name(pdev));
4933 
4934 	cas_program_bridge(pdev);
4935 
4936 	/*
4937 	 * On some architectures, the default cache line size set
4938 	 * by pci_try_set_mwi reduces perforamnce.  We have to increase
4939 	 * it for this case.  To start, we'll print some configuration
4940 	 * data.
4941 	 */
4942 #if 1
4943 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4944 			     &orig_cacheline_size);
4945 	if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4946 		cas_cacheline_size =
4947 			(CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4948 			CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4949 		if (pci_write_config_byte(pdev,
4950 					  PCI_CACHE_LINE_SIZE,
4951 					  cas_cacheline_size)) {
4952 			dev_err(&pdev->dev, "Could not set PCI cache "
4953 			       "line size\n");
4954 			goto err_out_free_res;
4955 		}
4956 	}
4957 #endif
4958 
4959 
4960 	/* Configure DMA attributes. */
4961 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4962 		pci_using_dac = 1;
4963 		err = pci_set_consistent_dma_mask(pdev,
4964 						  DMA_BIT_MASK(64));
4965 		if (err < 0) {
4966 			dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
4967 			       "for consistent allocations\n");
4968 			goto err_out_free_res;
4969 		}
4970 
4971 	} else {
4972 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4973 		if (err) {
4974 			dev_err(&pdev->dev, "No usable DMA configuration, "
4975 			       "aborting\n");
4976 			goto err_out_free_res;
4977 		}
4978 		pci_using_dac = 0;
4979 	}
4980 
4981 	casreg_len = pci_resource_len(pdev, 0);
4982 
4983 	cp = netdev_priv(dev);
4984 	cp->pdev = pdev;
4985 #if 1
4986 	/* A value of 0 indicates we never explicitly set it */
4987 	cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4988 #endif
4989 	cp->dev = dev;
4990 	cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4991 	  cassini_debug;
4992 
4993 #if defined(CONFIG_SPARC)
4994 	cp->of_node = pci_device_to_OF_node(pdev);
4995 #endif
4996 
4997 	cp->link_transition = LINK_TRANSITION_UNKNOWN;
4998 	cp->link_transition_jiffies_valid = 0;
4999 
5000 	spin_lock_init(&cp->lock);
5001 	spin_lock_init(&cp->rx_inuse_lock);
5002 	spin_lock_init(&cp->rx_spare_lock);
5003 	for (i = 0; i < N_TX_RINGS; i++) {
5004 		spin_lock_init(&cp->stat_lock[i]);
5005 		spin_lock_init(&cp->tx_lock[i]);
5006 	}
5007 	spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5008 	mutex_init(&cp->pm_mutex);
5009 
5010 	timer_setup(&cp->link_timer, cas_link_timer, 0);
5011 
5012 #if 1
5013 	/* Just in case the implementation of atomic operations
5014 	 * change so that an explicit initialization is necessary.
5015 	 */
5016 	atomic_set(&cp->reset_task_pending, 0);
5017 	atomic_set(&cp->reset_task_pending_all, 0);
5018 	atomic_set(&cp->reset_task_pending_spare, 0);
5019 	atomic_set(&cp->reset_task_pending_mtu, 0);
5020 #endif
5021 	INIT_WORK(&cp->reset_task, cas_reset_task);
5022 
5023 	/* Default link parameters */
5024 	if (link_mode >= 0 && link_mode < 6)
5025 		cp->link_cntl = link_modes[link_mode];
5026 	else
5027 		cp->link_cntl = BMCR_ANENABLE;
5028 	cp->lstate = link_down;
5029 	cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5030 	netif_carrier_off(cp->dev);
5031 	cp->timer_ticks = 0;
5032 
5033 	/* give us access to cassini registers */
5034 	cp->regs = pci_iomap(pdev, 0, casreg_len);
5035 	if (!cp->regs) {
5036 		dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5037 		goto err_out_free_res;
5038 	}
5039 	cp->casreg_len = casreg_len;
5040 
5041 	pci_save_state(pdev);
5042 	cas_check_pci_invariants(cp);
5043 	cas_hard_reset(cp);
5044 	cas_reset(cp, 0);
5045 	if (cas_check_invariants(cp))
5046 		goto err_out_iounmap;
5047 	if (cp->cas_flags & CAS_FLAG_SATURN)
5048 		cas_saturn_firmware_init(cp);
5049 
5050 	cp->init_block =
5051 		pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5052 				     &cp->block_dvma);
5053 	if (!cp->init_block) {
5054 		dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5055 		goto err_out_iounmap;
5056 	}
5057 
5058 	for (i = 0; i < N_TX_RINGS; i++)
5059 		cp->init_txds[i] = cp->init_block->txds[i];
5060 
5061 	for (i = 0; i < N_RX_DESC_RINGS; i++)
5062 		cp->init_rxds[i] = cp->init_block->rxds[i];
5063 
5064 	for (i = 0; i < N_RX_COMP_RINGS; i++)
5065 		cp->init_rxcs[i] = cp->init_block->rxcs[i];
5066 
5067 	for (i = 0; i < N_RX_FLOWS; i++)
5068 		skb_queue_head_init(&cp->rx_flows[i]);
5069 
5070 	dev->netdev_ops = &cas_netdev_ops;
5071 	dev->ethtool_ops = &cas_ethtool_ops;
5072 	dev->watchdog_timeo = CAS_TX_TIMEOUT;
5073 
5074 #ifdef USE_NAPI
5075 	netif_napi_add(dev, &cp->napi, cas_poll, 64);
5076 #endif
5077 	dev->irq = pdev->irq;
5078 	dev->dma = 0;
5079 
5080 	/* Cassini features. */
5081 	if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5082 		dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5083 
5084 	if (pci_using_dac)
5085 		dev->features |= NETIF_F_HIGHDMA;
5086 
5087 	/* MTU range: 60 - varies or 9000 */
5088 	dev->min_mtu = CAS_MIN_MTU;
5089 	dev->max_mtu = CAS_MAX_MTU;
5090 
5091 	if (register_netdev(dev)) {
5092 		dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5093 		goto err_out_free_consistent;
5094 	}
5095 
5096 	i = readl(cp->regs + REG_BIM_CFG);
5097 	netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5098 		    (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5099 		    (i & BIM_CFG_32BIT) ? "32" : "64",
5100 		    (i & BIM_CFG_66MHZ) ? "66" : "33",
5101 		    (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5102 		    dev->dev_addr);
5103 
5104 	pci_set_drvdata(pdev, dev);
5105 	cp->hw_running = 1;
5106 	cas_entropy_reset(cp);
5107 	cas_phy_init(cp);
5108 	cas_begin_auto_negotiation(cp, NULL);
5109 	return 0;
5110 
5111 err_out_free_consistent:
5112 	pci_free_consistent(pdev, sizeof(struct cas_init_block),
5113 			    cp->init_block, cp->block_dvma);
5114 
5115 err_out_iounmap:
5116 	mutex_lock(&cp->pm_mutex);
5117 	if (cp->hw_running)
5118 		cas_shutdown(cp);
5119 	mutex_unlock(&cp->pm_mutex);
5120 
5121 	pci_iounmap(pdev, cp->regs);
5122 
5123 
5124 err_out_free_res:
5125 	pci_release_regions(pdev);
5126 
5127 	/* Try to restore it in case the error occurred after we
5128 	 * set it.
5129 	 */
5130 	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5131 
5132 err_out_free_netdev:
5133 	free_netdev(dev);
5134 
5135 err_out_disable_pdev:
5136 	pci_disable_device(pdev);
5137 	return -ENODEV;
5138 }
5139 
5140 static void cas_remove_one(struct pci_dev *pdev)
5141 {
5142 	struct net_device *dev = pci_get_drvdata(pdev);
5143 	struct cas *cp;
5144 	if (!dev)
5145 		return;
5146 
5147 	cp = netdev_priv(dev);
5148 	unregister_netdev(dev);
5149 
5150 	vfree(cp->fw_data);
5151 
5152 	mutex_lock(&cp->pm_mutex);
5153 	cancel_work_sync(&cp->reset_task);
5154 	if (cp->hw_running)
5155 		cas_shutdown(cp);
5156 	mutex_unlock(&cp->pm_mutex);
5157 
5158 #if 1
5159 	if (cp->orig_cacheline_size) {
5160 		/* Restore the cache line size if we had modified
5161 		 * it.
5162 		 */
5163 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5164 				      cp->orig_cacheline_size);
5165 	}
5166 #endif
5167 	pci_free_consistent(pdev, sizeof(struct cas_init_block),
5168 			    cp->init_block, cp->block_dvma);
5169 	pci_iounmap(pdev, cp->regs);
5170 	free_netdev(dev);
5171 	pci_release_regions(pdev);
5172 	pci_disable_device(pdev);
5173 }
5174 
5175 #ifdef CONFIG_PM
5176 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5177 {
5178 	struct net_device *dev = pci_get_drvdata(pdev);
5179 	struct cas *cp = netdev_priv(dev);
5180 	unsigned long flags;
5181 
5182 	mutex_lock(&cp->pm_mutex);
5183 
5184 	/* If the driver is opened, we stop the DMA */
5185 	if (cp->opened) {
5186 		netif_device_detach(dev);
5187 
5188 		cas_lock_all_save(cp, flags);
5189 
5190 		/* We can set the second arg of cas_reset to 0
5191 		 * because on resume, we'll call cas_init_hw with
5192 		 * its second arg set so that autonegotiation is
5193 		 * restarted.
5194 		 */
5195 		cas_reset(cp, 0);
5196 		cas_clean_rings(cp);
5197 		cas_unlock_all_restore(cp, flags);
5198 	}
5199 
5200 	if (cp->hw_running)
5201 		cas_shutdown(cp);
5202 	mutex_unlock(&cp->pm_mutex);
5203 
5204 	return 0;
5205 }
5206 
5207 static int cas_resume(struct pci_dev *pdev)
5208 {
5209 	struct net_device *dev = pci_get_drvdata(pdev);
5210 	struct cas *cp = netdev_priv(dev);
5211 
5212 	netdev_info(dev, "resuming\n");
5213 
5214 	mutex_lock(&cp->pm_mutex);
5215 	cas_hard_reset(cp);
5216 	if (cp->opened) {
5217 		unsigned long flags;
5218 		cas_lock_all_save(cp, flags);
5219 		cas_reset(cp, 0);
5220 		cp->hw_running = 1;
5221 		cas_clean_rings(cp);
5222 		cas_init_hw(cp, 1);
5223 		cas_unlock_all_restore(cp, flags);
5224 
5225 		netif_device_attach(dev);
5226 	}
5227 	mutex_unlock(&cp->pm_mutex);
5228 	return 0;
5229 }
5230 #endif /* CONFIG_PM */
5231 
5232 static struct pci_driver cas_driver = {
5233 	.name		= DRV_MODULE_NAME,
5234 	.id_table	= cas_pci_tbl,
5235 	.probe		= cas_init_one,
5236 	.remove		= cas_remove_one,
5237 #ifdef CONFIG_PM
5238 	.suspend	= cas_suspend,
5239 	.resume		= cas_resume
5240 #endif
5241 };
5242 
5243 static int __init cas_init(void)
5244 {
5245 	if (linkdown_timeout > 0)
5246 		link_transition_timeout = linkdown_timeout * HZ;
5247 	else
5248 		link_transition_timeout = 0;
5249 
5250 	return pci_register_driver(&cas_driver);
5251 }
5252 
5253 static void __exit cas_cleanup(void)
5254 {
5255 	pci_unregister_driver(&cas_driver);
5256 }
5257 
5258 module_init(cas_init);
5259 module_exit(cas_cleanup);
5260