1 // SPDX-License-Identifier: GPL-2.0+ 2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver. 3 * 4 * Copyright (C) 2004 Sun Microsystems Inc. 5 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com) 6 * 7 * This driver uses the sungem driver (c) David Miller 8 * (davem@redhat.com) as its basis. 9 * 10 * The cassini chip has a number of features that distinguish it from 11 * the gem chip: 12 * 4 transmit descriptor rings that are used for either QoS (VLAN) or 13 * load balancing (non-VLAN mode) 14 * batching of multiple packets 15 * multiple CPU dispatching 16 * page-based RX descriptor engine with separate completion rings 17 * Gigabit support (GMII and PCS interface) 18 * MIF link up/down detection works 19 * 20 * RX is handled by page sized buffers that are attached as fragments to 21 * the skb. here's what's done: 22 * -- driver allocates pages at a time and keeps reference counts 23 * on them. 24 * -- the upper protocol layers assume that the header is in the skb 25 * itself. as a result, cassini will copy a small amount (64 bytes) 26 * to make them happy. 27 * -- driver appends the rest of the data pages as frags to skbuffs 28 * and increments the reference count 29 * -- on page reclamation, the driver swaps the page with a spare page. 30 * if that page is still in use, it frees its reference to that page, 31 * and allocates a new page for use. otherwise, it just recycles the 32 * page. 33 * 34 * NOTE: cassini can parse the header. however, it's not worth it 35 * as long as the network stack requires a header copy. 36 * 37 * TX has 4 queues. currently these queues are used in a round-robin 38 * fashion for load balancing. They can also be used for QoS. for that 39 * to work, however, QoS information needs to be exposed down to the driver 40 * level so that subqueues get targeted to particular transmit rings. 41 * alternatively, the queues can be configured via use of the all-purpose 42 * ioctl. 43 * 44 * RX DATA: the rx completion ring has all the info, but the rx desc 45 * ring has all of the data. RX can conceivably come in under multiple 46 * interrupts, but the INT# assignment needs to be set up properly by 47 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do 48 * that. also, the two descriptor rings are designed to distinguish between 49 * encrypted and non-encrypted packets, but we use them for buffering 50 * instead. 51 * 52 * by default, the selective clear mask is set up to process rx packets. 53 */ 54 55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 56 57 #include <linux/module.h> 58 #include <linux/kernel.h> 59 #include <linux/types.h> 60 #include <linux/compiler.h> 61 #include <linux/slab.h> 62 #include <linux/delay.h> 63 #include <linux/init.h> 64 #include <linux/interrupt.h> 65 #include <linux/vmalloc.h> 66 #include <linux/ioport.h> 67 #include <linux/pci.h> 68 #include <linux/mm.h> 69 #include <linux/highmem.h> 70 #include <linux/list.h> 71 #include <linux/dma-mapping.h> 72 73 #include <linux/netdevice.h> 74 #include <linux/etherdevice.h> 75 #include <linux/skbuff.h> 76 #include <linux/ethtool.h> 77 #include <linux/crc32.h> 78 #include <linux/random.h> 79 #include <linux/mii.h> 80 #include <linux/ip.h> 81 #include <linux/tcp.h> 82 #include <linux/mutex.h> 83 #include <linux/firmware.h> 84 85 #include <net/checksum.h> 86 87 #include <linux/atomic.h> 88 #include <asm/io.h> 89 #include <asm/byteorder.h> 90 #include <linux/uaccess.h> 91 #include <linux/jiffies.h> 92 93 #define CAS_NCPUS num_online_cpus() 94 95 #define cas_skb_release(x) netif_rx(x) 96 97 /* select which firmware to use */ 98 #define USE_HP_WORKAROUND 99 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */ 100 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */ 101 102 #include "cassini.h" 103 104 #define USE_TX_COMPWB /* use completion writeback registers */ 105 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */ 106 #define USE_RX_BLANK /* hw interrupt mitigation */ 107 #undef USE_ENTROPY_DEV /* don't test for entropy device */ 108 109 /* NOTE: these aren't useable unless PCI interrupts can be assigned. 110 * also, we need to make cp->lock finer-grained. 111 */ 112 #undef USE_PCI_INTB 113 #undef USE_PCI_INTC 114 #undef USE_PCI_INTD 115 #undef USE_QOS 116 117 #undef USE_VPD_DEBUG /* debug vpd information if defined */ 118 119 /* rx processing options */ 120 #define USE_PAGE_ORDER /* specify to allocate large rx pages */ 121 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */ 122 #define RX_COPY_ALWAYS 0 /* if 0, use frags */ 123 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */ 124 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */ 125 126 #define DRV_MODULE_NAME "cassini" 127 #define DRV_MODULE_VERSION "1.6" 128 #define DRV_MODULE_RELDATE "21 May 2008" 129 130 #define CAS_DEF_MSG_ENABLE \ 131 (NETIF_MSG_DRV | \ 132 NETIF_MSG_PROBE | \ 133 NETIF_MSG_LINK | \ 134 NETIF_MSG_TIMER | \ 135 NETIF_MSG_IFDOWN | \ 136 NETIF_MSG_IFUP | \ 137 NETIF_MSG_RX_ERR | \ 138 NETIF_MSG_TX_ERR) 139 140 /* length of time before we decide the hardware is borked, 141 * and dev->tx_timeout() should be called to fix the problem 142 */ 143 #define CAS_TX_TIMEOUT (HZ) 144 #define CAS_LINK_TIMEOUT (22*HZ/10) 145 #define CAS_LINK_FAST_TIMEOUT (1) 146 147 /* timeout values for state changing. these specify the number 148 * of 10us delays to be used before giving up. 149 */ 150 #define STOP_TRIES_PHY 1000 151 #define STOP_TRIES 5000 152 153 /* specify a minimum frame size to deal with some fifo issues 154 * max mtu == 2 * page size - ethernet header - 64 - swivel = 155 * 2 * page_size - 0x50 156 */ 157 #define CAS_MIN_FRAME 97 158 #define CAS_1000MB_MIN_FRAME 255 159 #define CAS_MIN_MTU 60 160 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000) 161 162 #if 1 163 /* 164 * Eliminate these and use separate atomic counters for each, to 165 * avoid a race condition. 166 */ 167 #else 168 #define CAS_RESET_MTU 1 169 #define CAS_RESET_ALL 2 170 #define CAS_RESET_SPARE 3 171 #endif 172 173 static char version[] = 174 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 175 176 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */ 177 static int link_mode; 178 179 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)"); 180 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver"); 181 MODULE_LICENSE("GPL"); 182 MODULE_FIRMWARE("sun/cassini.bin"); 183 module_param(cassini_debug, int, 0); 184 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value"); 185 module_param(link_mode, int, 0); 186 MODULE_PARM_DESC(link_mode, "default link mode"); 187 188 /* 189 * Work around for a PCS bug in which the link goes down due to the chip 190 * being confused and never showing a link status of "up." 191 */ 192 #define DEFAULT_LINKDOWN_TIMEOUT 5 193 /* 194 * Value in seconds, for user input. 195 */ 196 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT; 197 module_param(linkdown_timeout, int, 0); 198 MODULE_PARM_DESC(linkdown_timeout, 199 "min reset interval in sec. for PCS linkdown issue; disabled if not positive"); 200 201 /* 202 * value in 'ticks' (units used by jiffies). Set when we init the 203 * module because 'HZ' in actually a function call on some flavors of 204 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ. 205 */ 206 static int link_transition_timeout; 207 208 209 210 static u16 link_modes[] = { 211 BMCR_ANENABLE, /* 0 : autoneg */ 212 0, /* 1 : 10bt half duplex */ 213 BMCR_SPEED100, /* 2 : 100bt half duplex */ 214 BMCR_FULLDPLX, /* 3 : 10bt full duplex */ 215 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */ 216 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */ 217 }; 218 219 static const struct pci_device_id cas_pci_tbl[] = { 220 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI, 221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 222 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN, 223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 224 { 0, } 225 }; 226 227 MODULE_DEVICE_TABLE(pci, cas_pci_tbl); 228 229 static void cas_set_link_modes(struct cas *cp); 230 231 static inline void cas_lock_tx(struct cas *cp) 232 { 233 int i; 234 235 for (i = 0; i < N_TX_RINGS; i++) 236 spin_lock_nested(&cp->tx_lock[i], i); 237 } 238 239 /* WTZ: QA was finding deadlock problems with the previous 240 * versions after long test runs with multiple cards per machine. 241 * See if replacing cas_lock_all with safer versions helps. The 242 * symptoms QA is reporting match those we'd expect if interrupts 243 * aren't being properly restored, and we fixed a previous deadlock 244 * with similar symptoms by using save/restore versions in other 245 * places. 246 */ 247 #define cas_lock_all_save(cp, flags) \ 248 do { \ 249 struct cas *xxxcp = (cp); \ 250 spin_lock_irqsave(&xxxcp->lock, flags); \ 251 cas_lock_tx(xxxcp); \ 252 } while (0) 253 254 static inline void cas_unlock_tx(struct cas *cp) 255 { 256 int i; 257 258 for (i = N_TX_RINGS; i > 0; i--) 259 spin_unlock(&cp->tx_lock[i - 1]); 260 } 261 262 #define cas_unlock_all_restore(cp, flags) \ 263 do { \ 264 struct cas *xxxcp = (cp); \ 265 cas_unlock_tx(xxxcp); \ 266 spin_unlock_irqrestore(&xxxcp->lock, flags); \ 267 } while (0) 268 269 static void cas_disable_irq(struct cas *cp, const int ring) 270 { 271 /* Make sure we won't get any more interrupts */ 272 if (ring == 0) { 273 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); 274 return; 275 } 276 277 /* disable completion interrupts and selectively mask */ 278 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 279 switch (ring) { 280 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 281 #ifdef USE_PCI_INTB 282 case 1: 283 #endif 284 #ifdef USE_PCI_INTC 285 case 2: 286 #endif 287 #ifdef USE_PCI_INTD 288 case 3: 289 #endif 290 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, 291 cp->regs + REG_PLUS_INTRN_MASK(ring)); 292 break; 293 #endif 294 default: 295 writel(INTRN_MASK_CLEAR_ALL, cp->regs + 296 REG_PLUS_INTRN_MASK(ring)); 297 break; 298 } 299 } 300 } 301 302 static inline void cas_mask_intr(struct cas *cp) 303 { 304 int i; 305 306 for (i = 0; i < N_RX_COMP_RINGS; i++) 307 cas_disable_irq(cp, i); 308 } 309 310 static void cas_enable_irq(struct cas *cp, const int ring) 311 { 312 if (ring == 0) { /* all but TX_DONE */ 313 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); 314 return; 315 } 316 317 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 318 switch (ring) { 319 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 320 #ifdef USE_PCI_INTB 321 case 1: 322 #endif 323 #ifdef USE_PCI_INTC 324 case 2: 325 #endif 326 #ifdef USE_PCI_INTD 327 case 3: 328 #endif 329 writel(INTRN_MASK_RX_EN, cp->regs + 330 REG_PLUS_INTRN_MASK(ring)); 331 break; 332 #endif 333 default: 334 break; 335 } 336 } 337 } 338 339 static inline void cas_unmask_intr(struct cas *cp) 340 { 341 int i; 342 343 for (i = 0; i < N_RX_COMP_RINGS; i++) 344 cas_enable_irq(cp, i); 345 } 346 347 static inline void cas_entropy_gather(struct cas *cp) 348 { 349 #ifdef USE_ENTROPY_DEV 350 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 351 return; 352 353 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), 354 readl(cp->regs + REG_ENTROPY_IV), 355 sizeof(uint64_t)*8); 356 #endif 357 } 358 359 static inline void cas_entropy_reset(struct cas *cp) 360 { 361 #ifdef USE_ENTROPY_DEV 362 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 363 return; 364 365 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, 366 cp->regs + REG_BIM_LOCAL_DEV_EN); 367 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET); 368 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG); 369 370 /* if we read back 0x0, we don't have an entropy device */ 371 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0) 372 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV; 373 #endif 374 } 375 376 /* access to the phy. the following assumes that we've initialized the MIF to 377 * be in frame rather than bit-bang mode 378 */ 379 static u16 cas_phy_read(struct cas *cp, int reg) 380 { 381 u32 cmd; 382 int limit = STOP_TRIES_PHY; 383 384 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ; 385 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 386 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 387 cmd |= MIF_FRAME_TURN_AROUND_MSB; 388 writel(cmd, cp->regs + REG_MIF_FRAME); 389 390 /* poll for completion */ 391 while (limit-- > 0) { 392 udelay(10); 393 cmd = readl(cp->regs + REG_MIF_FRAME); 394 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 395 return cmd & MIF_FRAME_DATA_MASK; 396 } 397 return 0xFFFF; /* -1 */ 398 } 399 400 static int cas_phy_write(struct cas *cp, int reg, u16 val) 401 { 402 int limit = STOP_TRIES_PHY; 403 u32 cmd; 404 405 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE; 406 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 407 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 408 cmd |= MIF_FRAME_TURN_AROUND_MSB; 409 cmd |= val & MIF_FRAME_DATA_MASK; 410 writel(cmd, cp->regs + REG_MIF_FRAME); 411 412 /* poll for completion */ 413 while (limit-- > 0) { 414 udelay(10); 415 cmd = readl(cp->regs + REG_MIF_FRAME); 416 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 417 return 0; 418 } 419 return -1; 420 } 421 422 static void cas_phy_powerup(struct cas *cp) 423 { 424 u16 ctl = cas_phy_read(cp, MII_BMCR); 425 426 if ((ctl & BMCR_PDOWN) == 0) 427 return; 428 ctl &= ~BMCR_PDOWN; 429 cas_phy_write(cp, MII_BMCR, ctl); 430 } 431 432 static void cas_phy_powerdown(struct cas *cp) 433 { 434 u16 ctl = cas_phy_read(cp, MII_BMCR); 435 436 if (ctl & BMCR_PDOWN) 437 return; 438 ctl |= BMCR_PDOWN; 439 cas_phy_write(cp, MII_BMCR, ctl); 440 } 441 442 /* cp->lock held. note: the last put_page will free the buffer */ 443 static int cas_page_free(struct cas *cp, cas_page_t *page) 444 { 445 dma_unmap_page(&cp->pdev->dev, page->dma_addr, cp->page_size, 446 DMA_FROM_DEVICE); 447 __free_pages(page->buffer, cp->page_order); 448 kfree(page); 449 return 0; 450 } 451 452 #ifdef RX_COUNT_BUFFERS 453 #define RX_USED_ADD(x, y) ((x)->used += (y)) 454 #define RX_USED_SET(x, y) ((x)->used = (y)) 455 #else 456 #define RX_USED_ADD(x, y) do { } while(0) 457 #define RX_USED_SET(x, y) do { } while(0) 458 #endif 459 460 /* local page allocation routines for the receive buffers. jumbo pages 461 * require at least 8K contiguous and 8K aligned buffers. 462 */ 463 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags) 464 { 465 cas_page_t *page; 466 467 page = kmalloc(sizeof(cas_page_t), flags); 468 if (!page) 469 return NULL; 470 471 INIT_LIST_HEAD(&page->list); 472 RX_USED_SET(page, 0); 473 page->buffer = alloc_pages(flags, cp->page_order); 474 if (!page->buffer) 475 goto page_err; 476 page->dma_addr = dma_map_page(&cp->pdev->dev, page->buffer, 0, 477 cp->page_size, DMA_FROM_DEVICE); 478 return page; 479 480 page_err: 481 kfree(page); 482 return NULL; 483 } 484 485 /* initialize spare pool of rx buffers, but allocate during the open */ 486 static void cas_spare_init(struct cas *cp) 487 { 488 spin_lock(&cp->rx_inuse_lock); 489 INIT_LIST_HEAD(&cp->rx_inuse_list); 490 spin_unlock(&cp->rx_inuse_lock); 491 492 spin_lock(&cp->rx_spare_lock); 493 INIT_LIST_HEAD(&cp->rx_spare_list); 494 cp->rx_spares_needed = RX_SPARE_COUNT; 495 spin_unlock(&cp->rx_spare_lock); 496 } 497 498 /* used on close. free all the spare buffers. */ 499 static void cas_spare_free(struct cas *cp) 500 { 501 struct list_head list, *elem, *tmp; 502 503 /* free spare buffers */ 504 INIT_LIST_HEAD(&list); 505 spin_lock(&cp->rx_spare_lock); 506 list_splice_init(&cp->rx_spare_list, &list); 507 spin_unlock(&cp->rx_spare_lock); 508 list_for_each_safe(elem, tmp, &list) { 509 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 510 } 511 512 INIT_LIST_HEAD(&list); 513 #if 1 514 /* 515 * Looks like Adrian had protected this with a different 516 * lock than used everywhere else to manipulate this list. 517 */ 518 spin_lock(&cp->rx_inuse_lock); 519 list_splice_init(&cp->rx_inuse_list, &list); 520 spin_unlock(&cp->rx_inuse_lock); 521 #else 522 spin_lock(&cp->rx_spare_lock); 523 list_splice_init(&cp->rx_inuse_list, &list); 524 spin_unlock(&cp->rx_spare_lock); 525 #endif 526 list_for_each_safe(elem, tmp, &list) { 527 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 528 } 529 } 530 531 /* replenish spares if needed */ 532 static void cas_spare_recover(struct cas *cp, const gfp_t flags) 533 { 534 struct list_head list, *elem, *tmp; 535 int needed, i; 536 537 /* check inuse list. if we don't need any more free buffers, 538 * just free it 539 */ 540 541 /* make a local copy of the list */ 542 INIT_LIST_HEAD(&list); 543 spin_lock(&cp->rx_inuse_lock); 544 list_splice_init(&cp->rx_inuse_list, &list); 545 spin_unlock(&cp->rx_inuse_lock); 546 547 list_for_each_safe(elem, tmp, &list) { 548 cas_page_t *page = list_entry(elem, cas_page_t, list); 549 550 /* 551 * With the lockless pagecache, cassini buffering scheme gets 552 * slightly less accurate: we might find that a page has an 553 * elevated reference count here, due to a speculative ref, 554 * and skip it as in-use. Ideally we would be able to reclaim 555 * it. However this would be such a rare case, it doesn't 556 * matter too much as we should pick it up the next time round. 557 * 558 * Importantly, if we find that the page has a refcount of 1 559 * here (our refcount), then we know it is definitely not inuse 560 * so we can reuse it. 561 */ 562 if (page_count(page->buffer) > 1) 563 continue; 564 565 list_del(elem); 566 spin_lock(&cp->rx_spare_lock); 567 if (cp->rx_spares_needed > 0) { 568 list_add(elem, &cp->rx_spare_list); 569 cp->rx_spares_needed--; 570 spin_unlock(&cp->rx_spare_lock); 571 } else { 572 spin_unlock(&cp->rx_spare_lock); 573 cas_page_free(cp, page); 574 } 575 } 576 577 /* put any inuse buffers back on the list */ 578 if (!list_empty(&list)) { 579 spin_lock(&cp->rx_inuse_lock); 580 list_splice(&list, &cp->rx_inuse_list); 581 spin_unlock(&cp->rx_inuse_lock); 582 } 583 584 spin_lock(&cp->rx_spare_lock); 585 needed = cp->rx_spares_needed; 586 spin_unlock(&cp->rx_spare_lock); 587 if (!needed) 588 return; 589 590 /* we still need spares, so try to allocate some */ 591 INIT_LIST_HEAD(&list); 592 i = 0; 593 while (i < needed) { 594 cas_page_t *spare = cas_page_alloc(cp, flags); 595 if (!spare) 596 break; 597 list_add(&spare->list, &list); 598 i++; 599 } 600 601 spin_lock(&cp->rx_spare_lock); 602 list_splice(&list, &cp->rx_spare_list); 603 cp->rx_spares_needed -= i; 604 spin_unlock(&cp->rx_spare_lock); 605 } 606 607 /* pull a page from the list. */ 608 static cas_page_t *cas_page_dequeue(struct cas *cp) 609 { 610 struct list_head *entry; 611 int recover; 612 613 spin_lock(&cp->rx_spare_lock); 614 if (list_empty(&cp->rx_spare_list)) { 615 /* try to do a quick recovery */ 616 spin_unlock(&cp->rx_spare_lock); 617 cas_spare_recover(cp, GFP_ATOMIC); 618 spin_lock(&cp->rx_spare_lock); 619 if (list_empty(&cp->rx_spare_list)) { 620 netif_err(cp, rx_err, cp->dev, 621 "no spare buffers available\n"); 622 spin_unlock(&cp->rx_spare_lock); 623 return NULL; 624 } 625 } 626 627 entry = cp->rx_spare_list.next; 628 list_del(entry); 629 recover = ++cp->rx_spares_needed; 630 spin_unlock(&cp->rx_spare_lock); 631 632 /* trigger the timer to do the recovery */ 633 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) { 634 #if 1 635 atomic_inc(&cp->reset_task_pending); 636 atomic_inc(&cp->reset_task_pending_spare); 637 schedule_work(&cp->reset_task); 638 #else 639 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE); 640 schedule_work(&cp->reset_task); 641 #endif 642 } 643 return list_entry(entry, cas_page_t, list); 644 } 645 646 647 static void cas_mif_poll(struct cas *cp, const int enable) 648 { 649 u32 cfg; 650 651 cfg = readl(cp->regs + REG_MIF_CFG); 652 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1); 653 654 if (cp->phy_type & CAS_PHY_MII_MDIO1) 655 cfg |= MIF_CFG_PHY_SELECT; 656 657 /* poll and interrupt on link status change. */ 658 if (enable) { 659 cfg |= MIF_CFG_POLL_EN; 660 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR); 661 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr); 662 } 663 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, 664 cp->regs + REG_MIF_MASK); 665 writel(cfg, cp->regs + REG_MIF_CFG); 666 } 667 668 /* Must be invoked under cp->lock */ 669 static void cas_begin_auto_negotiation(struct cas *cp, 670 const struct ethtool_link_ksettings *ep) 671 { 672 u16 ctl; 673 #if 1 674 int lcntl; 675 int changed = 0; 676 int oldstate = cp->lstate; 677 int link_was_not_down = !(oldstate == link_down); 678 #endif 679 /* Setup link parameters */ 680 if (!ep) 681 goto start_aneg; 682 lcntl = cp->link_cntl; 683 if (ep->base.autoneg == AUTONEG_ENABLE) { 684 cp->link_cntl = BMCR_ANENABLE; 685 } else { 686 u32 speed = ep->base.speed; 687 cp->link_cntl = 0; 688 if (speed == SPEED_100) 689 cp->link_cntl |= BMCR_SPEED100; 690 else if (speed == SPEED_1000) 691 cp->link_cntl |= CAS_BMCR_SPEED1000; 692 if (ep->base.duplex == DUPLEX_FULL) 693 cp->link_cntl |= BMCR_FULLDPLX; 694 } 695 #if 1 696 changed = (lcntl != cp->link_cntl); 697 #endif 698 start_aneg: 699 if (cp->lstate == link_up) { 700 netdev_info(cp->dev, "PCS link down\n"); 701 } else { 702 if (changed) { 703 netdev_info(cp->dev, "link configuration changed\n"); 704 } 705 } 706 cp->lstate = link_down; 707 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 708 if (!cp->hw_running) 709 return; 710 #if 1 711 /* 712 * WTZ: If the old state was link_up, we turn off the carrier 713 * to replicate everything we do elsewhere on a link-down 714 * event when we were already in a link-up state.. 715 */ 716 if (oldstate == link_up) 717 netif_carrier_off(cp->dev); 718 if (changed && link_was_not_down) { 719 /* 720 * WTZ: This branch will simply schedule a full reset after 721 * we explicitly changed link modes in an ioctl. See if this 722 * fixes the link-problems we were having for forced mode. 723 */ 724 atomic_inc(&cp->reset_task_pending); 725 atomic_inc(&cp->reset_task_pending_all); 726 schedule_work(&cp->reset_task); 727 cp->timer_ticks = 0; 728 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 729 return; 730 } 731 #endif 732 if (cp->phy_type & CAS_PHY_SERDES) { 733 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); 734 735 if (cp->link_cntl & BMCR_ANENABLE) { 736 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN); 737 cp->lstate = link_aneg; 738 } else { 739 if (cp->link_cntl & BMCR_FULLDPLX) 740 val |= PCS_MII_CTRL_DUPLEX; 741 val &= ~PCS_MII_AUTONEG_EN; 742 cp->lstate = link_force_ok; 743 } 744 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 745 writel(val, cp->regs + REG_PCS_MII_CTRL); 746 747 } else { 748 cas_mif_poll(cp, 0); 749 ctl = cas_phy_read(cp, MII_BMCR); 750 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | 751 CAS_BMCR_SPEED1000 | BMCR_ANENABLE); 752 ctl |= cp->link_cntl; 753 if (ctl & BMCR_ANENABLE) { 754 ctl |= BMCR_ANRESTART; 755 cp->lstate = link_aneg; 756 } else { 757 cp->lstate = link_force_ok; 758 } 759 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 760 cas_phy_write(cp, MII_BMCR, ctl); 761 cas_mif_poll(cp, 1); 762 } 763 764 cp->timer_ticks = 0; 765 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 766 } 767 768 /* Must be invoked under cp->lock. */ 769 static int cas_reset_mii_phy(struct cas *cp) 770 { 771 int limit = STOP_TRIES_PHY; 772 u16 val; 773 774 cas_phy_write(cp, MII_BMCR, BMCR_RESET); 775 udelay(100); 776 while (--limit) { 777 val = cas_phy_read(cp, MII_BMCR); 778 if ((val & BMCR_RESET) == 0) 779 break; 780 udelay(10); 781 } 782 return limit <= 0; 783 } 784 785 static void cas_saturn_firmware_init(struct cas *cp) 786 { 787 const struct firmware *fw; 788 const char fw_name[] = "sun/cassini.bin"; 789 int err; 790 791 if (PHY_NS_DP83065 != cp->phy_id) 792 return; 793 794 err = request_firmware(&fw, fw_name, &cp->pdev->dev); 795 if (err) { 796 pr_err("Failed to load firmware \"%s\"\n", 797 fw_name); 798 return; 799 } 800 if (fw->size < 2) { 801 pr_err("bogus length %zu in \"%s\"\n", 802 fw->size, fw_name); 803 goto out; 804 } 805 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0]; 806 cp->fw_size = fw->size - 2; 807 cp->fw_data = vmalloc(cp->fw_size); 808 if (!cp->fw_data) 809 goto out; 810 memcpy(cp->fw_data, &fw->data[2], cp->fw_size); 811 out: 812 release_firmware(fw); 813 } 814 815 static void cas_saturn_firmware_load(struct cas *cp) 816 { 817 int i; 818 819 if (!cp->fw_data) 820 return; 821 822 cas_phy_powerdown(cp); 823 824 /* expanded memory access mode */ 825 cas_phy_write(cp, DP83065_MII_MEM, 0x0); 826 827 /* pointer configuration for new firmware */ 828 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9); 829 cas_phy_write(cp, DP83065_MII_REGD, 0xbd); 830 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa); 831 cas_phy_write(cp, DP83065_MII_REGD, 0x82); 832 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb); 833 cas_phy_write(cp, DP83065_MII_REGD, 0x0); 834 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc); 835 cas_phy_write(cp, DP83065_MII_REGD, 0x39); 836 837 /* download new firmware */ 838 cas_phy_write(cp, DP83065_MII_MEM, 0x1); 839 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr); 840 for (i = 0; i < cp->fw_size; i++) 841 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]); 842 843 /* enable firmware */ 844 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8); 845 cas_phy_write(cp, DP83065_MII_REGD, 0x1); 846 } 847 848 849 /* phy initialization */ 850 static void cas_phy_init(struct cas *cp) 851 { 852 u16 val; 853 854 /* if we're in MII/GMII mode, set up phy */ 855 if (CAS_PHY_MII(cp->phy_type)) { 856 writel(PCS_DATAPATH_MODE_MII, 857 cp->regs + REG_PCS_DATAPATH_MODE); 858 859 cas_mif_poll(cp, 0); 860 cas_reset_mii_phy(cp); /* take out of isolate mode */ 861 862 if (PHY_LUCENT_B0 == cp->phy_id) { 863 /* workaround link up/down issue with lucent */ 864 cas_phy_write(cp, LUCENT_MII_REG, 0x8000); 865 cas_phy_write(cp, MII_BMCR, 0x00f1); 866 cas_phy_write(cp, LUCENT_MII_REG, 0x0); 867 868 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) { 869 /* workarounds for broadcom phy */ 870 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20); 871 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012); 872 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804); 873 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013); 874 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204); 875 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 876 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132); 877 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 878 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232); 879 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F); 880 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20); 881 882 } else if (PHY_BROADCOM_5411 == cp->phy_id) { 883 val = cas_phy_read(cp, BROADCOM_MII_REG4); 884 val = cas_phy_read(cp, BROADCOM_MII_REG4); 885 if (val & 0x0080) { 886 /* link workaround */ 887 cas_phy_write(cp, BROADCOM_MII_REG4, 888 val & ~0x0080); 889 } 890 891 } else if (cp->cas_flags & CAS_FLAG_SATURN) { 892 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? 893 SATURN_PCFG_FSI : 0x0, 894 cp->regs + REG_SATURN_PCFG); 895 896 /* load firmware to address 10Mbps auto-negotiation 897 * issue. NOTE: this will need to be changed if the 898 * default firmware gets fixed. 899 */ 900 if (PHY_NS_DP83065 == cp->phy_id) { 901 cas_saturn_firmware_load(cp); 902 } 903 cas_phy_powerup(cp); 904 } 905 906 /* advertise capabilities */ 907 val = cas_phy_read(cp, MII_BMCR); 908 val &= ~BMCR_ANENABLE; 909 cas_phy_write(cp, MII_BMCR, val); 910 udelay(10); 911 912 cas_phy_write(cp, MII_ADVERTISE, 913 cas_phy_read(cp, MII_ADVERTISE) | 914 (ADVERTISE_10HALF | ADVERTISE_10FULL | 915 ADVERTISE_100HALF | ADVERTISE_100FULL | 916 CAS_ADVERTISE_PAUSE | 917 CAS_ADVERTISE_ASYM_PAUSE)); 918 919 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 920 /* make sure that we don't advertise half 921 * duplex to avoid a chip issue 922 */ 923 val = cas_phy_read(cp, CAS_MII_1000_CTRL); 924 val &= ~CAS_ADVERTISE_1000HALF; 925 val |= CAS_ADVERTISE_1000FULL; 926 cas_phy_write(cp, CAS_MII_1000_CTRL, val); 927 } 928 929 } else { 930 /* reset pcs for serdes */ 931 u32 val; 932 int limit; 933 934 writel(PCS_DATAPATH_MODE_SERDES, 935 cp->regs + REG_PCS_DATAPATH_MODE); 936 937 /* enable serdes pins on saturn */ 938 if (cp->cas_flags & CAS_FLAG_SATURN) 939 writel(0, cp->regs + REG_SATURN_PCFG); 940 941 /* Reset PCS unit. */ 942 val = readl(cp->regs + REG_PCS_MII_CTRL); 943 val |= PCS_MII_RESET; 944 writel(val, cp->regs + REG_PCS_MII_CTRL); 945 946 limit = STOP_TRIES; 947 while (--limit > 0) { 948 udelay(10); 949 if ((readl(cp->regs + REG_PCS_MII_CTRL) & 950 PCS_MII_RESET) == 0) 951 break; 952 } 953 if (limit <= 0) 954 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n", 955 readl(cp->regs + REG_PCS_STATE_MACHINE)); 956 957 /* Make sure PCS is disabled while changing advertisement 958 * configuration. 959 */ 960 writel(0x0, cp->regs + REG_PCS_CFG); 961 962 /* Advertise all capabilities except half-duplex. */ 963 val = readl(cp->regs + REG_PCS_MII_ADVERT); 964 val &= ~PCS_MII_ADVERT_HD; 965 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | 966 PCS_MII_ADVERT_ASYM_PAUSE); 967 writel(val, cp->regs + REG_PCS_MII_ADVERT); 968 969 /* enable PCS */ 970 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); 971 972 /* pcs workaround: enable sync detect */ 973 writel(PCS_SERDES_CTRL_SYNCD_EN, 974 cp->regs + REG_PCS_SERDES_CTRL); 975 } 976 } 977 978 979 static int cas_pcs_link_check(struct cas *cp) 980 { 981 u32 stat, state_machine; 982 int retval = 0; 983 984 /* The link status bit latches on zero, so you must 985 * read it twice in such a case to see a transition 986 * to the link being up. 987 */ 988 stat = readl(cp->regs + REG_PCS_MII_STATUS); 989 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0) 990 stat = readl(cp->regs + REG_PCS_MII_STATUS); 991 992 /* The remote-fault indication is only valid 993 * when autoneg has completed. 994 */ 995 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP | 996 PCS_MII_STATUS_REMOTE_FAULT)) == 997 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) 998 netif_info(cp, link, cp->dev, "PCS RemoteFault\n"); 999 1000 /* work around link detection issue by querying the PCS state 1001 * machine directly. 1002 */ 1003 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); 1004 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) { 1005 stat &= ~PCS_MII_STATUS_LINK_STATUS; 1006 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) { 1007 stat |= PCS_MII_STATUS_LINK_STATUS; 1008 } 1009 1010 if (stat & PCS_MII_STATUS_LINK_STATUS) { 1011 if (cp->lstate != link_up) { 1012 if (cp->opened) { 1013 cp->lstate = link_up; 1014 cp->link_transition = LINK_TRANSITION_LINK_UP; 1015 1016 cas_set_link_modes(cp); 1017 netif_carrier_on(cp->dev); 1018 } 1019 } 1020 } else if (cp->lstate == link_up) { 1021 cp->lstate = link_down; 1022 if (link_transition_timeout != 0 && 1023 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1024 !cp->link_transition_jiffies_valid) { 1025 /* 1026 * force a reset, as a workaround for the 1027 * link-failure problem. May want to move this to a 1028 * point a bit earlier in the sequence. If we had 1029 * generated a reset a short time ago, we'll wait for 1030 * the link timer to check the status until a 1031 * timer expires (link_transistion_jiffies_valid is 1032 * true when the timer is running.) Instead of using 1033 * a system timer, we just do a check whenever the 1034 * link timer is running - this clears the flag after 1035 * a suitable delay. 1036 */ 1037 retval = 1; 1038 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1039 cp->link_transition_jiffies = jiffies; 1040 cp->link_transition_jiffies_valid = 1; 1041 } else { 1042 cp->link_transition = LINK_TRANSITION_ON_FAILURE; 1043 } 1044 netif_carrier_off(cp->dev); 1045 if (cp->opened) 1046 netif_info(cp, link, cp->dev, "PCS link down\n"); 1047 1048 /* Cassini only: if you force a mode, there can be 1049 * sync problems on link down. to fix that, the following 1050 * things need to be checked: 1051 * 1) read serialink state register 1052 * 2) read pcs status register to verify link down. 1053 * 3) if link down and serial link == 0x03, then you need 1054 * to global reset the chip. 1055 */ 1056 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) { 1057 /* should check to see if we're in a forced mode */ 1058 stat = readl(cp->regs + REG_PCS_SERDES_STATE); 1059 if (stat == 0x03) 1060 return 1; 1061 } 1062 } else if (cp->lstate == link_down) { 1063 if (link_transition_timeout != 0 && 1064 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1065 !cp->link_transition_jiffies_valid) { 1066 /* force a reset, as a workaround for the 1067 * link-failure problem. May want to move 1068 * this to a point a bit earlier in the 1069 * sequence. 1070 */ 1071 retval = 1; 1072 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1073 cp->link_transition_jiffies = jiffies; 1074 cp->link_transition_jiffies_valid = 1; 1075 } else { 1076 cp->link_transition = LINK_TRANSITION_STILL_FAILED; 1077 } 1078 } 1079 1080 return retval; 1081 } 1082 1083 static int cas_pcs_interrupt(struct net_device *dev, 1084 struct cas *cp, u32 status) 1085 { 1086 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); 1087 1088 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) 1089 return 0; 1090 return cas_pcs_link_check(cp); 1091 } 1092 1093 static int cas_txmac_interrupt(struct net_device *dev, 1094 struct cas *cp, u32 status) 1095 { 1096 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); 1097 1098 if (!txmac_stat) 1099 return 0; 1100 1101 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1102 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat); 1103 1104 /* Defer timer expiration is quite normal, 1105 * don't even log the event. 1106 */ 1107 if ((txmac_stat & MAC_TX_DEFER_TIMER) && 1108 !(txmac_stat & ~MAC_TX_DEFER_TIMER)) 1109 return 0; 1110 1111 spin_lock(&cp->stat_lock[0]); 1112 if (txmac_stat & MAC_TX_UNDERRUN) { 1113 netdev_err(dev, "TX MAC xmit underrun\n"); 1114 cp->net_stats[0].tx_fifo_errors++; 1115 } 1116 1117 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) { 1118 netdev_err(dev, "TX MAC max packet size error\n"); 1119 cp->net_stats[0].tx_errors++; 1120 } 1121 1122 /* The rest are all cases of one of the 16-bit TX 1123 * counters expiring. 1124 */ 1125 if (txmac_stat & MAC_TX_COLL_NORMAL) 1126 cp->net_stats[0].collisions += 0x10000; 1127 1128 if (txmac_stat & MAC_TX_COLL_EXCESS) { 1129 cp->net_stats[0].tx_aborted_errors += 0x10000; 1130 cp->net_stats[0].collisions += 0x10000; 1131 } 1132 1133 if (txmac_stat & MAC_TX_COLL_LATE) { 1134 cp->net_stats[0].tx_aborted_errors += 0x10000; 1135 cp->net_stats[0].collisions += 0x10000; 1136 } 1137 spin_unlock(&cp->stat_lock[0]); 1138 1139 /* We do not keep track of MAC_TX_COLL_FIRST and 1140 * MAC_TX_PEAK_ATTEMPTS events. 1141 */ 1142 return 0; 1143 } 1144 1145 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) 1146 { 1147 cas_hp_inst_t *inst; 1148 u32 val; 1149 int i; 1150 1151 i = 0; 1152 while ((inst = firmware) && inst->note) { 1153 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); 1154 1155 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); 1156 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); 1157 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); 1158 1159 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); 1160 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); 1161 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); 1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); 1163 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); 1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); 1165 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); 1166 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); 1167 1168 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); 1169 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); 1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); 1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); 1172 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); 1173 ++firmware; 1174 ++i; 1175 } 1176 } 1177 1178 static void cas_init_rx_dma(struct cas *cp) 1179 { 1180 u64 desc_dma = cp->block_dvma; 1181 u32 val; 1182 int i, size; 1183 1184 /* rx free descriptors */ 1185 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); 1186 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0)); 1187 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0)); 1188 if ((N_RX_DESC_RINGS > 1) && 1189 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */ 1190 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1)); 1191 writel(val, cp->regs + REG_RX_CFG); 1192 1193 val = (unsigned long) cp->init_rxds[0] - 1194 (unsigned long) cp->init_block; 1195 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); 1196 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); 1197 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 1198 1199 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1200 /* rx desc 2 is for IPSEC packets. however, 1201 * we don't it that for that purpose. 1202 */ 1203 val = (unsigned long) cp->init_rxds[1] - 1204 (unsigned long) cp->init_block; 1205 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); 1206 writel((desc_dma + val) & 0xffffffff, cp->regs + 1207 REG_PLUS_RX_DB1_LOW); 1208 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + 1209 REG_PLUS_RX_KICK1); 1210 } 1211 1212 /* rx completion registers */ 1213 val = (unsigned long) cp->init_rxcs[0] - 1214 (unsigned long) cp->init_block; 1215 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); 1216 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); 1217 1218 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1219 /* rx comp 2-4 */ 1220 for (i = 1; i < MAX_RX_COMP_RINGS; i++) { 1221 val = (unsigned long) cp->init_rxcs[i] - 1222 (unsigned long) cp->init_block; 1223 writel((desc_dma + val) >> 32, cp->regs + 1224 REG_PLUS_RX_CBN_HI(i)); 1225 writel((desc_dma + val) & 0xffffffff, cp->regs + 1226 REG_PLUS_RX_CBN_LOW(i)); 1227 } 1228 } 1229 1230 /* read selective clear regs to prevent spurious interrupts 1231 * on reset because complete == kick. 1232 * selective clear set up to prevent interrupts on resets 1233 */ 1234 readl(cp->regs + REG_INTR_STATUS_ALIAS); 1235 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); 1236 1237 /* set up pause thresholds */ 1238 val = CAS_BASE(RX_PAUSE_THRESH_OFF, 1239 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM); 1240 val |= CAS_BASE(RX_PAUSE_THRESH_ON, 1241 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM); 1242 writel(val, cp->regs + REG_RX_PAUSE_THRESH); 1243 1244 /* zero out dma reassembly buffers */ 1245 for (i = 0; i < 64; i++) { 1246 writel(i, cp->regs + REG_RX_TABLE_ADDR); 1247 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); 1248 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); 1249 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); 1250 } 1251 1252 /* make sure address register is 0 for normal operation */ 1253 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); 1254 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); 1255 1256 /* interrupt mitigation */ 1257 #ifdef USE_RX_BLANK 1258 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL); 1259 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL); 1260 writel(val, cp->regs + REG_RX_BLANK); 1261 #else 1262 writel(0x0, cp->regs + REG_RX_BLANK); 1263 #endif 1264 1265 /* interrupt generation as a function of low water marks for 1266 * free desc and completion entries. these are used to trigger 1267 * housekeeping for rx descs. we don't use the free interrupt 1268 * as it's not very useful 1269 */ 1270 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */ 1271 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL); 1272 writel(val, cp->regs + REG_RX_AE_THRESH); 1273 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1274 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1)); 1275 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); 1276 } 1277 1278 /* Random early detect registers. useful for congestion avoidance. 1279 * this should be tunable. 1280 */ 1281 writel(0x0, cp->regs + REG_RX_RED); 1282 1283 /* receive page sizes. default == 2K (0x800) */ 1284 val = 0; 1285 if (cp->page_size == 0x1000) 1286 val = 0x1; 1287 else if (cp->page_size == 0x2000) 1288 val = 0x2; 1289 else if (cp->page_size == 0x4000) 1290 val = 0x3; 1291 1292 /* round mtu + offset. constrain to page size. */ 1293 size = cp->dev->mtu + 64; 1294 if (size > cp->page_size) 1295 size = cp->page_size; 1296 1297 if (size <= 0x400) 1298 i = 0x0; 1299 else if (size <= 0x800) 1300 i = 0x1; 1301 else if (size <= 0x1000) 1302 i = 0x2; 1303 else 1304 i = 0x3; 1305 1306 cp->mtu_stride = 1 << (i + 10); 1307 val = CAS_BASE(RX_PAGE_SIZE, val); 1308 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); 1309 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); 1310 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1); 1311 writel(val, cp->regs + REG_RX_PAGE_SIZE); 1312 1313 /* enable the header parser if desired */ 1314 if (&CAS_HP_FIRMWARE[0] == &cas_prog_null[0]) 1315 return; 1316 1317 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); 1318 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK; 1319 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL); 1320 writel(val, cp->regs + REG_HP_CFG); 1321 } 1322 1323 static inline void cas_rxc_init(struct cas_rx_comp *rxc) 1324 { 1325 memset(rxc, 0, sizeof(*rxc)); 1326 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); 1327 } 1328 1329 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1] 1330 * flipping is protected by the fact that the chip will not 1331 * hand back the same page index while it's being processed. 1332 */ 1333 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index) 1334 { 1335 cas_page_t *page = cp->rx_pages[1][index]; 1336 cas_page_t *new; 1337 1338 if (page_count(page->buffer) == 1) 1339 return page; 1340 1341 new = cas_page_dequeue(cp); 1342 if (new) { 1343 spin_lock(&cp->rx_inuse_lock); 1344 list_add(&page->list, &cp->rx_inuse_list); 1345 spin_unlock(&cp->rx_inuse_lock); 1346 } 1347 return new; 1348 } 1349 1350 /* this needs to be changed if we actually use the ENC RX DESC ring */ 1351 static cas_page_t *cas_page_swap(struct cas *cp, const int ring, 1352 const int index) 1353 { 1354 cas_page_t **page0 = cp->rx_pages[0]; 1355 cas_page_t **page1 = cp->rx_pages[1]; 1356 1357 /* swap if buffer is in use */ 1358 if (page_count(page0[index]->buffer) > 1) { 1359 cas_page_t *new = cas_page_spare(cp, index); 1360 if (new) { 1361 page1[index] = page0[index]; 1362 page0[index] = new; 1363 } 1364 } 1365 RX_USED_SET(page0[index], 0); 1366 return page0[index]; 1367 } 1368 1369 static void cas_clean_rxds(struct cas *cp) 1370 { 1371 /* only clean ring 0 as ring 1 is used for spare buffers */ 1372 struct cas_rx_desc *rxd = cp->init_rxds[0]; 1373 int i, size; 1374 1375 /* release all rx flows */ 1376 for (i = 0; i < N_RX_FLOWS; i++) { 1377 struct sk_buff *skb; 1378 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) { 1379 cas_skb_release(skb); 1380 } 1381 } 1382 1383 /* initialize descriptors */ 1384 size = RX_DESC_RINGN_SIZE(0); 1385 for (i = 0; i < size; i++) { 1386 cas_page_t *page = cas_page_swap(cp, 0, i); 1387 rxd[i].buffer = cpu_to_le64(page->dma_addr); 1388 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | 1389 CAS_BASE(RX_INDEX_RING, 0)); 1390 } 1391 1392 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4; 1393 cp->rx_last[0] = 0; 1394 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0); 1395 } 1396 1397 static void cas_clean_rxcs(struct cas *cp) 1398 { 1399 int i, j; 1400 1401 /* take ownership of rx comp descriptors */ 1402 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS); 1403 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS); 1404 for (i = 0; i < N_RX_COMP_RINGS; i++) { 1405 struct cas_rx_comp *rxc = cp->init_rxcs[i]; 1406 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) { 1407 cas_rxc_init(rxc + j); 1408 } 1409 } 1410 } 1411 1412 #if 0 1413 /* When we get a RX fifo overflow, the RX unit is probably hung 1414 * so we do the following. 1415 * 1416 * If any part of the reset goes wrong, we return 1 and that causes the 1417 * whole chip to be reset. 1418 */ 1419 static int cas_rxmac_reset(struct cas *cp) 1420 { 1421 struct net_device *dev = cp->dev; 1422 int limit; 1423 u32 val; 1424 1425 /* First, reset MAC RX. */ 1426 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 1427 for (limit = 0; limit < STOP_TRIES; limit++) { 1428 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN)) 1429 break; 1430 udelay(10); 1431 } 1432 if (limit == STOP_TRIES) { 1433 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n"); 1434 return 1; 1435 } 1436 1437 /* Second, disable RX DMA. */ 1438 writel(0, cp->regs + REG_RX_CFG); 1439 for (limit = 0; limit < STOP_TRIES; limit++) { 1440 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN)) 1441 break; 1442 udelay(10); 1443 } 1444 if (limit == STOP_TRIES) { 1445 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n"); 1446 return 1; 1447 } 1448 1449 mdelay(5); 1450 1451 /* Execute RX reset command. */ 1452 writel(SW_RESET_RX, cp->regs + REG_SW_RESET); 1453 for (limit = 0; limit < STOP_TRIES; limit++) { 1454 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX)) 1455 break; 1456 udelay(10); 1457 } 1458 if (limit == STOP_TRIES) { 1459 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n"); 1460 return 1; 1461 } 1462 1463 /* reset driver rx state */ 1464 cas_clean_rxds(cp); 1465 cas_clean_rxcs(cp); 1466 1467 /* Now, reprogram the rest of RX unit. */ 1468 cas_init_rx_dma(cp); 1469 1470 /* re-enable */ 1471 val = readl(cp->regs + REG_RX_CFG); 1472 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG); 1473 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); 1474 val = readl(cp->regs + REG_MAC_RX_CFG); 1475 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 1476 return 0; 1477 } 1478 #endif 1479 1480 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp, 1481 u32 status) 1482 { 1483 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); 1484 1485 if (!stat) 1486 return 0; 1487 1488 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat); 1489 1490 /* these are all rollovers */ 1491 spin_lock(&cp->stat_lock[0]); 1492 if (stat & MAC_RX_ALIGN_ERR) 1493 cp->net_stats[0].rx_frame_errors += 0x10000; 1494 1495 if (stat & MAC_RX_CRC_ERR) 1496 cp->net_stats[0].rx_crc_errors += 0x10000; 1497 1498 if (stat & MAC_RX_LEN_ERR) 1499 cp->net_stats[0].rx_length_errors += 0x10000; 1500 1501 if (stat & MAC_RX_OVERFLOW) { 1502 cp->net_stats[0].rx_over_errors++; 1503 cp->net_stats[0].rx_fifo_errors++; 1504 } 1505 1506 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR 1507 * events. 1508 */ 1509 spin_unlock(&cp->stat_lock[0]); 1510 return 0; 1511 } 1512 1513 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp, 1514 u32 status) 1515 { 1516 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); 1517 1518 if (!stat) 1519 return 0; 1520 1521 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1522 "mac interrupt, stat: 0x%x\n", stat); 1523 1524 /* This interrupt is just for pause frame and pause 1525 * tracking. It is useful for diagnostics and debug 1526 * but probably by default we will mask these events. 1527 */ 1528 if (stat & MAC_CTRL_PAUSE_STATE) 1529 cp->pause_entered++; 1530 1531 if (stat & MAC_CTRL_PAUSE_RECEIVED) 1532 cp->pause_last_time_recvd = (stat >> 16); 1533 1534 return 0; 1535 } 1536 1537 1538 /* Must be invoked under cp->lock. */ 1539 static inline int cas_mdio_link_not_up(struct cas *cp) 1540 { 1541 u16 val; 1542 1543 switch (cp->lstate) { 1544 case link_force_ret: 1545 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n"); 1546 cas_phy_write(cp, MII_BMCR, cp->link_fcntl); 1547 cp->timer_ticks = 5; 1548 cp->lstate = link_force_ok; 1549 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1550 break; 1551 1552 case link_aneg: 1553 val = cas_phy_read(cp, MII_BMCR); 1554 1555 /* Try forced modes. we try things in the following order: 1556 * 1000 full -> 100 full/half -> 10 half 1557 */ 1558 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE); 1559 val |= BMCR_FULLDPLX; 1560 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 1561 CAS_BMCR_SPEED1000 : BMCR_SPEED100; 1562 cas_phy_write(cp, MII_BMCR, val); 1563 cp->timer_ticks = 5; 1564 cp->lstate = link_force_try; 1565 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1566 break; 1567 1568 case link_force_try: 1569 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */ 1570 val = cas_phy_read(cp, MII_BMCR); 1571 cp->timer_ticks = 5; 1572 if (val & CAS_BMCR_SPEED1000) { /* gigabit */ 1573 val &= ~CAS_BMCR_SPEED1000; 1574 val |= (BMCR_SPEED100 | BMCR_FULLDPLX); 1575 cas_phy_write(cp, MII_BMCR, val); 1576 break; 1577 } 1578 1579 if (val & BMCR_SPEED100) { 1580 if (val & BMCR_FULLDPLX) /* fd failed */ 1581 val &= ~BMCR_FULLDPLX; 1582 else { /* 100Mbps failed */ 1583 val &= ~BMCR_SPEED100; 1584 } 1585 cas_phy_write(cp, MII_BMCR, val); 1586 break; 1587 } 1588 break; 1589 default: 1590 break; 1591 } 1592 return 0; 1593 } 1594 1595 1596 /* must be invoked with cp->lock held */ 1597 static int cas_mii_link_check(struct cas *cp, const u16 bmsr) 1598 { 1599 int restart; 1600 1601 if (bmsr & BMSR_LSTATUS) { 1602 /* Ok, here we got a link. If we had it due to a forced 1603 * fallback, and we were configured for autoneg, we 1604 * retry a short autoneg pass. If you know your hub is 1605 * broken, use ethtool ;) 1606 */ 1607 if ((cp->lstate == link_force_try) && 1608 (cp->link_cntl & BMCR_ANENABLE)) { 1609 cp->lstate = link_force_ret; 1610 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1611 cas_mif_poll(cp, 0); 1612 cp->link_fcntl = cas_phy_read(cp, MII_BMCR); 1613 cp->timer_ticks = 5; 1614 if (cp->opened) 1615 netif_info(cp, link, cp->dev, 1616 "Got link after fallback, retrying autoneg once...\n"); 1617 cas_phy_write(cp, MII_BMCR, 1618 cp->link_fcntl | BMCR_ANENABLE | 1619 BMCR_ANRESTART); 1620 cas_mif_poll(cp, 1); 1621 1622 } else if (cp->lstate != link_up) { 1623 cp->lstate = link_up; 1624 cp->link_transition = LINK_TRANSITION_LINK_UP; 1625 1626 if (cp->opened) { 1627 cas_set_link_modes(cp); 1628 netif_carrier_on(cp->dev); 1629 } 1630 } 1631 return 0; 1632 } 1633 1634 /* link not up. if the link was previously up, we restart the 1635 * whole process 1636 */ 1637 restart = 0; 1638 if (cp->lstate == link_up) { 1639 cp->lstate = link_down; 1640 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 1641 1642 netif_carrier_off(cp->dev); 1643 if (cp->opened) 1644 netif_info(cp, link, cp->dev, "Link down\n"); 1645 restart = 1; 1646 1647 } else if (++cp->timer_ticks > 10) 1648 cas_mdio_link_not_up(cp); 1649 1650 return restart; 1651 } 1652 1653 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp, 1654 u32 status) 1655 { 1656 u32 stat = readl(cp->regs + REG_MIF_STATUS); 1657 u16 bmsr; 1658 1659 /* check for a link change */ 1660 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0) 1661 return 0; 1662 1663 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat); 1664 return cas_mii_link_check(cp, bmsr); 1665 } 1666 1667 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp, 1668 u32 status) 1669 { 1670 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); 1671 1672 if (!stat) 1673 return 0; 1674 1675 netdev_err(dev, "PCI error [%04x:%04x]", 1676 stat, readl(cp->regs + REG_BIM_DIAG)); 1677 1678 /* cassini+ has this reserved */ 1679 if ((stat & PCI_ERR_BADACK) && 1680 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0)) 1681 pr_cont(" <No ACK64# during ABS64 cycle>"); 1682 1683 if (stat & PCI_ERR_DTRTO) 1684 pr_cont(" <Delayed transaction timeout>"); 1685 if (stat & PCI_ERR_OTHER) 1686 pr_cont(" <other>"); 1687 if (stat & PCI_ERR_BIM_DMA_WRITE) 1688 pr_cont(" <BIM DMA 0 write req>"); 1689 if (stat & PCI_ERR_BIM_DMA_READ) 1690 pr_cont(" <BIM DMA 0 read req>"); 1691 pr_cont("\n"); 1692 1693 if (stat & PCI_ERR_OTHER) { 1694 int pci_errs; 1695 1696 /* Interrogate PCI config space for the 1697 * true cause. 1698 */ 1699 pci_errs = pci_status_get_and_clear_errors(cp->pdev); 1700 1701 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs); 1702 if (pci_errs & PCI_STATUS_PARITY) 1703 netdev_err(dev, "PCI parity error detected\n"); 1704 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT) 1705 netdev_err(dev, "PCI target abort\n"); 1706 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT) 1707 netdev_err(dev, "PCI master acks target abort\n"); 1708 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT) 1709 netdev_err(dev, "PCI master abort\n"); 1710 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR) 1711 netdev_err(dev, "PCI system error SERR#\n"); 1712 if (pci_errs & PCI_STATUS_DETECTED_PARITY) 1713 netdev_err(dev, "PCI parity error\n"); 1714 } 1715 1716 /* For all PCI errors, we should reset the chip. */ 1717 return 1; 1718 } 1719 1720 /* All non-normal interrupt conditions get serviced here. 1721 * Returns non-zero if we should just exit the interrupt 1722 * handler right now (ie. if we reset the card which invalidates 1723 * all of the other original irq status bits). 1724 */ 1725 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp, 1726 u32 status) 1727 { 1728 if (status & INTR_RX_TAG_ERROR) { 1729 /* corrupt RX tag framing */ 1730 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1731 "corrupt rx tag framing\n"); 1732 spin_lock(&cp->stat_lock[0]); 1733 cp->net_stats[0].rx_errors++; 1734 spin_unlock(&cp->stat_lock[0]); 1735 goto do_reset; 1736 } 1737 1738 if (status & INTR_RX_LEN_MISMATCH) { 1739 /* length mismatch. */ 1740 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1741 "length mismatch for rx frame\n"); 1742 spin_lock(&cp->stat_lock[0]); 1743 cp->net_stats[0].rx_errors++; 1744 spin_unlock(&cp->stat_lock[0]); 1745 goto do_reset; 1746 } 1747 1748 if (status & INTR_PCS_STATUS) { 1749 if (cas_pcs_interrupt(dev, cp, status)) 1750 goto do_reset; 1751 } 1752 1753 if (status & INTR_TX_MAC_STATUS) { 1754 if (cas_txmac_interrupt(dev, cp, status)) 1755 goto do_reset; 1756 } 1757 1758 if (status & INTR_RX_MAC_STATUS) { 1759 if (cas_rxmac_interrupt(dev, cp, status)) 1760 goto do_reset; 1761 } 1762 1763 if (status & INTR_MAC_CTRL_STATUS) { 1764 if (cas_mac_interrupt(dev, cp, status)) 1765 goto do_reset; 1766 } 1767 1768 if (status & INTR_MIF_STATUS) { 1769 if (cas_mif_interrupt(dev, cp, status)) 1770 goto do_reset; 1771 } 1772 1773 if (status & INTR_PCI_ERROR_STATUS) { 1774 if (cas_pci_interrupt(dev, cp, status)) 1775 goto do_reset; 1776 } 1777 return 0; 1778 1779 do_reset: 1780 #if 1 1781 atomic_inc(&cp->reset_task_pending); 1782 atomic_inc(&cp->reset_task_pending_all); 1783 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status); 1784 schedule_work(&cp->reset_task); 1785 #else 1786 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 1787 netdev_err(dev, "reset called in cas_abnormal_irq\n"); 1788 schedule_work(&cp->reset_task); 1789 #endif 1790 return 1; 1791 } 1792 1793 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when 1794 * determining whether to do a netif_stop/wakeup 1795 */ 1796 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1) 1797 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK) 1798 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr, 1799 const int len) 1800 { 1801 unsigned long off = addr + len; 1802 1803 if (CAS_TABORT(cp) == 1) 1804 return 0; 1805 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN) 1806 return 0; 1807 return TX_TARGET_ABORT_LEN; 1808 } 1809 1810 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit) 1811 { 1812 struct cas_tx_desc *txds; 1813 struct sk_buff **skbs; 1814 struct net_device *dev = cp->dev; 1815 int entry, count; 1816 1817 spin_lock(&cp->tx_lock[ring]); 1818 txds = cp->init_txds[ring]; 1819 skbs = cp->tx_skbs[ring]; 1820 entry = cp->tx_old[ring]; 1821 1822 count = TX_BUFF_COUNT(ring, entry, limit); 1823 while (entry != limit) { 1824 struct sk_buff *skb = skbs[entry]; 1825 dma_addr_t daddr; 1826 u32 dlen; 1827 int frag; 1828 1829 if (!skb) { 1830 /* this should never occur */ 1831 entry = TX_DESC_NEXT(ring, entry); 1832 continue; 1833 } 1834 1835 /* however, we might get only a partial skb release. */ 1836 count -= skb_shinfo(skb)->nr_frags + 1837 + cp->tx_tiny_use[ring][entry].nbufs + 1; 1838 if (count < 0) 1839 break; 1840 1841 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev, 1842 "tx[%d] done, slot %d\n", ring, entry); 1843 1844 skbs[entry] = NULL; 1845 cp->tx_tiny_use[ring][entry].nbufs = 0; 1846 1847 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1848 struct cas_tx_desc *txd = txds + entry; 1849 1850 daddr = le64_to_cpu(txd->buffer); 1851 dlen = CAS_VAL(TX_DESC_BUFLEN, 1852 le64_to_cpu(txd->control)); 1853 dma_unmap_page(&cp->pdev->dev, daddr, dlen, 1854 DMA_TO_DEVICE); 1855 entry = TX_DESC_NEXT(ring, entry); 1856 1857 /* tiny buffer may follow */ 1858 if (cp->tx_tiny_use[ring][entry].used) { 1859 cp->tx_tiny_use[ring][entry].used = 0; 1860 entry = TX_DESC_NEXT(ring, entry); 1861 } 1862 } 1863 1864 spin_lock(&cp->stat_lock[ring]); 1865 cp->net_stats[ring].tx_packets++; 1866 cp->net_stats[ring].tx_bytes += skb->len; 1867 spin_unlock(&cp->stat_lock[ring]); 1868 dev_consume_skb_irq(skb); 1869 } 1870 cp->tx_old[ring] = entry; 1871 1872 /* this is wrong for multiple tx rings. the net device needs 1873 * multiple queues for this to do the right thing. we wait 1874 * for 2*packets to be available when using tiny buffers 1875 */ 1876 if (netif_queue_stopped(dev) && 1877 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))) 1878 netif_wake_queue(dev); 1879 spin_unlock(&cp->tx_lock[ring]); 1880 } 1881 1882 static void cas_tx(struct net_device *dev, struct cas *cp, 1883 u32 status) 1884 { 1885 int limit, ring; 1886 #ifdef USE_TX_COMPWB 1887 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb); 1888 #endif 1889 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1890 "tx interrupt, status: 0x%x, %llx\n", 1891 status, (unsigned long long)compwb); 1892 /* process all the rings */ 1893 for (ring = 0; ring < N_TX_RINGS; ring++) { 1894 #ifdef USE_TX_COMPWB 1895 /* use the completion writeback registers */ 1896 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) | 1897 CAS_VAL(TX_COMPWB_LSB, compwb); 1898 compwb = TX_COMPWB_NEXT(compwb); 1899 #else 1900 limit = readl(cp->regs + REG_TX_COMPN(ring)); 1901 #endif 1902 if (cp->tx_old[ring] != limit) 1903 cas_tx_ringN(cp, ring, limit); 1904 } 1905 } 1906 1907 1908 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, 1909 int entry, const u64 *words, 1910 struct sk_buff **skbref) 1911 { 1912 int dlen, hlen, len, i, alloclen; 1913 int off, swivel = RX_SWIVEL_OFF_VAL; 1914 struct cas_page *page; 1915 struct sk_buff *skb; 1916 void *crcaddr; 1917 __sum16 csum; 1918 char *p; 1919 1920 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]); 1921 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]); 1922 len = hlen + dlen; 1923 1924 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) 1925 alloclen = len; 1926 else 1927 alloclen = max(hlen, RX_COPY_MIN); 1928 1929 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size); 1930 if (skb == NULL) 1931 return -1; 1932 1933 *skbref = skb; 1934 skb_reserve(skb, swivel); 1935 1936 p = skb->data; 1937 crcaddr = NULL; 1938 if (hlen) { /* always copy header pages */ 1939 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 1940 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1941 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + 1942 swivel; 1943 1944 i = hlen; 1945 if (!dlen) /* attach FCS */ 1946 i += cp->crc_size; 1947 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 1948 i, DMA_FROM_DEVICE); 1949 memcpy(p, page_address(page->buffer) + off, i); 1950 dma_sync_single_for_device(&cp->pdev->dev, 1951 page->dma_addr + off, i, 1952 DMA_FROM_DEVICE); 1953 RX_USED_ADD(page, 0x100); 1954 p += hlen; 1955 swivel = 0; 1956 } 1957 1958 1959 if (alloclen < (hlen + dlen)) { 1960 skb_frag_t *frag = skb_shinfo(skb)->frags; 1961 1962 /* normal or jumbo packets. we use frags */ 1963 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 1964 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1965 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 1966 1967 hlen = min(cp->page_size - off, dlen); 1968 if (hlen < 0) { 1969 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1970 "rx page overflow: %d\n", hlen); 1971 dev_kfree_skb_irq(skb); 1972 return -1; 1973 } 1974 i = hlen; 1975 if (i == dlen) /* attach FCS */ 1976 i += cp->crc_size; 1977 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 1978 i, DMA_FROM_DEVICE); 1979 1980 /* make sure we always copy a header */ 1981 swivel = 0; 1982 if (p == (char *) skb->data) { /* not split */ 1983 memcpy(p, page_address(page->buffer) + off, 1984 RX_COPY_MIN); 1985 dma_sync_single_for_device(&cp->pdev->dev, 1986 page->dma_addr + off, i, 1987 DMA_FROM_DEVICE); 1988 off += RX_COPY_MIN; 1989 swivel = RX_COPY_MIN; 1990 RX_USED_ADD(page, cp->mtu_stride); 1991 } else { 1992 RX_USED_ADD(page, hlen); 1993 } 1994 skb_put(skb, alloclen); 1995 1996 skb_shinfo(skb)->nr_frags++; 1997 skb->data_len += hlen - swivel; 1998 skb->truesize += hlen - swivel; 1999 skb->len += hlen - swivel; 2000 2001 __skb_frag_set_page(frag, page->buffer); 2002 __skb_frag_ref(frag); 2003 skb_frag_off_set(frag, off); 2004 skb_frag_size_set(frag, hlen - swivel); 2005 2006 /* any more data? */ 2007 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 2008 hlen = dlen; 2009 off = 0; 2010 2011 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2012 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2013 dma_sync_single_for_cpu(&cp->pdev->dev, 2014 page->dma_addr, 2015 hlen + cp->crc_size, 2016 DMA_FROM_DEVICE); 2017 dma_sync_single_for_device(&cp->pdev->dev, 2018 page->dma_addr, 2019 hlen + cp->crc_size, 2020 DMA_FROM_DEVICE); 2021 2022 skb_shinfo(skb)->nr_frags++; 2023 skb->data_len += hlen; 2024 skb->len += hlen; 2025 frag++; 2026 2027 __skb_frag_set_page(frag, page->buffer); 2028 __skb_frag_ref(frag); 2029 skb_frag_off_set(frag, 0); 2030 skb_frag_size_set(frag, hlen); 2031 RX_USED_ADD(page, hlen + cp->crc_size); 2032 } 2033 2034 if (cp->crc_size) 2035 crcaddr = page_address(page->buffer) + off + hlen; 2036 2037 } else { 2038 /* copying packet */ 2039 if (!dlen) 2040 goto end_copy_pkt; 2041 2042 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 2043 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2044 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 2045 hlen = min(cp->page_size - off, dlen); 2046 if (hlen < 0) { 2047 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 2048 "rx page overflow: %d\n", hlen); 2049 dev_kfree_skb_irq(skb); 2050 return -1; 2051 } 2052 i = hlen; 2053 if (i == dlen) /* attach FCS */ 2054 i += cp->crc_size; 2055 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 2056 i, DMA_FROM_DEVICE); 2057 memcpy(p, page_address(page->buffer) + off, i); 2058 dma_sync_single_for_device(&cp->pdev->dev, 2059 page->dma_addr + off, i, 2060 DMA_FROM_DEVICE); 2061 if (p == (char *) skb->data) /* not split */ 2062 RX_USED_ADD(page, cp->mtu_stride); 2063 else 2064 RX_USED_ADD(page, i); 2065 2066 /* any more data? */ 2067 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 2068 p += hlen; 2069 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2070 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2071 dma_sync_single_for_cpu(&cp->pdev->dev, 2072 page->dma_addr, 2073 dlen + cp->crc_size, 2074 DMA_FROM_DEVICE); 2075 memcpy(p, page_address(page->buffer), dlen + cp->crc_size); 2076 dma_sync_single_for_device(&cp->pdev->dev, 2077 page->dma_addr, 2078 dlen + cp->crc_size, 2079 DMA_FROM_DEVICE); 2080 RX_USED_ADD(page, dlen + cp->crc_size); 2081 } 2082 end_copy_pkt: 2083 if (cp->crc_size) 2084 crcaddr = skb->data + alloclen; 2085 2086 skb_put(skb, alloclen); 2087 } 2088 2089 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3])); 2090 if (cp->crc_size) { 2091 /* checksum includes FCS. strip it out. */ 2092 csum = csum_fold(csum_partial(crcaddr, cp->crc_size, 2093 csum_unfold(csum))); 2094 } 2095 skb->protocol = eth_type_trans(skb, cp->dev); 2096 if (skb->protocol == htons(ETH_P_IP)) { 2097 skb->csum = csum_unfold(~csum); 2098 skb->ip_summed = CHECKSUM_COMPLETE; 2099 } else 2100 skb_checksum_none_assert(skb); 2101 return len; 2102 } 2103 2104 2105 /* we can handle up to 64 rx flows at a time. we do the same thing 2106 * as nonreassm except that we batch up the buffers. 2107 * NOTE: we currently just treat each flow as a bunch of packets that 2108 * we pass up. a better way would be to coalesce the packets 2109 * into a jumbo packet. to do that, we need to do the following: 2110 * 1) the first packet will have a clean split between header and 2111 * data. save both. 2112 * 2) each time the next flow packet comes in, extend the 2113 * data length and merge the checksums. 2114 * 3) on flow release, fix up the header. 2115 * 4) make sure the higher layer doesn't care. 2116 * because packets get coalesced, we shouldn't run into fragment count 2117 * issues. 2118 */ 2119 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words, 2120 struct sk_buff *skb) 2121 { 2122 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1); 2123 struct sk_buff_head *flow = &cp->rx_flows[flowid]; 2124 2125 /* this is protected at a higher layer, so no need to 2126 * do any additional locking here. stick the buffer 2127 * at the end. 2128 */ 2129 __skb_queue_tail(flow, skb); 2130 if (words[0] & RX_COMP1_RELEASE_FLOW) { 2131 while ((skb = __skb_dequeue(flow))) { 2132 cas_skb_release(skb); 2133 } 2134 } 2135 } 2136 2137 /* put rx descriptor back on ring. if a buffer is in use by a higher 2138 * layer, this will need to put in a replacement. 2139 */ 2140 static void cas_post_page(struct cas *cp, const int ring, const int index) 2141 { 2142 cas_page_t *new; 2143 int entry; 2144 2145 entry = cp->rx_old[ring]; 2146 2147 new = cas_page_swap(cp, ring, index); 2148 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr); 2149 cp->init_rxds[ring][entry].index = 2150 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | 2151 CAS_BASE(RX_INDEX_RING, ring)); 2152 2153 entry = RX_DESC_ENTRY(ring, entry + 1); 2154 cp->rx_old[ring] = entry; 2155 2156 if (entry % 4) 2157 return; 2158 2159 if (ring == 0) 2160 writel(entry, cp->regs + REG_RX_KICK); 2161 else if ((N_RX_DESC_RINGS > 1) && 2162 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2163 writel(entry, cp->regs + REG_PLUS_RX_KICK1); 2164 } 2165 2166 2167 /* only when things are bad */ 2168 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num) 2169 { 2170 unsigned int entry, last, count, released; 2171 int cluster; 2172 cas_page_t **page = cp->rx_pages[ring]; 2173 2174 entry = cp->rx_old[ring]; 2175 2176 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 2177 "rxd[%d] interrupt, done: %d\n", ring, entry); 2178 2179 cluster = -1; 2180 count = entry & 0x3; 2181 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4); 2182 released = 0; 2183 while (entry != last) { 2184 /* make a new buffer if it's still in use */ 2185 if (page_count(page[entry]->buffer) > 1) { 2186 cas_page_t *new = cas_page_dequeue(cp); 2187 if (!new) { 2188 /* let the timer know that we need to 2189 * do this again 2190 */ 2191 cp->cas_flags |= CAS_FLAG_RXD_POST(ring); 2192 if (!timer_pending(&cp->link_timer)) 2193 mod_timer(&cp->link_timer, jiffies + 2194 CAS_LINK_FAST_TIMEOUT); 2195 cp->rx_old[ring] = entry; 2196 cp->rx_last[ring] = num ? num - released : 0; 2197 return -ENOMEM; 2198 } 2199 spin_lock(&cp->rx_inuse_lock); 2200 list_add(&page[entry]->list, &cp->rx_inuse_list); 2201 spin_unlock(&cp->rx_inuse_lock); 2202 cp->init_rxds[ring][entry].buffer = 2203 cpu_to_le64(new->dma_addr); 2204 page[entry] = new; 2205 2206 } 2207 2208 if (++count == 4) { 2209 cluster = entry; 2210 count = 0; 2211 } 2212 released++; 2213 entry = RX_DESC_ENTRY(ring, entry + 1); 2214 } 2215 cp->rx_old[ring] = entry; 2216 2217 if (cluster < 0) 2218 return 0; 2219 2220 if (ring == 0) 2221 writel(cluster, cp->regs + REG_RX_KICK); 2222 else if ((N_RX_DESC_RINGS > 1) && 2223 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2224 writel(cluster, cp->regs + REG_PLUS_RX_KICK1); 2225 return 0; 2226 } 2227 2228 2229 /* process a completion ring. packets are set up in three basic ways: 2230 * small packets: should be copied header + data in single buffer. 2231 * large packets: header and data in a single buffer. 2232 * split packets: header in a separate buffer from data. 2233 * data may be in multiple pages. data may be > 256 2234 * bytes but in a single page. 2235 * 2236 * NOTE: RX page posting is done in this routine as well. while there's 2237 * the capability of using multiple RX completion rings, it isn't 2238 * really worthwhile due to the fact that the page posting will 2239 * force serialization on the single descriptor ring. 2240 */ 2241 static int cas_rx_ringN(struct cas *cp, int ring, int budget) 2242 { 2243 struct cas_rx_comp *rxcs = cp->init_rxcs[ring]; 2244 int entry, drops; 2245 int npackets = 0; 2246 2247 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 2248 "rx[%d] interrupt, done: %d/%d\n", 2249 ring, 2250 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]); 2251 2252 entry = cp->rx_new[ring]; 2253 drops = 0; 2254 while (1) { 2255 struct cas_rx_comp *rxc = rxcs + entry; 2256 struct sk_buff *skb; 2257 int type, len; 2258 u64 words[4]; 2259 int i, dring; 2260 2261 words[0] = le64_to_cpu(rxc->word1); 2262 words[1] = le64_to_cpu(rxc->word2); 2263 words[2] = le64_to_cpu(rxc->word3); 2264 words[3] = le64_to_cpu(rxc->word4); 2265 2266 /* don't touch if still owned by hw */ 2267 type = CAS_VAL(RX_COMP1_TYPE, words[0]); 2268 if (type == 0) 2269 break; 2270 2271 /* hw hasn't cleared the zero bit yet */ 2272 if (words[3] & RX_COMP4_ZERO) { 2273 break; 2274 } 2275 2276 /* get info on the packet */ 2277 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) { 2278 spin_lock(&cp->stat_lock[ring]); 2279 cp->net_stats[ring].rx_errors++; 2280 if (words[3] & RX_COMP4_LEN_MISMATCH) 2281 cp->net_stats[ring].rx_length_errors++; 2282 if (words[3] & RX_COMP4_BAD) 2283 cp->net_stats[ring].rx_crc_errors++; 2284 spin_unlock(&cp->stat_lock[ring]); 2285 2286 /* We'll just return it to Cassini. */ 2287 drop_it: 2288 spin_lock(&cp->stat_lock[ring]); 2289 ++cp->net_stats[ring].rx_dropped; 2290 spin_unlock(&cp->stat_lock[ring]); 2291 goto next; 2292 } 2293 2294 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb); 2295 if (len < 0) { 2296 ++drops; 2297 goto drop_it; 2298 } 2299 2300 /* see if it's a flow re-assembly or not. the driver 2301 * itself handles release back up. 2302 */ 2303 if (RX_DONT_BATCH || (type == 0x2)) { 2304 /* non-reassm: these always get released */ 2305 cas_skb_release(skb); 2306 } else { 2307 cas_rx_flow_pkt(cp, words, skb); 2308 } 2309 2310 spin_lock(&cp->stat_lock[ring]); 2311 cp->net_stats[ring].rx_packets++; 2312 cp->net_stats[ring].rx_bytes += len; 2313 spin_unlock(&cp->stat_lock[ring]); 2314 2315 next: 2316 npackets++; 2317 2318 /* should it be released? */ 2319 if (words[0] & RX_COMP1_RELEASE_HDR) { 2320 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 2321 dring = CAS_VAL(RX_INDEX_RING, i); 2322 i = CAS_VAL(RX_INDEX_NUM, i); 2323 cas_post_page(cp, dring, i); 2324 } 2325 2326 if (words[0] & RX_COMP1_RELEASE_DATA) { 2327 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 2328 dring = CAS_VAL(RX_INDEX_RING, i); 2329 i = CAS_VAL(RX_INDEX_NUM, i); 2330 cas_post_page(cp, dring, i); 2331 } 2332 2333 if (words[0] & RX_COMP1_RELEASE_NEXT) { 2334 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2335 dring = CAS_VAL(RX_INDEX_RING, i); 2336 i = CAS_VAL(RX_INDEX_NUM, i); 2337 cas_post_page(cp, dring, i); 2338 } 2339 2340 /* skip to the next entry */ 2341 entry = RX_COMP_ENTRY(ring, entry + 1 + 2342 CAS_VAL(RX_COMP1_SKIP, words[0])); 2343 #ifdef USE_NAPI 2344 if (budget && (npackets >= budget)) 2345 break; 2346 #endif 2347 } 2348 cp->rx_new[ring] = entry; 2349 2350 if (drops) 2351 netdev_info(cp->dev, "Memory squeeze, deferring packet\n"); 2352 return npackets; 2353 } 2354 2355 2356 /* put completion entries back on the ring */ 2357 static void cas_post_rxcs_ringN(struct net_device *dev, 2358 struct cas *cp, int ring) 2359 { 2360 struct cas_rx_comp *rxc = cp->init_rxcs[ring]; 2361 int last, entry; 2362 2363 last = cp->rx_cur[ring]; 2364 entry = cp->rx_new[ring]; 2365 netif_printk(cp, intr, KERN_DEBUG, dev, 2366 "rxc[%d] interrupt, done: %d/%d\n", 2367 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry); 2368 2369 /* zero and re-mark descriptors */ 2370 while (last != entry) { 2371 cas_rxc_init(rxc + last); 2372 last = RX_COMP_ENTRY(ring, last + 1); 2373 } 2374 cp->rx_cur[ring] = last; 2375 2376 if (ring == 0) 2377 writel(last, cp->regs + REG_RX_COMP_TAIL); 2378 else if (cp->cas_flags & CAS_FLAG_REG_PLUS) 2379 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); 2380 } 2381 2382 2383 2384 /* cassini can use all four PCI interrupts for the completion ring. 2385 * rings 3 and 4 are identical 2386 */ 2387 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 2388 static inline void cas_handle_irqN(struct net_device *dev, 2389 struct cas *cp, const u32 status, 2390 const int ring) 2391 { 2392 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) 2393 cas_post_rxcs_ringN(dev, cp, ring); 2394 } 2395 2396 static irqreturn_t cas_interruptN(int irq, void *dev_id) 2397 { 2398 struct net_device *dev = dev_id; 2399 struct cas *cp = netdev_priv(dev); 2400 unsigned long flags; 2401 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3; 2402 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); 2403 2404 /* check for shared irq */ 2405 if (status == 0) 2406 return IRQ_NONE; 2407 2408 spin_lock_irqsave(&cp->lock, flags); 2409 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2410 #ifdef USE_NAPI 2411 cas_mask_intr(cp); 2412 napi_schedule(&cp->napi); 2413 #else 2414 cas_rx_ringN(cp, ring, 0); 2415 #endif 2416 status &= ~INTR_RX_DONE_ALT; 2417 } 2418 2419 if (status) 2420 cas_handle_irqN(dev, cp, status, ring); 2421 spin_unlock_irqrestore(&cp->lock, flags); 2422 return IRQ_HANDLED; 2423 } 2424 #endif 2425 2426 #ifdef USE_PCI_INTB 2427 /* everything but rx packets */ 2428 static inline void cas_handle_irq1(struct cas *cp, const u32 status) 2429 { 2430 if (status & INTR_RX_BUF_UNAVAIL_1) { 2431 /* Frame arrived, no free RX buffers available. 2432 * NOTE: we can get this on a link transition. */ 2433 cas_post_rxds_ringN(cp, 1, 0); 2434 spin_lock(&cp->stat_lock[1]); 2435 cp->net_stats[1].rx_dropped++; 2436 spin_unlock(&cp->stat_lock[1]); 2437 } 2438 2439 if (status & INTR_RX_BUF_AE_1) 2440 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - 2441 RX_AE_FREEN_VAL(1)); 2442 2443 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2444 cas_post_rxcs_ringN(cp, 1); 2445 } 2446 2447 /* ring 2 handles a few more events than 3 and 4 */ 2448 static irqreturn_t cas_interrupt1(int irq, void *dev_id) 2449 { 2450 struct net_device *dev = dev_id; 2451 struct cas *cp = netdev_priv(dev); 2452 unsigned long flags; 2453 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2454 2455 /* check for shared interrupt */ 2456 if (status == 0) 2457 return IRQ_NONE; 2458 2459 spin_lock_irqsave(&cp->lock, flags); 2460 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2461 #ifdef USE_NAPI 2462 cas_mask_intr(cp); 2463 napi_schedule(&cp->napi); 2464 #else 2465 cas_rx_ringN(cp, 1, 0); 2466 #endif 2467 status &= ~INTR_RX_DONE_ALT; 2468 } 2469 if (status) 2470 cas_handle_irq1(cp, status); 2471 spin_unlock_irqrestore(&cp->lock, flags); 2472 return IRQ_HANDLED; 2473 } 2474 #endif 2475 2476 static inline void cas_handle_irq(struct net_device *dev, 2477 struct cas *cp, const u32 status) 2478 { 2479 /* housekeeping interrupts */ 2480 if (status & INTR_ERROR_MASK) 2481 cas_abnormal_irq(dev, cp, status); 2482 2483 if (status & INTR_RX_BUF_UNAVAIL) { 2484 /* Frame arrived, no free RX buffers available. 2485 * NOTE: we can get this on a link transition. 2486 */ 2487 cas_post_rxds_ringN(cp, 0, 0); 2488 spin_lock(&cp->stat_lock[0]); 2489 cp->net_stats[0].rx_dropped++; 2490 spin_unlock(&cp->stat_lock[0]); 2491 } else if (status & INTR_RX_BUF_AE) { 2492 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) - 2493 RX_AE_FREEN_VAL(0)); 2494 } 2495 2496 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2497 cas_post_rxcs_ringN(dev, cp, 0); 2498 } 2499 2500 static irqreturn_t cas_interrupt(int irq, void *dev_id) 2501 { 2502 struct net_device *dev = dev_id; 2503 struct cas *cp = netdev_priv(dev); 2504 unsigned long flags; 2505 u32 status = readl(cp->regs + REG_INTR_STATUS); 2506 2507 if (status == 0) 2508 return IRQ_NONE; 2509 2510 spin_lock_irqsave(&cp->lock, flags); 2511 if (status & (INTR_TX_ALL | INTR_TX_INTME)) { 2512 cas_tx(dev, cp, status); 2513 status &= ~(INTR_TX_ALL | INTR_TX_INTME); 2514 } 2515 2516 if (status & INTR_RX_DONE) { 2517 #ifdef USE_NAPI 2518 cas_mask_intr(cp); 2519 napi_schedule(&cp->napi); 2520 #else 2521 cas_rx_ringN(cp, 0, 0); 2522 #endif 2523 status &= ~INTR_RX_DONE; 2524 } 2525 2526 if (status) 2527 cas_handle_irq(dev, cp, status); 2528 spin_unlock_irqrestore(&cp->lock, flags); 2529 return IRQ_HANDLED; 2530 } 2531 2532 2533 #ifdef USE_NAPI 2534 static int cas_poll(struct napi_struct *napi, int budget) 2535 { 2536 struct cas *cp = container_of(napi, struct cas, napi); 2537 struct net_device *dev = cp->dev; 2538 int i, enable_intr, credits; 2539 u32 status = readl(cp->regs + REG_INTR_STATUS); 2540 unsigned long flags; 2541 2542 spin_lock_irqsave(&cp->lock, flags); 2543 cas_tx(dev, cp, status); 2544 spin_unlock_irqrestore(&cp->lock, flags); 2545 2546 /* NAPI rx packets. we spread the credits across all of the 2547 * rxc rings 2548 * 2549 * to make sure we're fair with the work we loop through each 2550 * ring N_RX_COMP_RING times with a request of 2551 * budget / N_RX_COMP_RINGS 2552 */ 2553 enable_intr = 1; 2554 credits = 0; 2555 for (i = 0; i < N_RX_COMP_RINGS; i++) { 2556 int j; 2557 for (j = 0; j < N_RX_COMP_RINGS; j++) { 2558 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS); 2559 if (credits >= budget) { 2560 enable_intr = 0; 2561 goto rx_comp; 2562 } 2563 } 2564 } 2565 2566 rx_comp: 2567 /* final rx completion */ 2568 spin_lock_irqsave(&cp->lock, flags); 2569 if (status) 2570 cas_handle_irq(dev, cp, status); 2571 2572 #ifdef USE_PCI_INTB 2573 if (N_RX_COMP_RINGS > 1) { 2574 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2575 if (status) 2576 cas_handle_irq1(dev, cp, status); 2577 } 2578 #endif 2579 2580 #ifdef USE_PCI_INTC 2581 if (N_RX_COMP_RINGS > 2) { 2582 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); 2583 if (status) 2584 cas_handle_irqN(dev, cp, status, 2); 2585 } 2586 #endif 2587 2588 #ifdef USE_PCI_INTD 2589 if (N_RX_COMP_RINGS > 3) { 2590 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); 2591 if (status) 2592 cas_handle_irqN(dev, cp, status, 3); 2593 } 2594 #endif 2595 spin_unlock_irqrestore(&cp->lock, flags); 2596 if (enable_intr) { 2597 napi_complete(napi); 2598 cas_unmask_intr(cp); 2599 } 2600 return credits; 2601 } 2602 #endif 2603 2604 #ifdef CONFIG_NET_POLL_CONTROLLER 2605 static void cas_netpoll(struct net_device *dev) 2606 { 2607 struct cas *cp = netdev_priv(dev); 2608 2609 cas_disable_irq(cp, 0); 2610 cas_interrupt(cp->pdev->irq, dev); 2611 cas_enable_irq(cp, 0); 2612 2613 #ifdef USE_PCI_INTB 2614 if (N_RX_COMP_RINGS > 1) { 2615 /* cas_interrupt1(); */ 2616 } 2617 #endif 2618 #ifdef USE_PCI_INTC 2619 if (N_RX_COMP_RINGS > 2) { 2620 /* cas_interruptN(); */ 2621 } 2622 #endif 2623 #ifdef USE_PCI_INTD 2624 if (N_RX_COMP_RINGS > 3) { 2625 /* cas_interruptN(); */ 2626 } 2627 #endif 2628 } 2629 #endif 2630 2631 static void cas_tx_timeout(struct net_device *dev, unsigned int txqueue) 2632 { 2633 struct cas *cp = netdev_priv(dev); 2634 2635 netdev_err(dev, "transmit timed out, resetting\n"); 2636 if (!cp->hw_running) { 2637 netdev_err(dev, "hrm.. hw not running!\n"); 2638 return; 2639 } 2640 2641 netdev_err(dev, "MIF_STATE[%08x]\n", 2642 readl(cp->regs + REG_MIF_STATE_MACHINE)); 2643 2644 netdev_err(dev, "MAC_STATE[%08x]\n", 2645 readl(cp->regs + REG_MAC_STATE_MACHINE)); 2646 2647 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n", 2648 readl(cp->regs + REG_TX_CFG), 2649 readl(cp->regs + REG_MAC_TX_STATUS), 2650 readl(cp->regs + REG_MAC_TX_CFG), 2651 readl(cp->regs + REG_TX_FIFO_PKT_CNT), 2652 readl(cp->regs + REG_TX_FIFO_WRITE_PTR), 2653 readl(cp->regs + REG_TX_FIFO_READ_PTR), 2654 readl(cp->regs + REG_TX_SM_1), 2655 readl(cp->regs + REG_TX_SM_2)); 2656 2657 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n", 2658 readl(cp->regs + REG_RX_CFG), 2659 readl(cp->regs + REG_MAC_RX_STATUS), 2660 readl(cp->regs + REG_MAC_RX_CFG)); 2661 2662 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n", 2663 readl(cp->regs + REG_HP_STATE_MACHINE), 2664 readl(cp->regs + REG_HP_STATUS0), 2665 readl(cp->regs + REG_HP_STATUS1), 2666 readl(cp->regs + REG_HP_STATUS2)); 2667 2668 #if 1 2669 atomic_inc(&cp->reset_task_pending); 2670 atomic_inc(&cp->reset_task_pending_all); 2671 schedule_work(&cp->reset_task); 2672 #else 2673 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 2674 schedule_work(&cp->reset_task); 2675 #endif 2676 } 2677 2678 static inline int cas_intme(int ring, int entry) 2679 { 2680 /* Algorithm: IRQ every 1/2 of descriptors. */ 2681 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1))) 2682 return 1; 2683 return 0; 2684 } 2685 2686 2687 static void cas_write_txd(struct cas *cp, int ring, int entry, 2688 dma_addr_t mapping, int len, u64 ctrl, int last) 2689 { 2690 struct cas_tx_desc *txd = cp->init_txds[ring] + entry; 2691 2692 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len); 2693 if (cas_intme(ring, entry)) 2694 ctrl |= TX_DESC_INTME; 2695 if (last) 2696 ctrl |= TX_DESC_EOF; 2697 txd->control = cpu_to_le64(ctrl); 2698 txd->buffer = cpu_to_le64(mapping); 2699 } 2700 2701 static inline void *tx_tiny_buf(struct cas *cp, const int ring, 2702 const int entry) 2703 { 2704 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry; 2705 } 2706 2707 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, 2708 const int entry, const int tentry) 2709 { 2710 cp->tx_tiny_use[ring][tentry].nbufs++; 2711 cp->tx_tiny_use[ring][entry].used = 1; 2712 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry; 2713 } 2714 2715 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, 2716 struct sk_buff *skb) 2717 { 2718 struct net_device *dev = cp->dev; 2719 int entry, nr_frags, frag, tabort, tentry; 2720 dma_addr_t mapping; 2721 unsigned long flags; 2722 u64 ctrl; 2723 u32 len; 2724 2725 spin_lock_irqsave(&cp->tx_lock[ring], flags); 2726 2727 /* This is a hard error, log it. */ 2728 if (TX_BUFFS_AVAIL(cp, ring) <= 2729 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) { 2730 netif_stop_queue(dev); 2731 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2732 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 2733 return 1; 2734 } 2735 2736 ctrl = 0; 2737 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2738 const u64 csum_start_off = skb_checksum_start_offset(skb); 2739 const u64 csum_stuff_off = csum_start_off + skb->csum_offset; 2740 2741 ctrl = TX_DESC_CSUM_EN | 2742 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) | 2743 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off); 2744 } 2745 2746 entry = cp->tx_new[ring]; 2747 cp->tx_skbs[ring][entry] = skb; 2748 2749 nr_frags = skb_shinfo(skb)->nr_frags; 2750 len = skb_headlen(skb); 2751 mapping = dma_map_page(&cp->pdev->dev, virt_to_page(skb->data), 2752 offset_in_page(skb->data), len, DMA_TO_DEVICE); 2753 2754 tentry = entry; 2755 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len); 2756 if (unlikely(tabort)) { 2757 /* NOTE: len is always > tabort */ 2758 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2759 ctrl | TX_DESC_SOF, 0); 2760 entry = TX_DESC_NEXT(ring, entry); 2761 2762 skb_copy_from_linear_data_offset(skb, len - tabort, 2763 tx_tiny_buf(cp, ring, entry), tabort); 2764 mapping = tx_tiny_map(cp, ring, entry, tentry); 2765 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl, 2766 (nr_frags == 0)); 2767 } else { 2768 cas_write_txd(cp, ring, entry, mapping, len, ctrl | 2769 TX_DESC_SOF, (nr_frags == 0)); 2770 } 2771 entry = TX_DESC_NEXT(ring, entry); 2772 2773 for (frag = 0; frag < nr_frags; frag++) { 2774 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 2775 2776 len = skb_frag_size(fragp); 2777 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len, 2778 DMA_TO_DEVICE); 2779 2780 tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len); 2781 if (unlikely(tabort)) { 2782 /* NOTE: len is always > tabort */ 2783 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2784 ctrl, 0); 2785 entry = TX_DESC_NEXT(ring, entry); 2786 memcpy_from_page(tx_tiny_buf(cp, ring, entry), 2787 skb_frag_page(fragp), 2788 skb_frag_off(fragp) + len - tabort, 2789 tabort); 2790 mapping = tx_tiny_map(cp, ring, entry, tentry); 2791 len = tabort; 2792 } 2793 2794 cas_write_txd(cp, ring, entry, mapping, len, ctrl, 2795 (frag + 1 == nr_frags)); 2796 entry = TX_DESC_NEXT(ring, entry); 2797 } 2798 2799 cp->tx_new[ring] = entry; 2800 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)) 2801 netif_stop_queue(dev); 2802 2803 netif_printk(cp, tx_queued, KERN_DEBUG, dev, 2804 "tx[%d] queued, slot %d, skblen %d, avail %d\n", 2805 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring)); 2806 writel(entry, cp->regs + REG_TX_KICKN(ring)); 2807 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2808 return 0; 2809 } 2810 2811 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev) 2812 { 2813 struct cas *cp = netdev_priv(dev); 2814 2815 /* this is only used as a load-balancing hint, so it doesn't 2816 * need to be SMP safe 2817 */ 2818 static int ring; 2819 2820 if (skb_padto(skb, cp->min_frame_size)) 2821 return NETDEV_TX_OK; 2822 2823 /* XXX: we need some higher-level QoS hooks to steer packets to 2824 * individual queues. 2825 */ 2826 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb)) 2827 return NETDEV_TX_BUSY; 2828 return NETDEV_TX_OK; 2829 } 2830 2831 static void cas_init_tx_dma(struct cas *cp) 2832 { 2833 u64 desc_dma = cp->block_dvma; 2834 unsigned long off; 2835 u32 val; 2836 int i; 2837 2838 /* set up tx completion writeback registers. must be 8-byte aligned */ 2839 #ifdef USE_TX_COMPWB 2840 off = offsetof(struct cas_init_block, tx_compwb); 2841 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); 2842 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); 2843 #endif 2844 2845 /* enable completion writebacks, enable paced mode, 2846 * disable read pipe, and disable pre-interrupt compwbs 2847 */ 2848 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | 2849 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 | 2850 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | 2851 TX_CFG_INTR_COMPWB_DIS; 2852 2853 /* write out tx ring info and tx desc bases */ 2854 for (i = 0; i < MAX_TX_RINGS; i++) { 2855 off = (unsigned long) cp->init_txds[i] - 2856 (unsigned long) cp->init_block; 2857 2858 val |= CAS_TX_RINGN_BASE(i); 2859 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); 2860 writel((desc_dma + off) & 0xffffffff, cp->regs + 2861 REG_TX_DBN_LOW(i)); 2862 /* don't zero out the kick register here as the system 2863 * will wedge 2864 */ 2865 } 2866 writel(val, cp->regs + REG_TX_CFG); 2867 2868 /* program max burst sizes. these numbers should be different 2869 * if doing QoS. 2870 */ 2871 #ifdef USE_QOS 2872 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2873 writel(0x1600, cp->regs + REG_TX_MAXBURST_1); 2874 writel(0x2400, cp->regs + REG_TX_MAXBURST_2); 2875 writel(0x4800, cp->regs + REG_TX_MAXBURST_3); 2876 #else 2877 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2878 writel(0x800, cp->regs + REG_TX_MAXBURST_1); 2879 writel(0x800, cp->regs + REG_TX_MAXBURST_2); 2880 writel(0x800, cp->regs + REG_TX_MAXBURST_3); 2881 #endif 2882 } 2883 2884 /* Must be invoked under cp->lock. */ 2885 static inline void cas_init_dma(struct cas *cp) 2886 { 2887 cas_init_tx_dma(cp); 2888 cas_init_rx_dma(cp); 2889 } 2890 2891 static void cas_process_mc_list(struct cas *cp) 2892 { 2893 u16 hash_table[16]; 2894 u32 crc; 2895 struct netdev_hw_addr *ha; 2896 int i = 1; 2897 2898 memset(hash_table, 0, sizeof(hash_table)); 2899 netdev_for_each_mc_addr(ha, cp->dev) { 2900 if (i <= CAS_MC_EXACT_MATCH_SIZE) { 2901 /* use the alternate mac address registers for the 2902 * first 15 multicast addresses 2903 */ 2904 writel((ha->addr[4] << 8) | ha->addr[5], 2905 cp->regs + REG_MAC_ADDRN(i*3 + 0)); 2906 writel((ha->addr[2] << 8) | ha->addr[3], 2907 cp->regs + REG_MAC_ADDRN(i*3 + 1)); 2908 writel((ha->addr[0] << 8) | ha->addr[1], 2909 cp->regs + REG_MAC_ADDRN(i*3 + 2)); 2910 i++; 2911 } 2912 else { 2913 /* use hw hash table for the next series of 2914 * multicast addresses 2915 */ 2916 crc = ether_crc_le(ETH_ALEN, ha->addr); 2917 crc >>= 24; 2918 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); 2919 } 2920 } 2921 for (i = 0; i < 16; i++) 2922 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i)); 2923 } 2924 2925 /* Must be invoked under cp->lock. */ 2926 static u32 cas_setup_multicast(struct cas *cp) 2927 { 2928 u32 rxcfg = 0; 2929 int i; 2930 2931 if (cp->dev->flags & IFF_PROMISC) { 2932 rxcfg |= MAC_RX_CFG_PROMISC_EN; 2933 2934 } else if (cp->dev->flags & IFF_ALLMULTI) { 2935 for (i=0; i < 16; i++) 2936 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); 2937 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2938 2939 } else { 2940 cas_process_mc_list(cp); 2941 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2942 } 2943 2944 return rxcfg; 2945 } 2946 2947 /* must be invoked under cp->stat_lock[N_TX_RINGS] */ 2948 static void cas_clear_mac_err(struct cas *cp) 2949 { 2950 writel(0, cp->regs + REG_MAC_COLL_NORMAL); 2951 writel(0, cp->regs + REG_MAC_COLL_FIRST); 2952 writel(0, cp->regs + REG_MAC_COLL_EXCESS); 2953 writel(0, cp->regs + REG_MAC_COLL_LATE); 2954 writel(0, cp->regs + REG_MAC_TIMER_DEFER); 2955 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); 2956 writel(0, cp->regs + REG_MAC_RECV_FRAME); 2957 writel(0, cp->regs + REG_MAC_LEN_ERR); 2958 writel(0, cp->regs + REG_MAC_ALIGN_ERR); 2959 writel(0, cp->regs + REG_MAC_FCS_ERR); 2960 writel(0, cp->regs + REG_MAC_RX_CODE_ERR); 2961 } 2962 2963 2964 static void cas_mac_reset(struct cas *cp) 2965 { 2966 int i; 2967 2968 /* do both TX and RX reset */ 2969 writel(0x1, cp->regs + REG_MAC_TX_RESET); 2970 writel(0x1, cp->regs + REG_MAC_RX_RESET); 2971 2972 /* wait for TX */ 2973 i = STOP_TRIES; 2974 while (i-- > 0) { 2975 if (readl(cp->regs + REG_MAC_TX_RESET) == 0) 2976 break; 2977 udelay(10); 2978 } 2979 2980 /* wait for RX */ 2981 i = STOP_TRIES; 2982 while (i-- > 0) { 2983 if (readl(cp->regs + REG_MAC_RX_RESET) == 0) 2984 break; 2985 udelay(10); 2986 } 2987 2988 if (readl(cp->regs + REG_MAC_TX_RESET) | 2989 readl(cp->regs + REG_MAC_RX_RESET)) 2990 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n", 2991 readl(cp->regs + REG_MAC_TX_RESET), 2992 readl(cp->regs + REG_MAC_RX_RESET), 2993 readl(cp->regs + REG_MAC_STATE_MACHINE)); 2994 } 2995 2996 2997 /* Must be invoked under cp->lock. */ 2998 static void cas_init_mac(struct cas *cp) 2999 { 3000 const unsigned char *e = &cp->dev->dev_addr[0]; 3001 int i; 3002 cas_mac_reset(cp); 3003 3004 /* setup core arbitration weight register */ 3005 writel(CAWR_RR_DIS, cp->regs + REG_CAWR); 3006 3007 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) 3008 /* set the infinite burst register for chips that don't have 3009 * pci issues. 3010 */ 3011 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0) 3012 writel(INF_BURST_EN, cp->regs + REG_INF_BURST); 3013 #endif 3014 3015 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); 3016 3017 writel(0x00, cp->regs + REG_MAC_IPG0); 3018 writel(0x08, cp->regs + REG_MAC_IPG1); 3019 writel(0x04, cp->regs + REG_MAC_IPG2); 3020 3021 /* change later for 802.3z */ 3022 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 3023 3024 /* min frame + FCS */ 3025 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); 3026 3027 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we 3028 * specify the maximum frame size to prevent RX tag errors on 3029 * oversized frames. 3030 */ 3031 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) | 3032 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, 3033 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), 3034 cp->regs + REG_MAC_FRAMESIZE_MAX); 3035 3036 /* NOTE: crc_size is used as a surrogate for half-duplex. 3037 * workaround saturn half-duplex issue by increasing preamble 3038 * size to 65 bytes. 3039 */ 3040 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size) 3041 writel(0x41, cp->regs + REG_MAC_PA_SIZE); 3042 else 3043 writel(0x07, cp->regs + REG_MAC_PA_SIZE); 3044 writel(0x04, cp->regs + REG_MAC_JAM_SIZE); 3045 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); 3046 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); 3047 3048 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); 3049 3050 writel(0, cp->regs + REG_MAC_ADDR_FILTER0); 3051 writel(0, cp->regs + REG_MAC_ADDR_FILTER1); 3052 writel(0, cp->regs + REG_MAC_ADDR_FILTER2); 3053 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); 3054 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); 3055 3056 /* setup mac address in perfect filter array */ 3057 for (i = 0; i < 45; i++) 3058 writel(0x0, cp->regs + REG_MAC_ADDRN(i)); 3059 3060 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); 3061 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); 3062 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); 3063 3064 writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); 3065 writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); 3066 writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); 3067 3068 cp->mac_rx_cfg = cas_setup_multicast(cp); 3069 3070 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3071 cas_clear_mac_err(cp); 3072 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3073 3074 /* Setup MAC interrupts. We want to get all of the interesting 3075 * counter expiration events, but we do not want to hear about 3076 * normal rx/tx as the DMA engine tells us that. 3077 */ 3078 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); 3079 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); 3080 3081 /* Don't enable even the PAUSE interrupts for now, we 3082 * make no use of those events other than to record them. 3083 */ 3084 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); 3085 } 3086 3087 /* Must be invoked under cp->lock. */ 3088 static void cas_init_pause_thresholds(struct cas *cp) 3089 { 3090 /* Calculate pause thresholds. Setting the OFF threshold to the 3091 * full RX fifo size effectively disables PAUSE generation 3092 */ 3093 if (cp->rx_fifo_size <= (2 * 1024)) { 3094 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size; 3095 } else { 3096 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63; 3097 if (max_frame * 3 > cp->rx_fifo_size) { 3098 cp->rx_pause_off = 7104; 3099 cp->rx_pause_on = 960; 3100 } else { 3101 int off = (cp->rx_fifo_size - (max_frame * 2)); 3102 int on = off - max_frame; 3103 cp->rx_pause_off = off; 3104 cp->rx_pause_on = on; 3105 } 3106 } 3107 } 3108 3109 static int cas_vpd_match(const void __iomem *p, const char *str) 3110 { 3111 int len = strlen(str) + 1; 3112 int i; 3113 3114 for (i = 0; i < len; i++) { 3115 if (readb(p + i) != str[i]) 3116 return 0; 3117 } 3118 return 1; 3119 } 3120 3121 3122 /* get the mac address by reading the vpd information in the rom. 3123 * also get the phy type and determine if there's an entropy generator. 3124 * NOTE: this is a bit convoluted for the following reasons: 3125 * 1) vpd info has order-dependent mac addresses for multinic cards 3126 * 2) the only way to determine the nic order is to use the slot 3127 * number. 3128 * 3) fiber cards don't have bridges, so their slot numbers don't 3129 * mean anything. 3130 * 4) we don't actually know we have a fiber card until after 3131 * the mac addresses are parsed. 3132 */ 3133 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr, 3134 const int offset) 3135 { 3136 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START; 3137 void __iomem *base, *kstart; 3138 int i, len; 3139 int found = 0; 3140 #define VPD_FOUND_MAC 0x01 3141 #define VPD_FOUND_PHY 0x02 3142 3143 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */ 3144 int mac_off = 0; 3145 3146 #if defined(CONFIG_SPARC) 3147 const unsigned char *addr; 3148 #endif 3149 3150 /* give us access to the PROM */ 3151 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD, 3152 cp->regs + REG_BIM_LOCAL_DEV_EN); 3153 3154 /* check for an expansion rom */ 3155 if (readb(p) != 0x55 || readb(p + 1) != 0xaa) 3156 goto use_random_mac_addr; 3157 3158 /* search for beginning of vpd */ 3159 base = NULL; 3160 for (i = 2; i < EXPANSION_ROM_SIZE; i++) { 3161 /* check for PCIR */ 3162 if ((readb(p + i + 0) == 0x50) && 3163 (readb(p + i + 1) == 0x43) && 3164 (readb(p + i + 2) == 0x49) && 3165 (readb(p + i + 3) == 0x52)) { 3166 base = p + (readb(p + i + 8) | 3167 (readb(p + i + 9) << 8)); 3168 break; 3169 } 3170 } 3171 3172 if (!base || (readb(base) != 0x82)) 3173 goto use_random_mac_addr; 3174 3175 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3; 3176 while (i < EXPANSION_ROM_SIZE) { 3177 if (readb(base + i) != 0x90) /* no vpd found */ 3178 goto use_random_mac_addr; 3179 3180 /* found a vpd field */ 3181 len = readb(base + i + 1) | (readb(base + i + 2) << 8); 3182 3183 /* extract keywords */ 3184 kstart = base + i + 3; 3185 p = kstart; 3186 while ((p - kstart) < len) { 3187 int klen = readb(p + 2); 3188 int j; 3189 char type; 3190 3191 p += 3; 3192 3193 /* look for the following things: 3194 * -- correct length == 29 3195 * 3 (type) + 2 (size) + 3196 * 18 (strlen("local-mac-address") + 1) + 3197 * 6 (mac addr) 3198 * -- VPD Instance 'I' 3199 * -- VPD Type Bytes 'B' 3200 * -- VPD data length == 6 3201 * -- property string == local-mac-address 3202 * 3203 * -- correct length == 24 3204 * 3 (type) + 2 (size) + 3205 * 12 (strlen("entropy-dev") + 1) + 3206 * 7 (strlen("vms110") + 1) 3207 * -- VPD Instance 'I' 3208 * -- VPD Type String 'B' 3209 * -- VPD data length == 7 3210 * -- property string == entropy-dev 3211 * 3212 * -- correct length == 18 3213 * 3 (type) + 2 (size) + 3214 * 9 (strlen("phy-type") + 1) + 3215 * 4 (strlen("pcs") + 1) 3216 * -- VPD Instance 'I' 3217 * -- VPD Type String 'S' 3218 * -- VPD data length == 4 3219 * -- property string == phy-type 3220 * 3221 * -- correct length == 23 3222 * 3 (type) + 2 (size) + 3223 * 14 (strlen("phy-interface") + 1) + 3224 * 4 (strlen("pcs") + 1) 3225 * -- VPD Instance 'I' 3226 * -- VPD Type String 'S' 3227 * -- VPD data length == 4 3228 * -- property string == phy-interface 3229 */ 3230 if (readb(p) != 'I') 3231 goto next; 3232 3233 /* finally, check string and length */ 3234 type = readb(p + 3); 3235 if (type == 'B') { 3236 if ((klen == 29) && readb(p + 4) == 6 && 3237 cas_vpd_match(p + 5, 3238 "local-mac-address")) { 3239 if (mac_off++ > offset) 3240 goto next; 3241 3242 /* set mac address */ 3243 for (j = 0; j < 6; j++) 3244 dev_addr[j] = 3245 readb(p + 23 + j); 3246 goto found_mac; 3247 } 3248 } 3249 3250 if (type != 'S') 3251 goto next; 3252 3253 #ifdef USE_ENTROPY_DEV 3254 if ((klen == 24) && 3255 cas_vpd_match(p + 5, "entropy-dev") && 3256 cas_vpd_match(p + 17, "vms110")) { 3257 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV; 3258 goto next; 3259 } 3260 #endif 3261 3262 if (found & VPD_FOUND_PHY) 3263 goto next; 3264 3265 if ((klen == 18) && readb(p + 4) == 4 && 3266 cas_vpd_match(p + 5, "phy-type")) { 3267 if (cas_vpd_match(p + 14, "pcs")) { 3268 phy_type = CAS_PHY_SERDES; 3269 goto found_phy; 3270 } 3271 } 3272 3273 if ((klen == 23) && readb(p + 4) == 4 && 3274 cas_vpd_match(p + 5, "phy-interface")) { 3275 if (cas_vpd_match(p + 19, "pcs")) { 3276 phy_type = CAS_PHY_SERDES; 3277 goto found_phy; 3278 } 3279 } 3280 found_mac: 3281 found |= VPD_FOUND_MAC; 3282 goto next; 3283 3284 found_phy: 3285 found |= VPD_FOUND_PHY; 3286 3287 next: 3288 p += klen; 3289 } 3290 i += len + 3; 3291 } 3292 3293 use_random_mac_addr: 3294 if (found & VPD_FOUND_MAC) 3295 goto done; 3296 3297 #if defined(CONFIG_SPARC) 3298 addr = of_get_property(cp->of_node, "local-mac-address", NULL); 3299 if (addr != NULL) { 3300 memcpy(dev_addr, addr, ETH_ALEN); 3301 goto done; 3302 } 3303 #endif 3304 3305 /* Sun MAC prefix then 3 random bytes. */ 3306 pr_info("MAC address not found in ROM VPD\n"); 3307 dev_addr[0] = 0x08; 3308 dev_addr[1] = 0x00; 3309 dev_addr[2] = 0x20; 3310 get_random_bytes(dev_addr + 3, 3); 3311 3312 done: 3313 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3314 return phy_type; 3315 } 3316 3317 /* check pci invariants */ 3318 static void cas_check_pci_invariants(struct cas *cp) 3319 { 3320 struct pci_dev *pdev = cp->pdev; 3321 3322 cp->cas_flags = 0; 3323 if ((pdev->vendor == PCI_VENDOR_ID_SUN) && 3324 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) { 3325 if (pdev->revision >= CAS_ID_REVPLUS) 3326 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3327 if (pdev->revision < CAS_ID_REVPLUS02u) 3328 cp->cas_flags |= CAS_FLAG_TARGET_ABORT; 3329 3330 /* Original Cassini supports HW CSUM, but it's not 3331 * enabled by default as it can trigger TX hangs. 3332 */ 3333 if (pdev->revision < CAS_ID_REV2) 3334 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM; 3335 } else { 3336 /* Only sun has original cassini chips. */ 3337 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3338 3339 /* We use a flag because the same phy might be externally 3340 * connected. 3341 */ 3342 if ((pdev->vendor == PCI_VENDOR_ID_NS) && 3343 (pdev->device == PCI_DEVICE_ID_NS_SATURN)) 3344 cp->cas_flags |= CAS_FLAG_SATURN; 3345 } 3346 } 3347 3348 3349 static int cas_check_invariants(struct cas *cp) 3350 { 3351 struct pci_dev *pdev = cp->pdev; 3352 u8 addr[ETH_ALEN]; 3353 u32 cfg; 3354 int i; 3355 3356 /* get page size for rx buffers. */ 3357 cp->page_order = 0; 3358 #ifdef USE_PAGE_ORDER 3359 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) { 3360 /* see if we can allocate larger pages */ 3361 struct page *page = alloc_pages(GFP_ATOMIC, 3362 CAS_JUMBO_PAGE_SHIFT - 3363 PAGE_SHIFT); 3364 if (page) { 3365 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT); 3366 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT; 3367 } else { 3368 printk("MTU limited to %d bytes\n", CAS_MAX_MTU); 3369 } 3370 } 3371 #endif 3372 cp->page_size = (PAGE_SIZE << cp->page_order); 3373 3374 /* Fetch the FIFO configurations. */ 3375 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; 3376 cp->rx_fifo_size = RX_FIFO_SIZE; 3377 3378 /* finish phy determination. MDIO1 takes precedence over MDIO0 if 3379 * they're both connected. 3380 */ 3381 cp->phy_type = cas_get_vpd_info(cp, addr, PCI_SLOT(pdev->devfn)); 3382 eth_hw_addr_set(cp->dev, addr); 3383 if (cp->phy_type & CAS_PHY_SERDES) { 3384 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3385 return 0; /* no more checking needed */ 3386 } 3387 3388 /* MII */ 3389 cfg = readl(cp->regs + REG_MIF_CFG); 3390 if (cfg & MIF_CFG_MDIO_1) { 3391 cp->phy_type = CAS_PHY_MII_MDIO1; 3392 } else if (cfg & MIF_CFG_MDIO_0) { 3393 cp->phy_type = CAS_PHY_MII_MDIO0; 3394 } 3395 3396 cas_mif_poll(cp, 0); 3397 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3398 3399 for (i = 0; i < 32; i++) { 3400 u32 phy_id; 3401 int j; 3402 3403 for (j = 0; j < 3; j++) { 3404 cp->phy_addr = i; 3405 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16; 3406 phy_id |= cas_phy_read(cp, MII_PHYSID2); 3407 if (phy_id && (phy_id != 0xFFFFFFFF)) { 3408 cp->phy_id = phy_id; 3409 goto done; 3410 } 3411 } 3412 } 3413 pr_err("MII phy did not respond [%08x]\n", 3414 readl(cp->regs + REG_MIF_STATE_MACHINE)); 3415 return -1; 3416 3417 done: 3418 /* see if we can do gigabit */ 3419 cfg = cas_phy_read(cp, MII_BMSR); 3420 if ((cfg & CAS_BMSR_1000_EXTEND) && 3421 cas_phy_read(cp, CAS_MII_1000_EXTEND)) 3422 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3423 return 0; 3424 } 3425 3426 /* Must be invoked under cp->lock. */ 3427 static inline void cas_start_dma(struct cas *cp) 3428 { 3429 int i; 3430 u32 val; 3431 int txfailed = 0; 3432 3433 /* enable dma */ 3434 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; 3435 writel(val, cp->regs + REG_TX_CFG); 3436 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; 3437 writel(val, cp->regs + REG_RX_CFG); 3438 3439 /* enable the mac */ 3440 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; 3441 writel(val, cp->regs + REG_MAC_TX_CFG); 3442 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; 3443 writel(val, cp->regs + REG_MAC_RX_CFG); 3444 3445 i = STOP_TRIES; 3446 while (i-- > 0) { 3447 val = readl(cp->regs + REG_MAC_TX_CFG); 3448 if ((val & MAC_TX_CFG_EN)) 3449 break; 3450 udelay(10); 3451 } 3452 if (i < 0) txfailed = 1; 3453 i = STOP_TRIES; 3454 while (i-- > 0) { 3455 val = readl(cp->regs + REG_MAC_RX_CFG); 3456 if ((val & MAC_RX_CFG_EN)) { 3457 if (txfailed) { 3458 netdev_err(cp->dev, 3459 "enabling mac failed [tx:%08x:%08x]\n", 3460 readl(cp->regs + REG_MIF_STATE_MACHINE), 3461 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3462 } 3463 goto enable_rx_done; 3464 } 3465 udelay(10); 3466 } 3467 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n", 3468 (txfailed ? "tx,rx" : "rx"), 3469 readl(cp->regs + REG_MIF_STATE_MACHINE), 3470 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3471 3472 enable_rx_done: 3473 cas_unmask_intr(cp); /* enable interrupts */ 3474 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 3475 writel(0, cp->regs + REG_RX_COMP_TAIL); 3476 3477 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 3478 if (N_RX_DESC_RINGS > 1) 3479 writel(RX_DESC_RINGN_SIZE(1) - 4, 3480 cp->regs + REG_PLUS_RX_KICK1); 3481 } 3482 } 3483 3484 /* Must be invoked under cp->lock. */ 3485 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd, 3486 int *pause) 3487 { 3488 u32 val = readl(cp->regs + REG_PCS_MII_LPA); 3489 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0; 3490 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00; 3491 if (val & PCS_MII_LPA_ASYM_PAUSE) 3492 *pause |= 0x10; 3493 *spd = 1000; 3494 } 3495 3496 /* Must be invoked under cp->lock. */ 3497 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd, 3498 int *pause) 3499 { 3500 u32 val; 3501 3502 *fd = 0; 3503 *spd = 10; 3504 *pause = 0; 3505 3506 /* use GMII registers */ 3507 val = cas_phy_read(cp, MII_LPA); 3508 if (val & CAS_LPA_PAUSE) 3509 *pause = 0x01; 3510 3511 if (val & CAS_LPA_ASYM_PAUSE) 3512 *pause |= 0x10; 3513 3514 if (val & LPA_DUPLEX) 3515 *fd = 1; 3516 if (val & LPA_100) 3517 *spd = 100; 3518 3519 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 3520 val = cas_phy_read(cp, CAS_MII_1000_STATUS); 3521 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF)) 3522 *spd = 1000; 3523 if (val & CAS_LPA_1000FULL) 3524 *fd = 1; 3525 } 3526 } 3527 3528 /* A link-up condition has occurred, initialize and enable the 3529 * rest of the chip. 3530 * 3531 * Must be invoked under cp->lock. 3532 */ 3533 static void cas_set_link_modes(struct cas *cp) 3534 { 3535 u32 val; 3536 int full_duplex, speed, pause; 3537 3538 full_duplex = 0; 3539 speed = 10; 3540 pause = 0; 3541 3542 if (CAS_PHY_MII(cp->phy_type)) { 3543 cas_mif_poll(cp, 0); 3544 val = cas_phy_read(cp, MII_BMCR); 3545 if (val & BMCR_ANENABLE) { 3546 cas_read_mii_link_mode(cp, &full_duplex, &speed, 3547 &pause); 3548 } else { 3549 if (val & BMCR_FULLDPLX) 3550 full_duplex = 1; 3551 3552 if (val & BMCR_SPEED100) 3553 speed = 100; 3554 else if (val & CAS_BMCR_SPEED1000) 3555 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 3556 1000 : 100; 3557 } 3558 cas_mif_poll(cp, 1); 3559 3560 } else { 3561 val = readl(cp->regs + REG_PCS_MII_CTRL); 3562 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause); 3563 if ((val & PCS_MII_AUTONEG_EN) == 0) { 3564 if (val & PCS_MII_CTRL_DUPLEX) 3565 full_duplex = 1; 3566 } 3567 } 3568 3569 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n", 3570 speed, full_duplex ? "full" : "half"); 3571 3572 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED; 3573 if (CAS_PHY_MII(cp->phy_type)) { 3574 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN; 3575 if (!full_duplex) 3576 val |= MAC_XIF_DISABLE_ECHO; 3577 } 3578 if (full_duplex) 3579 val |= MAC_XIF_FDPLX_LED; 3580 if (speed == 1000) 3581 val |= MAC_XIF_GMII_MODE; 3582 writel(val, cp->regs + REG_MAC_XIF_CFG); 3583 3584 /* deal with carrier and collision detect. */ 3585 val = MAC_TX_CFG_IPG_EN; 3586 if (full_duplex) { 3587 val |= MAC_TX_CFG_IGNORE_CARRIER; 3588 val |= MAC_TX_CFG_IGNORE_COLL; 3589 } else { 3590 #ifndef USE_CSMA_CD_PROTO 3591 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN; 3592 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM; 3593 #endif 3594 } 3595 /* val now set up for REG_MAC_TX_CFG */ 3596 3597 /* If gigabit and half-duplex, enable carrier extension 3598 * mode. increase slot time to 512 bytes as well. 3599 * else, disable it and make sure slot time is 64 bytes. 3600 * also activate checksum bug workaround 3601 */ 3602 if ((speed == 1000) && !full_duplex) { 3603 writel(val | MAC_TX_CFG_CARRIER_EXTEND, 3604 cp->regs + REG_MAC_TX_CFG); 3605 3606 val = readl(cp->regs + REG_MAC_RX_CFG); 3607 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */ 3608 writel(val | MAC_RX_CFG_CARRIER_EXTEND, 3609 cp->regs + REG_MAC_RX_CFG); 3610 3611 writel(0x200, cp->regs + REG_MAC_SLOT_TIME); 3612 3613 cp->crc_size = 4; 3614 /* minimum size gigabit frame at half duplex */ 3615 cp->min_frame_size = CAS_1000MB_MIN_FRAME; 3616 3617 } else { 3618 writel(val, cp->regs + REG_MAC_TX_CFG); 3619 3620 /* checksum bug workaround. don't strip FCS when in 3621 * half-duplex mode 3622 */ 3623 val = readl(cp->regs + REG_MAC_RX_CFG); 3624 if (full_duplex) { 3625 val |= MAC_RX_CFG_STRIP_FCS; 3626 cp->crc_size = 0; 3627 cp->min_frame_size = CAS_MIN_MTU; 3628 } else { 3629 val &= ~MAC_RX_CFG_STRIP_FCS; 3630 cp->crc_size = 4; 3631 cp->min_frame_size = CAS_MIN_FRAME; 3632 } 3633 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, 3634 cp->regs + REG_MAC_RX_CFG); 3635 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 3636 } 3637 3638 if (netif_msg_link(cp)) { 3639 if (pause & 0x01) { 3640 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n", 3641 cp->rx_fifo_size, 3642 cp->rx_pause_off, 3643 cp->rx_pause_on); 3644 } else if (pause & 0x10) { 3645 netdev_info(cp->dev, "TX pause enabled\n"); 3646 } else { 3647 netdev_info(cp->dev, "Pause is disabled\n"); 3648 } 3649 } 3650 3651 val = readl(cp->regs + REG_MAC_CTRL_CFG); 3652 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN); 3653 if (pause) { /* symmetric or asymmetric pause */ 3654 val |= MAC_CTRL_CFG_SEND_PAUSE_EN; 3655 if (pause & 0x01) { /* symmetric pause */ 3656 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 3657 } 3658 } 3659 writel(val, cp->regs + REG_MAC_CTRL_CFG); 3660 cas_start_dma(cp); 3661 } 3662 3663 /* Must be invoked under cp->lock. */ 3664 static void cas_init_hw(struct cas *cp, int restart_link) 3665 { 3666 if (restart_link) 3667 cas_phy_init(cp); 3668 3669 cas_init_pause_thresholds(cp); 3670 cas_init_mac(cp); 3671 cas_init_dma(cp); 3672 3673 if (restart_link) { 3674 /* Default aneg parameters */ 3675 cp->timer_ticks = 0; 3676 cas_begin_auto_negotiation(cp, NULL); 3677 } else if (cp->lstate == link_up) { 3678 cas_set_link_modes(cp); 3679 netif_carrier_on(cp->dev); 3680 } 3681 } 3682 3683 /* Must be invoked under cp->lock. on earlier cassini boards, 3684 * SOFT_0 is tied to PCI reset. we use this to force a pci reset, 3685 * let it settle out, and then restore pci state. 3686 */ 3687 static void cas_hard_reset(struct cas *cp) 3688 { 3689 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3690 udelay(20); 3691 pci_restore_state(cp->pdev); 3692 } 3693 3694 3695 static void cas_global_reset(struct cas *cp, int blkflag) 3696 { 3697 int limit; 3698 3699 /* issue a global reset. don't use RSTOUT. */ 3700 if (blkflag && !CAS_PHY_MII(cp->phy_type)) { 3701 /* For PCS, when the blkflag is set, we should set the 3702 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of 3703 * the last autonegotiation from being cleared. We'll 3704 * need some special handling if the chip is set into a 3705 * loopback mode. 3706 */ 3707 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), 3708 cp->regs + REG_SW_RESET); 3709 } else { 3710 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); 3711 } 3712 3713 /* need to wait at least 3ms before polling register */ 3714 mdelay(3); 3715 3716 limit = STOP_TRIES; 3717 while (limit-- > 0) { 3718 u32 val = readl(cp->regs + REG_SW_RESET); 3719 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0) 3720 goto done; 3721 udelay(10); 3722 } 3723 netdev_err(cp->dev, "sw reset failed\n"); 3724 3725 done: 3726 /* enable various BIM interrupts */ 3727 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | 3728 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG); 3729 3730 /* clear out pci error status mask for handled errors. 3731 * we don't deal with DMA counter overflows as they happen 3732 * all the time. 3733 */ 3734 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | 3735 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE | 3736 PCI_ERR_BIM_DMA_READ), cp->regs + 3737 REG_PCI_ERR_STATUS_MASK); 3738 3739 /* set up for MII by default to address mac rx reset timeout 3740 * issue 3741 */ 3742 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3743 } 3744 3745 static void cas_reset(struct cas *cp, int blkflag) 3746 { 3747 u32 val; 3748 3749 cas_mask_intr(cp); 3750 cas_global_reset(cp, blkflag); 3751 cas_mac_reset(cp); 3752 cas_entropy_reset(cp); 3753 3754 /* disable dma engines. */ 3755 val = readl(cp->regs + REG_TX_CFG); 3756 val &= ~TX_CFG_DMA_EN; 3757 writel(val, cp->regs + REG_TX_CFG); 3758 3759 val = readl(cp->regs + REG_RX_CFG); 3760 val &= ~RX_CFG_DMA_EN; 3761 writel(val, cp->regs + REG_RX_CFG); 3762 3763 /* program header parser */ 3764 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || 3765 (&CAS_HP_ALT_FIRMWARE[0] == &cas_prog_null[0])) { 3766 cas_load_firmware(cp, CAS_HP_FIRMWARE); 3767 } else { 3768 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); 3769 } 3770 3771 /* clear out error registers */ 3772 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3773 cas_clear_mac_err(cp); 3774 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3775 } 3776 3777 /* Shut down the chip, must be called with pm_mutex held. */ 3778 static void cas_shutdown(struct cas *cp) 3779 { 3780 unsigned long flags; 3781 3782 /* Make us not-running to avoid timers respawning */ 3783 cp->hw_running = 0; 3784 3785 del_timer_sync(&cp->link_timer); 3786 3787 /* Stop the reset task */ 3788 #if 0 3789 while (atomic_read(&cp->reset_task_pending_mtu) || 3790 atomic_read(&cp->reset_task_pending_spare) || 3791 atomic_read(&cp->reset_task_pending_all)) 3792 schedule(); 3793 3794 #else 3795 while (atomic_read(&cp->reset_task_pending)) 3796 schedule(); 3797 #endif 3798 /* Actually stop the chip */ 3799 cas_lock_all_save(cp, flags); 3800 cas_reset(cp, 0); 3801 if (cp->cas_flags & CAS_FLAG_SATURN) 3802 cas_phy_powerdown(cp); 3803 cas_unlock_all_restore(cp, flags); 3804 } 3805 3806 static int cas_change_mtu(struct net_device *dev, int new_mtu) 3807 { 3808 struct cas *cp = netdev_priv(dev); 3809 3810 dev->mtu = new_mtu; 3811 if (!netif_running(dev) || !netif_device_present(dev)) 3812 return 0; 3813 3814 /* let the reset task handle it */ 3815 #if 1 3816 atomic_inc(&cp->reset_task_pending); 3817 if ((cp->phy_type & CAS_PHY_SERDES)) { 3818 atomic_inc(&cp->reset_task_pending_all); 3819 } else { 3820 atomic_inc(&cp->reset_task_pending_mtu); 3821 } 3822 schedule_work(&cp->reset_task); 3823 #else 3824 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ? 3825 CAS_RESET_ALL : CAS_RESET_MTU); 3826 pr_err("reset called in cas_change_mtu\n"); 3827 schedule_work(&cp->reset_task); 3828 #endif 3829 3830 flush_work(&cp->reset_task); 3831 return 0; 3832 } 3833 3834 static void cas_clean_txd(struct cas *cp, int ring) 3835 { 3836 struct cas_tx_desc *txd = cp->init_txds[ring]; 3837 struct sk_buff *skb, **skbs = cp->tx_skbs[ring]; 3838 u64 daddr, dlen; 3839 int i, size; 3840 3841 size = TX_DESC_RINGN_SIZE(ring); 3842 for (i = 0; i < size; i++) { 3843 int frag; 3844 3845 if (skbs[i] == NULL) 3846 continue; 3847 3848 skb = skbs[i]; 3849 skbs[i] = NULL; 3850 3851 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 3852 int ent = i & (size - 1); 3853 3854 /* first buffer is never a tiny buffer and so 3855 * needs to be unmapped. 3856 */ 3857 daddr = le64_to_cpu(txd[ent].buffer); 3858 dlen = CAS_VAL(TX_DESC_BUFLEN, 3859 le64_to_cpu(txd[ent].control)); 3860 dma_unmap_page(&cp->pdev->dev, daddr, dlen, 3861 DMA_TO_DEVICE); 3862 3863 if (frag != skb_shinfo(skb)->nr_frags) { 3864 i++; 3865 3866 /* next buffer might by a tiny buffer. 3867 * skip past it. 3868 */ 3869 ent = i & (size - 1); 3870 if (cp->tx_tiny_use[ring][ent].used) 3871 i++; 3872 } 3873 } 3874 dev_kfree_skb_any(skb); 3875 } 3876 3877 /* zero out tiny buf usage */ 3878 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring])); 3879 } 3880 3881 /* freed on close */ 3882 static inline void cas_free_rx_desc(struct cas *cp, int ring) 3883 { 3884 cas_page_t **page = cp->rx_pages[ring]; 3885 int i, size; 3886 3887 size = RX_DESC_RINGN_SIZE(ring); 3888 for (i = 0; i < size; i++) { 3889 if (page[i]) { 3890 cas_page_free(cp, page[i]); 3891 page[i] = NULL; 3892 } 3893 } 3894 } 3895 3896 static void cas_free_rxds(struct cas *cp) 3897 { 3898 int i; 3899 3900 for (i = 0; i < N_RX_DESC_RINGS; i++) 3901 cas_free_rx_desc(cp, i); 3902 } 3903 3904 /* Must be invoked under cp->lock. */ 3905 static void cas_clean_rings(struct cas *cp) 3906 { 3907 int i; 3908 3909 /* need to clean all tx rings */ 3910 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS); 3911 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS); 3912 for (i = 0; i < N_TX_RINGS; i++) 3913 cas_clean_txd(cp, i); 3914 3915 /* zero out init block */ 3916 memset(cp->init_block, 0, sizeof(struct cas_init_block)); 3917 cas_clean_rxds(cp); 3918 cas_clean_rxcs(cp); 3919 } 3920 3921 /* allocated on open */ 3922 static inline int cas_alloc_rx_desc(struct cas *cp, int ring) 3923 { 3924 cas_page_t **page = cp->rx_pages[ring]; 3925 int size, i = 0; 3926 3927 size = RX_DESC_RINGN_SIZE(ring); 3928 for (i = 0; i < size; i++) { 3929 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL) 3930 return -1; 3931 } 3932 return 0; 3933 } 3934 3935 static int cas_alloc_rxds(struct cas *cp) 3936 { 3937 int i; 3938 3939 for (i = 0; i < N_RX_DESC_RINGS; i++) { 3940 if (cas_alloc_rx_desc(cp, i) < 0) { 3941 cas_free_rxds(cp); 3942 return -1; 3943 } 3944 } 3945 return 0; 3946 } 3947 3948 static void cas_reset_task(struct work_struct *work) 3949 { 3950 struct cas *cp = container_of(work, struct cas, reset_task); 3951 #if 0 3952 int pending = atomic_read(&cp->reset_task_pending); 3953 #else 3954 int pending_all = atomic_read(&cp->reset_task_pending_all); 3955 int pending_spare = atomic_read(&cp->reset_task_pending_spare); 3956 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu); 3957 3958 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) { 3959 /* We can have more tasks scheduled than actually 3960 * needed. 3961 */ 3962 atomic_dec(&cp->reset_task_pending); 3963 return; 3964 } 3965 #endif 3966 /* The link went down, we reset the ring, but keep 3967 * DMA stopped. Use this function for reset 3968 * on error as well. 3969 */ 3970 if (cp->hw_running) { 3971 unsigned long flags; 3972 3973 /* Make sure we don't get interrupts or tx packets */ 3974 netif_device_detach(cp->dev); 3975 cas_lock_all_save(cp, flags); 3976 3977 if (cp->opened) { 3978 /* We call cas_spare_recover when we call cas_open. 3979 * but we do not initialize the lists cas_spare_recover 3980 * uses until cas_open is called. 3981 */ 3982 cas_spare_recover(cp, GFP_ATOMIC); 3983 } 3984 #if 1 3985 /* test => only pending_spare set */ 3986 if (!pending_all && !pending_mtu) 3987 goto done; 3988 #else 3989 if (pending == CAS_RESET_SPARE) 3990 goto done; 3991 #endif 3992 /* when pending == CAS_RESET_ALL, the following 3993 * call to cas_init_hw will restart auto negotiation. 3994 * Setting the second argument of cas_reset to 3995 * !(pending == CAS_RESET_ALL) will set this argument 3996 * to 1 (avoiding reinitializing the PHY for the normal 3997 * PCS case) when auto negotiation is not restarted. 3998 */ 3999 #if 1 4000 cas_reset(cp, !(pending_all > 0)); 4001 if (cp->opened) 4002 cas_clean_rings(cp); 4003 cas_init_hw(cp, (pending_all > 0)); 4004 #else 4005 cas_reset(cp, !(pending == CAS_RESET_ALL)); 4006 if (cp->opened) 4007 cas_clean_rings(cp); 4008 cas_init_hw(cp, pending == CAS_RESET_ALL); 4009 #endif 4010 4011 done: 4012 cas_unlock_all_restore(cp, flags); 4013 netif_device_attach(cp->dev); 4014 } 4015 #if 1 4016 atomic_sub(pending_all, &cp->reset_task_pending_all); 4017 atomic_sub(pending_spare, &cp->reset_task_pending_spare); 4018 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu); 4019 atomic_dec(&cp->reset_task_pending); 4020 #else 4021 atomic_set(&cp->reset_task_pending, 0); 4022 #endif 4023 } 4024 4025 static void cas_link_timer(struct timer_list *t) 4026 { 4027 struct cas *cp = from_timer(cp, t, link_timer); 4028 int mask, pending = 0, reset = 0; 4029 unsigned long flags; 4030 4031 if (link_transition_timeout != 0 && 4032 cp->link_transition_jiffies_valid && 4033 time_is_before_jiffies(cp->link_transition_jiffies + 4034 link_transition_timeout)) { 4035 /* One-second counter so link-down workaround doesn't 4036 * cause resets to occur so fast as to fool the switch 4037 * into thinking the link is down. 4038 */ 4039 cp->link_transition_jiffies_valid = 0; 4040 } 4041 4042 if (!cp->hw_running) 4043 return; 4044 4045 spin_lock_irqsave(&cp->lock, flags); 4046 cas_lock_tx(cp); 4047 cas_entropy_gather(cp); 4048 4049 /* If the link task is still pending, we just 4050 * reschedule the link timer 4051 */ 4052 #if 1 4053 if (atomic_read(&cp->reset_task_pending_all) || 4054 atomic_read(&cp->reset_task_pending_spare) || 4055 atomic_read(&cp->reset_task_pending_mtu)) 4056 goto done; 4057 #else 4058 if (atomic_read(&cp->reset_task_pending)) 4059 goto done; 4060 #endif 4061 4062 /* check for rx cleaning */ 4063 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { 4064 int i, rmask; 4065 4066 for (i = 0; i < MAX_RX_DESC_RINGS; i++) { 4067 rmask = CAS_FLAG_RXD_POST(i); 4068 if ((mask & rmask) == 0) 4069 continue; 4070 4071 /* post_rxds will do a mod_timer */ 4072 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) { 4073 pending = 1; 4074 continue; 4075 } 4076 cp->cas_flags &= ~rmask; 4077 } 4078 } 4079 4080 if (CAS_PHY_MII(cp->phy_type)) { 4081 u16 bmsr; 4082 cas_mif_poll(cp, 0); 4083 bmsr = cas_phy_read(cp, MII_BMSR); 4084 /* WTZ: Solaris driver reads this twice, but that 4085 * may be due to the PCS case and the use of a 4086 * common implementation. Read it twice here to be 4087 * safe. 4088 */ 4089 bmsr = cas_phy_read(cp, MII_BMSR); 4090 cas_mif_poll(cp, 1); 4091 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ 4092 reset = cas_mii_link_check(cp, bmsr); 4093 } else { 4094 reset = cas_pcs_link_check(cp); 4095 } 4096 4097 if (reset) 4098 goto done; 4099 4100 /* check for tx state machine confusion */ 4101 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { 4102 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); 4103 u32 wptr, rptr; 4104 int tlm = CAS_VAL(MAC_SM_TLM, val); 4105 4106 if (((tlm == 0x5) || (tlm == 0x3)) && 4107 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) { 4108 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, 4109 "tx err: MAC_STATE[%08x]\n", val); 4110 reset = 1; 4111 goto done; 4112 } 4113 4114 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); 4115 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); 4116 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); 4117 if ((val == 0) && (wptr != rptr)) { 4118 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, 4119 "tx err: TX_FIFO[%08x:%08x:%08x]\n", 4120 val, wptr, rptr); 4121 reset = 1; 4122 } 4123 4124 if (reset) 4125 cas_hard_reset(cp); 4126 } 4127 4128 done: 4129 if (reset) { 4130 #if 1 4131 atomic_inc(&cp->reset_task_pending); 4132 atomic_inc(&cp->reset_task_pending_all); 4133 schedule_work(&cp->reset_task); 4134 #else 4135 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 4136 pr_err("reset called in cas_link_timer\n"); 4137 schedule_work(&cp->reset_task); 4138 #endif 4139 } 4140 4141 if (!pending) 4142 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 4143 cas_unlock_tx(cp); 4144 spin_unlock_irqrestore(&cp->lock, flags); 4145 } 4146 4147 /* tiny buffers are used to avoid target abort issues with 4148 * older cassini's 4149 */ 4150 static void cas_tx_tiny_free(struct cas *cp) 4151 { 4152 struct pci_dev *pdev = cp->pdev; 4153 int i; 4154 4155 for (i = 0; i < N_TX_RINGS; i++) { 4156 if (!cp->tx_tiny_bufs[i]) 4157 continue; 4158 4159 dma_free_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, 4160 cp->tx_tiny_bufs[i], cp->tx_tiny_dvma[i]); 4161 cp->tx_tiny_bufs[i] = NULL; 4162 } 4163 } 4164 4165 static int cas_tx_tiny_alloc(struct cas *cp) 4166 { 4167 struct pci_dev *pdev = cp->pdev; 4168 int i; 4169 4170 for (i = 0; i < N_TX_RINGS; i++) { 4171 cp->tx_tiny_bufs[i] = 4172 dma_alloc_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, 4173 &cp->tx_tiny_dvma[i], GFP_KERNEL); 4174 if (!cp->tx_tiny_bufs[i]) { 4175 cas_tx_tiny_free(cp); 4176 return -1; 4177 } 4178 } 4179 return 0; 4180 } 4181 4182 4183 static int cas_open(struct net_device *dev) 4184 { 4185 struct cas *cp = netdev_priv(dev); 4186 int hw_was_up, err; 4187 unsigned long flags; 4188 4189 mutex_lock(&cp->pm_mutex); 4190 4191 hw_was_up = cp->hw_running; 4192 4193 /* The power-management mutex protects the hw_running 4194 * etc. state so it is safe to do this bit without cp->lock 4195 */ 4196 if (!cp->hw_running) { 4197 /* Reset the chip */ 4198 cas_lock_all_save(cp, flags); 4199 /* We set the second arg to cas_reset to zero 4200 * because cas_init_hw below will have its second 4201 * argument set to non-zero, which will force 4202 * autonegotiation to start. 4203 */ 4204 cas_reset(cp, 0); 4205 cp->hw_running = 1; 4206 cas_unlock_all_restore(cp, flags); 4207 } 4208 4209 err = -ENOMEM; 4210 if (cas_tx_tiny_alloc(cp) < 0) 4211 goto err_unlock; 4212 4213 /* alloc rx descriptors */ 4214 if (cas_alloc_rxds(cp) < 0) 4215 goto err_tx_tiny; 4216 4217 /* allocate spares */ 4218 cas_spare_init(cp); 4219 cas_spare_recover(cp, GFP_KERNEL); 4220 4221 /* We can now request the interrupt as we know it's masked 4222 * on the controller. cassini+ has up to 4 interrupts 4223 * that can be used, but you need to do explicit pci interrupt 4224 * mapping to expose them 4225 */ 4226 if (request_irq(cp->pdev->irq, cas_interrupt, 4227 IRQF_SHARED, dev->name, (void *) dev)) { 4228 netdev_err(cp->dev, "failed to request irq !\n"); 4229 err = -EAGAIN; 4230 goto err_spare; 4231 } 4232 4233 #ifdef USE_NAPI 4234 napi_enable(&cp->napi); 4235 #endif 4236 /* init hw */ 4237 cas_lock_all_save(cp, flags); 4238 cas_clean_rings(cp); 4239 cas_init_hw(cp, !hw_was_up); 4240 cp->opened = 1; 4241 cas_unlock_all_restore(cp, flags); 4242 4243 netif_start_queue(dev); 4244 mutex_unlock(&cp->pm_mutex); 4245 return 0; 4246 4247 err_spare: 4248 cas_spare_free(cp); 4249 cas_free_rxds(cp); 4250 err_tx_tiny: 4251 cas_tx_tiny_free(cp); 4252 err_unlock: 4253 mutex_unlock(&cp->pm_mutex); 4254 return err; 4255 } 4256 4257 static int cas_close(struct net_device *dev) 4258 { 4259 unsigned long flags; 4260 struct cas *cp = netdev_priv(dev); 4261 4262 #ifdef USE_NAPI 4263 napi_disable(&cp->napi); 4264 #endif 4265 /* Make sure we don't get distracted by suspend/resume */ 4266 mutex_lock(&cp->pm_mutex); 4267 4268 netif_stop_queue(dev); 4269 4270 /* Stop traffic, mark us closed */ 4271 cas_lock_all_save(cp, flags); 4272 cp->opened = 0; 4273 cas_reset(cp, 0); 4274 cas_phy_init(cp); 4275 cas_begin_auto_negotiation(cp, NULL); 4276 cas_clean_rings(cp); 4277 cas_unlock_all_restore(cp, flags); 4278 4279 free_irq(cp->pdev->irq, (void *) dev); 4280 cas_spare_free(cp); 4281 cas_free_rxds(cp); 4282 cas_tx_tiny_free(cp); 4283 mutex_unlock(&cp->pm_mutex); 4284 return 0; 4285 } 4286 4287 static struct { 4288 const char name[ETH_GSTRING_LEN]; 4289 } ethtool_cassini_statnames[] = { 4290 {"collisions"}, 4291 {"rx_bytes"}, 4292 {"rx_crc_errors"}, 4293 {"rx_dropped"}, 4294 {"rx_errors"}, 4295 {"rx_fifo_errors"}, 4296 {"rx_frame_errors"}, 4297 {"rx_length_errors"}, 4298 {"rx_over_errors"}, 4299 {"rx_packets"}, 4300 {"tx_aborted_errors"}, 4301 {"tx_bytes"}, 4302 {"tx_dropped"}, 4303 {"tx_errors"}, 4304 {"tx_fifo_errors"}, 4305 {"tx_packets"} 4306 }; 4307 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames) 4308 4309 static struct { 4310 const int offsets; /* neg. values for 2nd arg to cas_read_phy */ 4311 } ethtool_register_table[] = { 4312 {-MII_BMSR}, 4313 {-MII_BMCR}, 4314 {REG_CAWR}, 4315 {REG_INF_BURST}, 4316 {REG_BIM_CFG}, 4317 {REG_RX_CFG}, 4318 {REG_HP_CFG}, 4319 {REG_MAC_TX_CFG}, 4320 {REG_MAC_RX_CFG}, 4321 {REG_MAC_CTRL_CFG}, 4322 {REG_MAC_XIF_CFG}, 4323 {REG_MIF_CFG}, 4324 {REG_PCS_CFG}, 4325 {REG_SATURN_PCFG}, 4326 {REG_PCS_MII_STATUS}, 4327 {REG_PCS_STATE_MACHINE}, 4328 {REG_MAC_COLL_EXCESS}, 4329 {REG_MAC_COLL_LATE} 4330 }; 4331 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table) 4332 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN) 4333 4334 static void cas_read_regs(struct cas *cp, u8 *ptr, int len) 4335 { 4336 u8 *p; 4337 int i; 4338 unsigned long flags; 4339 4340 spin_lock_irqsave(&cp->lock, flags); 4341 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) { 4342 u16 hval; 4343 u32 val; 4344 if (ethtool_register_table[i].offsets < 0) { 4345 hval = cas_phy_read(cp, 4346 -ethtool_register_table[i].offsets); 4347 val = hval; 4348 } else { 4349 val= readl(cp->regs+ethtool_register_table[i].offsets); 4350 } 4351 memcpy(p, (u8 *)&val, sizeof(u32)); 4352 } 4353 spin_unlock_irqrestore(&cp->lock, flags); 4354 } 4355 4356 static struct net_device_stats *cas_get_stats(struct net_device *dev) 4357 { 4358 struct cas *cp = netdev_priv(dev); 4359 struct net_device_stats *stats = cp->net_stats; 4360 unsigned long flags; 4361 int i; 4362 unsigned long tmp; 4363 4364 /* we collate all of the stats into net_stats[N_TX_RING] */ 4365 if (!cp->hw_running) 4366 return stats + N_TX_RINGS; 4367 4368 /* collect outstanding stats */ 4369 /* WTZ: the Cassini spec gives these as 16 bit counters but 4370 * stored in 32-bit words. Added a mask of 0xffff to be safe, 4371 * in case the chip somehow puts any garbage in the other bits. 4372 * Also, counter usage didn't seem to mach what Adrian did 4373 * in the parts of the code that set these quantities. Made 4374 * that consistent. 4375 */ 4376 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags); 4377 stats[N_TX_RINGS].rx_crc_errors += 4378 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; 4379 stats[N_TX_RINGS].rx_frame_errors += 4380 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; 4381 stats[N_TX_RINGS].rx_length_errors += 4382 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; 4383 #if 1 4384 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + 4385 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); 4386 stats[N_TX_RINGS].tx_aborted_errors += tmp; 4387 stats[N_TX_RINGS].collisions += 4388 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); 4389 #else 4390 stats[N_TX_RINGS].tx_aborted_errors += 4391 readl(cp->regs + REG_MAC_COLL_EXCESS); 4392 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) + 4393 readl(cp->regs + REG_MAC_COLL_LATE); 4394 #endif 4395 cas_clear_mac_err(cp); 4396 4397 /* saved bits that are unique to ring 0 */ 4398 spin_lock(&cp->stat_lock[0]); 4399 stats[N_TX_RINGS].collisions += stats[0].collisions; 4400 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors; 4401 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors; 4402 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors; 4403 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors; 4404 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors; 4405 spin_unlock(&cp->stat_lock[0]); 4406 4407 for (i = 0; i < N_TX_RINGS; i++) { 4408 spin_lock(&cp->stat_lock[i]); 4409 stats[N_TX_RINGS].rx_length_errors += 4410 stats[i].rx_length_errors; 4411 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors; 4412 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets; 4413 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets; 4414 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes; 4415 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes; 4416 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors; 4417 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors; 4418 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped; 4419 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped; 4420 memset(stats + i, 0, sizeof(struct net_device_stats)); 4421 spin_unlock(&cp->stat_lock[i]); 4422 } 4423 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags); 4424 return stats + N_TX_RINGS; 4425 } 4426 4427 4428 static void cas_set_multicast(struct net_device *dev) 4429 { 4430 struct cas *cp = netdev_priv(dev); 4431 u32 rxcfg, rxcfg_new; 4432 unsigned long flags; 4433 int limit = STOP_TRIES; 4434 4435 if (!cp->hw_running) 4436 return; 4437 4438 spin_lock_irqsave(&cp->lock, flags); 4439 rxcfg = readl(cp->regs + REG_MAC_RX_CFG); 4440 4441 /* disable RX MAC and wait for completion */ 4442 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4443 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { 4444 if (!limit--) 4445 break; 4446 udelay(10); 4447 } 4448 4449 /* disable hash filter and wait for completion */ 4450 limit = STOP_TRIES; 4451 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN); 4452 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4453 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { 4454 if (!limit--) 4455 break; 4456 udelay(10); 4457 } 4458 4459 /* program hash filters */ 4460 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp); 4461 rxcfg |= rxcfg_new; 4462 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); 4463 spin_unlock_irqrestore(&cp->lock, flags); 4464 } 4465 4466 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 4467 { 4468 struct cas *cp = netdev_priv(dev); 4469 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 4470 strscpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 4471 strscpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info)); 4472 } 4473 4474 static int cas_get_link_ksettings(struct net_device *dev, 4475 struct ethtool_link_ksettings *cmd) 4476 { 4477 struct cas *cp = netdev_priv(dev); 4478 u16 bmcr; 4479 int full_duplex, speed, pause; 4480 unsigned long flags; 4481 enum link_state linkstate = link_up; 4482 u32 supported, advertising; 4483 4484 advertising = 0; 4485 supported = SUPPORTED_Autoneg; 4486 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 4487 supported |= SUPPORTED_1000baseT_Full; 4488 advertising |= ADVERTISED_1000baseT_Full; 4489 } 4490 4491 /* Record PHY settings if HW is on. */ 4492 spin_lock_irqsave(&cp->lock, flags); 4493 bmcr = 0; 4494 linkstate = cp->lstate; 4495 if (CAS_PHY_MII(cp->phy_type)) { 4496 cmd->base.port = PORT_MII; 4497 cmd->base.phy_address = cp->phy_addr; 4498 advertising |= ADVERTISED_TP | ADVERTISED_MII | 4499 ADVERTISED_10baseT_Half | 4500 ADVERTISED_10baseT_Full | 4501 ADVERTISED_100baseT_Half | 4502 ADVERTISED_100baseT_Full; 4503 4504 supported |= 4505 (SUPPORTED_10baseT_Half | 4506 SUPPORTED_10baseT_Full | 4507 SUPPORTED_100baseT_Half | 4508 SUPPORTED_100baseT_Full | 4509 SUPPORTED_TP | SUPPORTED_MII); 4510 4511 if (cp->hw_running) { 4512 cas_mif_poll(cp, 0); 4513 bmcr = cas_phy_read(cp, MII_BMCR); 4514 cas_read_mii_link_mode(cp, &full_duplex, 4515 &speed, &pause); 4516 cas_mif_poll(cp, 1); 4517 } 4518 4519 } else { 4520 cmd->base.port = PORT_FIBRE; 4521 cmd->base.phy_address = 0; 4522 supported |= SUPPORTED_FIBRE; 4523 advertising |= ADVERTISED_FIBRE; 4524 4525 if (cp->hw_running) { 4526 /* pcs uses the same bits as mii */ 4527 bmcr = readl(cp->regs + REG_PCS_MII_CTRL); 4528 cas_read_pcs_link_mode(cp, &full_duplex, 4529 &speed, &pause); 4530 } 4531 } 4532 spin_unlock_irqrestore(&cp->lock, flags); 4533 4534 if (bmcr & BMCR_ANENABLE) { 4535 advertising |= ADVERTISED_Autoneg; 4536 cmd->base.autoneg = AUTONEG_ENABLE; 4537 cmd->base.speed = ((speed == 10) ? 4538 SPEED_10 : 4539 ((speed == 1000) ? 4540 SPEED_1000 : SPEED_100)); 4541 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 4542 } else { 4543 cmd->base.autoneg = AUTONEG_DISABLE; 4544 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ? 4545 SPEED_1000 : 4546 ((bmcr & BMCR_SPEED100) ? 4547 SPEED_100 : SPEED_10)); 4548 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? 4549 DUPLEX_FULL : DUPLEX_HALF; 4550 } 4551 if (linkstate != link_up) { 4552 /* Force these to "unknown" if the link is not up and 4553 * autonogotiation in enabled. We can set the link 4554 * speed to 0, but not cmd->duplex, 4555 * because its legal values are 0 and 1. Ethtool will 4556 * print the value reported in parentheses after the 4557 * word "Unknown" for unrecognized values. 4558 * 4559 * If in forced mode, we report the speed and duplex 4560 * settings that we configured. 4561 */ 4562 if (cp->link_cntl & BMCR_ANENABLE) { 4563 cmd->base.speed = 0; 4564 cmd->base.duplex = 0xff; 4565 } else { 4566 cmd->base.speed = SPEED_10; 4567 if (cp->link_cntl & BMCR_SPEED100) { 4568 cmd->base.speed = SPEED_100; 4569 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) { 4570 cmd->base.speed = SPEED_1000; 4571 } 4572 cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ? 4573 DUPLEX_FULL : DUPLEX_HALF; 4574 } 4575 } 4576 4577 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 4578 supported); 4579 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 4580 advertising); 4581 4582 return 0; 4583 } 4584 4585 static int cas_set_link_ksettings(struct net_device *dev, 4586 const struct ethtool_link_ksettings *cmd) 4587 { 4588 struct cas *cp = netdev_priv(dev); 4589 unsigned long flags; 4590 u32 speed = cmd->base.speed; 4591 4592 /* Verify the settings we care about. */ 4593 if (cmd->base.autoneg != AUTONEG_ENABLE && 4594 cmd->base.autoneg != AUTONEG_DISABLE) 4595 return -EINVAL; 4596 4597 if (cmd->base.autoneg == AUTONEG_DISABLE && 4598 ((speed != SPEED_1000 && 4599 speed != SPEED_100 && 4600 speed != SPEED_10) || 4601 (cmd->base.duplex != DUPLEX_HALF && 4602 cmd->base.duplex != DUPLEX_FULL))) 4603 return -EINVAL; 4604 4605 /* Apply settings and restart link process. */ 4606 spin_lock_irqsave(&cp->lock, flags); 4607 cas_begin_auto_negotiation(cp, cmd); 4608 spin_unlock_irqrestore(&cp->lock, flags); 4609 return 0; 4610 } 4611 4612 static int cas_nway_reset(struct net_device *dev) 4613 { 4614 struct cas *cp = netdev_priv(dev); 4615 unsigned long flags; 4616 4617 if ((cp->link_cntl & BMCR_ANENABLE) == 0) 4618 return -EINVAL; 4619 4620 /* Restart link process. */ 4621 spin_lock_irqsave(&cp->lock, flags); 4622 cas_begin_auto_negotiation(cp, NULL); 4623 spin_unlock_irqrestore(&cp->lock, flags); 4624 4625 return 0; 4626 } 4627 4628 static u32 cas_get_link(struct net_device *dev) 4629 { 4630 struct cas *cp = netdev_priv(dev); 4631 return cp->lstate == link_up; 4632 } 4633 4634 static u32 cas_get_msglevel(struct net_device *dev) 4635 { 4636 struct cas *cp = netdev_priv(dev); 4637 return cp->msg_enable; 4638 } 4639 4640 static void cas_set_msglevel(struct net_device *dev, u32 value) 4641 { 4642 struct cas *cp = netdev_priv(dev); 4643 cp->msg_enable = value; 4644 } 4645 4646 static int cas_get_regs_len(struct net_device *dev) 4647 { 4648 struct cas *cp = netdev_priv(dev); 4649 return min_t(int, cp->casreg_len, CAS_MAX_REGS); 4650 } 4651 4652 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4653 void *p) 4654 { 4655 struct cas *cp = netdev_priv(dev); 4656 regs->version = 0; 4657 /* cas_read_regs handles locks (cp->lock). */ 4658 cas_read_regs(cp, p, regs->len / sizeof(u32)); 4659 } 4660 4661 static int cas_get_sset_count(struct net_device *dev, int sset) 4662 { 4663 switch (sset) { 4664 case ETH_SS_STATS: 4665 return CAS_NUM_STAT_KEYS; 4666 default: 4667 return -EOPNOTSUPP; 4668 } 4669 } 4670 4671 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4672 { 4673 memcpy(data, ðtool_cassini_statnames, 4674 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN); 4675 } 4676 4677 static void cas_get_ethtool_stats(struct net_device *dev, 4678 struct ethtool_stats *estats, u64 *data) 4679 { 4680 struct cas *cp = netdev_priv(dev); 4681 struct net_device_stats *stats = cas_get_stats(cp->dev); 4682 int i = 0; 4683 data[i++] = stats->collisions; 4684 data[i++] = stats->rx_bytes; 4685 data[i++] = stats->rx_crc_errors; 4686 data[i++] = stats->rx_dropped; 4687 data[i++] = stats->rx_errors; 4688 data[i++] = stats->rx_fifo_errors; 4689 data[i++] = stats->rx_frame_errors; 4690 data[i++] = stats->rx_length_errors; 4691 data[i++] = stats->rx_over_errors; 4692 data[i++] = stats->rx_packets; 4693 data[i++] = stats->tx_aborted_errors; 4694 data[i++] = stats->tx_bytes; 4695 data[i++] = stats->tx_dropped; 4696 data[i++] = stats->tx_errors; 4697 data[i++] = stats->tx_fifo_errors; 4698 data[i++] = stats->tx_packets; 4699 BUG_ON(i != CAS_NUM_STAT_KEYS); 4700 } 4701 4702 static const struct ethtool_ops cas_ethtool_ops = { 4703 .get_drvinfo = cas_get_drvinfo, 4704 .nway_reset = cas_nway_reset, 4705 .get_link = cas_get_link, 4706 .get_msglevel = cas_get_msglevel, 4707 .set_msglevel = cas_set_msglevel, 4708 .get_regs_len = cas_get_regs_len, 4709 .get_regs = cas_get_regs, 4710 .get_sset_count = cas_get_sset_count, 4711 .get_strings = cas_get_strings, 4712 .get_ethtool_stats = cas_get_ethtool_stats, 4713 .get_link_ksettings = cas_get_link_ksettings, 4714 .set_link_ksettings = cas_set_link_ksettings, 4715 }; 4716 4717 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4718 { 4719 struct cas *cp = netdev_priv(dev); 4720 struct mii_ioctl_data *data = if_mii(ifr); 4721 unsigned long flags; 4722 int rc = -EOPNOTSUPP; 4723 4724 /* Hold the PM mutex while doing ioctl's or we may collide 4725 * with open/close and power management and oops. 4726 */ 4727 mutex_lock(&cp->pm_mutex); 4728 switch (cmd) { 4729 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 4730 data->phy_id = cp->phy_addr; 4731 fallthrough; 4732 4733 case SIOCGMIIREG: /* Read MII PHY register. */ 4734 spin_lock_irqsave(&cp->lock, flags); 4735 cas_mif_poll(cp, 0); 4736 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); 4737 cas_mif_poll(cp, 1); 4738 spin_unlock_irqrestore(&cp->lock, flags); 4739 rc = 0; 4740 break; 4741 4742 case SIOCSMIIREG: /* Write MII PHY register. */ 4743 spin_lock_irqsave(&cp->lock, flags); 4744 cas_mif_poll(cp, 0); 4745 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); 4746 cas_mif_poll(cp, 1); 4747 spin_unlock_irqrestore(&cp->lock, flags); 4748 break; 4749 default: 4750 break; 4751 } 4752 4753 mutex_unlock(&cp->pm_mutex); 4754 return rc; 4755 } 4756 4757 /* When this chip sits underneath an Intel 31154 bridge, it is the 4758 * only subordinate device and we can tweak the bridge settings to 4759 * reflect that fact. 4760 */ 4761 static void cas_program_bridge(struct pci_dev *cas_pdev) 4762 { 4763 struct pci_dev *pdev = cas_pdev->bus->self; 4764 u32 val; 4765 4766 if (!pdev) 4767 return; 4768 4769 if (pdev->vendor != 0x8086 || pdev->device != 0x537c) 4770 return; 4771 4772 /* Clear bit 10 (Bus Parking Control) in the Secondary 4773 * Arbiter Control/Status Register which lives at offset 4774 * 0x41. Using a 32-bit word read/modify/write at 0x40 4775 * is much simpler so that's how we do this. 4776 */ 4777 pci_read_config_dword(pdev, 0x40, &val); 4778 val &= ~0x00040000; 4779 pci_write_config_dword(pdev, 0x40, val); 4780 4781 /* Max out the Multi-Transaction Timer settings since 4782 * Cassini is the only device present. 4783 * 4784 * The register is 16-bit and lives at 0x50. When the 4785 * settings are enabled, it extends the GRANT# signal 4786 * for a requestor after a transaction is complete. This 4787 * allows the next request to run without first needing 4788 * to negotiate the GRANT# signal back. 4789 * 4790 * Bits 12:10 define the grant duration: 4791 * 4792 * 1 -- 16 clocks 4793 * 2 -- 32 clocks 4794 * 3 -- 64 clocks 4795 * 4 -- 128 clocks 4796 * 5 -- 256 clocks 4797 * 4798 * All other values are illegal. 4799 * 4800 * Bits 09:00 define which REQ/GNT signal pairs get the 4801 * GRANT# signal treatment. We set them all. 4802 */ 4803 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff); 4804 4805 /* The Read Prefecth Policy register is 16-bit and sits at 4806 * offset 0x52. It enables a "smart" pre-fetch policy. We 4807 * enable it and max out all of the settings since only one 4808 * device is sitting underneath and thus bandwidth sharing is 4809 * not an issue. 4810 * 4811 * The register has several 3 bit fields, which indicates a 4812 * multiplier applied to the base amount of prefetching the 4813 * chip would do. These fields are at: 4814 * 4815 * 15:13 --- ReRead Primary Bus 4816 * 12:10 --- FirstRead Primary Bus 4817 * 09:07 --- ReRead Secondary Bus 4818 * 06:04 --- FirstRead Secondary Bus 4819 * 4820 * Bits 03:00 control which REQ/GNT pairs the prefetch settings 4821 * get enabled on. Bit 3 is a grouped enabler which controls 4822 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control 4823 * the individual REQ/GNT pairs [2:0]. 4824 */ 4825 pci_write_config_word(pdev, 0x52, 4826 (0x7 << 13) | 4827 (0x7 << 10) | 4828 (0x7 << 7) | 4829 (0x7 << 4) | 4830 (0xf << 0)); 4831 4832 /* Force cacheline size to 0x8 */ 4833 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); 4834 4835 /* Force latency timer to maximum setting so Cassini can 4836 * sit on the bus as long as it likes. 4837 */ 4838 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff); 4839 } 4840 4841 static const struct net_device_ops cas_netdev_ops = { 4842 .ndo_open = cas_open, 4843 .ndo_stop = cas_close, 4844 .ndo_start_xmit = cas_start_xmit, 4845 .ndo_get_stats = cas_get_stats, 4846 .ndo_set_rx_mode = cas_set_multicast, 4847 .ndo_eth_ioctl = cas_ioctl, 4848 .ndo_tx_timeout = cas_tx_timeout, 4849 .ndo_change_mtu = cas_change_mtu, 4850 .ndo_set_mac_address = eth_mac_addr, 4851 .ndo_validate_addr = eth_validate_addr, 4852 #ifdef CONFIG_NET_POLL_CONTROLLER 4853 .ndo_poll_controller = cas_netpoll, 4854 #endif 4855 }; 4856 4857 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4858 { 4859 static int cas_version_printed = 0; 4860 unsigned long casreg_len; 4861 struct net_device *dev; 4862 struct cas *cp; 4863 u16 pci_cmd; 4864 int i, err; 4865 u8 orig_cacheline_size = 0, cas_cacheline_size = 0; 4866 4867 if (cas_version_printed++ == 0) 4868 pr_info("%s", version); 4869 4870 err = pci_enable_device(pdev); 4871 if (err) { 4872 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 4873 return err; 4874 } 4875 4876 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 4877 dev_err(&pdev->dev, "Cannot find proper PCI device " 4878 "base address, aborting\n"); 4879 err = -ENODEV; 4880 goto err_out_disable_pdev; 4881 } 4882 4883 dev = alloc_etherdev(sizeof(*cp)); 4884 if (!dev) { 4885 err = -ENOMEM; 4886 goto err_out_disable_pdev; 4887 } 4888 SET_NETDEV_DEV(dev, &pdev->dev); 4889 4890 err = pci_request_regions(pdev, dev->name); 4891 if (err) { 4892 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 4893 goto err_out_free_netdev; 4894 } 4895 pci_set_master(pdev); 4896 4897 /* we must always turn on parity response or else parity 4898 * doesn't get generated properly. disable SERR/PERR as well. 4899 * in addition, we want to turn MWI on. 4900 */ 4901 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4902 pci_cmd &= ~PCI_COMMAND_SERR; 4903 pci_cmd |= PCI_COMMAND_PARITY; 4904 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4905 if (pci_try_set_mwi(pdev)) 4906 pr_warn("Could not enable MWI for %s\n", pci_name(pdev)); 4907 4908 cas_program_bridge(pdev); 4909 4910 /* 4911 * On some architectures, the default cache line size set 4912 * by pci_try_set_mwi reduces perforamnce. We have to increase 4913 * it for this case. To start, we'll print some configuration 4914 * data. 4915 */ 4916 #if 1 4917 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, 4918 &orig_cacheline_size); 4919 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) { 4920 cas_cacheline_size = 4921 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ? 4922 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES; 4923 if (pci_write_config_byte(pdev, 4924 PCI_CACHE_LINE_SIZE, 4925 cas_cacheline_size)) { 4926 dev_err(&pdev->dev, "Could not set PCI cache " 4927 "line size\n"); 4928 goto err_out_free_res; 4929 } 4930 } 4931 #endif 4932 4933 4934 /* Configure DMA attributes. */ 4935 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 4936 if (err) { 4937 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 4938 goto err_out_free_res; 4939 } 4940 4941 casreg_len = pci_resource_len(pdev, 0); 4942 4943 cp = netdev_priv(dev); 4944 cp->pdev = pdev; 4945 #if 1 4946 /* A value of 0 indicates we never explicitly set it */ 4947 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0; 4948 #endif 4949 cp->dev = dev; 4950 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : 4951 cassini_debug; 4952 4953 #if defined(CONFIG_SPARC) 4954 cp->of_node = pci_device_to_OF_node(pdev); 4955 #endif 4956 4957 cp->link_transition = LINK_TRANSITION_UNKNOWN; 4958 cp->link_transition_jiffies_valid = 0; 4959 4960 spin_lock_init(&cp->lock); 4961 spin_lock_init(&cp->rx_inuse_lock); 4962 spin_lock_init(&cp->rx_spare_lock); 4963 for (i = 0; i < N_TX_RINGS; i++) { 4964 spin_lock_init(&cp->stat_lock[i]); 4965 spin_lock_init(&cp->tx_lock[i]); 4966 } 4967 spin_lock_init(&cp->stat_lock[N_TX_RINGS]); 4968 mutex_init(&cp->pm_mutex); 4969 4970 timer_setup(&cp->link_timer, cas_link_timer, 0); 4971 4972 #if 1 4973 /* Just in case the implementation of atomic operations 4974 * change so that an explicit initialization is necessary. 4975 */ 4976 atomic_set(&cp->reset_task_pending, 0); 4977 atomic_set(&cp->reset_task_pending_all, 0); 4978 atomic_set(&cp->reset_task_pending_spare, 0); 4979 atomic_set(&cp->reset_task_pending_mtu, 0); 4980 #endif 4981 INIT_WORK(&cp->reset_task, cas_reset_task); 4982 4983 /* Default link parameters */ 4984 if (link_mode >= 0 && link_mode < 6) 4985 cp->link_cntl = link_modes[link_mode]; 4986 else 4987 cp->link_cntl = BMCR_ANENABLE; 4988 cp->lstate = link_down; 4989 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 4990 netif_carrier_off(cp->dev); 4991 cp->timer_ticks = 0; 4992 4993 /* give us access to cassini registers */ 4994 cp->regs = pci_iomap(pdev, 0, casreg_len); 4995 if (!cp->regs) { 4996 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 4997 goto err_out_free_res; 4998 } 4999 cp->casreg_len = casreg_len; 5000 5001 pci_save_state(pdev); 5002 cas_check_pci_invariants(cp); 5003 cas_hard_reset(cp); 5004 cas_reset(cp, 0); 5005 if (cas_check_invariants(cp)) 5006 goto err_out_iounmap; 5007 if (cp->cas_flags & CAS_FLAG_SATURN) 5008 cas_saturn_firmware_init(cp); 5009 5010 cp->init_block = 5011 dma_alloc_coherent(&pdev->dev, sizeof(struct cas_init_block), 5012 &cp->block_dvma, GFP_KERNEL); 5013 if (!cp->init_block) { 5014 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n"); 5015 goto err_out_iounmap; 5016 } 5017 5018 for (i = 0; i < N_TX_RINGS; i++) 5019 cp->init_txds[i] = cp->init_block->txds[i]; 5020 5021 for (i = 0; i < N_RX_DESC_RINGS; i++) 5022 cp->init_rxds[i] = cp->init_block->rxds[i]; 5023 5024 for (i = 0; i < N_RX_COMP_RINGS; i++) 5025 cp->init_rxcs[i] = cp->init_block->rxcs[i]; 5026 5027 for (i = 0; i < N_RX_FLOWS; i++) 5028 skb_queue_head_init(&cp->rx_flows[i]); 5029 5030 dev->netdev_ops = &cas_netdev_ops; 5031 dev->ethtool_ops = &cas_ethtool_ops; 5032 dev->watchdog_timeo = CAS_TX_TIMEOUT; 5033 5034 #ifdef USE_NAPI 5035 netif_napi_add(dev, &cp->napi, cas_poll); 5036 #endif 5037 dev->irq = pdev->irq; 5038 dev->dma = 0; 5039 5040 /* Cassini features. */ 5041 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0) 5042 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; 5043 5044 dev->features |= NETIF_F_HIGHDMA; 5045 5046 /* MTU range: 60 - varies or 9000 */ 5047 dev->min_mtu = CAS_MIN_MTU; 5048 dev->max_mtu = CAS_MAX_MTU; 5049 5050 if (register_netdev(dev)) { 5051 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 5052 goto err_out_free_consistent; 5053 } 5054 5055 i = readl(cp->regs + REG_BIM_CFG); 5056 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n", 5057 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", 5058 (i & BIM_CFG_32BIT) ? "32" : "64", 5059 (i & BIM_CFG_66MHZ) ? "66" : "33", 5060 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq, 5061 dev->dev_addr); 5062 5063 pci_set_drvdata(pdev, dev); 5064 cp->hw_running = 1; 5065 cas_entropy_reset(cp); 5066 cas_phy_init(cp); 5067 cas_begin_auto_negotiation(cp, NULL); 5068 return 0; 5069 5070 err_out_free_consistent: 5071 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), 5072 cp->init_block, cp->block_dvma); 5073 5074 err_out_iounmap: 5075 mutex_lock(&cp->pm_mutex); 5076 if (cp->hw_running) 5077 cas_shutdown(cp); 5078 mutex_unlock(&cp->pm_mutex); 5079 5080 vfree(cp->fw_data); 5081 5082 pci_iounmap(pdev, cp->regs); 5083 5084 5085 err_out_free_res: 5086 pci_release_regions(pdev); 5087 5088 /* Try to restore it in case the error occurred after we 5089 * set it. 5090 */ 5091 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); 5092 5093 err_out_free_netdev: 5094 free_netdev(dev); 5095 5096 err_out_disable_pdev: 5097 pci_disable_device(pdev); 5098 return -ENODEV; 5099 } 5100 5101 static void cas_remove_one(struct pci_dev *pdev) 5102 { 5103 struct net_device *dev = pci_get_drvdata(pdev); 5104 struct cas *cp; 5105 if (!dev) 5106 return; 5107 5108 cp = netdev_priv(dev); 5109 unregister_netdev(dev); 5110 5111 vfree(cp->fw_data); 5112 5113 mutex_lock(&cp->pm_mutex); 5114 cancel_work_sync(&cp->reset_task); 5115 if (cp->hw_running) 5116 cas_shutdown(cp); 5117 mutex_unlock(&cp->pm_mutex); 5118 5119 #if 1 5120 if (cp->orig_cacheline_size) { 5121 /* Restore the cache line size if we had modified 5122 * it. 5123 */ 5124 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 5125 cp->orig_cacheline_size); 5126 } 5127 #endif 5128 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), 5129 cp->init_block, cp->block_dvma); 5130 pci_iounmap(pdev, cp->regs); 5131 free_netdev(dev); 5132 pci_release_regions(pdev); 5133 pci_disable_device(pdev); 5134 } 5135 5136 static int __maybe_unused cas_suspend(struct device *dev_d) 5137 { 5138 struct net_device *dev = dev_get_drvdata(dev_d); 5139 struct cas *cp = netdev_priv(dev); 5140 unsigned long flags; 5141 5142 mutex_lock(&cp->pm_mutex); 5143 5144 /* If the driver is opened, we stop the DMA */ 5145 if (cp->opened) { 5146 netif_device_detach(dev); 5147 5148 cas_lock_all_save(cp, flags); 5149 5150 /* We can set the second arg of cas_reset to 0 5151 * because on resume, we'll call cas_init_hw with 5152 * its second arg set so that autonegotiation is 5153 * restarted. 5154 */ 5155 cas_reset(cp, 0); 5156 cas_clean_rings(cp); 5157 cas_unlock_all_restore(cp, flags); 5158 } 5159 5160 if (cp->hw_running) 5161 cas_shutdown(cp); 5162 mutex_unlock(&cp->pm_mutex); 5163 5164 return 0; 5165 } 5166 5167 static int __maybe_unused cas_resume(struct device *dev_d) 5168 { 5169 struct net_device *dev = dev_get_drvdata(dev_d); 5170 struct cas *cp = netdev_priv(dev); 5171 5172 netdev_info(dev, "resuming\n"); 5173 5174 mutex_lock(&cp->pm_mutex); 5175 cas_hard_reset(cp); 5176 if (cp->opened) { 5177 unsigned long flags; 5178 cas_lock_all_save(cp, flags); 5179 cas_reset(cp, 0); 5180 cp->hw_running = 1; 5181 cas_clean_rings(cp); 5182 cas_init_hw(cp, 1); 5183 cas_unlock_all_restore(cp, flags); 5184 5185 netif_device_attach(dev); 5186 } 5187 mutex_unlock(&cp->pm_mutex); 5188 return 0; 5189 } 5190 5191 static SIMPLE_DEV_PM_OPS(cas_pm_ops, cas_suspend, cas_resume); 5192 5193 static struct pci_driver cas_driver = { 5194 .name = DRV_MODULE_NAME, 5195 .id_table = cas_pci_tbl, 5196 .probe = cas_init_one, 5197 .remove = cas_remove_one, 5198 .driver.pm = &cas_pm_ops, 5199 }; 5200 5201 static int __init cas_init(void) 5202 { 5203 if (linkdown_timeout > 0) 5204 link_transition_timeout = linkdown_timeout * HZ; 5205 else 5206 link_transition_timeout = 0; 5207 5208 return pci_register_driver(&cas_driver); 5209 } 5210 5211 static void __exit cas_cleanup(void) 5212 { 5213 pci_unregister_driver(&cas_driver); 5214 } 5215 5216 module_init(cas_init); 5217 module_exit(cas_cleanup); 5218