1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac TC Handling (HW only) 5 */ 6 7 #include <net/pkt_cls.h> 8 #include <net/tc_act/tc_gact.h> 9 #include "common.h" 10 #include "dwmac4.h" 11 #include "dwmac5.h" 12 #include "stmmac.h" 13 14 static void tc_fill_all_pass_entry(struct stmmac_tc_entry *entry) 15 { 16 memset(entry, 0, sizeof(*entry)); 17 entry->in_use = true; 18 entry->is_last = true; 19 entry->is_frag = false; 20 entry->prio = ~0x0; 21 entry->handle = 0; 22 entry->val.match_data = 0x0; 23 entry->val.match_en = 0x0; 24 entry->val.af = 1; 25 entry->val.dma_ch_no = 0x0; 26 } 27 28 static struct stmmac_tc_entry *tc_find_entry(struct stmmac_priv *priv, 29 struct tc_cls_u32_offload *cls, 30 bool free) 31 { 32 struct stmmac_tc_entry *entry, *first = NULL, *dup = NULL; 33 u32 loc = cls->knode.handle; 34 int i; 35 36 for (i = 0; i < priv->tc_entries_max; i++) { 37 entry = &priv->tc_entries[i]; 38 if (!entry->in_use && !first && free) 39 first = entry; 40 if ((entry->handle == loc) && !free && !entry->is_frag) 41 dup = entry; 42 } 43 44 if (dup) 45 return dup; 46 if (first) { 47 first->handle = loc; 48 first->in_use = true; 49 50 /* Reset HW values */ 51 memset(&first->val, 0, sizeof(first->val)); 52 } 53 54 return first; 55 } 56 57 static int tc_fill_actions(struct stmmac_tc_entry *entry, 58 struct stmmac_tc_entry *frag, 59 struct tc_cls_u32_offload *cls) 60 { 61 struct stmmac_tc_entry *action_entry = entry; 62 const struct tc_action *act; 63 struct tcf_exts *exts; 64 int i; 65 66 exts = cls->knode.exts; 67 if (!tcf_exts_has_actions(exts)) 68 return -EINVAL; 69 if (frag) 70 action_entry = frag; 71 72 tcf_exts_for_each_action(i, act, exts) { 73 /* Accept */ 74 if (is_tcf_gact_ok(act)) { 75 action_entry->val.af = 1; 76 break; 77 } 78 /* Drop */ 79 if (is_tcf_gact_shot(act)) { 80 action_entry->val.rf = 1; 81 break; 82 } 83 84 /* Unsupported */ 85 return -EINVAL; 86 } 87 88 return 0; 89 } 90 91 static int tc_fill_entry(struct stmmac_priv *priv, 92 struct tc_cls_u32_offload *cls) 93 { 94 struct stmmac_tc_entry *entry, *frag = NULL; 95 struct tc_u32_sel *sel = cls->knode.sel; 96 u32 off, data, mask, real_off, rem; 97 u32 prio = cls->common.prio << 16; 98 int ret; 99 100 /* Only 1 match per entry */ 101 if (sel->nkeys <= 0 || sel->nkeys > 1) 102 return -EINVAL; 103 104 off = sel->keys[0].off << sel->offshift; 105 data = sel->keys[0].val; 106 mask = sel->keys[0].mask; 107 108 switch (ntohs(cls->common.protocol)) { 109 case ETH_P_ALL: 110 break; 111 case ETH_P_IP: 112 off += ETH_HLEN; 113 break; 114 default: 115 return -EINVAL; 116 } 117 118 if (off > priv->tc_off_max) 119 return -EINVAL; 120 121 real_off = off / 4; 122 rem = off % 4; 123 124 entry = tc_find_entry(priv, cls, true); 125 if (!entry) 126 return -EINVAL; 127 128 if (rem) { 129 frag = tc_find_entry(priv, cls, true); 130 if (!frag) { 131 ret = -EINVAL; 132 goto err_unuse; 133 } 134 135 entry->frag_ptr = frag; 136 entry->val.match_en = (mask << (rem * 8)) & 137 GENMASK(31, rem * 8); 138 entry->val.match_data = (data << (rem * 8)) & 139 GENMASK(31, rem * 8); 140 entry->val.frame_offset = real_off; 141 entry->prio = prio; 142 143 frag->val.match_en = (mask >> (rem * 8)) & 144 GENMASK(rem * 8 - 1, 0); 145 frag->val.match_data = (data >> (rem * 8)) & 146 GENMASK(rem * 8 - 1, 0); 147 frag->val.frame_offset = real_off + 1; 148 frag->prio = prio; 149 frag->is_frag = true; 150 } else { 151 entry->frag_ptr = NULL; 152 entry->val.match_en = mask; 153 entry->val.match_data = data; 154 entry->val.frame_offset = real_off; 155 entry->prio = prio; 156 } 157 158 ret = tc_fill_actions(entry, frag, cls); 159 if (ret) 160 goto err_unuse; 161 162 return 0; 163 164 err_unuse: 165 if (frag) 166 frag->in_use = false; 167 entry->in_use = false; 168 return ret; 169 } 170 171 static void tc_unfill_entry(struct stmmac_priv *priv, 172 struct tc_cls_u32_offload *cls) 173 { 174 struct stmmac_tc_entry *entry; 175 176 entry = tc_find_entry(priv, cls, false); 177 if (!entry) 178 return; 179 180 entry->in_use = false; 181 if (entry->frag_ptr) { 182 entry = entry->frag_ptr; 183 entry->is_frag = false; 184 entry->in_use = false; 185 } 186 } 187 188 static int tc_config_knode(struct stmmac_priv *priv, 189 struct tc_cls_u32_offload *cls) 190 { 191 int ret; 192 193 ret = tc_fill_entry(priv, cls); 194 if (ret) 195 return ret; 196 197 ret = stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries, 198 priv->tc_entries_max); 199 if (ret) 200 goto err_unfill; 201 202 return 0; 203 204 err_unfill: 205 tc_unfill_entry(priv, cls); 206 return ret; 207 } 208 209 static int tc_delete_knode(struct stmmac_priv *priv, 210 struct tc_cls_u32_offload *cls) 211 { 212 /* Set entry and fragments as not used */ 213 tc_unfill_entry(priv, cls); 214 215 return stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries, 216 priv->tc_entries_max); 217 } 218 219 static int tc_setup_cls_u32(struct stmmac_priv *priv, 220 struct tc_cls_u32_offload *cls) 221 { 222 switch (cls->command) { 223 case TC_CLSU32_REPLACE_KNODE: 224 tc_unfill_entry(priv, cls); 225 fallthrough; 226 case TC_CLSU32_NEW_KNODE: 227 return tc_config_knode(priv, cls); 228 case TC_CLSU32_DELETE_KNODE: 229 return tc_delete_knode(priv, cls); 230 default: 231 return -EOPNOTSUPP; 232 } 233 } 234 235 static int tc_init(struct stmmac_priv *priv) 236 { 237 struct dma_features *dma_cap = &priv->dma_cap; 238 unsigned int count; 239 int i; 240 241 if (dma_cap->l3l4fnum) { 242 priv->flow_entries_max = dma_cap->l3l4fnum; 243 priv->flow_entries = devm_kcalloc(priv->device, 244 dma_cap->l3l4fnum, 245 sizeof(*priv->flow_entries), 246 GFP_KERNEL); 247 if (!priv->flow_entries) 248 return -ENOMEM; 249 250 for (i = 0; i < priv->flow_entries_max; i++) 251 priv->flow_entries[i].idx = i; 252 253 dev_info(priv->device, "Enabled Flow TC (entries=%d)\n", 254 priv->flow_entries_max); 255 } 256 257 /* Fail silently as we can still use remaining features, e.g. CBS */ 258 if (!dma_cap->frpsel) 259 return 0; 260 261 switch (dma_cap->frpbs) { 262 case 0x0: 263 priv->tc_off_max = 64; 264 break; 265 case 0x1: 266 priv->tc_off_max = 128; 267 break; 268 case 0x2: 269 priv->tc_off_max = 256; 270 break; 271 default: 272 return -EINVAL; 273 } 274 275 switch (dma_cap->frpes) { 276 case 0x0: 277 count = 64; 278 break; 279 case 0x1: 280 count = 128; 281 break; 282 case 0x2: 283 count = 256; 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 /* Reserve one last filter which lets all pass */ 290 priv->tc_entries_max = count; 291 priv->tc_entries = devm_kcalloc(priv->device, 292 count, sizeof(*priv->tc_entries), GFP_KERNEL); 293 if (!priv->tc_entries) 294 return -ENOMEM; 295 296 tc_fill_all_pass_entry(&priv->tc_entries[count - 1]); 297 298 dev_info(priv->device, "Enabling HW TC (entries=%d, max_off=%d)\n", 299 priv->tc_entries_max, priv->tc_off_max); 300 return 0; 301 } 302 303 static int tc_setup_cbs(struct stmmac_priv *priv, 304 struct tc_cbs_qopt_offload *qopt) 305 { 306 u32 tx_queues_count = priv->plat->tx_queues_to_use; 307 u32 queue = qopt->queue; 308 u32 ptr, speed_div; 309 u32 mode_to_use; 310 u64 value; 311 int ret; 312 313 /* Queue 0 is not AVB capable */ 314 if (queue <= 0 || queue >= tx_queues_count) 315 return -EINVAL; 316 if (!priv->dma_cap.av) 317 return -EOPNOTSUPP; 318 319 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 320 if (mode_to_use == MTL_QUEUE_DCB && qopt->enable) { 321 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue, MTL_QUEUE_AVB); 322 if (ret) 323 return ret; 324 325 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_AVB; 326 } else if (!qopt->enable) { 327 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue, 328 MTL_QUEUE_DCB); 329 if (ret) 330 return ret; 331 332 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB; 333 } 334 335 /* Port Transmit Rate and Speed Divider */ 336 ptr = (priv->speed == SPEED_100) ? 4 : 8; 337 speed_div = (priv->speed == SPEED_100) ? 100000 : 1000000; 338 339 /* Final adjustments for HW */ 340 value = div_s64(qopt->idleslope * 1024ll * ptr, speed_div); 341 priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0); 342 343 value = div_s64(-qopt->sendslope * 1024ll * ptr, speed_div); 344 priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0); 345 346 value = qopt->hicredit * 1024ll * 8; 347 priv->plat->tx_queues_cfg[queue].high_credit = value & GENMASK(31, 0); 348 349 value = qopt->locredit * 1024ll * 8; 350 priv->plat->tx_queues_cfg[queue].low_credit = value & GENMASK(31, 0); 351 352 ret = stmmac_config_cbs(priv, priv->hw, 353 priv->plat->tx_queues_cfg[queue].send_slope, 354 priv->plat->tx_queues_cfg[queue].idle_slope, 355 priv->plat->tx_queues_cfg[queue].high_credit, 356 priv->plat->tx_queues_cfg[queue].low_credit, 357 queue); 358 if (ret) 359 return ret; 360 361 dev_info(priv->device, "CBS queue %d: send %d, idle %d, hi %d, lo %d\n", 362 queue, qopt->sendslope, qopt->idleslope, 363 qopt->hicredit, qopt->locredit); 364 return 0; 365 } 366 367 static int tc_parse_flow_actions(struct stmmac_priv *priv, 368 struct flow_action *action, 369 struct stmmac_flow_entry *entry, 370 struct netlink_ext_ack *extack) 371 { 372 struct flow_action_entry *act; 373 int i; 374 375 if (!flow_action_has_entries(action)) 376 return -EINVAL; 377 378 if (!flow_action_basic_hw_stats_check(action, extack)) 379 return -EOPNOTSUPP; 380 381 flow_action_for_each(i, act, action) { 382 switch (act->id) { 383 case FLOW_ACTION_DROP: 384 entry->action |= STMMAC_FLOW_ACTION_DROP; 385 return 0; 386 default: 387 break; 388 } 389 } 390 391 /* Nothing to do, maybe inverse filter ? */ 392 return 0; 393 } 394 395 static int tc_add_basic_flow(struct stmmac_priv *priv, 396 struct flow_cls_offload *cls, 397 struct stmmac_flow_entry *entry) 398 { 399 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 400 struct flow_dissector *dissector = rule->match.dissector; 401 struct flow_match_basic match; 402 403 /* Nothing to do here */ 404 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_BASIC)) 405 return -EINVAL; 406 407 flow_rule_match_basic(rule, &match); 408 entry->ip_proto = match.key->ip_proto; 409 return 0; 410 } 411 412 static int tc_add_ip4_flow(struct stmmac_priv *priv, 413 struct flow_cls_offload *cls, 414 struct stmmac_flow_entry *entry) 415 { 416 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 417 struct flow_dissector *dissector = rule->match.dissector; 418 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; 419 struct flow_match_ipv4_addrs match; 420 u32 hw_match; 421 int ret; 422 423 /* Nothing to do here */ 424 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) 425 return -EINVAL; 426 427 flow_rule_match_ipv4_addrs(rule, &match); 428 hw_match = ntohl(match.key->src) & ntohl(match.mask->src); 429 if (hw_match) { 430 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true, 431 false, true, inv, hw_match); 432 if (ret) 433 return ret; 434 } 435 436 hw_match = ntohl(match.key->dst) & ntohl(match.mask->dst); 437 if (hw_match) { 438 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true, 439 false, false, inv, hw_match); 440 if (ret) 441 return ret; 442 } 443 444 return 0; 445 } 446 447 static int tc_add_ports_flow(struct stmmac_priv *priv, 448 struct flow_cls_offload *cls, 449 struct stmmac_flow_entry *entry) 450 { 451 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 452 struct flow_dissector *dissector = rule->match.dissector; 453 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; 454 struct flow_match_ports match; 455 u32 hw_match; 456 bool is_udp; 457 int ret; 458 459 /* Nothing to do here */ 460 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_PORTS)) 461 return -EINVAL; 462 463 switch (entry->ip_proto) { 464 case IPPROTO_TCP: 465 is_udp = false; 466 break; 467 case IPPROTO_UDP: 468 is_udp = true; 469 break; 470 default: 471 return -EINVAL; 472 } 473 474 flow_rule_match_ports(rule, &match); 475 476 hw_match = ntohs(match.key->src) & ntohs(match.mask->src); 477 if (hw_match) { 478 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true, 479 is_udp, true, inv, hw_match); 480 if (ret) 481 return ret; 482 } 483 484 hw_match = ntohs(match.key->dst) & ntohs(match.mask->dst); 485 if (hw_match) { 486 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true, 487 is_udp, false, inv, hw_match); 488 if (ret) 489 return ret; 490 } 491 492 entry->is_l4 = true; 493 return 0; 494 } 495 496 static struct stmmac_flow_entry *tc_find_flow(struct stmmac_priv *priv, 497 struct flow_cls_offload *cls, 498 bool get_free) 499 { 500 int i; 501 502 for (i = 0; i < priv->flow_entries_max; i++) { 503 struct stmmac_flow_entry *entry = &priv->flow_entries[i]; 504 505 if (entry->cookie == cls->cookie) 506 return entry; 507 if (get_free && (entry->in_use == false)) 508 return entry; 509 } 510 511 return NULL; 512 } 513 514 static struct { 515 int (*fn)(struct stmmac_priv *priv, struct flow_cls_offload *cls, 516 struct stmmac_flow_entry *entry); 517 } tc_flow_parsers[] = { 518 { .fn = tc_add_basic_flow }, 519 { .fn = tc_add_ip4_flow }, 520 { .fn = tc_add_ports_flow }, 521 }; 522 523 static int tc_add_flow(struct stmmac_priv *priv, 524 struct flow_cls_offload *cls) 525 { 526 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false); 527 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 528 int i, ret; 529 530 if (!entry) { 531 entry = tc_find_flow(priv, cls, true); 532 if (!entry) 533 return -ENOENT; 534 } 535 536 ret = tc_parse_flow_actions(priv, &rule->action, entry, 537 cls->common.extack); 538 if (ret) 539 return ret; 540 541 for (i = 0; i < ARRAY_SIZE(tc_flow_parsers); i++) { 542 ret = tc_flow_parsers[i].fn(priv, cls, entry); 543 if (!ret) { 544 entry->in_use = true; 545 continue; 546 } 547 } 548 549 if (!entry->in_use) 550 return -EINVAL; 551 552 entry->cookie = cls->cookie; 553 return 0; 554 } 555 556 static int tc_del_flow(struct stmmac_priv *priv, 557 struct flow_cls_offload *cls) 558 { 559 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false); 560 int ret; 561 562 if (!entry || !entry->in_use) 563 return -ENOENT; 564 565 if (entry->is_l4) { 566 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, false, 567 false, false, false, 0); 568 } else { 569 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, false, 570 false, false, false, 0); 571 } 572 573 entry->in_use = false; 574 entry->cookie = 0; 575 entry->is_l4 = false; 576 return ret; 577 } 578 579 static int tc_setup_cls(struct stmmac_priv *priv, 580 struct flow_cls_offload *cls) 581 { 582 int ret = 0; 583 584 /* When RSS is enabled, the filtering will be bypassed */ 585 if (priv->rss.enable) 586 return -EBUSY; 587 588 switch (cls->command) { 589 case FLOW_CLS_REPLACE: 590 ret = tc_add_flow(priv, cls); 591 break; 592 case FLOW_CLS_DESTROY: 593 ret = tc_del_flow(priv, cls); 594 break; 595 default: 596 return -EOPNOTSUPP; 597 } 598 599 return ret; 600 } 601 602 static int tc_setup_taprio(struct stmmac_priv *priv, 603 struct tc_taprio_qopt_offload *qopt) 604 { 605 u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep; 606 struct plat_stmmacenet_data *plat = priv->plat; 607 struct timespec64 time, current_time; 608 ktime_t current_time_ns; 609 bool fpe = false; 610 int i, ret = 0; 611 u64 ctr; 612 613 if (!priv->dma_cap.estsel) 614 return -EOPNOTSUPP; 615 616 switch (wid) { 617 case 0x1: 618 wid = 16; 619 break; 620 case 0x2: 621 wid = 20; 622 break; 623 case 0x3: 624 wid = 24; 625 break; 626 default: 627 return -EOPNOTSUPP; 628 } 629 630 switch (dep) { 631 case 0x1: 632 dep = 64; 633 break; 634 case 0x2: 635 dep = 128; 636 break; 637 case 0x3: 638 dep = 256; 639 break; 640 case 0x4: 641 dep = 512; 642 break; 643 case 0x5: 644 dep = 1024; 645 break; 646 default: 647 return -EOPNOTSUPP; 648 } 649 650 if (!qopt->enable) 651 goto disable; 652 if (qopt->num_entries >= dep) 653 return -EINVAL; 654 if (!qopt->base_time) 655 return -ERANGE; 656 if (!qopt->cycle_time) 657 return -ERANGE; 658 659 if (!plat->est) { 660 plat->est = devm_kzalloc(priv->device, sizeof(*plat->est), 661 GFP_KERNEL); 662 if (!plat->est) 663 return -ENOMEM; 664 } else { 665 memset(plat->est, 0, sizeof(*plat->est)); 666 } 667 668 size = qopt->num_entries; 669 670 priv->plat->est->gcl_size = size; 671 priv->plat->est->enable = qopt->enable; 672 673 for (i = 0; i < size; i++) { 674 s64 delta_ns = qopt->entries[i].interval; 675 u32 gates = qopt->entries[i].gate_mask; 676 677 if (delta_ns > GENMASK(wid, 0)) 678 return -ERANGE; 679 if (gates > GENMASK(31 - wid, 0)) 680 return -ERANGE; 681 682 switch (qopt->entries[i].command) { 683 case TC_TAPRIO_CMD_SET_GATES: 684 if (fpe) 685 return -EINVAL; 686 break; 687 case TC_TAPRIO_CMD_SET_AND_HOLD: 688 gates |= BIT(0); 689 fpe = true; 690 break; 691 case TC_TAPRIO_CMD_SET_AND_RELEASE: 692 gates &= ~BIT(0); 693 fpe = true; 694 break; 695 default: 696 return -EOPNOTSUPP; 697 } 698 699 priv->plat->est->gcl[i] = delta_ns | (gates << wid); 700 } 701 702 /* Adjust for real system time */ 703 priv->ptp_clock_ops.gettime64(&priv->ptp_clock_ops, ¤t_time); 704 current_time_ns = timespec64_to_ktime(current_time); 705 if (ktime_after(qopt->base_time, current_time_ns)) { 706 time = ktime_to_timespec64(qopt->base_time); 707 } else { 708 ktime_t base_time; 709 s64 n; 710 711 n = div64_s64(ktime_sub_ns(current_time_ns, qopt->base_time), 712 qopt->cycle_time); 713 base_time = ktime_add_ns(qopt->base_time, 714 (n + 1) * qopt->cycle_time); 715 716 time = ktime_to_timespec64(base_time); 717 } 718 719 priv->plat->est->btr[0] = (u32)time.tv_nsec; 720 priv->plat->est->btr[1] = (u32)time.tv_sec; 721 722 ctr = qopt->cycle_time; 723 priv->plat->est->ctr[0] = do_div(ctr, NSEC_PER_SEC); 724 priv->plat->est->ctr[1] = (u32)ctr; 725 726 if (fpe && !priv->dma_cap.fpesel) 727 return -EOPNOTSUPP; 728 729 ret = stmmac_fpe_configure(priv, priv->ioaddr, 730 priv->plat->tx_queues_to_use, 731 priv->plat->rx_queues_to_use, fpe); 732 if (ret && fpe) { 733 netdev_err(priv->dev, "failed to enable Frame Preemption\n"); 734 return ret; 735 } 736 737 ret = stmmac_est_configure(priv, priv->ioaddr, priv->plat->est, 738 priv->plat->clk_ptp_rate); 739 if (ret) { 740 netdev_err(priv->dev, "failed to configure EST\n"); 741 goto disable; 742 } 743 744 netdev_info(priv->dev, "configured EST\n"); 745 return 0; 746 747 disable: 748 priv->plat->est->enable = false; 749 stmmac_est_configure(priv, priv->ioaddr, priv->plat->est, 750 priv->plat->clk_ptp_rate); 751 return ret; 752 } 753 754 static int tc_setup_etf(struct stmmac_priv *priv, 755 struct tc_etf_qopt_offload *qopt) 756 { 757 if (!priv->dma_cap.tbssel) 758 return -EOPNOTSUPP; 759 if (qopt->queue >= priv->plat->tx_queues_to_use) 760 return -EINVAL; 761 if (!(priv->tx_queue[qopt->queue].tbs & STMMAC_TBS_AVAIL)) 762 return -EINVAL; 763 764 if (qopt->enable) 765 priv->tx_queue[qopt->queue].tbs |= STMMAC_TBS_EN; 766 else 767 priv->tx_queue[qopt->queue].tbs &= ~STMMAC_TBS_EN; 768 769 netdev_info(priv->dev, "%s ETF for Queue %d\n", 770 qopt->enable ? "enabled" : "disabled", qopt->queue); 771 return 0; 772 } 773 774 const struct stmmac_tc_ops dwmac510_tc_ops = { 775 .init = tc_init, 776 .setup_cls_u32 = tc_setup_cls_u32, 777 .setup_cbs = tc_setup_cbs, 778 .setup_cls = tc_setup_cls, 779 .setup_taprio = tc_setup_taprio, 780 .setup_etf = tc_setup_etf, 781 }; 782