1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /******************************************************************************
3   PTP Header file
4 
5   Copyright (C) 2013  Vayavya Labs Pvt Ltd
6 
7 
8   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9 ******************************************************************************/
10 
11 #ifndef	__STMMAC_PTP_H__
12 #define	__STMMAC_PTP_H__
13 
14 #define PTP_XGMAC_OFFSET	0xd00
15 #define	PTP_GMAC4_OFFSET	0xb00
16 #define	PTP_GMAC3_X_OFFSET	0x700
17 
18 /* IEEE 1588 PTP register offsets */
19 #define	PTP_TCR		0x00	/* Timestamp Control Reg */
20 #define	PTP_SSIR	0x04	/* Sub-Second Increment Reg */
21 #define	PTP_STSR	0x08	/* System Time – Seconds Regr */
22 #define	PTP_STNSR	0x0c	/* System Time – Nanoseconds Reg */
23 #define	PTP_STSUR	0x10	/* System Time – Seconds Update Reg */
24 #define	PTP_STNSUR	0x14	/* System Time – Nanoseconds Update Reg */
25 #define	PTP_TAR		0x18	/* Timestamp Addend Reg */
26 #define	PTP_ACR		0x40	/* Auxiliary Control Reg */
27 #define	PTP_ATNR	0x48	/* Auxiliary Timestamp - Nanoseconds Reg */
28 #define	PTP_ATSR	0x4c	/* Auxiliary Timestamp - Seconds Reg */
29 
30 #define	PTP_STNSUR_ADDSUB_SHIFT	31
31 #define	PTP_DIGITAL_ROLLOVER_MODE	0x3B9ACA00	/* 10e9-1 ns */
32 #define	PTP_BINARY_ROLLOVER_MODE	0x80000000	/* ~0.466 ns */
33 
34 /* PTP Timestamp control register defines */
35 #define	PTP_TCR_TSENA		BIT(0)	/* Timestamp Enable */
36 #define	PTP_TCR_TSCFUPDT	BIT(1)	/* Timestamp Fine/Coarse Update */
37 #define	PTP_TCR_TSINIT		BIT(2)	/* Timestamp Initialize */
38 #define	PTP_TCR_TSUPDT		BIT(3)	/* Timestamp Update */
39 #define	PTP_TCR_TSTRIG		BIT(4)	/* Timestamp Interrupt Trigger Enable */
40 #define	PTP_TCR_TSADDREG	BIT(5)	/* Addend Reg Update */
41 #define	PTP_TCR_TSENALL		BIT(8)	/* Enable Timestamp for All Frames */
42 #define	PTP_TCR_TSCTRLSSR	BIT(9)	/* Digital or Binary Rollover Control */
43 /* Enable PTP packet Processing for Version 2 Format */
44 #define	PTP_TCR_TSVER2ENA	BIT(10)
45 /* Enable Processing of PTP over Ethernet Frames */
46 #define	PTP_TCR_TSIPENA		BIT(11)
47 /* Enable Processing of PTP Frames Sent over IPv6-UDP */
48 #define	PTP_TCR_TSIPV6ENA	BIT(12)
49 /* Enable Processing of PTP Frames Sent over IPv4-UDP */
50 #define	PTP_TCR_TSIPV4ENA	BIT(13)
51 /* Enable Timestamp Snapshot for Event Messages */
52 #define	PTP_TCR_TSEVNTENA	BIT(14)
53 /* Enable Snapshot for Messages Relevant to Master */
54 #define	PTP_TCR_TSMSTRENA	BIT(15)
55 /* Select PTP packets for Taking Snapshots
56  * On gmac4 specifically:
57  * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
58  * or
59  * Enable  SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
60  * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
61  */
62 #define	PTP_TCR_SNAPTYPSEL_1	BIT(16)
63 /* Enable MAC address for PTP Frame Filtering */
64 #define	PTP_TCR_TSENMACADDR	BIT(18)
65 
66 /* SSIR defines */
67 #define	PTP_SSIR_SSINC_MAX		0xff
68 #define	GMAC4_PTP_SSIR_SSINC_SHIFT	16
69 
70 /* Auxiliary Control defines */
71 #define	PTP_ACR_ATSFC		BIT(0)	/* Auxiliary Snapshot FIFO Clear */
72 #define	PTP_ACR_ATSEN0		BIT(4)	/* Auxiliary Snapshot 0 Enable */
73 #define	PTP_ACR_ATSEN1		BIT(5)	/* Auxiliary Snapshot 1 Enable */
74 #define	PTP_ACR_ATSEN2		BIT(6)	/* Auxiliary Snapshot 2 Enable */
75 #define	PTP_ACR_ATSEN3		BIT(7)	/* Auxiliary Snapshot 3 Enable */
76 #define	PTP_ACR_ATSEN_SHIFT	5	/* Auxiliary Snapshot shift */
77 #define	PTP_ACR_MASK		GENMASK(7, 4)	/* Aux Snapshot Mask */
78 #define	PMC_ART_VALUE0		0x01	/* PMC_ART[15:0] timer value */
79 #define	PMC_ART_VALUE1		0x02	/* PMC_ART[31:16] timer value */
80 #define	PMC_ART_VALUE2		0x03	/* PMC_ART[47:32] timer value */
81 #define	PMC_ART_VALUE3		0x04	/* PMC_ART[63:48] timer value */
82 #define	GMAC4_ART_TIME_SHIFT	16	/* ART TIME 16-bits shift */
83 
84 enum aux_snapshot {
85 	AUX_SNAPSHOT0 = 0x10,
86 	AUX_SNAPSHOT1 = 0x20,
87 	AUX_SNAPSHOT2 = 0x40,
88 	AUX_SNAPSHOT3 = 0x80,
89 };
90 
91 #endif	/* __STMMAC_PTP_H__ */
92