1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This contains the functions to handle the pci driver. 4 5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd 6 7 8 Author: Rayagond Kokatanur <rayagond@vayavyalabs.com> 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 *******************************************************************************/ 11 12 #include <linux/clk-provider.h> 13 #include <linux/pci.h> 14 #include <linux/dmi.h> 15 16 #include "stmmac.h" 17 18 /* 19 * This struct is used to associate PCI Function of MAC controller on a board, 20 * discovered via DMI, with the address of PHY connected to the MAC. The 21 * negative value of the address means that MAC controller is not connected 22 * with PHY. 23 */ 24 struct stmmac_pci_func_data { 25 unsigned int func; 26 int phy_addr; 27 }; 28 29 struct stmmac_pci_dmi_data { 30 const struct stmmac_pci_func_data *func; 31 size_t nfuncs; 32 }; 33 34 struct stmmac_pci_info { 35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 36 }; 37 38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 39 const struct dmi_system_id *dmi_list) 40 { 41 const struct stmmac_pci_func_data *func_data; 42 const struct stmmac_pci_dmi_data *dmi_data; 43 const struct dmi_system_id *dmi_id; 44 int func = PCI_FUNC(pdev->devfn); 45 size_t n; 46 47 dmi_id = dmi_first_match(dmi_list); 48 if (!dmi_id) 49 return -ENODEV; 50 51 dmi_data = dmi_id->driver_data; 52 func_data = dmi_data->func; 53 54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 55 if (func_data->func == func) 56 return func_data->phy_addr; 57 58 return -ENODEV; 59 } 60 61 static void common_default_data(struct plat_stmmacenet_data *plat) 62 { 63 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 64 plat->has_gmac = 1; 65 plat->force_sf_dma_mode = 1; 66 67 plat->mdio_bus_data->needs_reset = true; 68 69 /* Set default value for multicast hash bins */ 70 plat->multicast_filter_bins = HASH_TABLE_SIZE; 71 72 /* Set default value for unicast filter entries */ 73 plat->unicast_filter_entries = 1; 74 75 /* Set the maxmtu to a default of JUMBO_LEN */ 76 plat->maxmtu = JUMBO_LEN; 77 78 /* Set default number of RX and TX queues to use */ 79 plat->tx_queues_to_use = 1; 80 plat->rx_queues_to_use = 1; 81 82 /* Disable Priority config by default */ 83 plat->tx_queues_cfg[0].use_prio = false; 84 plat->rx_queues_cfg[0].use_prio = false; 85 86 /* Disable RX queues routing by default */ 87 plat->rx_queues_cfg[0].pkt_route = 0x0; 88 } 89 90 static int stmmac_default_data(struct pci_dev *pdev, 91 struct plat_stmmacenet_data *plat) 92 { 93 /* Set common default data first */ 94 common_default_data(plat); 95 96 plat->bus_id = 1; 97 plat->phy_addr = 0; 98 plat->interface = PHY_INTERFACE_MODE_GMII; 99 100 plat->dma_cfg->pbl = 32; 101 plat->dma_cfg->pblx8 = true; 102 /* TODO: AXI */ 103 104 return 0; 105 } 106 107 static const struct stmmac_pci_info stmmac_pci_info = { 108 .setup = stmmac_default_data, 109 }; 110 111 static int intel_mgbe_common_data(struct pci_dev *pdev, 112 struct plat_stmmacenet_data *plat) 113 { 114 int i; 115 116 plat->clk_csr = 5; 117 plat->has_gmac = 0; 118 plat->has_gmac4 = 1; 119 plat->force_sf_dma_mode = 0; 120 plat->tso_en = 1; 121 122 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 123 124 for (i = 0; i < plat->rx_queues_to_use; i++) { 125 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 126 plat->rx_queues_cfg[i].chan = i; 127 128 /* Disable Priority config by default */ 129 plat->rx_queues_cfg[i].use_prio = false; 130 131 /* Disable RX queues routing by default */ 132 plat->rx_queues_cfg[i].pkt_route = 0x0; 133 } 134 135 for (i = 0; i < plat->tx_queues_to_use; i++) { 136 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 137 138 /* Disable Priority config by default */ 139 plat->tx_queues_cfg[i].use_prio = false; 140 } 141 142 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 143 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 144 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 145 146 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 147 plat->tx_queues_cfg[0].weight = 0x09; 148 plat->tx_queues_cfg[1].weight = 0x0A; 149 plat->tx_queues_cfg[2].weight = 0x0B; 150 plat->tx_queues_cfg[3].weight = 0x0C; 151 plat->tx_queues_cfg[4].weight = 0x0D; 152 plat->tx_queues_cfg[5].weight = 0x0E; 153 plat->tx_queues_cfg[6].weight = 0x0F; 154 plat->tx_queues_cfg[7].weight = 0x10; 155 156 plat->dma_cfg->pbl = 32; 157 plat->dma_cfg->pblx8 = true; 158 plat->dma_cfg->fixed_burst = 0; 159 plat->dma_cfg->mixed_burst = 0; 160 plat->dma_cfg->aal = 0; 161 162 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 163 GFP_KERNEL); 164 if (!plat->axi) 165 return -ENOMEM; 166 167 plat->axi->axi_lpi_en = 0; 168 plat->axi->axi_xit_frm = 0; 169 plat->axi->axi_wr_osr_lmt = 1; 170 plat->axi->axi_rd_osr_lmt = 1; 171 plat->axi->axi_blen[0] = 4; 172 plat->axi->axi_blen[1] = 8; 173 plat->axi->axi_blen[2] = 16; 174 175 plat->ptp_max_adj = plat->clk_ptp_rate; 176 177 /* Set system clock */ 178 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 179 "stmmac-clk", NULL, 0, 180 plat->clk_ptp_rate); 181 182 if (IS_ERR(plat->stmmac_clk)) { 183 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 184 plat->stmmac_clk = NULL; 185 } 186 clk_prepare_enable(plat->stmmac_clk); 187 188 /* Set default value for multicast hash bins */ 189 plat->multicast_filter_bins = HASH_TABLE_SIZE; 190 191 /* Set default value for unicast filter entries */ 192 plat->unicast_filter_entries = 1; 193 194 /* Set the maxmtu to a default of JUMBO_LEN */ 195 plat->maxmtu = JUMBO_LEN; 196 197 return 0; 198 } 199 200 static int ehl_common_data(struct pci_dev *pdev, 201 struct plat_stmmacenet_data *plat) 202 { 203 int ret; 204 205 plat->rx_queues_to_use = 8; 206 plat->tx_queues_to_use = 8; 207 plat->clk_ptp_rate = 200000000; 208 ret = intel_mgbe_common_data(pdev, plat); 209 if (ret) 210 return ret; 211 212 return 0; 213 } 214 215 static int ehl_sgmii_data(struct pci_dev *pdev, 216 struct plat_stmmacenet_data *plat) 217 { 218 plat->bus_id = 1; 219 plat->phy_addr = 0; 220 plat->interface = PHY_INTERFACE_MODE_SGMII; 221 return ehl_common_data(pdev, plat); 222 } 223 224 static struct stmmac_pci_info ehl_sgmii1g_pci_info = { 225 .setup = ehl_sgmii_data, 226 }; 227 228 static int ehl_rgmii_data(struct pci_dev *pdev, 229 struct plat_stmmacenet_data *plat) 230 { 231 plat->bus_id = 1; 232 plat->phy_addr = 0; 233 plat->interface = PHY_INTERFACE_MODE_RGMII; 234 return ehl_common_data(pdev, plat); 235 } 236 237 static struct stmmac_pci_info ehl_rgmii1g_pci_info = { 238 .setup = ehl_rgmii_data, 239 }; 240 241 static int tgl_common_data(struct pci_dev *pdev, 242 struct plat_stmmacenet_data *plat) 243 { 244 int ret; 245 246 plat->rx_queues_to_use = 6; 247 plat->tx_queues_to_use = 4; 248 plat->clk_ptp_rate = 200000000; 249 ret = intel_mgbe_common_data(pdev, plat); 250 if (ret) 251 return ret; 252 253 return 0; 254 } 255 256 static int tgl_sgmii_data(struct pci_dev *pdev, 257 struct plat_stmmacenet_data *plat) 258 { 259 plat->bus_id = 1; 260 plat->phy_addr = 0; 261 plat->interface = PHY_INTERFACE_MODE_SGMII; 262 return tgl_common_data(pdev, plat); 263 } 264 265 static struct stmmac_pci_info tgl_sgmii1g_pci_info = { 266 .setup = tgl_sgmii_data, 267 }; 268 269 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 270 { 271 .func = 6, 272 .phy_addr = 1, 273 }, 274 }; 275 276 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 277 .func = galileo_stmmac_func_data, 278 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 279 }; 280 281 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 282 { 283 .func = 6, 284 .phy_addr = 1, 285 }, 286 { 287 .func = 7, 288 .phy_addr = 1, 289 }, 290 }; 291 292 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 293 .func = iot2040_stmmac_func_data, 294 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 295 }; 296 297 static const struct dmi_system_id quark_pci_dmi[] = { 298 { 299 .matches = { 300 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 301 }, 302 .driver_data = (void *)&galileo_stmmac_dmi_data, 303 }, 304 { 305 .matches = { 306 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 307 }, 308 .driver_data = (void *)&galileo_stmmac_dmi_data, 309 }, 310 /* 311 * There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 312 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 313 * has only one pci network device while other asset tags are 314 * for IOT2040 which has two. 315 */ 316 { 317 .matches = { 318 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 319 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 320 "6ES7647-0AA00-0YA2"), 321 }, 322 .driver_data = (void *)&galileo_stmmac_dmi_data, 323 }, 324 { 325 .matches = { 326 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 327 }, 328 .driver_data = (void *)&iot2040_stmmac_dmi_data, 329 }, 330 {} 331 }; 332 333 static int quark_default_data(struct pci_dev *pdev, 334 struct plat_stmmacenet_data *plat) 335 { 336 int ret; 337 338 /* Set common default data first */ 339 common_default_data(plat); 340 341 /* 342 * Refuse to load the driver and register net device if MAC controller 343 * does not connect to any PHY interface. 344 */ 345 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 346 if (ret < 0) { 347 /* Return error to the caller on DMI enabled boards. */ 348 if (dmi_get_system_info(DMI_BOARD_NAME)) 349 return ret; 350 351 /* 352 * Galileo boards with old firmware don't support DMI. We always 353 * use 1 here as PHY address, so at least the first found MAC 354 * controller would be probed. 355 */ 356 ret = 1; 357 } 358 359 plat->bus_id = pci_dev_id(pdev); 360 plat->phy_addr = ret; 361 plat->interface = PHY_INTERFACE_MODE_RMII; 362 363 plat->dma_cfg->pbl = 16; 364 plat->dma_cfg->pblx8 = true; 365 plat->dma_cfg->fixed_burst = 1; 366 /* AXI (TODO) */ 367 368 return 0; 369 } 370 371 static const struct stmmac_pci_info quark_pci_info = { 372 .setup = quark_default_data, 373 }; 374 375 static int snps_gmac5_default_data(struct pci_dev *pdev, 376 struct plat_stmmacenet_data *plat) 377 { 378 int i; 379 380 plat->clk_csr = 5; 381 plat->has_gmac4 = 1; 382 plat->force_sf_dma_mode = 1; 383 plat->tso_en = 1; 384 plat->pmt = 1; 385 386 /* Set default value for multicast hash bins */ 387 plat->multicast_filter_bins = HASH_TABLE_SIZE; 388 389 /* Set default value for unicast filter entries */ 390 plat->unicast_filter_entries = 1; 391 392 /* Set the maxmtu to a default of JUMBO_LEN */ 393 plat->maxmtu = JUMBO_LEN; 394 395 /* Set default number of RX and TX queues to use */ 396 plat->tx_queues_to_use = 4; 397 plat->rx_queues_to_use = 4; 398 399 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 400 for (i = 0; i < plat->tx_queues_to_use; i++) { 401 plat->tx_queues_cfg[i].use_prio = false; 402 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 403 plat->tx_queues_cfg[i].weight = 25; 404 if (i > 0) 405 plat->tx_queues_cfg[i].tbs_en = 1; 406 } 407 408 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 409 for (i = 0; i < plat->rx_queues_to_use; i++) { 410 plat->rx_queues_cfg[i].use_prio = false; 411 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 412 plat->rx_queues_cfg[i].pkt_route = 0x0; 413 plat->rx_queues_cfg[i].chan = i; 414 } 415 416 plat->bus_id = 1; 417 plat->phy_addr = -1; 418 plat->interface = PHY_INTERFACE_MODE_GMII; 419 420 plat->dma_cfg->pbl = 32; 421 plat->dma_cfg->pblx8 = true; 422 423 /* Axi Configuration */ 424 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL); 425 if (!plat->axi) 426 return -ENOMEM; 427 428 plat->axi->axi_wr_osr_lmt = 31; 429 plat->axi->axi_rd_osr_lmt = 31; 430 431 plat->axi->axi_fb = false; 432 plat->axi->axi_blen[0] = 4; 433 plat->axi->axi_blen[1] = 8; 434 plat->axi->axi_blen[2] = 16; 435 plat->axi->axi_blen[3] = 32; 436 437 return 0; 438 } 439 440 static const struct stmmac_pci_info snps_gmac5_pci_info = { 441 .setup = snps_gmac5_default_data, 442 }; 443 444 /** 445 * stmmac_pci_probe 446 * 447 * @pdev: pci device pointer 448 * @id: pointer to table of device id/id's. 449 * 450 * Description: This probing function gets called for all PCI devices which 451 * match the ID table and are not "owned" by other driver yet. This function 452 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 453 * matches the device. The probe functions returns zero when the driver choose 454 * to take "ownership" of the device or an error code(-ve no) otherwise. 455 */ 456 static int stmmac_pci_probe(struct pci_dev *pdev, 457 const struct pci_device_id *id) 458 { 459 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 460 struct plat_stmmacenet_data *plat; 461 struct stmmac_resources res; 462 int i; 463 int ret; 464 465 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 466 if (!plat) 467 return -ENOMEM; 468 469 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 470 sizeof(*plat->mdio_bus_data), 471 GFP_KERNEL); 472 if (!plat->mdio_bus_data) 473 return -ENOMEM; 474 475 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 476 GFP_KERNEL); 477 if (!plat->dma_cfg) 478 return -ENOMEM; 479 480 /* Enable pci device */ 481 ret = pci_enable_device(pdev); 482 if (ret) { 483 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 484 __func__); 485 return ret; 486 } 487 488 /* Get the base address of device */ 489 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 490 if (pci_resource_len(pdev, i) == 0) 491 continue; 492 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev)); 493 if (ret) 494 return ret; 495 break; 496 } 497 498 pci_set_master(pdev); 499 500 ret = info->setup(pdev, plat); 501 if (ret) 502 return ret; 503 504 pci_enable_msi(pdev); 505 506 memset(&res, 0, sizeof(res)); 507 res.addr = pcim_iomap_table(pdev)[i]; 508 res.wol_irq = pdev->irq; 509 res.irq = pdev->irq; 510 511 return stmmac_dvr_probe(&pdev->dev, plat, &res); 512 } 513 514 /** 515 * stmmac_pci_remove 516 * 517 * @pdev: platform device pointer 518 * Description: this function calls the main to free the net resources 519 * and releases the PCI resources. 520 */ 521 static void stmmac_pci_remove(struct pci_dev *pdev) 522 { 523 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 524 struct stmmac_priv *priv = netdev_priv(ndev); 525 int i; 526 527 stmmac_dvr_remove(&pdev->dev); 528 529 if (priv->plat->stmmac_clk) 530 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 531 532 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 533 if (pci_resource_len(pdev, i) == 0) 534 continue; 535 pcim_iounmap_regions(pdev, BIT(i)); 536 break; 537 } 538 539 pci_disable_device(pdev); 540 } 541 542 static int __maybe_unused stmmac_pci_suspend(struct device *dev) 543 { 544 struct pci_dev *pdev = to_pci_dev(dev); 545 int ret; 546 547 ret = stmmac_suspend(dev); 548 if (ret) 549 return ret; 550 551 ret = pci_save_state(pdev); 552 if (ret) 553 return ret; 554 555 pci_disable_device(pdev); 556 pci_wake_from_d3(pdev, true); 557 return 0; 558 } 559 560 static int __maybe_unused stmmac_pci_resume(struct device *dev) 561 { 562 struct pci_dev *pdev = to_pci_dev(dev); 563 int ret; 564 565 pci_restore_state(pdev); 566 pci_set_power_state(pdev, PCI_D0); 567 568 ret = pci_enable_device(pdev); 569 if (ret) 570 return ret; 571 572 pci_set_master(pdev); 573 574 return stmmac_resume(dev); 575 } 576 577 static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); 578 579 /* synthetic ID, no official vendor */ 580 #define PCI_VENDOR_ID_STMMAC 0x700 581 582 #define STMMAC_QUARK_ID 0x0937 583 #define STMMAC_DEVICE_ID 0x1108 584 #define STMMAC_EHL_RGMII1G_ID 0x4b30 585 #define STMMAC_EHL_SGMII1G_ID 0x4b31 586 #define STMMAC_TGL_SGMII1G_ID 0xa0ac 587 #define STMMAC_GMAC5_ID 0x7102 588 589 #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ 590 PCI_VDEVICE(vendor_id, dev_id), \ 591 .driver_data = (kernel_ulong_t)&info \ 592 } 593 594 static const struct pci_device_id stmmac_id_table[] = { 595 STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info), 596 STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), 597 STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), 598 STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info), 599 STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), 600 STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info), 601 STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info), 602 {} 603 }; 604 605 MODULE_DEVICE_TABLE(pci, stmmac_id_table); 606 607 static struct pci_driver stmmac_pci_driver = { 608 .name = STMMAC_RESOURCE_NAME, 609 .id_table = stmmac_id_table, 610 .probe = stmmac_pci_probe, 611 .remove = stmmac_pci_remove, 612 .driver = { 613 .pm = &stmmac_pm_ops, 614 }, 615 }; 616 617 module_pci_driver(stmmac_pci_driver); 618 619 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet PCI driver"); 620 MODULE_AUTHOR("Rayagond Kokatanur <rayagond.kokatanur@vayavyalabs.com>"); 621 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 622 MODULE_LICENSE("GPL"); 623