1 /******************************************************************************* 2 STMMAC Ethernet Driver -- MDIO bus implementation 3 Provides Bus interface for MII registers 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Carl Shaw <carl.shaw@st.com> 24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 25 *******************************************************************************/ 26 27 #include <linux/mii.h> 28 #include <linux/phy.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/of_gpio.h> 32 #include <linux/of_mdio.h> 33 #include <asm/io.h> 34 35 #include "stmmac.h" 36 37 #define MII_BUSY 0x00000001 38 #define MII_WRITE 0x00000002 39 40 /* GMAC4 defines */ 41 #define MII_GMAC4_GOC_SHIFT 2 42 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT) 43 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT) 44 45 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr) 46 { 47 unsigned long curr; 48 unsigned long finish = jiffies + 3 * HZ; 49 50 do { 51 curr = jiffies; 52 if (readl(ioaddr + mii_addr) & MII_BUSY) 53 cpu_relax(); 54 else 55 return 0; 56 } while (!time_after_eq(curr, finish)); 57 58 return -EBUSY; 59 } 60 61 /** 62 * stmmac_mdio_read 63 * @bus: points to the mii_bus structure 64 * @phyaddr: MII addr 65 * @phyreg: MII reg 66 * Description: it reads data from the MII register from within the phy device. 67 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 68 * accessing the PHY registers. 69 * Fortunately, it seems this has no drawback for the 7109 MAC. 70 */ 71 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 72 { 73 struct net_device *ndev = bus->priv; 74 struct stmmac_priv *priv = netdev_priv(ndev); 75 unsigned int mii_address = priv->hw->mii.addr; 76 unsigned int mii_data = priv->hw->mii.data; 77 78 int data; 79 u32 value = MII_BUSY; 80 81 value |= (phyaddr << priv->hw->mii.addr_shift) 82 & priv->hw->mii.addr_mask; 83 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 84 value |= (priv->clk_csr & priv->hw->mii.clk_csr_mask) 85 << priv->hw->mii.clk_csr_shift; 86 if (priv->plat->has_gmac4) 87 value |= MII_GMAC4_READ; 88 89 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) 90 return -EBUSY; 91 92 writel(value, priv->ioaddr + mii_address); 93 94 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) 95 return -EBUSY; 96 97 /* Read the data from the MII data register */ 98 data = (int)readl(priv->ioaddr + mii_data); 99 100 return data; 101 } 102 103 /** 104 * stmmac_mdio_write 105 * @bus: points to the mii_bus structure 106 * @phyaddr: MII addr 107 * @phyreg: MII reg 108 * @phydata: phy data 109 * Description: it writes the data into the MII register from within the device. 110 */ 111 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, 112 u16 phydata) 113 { 114 struct net_device *ndev = bus->priv; 115 struct stmmac_priv *priv = netdev_priv(ndev); 116 unsigned int mii_address = priv->hw->mii.addr; 117 unsigned int mii_data = priv->hw->mii.data; 118 119 u32 value = MII_WRITE | MII_BUSY; 120 121 value |= (phyaddr << priv->hw->mii.addr_shift) 122 & priv->hw->mii.addr_mask; 123 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 124 125 value |= ((priv->clk_csr & priv->hw->mii.clk_csr_mask) 126 << priv->hw->mii.clk_csr_shift); 127 if (priv->plat->has_gmac4) 128 value |= MII_GMAC4_WRITE; 129 130 /* Wait until any existing MII operation is complete */ 131 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) 132 return -EBUSY; 133 134 /* Set the MII address register to write */ 135 writel(phydata, priv->ioaddr + mii_data); 136 writel(value, priv->ioaddr + mii_address); 137 138 /* Wait until any existing MII operation is complete */ 139 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address); 140 } 141 142 /** 143 * stmmac_mdio_reset 144 * @bus: points to the mii_bus structure 145 * Description: reset the MII bus 146 */ 147 int stmmac_mdio_reset(struct mii_bus *bus) 148 { 149 #if defined(CONFIG_STMMAC_PLATFORM) 150 struct net_device *ndev = bus->priv; 151 struct stmmac_priv *priv = netdev_priv(ndev); 152 unsigned int mii_address = priv->hw->mii.addr; 153 struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data; 154 155 #ifdef CONFIG_OF 156 if (priv->device->of_node) { 157 158 if (data->reset_gpio < 0) { 159 struct device_node *np = priv->device->of_node; 160 if (!np) 161 return 0; 162 163 data->reset_gpio = of_get_named_gpio(np, 164 "snps,reset-gpio", 0); 165 if (data->reset_gpio < 0) 166 return 0; 167 168 data->active_low = of_property_read_bool(np, 169 "snps,reset-active-low"); 170 of_property_read_u32_array(np, 171 "snps,reset-delays-us", data->delays, 3); 172 173 if (gpio_request(data->reset_gpio, "mdio-reset")) 174 return 0; 175 } 176 177 gpio_direction_output(data->reset_gpio, 178 data->active_low ? 1 : 0); 179 if (data->delays[0]) 180 msleep(DIV_ROUND_UP(data->delays[0], 1000)); 181 182 gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1); 183 if (data->delays[1]) 184 msleep(DIV_ROUND_UP(data->delays[1], 1000)); 185 186 gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0); 187 if (data->delays[2]) 188 msleep(DIV_ROUND_UP(data->delays[2], 1000)); 189 } 190 #endif 191 192 if (data->phy_reset) { 193 netdev_dbg(ndev, "stmmac_mdio_reset: calling phy_reset\n"); 194 data->phy_reset(priv->plat->bsp_priv); 195 } 196 197 /* This is a workaround for problems with the STE101P PHY. 198 * It doesn't complete its reset until at least one clock cycle 199 * on MDC, so perform a dummy mdio read. To be upadted for GMAC4 200 * if needed. 201 */ 202 if (!priv->plat->has_gmac4) 203 writel(0, priv->ioaddr + mii_address); 204 #endif 205 return 0; 206 } 207 208 /** 209 * stmmac_mdio_register 210 * @ndev: net device structure 211 * Description: it registers the MII bus 212 */ 213 int stmmac_mdio_register(struct net_device *ndev) 214 { 215 int err = 0; 216 struct mii_bus *new_bus; 217 struct stmmac_priv *priv = netdev_priv(ndev); 218 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 219 struct device_node *mdio_node = priv->plat->mdio_node; 220 int addr, found; 221 222 if (!mdio_bus_data) 223 return 0; 224 225 new_bus = mdiobus_alloc(); 226 if (new_bus == NULL) 227 return -ENOMEM; 228 229 if (mdio_bus_data->irqs) 230 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq)); 231 232 #ifdef CONFIG_OF 233 if (priv->device->of_node) 234 mdio_bus_data->reset_gpio = -1; 235 #endif 236 237 new_bus->name = "stmmac"; 238 new_bus->read = &stmmac_mdio_read; 239 new_bus->write = &stmmac_mdio_write; 240 241 new_bus->reset = &stmmac_mdio_reset; 242 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", 243 new_bus->name, priv->plat->bus_id); 244 new_bus->priv = ndev; 245 new_bus->phy_mask = mdio_bus_data->phy_mask; 246 new_bus->parent = priv->device; 247 248 if (mdio_node) 249 err = of_mdiobus_register(new_bus, mdio_node); 250 else 251 err = mdiobus_register(new_bus); 252 if (err != 0) { 253 netdev_err(ndev, "Cannot register the MDIO bus\n"); 254 goto bus_register_fail; 255 } 256 257 if (priv->plat->phy_node || mdio_node) 258 goto bus_register_done; 259 260 found = 0; 261 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 262 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr); 263 if (phydev) { 264 int act = 0; 265 char irq_num[4]; 266 char *irq_str; 267 268 /* 269 * If an IRQ was provided to be assigned after 270 * the bus probe, do it here. 271 */ 272 if ((mdio_bus_data->irqs == NULL) && 273 (mdio_bus_data->probed_phy_irq > 0)) { 274 new_bus->irq[addr] = 275 mdio_bus_data->probed_phy_irq; 276 phydev->irq = mdio_bus_data->probed_phy_irq; 277 } 278 279 /* 280 * If we're going to bind the MAC to this PHY bus, 281 * and no PHY number was provided to the MAC, 282 * use the one probed here. 283 */ 284 if (priv->plat->phy_addr == -1) 285 priv->plat->phy_addr = addr; 286 287 act = (priv->plat->phy_addr == addr); 288 switch (phydev->irq) { 289 case PHY_POLL: 290 irq_str = "POLL"; 291 break; 292 case PHY_IGNORE_INTERRUPT: 293 irq_str = "IGNORE"; 294 break; 295 default: 296 sprintf(irq_num, "%d", phydev->irq); 297 irq_str = irq_num; 298 break; 299 } 300 netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n", 301 phydev->phy_id, addr, 302 irq_str, phydev_name(phydev), 303 act ? " active" : ""); 304 found = 1; 305 } 306 } 307 308 if (!found && !mdio_node) { 309 netdev_warn(ndev, "No PHY found\n"); 310 mdiobus_unregister(new_bus); 311 mdiobus_free(new_bus); 312 return -ENODEV; 313 } 314 315 bus_register_done: 316 priv->mii = new_bus; 317 318 return 0; 319 320 bus_register_fail: 321 mdiobus_free(new_bus); 322 return err; 323 } 324 325 /** 326 * stmmac_mdio_unregister 327 * @ndev: net device structure 328 * Description: it unregisters the MII bus 329 */ 330 int stmmac_mdio_unregister(struct net_device *ndev) 331 { 332 struct stmmac_priv *priv = netdev_priv(ndev); 333 334 if (!priv->mii) 335 return 0; 336 337 mdiobus_unregister(priv->mii); 338 priv->mii->priv = NULL; 339 mdiobus_free(priv->mii); 340 priv->mii = NULL; 341 342 return 0; 343 } 344