1 /******************************************************************************* 2 STMMAC Ethernet Driver -- MDIO bus implementation 3 Provides Bus interface for MII registers 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Carl Shaw <carl.shaw@st.com> 24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 25 *******************************************************************************/ 26 27 #include <linux/mii.h> 28 #include <linux/phy.h> 29 #include <linux/slab.h> 30 #include <asm/io.h> 31 32 #include "stmmac.h" 33 34 #define MII_BUSY 0x00000001 35 #define MII_WRITE 0x00000002 36 37 /** 38 * stmmac_mdio_read 39 * @bus: points to the mii_bus structure 40 * @phyaddr: MII addr reg bits 15-11 41 * @phyreg: MII addr reg bits 10-6 42 * Description: it reads data from the MII register from within the phy device. 43 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 44 * accessing the PHY registers. 45 * Fortunately, it seems this has no drawback for the 7109 MAC. 46 */ 47 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 48 { 49 struct net_device *ndev = bus->priv; 50 struct stmmac_priv *priv = netdev_priv(ndev); 51 unsigned int mii_address = priv->hw->mii.addr; 52 unsigned int mii_data = priv->hw->mii.data; 53 54 int data; 55 u16 regValue = (((phyaddr << 11) & (0x0000F800)) | 56 ((phyreg << 6) & (0x000007C0))); 57 regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); 58 59 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 60 writel(regValue, priv->ioaddr + mii_address); 61 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 62 63 /* Read the data from the MII data register */ 64 data = (int)readl(priv->ioaddr + mii_data); 65 66 return data; 67 } 68 69 /** 70 * stmmac_mdio_write 71 * @bus: points to the mii_bus structure 72 * @phyaddr: MII addr reg bits 15-11 73 * @phyreg: MII addr reg bits 10-6 74 * @phydata: phy data 75 * Description: it writes the data into the MII register from within the device. 76 */ 77 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, 78 u16 phydata) 79 { 80 struct net_device *ndev = bus->priv; 81 struct stmmac_priv *priv = netdev_priv(ndev); 82 unsigned int mii_address = priv->hw->mii.addr; 83 unsigned int mii_data = priv->hw->mii.data; 84 85 u16 value = 86 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) 87 | MII_WRITE; 88 89 value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); 90 91 92 /* Wait until any existing MII operation is complete */ 93 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 94 95 /* Set the MII address register to write */ 96 writel(phydata, priv->ioaddr + mii_data); 97 writel(value, priv->ioaddr + mii_address); 98 99 /* Wait until any existing MII operation is complete */ 100 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 101 102 return 0; 103 } 104 105 /** 106 * stmmac_mdio_reset 107 * @bus: points to the mii_bus structure 108 * Description: reset the MII bus 109 */ 110 static int stmmac_mdio_reset(struct mii_bus *bus) 111 { 112 #if defined(CONFIG_STMMAC_PLATFORM) 113 struct net_device *ndev = bus->priv; 114 struct stmmac_priv *priv = netdev_priv(ndev); 115 unsigned int mii_address = priv->hw->mii.addr; 116 117 if (priv->plat->mdio_bus_data->phy_reset) { 118 pr_debug("stmmac_mdio_reset: calling phy_reset\n"); 119 priv->plat->mdio_bus_data->phy_reset(priv->plat->bsp_priv); 120 } 121 122 /* This is a workaround for problems with the STE101P PHY. 123 * It doesn't complete its reset until at least one clock cycle 124 * on MDC, so perform a dummy mdio read. 125 */ 126 writel(0, priv->ioaddr + mii_address); 127 #endif 128 return 0; 129 } 130 131 /** 132 * stmmac_mdio_register 133 * @ndev: net device structure 134 * Description: it registers the MII bus 135 */ 136 int stmmac_mdio_register(struct net_device *ndev) 137 { 138 int err = 0; 139 struct mii_bus *new_bus; 140 int *irqlist; 141 struct stmmac_priv *priv = netdev_priv(ndev); 142 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 143 int addr, found; 144 145 if (!mdio_bus_data) 146 return 0; 147 148 new_bus = mdiobus_alloc(); 149 if (new_bus == NULL) 150 return -ENOMEM; 151 152 if (mdio_bus_data->irqs) 153 irqlist = mdio_bus_data->irqs; 154 else 155 irqlist = priv->mii_irq; 156 157 new_bus->name = "stmmac"; 158 new_bus->read = &stmmac_mdio_read; 159 new_bus->write = &stmmac_mdio_write; 160 new_bus->reset = &stmmac_mdio_reset; 161 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", 162 new_bus->name, mdio_bus_data->bus_id); 163 new_bus->priv = ndev; 164 new_bus->irq = irqlist; 165 new_bus->phy_mask = mdio_bus_data->phy_mask; 166 new_bus->parent = priv->device; 167 err = mdiobus_register(new_bus); 168 if (err != 0) { 169 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name); 170 goto bus_register_fail; 171 } 172 173 priv->mii = new_bus; 174 175 found = 0; 176 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 177 struct phy_device *phydev = new_bus->phy_map[addr]; 178 if (phydev) { 179 int act = 0; 180 char irq_num[4]; 181 char *irq_str; 182 183 /* 184 * If an IRQ was provided to be assigned after 185 * the bus probe, do it here. 186 */ 187 if ((mdio_bus_data->irqs == NULL) && 188 (mdio_bus_data->probed_phy_irq > 0)) { 189 irqlist[addr] = mdio_bus_data->probed_phy_irq; 190 phydev->irq = mdio_bus_data->probed_phy_irq; 191 } 192 193 /* 194 * If we're going to bind the MAC to this PHY bus, 195 * and no PHY number was provided to the MAC, 196 * use the one probed here. 197 */ 198 if ((priv->plat->bus_id == mdio_bus_data->bus_id) && 199 (priv->plat->phy_addr == -1)) 200 priv->plat->phy_addr = addr; 201 202 act = (priv->plat->bus_id == mdio_bus_data->bus_id) && 203 (priv->plat->phy_addr == addr); 204 switch (phydev->irq) { 205 case PHY_POLL: 206 irq_str = "POLL"; 207 break; 208 case PHY_IGNORE_INTERRUPT: 209 irq_str = "IGNORE"; 210 break; 211 default: 212 sprintf(irq_num, "%d", phydev->irq); 213 irq_str = irq_num; 214 break; 215 } 216 pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n", 217 ndev->name, phydev->phy_id, addr, 218 irq_str, dev_name(&phydev->dev), 219 act ? " active" : ""); 220 found = 1; 221 } 222 } 223 224 if (!found) 225 pr_warning("%s: No PHY found\n", ndev->name); 226 227 return 0; 228 229 bus_register_fail: 230 mdiobus_free(new_bus); 231 return err; 232 } 233 234 /** 235 * stmmac_mdio_unregister 236 * @ndev: net device structure 237 * Description: it unregisters the MII bus 238 */ 239 int stmmac_mdio_unregister(struct net_device *ndev) 240 { 241 struct stmmac_priv *priv = netdev_priv(ndev); 242 243 mdiobus_unregister(priv->mii); 244 priv->mii->priv = NULL; 245 mdiobus_free(priv->mii); 246 priv->mii = NULL; 247 248 return 0; 249 } 250