1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3   STMMAC Ethernet Driver -- MDIO bus implementation
4   Provides Bus interface for MII registers
5 
6   Copyright (C) 2007-2009  STMicroelectronics Ltd
7 
8 
9   Author: Carl Shaw <carl.shaw@st.com>
10   Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 *******************************************************************************/
12 
13 #include <linux/gpio/consumer.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/mii.h>
17 #include <linux/of_mdio.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/phy.h>
20 #include <linux/property.h>
21 #include <linux/slab.h>
22 
23 #include "dwxgmac2.h"
24 #include "stmmac.h"
25 
26 #define MII_BUSY 0x00000001
27 #define MII_WRITE 0x00000002
28 #define MII_DATA_MASK GENMASK(15, 0)
29 
30 /* GMAC4 defines */
31 #define MII_GMAC4_GOC_SHIFT		2
32 #define MII_GMAC4_REG_ADDR_SHIFT	16
33 #define MII_GMAC4_WRITE			(1 << MII_GMAC4_GOC_SHIFT)
34 #define MII_GMAC4_READ			(3 << MII_GMAC4_GOC_SHIFT)
35 #define MII_GMAC4_C45E			BIT(1)
36 
37 /* XGMAC defines */
38 #define MII_XGMAC_SADDR			BIT(18)
39 #define MII_XGMAC_CMD_SHIFT		16
40 #define MII_XGMAC_WRITE			(1 << MII_XGMAC_CMD_SHIFT)
41 #define MII_XGMAC_READ			(3 << MII_XGMAC_CMD_SHIFT)
42 #define MII_XGMAC_BUSY			BIT(22)
43 #define MII_XGMAC_MAX_C22ADDR		3
44 #define MII_XGMAC_C22P_MASK		GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
45 #define MII_XGMAC_PA_SHIFT		16
46 #define MII_XGMAC_DA_SHIFT		21
47 
48 static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
49 				     int devad, int phyreg, u32 *hw_addr)
50 {
51 	u32 tmp;
52 
53 	/* Set port as Clause 45 */
54 	tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
55 	tmp &= ~BIT(phyaddr);
56 	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
57 
58 	*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
59 	*hw_addr |= devad << MII_XGMAC_DA_SHIFT;
60 }
61 
62 static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
63 				     int phyreg, u32 *hw_addr)
64 {
65 	u32 tmp;
66 
67 	/* Set port as Clause 22 */
68 	tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
69 	tmp &= ~MII_XGMAC_C22P_MASK;
70 	tmp |= BIT(phyaddr);
71 	writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
72 
73 	*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
74 }
75 
76 static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr,
77 				   u32 value)
78 {
79 	unsigned int mii_address = priv->hw->mii.addr;
80 	unsigned int mii_data = priv->hw->mii.data;
81 	u32 tmp;
82 	int ret;
83 
84 	ret = pm_runtime_resume_and_get(priv->device);
85 	if (ret < 0)
86 		return ret;
87 
88 	/* Wait until any existing MII operation is complete */
89 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
90 			       !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
91 		ret = -EBUSY;
92 		goto err_disable_clks;
93 	}
94 
95 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
96 		& priv->hw->mii.clk_csr_mask;
97 	value |= MII_XGMAC_READ;
98 
99 	/* Wait until any existing MII operation is complete */
100 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
101 			       !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
102 		ret = -EBUSY;
103 		goto err_disable_clks;
104 	}
105 
106 	/* Set the MII address register to read */
107 	writel(addr, priv->ioaddr + mii_address);
108 	writel(value, priv->ioaddr + mii_data);
109 
110 	/* Wait until any existing MII operation is complete */
111 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
112 			       !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
113 		ret = -EBUSY;
114 		goto err_disable_clks;
115 	}
116 
117 	/* Read the data from the MII data register */
118 	ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
119 
120 err_disable_clks:
121 	pm_runtime_put(priv->device);
122 
123 	return ret;
124 }
125 
126 static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr,
127 				       int phyreg)
128 {
129 	struct net_device *ndev = bus->priv;
130 	struct stmmac_priv *priv;
131 	u32 addr;
132 
133 	priv = netdev_priv(ndev);
134 
135 	/* HW does not support C22 addr >= 4 */
136 	if (phyaddr > MII_XGMAC_MAX_C22ADDR)
137 		return -ENODEV;
138 
139 	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
140 
141 	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
142 }
143 
144 static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr,
145 				       int devad, int phyreg)
146 {
147 	struct net_device *ndev = bus->priv;
148 	struct stmmac_priv *priv;
149 	u32 addr;
150 
151 	priv = netdev_priv(ndev);
152 
153 	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
154 
155 	return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY);
156 }
157 
158 static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr,
159 				    u32 value, u16 phydata)
160 {
161 	unsigned int mii_address = priv->hw->mii.addr;
162 	unsigned int mii_data = priv->hw->mii.data;
163 	u32 tmp;
164 	int ret;
165 
166 	ret = pm_runtime_resume_and_get(priv->device);
167 	if (ret < 0)
168 		return ret;
169 
170 	/* Wait until any existing MII operation is complete */
171 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
172 			       !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
173 		ret = -EBUSY;
174 		goto err_disable_clks;
175 	}
176 
177 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
178 		& priv->hw->mii.clk_csr_mask;
179 	value |= phydata;
180 	value |= MII_XGMAC_WRITE;
181 
182 	/* Wait until any existing MII operation is complete */
183 	if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
184 			       !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
185 		ret = -EBUSY;
186 		goto err_disable_clks;
187 	}
188 
189 	/* Set the MII address register to write */
190 	writel(addr, priv->ioaddr + mii_address);
191 	writel(value, priv->ioaddr + mii_data);
192 
193 	/* Wait until any existing MII operation is complete */
194 	ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
195 				 !(tmp & MII_XGMAC_BUSY), 100, 10000);
196 
197 err_disable_clks:
198 	pm_runtime_put(priv->device);
199 
200 	return ret;
201 }
202 
203 static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr,
204 					int phyreg, u16 phydata)
205 {
206 	struct net_device *ndev = bus->priv;
207 	struct stmmac_priv *priv;
208 	u32 addr;
209 
210 	priv = netdev_priv(ndev);
211 
212 	/* HW does not support C22 addr >= 4 */
213 	if (phyaddr > MII_XGMAC_MAX_C22ADDR)
214 		return -ENODEV;
215 
216 	stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
217 
218 	return stmmac_xgmac2_mdio_write(priv, addr,
219 					MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata);
220 }
221 
222 static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr,
223 					int devad, int phyreg, u16 phydata)
224 {
225 	struct net_device *ndev = bus->priv;
226 	struct stmmac_priv *priv;
227 	u32 addr;
228 
229 	priv = netdev_priv(ndev);
230 
231 	stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr);
232 
233 	return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY,
234 					phydata);
235 }
236 
237 static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value)
238 {
239 	unsigned int mii_address = priv->hw->mii.addr;
240 	unsigned int mii_data = priv->hw->mii.data;
241 	u32 v;
242 
243 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
244 			       100, 10000))
245 		return -EBUSY;
246 
247 	writel(data, priv->ioaddr + mii_data);
248 	writel(value, priv->ioaddr + mii_address);
249 
250 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
251 			       100, 10000))
252 		return -EBUSY;
253 
254 	/* Read the data from the MII data register */
255 	return readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
256 }
257 
258 /**
259  * stmmac_mdio_read_c22
260  * @bus: points to the mii_bus structure
261  * @phyaddr: MII addr
262  * @phyreg: MII reg
263  * Description: it reads data from the MII register from within the phy device.
264  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
265  * accessing the PHY registers.
266  * Fortunately, it seems this has no drawback for the 7109 MAC.
267  */
268 static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)
269 {
270 	struct net_device *ndev = bus->priv;
271 	struct stmmac_priv *priv = netdev_priv(ndev);
272 	u32 value = MII_BUSY;
273 	int data = 0;
274 
275 	data = pm_runtime_resume_and_get(priv->device);
276 	if (data < 0)
277 		return data;
278 
279 	value |= (phyaddr << priv->hw->mii.addr_shift)
280 		& priv->hw->mii.addr_mask;
281 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
282 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
283 		& priv->hw->mii.clk_csr_mask;
284 	if (priv->plat->has_gmac4)
285 		value |= MII_GMAC4_READ;
286 
287 	data = stmmac_mdio_read(priv, data, value);
288 
289 	pm_runtime_put(priv->device);
290 
291 	return data;
292 }
293 
294 /**
295  * stmmac_mdio_read_c45
296  * @bus: points to the mii_bus structure
297  * @phyaddr: MII addr
298  * @devad: device address to read
299  * @phyreg: MII reg
300  * Description: it reads data from the MII register from within the phy device.
301  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
302  * accessing the PHY registers.
303  * Fortunately, it seems this has no drawback for the 7109 MAC.
304  */
305 static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad,
306 				int phyreg)
307 {
308 	struct net_device *ndev = bus->priv;
309 	struct stmmac_priv *priv = netdev_priv(ndev);
310 	u32 value = MII_BUSY;
311 	int data = 0;
312 
313 	data = pm_runtime_get_sync(priv->device);
314 	if (data < 0) {
315 		pm_runtime_put_noidle(priv->device);
316 		return data;
317 	}
318 
319 	value |= (phyaddr << priv->hw->mii.addr_shift)
320 		& priv->hw->mii.addr_mask;
321 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
322 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
323 		& priv->hw->mii.clk_csr_mask;
324 	value |= MII_GMAC4_READ;
325 	value |= MII_GMAC4_C45E;
326 	value &= ~priv->hw->mii.reg_mask;
327 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
328 
329 	data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
330 
331 	data = stmmac_mdio_read(priv, data, value);
332 
333 	pm_runtime_put(priv->device);
334 
335 	return data;
336 }
337 
338 static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
339 {
340 	unsigned int mii_address = priv->hw->mii.addr;
341 	unsigned int mii_data = priv->hw->mii.data;
342 	u32 v;
343 
344 	/* Wait until any existing MII operation is complete */
345 	if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
346 			       100, 10000))
347 		return -EBUSY;
348 
349 	/* Set the MII address register to write */
350 	writel(data, priv->ioaddr + mii_data);
351 	writel(value, priv->ioaddr + mii_address);
352 
353 	/* Wait until any existing MII operation is complete */
354 	return readl_poll_timeout(priv->ioaddr + mii_address, v,
355 				  !(v & MII_BUSY), 100, 10000);
356 }
357 
358 /**
359  * stmmac_mdio_write_c22
360  * @bus: points to the mii_bus structure
361  * @phyaddr: MII addr
362  * @phyreg: MII reg
363  * @phydata: phy data
364  * Description: it writes the data into the MII register from within the device.
365  */
366 static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg,
367 				 u16 phydata)
368 {
369 	struct net_device *ndev = bus->priv;
370 	struct stmmac_priv *priv = netdev_priv(ndev);
371 	int ret, data = phydata;
372 	u32 value = MII_BUSY;
373 
374 	ret = pm_runtime_resume_and_get(priv->device);
375 	if (ret < 0)
376 		return ret;
377 
378 	value |= (phyaddr << priv->hw->mii.addr_shift)
379 		& priv->hw->mii.addr_mask;
380 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
381 
382 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
383 		& priv->hw->mii.clk_csr_mask;
384 	if (priv->plat->has_gmac4)
385 		value |= MII_GMAC4_WRITE;
386 	else
387 		value |= MII_WRITE;
388 
389 	ret = stmmac_mdio_write(priv, data, value);
390 
391 	pm_runtime_put(priv->device);
392 
393 	return ret;
394 }
395 
396 /**
397  * stmmac_mdio_write_c45
398  * @bus: points to the mii_bus structure
399  * @phyaddr: MII addr
400  * @phyreg: MII reg
401  * @devad: device address to read
402  * @phydata: phy data
403  * Description: it writes the data into the MII register from within the device.
404  */
405 static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr,
406 				 int devad, int phyreg, u16 phydata)
407 {
408 	struct net_device *ndev = bus->priv;
409 	struct stmmac_priv *priv = netdev_priv(ndev);
410 	int ret, data = phydata;
411 	u32 value = MII_BUSY;
412 
413 	ret = pm_runtime_get_sync(priv->device);
414 	if (ret < 0) {
415 		pm_runtime_put_noidle(priv->device);
416 		return ret;
417 	}
418 
419 	value |= (phyaddr << priv->hw->mii.addr_shift)
420 		& priv->hw->mii.addr_mask;
421 	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
422 
423 	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
424 		& priv->hw->mii.clk_csr_mask;
425 
426 	value |= MII_GMAC4_WRITE;
427 	value |= MII_GMAC4_C45E;
428 	value &= ~priv->hw->mii.reg_mask;
429 	value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
430 
431 	data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
432 
433 	ret = stmmac_mdio_write(priv, data, value);
434 
435 	pm_runtime_put(priv->device);
436 
437 	return ret;
438 }
439 
440 /**
441  * stmmac_mdio_reset
442  * @bus: points to the mii_bus structure
443  * Description: reset the MII bus
444  */
445 int stmmac_mdio_reset(struct mii_bus *bus)
446 {
447 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
448 	struct net_device *ndev = bus->priv;
449 	struct stmmac_priv *priv = netdev_priv(ndev);
450 	unsigned int mii_address = priv->hw->mii.addr;
451 
452 #ifdef CONFIG_OF
453 	if (priv->device->of_node) {
454 		struct gpio_desc *reset_gpio;
455 		u32 delays[3] = { 0, 0, 0 };
456 
457 		reset_gpio = devm_gpiod_get_optional(priv->device,
458 						     "snps,reset",
459 						     GPIOD_OUT_LOW);
460 		if (IS_ERR(reset_gpio))
461 			return PTR_ERR(reset_gpio);
462 
463 		device_property_read_u32_array(priv->device,
464 					       "snps,reset-delays-us",
465 					       delays, ARRAY_SIZE(delays));
466 
467 		if (delays[0])
468 			msleep(DIV_ROUND_UP(delays[0], 1000));
469 
470 		gpiod_set_value_cansleep(reset_gpio, 1);
471 		if (delays[1])
472 			msleep(DIV_ROUND_UP(delays[1], 1000));
473 
474 		gpiod_set_value_cansleep(reset_gpio, 0);
475 		if (delays[2])
476 			msleep(DIV_ROUND_UP(delays[2], 1000));
477 	}
478 #endif
479 
480 	/* This is a workaround for problems with the STE101P PHY.
481 	 * It doesn't complete its reset until at least one clock cycle
482 	 * on MDC, so perform a dummy mdio read. To be updated for GMAC4
483 	 * if needed.
484 	 */
485 	if (!priv->plat->has_gmac4)
486 		writel(0, priv->ioaddr + mii_address);
487 #endif
488 	return 0;
489 }
490 
491 int stmmac_xpcs_setup(struct mii_bus *bus)
492 {
493 	struct net_device *ndev = bus->priv;
494 	struct mdio_device *mdiodev;
495 	struct stmmac_priv *priv;
496 	struct dw_xpcs *xpcs;
497 	int mode, addr;
498 
499 	priv = netdev_priv(ndev);
500 	mode = priv->plat->phy_interface;
501 
502 	/* Try to probe the XPCS by scanning all addresses. */
503 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
504 		mdiodev = mdio_device_create(bus, addr);
505 		if (IS_ERR(mdiodev))
506 			continue;
507 
508 		xpcs = xpcs_create(mdiodev, mode);
509 		if (IS_ERR_OR_NULL(xpcs)) {
510 			mdio_device_free(mdiodev);
511 			continue;
512 		}
513 
514 		priv->hw->xpcs = xpcs;
515 		break;
516 	}
517 
518 	if (!priv->hw->xpcs) {
519 		dev_warn(priv->device, "No xPCS found\n");
520 		return -ENODEV;
521 	}
522 
523 	return 0;
524 }
525 
526 /**
527  * stmmac_mdio_register
528  * @ndev: net device structure
529  * Description: it registers the MII bus
530  */
531 int stmmac_mdio_register(struct net_device *ndev)
532 {
533 	int err = 0;
534 	struct mii_bus *new_bus;
535 	struct stmmac_priv *priv = netdev_priv(ndev);
536 	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
537 	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
538 	struct device_node *mdio_node = priv->plat->mdio_node;
539 	struct device *dev = ndev->dev.parent;
540 	struct fwnode_handle *fixed_node;
541 	int addr, found, max_addr;
542 
543 	if (!mdio_bus_data)
544 		return 0;
545 
546 	new_bus = mdiobus_alloc();
547 	if (!new_bus)
548 		return -ENOMEM;
549 
550 	if (mdio_bus_data->irqs)
551 		memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
552 
553 	new_bus->name = "stmmac";
554 
555 	if (priv->plat->has_xgmac) {
556 		new_bus->read = &stmmac_xgmac2_mdio_read_c22;
557 		new_bus->write = &stmmac_xgmac2_mdio_write_c22;
558 		new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45;
559 		new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45;
560 
561 		/* Right now only C22 phys are supported */
562 		max_addr = MII_XGMAC_MAX_C22ADDR + 1;
563 
564 		/* Check if DT specified an unsupported phy addr */
565 		if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
566 			dev_err(dev, "Unsupported phy_addr (max=%d)\n",
567 					MII_XGMAC_MAX_C22ADDR);
568 	} else {
569 		new_bus->read = &stmmac_mdio_read_c22;
570 		new_bus->write = &stmmac_mdio_write_c22;
571 		if (priv->plat->has_gmac4) {
572 			new_bus->read_c45 = &stmmac_mdio_read_c45;
573 			new_bus->write_c45 = &stmmac_mdio_write_c45;
574 		}
575 
576 		max_addr = PHY_MAX_ADDR;
577 	}
578 
579 	if (mdio_bus_data->needs_reset)
580 		new_bus->reset = &stmmac_mdio_reset;
581 
582 	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
583 		 new_bus->name, priv->plat->bus_id);
584 	new_bus->priv = ndev;
585 	new_bus->phy_mask = mdio_bus_data->phy_mask;
586 	new_bus->parent = priv->device;
587 
588 	err = of_mdiobus_register(new_bus, mdio_node);
589 	if (err != 0) {
590 		dev_err_probe(dev, err, "Cannot register the MDIO bus\n");
591 		goto bus_register_fail;
592 	}
593 
594 	/* Looks like we need a dummy read for XGMAC only and C45 PHYs */
595 	if (priv->plat->has_xgmac)
596 		stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);
597 
598 	/* If fixed-link is set, skip PHY scanning */
599 	if (!fwnode)
600 		fwnode = dev_fwnode(priv->device);
601 
602 	if (fwnode) {
603 		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
604 		if (fixed_node) {
605 			fwnode_handle_put(fixed_node);
606 			goto bus_register_done;
607 		}
608 	}
609 
610 	if (priv->plat->phy_node || mdio_node)
611 		goto bus_register_done;
612 
613 	found = 0;
614 	for (addr = 0; addr < max_addr; addr++) {
615 		struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
616 
617 		if (!phydev)
618 			continue;
619 
620 		/*
621 		 * If an IRQ was provided to be assigned after
622 		 * the bus probe, do it here.
623 		 */
624 		if (!mdio_bus_data->irqs &&
625 		    (mdio_bus_data->probed_phy_irq > 0)) {
626 			new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
627 			phydev->irq = mdio_bus_data->probed_phy_irq;
628 		}
629 
630 		/*
631 		 * If we're going to bind the MAC to this PHY bus,
632 		 * and no PHY number was provided to the MAC,
633 		 * use the one probed here.
634 		 */
635 		if (priv->plat->phy_addr == -1)
636 			priv->plat->phy_addr = addr;
637 
638 		phy_attached_info(phydev);
639 		found = 1;
640 	}
641 
642 	if (!found && !mdio_node) {
643 		dev_warn(dev, "No PHY found\n");
644 		err = -ENODEV;
645 		goto no_phy_found;
646 	}
647 
648 bus_register_done:
649 	priv->mii = new_bus;
650 
651 	return 0;
652 
653 no_phy_found:
654 	mdiobus_unregister(new_bus);
655 bus_register_fail:
656 	mdiobus_free(new_bus);
657 	return err;
658 }
659 
660 /**
661  * stmmac_mdio_unregister
662  * @ndev: net device structure
663  * Description: it unregisters the MII bus
664  */
665 int stmmac_mdio_unregister(struct net_device *ndev)
666 {
667 	struct stmmac_priv *priv = netdev_priv(ndev);
668 
669 	if (!priv->mii)
670 		return 0;
671 
672 	if (priv->hw->xpcs) {
673 		mdio_device_free(priv->hw->xpcs->mdiodev);
674 		xpcs_destroy(priv->hw->xpcs);
675 	}
676 
677 	mdiobus_unregister(priv->mii);
678 	priv->mii->priv = NULL;
679 	mdiobus_free(priv->mii);
680 	priv->mii = NULL;
681 
682 	return 0;
683 }
684