1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #ifdef CONFIG_STMMAC_DEBUG_FS 47 #include <linux/debugfs.h> 48 #include <linux/seq_file.h> 49 #endif /* CONFIG_STMMAC_DEBUG_FS */ 50 #include <linux/net_tstamp.h> 51 #include "stmmac_ptp.h" 52 #include "stmmac.h" 53 54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 55 #define JUMBO_LEN 9000 56 57 /* Module parameters */ 58 #define TX_TIMEO 5000 59 static int watchdog = TX_TIMEO; 60 module_param(watchdog, int, S_IRUGO | S_IWUSR); 61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 62 63 static int debug = -1; 64 module_param(debug, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 66 67 int phyaddr = -1; 68 module_param(phyaddr, int, S_IRUGO); 69 MODULE_PARM_DESC(phyaddr, "Physical device address"); 70 71 #define DMA_TX_SIZE 256 72 static int dma_txsize = DMA_TX_SIZE; 73 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 74 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 75 76 #define DMA_RX_SIZE 256 77 static int dma_rxsize = DMA_RX_SIZE; 78 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 79 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 80 81 static int flow_ctrl = FLOW_OFF; 82 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 83 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 84 85 static int pause = PAUSE_TIME; 86 module_param(pause, int, S_IRUGO | S_IWUSR); 87 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 88 89 #define TC_DEFAULT 64 90 static int tc = TC_DEFAULT; 91 module_param(tc, int, S_IRUGO | S_IWUSR); 92 MODULE_PARM_DESC(tc, "DMA threshold control value"); 93 94 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB 95 static int buf_sz = DMA_BUFFER_SIZE; 96 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 97 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 98 99 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 100 NETIF_MSG_LINK | NETIF_MSG_IFUP | 101 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 102 103 #define STMMAC_DEFAULT_LPI_TIMER 1000 104 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 105 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 106 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 107 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 108 109 /* By default the driver will use the ring mode to manage tx and rx descriptors 110 * but passing this value so user can force to use the chain instead of the ring 111 */ 112 static unsigned int chain_mode; 113 module_param(chain_mode, int, S_IRUGO); 114 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 115 116 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 117 118 #ifdef CONFIG_STMMAC_DEBUG_FS 119 static int stmmac_init_fs(struct net_device *dev); 120 static void stmmac_exit_fs(void); 121 #endif 122 123 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 124 125 /** 126 * stmmac_verify_args - verify the driver parameters. 127 * Description: it verifies if some wrong parameter is passed to the driver. 128 * Note that wrong parameters are replaced with the default values. 129 */ 130 static void stmmac_verify_args(void) 131 { 132 if (unlikely(watchdog < 0)) 133 watchdog = TX_TIMEO; 134 if (unlikely(dma_rxsize < 0)) 135 dma_rxsize = DMA_RX_SIZE; 136 if (unlikely(dma_txsize < 0)) 137 dma_txsize = DMA_TX_SIZE; 138 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 139 buf_sz = DMA_BUFFER_SIZE; 140 if (unlikely(flow_ctrl > 1)) 141 flow_ctrl = FLOW_AUTO; 142 else if (likely(flow_ctrl < 0)) 143 flow_ctrl = FLOW_OFF; 144 if (unlikely((pause < 0) || (pause > 0xffff))) 145 pause = PAUSE_TIME; 146 if (eee_timer < 0) 147 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 148 } 149 150 /** 151 * stmmac_clk_csr_set - dynamically set the MDC clock 152 * @priv: driver private structure 153 * Description: this is to dynamically set the MDC clock according to the csr 154 * clock input. 155 * Note: 156 * If a specific clk_csr value is passed from the platform 157 * this means that the CSR Clock Range selection cannot be 158 * changed at run-time and it is fixed (as reported in the driver 159 * documentation). Viceversa the driver will try to set the MDC 160 * clock dynamically according to the actual clock input. 161 */ 162 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 163 { 164 u32 clk_rate; 165 166 clk_rate = clk_get_rate(priv->stmmac_clk); 167 168 /* Platform provided default clk_csr would be assumed valid 169 * for all other cases except for the below mentioned ones. 170 * For values higher than the IEEE 802.3 specified frequency 171 * we can not estimate the proper divider as it is not known 172 * the frequency of clk_csr_i. So we do not change the default 173 * divider. 174 */ 175 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 176 if (clk_rate < CSR_F_35M) 177 priv->clk_csr = STMMAC_CSR_20_35M; 178 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 179 priv->clk_csr = STMMAC_CSR_35_60M; 180 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 181 priv->clk_csr = STMMAC_CSR_60_100M; 182 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 183 priv->clk_csr = STMMAC_CSR_100_150M; 184 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 185 priv->clk_csr = STMMAC_CSR_150_250M; 186 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 187 priv->clk_csr = STMMAC_CSR_250_300M; 188 } 189 } 190 191 static void print_pkt(unsigned char *buf, int len) 192 { 193 int j; 194 pr_debug("len = %d byte, buf addr: 0x%p", len, buf); 195 for (j = 0; j < len; j++) { 196 if ((j % 16) == 0) 197 pr_debug("\n %03x:", j); 198 pr_debug(" %02x", buf[j]); 199 } 200 pr_debug("\n"); 201 } 202 203 /* minimum number of free TX descriptors required to wake up TX process */ 204 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 205 206 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 207 { 208 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 209 } 210 211 /** 212 * stmmac_hw_fix_mac_speed: callback for speed selection 213 * @priv: driver private structure 214 * Description: on some platforms (e.g. ST), some HW system configuraton 215 * registers have to be set according to the link speed negotiated. 216 */ 217 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 218 { 219 struct phy_device *phydev = priv->phydev; 220 221 if (likely(priv->plat->fix_mac_speed)) 222 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 223 } 224 225 /** 226 * stmmac_enable_eee_mode: Check and enter in LPI mode 227 * @priv: driver private structure 228 * Description: this function is to verify and enter in LPI mode for EEE. 229 */ 230 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 231 { 232 /* Check and enter in LPI mode */ 233 if ((priv->dirty_tx == priv->cur_tx) && 234 (priv->tx_path_in_lpi_mode == false)) 235 priv->hw->mac->set_eee_mode(priv->ioaddr); 236 } 237 238 /** 239 * stmmac_disable_eee_mode: disable/exit from EEE 240 * @priv: driver private structure 241 * Description: this function is to exit and disable EEE in case of 242 * LPI state is true. This is called by the xmit. 243 */ 244 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 245 { 246 priv->hw->mac->reset_eee_mode(priv->ioaddr); 247 del_timer_sync(&priv->eee_ctrl_timer); 248 priv->tx_path_in_lpi_mode = false; 249 } 250 251 /** 252 * stmmac_eee_ctrl_timer: EEE TX SW timer. 253 * @arg : data hook 254 * Description: 255 * if there is no data transfer and if we are not in LPI state, 256 * then MAC Transmitter can be moved to LPI state. 257 */ 258 static void stmmac_eee_ctrl_timer(unsigned long arg) 259 { 260 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 261 262 stmmac_enable_eee_mode(priv); 263 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 264 } 265 266 /** 267 * stmmac_eee_init: init EEE 268 * @priv: driver private structure 269 * Description: 270 * If the EEE support has been enabled while configuring the driver, 271 * if the GMAC actually supports the EEE (from the HW cap reg) and the 272 * phy can also manage EEE, so enable the LPI state and start the timer 273 * to verify if the tx path can enter in LPI state. 274 */ 275 bool stmmac_eee_init(struct stmmac_priv *priv) 276 { 277 bool ret = false; 278 279 /* Using PCS we cannot dial with the phy registers at this stage 280 * so we do not support extra feature like EEE. 281 */ 282 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 283 (priv->pcs == STMMAC_PCS_RTBI)) 284 goto out; 285 286 /* MAC core supports the EEE feature. */ 287 if (priv->dma_cap.eee) { 288 /* Check if the PHY supports EEE */ 289 if (phy_init_eee(priv->phydev, 1)) 290 goto out; 291 292 if (!priv->eee_active) { 293 priv->eee_active = 1; 294 init_timer(&priv->eee_ctrl_timer); 295 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 296 priv->eee_ctrl_timer.data = (unsigned long)priv; 297 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 298 add_timer(&priv->eee_ctrl_timer); 299 300 priv->hw->mac->set_eee_timer(priv->ioaddr, 301 STMMAC_DEFAULT_LIT_LS, 302 priv->tx_lpi_timer); 303 } else 304 /* Set HW EEE according to the speed */ 305 priv->hw->mac->set_eee_pls(priv->ioaddr, 306 priv->phydev->link); 307 308 pr_info("stmmac: Energy-Efficient Ethernet initialized\n"); 309 310 ret = true; 311 } 312 out: 313 return ret; 314 } 315 316 /* stmmac_get_tx_hwtstamp: get HW TX timestamps 317 * @priv: driver private structure 318 * @entry : descriptor index to be used. 319 * @skb : the socket buffer 320 * Description : 321 * This function will read timestamp from the descriptor & pass it to stack. 322 * and also perform some sanity checks. 323 */ 324 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 325 unsigned int entry, struct sk_buff *skb) 326 { 327 struct skb_shared_hwtstamps shhwtstamp; 328 u64 ns; 329 void *desc = NULL; 330 331 if (!priv->hwts_tx_en) 332 return; 333 334 /* exit if skb doesn't support hw tstamp */ 335 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 336 return; 337 338 if (priv->adv_ts) 339 desc = (priv->dma_etx + entry); 340 else 341 desc = (priv->dma_tx + entry); 342 343 /* check tx tstamp status */ 344 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 345 return; 346 347 /* get the valid tstamp */ 348 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 349 350 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 351 shhwtstamp.hwtstamp = ns_to_ktime(ns); 352 /* pass tstamp to stack */ 353 skb_tstamp_tx(skb, &shhwtstamp); 354 355 return; 356 } 357 358 /* stmmac_get_rx_hwtstamp: get HW RX timestamps 359 * @priv: driver private structure 360 * @entry : descriptor index to be used. 361 * @skb : the socket buffer 362 * Description : 363 * This function will read received packet's timestamp from the descriptor 364 * and pass it to stack. It also perform some sanity checks. 365 */ 366 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 367 unsigned int entry, struct sk_buff *skb) 368 { 369 struct skb_shared_hwtstamps *shhwtstamp = NULL; 370 u64 ns; 371 void *desc = NULL; 372 373 if (!priv->hwts_rx_en) 374 return; 375 376 if (priv->adv_ts) 377 desc = (priv->dma_erx + entry); 378 else 379 desc = (priv->dma_rx + entry); 380 381 /* exit if rx tstamp is not valid */ 382 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 383 return; 384 385 /* get valid tstamp */ 386 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 387 shhwtstamp = skb_hwtstamps(skb); 388 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 389 shhwtstamp->hwtstamp = ns_to_ktime(ns); 390 } 391 392 /** 393 * stmmac_hwtstamp_ioctl - control hardware timestamping. 394 * @dev: device pointer. 395 * @ifr: An IOCTL specefic structure, that can contain a pointer to 396 * a proprietary structure used to pass information to the driver. 397 * Description: 398 * This function configures the MAC to enable/disable both outgoing(TX) 399 * and incoming(RX) packets time stamping based on user input. 400 * Return Value: 401 * 0 on success and an appropriate -ve integer on failure. 402 */ 403 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 404 { 405 struct stmmac_priv *priv = netdev_priv(dev); 406 struct hwtstamp_config config; 407 struct timespec now; 408 u64 temp = 0; 409 u32 ptp_v2 = 0; 410 u32 tstamp_all = 0; 411 u32 ptp_over_ipv4_udp = 0; 412 u32 ptp_over_ipv6_udp = 0; 413 u32 ptp_over_ethernet = 0; 414 u32 snap_type_sel = 0; 415 u32 ts_master_en = 0; 416 u32 ts_event_en = 0; 417 u32 value = 0; 418 419 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 420 netdev_alert(priv->dev, "No support for HW time stamping\n"); 421 priv->hwts_tx_en = 0; 422 priv->hwts_rx_en = 0; 423 424 return -EOPNOTSUPP; 425 } 426 427 if (copy_from_user(&config, ifr->ifr_data, 428 sizeof(struct hwtstamp_config))) 429 return -EFAULT; 430 431 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 432 __func__, config.flags, config.tx_type, config.rx_filter); 433 434 /* reserved for future extensions */ 435 if (config.flags) 436 return -EINVAL; 437 438 switch (config.tx_type) { 439 case HWTSTAMP_TX_OFF: 440 priv->hwts_tx_en = 0; 441 break; 442 case HWTSTAMP_TX_ON: 443 priv->hwts_tx_en = 1; 444 break; 445 default: 446 return -ERANGE; 447 } 448 449 if (priv->adv_ts) { 450 switch (config.rx_filter) { 451 case HWTSTAMP_FILTER_NONE: 452 /* time stamp no incoming packet at all */ 453 config.rx_filter = HWTSTAMP_FILTER_NONE; 454 break; 455 456 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 457 /* PTP v1, UDP, any kind of event packet */ 458 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 459 /* take time stamp for all event messages */ 460 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 461 462 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 463 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 464 break; 465 466 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 467 /* PTP v1, UDP, Sync packet */ 468 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 469 /* take time stamp for SYNC messages only */ 470 ts_event_en = PTP_TCR_TSEVNTENA; 471 472 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 473 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 474 break; 475 476 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 477 /* PTP v1, UDP, Delay_req packet */ 478 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 479 /* take time stamp for Delay_Req messages only */ 480 ts_master_en = PTP_TCR_TSMSTRENA; 481 ts_event_en = PTP_TCR_TSEVNTENA; 482 483 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 484 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 485 break; 486 487 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 488 /* PTP v2, UDP, any kind of event packet */ 489 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 490 ptp_v2 = PTP_TCR_TSVER2ENA; 491 /* take time stamp for all event messages */ 492 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 493 494 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 495 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 496 break; 497 498 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 499 /* PTP v2, UDP, Sync packet */ 500 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 501 ptp_v2 = PTP_TCR_TSVER2ENA; 502 /* take time stamp for SYNC messages only */ 503 ts_event_en = PTP_TCR_TSEVNTENA; 504 505 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 506 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 507 break; 508 509 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 510 /* PTP v2, UDP, Delay_req packet */ 511 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 512 ptp_v2 = PTP_TCR_TSVER2ENA; 513 /* take time stamp for Delay_Req messages only */ 514 ts_master_en = PTP_TCR_TSMSTRENA; 515 ts_event_en = PTP_TCR_TSEVNTENA; 516 517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 519 break; 520 521 case HWTSTAMP_FILTER_PTP_V2_EVENT: 522 /* PTP v2/802.AS1 any layer, any kind of event packet */ 523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 524 ptp_v2 = PTP_TCR_TSVER2ENA; 525 /* take time stamp for all event messages */ 526 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 527 528 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 529 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 530 ptp_over_ethernet = PTP_TCR_TSIPENA; 531 break; 532 533 case HWTSTAMP_FILTER_PTP_V2_SYNC: 534 /* PTP v2/802.AS1, any layer, Sync packet */ 535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 536 ptp_v2 = PTP_TCR_TSVER2ENA; 537 /* take time stamp for SYNC messages only */ 538 ts_event_en = PTP_TCR_TSEVNTENA; 539 540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 542 ptp_over_ethernet = PTP_TCR_TSIPENA; 543 break; 544 545 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 546 /* PTP v2/802.AS1, any layer, Delay_req packet */ 547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 548 ptp_v2 = PTP_TCR_TSVER2ENA; 549 /* take time stamp for Delay_Req messages only */ 550 ts_master_en = PTP_TCR_TSMSTRENA; 551 ts_event_en = PTP_TCR_TSEVNTENA; 552 553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 555 ptp_over_ethernet = PTP_TCR_TSIPENA; 556 break; 557 558 case HWTSTAMP_FILTER_ALL: 559 /* time stamp any incoming packet */ 560 config.rx_filter = HWTSTAMP_FILTER_ALL; 561 tstamp_all = PTP_TCR_TSENALL; 562 break; 563 564 default: 565 return -ERANGE; 566 } 567 } else { 568 switch (config.rx_filter) { 569 case HWTSTAMP_FILTER_NONE: 570 config.rx_filter = HWTSTAMP_FILTER_NONE; 571 break; 572 default: 573 /* PTP v1, UDP, any kind of event packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 575 break; 576 } 577 } 578 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 579 580 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 581 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 582 else { 583 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 584 tstamp_all | ptp_v2 | ptp_over_ethernet | 585 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 586 ts_master_en | snap_type_sel); 587 588 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 589 590 /* program Sub Second Increment reg */ 591 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 592 593 /* calculate default added value: 594 * formula is : 595 * addend = (2^32)/freq_div_ratio; 596 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz 597 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK; 598 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to 599 * achive 20ns accuracy. 600 * 601 * 2^x * y == (y << x), hence 602 * 2^32 * 50000000 ==> (50000000 << 32) 603 */ 604 temp = (u64) (50000000ULL << 32); 605 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK); 606 priv->hw->ptp->config_addend(priv->ioaddr, 607 priv->default_addend); 608 609 /* initialize system time */ 610 getnstimeofday(&now); 611 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 612 now.tv_nsec); 613 } 614 615 return copy_to_user(ifr->ifr_data, &config, 616 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 617 } 618 619 /** 620 * stmmac_init_ptp: init PTP 621 * @priv: driver private structure 622 * Description: this is to verify if the HW supports the PTPv1 or v2. 623 * This is done by looking at the HW cap. register. 624 * Also it registers the ptp driver. 625 */ 626 static int stmmac_init_ptp(struct stmmac_priv *priv) 627 { 628 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 629 return -EOPNOTSUPP; 630 631 if (netif_msg_hw(priv)) { 632 if (priv->dma_cap.time_stamp) { 633 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 634 priv->adv_ts = 0; 635 } 636 if (priv->dma_cap.atime_stamp && priv->extend_desc) { 637 pr_debug 638 ("IEEE 1588-2008 Advanced Time Stamp supported\n"); 639 priv->adv_ts = 1; 640 } 641 } 642 643 priv->hw->ptp = &stmmac_ptp; 644 priv->hwts_tx_en = 0; 645 priv->hwts_rx_en = 0; 646 647 return stmmac_ptp_register(priv); 648 } 649 650 static void stmmac_release_ptp(struct stmmac_priv *priv) 651 { 652 stmmac_ptp_unregister(priv); 653 } 654 655 /** 656 * stmmac_adjust_link 657 * @dev: net device structure 658 * Description: it adjusts the link parameters. 659 */ 660 static void stmmac_adjust_link(struct net_device *dev) 661 { 662 struct stmmac_priv *priv = netdev_priv(dev); 663 struct phy_device *phydev = priv->phydev; 664 unsigned long flags; 665 int new_state = 0; 666 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 667 668 if (phydev == NULL) 669 return; 670 671 spin_lock_irqsave(&priv->lock, flags); 672 673 if (phydev->link) { 674 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 675 676 /* Now we make sure that we can be in full duplex mode. 677 * If not, we operate in half-duplex mode. */ 678 if (phydev->duplex != priv->oldduplex) { 679 new_state = 1; 680 if (!(phydev->duplex)) 681 ctrl &= ~priv->hw->link.duplex; 682 else 683 ctrl |= priv->hw->link.duplex; 684 priv->oldduplex = phydev->duplex; 685 } 686 /* Flow Control operation */ 687 if (phydev->pause) 688 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 689 fc, pause_time); 690 691 if (phydev->speed != priv->speed) { 692 new_state = 1; 693 switch (phydev->speed) { 694 case 1000: 695 if (likely(priv->plat->has_gmac)) 696 ctrl &= ~priv->hw->link.port; 697 stmmac_hw_fix_mac_speed(priv); 698 break; 699 case 100: 700 case 10: 701 if (priv->plat->has_gmac) { 702 ctrl |= priv->hw->link.port; 703 if (phydev->speed == SPEED_100) { 704 ctrl |= priv->hw->link.speed; 705 } else { 706 ctrl &= ~(priv->hw->link.speed); 707 } 708 } else { 709 ctrl &= ~priv->hw->link.port; 710 } 711 stmmac_hw_fix_mac_speed(priv); 712 break; 713 default: 714 if (netif_msg_link(priv)) 715 pr_warn("%s: Speed (%d) not 10/100\n", 716 dev->name, phydev->speed); 717 break; 718 } 719 720 priv->speed = phydev->speed; 721 } 722 723 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 724 725 if (!priv->oldlink) { 726 new_state = 1; 727 priv->oldlink = 1; 728 } 729 } else if (priv->oldlink) { 730 new_state = 1; 731 priv->oldlink = 0; 732 priv->speed = 0; 733 priv->oldduplex = -1; 734 } 735 736 if (new_state && netif_msg_link(priv)) 737 phy_print_status(phydev); 738 739 /* At this stage, it could be needed to setup the EEE or adjust some 740 * MAC related HW registers. 741 */ 742 priv->eee_enabled = stmmac_eee_init(priv); 743 744 spin_unlock_irqrestore(&priv->lock, flags); 745 } 746 747 /** 748 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported 749 * @priv: driver private structure 750 * Description: this is to verify if the HW supports the PCS. 751 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 752 * configured for the TBI, RTBI, or SGMII PHY interface. 753 */ 754 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 755 { 756 int interface = priv->plat->interface; 757 758 if (priv->dma_cap.pcs) { 759 if ((interface == PHY_INTERFACE_MODE_RGMII) || 760 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 761 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 762 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 763 pr_debug("STMMAC: PCS RGMII support enable\n"); 764 priv->pcs = STMMAC_PCS_RGMII; 765 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 766 pr_debug("STMMAC: PCS SGMII support enable\n"); 767 priv->pcs = STMMAC_PCS_SGMII; 768 } 769 } 770 } 771 772 /** 773 * stmmac_init_phy - PHY initialization 774 * @dev: net device structure 775 * Description: it initializes the driver's PHY state, and attaches the PHY 776 * to the mac driver. 777 * Return value: 778 * 0 on success 779 */ 780 static int stmmac_init_phy(struct net_device *dev) 781 { 782 struct stmmac_priv *priv = netdev_priv(dev); 783 struct phy_device *phydev; 784 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 785 char bus_id[MII_BUS_ID_SIZE]; 786 int interface = priv->plat->interface; 787 priv->oldlink = 0; 788 priv->speed = 0; 789 priv->oldduplex = -1; 790 791 if (priv->plat->phy_bus_name) 792 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 793 priv->plat->phy_bus_name, priv->plat->bus_id); 794 else 795 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 796 priv->plat->bus_id); 797 798 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 799 priv->plat->phy_addr); 800 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 801 802 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 803 804 if (IS_ERR(phydev)) { 805 pr_err("%s: Could not attach to PHY\n", dev->name); 806 return PTR_ERR(phydev); 807 } 808 809 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 810 if ((interface == PHY_INTERFACE_MODE_MII) || 811 (interface == PHY_INTERFACE_MODE_RMII)) 812 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 813 SUPPORTED_1000baseT_Full); 814 815 /* 816 * Broken HW is sometimes missing the pull-up resistor on the 817 * MDIO line, which results in reads to non-existent devices returning 818 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 819 * device as well. 820 * Note: phydev->phy_id is the result of reading the UID PHY registers. 821 */ 822 if (phydev->phy_id == 0) { 823 phy_disconnect(phydev); 824 return -ENODEV; 825 } 826 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 827 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 828 829 priv->phydev = phydev; 830 831 return 0; 832 } 833 834 /** 835 * stmmac_display_ring: display ring 836 * @head: pointer to the head of the ring passed. 837 * @size: size of the ring. 838 * @extend_desc: to verify if extended descriptors are used. 839 * Description: display the control/status and buffer descriptors. 840 */ 841 static void stmmac_display_ring(void *head, int size, int extend_desc) 842 { 843 int i; 844 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 845 struct dma_desc *p = (struct dma_desc *)head; 846 847 for (i = 0; i < size; i++) { 848 u64 x; 849 if (extend_desc) { 850 x = *(u64 *) ep; 851 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 852 i, (unsigned int)virt_to_phys(ep), 853 (unsigned int)x, (unsigned int)(x >> 32), 854 ep->basic.des2, ep->basic.des3); 855 ep++; 856 } else { 857 x = *(u64 *) p; 858 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 859 i, (unsigned int)virt_to_phys(p), 860 (unsigned int)x, (unsigned int)(x >> 32), 861 p->des2, p->des3); 862 p++; 863 } 864 pr_info("\n"); 865 } 866 } 867 868 static void stmmac_display_rings(struct stmmac_priv *priv) 869 { 870 unsigned int txsize = priv->dma_tx_size; 871 unsigned int rxsize = priv->dma_rx_size; 872 873 if (priv->extend_desc) { 874 pr_info("Extended RX descriptor ring:\n"); 875 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 876 pr_info("Extended TX descriptor ring:\n"); 877 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 878 } else { 879 pr_info("RX descriptor ring:\n"); 880 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 881 pr_info("TX descriptor ring:\n"); 882 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 883 } 884 } 885 886 static int stmmac_set_bfsize(int mtu, int bufsize) 887 { 888 int ret = bufsize; 889 890 if (mtu >= BUF_SIZE_4KiB) 891 ret = BUF_SIZE_8KiB; 892 else if (mtu >= BUF_SIZE_2KiB) 893 ret = BUF_SIZE_4KiB; 894 else if (mtu >= DMA_BUFFER_SIZE) 895 ret = BUF_SIZE_2KiB; 896 else 897 ret = DMA_BUFFER_SIZE; 898 899 return ret; 900 } 901 902 /** 903 * stmmac_clear_descriptors: clear descriptors 904 * @priv: driver private structure 905 * Description: this function is called to clear the tx and rx descriptors 906 * in case of both basic and extended descriptors are used. 907 */ 908 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 909 { 910 int i; 911 unsigned int txsize = priv->dma_tx_size; 912 unsigned int rxsize = priv->dma_rx_size; 913 914 /* Clear the Rx/Tx descriptors */ 915 for (i = 0; i < rxsize; i++) 916 if (priv->extend_desc) 917 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 918 priv->use_riwt, priv->mode, 919 (i == rxsize - 1)); 920 else 921 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 922 priv->use_riwt, priv->mode, 923 (i == rxsize - 1)); 924 for (i = 0; i < txsize; i++) 925 if (priv->extend_desc) 926 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 927 priv->mode, 928 (i == txsize - 1)); 929 else 930 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 931 priv->mode, 932 (i == txsize - 1)); 933 } 934 935 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 936 int i) 937 { 938 struct sk_buff *skb; 939 940 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 941 GFP_KERNEL); 942 if (!skb) { 943 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 944 return -ENOMEM; 945 } 946 skb_reserve(skb, NET_IP_ALIGN); 947 priv->rx_skbuff[i] = skb; 948 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 949 priv->dma_buf_sz, 950 DMA_FROM_DEVICE); 951 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 952 pr_err("%s: DMA mapping error\n", __func__); 953 dev_kfree_skb_any(skb); 954 return -EINVAL; 955 } 956 957 p->des2 = priv->rx_skbuff_dma[i]; 958 959 if ((priv->mode == STMMAC_RING_MODE) && 960 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 961 priv->hw->ring->init_desc3(p); 962 963 return 0; 964 } 965 966 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 967 { 968 if (priv->rx_skbuff[i]) { 969 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 970 priv->dma_buf_sz, DMA_FROM_DEVICE); 971 dev_kfree_skb_any(priv->rx_skbuff[i]); 972 } 973 priv->rx_skbuff[i] = NULL; 974 } 975 976 /** 977 * init_dma_desc_rings - init the RX/TX descriptor rings 978 * @dev: net device structure 979 * Description: this function initializes the DMA RX/TX descriptors 980 * and allocates the socket buffers. It suppors the chained and ring 981 * modes. 982 */ 983 static int init_dma_desc_rings(struct net_device *dev) 984 { 985 int i; 986 struct stmmac_priv *priv = netdev_priv(dev); 987 unsigned int txsize = priv->dma_tx_size; 988 unsigned int rxsize = priv->dma_rx_size; 989 unsigned int bfsize = 0; 990 int ret = -ENOMEM; 991 992 /* Set the max buffer size according to the DESC mode 993 * and the MTU. Note that RING mode allows 16KiB bsize. 994 */ 995 if (priv->mode == STMMAC_RING_MODE) 996 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 997 998 if (bfsize < BUF_SIZE_16KiB) 999 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1000 1001 if (netif_msg_probe(priv)) 1002 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1003 txsize, rxsize, bfsize); 1004 1005 if (priv->extend_desc) { 1006 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1007 sizeof(struct 1008 dma_extended_desc), 1009 &priv->dma_rx_phy, 1010 GFP_KERNEL); 1011 if (!priv->dma_erx) 1012 goto err_dma; 1013 1014 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1015 sizeof(struct 1016 dma_extended_desc), 1017 &priv->dma_tx_phy, 1018 GFP_KERNEL); 1019 if (!priv->dma_etx) { 1020 dma_free_coherent(priv->device, priv->dma_rx_size * 1021 sizeof(struct dma_extended_desc), 1022 priv->dma_erx, priv->dma_rx_phy); 1023 goto err_dma; 1024 } 1025 } else { 1026 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1027 sizeof(struct dma_desc), 1028 &priv->dma_rx_phy, 1029 GFP_KERNEL); 1030 if (!priv->dma_rx) 1031 goto err_dma; 1032 1033 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1034 sizeof(struct dma_desc), 1035 &priv->dma_tx_phy, 1036 GFP_KERNEL); 1037 if (!priv->dma_tx) { 1038 dma_free_coherent(priv->device, priv->dma_rx_size * 1039 sizeof(struct dma_desc), 1040 priv->dma_rx, priv->dma_rx_phy); 1041 goto err_dma; 1042 } 1043 } 1044 1045 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1046 GFP_KERNEL); 1047 if (!priv->rx_skbuff_dma) 1048 goto err_rx_skbuff_dma; 1049 1050 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1051 GFP_KERNEL); 1052 if (!priv->rx_skbuff) 1053 goto err_rx_skbuff; 1054 1055 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t), 1056 GFP_KERNEL); 1057 if (!priv->tx_skbuff_dma) 1058 goto err_tx_skbuff_dma; 1059 1060 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1061 GFP_KERNEL); 1062 if (!priv->tx_skbuff) 1063 goto err_tx_skbuff; 1064 1065 if (netif_msg_probe(priv)) { 1066 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1067 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1068 1069 /* RX INITIALIZATION */ 1070 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1071 } 1072 for (i = 0; i < rxsize; i++) { 1073 struct dma_desc *p; 1074 if (priv->extend_desc) 1075 p = &((priv->dma_erx + i)->basic); 1076 else 1077 p = priv->dma_rx + i; 1078 1079 ret = stmmac_init_rx_buffers(priv, p, i); 1080 if (ret) 1081 goto err_init_rx_buffers; 1082 1083 if (netif_msg_probe(priv)) 1084 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1085 priv->rx_skbuff[i]->data, 1086 (unsigned int)priv->rx_skbuff_dma[i]); 1087 } 1088 priv->cur_rx = 0; 1089 priv->dirty_rx = (unsigned int)(i - rxsize); 1090 priv->dma_buf_sz = bfsize; 1091 buf_sz = bfsize; 1092 1093 /* Setup the chained descriptor addresses */ 1094 if (priv->mode == STMMAC_CHAIN_MODE) { 1095 if (priv->extend_desc) { 1096 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy, 1097 rxsize, 1); 1098 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy, 1099 txsize, 1); 1100 } else { 1101 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy, 1102 rxsize, 0); 1103 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy, 1104 txsize, 0); 1105 } 1106 } 1107 1108 /* TX INITIALIZATION */ 1109 for (i = 0; i < txsize; i++) { 1110 struct dma_desc *p; 1111 if (priv->extend_desc) 1112 p = &((priv->dma_etx + i)->basic); 1113 else 1114 p = priv->dma_tx + i; 1115 p->des2 = 0; 1116 priv->tx_skbuff_dma[i] = 0; 1117 priv->tx_skbuff[i] = NULL; 1118 } 1119 1120 priv->dirty_tx = 0; 1121 priv->cur_tx = 0; 1122 1123 stmmac_clear_descriptors(priv); 1124 1125 if (netif_msg_hw(priv)) 1126 stmmac_display_rings(priv); 1127 1128 return 0; 1129 err_init_rx_buffers: 1130 while (--i >= 0) 1131 stmmac_free_rx_buffers(priv, i); 1132 kfree(priv->tx_skbuff); 1133 err_tx_skbuff: 1134 kfree(priv->tx_skbuff_dma); 1135 err_tx_skbuff_dma: 1136 kfree(priv->rx_skbuff); 1137 err_rx_skbuff: 1138 kfree(priv->rx_skbuff_dma); 1139 err_rx_skbuff_dma: 1140 if (priv->extend_desc) { 1141 dma_free_coherent(priv->device, priv->dma_tx_size * 1142 sizeof(struct dma_extended_desc), 1143 priv->dma_etx, priv->dma_tx_phy); 1144 dma_free_coherent(priv->device, priv->dma_rx_size * 1145 sizeof(struct dma_extended_desc), 1146 priv->dma_erx, priv->dma_rx_phy); 1147 } else { 1148 dma_free_coherent(priv->device, 1149 priv->dma_tx_size * sizeof(struct dma_desc), 1150 priv->dma_tx, priv->dma_tx_phy); 1151 dma_free_coherent(priv->device, 1152 priv->dma_rx_size * sizeof(struct dma_desc), 1153 priv->dma_rx, priv->dma_rx_phy); 1154 } 1155 err_dma: 1156 return ret; 1157 } 1158 1159 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1160 { 1161 int i; 1162 1163 for (i = 0; i < priv->dma_rx_size; i++) 1164 stmmac_free_rx_buffers(priv, i); 1165 } 1166 1167 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1168 { 1169 int i; 1170 1171 for (i = 0; i < priv->dma_tx_size; i++) { 1172 if (priv->tx_skbuff[i] != NULL) { 1173 struct dma_desc *p; 1174 if (priv->extend_desc) 1175 p = &((priv->dma_etx + i)->basic); 1176 else 1177 p = priv->dma_tx + i; 1178 1179 if (priv->tx_skbuff_dma[i]) 1180 dma_unmap_single(priv->device, 1181 priv->tx_skbuff_dma[i], 1182 priv->hw->desc->get_tx_len(p), 1183 DMA_TO_DEVICE); 1184 dev_kfree_skb_any(priv->tx_skbuff[i]); 1185 priv->tx_skbuff[i] = NULL; 1186 priv->tx_skbuff_dma[i] = 0; 1187 } 1188 } 1189 } 1190 1191 static void free_dma_desc_resources(struct stmmac_priv *priv) 1192 { 1193 /* Release the DMA TX/RX socket buffers */ 1194 dma_free_rx_skbufs(priv); 1195 dma_free_tx_skbufs(priv); 1196 1197 /* Free DMA regions of consistent memory previously allocated */ 1198 if (!priv->extend_desc) { 1199 dma_free_coherent(priv->device, 1200 priv->dma_tx_size * sizeof(struct dma_desc), 1201 priv->dma_tx, priv->dma_tx_phy); 1202 dma_free_coherent(priv->device, 1203 priv->dma_rx_size * sizeof(struct dma_desc), 1204 priv->dma_rx, priv->dma_rx_phy); 1205 } else { 1206 dma_free_coherent(priv->device, priv->dma_tx_size * 1207 sizeof(struct dma_extended_desc), 1208 priv->dma_etx, priv->dma_tx_phy); 1209 dma_free_coherent(priv->device, priv->dma_rx_size * 1210 sizeof(struct dma_extended_desc), 1211 priv->dma_erx, priv->dma_rx_phy); 1212 } 1213 kfree(priv->rx_skbuff_dma); 1214 kfree(priv->rx_skbuff); 1215 kfree(priv->tx_skbuff_dma); 1216 kfree(priv->tx_skbuff); 1217 } 1218 1219 /** 1220 * stmmac_dma_operation_mode - HW DMA operation mode 1221 * @priv: driver private structure 1222 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 1223 * or Store-And-Forward capability. 1224 */ 1225 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1226 { 1227 if (priv->plat->force_thresh_dma_mode) 1228 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1229 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1230 /* 1231 * In case of GMAC, SF mode can be enabled 1232 * to perform the TX COE in HW. This depends on: 1233 * 1) TX COE if actually supported 1234 * 2) There is no bugged Jumbo frame support 1235 * that needs to not insert csum in the TDES. 1236 */ 1237 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1238 tc = SF_DMA_MODE; 1239 } else 1240 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1241 } 1242 1243 /** 1244 * stmmac_tx_clean: 1245 * @priv: driver private structure 1246 * Description: it reclaims resources after transmission completes. 1247 */ 1248 static void stmmac_tx_clean(struct stmmac_priv *priv) 1249 { 1250 unsigned int txsize = priv->dma_tx_size; 1251 1252 spin_lock(&priv->tx_lock); 1253 1254 priv->xstats.tx_clean++; 1255 1256 while (priv->dirty_tx != priv->cur_tx) { 1257 int last; 1258 unsigned int entry = priv->dirty_tx % txsize; 1259 struct sk_buff *skb = priv->tx_skbuff[entry]; 1260 struct dma_desc *p; 1261 1262 if (priv->extend_desc) 1263 p = (struct dma_desc *)(priv->dma_etx + entry); 1264 else 1265 p = priv->dma_tx + entry; 1266 1267 /* Check if the descriptor is owned by the DMA. */ 1268 if (priv->hw->desc->get_tx_owner(p)) 1269 break; 1270 1271 /* Verify tx error by looking at the last segment. */ 1272 last = priv->hw->desc->get_tx_ls(p); 1273 if (likely(last)) { 1274 int tx_error = 1275 priv->hw->desc->tx_status(&priv->dev->stats, 1276 &priv->xstats, p, 1277 priv->ioaddr); 1278 if (likely(tx_error == 0)) { 1279 priv->dev->stats.tx_packets++; 1280 priv->xstats.tx_pkt_n++; 1281 } else 1282 priv->dev->stats.tx_errors++; 1283 1284 stmmac_get_tx_hwtstamp(priv, entry, skb); 1285 } 1286 if (netif_msg_tx_done(priv)) 1287 pr_debug("%s: curr %d, dirty %d\n", __func__, 1288 priv->cur_tx, priv->dirty_tx); 1289 1290 if (likely(priv->tx_skbuff_dma[entry])) { 1291 dma_unmap_single(priv->device, 1292 priv->tx_skbuff_dma[entry], 1293 priv->hw->desc->get_tx_len(p), 1294 DMA_TO_DEVICE); 1295 priv->tx_skbuff_dma[entry] = 0; 1296 } 1297 priv->hw->ring->clean_desc3(priv, p); 1298 1299 if (likely(skb != NULL)) { 1300 dev_kfree_skb(skb); 1301 priv->tx_skbuff[entry] = NULL; 1302 } 1303 1304 priv->hw->desc->release_tx_desc(p, priv->mode); 1305 1306 priv->dirty_tx++; 1307 } 1308 if (unlikely(netif_queue_stopped(priv->dev) && 1309 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1310 netif_tx_lock(priv->dev); 1311 if (netif_queue_stopped(priv->dev) && 1312 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1313 if (netif_msg_tx_done(priv)) 1314 pr_debug("%s: restart transmit\n", __func__); 1315 netif_wake_queue(priv->dev); 1316 } 1317 netif_tx_unlock(priv->dev); 1318 } 1319 1320 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1321 stmmac_enable_eee_mode(priv); 1322 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1323 } 1324 spin_unlock(&priv->tx_lock); 1325 } 1326 1327 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1328 { 1329 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1330 } 1331 1332 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1333 { 1334 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1335 } 1336 1337 /** 1338 * stmmac_tx_err: irq tx error mng function 1339 * @priv: driver private structure 1340 * Description: it cleans the descriptors and restarts the transmission 1341 * in case of errors. 1342 */ 1343 static void stmmac_tx_err(struct stmmac_priv *priv) 1344 { 1345 int i; 1346 int txsize = priv->dma_tx_size; 1347 netif_stop_queue(priv->dev); 1348 1349 priv->hw->dma->stop_tx(priv->ioaddr); 1350 dma_free_tx_skbufs(priv); 1351 for (i = 0; i < txsize; i++) 1352 if (priv->extend_desc) 1353 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1354 priv->mode, 1355 (i == txsize - 1)); 1356 else 1357 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1358 priv->mode, 1359 (i == txsize - 1)); 1360 priv->dirty_tx = 0; 1361 priv->cur_tx = 0; 1362 priv->hw->dma->start_tx(priv->ioaddr); 1363 1364 priv->dev->stats.tx_errors++; 1365 netif_wake_queue(priv->dev); 1366 } 1367 1368 /** 1369 * stmmac_dma_interrupt: DMA ISR 1370 * @priv: driver private structure 1371 * Description: this is the DMA ISR. It is called by the main ISR. 1372 * It calls the dwmac dma routine to understand which type of interrupt 1373 * happened. In case of there is a Normal interrupt and either TX or RX 1374 * interrupt happened so the NAPI is scheduled. 1375 */ 1376 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1377 { 1378 int status; 1379 1380 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1381 if (likely((status & handle_rx)) || (status & handle_tx)) { 1382 if (likely(napi_schedule_prep(&priv->napi))) { 1383 stmmac_disable_dma_irq(priv); 1384 __napi_schedule(&priv->napi); 1385 } 1386 } 1387 if (unlikely(status & tx_hard_error_bump_tc)) { 1388 /* Try to bump up the dma threshold on this failure */ 1389 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1390 tc += 64; 1391 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1392 priv->xstats.threshold = tc; 1393 } 1394 } else if (unlikely(status == tx_hard_error)) 1395 stmmac_tx_err(priv); 1396 } 1397 1398 /** 1399 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1400 * @priv: driver private structure 1401 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1402 */ 1403 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1404 { 1405 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1406 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1407 1408 dwmac_mmc_intr_all_mask(priv->ioaddr); 1409 1410 if (priv->dma_cap.rmon) { 1411 dwmac_mmc_ctrl(priv->ioaddr, mode); 1412 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1413 } else 1414 pr_info(" No MAC Management Counters available\n"); 1415 } 1416 1417 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1418 { 1419 u32 hwid = priv->hw->synopsys_uid; 1420 1421 /* Check Synopsys Id (not available on old chips) */ 1422 if (likely(hwid)) { 1423 u32 uid = ((hwid & 0x0000ff00) >> 8); 1424 u32 synid = (hwid & 0x000000ff); 1425 1426 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1427 uid, synid); 1428 1429 return synid; 1430 } 1431 return 0; 1432 } 1433 1434 /** 1435 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors 1436 * @priv: driver private structure 1437 * Description: select the Enhanced/Alternate or Normal descriptors. 1438 * In case of Enhanced/Alternate, it looks at the extended descriptors are 1439 * supported by the HW cap. register. 1440 */ 1441 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1442 { 1443 if (priv->plat->enh_desc) { 1444 pr_info(" Enhanced/Alternate descriptors\n"); 1445 1446 /* GMAC older than 3.50 has no extended descriptors */ 1447 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1448 pr_info("\tEnabled extended descriptors\n"); 1449 priv->extend_desc = 1; 1450 } else 1451 pr_warn("Extended descriptors not supported\n"); 1452 1453 priv->hw->desc = &enh_desc_ops; 1454 } else { 1455 pr_info(" Normal descriptors\n"); 1456 priv->hw->desc = &ndesc_ops; 1457 } 1458 } 1459 1460 /** 1461 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. 1462 * @priv: driver private structure 1463 * Description: 1464 * new GMAC chip generations have a new register to indicate the 1465 * presence of the optional feature/functions. 1466 * This can be also used to override the value passed through the 1467 * platform and necessary for old MAC10/100 and GMAC chips. 1468 */ 1469 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1470 { 1471 u32 hw_cap = 0; 1472 1473 if (priv->hw->dma->get_hw_feature) { 1474 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1475 1476 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1477 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1478 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1479 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1480 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1481 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1482 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1483 priv->dma_cap.pmt_remote_wake_up = 1484 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1485 priv->dma_cap.pmt_magic_frame = 1486 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1487 /* MMC */ 1488 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1489 /* IEEE 1588-2002 */ 1490 priv->dma_cap.time_stamp = 1491 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1492 /* IEEE 1588-2008 */ 1493 priv->dma_cap.atime_stamp = 1494 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1495 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1496 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1497 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1498 /* TX and RX csum */ 1499 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1500 priv->dma_cap.rx_coe_type1 = 1501 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1502 priv->dma_cap.rx_coe_type2 = 1503 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1504 priv->dma_cap.rxfifo_over_2048 = 1505 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1506 /* TX and RX number of channels */ 1507 priv->dma_cap.number_rx_channel = 1508 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1509 priv->dma_cap.number_tx_channel = 1510 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1511 /* Alternate (enhanced) DESC mode */ 1512 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1513 } 1514 1515 return hw_cap; 1516 } 1517 1518 /** 1519 * stmmac_check_ether_addr: check if the MAC addr is valid 1520 * @priv: driver private structure 1521 * Description: 1522 * it is to verify if the MAC address is valid, in case of failures it 1523 * generates a random MAC address 1524 */ 1525 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1526 { 1527 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1528 priv->hw->mac->get_umac_addr((void __iomem *) 1529 priv->dev->base_addr, 1530 priv->dev->dev_addr, 0); 1531 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1532 eth_hw_addr_random(priv->dev); 1533 } 1534 pr_warn("%s: device MAC address %pM\n", priv->dev->name, 1535 priv->dev->dev_addr); 1536 } 1537 1538 /** 1539 * stmmac_init_dma_engine: DMA init. 1540 * @priv: driver private structure 1541 * Description: 1542 * It inits the DMA invoking the specific MAC/GMAC callback. 1543 * Some DMA parameters can be passed from the platform; 1544 * in case of these are not passed a default is kept for the MAC or GMAC. 1545 */ 1546 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1547 { 1548 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1549 int mixed_burst = 0; 1550 int atds = 0; 1551 1552 if (priv->plat->dma_cfg) { 1553 pbl = priv->plat->dma_cfg->pbl; 1554 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1555 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1556 burst_len = priv->plat->dma_cfg->burst_len; 1557 } 1558 1559 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1560 atds = 1; 1561 1562 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1563 burst_len, priv->dma_tx_phy, 1564 priv->dma_rx_phy, atds); 1565 } 1566 1567 /** 1568 * stmmac_tx_timer: mitigation sw timer for tx. 1569 * @data: data pointer 1570 * Description: 1571 * This is the timer handler to directly invoke the stmmac_tx_clean. 1572 */ 1573 static void stmmac_tx_timer(unsigned long data) 1574 { 1575 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1576 1577 stmmac_tx_clean(priv); 1578 } 1579 1580 /** 1581 * stmmac_init_tx_coalesce: init tx mitigation options. 1582 * @priv: driver private structure 1583 * Description: 1584 * This inits the transmit coalesce parameters: i.e. timer rate, 1585 * timer handler and default threshold used for enabling the 1586 * interrupt on completion bit. 1587 */ 1588 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1589 { 1590 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1591 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1592 init_timer(&priv->txtimer); 1593 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1594 priv->txtimer.data = (unsigned long)priv; 1595 priv->txtimer.function = stmmac_tx_timer; 1596 add_timer(&priv->txtimer); 1597 } 1598 1599 /** 1600 * stmmac_open - open entry point of the driver 1601 * @dev : pointer to the device structure. 1602 * Description: 1603 * This function is the open entry point of the driver. 1604 * Return value: 1605 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1606 * file on failure. 1607 */ 1608 static int stmmac_open(struct net_device *dev) 1609 { 1610 struct stmmac_priv *priv = netdev_priv(dev); 1611 int ret; 1612 1613 clk_prepare_enable(priv->stmmac_clk); 1614 1615 stmmac_check_ether_addr(priv); 1616 1617 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1618 priv->pcs != STMMAC_PCS_RTBI) { 1619 ret = stmmac_init_phy(dev); 1620 if (ret) { 1621 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1622 __func__, ret); 1623 goto phy_error; 1624 } 1625 } 1626 1627 /* Create and initialize the TX/RX descriptors chains. */ 1628 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1629 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1630 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1631 1632 ret = init_dma_desc_rings(dev); 1633 if (ret < 0) { 1634 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1635 goto dma_desc_error; 1636 } 1637 1638 /* DMA initialization and SW reset */ 1639 ret = stmmac_init_dma_engine(priv); 1640 if (ret < 0) { 1641 pr_err("%s: DMA engine initialization failed\n", __func__); 1642 goto init_error; 1643 } 1644 1645 /* Copy the MAC addr into the HW */ 1646 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1647 1648 /* If required, perform hw setup of the bus. */ 1649 if (priv->plat->bus_setup) 1650 priv->plat->bus_setup(priv->ioaddr); 1651 1652 /* Initialize the MAC Core */ 1653 priv->hw->mac->core_init(priv->ioaddr); 1654 1655 /* Request the IRQ lines */ 1656 ret = request_irq(dev->irq, stmmac_interrupt, 1657 IRQF_SHARED, dev->name, dev); 1658 if (unlikely(ret < 0)) { 1659 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1660 __func__, dev->irq, ret); 1661 goto init_error; 1662 } 1663 1664 /* Request the Wake IRQ in case of another line is used for WoL */ 1665 if (priv->wol_irq != dev->irq) { 1666 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1667 IRQF_SHARED, dev->name, dev); 1668 if (unlikely(ret < 0)) { 1669 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1670 __func__, priv->wol_irq, ret); 1671 goto wolirq_error; 1672 } 1673 } 1674 1675 /* Request the IRQ lines */ 1676 if (priv->lpi_irq != -ENXIO) { 1677 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1678 dev->name, dev); 1679 if (unlikely(ret < 0)) { 1680 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1681 __func__, priv->lpi_irq, ret); 1682 goto lpiirq_error; 1683 } 1684 } 1685 1686 /* Enable the MAC Rx/Tx */ 1687 stmmac_set_mac(priv->ioaddr, true); 1688 1689 /* Set the HW DMA mode and the COE */ 1690 stmmac_dma_operation_mode(priv); 1691 1692 /* Extra statistics */ 1693 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1694 priv->xstats.threshold = tc; 1695 1696 stmmac_mmc_setup(priv); 1697 1698 ret = stmmac_init_ptp(priv); 1699 if (ret) 1700 pr_warn("%s: failed PTP initialisation\n", __func__); 1701 1702 #ifdef CONFIG_STMMAC_DEBUG_FS 1703 ret = stmmac_init_fs(dev); 1704 if (ret < 0) 1705 pr_warn("%s: failed debugFS registration\n", __func__); 1706 #endif 1707 /* Start the ball rolling... */ 1708 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1709 priv->hw->dma->start_tx(priv->ioaddr); 1710 priv->hw->dma->start_rx(priv->ioaddr); 1711 1712 /* Dump DMA/MAC registers */ 1713 if (netif_msg_hw(priv)) { 1714 priv->hw->mac->dump_regs(priv->ioaddr); 1715 priv->hw->dma->dump_regs(priv->ioaddr); 1716 } 1717 1718 if (priv->phydev) 1719 phy_start(priv->phydev); 1720 1721 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1722 1723 priv->eee_enabled = stmmac_eee_init(priv); 1724 1725 stmmac_init_tx_coalesce(priv); 1726 1727 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1728 priv->rx_riwt = MAX_DMA_RIWT; 1729 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1730 } 1731 1732 if (priv->pcs && priv->hw->mac->ctrl_ane) 1733 priv->hw->mac->ctrl_ane(priv->ioaddr, 0); 1734 1735 napi_enable(&priv->napi); 1736 netif_start_queue(dev); 1737 1738 return 0; 1739 1740 lpiirq_error: 1741 if (priv->wol_irq != dev->irq) 1742 free_irq(priv->wol_irq, dev); 1743 wolirq_error: 1744 free_irq(dev->irq, dev); 1745 1746 init_error: 1747 free_dma_desc_resources(priv); 1748 dma_desc_error: 1749 if (priv->phydev) 1750 phy_disconnect(priv->phydev); 1751 phy_error: 1752 clk_disable_unprepare(priv->stmmac_clk); 1753 1754 return ret; 1755 } 1756 1757 /** 1758 * stmmac_release - close entry point of the driver 1759 * @dev : device pointer. 1760 * Description: 1761 * This is the stop entry point of the driver. 1762 */ 1763 static int stmmac_release(struct net_device *dev) 1764 { 1765 struct stmmac_priv *priv = netdev_priv(dev); 1766 1767 if (priv->eee_enabled) 1768 del_timer_sync(&priv->eee_ctrl_timer); 1769 1770 /* Stop and disconnect the PHY */ 1771 if (priv->phydev) { 1772 phy_stop(priv->phydev); 1773 phy_disconnect(priv->phydev); 1774 priv->phydev = NULL; 1775 } 1776 1777 netif_stop_queue(dev); 1778 1779 napi_disable(&priv->napi); 1780 1781 del_timer_sync(&priv->txtimer); 1782 1783 /* Free the IRQ lines */ 1784 free_irq(dev->irq, dev); 1785 if (priv->wol_irq != dev->irq) 1786 free_irq(priv->wol_irq, dev); 1787 if (priv->lpi_irq != -ENXIO) 1788 free_irq(priv->lpi_irq, dev); 1789 1790 /* Stop TX/RX DMA and clear the descriptors */ 1791 priv->hw->dma->stop_tx(priv->ioaddr); 1792 priv->hw->dma->stop_rx(priv->ioaddr); 1793 1794 /* Release and free the Rx/Tx resources */ 1795 free_dma_desc_resources(priv); 1796 1797 /* Disable the MAC Rx/Tx */ 1798 stmmac_set_mac(priv->ioaddr, false); 1799 1800 netif_carrier_off(dev); 1801 1802 #ifdef CONFIG_STMMAC_DEBUG_FS 1803 stmmac_exit_fs(); 1804 #endif 1805 clk_disable_unprepare(priv->stmmac_clk); 1806 1807 stmmac_release_ptp(priv); 1808 1809 return 0; 1810 } 1811 1812 /** 1813 * stmmac_xmit: Tx entry point of the driver 1814 * @skb : the socket buffer 1815 * @dev : device pointer 1816 * Description : this is the tx entry point of the driver. 1817 * It programs the chain or the ring and supports oversized frames 1818 * and SG feature. 1819 */ 1820 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1821 { 1822 struct stmmac_priv *priv = netdev_priv(dev); 1823 unsigned int txsize = priv->dma_tx_size; 1824 unsigned int entry; 1825 int i, csum_insertion = 0, is_jumbo = 0; 1826 int nfrags = skb_shinfo(skb)->nr_frags; 1827 struct dma_desc *desc, *first; 1828 unsigned int nopaged_len = skb_headlen(skb); 1829 1830 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1831 if (!netif_queue_stopped(dev)) { 1832 netif_stop_queue(dev); 1833 /* This is a hard error, log it. */ 1834 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1835 } 1836 return NETDEV_TX_BUSY; 1837 } 1838 1839 spin_lock(&priv->tx_lock); 1840 1841 if (priv->tx_path_in_lpi_mode) 1842 stmmac_disable_eee_mode(priv); 1843 1844 entry = priv->cur_tx % txsize; 1845 1846 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1847 1848 if (priv->extend_desc) 1849 desc = (struct dma_desc *)(priv->dma_etx + entry); 1850 else 1851 desc = priv->dma_tx + entry; 1852 1853 first = desc; 1854 1855 priv->tx_skbuff[entry] = skb; 1856 1857 /* To program the descriptors according to the size of the frame */ 1858 if (priv->mode == STMMAC_RING_MODE) { 1859 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len, 1860 priv->plat->enh_desc); 1861 if (unlikely(is_jumbo)) 1862 entry = priv->hw->ring->jumbo_frm(priv, skb, 1863 csum_insertion); 1864 } else { 1865 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len, 1866 priv->plat->enh_desc); 1867 if (unlikely(is_jumbo)) 1868 entry = priv->hw->chain->jumbo_frm(priv, skb, 1869 csum_insertion); 1870 } 1871 if (likely(!is_jumbo)) { 1872 desc->des2 = dma_map_single(priv->device, skb->data, 1873 nopaged_len, DMA_TO_DEVICE); 1874 priv->tx_skbuff_dma[entry] = desc->des2; 1875 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1876 csum_insertion, priv->mode); 1877 } else 1878 desc = first; 1879 1880 for (i = 0; i < nfrags; i++) { 1881 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1882 int len = skb_frag_size(frag); 1883 1884 entry = (++priv->cur_tx) % txsize; 1885 if (priv->extend_desc) 1886 desc = (struct dma_desc *)(priv->dma_etx + entry); 1887 else 1888 desc = priv->dma_tx + entry; 1889 1890 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1891 DMA_TO_DEVICE); 1892 priv->tx_skbuff_dma[entry] = desc->des2; 1893 priv->tx_skbuff[entry] = NULL; 1894 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1895 priv->mode); 1896 wmb(); 1897 priv->hw->desc->set_tx_owner(desc); 1898 wmb(); 1899 } 1900 1901 /* Finalize the latest segment. */ 1902 priv->hw->desc->close_tx_desc(desc); 1903 1904 wmb(); 1905 /* According to the coalesce parameter the IC bit for the latest 1906 * segment could be reset and the timer re-started to invoke the 1907 * stmmac_tx function. This approach takes care about the fragments. 1908 */ 1909 priv->tx_count_frames += nfrags + 1; 1910 if (priv->tx_coal_frames > priv->tx_count_frames) { 1911 priv->hw->desc->clear_tx_ic(desc); 1912 priv->xstats.tx_reset_ic_bit++; 1913 mod_timer(&priv->txtimer, 1914 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1915 } else 1916 priv->tx_count_frames = 0; 1917 1918 /* To avoid raise condition */ 1919 priv->hw->desc->set_tx_owner(first); 1920 wmb(); 1921 1922 priv->cur_tx++; 1923 1924 if (netif_msg_pktdata(priv)) { 1925 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 1926 __func__, (priv->cur_tx % txsize), 1927 (priv->dirty_tx % txsize), entry, first, nfrags); 1928 1929 if (priv->extend_desc) 1930 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 1931 else 1932 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 1933 1934 pr_debug(">>> frame to be transmitted: "); 1935 print_pkt(skb->data, skb->len); 1936 } 1937 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1938 if (netif_msg_hw(priv)) 1939 pr_debug("%s: stop transmitted packets\n", __func__); 1940 netif_stop_queue(dev); 1941 } 1942 1943 dev->stats.tx_bytes += skb->len; 1944 1945 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1946 priv->hwts_tx_en)) { 1947 /* declare that device is doing timestamping */ 1948 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1949 priv->hw->desc->enable_tx_timestamp(first); 1950 } 1951 1952 if (!priv->hwts_tx_en) 1953 skb_tx_timestamp(skb); 1954 1955 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1956 1957 spin_unlock(&priv->tx_lock); 1958 1959 return NETDEV_TX_OK; 1960 } 1961 1962 /** 1963 * stmmac_rx_refill: refill used skb preallocated buffers 1964 * @priv: driver private structure 1965 * Description : this is to reallocate the skb for the reception process 1966 * that is based on zero-copy. 1967 */ 1968 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 1969 { 1970 unsigned int rxsize = priv->dma_rx_size; 1971 int bfsize = priv->dma_buf_sz; 1972 1973 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 1974 unsigned int entry = priv->dirty_rx % rxsize; 1975 struct dma_desc *p; 1976 1977 if (priv->extend_desc) 1978 p = (struct dma_desc *)(priv->dma_erx + entry); 1979 else 1980 p = priv->dma_rx + entry; 1981 1982 if (likely(priv->rx_skbuff[entry] == NULL)) { 1983 struct sk_buff *skb; 1984 1985 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 1986 1987 if (unlikely(skb == NULL)) 1988 break; 1989 1990 priv->rx_skbuff[entry] = skb; 1991 priv->rx_skbuff_dma[entry] = 1992 dma_map_single(priv->device, skb->data, bfsize, 1993 DMA_FROM_DEVICE); 1994 1995 p->des2 = priv->rx_skbuff_dma[entry]; 1996 1997 priv->hw->ring->refill_desc3(priv, p); 1998 1999 if (netif_msg_rx_status(priv)) 2000 pr_debug("\trefill entry #%d\n", entry); 2001 } 2002 wmb(); 2003 priv->hw->desc->set_rx_owner(p); 2004 wmb(); 2005 } 2006 } 2007 2008 /** 2009 * stmmac_rx_refill: refill used skb preallocated buffers 2010 * @priv: driver private structure 2011 * @limit: napi bugget. 2012 * Description : this the function called by the napi poll method. 2013 * It gets all the frames inside the ring. 2014 */ 2015 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2016 { 2017 unsigned int rxsize = priv->dma_rx_size; 2018 unsigned int entry = priv->cur_rx % rxsize; 2019 unsigned int next_entry; 2020 unsigned int count = 0; 2021 int coe = priv->plat->rx_coe; 2022 2023 if (netif_msg_rx_status(priv)) { 2024 pr_debug("%s: descriptor ring:\n", __func__); 2025 if (priv->extend_desc) 2026 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2027 else 2028 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2029 } 2030 while (count < limit) { 2031 int status; 2032 struct dma_desc *p; 2033 2034 if (priv->extend_desc) 2035 p = (struct dma_desc *)(priv->dma_erx + entry); 2036 else 2037 p = priv->dma_rx + entry; 2038 2039 if (priv->hw->desc->get_rx_owner(p)) 2040 break; 2041 2042 count++; 2043 2044 next_entry = (++priv->cur_rx) % rxsize; 2045 if (priv->extend_desc) 2046 prefetch(priv->dma_erx + next_entry); 2047 else 2048 prefetch(priv->dma_rx + next_entry); 2049 2050 /* read the status of the incoming frame */ 2051 status = priv->hw->desc->rx_status(&priv->dev->stats, 2052 &priv->xstats, p); 2053 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2054 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2055 &priv->xstats, 2056 priv->dma_erx + 2057 entry); 2058 if (unlikely(status == discard_frame)) { 2059 priv->dev->stats.rx_errors++; 2060 if (priv->hwts_rx_en && !priv->extend_desc) { 2061 /* DESC2 & DESC3 will be overwitten by device 2062 * with timestamp value, hence reinitialize 2063 * them in stmmac_rx_refill() function so that 2064 * device can reuse it. 2065 */ 2066 priv->rx_skbuff[entry] = NULL; 2067 dma_unmap_single(priv->device, 2068 priv->rx_skbuff_dma[entry], 2069 priv->dma_buf_sz, 2070 DMA_FROM_DEVICE); 2071 } 2072 } else { 2073 struct sk_buff *skb; 2074 int frame_len; 2075 2076 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2077 2078 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2079 * Type frames (LLC/LLC-SNAP) 2080 */ 2081 if (unlikely(status != llc_snap)) 2082 frame_len -= ETH_FCS_LEN; 2083 2084 if (netif_msg_rx_status(priv)) { 2085 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2086 p, entry, p->des2); 2087 if (frame_len > ETH_FRAME_LEN) 2088 pr_debug("\tframe size %d, COE: %d\n", 2089 frame_len, status); 2090 } 2091 skb = priv->rx_skbuff[entry]; 2092 if (unlikely(!skb)) { 2093 pr_err("%s: Inconsistent Rx descriptor chain\n", 2094 priv->dev->name); 2095 priv->dev->stats.rx_dropped++; 2096 break; 2097 } 2098 prefetch(skb->data - NET_IP_ALIGN); 2099 priv->rx_skbuff[entry] = NULL; 2100 2101 stmmac_get_rx_hwtstamp(priv, entry, skb); 2102 2103 skb_put(skb, frame_len); 2104 dma_unmap_single(priv->device, 2105 priv->rx_skbuff_dma[entry], 2106 priv->dma_buf_sz, DMA_FROM_DEVICE); 2107 2108 if (netif_msg_pktdata(priv)) { 2109 pr_debug("frame received (%dbytes)", frame_len); 2110 print_pkt(skb->data, frame_len); 2111 } 2112 2113 skb->protocol = eth_type_trans(skb, priv->dev); 2114 2115 if (unlikely(!coe)) 2116 skb_checksum_none_assert(skb); 2117 else 2118 skb->ip_summed = CHECKSUM_UNNECESSARY; 2119 2120 napi_gro_receive(&priv->napi, skb); 2121 2122 priv->dev->stats.rx_packets++; 2123 priv->dev->stats.rx_bytes += frame_len; 2124 } 2125 entry = next_entry; 2126 } 2127 2128 stmmac_rx_refill(priv); 2129 2130 priv->xstats.rx_pkt_n += count; 2131 2132 return count; 2133 } 2134 2135 /** 2136 * stmmac_poll - stmmac poll method (NAPI) 2137 * @napi : pointer to the napi structure. 2138 * @budget : maximum number of packets that the current CPU can receive from 2139 * all interfaces. 2140 * Description : 2141 * To look at the incoming frames and clear the tx resources. 2142 */ 2143 static int stmmac_poll(struct napi_struct *napi, int budget) 2144 { 2145 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2146 int work_done = 0; 2147 2148 priv->xstats.napi_poll++; 2149 stmmac_tx_clean(priv); 2150 2151 work_done = stmmac_rx(priv, budget); 2152 if (work_done < budget) { 2153 napi_complete(napi); 2154 stmmac_enable_dma_irq(priv); 2155 } 2156 return work_done; 2157 } 2158 2159 /** 2160 * stmmac_tx_timeout 2161 * @dev : Pointer to net device structure 2162 * Description: this function is called when a packet transmission fails to 2163 * complete within a reasonable time. The driver will mark the error in the 2164 * netdev structure and arrange for the device to be reset to a sane state 2165 * in order to transmit a new packet. 2166 */ 2167 static void stmmac_tx_timeout(struct net_device *dev) 2168 { 2169 struct stmmac_priv *priv = netdev_priv(dev); 2170 2171 /* Clear Tx resources and restart transmitting again */ 2172 stmmac_tx_err(priv); 2173 } 2174 2175 /* Configuration changes (passed on by ifconfig) */ 2176 static int stmmac_config(struct net_device *dev, struct ifmap *map) 2177 { 2178 if (dev->flags & IFF_UP) /* can't act on a running interface */ 2179 return -EBUSY; 2180 2181 /* Don't allow changing the I/O address */ 2182 if (map->base_addr != dev->base_addr) { 2183 pr_warn("%s: can't change I/O address\n", dev->name); 2184 return -EOPNOTSUPP; 2185 } 2186 2187 /* Don't allow changing the IRQ */ 2188 if (map->irq != dev->irq) { 2189 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq); 2190 return -EOPNOTSUPP; 2191 } 2192 2193 return 0; 2194 } 2195 2196 /** 2197 * stmmac_set_rx_mode - entry point for multicast addressing 2198 * @dev : pointer to the device structure 2199 * Description: 2200 * This function is a driver entry point which gets called by the kernel 2201 * whenever multicast addresses must be enabled/disabled. 2202 * Return value: 2203 * void. 2204 */ 2205 static void stmmac_set_rx_mode(struct net_device *dev) 2206 { 2207 struct stmmac_priv *priv = netdev_priv(dev); 2208 2209 spin_lock(&priv->lock); 2210 priv->hw->mac->set_filter(dev, priv->synopsys_id); 2211 spin_unlock(&priv->lock); 2212 } 2213 2214 /** 2215 * stmmac_change_mtu - entry point to change MTU size for the device. 2216 * @dev : device pointer. 2217 * @new_mtu : the new MTU size for the device. 2218 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2219 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2220 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2221 * Return value: 2222 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2223 * file on failure. 2224 */ 2225 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2226 { 2227 struct stmmac_priv *priv = netdev_priv(dev); 2228 int max_mtu; 2229 2230 if (netif_running(dev)) { 2231 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2232 return -EBUSY; 2233 } 2234 2235 if (priv->plat->enh_desc) 2236 max_mtu = JUMBO_LEN; 2237 else 2238 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2239 2240 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2241 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2242 return -EINVAL; 2243 } 2244 2245 dev->mtu = new_mtu; 2246 netdev_update_features(dev); 2247 2248 return 0; 2249 } 2250 2251 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2252 netdev_features_t features) 2253 { 2254 struct stmmac_priv *priv = netdev_priv(dev); 2255 2256 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2257 features &= ~NETIF_F_RXCSUM; 2258 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 2259 features &= ~NETIF_F_IPV6_CSUM; 2260 if (!priv->plat->tx_coe) 2261 features &= ~NETIF_F_ALL_CSUM; 2262 2263 /* Some GMAC devices have a bugged Jumbo frame support that 2264 * needs to have the Tx COE disabled for oversized frames 2265 * (due to limited buffer sizes). In this case we disable 2266 * the TX csum insertionin the TDES and not use SF. 2267 */ 2268 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2269 features &= ~NETIF_F_ALL_CSUM; 2270 2271 return features; 2272 } 2273 2274 /** 2275 * stmmac_interrupt - main ISR 2276 * @irq: interrupt number. 2277 * @dev_id: to pass the net device pointer. 2278 * Description: this is the main driver interrupt service routine. 2279 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 2280 * interrupts. 2281 */ 2282 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2283 { 2284 struct net_device *dev = (struct net_device *)dev_id; 2285 struct stmmac_priv *priv = netdev_priv(dev); 2286 2287 if (unlikely(!dev)) { 2288 pr_err("%s: invalid dev pointer\n", __func__); 2289 return IRQ_NONE; 2290 } 2291 2292 /* To handle GMAC own interrupts */ 2293 if (priv->plat->has_gmac) { 2294 int status = priv->hw->mac->host_irq_status((void __iomem *) 2295 dev->base_addr, 2296 &priv->xstats); 2297 if (unlikely(status)) { 2298 /* For LPI we need to save the tx status */ 2299 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2300 priv->tx_path_in_lpi_mode = true; 2301 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2302 priv->tx_path_in_lpi_mode = false; 2303 } 2304 } 2305 2306 /* To handle DMA interrupts */ 2307 stmmac_dma_interrupt(priv); 2308 2309 return IRQ_HANDLED; 2310 } 2311 2312 #ifdef CONFIG_NET_POLL_CONTROLLER 2313 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2314 * to allow network I/O with interrupts disabled. 2315 */ 2316 static void stmmac_poll_controller(struct net_device *dev) 2317 { 2318 disable_irq(dev->irq); 2319 stmmac_interrupt(dev->irq, dev); 2320 enable_irq(dev->irq); 2321 } 2322 #endif 2323 2324 /** 2325 * stmmac_ioctl - Entry point for the Ioctl 2326 * @dev: Device pointer. 2327 * @rq: An IOCTL specefic structure, that can contain a pointer to 2328 * a proprietary structure used to pass information to the driver. 2329 * @cmd: IOCTL command 2330 * Description: 2331 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2332 */ 2333 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2334 { 2335 struct stmmac_priv *priv = netdev_priv(dev); 2336 int ret = -EOPNOTSUPP; 2337 2338 if (!netif_running(dev)) 2339 return -EINVAL; 2340 2341 switch (cmd) { 2342 case SIOCGMIIPHY: 2343 case SIOCGMIIREG: 2344 case SIOCSMIIREG: 2345 if (!priv->phydev) 2346 return -EINVAL; 2347 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2348 break; 2349 case SIOCSHWTSTAMP: 2350 ret = stmmac_hwtstamp_ioctl(dev, rq); 2351 break; 2352 default: 2353 break; 2354 } 2355 2356 return ret; 2357 } 2358 2359 #ifdef CONFIG_STMMAC_DEBUG_FS 2360 static struct dentry *stmmac_fs_dir; 2361 static struct dentry *stmmac_rings_status; 2362 static struct dentry *stmmac_dma_cap; 2363 2364 static void sysfs_display_ring(void *head, int size, int extend_desc, 2365 struct seq_file *seq) 2366 { 2367 int i; 2368 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2369 struct dma_desc *p = (struct dma_desc *)head; 2370 2371 for (i = 0; i < size; i++) { 2372 u64 x; 2373 if (extend_desc) { 2374 x = *(u64 *) ep; 2375 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2376 i, (unsigned int)virt_to_phys(ep), 2377 (unsigned int)x, (unsigned int)(x >> 32), 2378 ep->basic.des2, ep->basic.des3); 2379 ep++; 2380 } else { 2381 x = *(u64 *) p; 2382 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2383 i, (unsigned int)virt_to_phys(ep), 2384 (unsigned int)x, (unsigned int)(x >> 32), 2385 p->des2, p->des3); 2386 p++; 2387 } 2388 seq_printf(seq, "\n"); 2389 } 2390 } 2391 2392 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2393 { 2394 struct net_device *dev = seq->private; 2395 struct stmmac_priv *priv = netdev_priv(dev); 2396 unsigned int txsize = priv->dma_tx_size; 2397 unsigned int rxsize = priv->dma_rx_size; 2398 2399 if (priv->extend_desc) { 2400 seq_printf(seq, "Extended RX descriptor ring:\n"); 2401 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2402 seq_printf(seq, "Extended TX descriptor ring:\n"); 2403 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2404 } else { 2405 seq_printf(seq, "RX descriptor ring:\n"); 2406 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2407 seq_printf(seq, "TX descriptor ring:\n"); 2408 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2409 } 2410 2411 return 0; 2412 } 2413 2414 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2415 { 2416 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2417 } 2418 2419 static const struct file_operations stmmac_rings_status_fops = { 2420 .owner = THIS_MODULE, 2421 .open = stmmac_sysfs_ring_open, 2422 .read = seq_read, 2423 .llseek = seq_lseek, 2424 .release = single_release, 2425 }; 2426 2427 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2428 { 2429 struct net_device *dev = seq->private; 2430 struct stmmac_priv *priv = netdev_priv(dev); 2431 2432 if (!priv->hw_cap_support) { 2433 seq_printf(seq, "DMA HW features not supported\n"); 2434 return 0; 2435 } 2436 2437 seq_printf(seq, "==============================\n"); 2438 seq_printf(seq, "\tDMA HW features\n"); 2439 seq_printf(seq, "==============================\n"); 2440 2441 seq_printf(seq, "\t10/100 Mbps %s\n", 2442 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2443 seq_printf(seq, "\t1000 Mbps %s\n", 2444 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2445 seq_printf(seq, "\tHalf duple %s\n", 2446 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2447 seq_printf(seq, "\tHash Filter: %s\n", 2448 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2449 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2450 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2451 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2452 (priv->dma_cap.pcs) ? "Y" : "N"); 2453 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2454 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2455 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2456 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2457 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2458 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2459 seq_printf(seq, "\tRMON module: %s\n", 2460 (priv->dma_cap.rmon) ? "Y" : "N"); 2461 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2462 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2463 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2464 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2465 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2466 (priv->dma_cap.eee) ? "Y" : "N"); 2467 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2468 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2469 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2470 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2471 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2472 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2473 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2474 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2475 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2476 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2477 priv->dma_cap.number_rx_channel); 2478 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2479 priv->dma_cap.number_tx_channel); 2480 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2481 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2482 2483 return 0; 2484 } 2485 2486 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2487 { 2488 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2489 } 2490 2491 static const struct file_operations stmmac_dma_cap_fops = { 2492 .owner = THIS_MODULE, 2493 .open = stmmac_sysfs_dma_cap_open, 2494 .read = seq_read, 2495 .llseek = seq_lseek, 2496 .release = single_release, 2497 }; 2498 2499 static int stmmac_init_fs(struct net_device *dev) 2500 { 2501 /* Create debugfs entries */ 2502 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2503 2504 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2505 pr_err("ERROR %s, debugfs create directory failed\n", 2506 STMMAC_RESOURCE_NAME); 2507 2508 return -ENOMEM; 2509 } 2510 2511 /* Entry to report DMA RX/TX rings */ 2512 stmmac_rings_status = debugfs_create_file("descriptors_status", 2513 S_IRUGO, stmmac_fs_dir, dev, 2514 &stmmac_rings_status_fops); 2515 2516 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2517 pr_info("ERROR creating stmmac ring debugfs file\n"); 2518 debugfs_remove(stmmac_fs_dir); 2519 2520 return -ENOMEM; 2521 } 2522 2523 /* Entry to report the DMA HW features */ 2524 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2525 dev, &stmmac_dma_cap_fops); 2526 2527 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2528 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2529 debugfs_remove(stmmac_rings_status); 2530 debugfs_remove(stmmac_fs_dir); 2531 2532 return -ENOMEM; 2533 } 2534 2535 return 0; 2536 } 2537 2538 static void stmmac_exit_fs(void) 2539 { 2540 debugfs_remove(stmmac_rings_status); 2541 debugfs_remove(stmmac_dma_cap); 2542 debugfs_remove(stmmac_fs_dir); 2543 } 2544 #endif /* CONFIG_STMMAC_DEBUG_FS */ 2545 2546 static const struct net_device_ops stmmac_netdev_ops = { 2547 .ndo_open = stmmac_open, 2548 .ndo_start_xmit = stmmac_xmit, 2549 .ndo_stop = stmmac_release, 2550 .ndo_change_mtu = stmmac_change_mtu, 2551 .ndo_fix_features = stmmac_fix_features, 2552 .ndo_set_rx_mode = stmmac_set_rx_mode, 2553 .ndo_tx_timeout = stmmac_tx_timeout, 2554 .ndo_do_ioctl = stmmac_ioctl, 2555 .ndo_set_config = stmmac_config, 2556 #ifdef CONFIG_NET_POLL_CONTROLLER 2557 .ndo_poll_controller = stmmac_poll_controller, 2558 #endif 2559 .ndo_set_mac_address = eth_mac_addr, 2560 }; 2561 2562 /** 2563 * stmmac_hw_init - Init the MAC device 2564 * @priv: driver private structure 2565 * Description: this function detects which MAC device 2566 * (GMAC/MAC10-100) has to attached, checks the HW capability 2567 * (if supported) and sets the driver's features (for example 2568 * to use the ring or chaine mode or support the normal/enh 2569 * descriptor structure). 2570 */ 2571 static int stmmac_hw_init(struct stmmac_priv *priv) 2572 { 2573 int ret; 2574 struct mac_device_info *mac; 2575 2576 /* Identify the MAC HW device */ 2577 if (priv->plat->has_gmac) { 2578 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2579 mac = dwmac1000_setup(priv->ioaddr); 2580 } else { 2581 mac = dwmac100_setup(priv->ioaddr); 2582 } 2583 if (!mac) 2584 return -ENOMEM; 2585 2586 priv->hw = mac; 2587 2588 /* Get and dump the chip ID */ 2589 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2590 2591 /* To use the chained or ring mode */ 2592 if (chain_mode) { 2593 priv->hw->chain = &chain_mode_ops; 2594 pr_info(" Chain mode enabled\n"); 2595 priv->mode = STMMAC_CHAIN_MODE; 2596 } else { 2597 priv->hw->ring = &ring_mode_ops; 2598 pr_info(" Ring mode enabled\n"); 2599 priv->mode = STMMAC_RING_MODE; 2600 } 2601 2602 /* Get the HW capability (new GMAC newer than 3.50a) */ 2603 priv->hw_cap_support = stmmac_get_hw_features(priv); 2604 if (priv->hw_cap_support) { 2605 pr_info(" DMA HW capability register supported"); 2606 2607 /* We can override some gmac/dma configuration fields: e.g. 2608 * enh_desc, tx_coe (e.g. that are passed through the 2609 * platform) with the values from the HW capability 2610 * register (if supported). 2611 */ 2612 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2613 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2614 2615 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2616 2617 if (priv->dma_cap.rx_coe_type2) 2618 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2619 else if (priv->dma_cap.rx_coe_type1) 2620 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2621 2622 } else 2623 pr_info(" No HW DMA feature register supported"); 2624 2625 /* To use alternate (extended) or normal descriptor structures */ 2626 stmmac_selec_desc_mode(priv); 2627 2628 ret = priv->hw->mac->rx_ipc(priv->ioaddr); 2629 if (!ret) { 2630 pr_warn(" RX IPC Checksum Offload not configured.\n"); 2631 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2632 } 2633 2634 if (priv->plat->rx_coe) 2635 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2636 priv->plat->rx_coe); 2637 if (priv->plat->tx_coe) 2638 pr_info(" TX Checksum insertion supported\n"); 2639 2640 if (priv->plat->pmt) { 2641 pr_info(" Wake-Up On Lan supported\n"); 2642 device_set_wakeup_capable(priv->device, 1); 2643 } 2644 2645 return 0; 2646 } 2647 2648 /** 2649 * stmmac_dvr_probe 2650 * @device: device pointer 2651 * @plat_dat: platform data pointer 2652 * @addr: iobase memory address 2653 * Description: this is the main probe function used to 2654 * call the alloc_etherdev, allocate the priv structure. 2655 */ 2656 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2657 struct plat_stmmacenet_data *plat_dat, 2658 void __iomem *addr) 2659 { 2660 int ret = 0; 2661 struct net_device *ndev = NULL; 2662 struct stmmac_priv *priv; 2663 2664 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2665 if (!ndev) 2666 return NULL; 2667 2668 SET_NETDEV_DEV(ndev, device); 2669 2670 priv = netdev_priv(ndev); 2671 priv->device = device; 2672 priv->dev = ndev; 2673 2674 ether_setup(ndev); 2675 2676 stmmac_set_ethtool_ops(ndev); 2677 priv->pause = pause; 2678 priv->plat = plat_dat; 2679 priv->ioaddr = addr; 2680 priv->dev->base_addr = (unsigned long)addr; 2681 2682 /* Verify driver arguments */ 2683 stmmac_verify_args(); 2684 2685 /* Override with kernel parameters if supplied XXX CRS XXX 2686 * this needs to have multiple instances 2687 */ 2688 if ((phyaddr >= 0) && (phyaddr <= 31)) 2689 priv->plat->phy_addr = phyaddr; 2690 2691 /* Init MAC and get the capabilities */ 2692 ret = stmmac_hw_init(priv); 2693 if (ret) 2694 goto error_free_netdev; 2695 2696 ndev->netdev_ops = &stmmac_netdev_ops; 2697 2698 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2699 NETIF_F_RXCSUM; 2700 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2701 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2702 #ifdef STMMAC_VLAN_TAG_USED 2703 /* Both mac100 and gmac support receive VLAN tag detection */ 2704 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2705 #endif 2706 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2707 2708 if (flow_ctrl) 2709 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2710 2711 /* Rx Watchdog is available in the COREs newer than the 3.40. 2712 * In some case, for example on bugged HW this feature 2713 * has to be disable and this can be done by passing the 2714 * riwt_off field from the platform. 2715 */ 2716 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2717 priv->use_riwt = 1; 2718 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2719 } 2720 2721 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2722 2723 spin_lock_init(&priv->lock); 2724 spin_lock_init(&priv->tx_lock); 2725 2726 ret = register_netdev(ndev); 2727 if (ret) { 2728 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2729 goto error_netdev_register; 2730 } 2731 2732 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME); 2733 if (IS_ERR(priv->stmmac_clk)) { 2734 pr_warn("%s: warning: cannot get CSR clock\n", __func__); 2735 goto error_clk_get; 2736 } 2737 2738 /* If a specific clk_csr value is passed from the platform 2739 * this means that the CSR Clock Range selection cannot be 2740 * changed at run-time and it is fixed. Viceversa the driver'll try to 2741 * set the MDC clock dynamically according to the csr actual 2742 * clock input. 2743 */ 2744 if (!priv->plat->clk_csr) 2745 stmmac_clk_csr_set(priv); 2746 else 2747 priv->clk_csr = priv->plat->clk_csr; 2748 2749 stmmac_check_pcs_mode(priv); 2750 2751 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2752 priv->pcs != STMMAC_PCS_RTBI) { 2753 /* MDIO bus Registration */ 2754 ret = stmmac_mdio_register(ndev); 2755 if (ret < 0) { 2756 pr_debug("%s: MDIO bus (id: %d) registration failed", 2757 __func__, priv->plat->bus_id); 2758 goto error_mdio_register; 2759 } 2760 } 2761 2762 return priv; 2763 2764 error_mdio_register: 2765 clk_put(priv->stmmac_clk); 2766 error_clk_get: 2767 unregister_netdev(ndev); 2768 error_netdev_register: 2769 netif_napi_del(&priv->napi); 2770 error_free_netdev: 2771 free_netdev(ndev); 2772 2773 return NULL; 2774 } 2775 2776 /** 2777 * stmmac_dvr_remove 2778 * @ndev: net device pointer 2779 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2780 * changes the link status, releases the DMA descriptor rings. 2781 */ 2782 int stmmac_dvr_remove(struct net_device *ndev) 2783 { 2784 struct stmmac_priv *priv = netdev_priv(ndev); 2785 2786 pr_info("%s:\n\tremoving driver", __func__); 2787 2788 priv->hw->dma->stop_rx(priv->ioaddr); 2789 priv->hw->dma->stop_tx(priv->ioaddr); 2790 2791 stmmac_set_mac(priv->ioaddr, false); 2792 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2793 priv->pcs != STMMAC_PCS_RTBI) 2794 stmmac_mdio_unregister(ndev); 2795 netif_carrier_off(ndev); 2796 unregister_netdev(ndev); 2797 free_netdev(ndev); 2798 2799 return 0; 2800 } 2801 2802 #ifdef CONFIG_PM 2803 int stmmac_suspend(struct net_device *ndev) 2804 { 2805 struct stmmac_priv *priv = netdev_priv(ndev); 2806 unsigned long flags; 2807 2808 if (!ndev || !netif_running(ndev)) 2809 return 0; 2810 2811 if (priv->phydev) 2812 phy_stop(priv->phydev); 2813 2814 spin_lock_irqsave(&priv->lock, flags); 2815 2816 netif_device_detach(ndev); 2817 netif_stop_queue(ndev); 2818 2819 napi_disable(&priv->napi); 2820 2821 /* Stop TX/RX DMA */ 2822 priv->hw->dma->stop_tx(priv->ioaddr); 2823 priv->hw->dma->stop_rx(priv->ioaddr); 2824 2825 stmmac_clear_descriptors(priv); 2826 2827 /* Enable Power down mode by programming the PMT regs */ 2828 if (device_may_wakeup(priv->device)) 2829 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 2830 else { 2831 stmmac_set_mac(priv->ioaddr, false); 2832 /* Disable clock in case of PWM is off */ 2833 clk_disable_unprepare(priv->stmmac_clk); 2834 } 2835 spin_unlock_irqrestore(&priv->lock, flags); 2836 return 0; 2837 } 2838 2839 int stmmac_resume(struct net_device *ndev) 2840 { 2841 struct stmmac_priv *priv = netdev_priv(ndev); 2842 unsigned long flags; 2843 2844 if (!netif_running(ndev)) 2845 return 0; 2846 2847 spin_lock_irqsave(&priv->lock, flags); 2848 2849 /* Power Down bit, into the PM register, is cleared 2850 * automatically as soon as a magic packet or a Wake-up frame 2851 * is received. Anyway, it's better to manually clear 2852 * this bit because it can generate problems while resuming 2853 * from another devices (e.g. serial console). 2854 */ 2855 if (device_may_wakeup(priv->device)) 2856 priv->hw->mac->pmt(priv->ioaddr, 0); 2857 else 2858 /* enable the clk prevously disabled */ 2859 clk_prepare_enable(priv->stmmac_clk); 2860 2861 netif_device_attach(ndev); 2862 2863 /* Enable the MAC and DMA */ 2864 stmmac_set_mac(priv->ioaddr, true); 2865 priv->hw->dma->start_tx(priv->ioaddr); 2866 priv->hw->dma->start_rx(priv->ioaddr); 2867 2868 napi_enable(&priv->napi); 2869 2870 netif_start_queue(ndev); 2871 2872 spin_unlock_irqrestore(&priv->lock, flags); 2873 2874 if (priv->phydev) 2875 phy_start(priv->phydev); 2876 2877 return 0; 2878 } 2879 2880 int stmmac_freeze(struct net_device *ndev) 2881 { 2882 if (!ndev || !netif_running(ndev)) 2883 return 0; 2884 2885 return stmmac_release(ndev); 2886 } 2887 2888 int stmmac_restore(struct net_device *ndev) 2889 { 2890 if (!ndev || !netif_running(ndev)) 2891 return 0; 2892 2893 return stmmac_open(ndev); 2894 } 2895 #endif /* CONFIG_PM */ 2896 2897 /* Driver can be configured w/ and w/ both PCI and Platf drivers 2898 * depending on the configuration selected. 2899 */ 2900 static int __init stmmac_init(void) 2901 { 2902 int ret; 2903 2904 ret = stmmac_register_platform(); 2905 if (ret) 2906 goto err; 2907 ret = stmmac_register_pci(); 2908 if (ret) 2909 goto err_pci; 2910 return 0; 2911 err_pci: 2912 stmmac_unregister_platform(); 2913 err: 2914 pr_err("stmmac: driver registration failed\n"); 2915 return ret; 2916 } 2917 2918 static void __exit stmmac_exit(void) 2919 { 2920 stmmac_unregister_platform(); 2921 stmmac_unregister_pci(); 2922 } 2923 2924 module_init(stmmac_init); 2925 module_exit(stmmac_exit); 2926 2927 #ifndef MODULE 2928 static int __init stmmac_cmdline_opt(char *str) 2929 { 2930 char *opt; 2931 2932 if (!str || !*str) 2933 return -EINVAL; 2934 while ((opt = strsep(&str, ",")) != NULL) { 2935 if (!strncmp(opt, "debug:", 6)) { 2936 if (kstrtoint(opt + 6, 0, &debug)) 2937 goto err; 2938 } else if (!strncmp(opt, "phyaddr:", 8)) { 2939 if (kstrtoint(opt + 8, 0, &phyaddr)) 2940 goto err; 2941 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2942 if (kstrtoint(opt + 11, 0, &dma_txsize)) 2943 goto err; 2944 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2945 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 2946 goto err; 2947 } else if (!strncmp(opt, "buf_sz:", 7)) { 2948 if (kstrtoint(opt + 7, 0, &buf_sz)) 2949 goto err; 2950 } else if (!strncmp(opt, "tc:", 3)) { 2951 if (kstrtoint(opt + 3, 0, &tc)) 2952 goto err; 2953 } else if (!strncmp(opt, "watchdog:", 9)) { 2954 if (kstrtoint(opt + 9, 0, &watchdog)) 2955 goto err; 2956 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2957 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 2958 goto err; 2959 } else if (!strncmp(opt, "pause:", 6)) { 2960 if (kstrtoint(opt + 6, 0, &pause)) 2961 goto err; 2962 } else if (!strncmp(opt, "eee_timer:", 10)) { 2963 if (kstrtoint(opt + 10, 0, &eee_timer)) 2964 goto err; 2965 } else if (!strncmp(opt, "chain_mode:", 11)) { 2966 if (kstrtoint(opt + 11, 0, &chain_mode)) 2967 goto err; 2968 } 2969 } 2970 return 0; 2971 2972 err: 2973 pr_err("%s: ERROR broken module parameter conversion", __func__); 2974 return -EINVAL; 2975 } 2976 2977 __setup("stmmaceth=", stmmac_cmdline_opt); 2978 #endif /* MODULE */ 2979 2980 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 2981 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 2982 MODULE_LICENSE("GPL"); 2983