1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 if (priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) 992 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 993 994 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 995 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 996 997 if (interface == PHY_INTERFACE_MODE_USXGMII) { 998 switch (speed) { 999 case SPEED_10000: 1000 ctrl |= priv->hw->link.xgmii.speed10000; 1001 break; 1002 case SPEED_5000: 1003 ctrl |= priv->hw->link.xgmii.speed5000; 1004 break; 1005 case SPEED_2500: 1006 ctrl |= priv->hw->link.xgmii.speed2500; 1007 break; 1008 default: 1009 return; 1010 } 1011 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1012 switch (speed) { 1013 case SPEED_100000: 1014 ctrl |= priv->hw->link.xlgmii.speed100000; 1015 break; 1016 case SPEED_50000: 1017 ctrl |= priv->hw->link.xlgmii.speed50000; 1018 break; 1019 case SPEED_40000: 1020 ctrl |= priv->hw->link.xlgmii.speed40000; 1021 break; 1022 case SPEED_25000: 1023 ctrl |= priv->hw->link.xlgmii.speed25000; 1024 break; 1025 case SPEED_10000: 1026 ctrl |= priv->hw->link.xgmii.speed10000; 1027 break; 1028 case SPEED_2500: 1029 ctrl |= priv->hw->link.speed2500; 1030 break; 1031 case SPEED_1000: 1032 ctrl |= priv->hw->link.speed1000; 1033 break; 1034 default: 1035 return; 1036 } 1037 } else { 1038 switch (speed) { 1039 case SPEED_2500: 1040 ctrl |= priv->hw->link.speed2500; 1041 break; 1042 case SPEED_1000: 1043 ctrl |= priv->hw->link.speed1000; 1044 break; 1045 case SPEED_100: 1046 ctrl |= priv->hw->link.speed100; 1047 break; 1048 case SPEED_10: 1049 ctrl |= priv->hw->link.speed10; 1050 break; 1051 default: 1052 return; 1053 } 1054 } 1055 1056 priv->speed = speed; 1057 1058 if (priv->plat->fix_mac_speed) 1059 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1060 1061 if (!duplex) 1062 ctrl &= ~priv->hw->link.duplex; 1063 else 1064 ctrl |= priv->hw->link.duplex; 1065 1066 /* Flow Control operation */ 1067 if (rx_pause && tx_pause) 1068 priv->flow_ctrl = FLOW_AUTO; 1069 else if (rx_pause && !tx_pause) 1070 priv->flow_ctrl = FLOW_RX; 1071 else if (!rx_pause && tx_pause) 1072 priv->flow_ctrl = FLOW_TX; 1073 else 1074 priv->flow_ctrl = FLOW_OFF; 1075 1076 stmmac_mac_flow_ctrl(priv, duplex); 1077 1078 if (ctrl != old_ctrl) 1079 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1080 1081 stmmac_mac_set(priv, priv->ioaddr, true); 1082 if (phy && priv->dma_cap.eee) { 1083 priv->eee_active = 1084 phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0; 1085 priv->eee_enabled = stmmac_eee_init(priv); 1086 priv->tx_lpi_enabled = priv->eee_enabled; 1087 stmmac_set_eee_pls(priv, priv->hw, true); 1088 } 1089 1090 if (priv->dma_cap.fpesel) 1091 stmmac_fpe_link_state_handle(priv, true); 1092 } 1093 1094 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1095 .mac_select_pcs = stmmac_mac_select_pcs, 1096 .mac_config = stmmac_mac_config, 1097 .mac_link_down = stmmac_mac_link_down, 1098 .mac_link_up = stmmac_mac_link_up, 1099 }; 1100 1101 /** 1102 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1103 * @priv: driver private structure 1104 * Description: this is to verify if the HW supports the PCS. 1105 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1106 * configured for the TBI, RTBI, or SGMII PHY interface. 1107 */ 1108 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1109 { 1110 int interface = priv->plat->interface; 1111 1112 if (priv->dma_cap.pcs) { 1113 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1114 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1115 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1116 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1117 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1118 priv->hw->pcs = STMMAC_PCS_RGMII; 1119 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1120 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1121 priv->hw->pcs = STMMAC_PCS_SGMII; 1122 } 1123 } 1124 } 1125 1126 /** 1127 * stmmac_init_phy - PHY initialization 1128 * @dev: net device structure 1129 * Description: it initializes the driver's PHY state, and attaches the PHY 1130 * to the mac driver. 1131 * Return value: 1132 * 0 on success 1133 */ 1134 static int stmmac_init_phy(struct net_device *dev) 1135 { 1136 struct stmmac_priv *priv = netdev_priv(dev); 1137 struct fwnode_handle *fwnode; 1138 int ret; 1139 1140 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1141 if (!fwnode) 1142 fwnode = dev_fwnode(priv->device); 1143 1144 if (fwnode) 1145 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1146 1147 /* Some DT bindings do not set-up the PHY handle. Let's try to 1148 * manually parse it 1149 */ 1150 if (!fwnode || ret) { 1151 int addr = priv->plat->phy_addr; 1152 struct phy_device *phydev; 1153 1154 if (addr < 0) { 1155 netdev_err(priv->dev, "no phy found\n"); 1156 return -ENODEV; 1157 } 1158 1159 phydev = mdiobus_get_phy(priv->mii, addr); 1160 if (!phydev) { 1161 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1162 return -ENODEV; 1163 } 1164 1165 ret = phylink_connect_phy(priv->phylink, phydev); 1166 } 1167 1168 if (!priv->plat->pmt) { 1169 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1170 1171 phylink_ethtool_get_wol(priv->phylink, &wol); 1172 device_set_wakeup_capable(priv->device, !!wol.supported); 1173 device_set_wakeup_enable(priv->device, !!wol.wolopts); 1174 } 1175 1176 return ret; 1177 } 1178 1179 static int stmmac_phy_setup(struct stmmac_priv *priv) 1180 { 1181 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1182 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1183 int max_speed = priv->plat->max_speed; 1184 int mode = priv->plat->phy_interface; 1185 struct phylink *phylink; 1186 1187 priv->phylink_config.dev = &priv->dev->dev; 1188 priv->phylink_config.type = PHYLINK_NETDEV; 1189 if (priv->plat->mdio_bus_data) 1190 priv->phylink_config.ovr_an_inband = 1191 mdio_bus_data->xpcs_an_inband; 1192 1193 if (!fwnode) 1194 fwnode = dev_fwnode(priv->device); 1195 1196 /* Set the platform/firmware specified interface mode */ 1197 __set_bit(mode, priv->phylink_config.supported_interfaces); 1198 1199 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1200 if (priv->hw->xpcs) 1201 xpcs_get_interfaces(priv->hw->xpcs, 1202 priv->phylink_config.supported_interfaces); 1203 1204 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1205 MAC_10 | MAC_100; 1206 1207 if (!max_speed || max_speed >= 1000) 1208 priv->phylink_config.mac_capabilities |= MAC_1000; 1209 1210 if (priv->plat->has_gmac4) { 1211 if (!max_speed || max_speed >= 2500) 1212 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1213 } else if (priv->plat->has_xgmac) { 1214 if (!max_speed || max_speed >= 2500) 1215 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1216 if (!max_speed || max_speed >= 5000) 1217 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1218 if (!max_speed || max_speed >= 10000) 1219 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1220 if (!max_speed || max_speed >= 25000) 1221 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1222 if (!max_speed || max_speed >= 40000) 1223 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1224 if (!max_speed || max_speed >= 50000) 1225 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1226 if (!max_speed || max_speed >= 100000) 1227 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1228 } 1229 1230 /* Half-Duplex can only work with single queue */ 1231 if (priv->plat->tx_queues_to_use > 1) 1232 priv->phylink_config.mac_capabilities &= 1233 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1234 priv->phylink_config.mac_managed_pm = true; 1235 1236 phylink = phylink_create(&priv->phylink_config, fwnode, 1237 mode, &stmmac_phylink_mac_ops); 1238 if (IS_ERR(phylink)) 1239 return PTR_ERR(phylink); 1240 1241 priv->phylink = phylink; 1242 return 0; 1243 } 1244 1245 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1246 struct stmmac_dma_conf *dma_conf) 1247 { 1248 u32 rx_cnt = priv->plat->rx_queues_to_use; 1249 unsigned int desc_size; 1250 void *head_rx; 1251 u32 queue; 1252 1253 /* Display RX rings */ 1254 for (queue = 0; queue < rx_cnt; queue++) { 1255 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1256 1257 pr_info("\tRX Queue %u rings\n", queue); 1258 1259 if (priv->extend_desc) { 1260 head_rx = (void *)rx_q->dma_erx; 1261 desc_size = sizeof(struct dma_extended_desc); 1262 } else { 1263 head_rx = (void *)rx_q->dma_rx; 1264 desc_size = sizeof(struct dma_desc); 1265 } 1266 1267 /* Display RX ring */ 1268 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1269 rx_q->dma_rx_phy, desc_size); 1270 } 1271 } 1272 1273 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1274 struct stmmac_dma_conf *dma_conf) 1275 { 1276 u32 tx_cnt = priv->plat->tx_queues_to_use; 1277 unsigned int desc_size; 1278 void *head_tx; 1279 u32 queue; 1280 1281 /* Display TX rings */ 1282 for (queue = 0; queue < tx_cnt; queue++) { 1283 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1284 1285 pr_info("\tTX Queue %d rings\n", queue); 1286 1287 if (priv->extend_desc) { 1288 head_tx = (void *)tx_q->dma_etx; 1289 desc_size = sizeof(struct dma_extended_desc); 1290 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1291 head_tx = (void *)tx_q->dma_entx; 1292 desc_size = sizeof(struct dma_edesc); 1293 } else { 1294 head_tx = (void *)tx_q->dma_tx; 1295 desc_size = sizeof(struct dma_desc); 1296 } 1297 1298 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1299 tx_q->dma_tx_phy, desc_size); 1300 } 1301 } 1302 1303 static void stmmac_display_rings(struct stmmac_priv *priv, 1304 struct stmmac_dma_conf *dma_conf) 1305 { 1306 /* Display RX ring */ 1307 stmmac_display_rx_rings(priv, dma_conf); 1308 1309 /* Display TX ring */ 1310 stmmac_display_tx_rings(priv, dma_conf); 1311 } 1312 1313 static int stmmac_set_bfsize(int mtu, int bufsize) 1314 { 1315 int ret = bufsize; 1316 1317 if (mtu >= BUF_SIZE_8KiB) 1318 ret = BUF_SIZE_16KiB; 1319 else if (mtu >= BUF_SIZE_4KiB) 1320 ret = BUF_SIZE_8KiB; 1321 else if (mtu >= BUF_SIZE_2KiB) 1322 ret = BUF_SIZE_4KiB; 1323 else if (mtu > DEFAULT_BUFSIZE) 1324 ret = BUF_SIZE_2KiB; 1325 else 1326 ret = DEFAULT_BUFSIZE; 1327 1328 return ret; 1329 } 1330 1331 /** 1332 * stmmac_clear_rx_descriptors - clear RX descriptors 1333 * @priv: driver private structure 1334 * @dma_conf: structure to take the dma data 1335 * @queue: RX queue index 1336 * Description: this function is called to clear the RX descriptors 1337 * in case of both basic and extended descriptors are used. 1338 */ 1339 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1340 struct stmmac_dma_conf *dma_conf, 1341 u32 queue) 1342 { 1343 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1344 int i; 1345 1346 /* Clear the RX descriptors */ 1347 for (i = 0; i < dma_conf->dma_rx_size; i++) 1348 if (priv->extend_desc) 1349 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1350 priv->use_riwt, priv->mode, 1351 (i == dma_conf->dma_rx_size - 1), 1352 dma_conf->dma_buf_sz); 1353 else 1354 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1355 priv->use_riwt, priv->mode, 1356 (i == dma_conf->dma_rx_size - 1), 1357 dma_conf->dma_buf_sz); 1358 } 1359 1360 /** 1361 * stmmac_clear_tx_descriptors - clear tx descriptors 1362 * @priv: driver private structure 1363 * @dma_conf: structure to take the dma data 1364 * @queue: TX queue index. 1365 * Description: this function is called to clear the TX descriptors 1366 * in case of both basic and extended descriptors are used. 1367 */ 1368 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1369 struct stmmac_dma_conf *dma_conf, 1370 u32 queue) 1371 { 1372 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1373 int i; 1374 1375 /* Clear the TX descriptors */ 1376 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1377 int last = (i == (dma_conf->dma_tx_size - 1)); 1378 struct dma_desc *p; 1379 1380 if (priv->extend_desc) 1381 p = &tx_q->dma_etx[i].basic; 1382 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1383 p = &tx_q->dma_entx[i].basic; 1384 else 1385 p = &tx_q->dma_tx[i]; 1386 1387 stmmac_init_tx_desc(priv, p, priv->mode, last); 1388 } 1389 } 1390 1391 /** 1392 * stmmac_clear_descriptors - clear descriptors 1393 * @priv: driver private structure 1394 * @dma_conf: structure to take the dma data 1395 * Description: this function is called to clear the TX and RX descriptors 1396 * in case of both basic and extended descriptors are used. 1397 */ 1398 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1399 struct stmmac_dma_conf *dma_conf) 1400 { 1401 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1402 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1403 u32 queue; 1404 1405 /* Clear the RX descriptors */ 1406 for (queue = 0; queue < rx_queue_cnt; queue++) 1407 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1408 1409 /* Clear the TX descriptors */ 1410 for (queue = 0; queue < tx_queue_cnt; queue++) 1411 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1412 } 1413 1414 /** 1415 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1416 * @priv: driver private structure 1417 * @dma_conf: structure to take the dma data 1418 * @p: descriptor pointer 1419 * @i: descriptor index 1420 * @flags: gfp flag 1421 * @queue: RX queue index 1422 * Description: this function is called to allocate a receive buffer, perform 1423 * the DMA mapping and init the descriptor. 1424 */ 1425 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1426 struct stmmac_dma_conf *dma_conf, 1427 struct dma_desc *p, 1428 int i, gfp_t flags, u32 queue) 1429 { 1430 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1431 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1432 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1433 1434 if (priv->dma_cap.addr64 <= 32) 1435 gfp |= GFP_DMA32; 1436 1437 if (!buf->page) { 1438 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1439 if (!buf->page) 1440 return -ENOMEM; 1441 buf->page_offset = stmmac_rx_offset(priv); 1442 } 1443 1444 if (priv->sph && !buf->sec_page) { 1445 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1446 if (!buf->sec_page) 1447 return -ENOMEM; 1448 1449 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1450 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1451 } else { 1452 buf->sec_page = NULL; 1453 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1454 } 1455 1456 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1457 1458 stmmac_set_desc_addr(priv, p, buf->addr); 1459 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1460 stmmac_init_desc3(priv, p); 1461 1462 return 0; 1463 } 1464 1465 /** 1466 * stmmac_free_rx_buffer - free RX dma buffers 1467 * @priv: private structure 1468 * @rx_q: RX queue 1469 * @i: buffer index. 1470 */ 1471 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1472 struct stmmac_rx_queue *rx_q, 1473 int i) 1474 { 1475 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1476 1477 if (buf->page) 1478 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1479 buf->page = NULL; 1480 1481 if (buf->sec_page) 1482 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1483 buf->sec_page = NULL; 1484 } 1485 1486 /** 1487 * stmmac_free_tx_buffer - free RX dma buffers 1488 * @priv: private structure 1489 * @dma_conf: structure to take the dma data 1490 * @queue: RX queue index 1491 * @i: buffer index. 1492 */ 1493 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1494 struct stmmac_dma_conf *dma_conf, 1495 u32 queue, int i) 1496 { 1497 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1498 1499 if (tx_q->tx_skbuff_dma[i].buf && 1500 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1501 if (tx_q->tx_skbuff_dma[i].map_as_page) 1502 dma_unmap_page(priv->device, 1503 tx_q->tx_skbuff_dma[i].buf, 1504 tx_q->tx_skbuff_dma[i].len, 1505 DMA_TO_DEVICE); 1506 else 1507 dma_unmap_single(priv->device, 1508 tx_q->tx_skbuff_dma[i].buf, 1509 tx_q->tx_skbuff_dma[i].len, 1510 DMA_TO_DEVICE); 1511 } 1512 1513 if (tx_q->xdpf[i] && 1514 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1515 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1516 xdp_return_frame(tx_q->xdpf[i]); 1517 tx_q->xdpf[i] = NULL; 1518 } 1519 1520 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1521 tx_q->xsk_frames_done++; 1522 1523 if (tx_q->tx_skbuff[i] && 1524 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1525 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1526 tx_q->tx_skbuff[i] = NULL; 1527 } 1528 1529 tx_q->tx_skbuff_dma[i].buf = 0; 1530 tx_q->tx_skbuff_dma[i].map_as_page = false; 1531 } 1532 1533 /** 1534 * dma_free_rx_skbufs - free RX dma buffers 1535 * @priv: private structure 1536 * @dma_conf: structure to take the dma data 1537 * @queue: RX queue index 1538 */ 1539 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1540 struct stmmac_dma_conf *dma_conf, 1541 u32 queue) 1542 { 1543 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1544 int i; 1545 1546 for (i = 0; i < dma_conf->dma_rx_size; i++) 1547 stmmac_free_rx_buffer(priv, rx_q, i); 1548 } 1549 1550 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1551 struct stmmac_dma_conf *dma_conf, 1552 u32 queue, gfp_t flags) 1553 { 1554 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1555 int i; 1556 1557 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1558 struct dma_desc *p; 1559 int ret; 1560 1561 if (priv->extend_desc) 1562 p = &((rx_q->dma_erx + i)->basic); 1563 else 1564 p = rx_q->dma_rx + i; 1565 1566 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1567 queue); 1568 if (ret) 1569 return ret; 1570 1571 rx_q->buf_alloc_num++; 1572 } 1573 1574 return 0; 1575 } 1576 1577 /** 1578 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1579 * @priv: private structure 1580 * @dma_conf: structure to take the dma data 1581 * @queue: RX queue index 1582 */ 1583 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1584 struct stmmac_dma_conf *dma_conf, 1585 u32 queue) 1586 { 1587 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1588 int i; 1589 1590 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1591 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1592 1593 if (!buf->xdp) 1594 continue; 1595 1596 xsk_buff_free(buf->xdp); 1597 buf->xdp = NULL; 1598 } 1599 } 1600 1601 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1602 struct stmmac_dma_conf *dma_conf, 1603 u32 queue) 1604 { 1605 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1606 int i; 1607 1608 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1609 struct stmmac_rx_buffer *buf; 1610 dma_addr_t dma_addr; 1611 struct dma_desc *p; 1612 1613 if (priv->extend_desc) 1614 p = (struct dma_desc *)(rx_q->dma_erx + i); 1615 else 1616 p = rx_q->dma_rx + i; 1617 1618 buf = &rx_q->buf_pool[i]; 1619 1620 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1621 if (!buf->xdp) 1622 return -ENOMEM; 1623 1624 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1625 stmmac_set_desc_addr(priv, p, dma_addr); 1626 rx_q->buf_alloc_num++; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1633 { 1634 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1635 return NULL; 1636 1637 return xsk_get_pool_from_qid(priv->dev, queue); 1638 } 1639 1640 /** 1641 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1642 * @priv: driver private structure 1643 * @dma_conf: structure to take the dma data 1644 * @queue: RX queue index 1645 * @flags: gfp flag. 1646 * Description: this function initializes the DMA RX descriptors 1647 * and allocates the socket buffers. It supports the chained and ring 1648 * modes. 1649 */ 1650 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1651 struct stmmac_dma_conf *dma_conf, 1652 u32 queue, gfp_t flags) 1653 { 1654 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1655 int ret; 1656 1657 netif_dbg(priv, probe, priv->dev, 1658 "(%s) dma_rx_phy=0x%08x\n", __func__, 1659 (u32)rx_q->dma_rx_phy); 1660 1661 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1662 1663 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1664 1665 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1666 1667 if (rx_q->xsk_pool) { 1668 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1669 MEM_TYPE_XSK_BUFF_POOL, 1670 NULL)); 1671 netdev_info(priv->dev, 1672 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1673 rx_q->queue_index); 1674 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1675 } else { 1676 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1677 MEM_TYPE_PAGE_POOL, 1678 rx_q->page_pool)); 1679 netdev_info(priv->dev, 1680 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1681 rx_q->queue_index); 1682 } 1683 1684 if (rx_q->xsk_pool) { 1685 /* RX XDP ZC buffer pool may not be populated, e.g. 1686 * xdpsock TX-only. 1687 */ 1688 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1689 } else { 1690 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1691 if (ret < 0) 1692 return -ENOMEM; 1693 } 1694 1695 /* Setup the chained descriptor addresses */ 1696 if (priv->mode == STMMAC_CHAIN_MODE) { 1697 if (priv->extend_desc) 1698 stmmac_mode_init(priv, rx_q->dma_erx, 1699 rx_q->dma_rx_phy, 1700 dma_conf->dma_rx_size, 1); 1701 else 1702 stmmac_mode_init(priv, rx_q->dma_rx, 1703 rx_q->dma_rx_phy, 1704 dma_conf->dma_rx_size, 0); 1705 } 1706 1707 return 0; 1708 } 1709 1710 static int init_dma_rx_desc_rings(struct net_device *dev, 1711 struct stmmac_dma_conf *dma_conf, 1712 gfp_t flags) 1713 { 1714 struct stmmac_priv *priv = netdev_priv(dev); 1715 u32 rx_count = priv->plat->rx_queues_to_use; 1716 int queue; 1717 int ret; 1718 1719 /* RX INITIALIZATION */ 1720 netif_dbg(priv, probe, priv->dev, 1721 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1722 1723 for (queue = 0; queue < rx_count; queue++) { 1724 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1725 if (ret) 1726 goto err_init_rx_buffers; 1727 } 1728 1729 return 0; 1730 1731 err_init_rx_buffers: 1732 while (queue >= 0) { 1733 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1734 1735 if (rx_q->xsk_pool) 1736 dma_free_rx_xskbufs(priv, dma_conf, queue); 1737 else 1738 dma_free_rx_skbufs(priv, dma_conf, queue); 1739 1740 rx_q->buf_alloc_num = 0; 1741 rx_q->xsk_pool = NULL; 1742 1743 queue--; 1744 } 1745 1746 return ret; 1747 } 1748 1749 /** 1750 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1751 * @priv: driver private structure 1752 * @dma_conf: structure to take the dma data 1753 * @queue: TX queue index 1754 * Description: this function initializes the DMA TX descriptors 1755 * and allocates the socket buffers. It supports the chained and ring 1756 * modes. 1757 */ 1758 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1759 struct stmmac_dma_conf *dma_conf, 1760 u32 queue) 1761 { 1762 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1763 int i; 1764 1765 netif_dbg(priv, probe, priv->dev, 1766 "(%s) dma_tx_phy=0x%08x\n", __func__, 1767 (u32)tx_q->dma_tx_phy); 1768 1769 /* Setup the chained descriptor addresses */ 1770 if (priv->mode == STMMAC_CHAIN_MODE) { 1771 if (priv->extend_desc) 1772 stmmac_mode_init(priv, tx_q->dma_etx, 1773 tx_q->dma_tx_phy, 1774 dma_conf->dma_tx_size, 1); 1775 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1776 stmmac_mode_init(priv, tx_q->dma_tx, 1777 tx_q->dma_tx_phy, 1778 dma_conf->dma_tx_size, 0); 1779 } 1780 1781 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1782 1783 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1784 struct dma_desc *p; 1785 1786 if (priv->extend_desc) 1787 p = &((tx_q->dma_etx + i)->basic); 1788 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1789 p = &((tx_q->dma_entx + i)->basic); 1790 else 1791 p = tx_q->dma_tx + i; 1792 1793 stmmac_clear_desc(priv, p); 1794 1795 tx_q->tx_skbuff_dma[i].buf = 0; 1796 tx_q->tx_skbuff_dma[i].map_as_page = false; 1797 tx_q->tx_skbuff_dma[i].len = 0; 1798 tx_q->tx_skbuff_dma[i].last_segment = false; 1799 tx_q->tx_skbuff[i] = NULL; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int init_dma_tx_desc_rings(struct net_device *dev, 1806 struct stmmac_dma_conf *dma_conf) 1807 { 1808 struct stmmac_priv *priv = netdev_priv(dev); 1809 u32 tx_queue_cnt; 1810 u32 queue; 1811 1812 tx_queue_cnt = priv->plat->tx_queues_to_use; 1813 1814 for (queue = 0; queue < tx_queue_cnt; queue++) 1815 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1816 1817 return 0; 1818 } 1819 1820 /** 1821 * init_dma_desc_rings - init the RX/TX descriptor rings 1822 * @dev: net device structure 1823 * @dma_conf: structure to take the dma data 1824 * @flags: gfp flag. 1825 * Description: this function initializes the DMA RX/TX descriptors 1826 * and allocates the socket buffers. It supports the chained and ring 1827 * modes. 1828 */ 1829 static int init_dma_desc_rings(struct net_device *dev, 1830 struct stmmac_dma_conf *dma_conf, 1831 gfp_t flags) 1832 { 1833 struct stmmac_priv *priv = netdev_priv(dev); 1834 int ret; 1835 1836 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1837 if (ret) 1838 return ret; 1839 1840 ret = init_dma_tx_desc_rings(dev, dma_conf); 1841 1842 stmmac_clear_descriptors(priv, dma_conf); 1843 1844 if (netif_msg_hw(priv)) 1845 stmmac_display_rings(priv, dma_conf); 1846 1847 return ret; 1848 } 1849 1850 /** 1851 * dma_free_tx_skbufs - free TX dma buffers 1852 * @priv: private structure 1853 * @dma_conf: structure to take the dma data 1854 * @queue: TX queue index 1855 */ 1856 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1857 struct stmmac_dma_conf *dma_conf, 1858 u32 queue) 1859 { 1860 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1861 int i; 1862 1863 tx_q->xsk_frames_done = 0; 1864 1865 for (i = 0; i < dma_conf->dma_tx_size; i++) 1866 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1867 1868 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1869 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1870 tx_q->xsk_frames_done = 0; 1871 tx_q->xsk_pool = NULL; 1872 } 1873 } 1874 1875 /** 1876 * stmmac_free_tx_skbufs - free TX skb buffers 1877 * @priv: private structure 1878 */ 1879 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1880 { 1881 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1882 u32 queue; 1883 1884 for (queue = 0; queue < tx_queue_cnt; queue++) 1885 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1886 } 1887 1888 /** 1889 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1890 * @priv: private structure 1891 * @dma_conf: structure to take the dma data 1892 * @queue: RX queue index 1893 */ 1894 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1895 struct stmmac_dma_conf *dma_conf, 1896 u32 queue) 1897 { 1898 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1899 1900 /* Release the DMA RX socket buffers */ 1901 if (rx_q->xsk_pool) 1902 dma_free_rx_xskbufs(priv, dma_conf, queue); 1903 else 1904 dma_free_rx_skbufs(priv, dma_conf, queue); 1905 1906 rx_q->buf_alloc_num = 0; 1907 rx_q->xsk_pool = NULL; 1908 1909 /* Free DMA regions of consistent memory previously allocated */ 1910 if (!priv->extend_desc) 1911 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1912 sizeof(struct dma_desc), 1913 rx_q->dma_rx, rx_q->dma_rx_phy); 1914 else 1915 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1916 sizeof(struct dma_extended_desc), 1917 rx_q->dma_erx, rx_q->dma_rx_phy); 1918 1919 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1920 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1921 1922 kfree(rx_q->buf_pool); 1923 if (rx_q->page_pool) 1924 page_pool_destroy(rx_q->page_pool); 1925 } 1926 1927 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1928 struct stmmac_dma_conf *dma_conf) 1929 { 1930 u32 rx_count = priv->plat->rx_queues_to_use; 1931 u32 queue; 1932 1933 /* Free RX queue resources */ 1934 for (queue = 0; queue < rx_count; queue++) 1935 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1936 } 1937 1938 /** 1939 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1940 * @priv: private structure 1941 * @dma_conf: structure to take the dma data 1942 * @queue: TX queue index 1943 */ 1944 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1945 struct stmmac_dma_conf *dma_conf, 1946 u32 queue) 1947 { 1948 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1949 size_t size; 1950 void *addr; 1951 1952 /* Release the DMA TX socket buffers */ 1953 dma_free_tx_skbufs(priv, dma_conf, queue); 1954 1955 if (priv->extend_desc) { 1956 size = sizeof(struct dma_extended_desc); 1957 addr = tx_q->dma_etx; 1958 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1959 size = sizeof(struct dma_edesc); 1960 addr = tx_q->dma_entx; 1961 } else { 1962 size = sizeof(struct dma_desc); 1963 addr = tx_q->dma_tx; 1964 } 1965 1966 size *= dma_conf->dma_tx_size; 1967 1968 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1969 1970 kfree(tx_q->tx_skbuff_dma); 1971 kfree(tx_q->tx_skbuff); 1972 } 1973 1974 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1975 struct stmmac_dma_conf *dma_conf) 1976 { 1977 u32 tx_count = priv->plat->tx_queues_to_use; 1978 u32 queue; 1979 1980 /* Free TX queue resources */ 1981 for (queue = 0; queue < tx_count; queue++) 1982 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1983 } 1984 1985 /** 1986 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1987 * @priv: private structure 1988 * @dma_conf: structure to take the dma data 1989 * @queue: RX queue index 1990 * Description: according to which descriptor can be used (extend or basic) 1991 * this function allocates the resources for TX and RX paths. In case of 1992 * reception, for example, it pre-allocated the RX socket buffer in order to 1993 * allow zero-copy mechanism. 1994 */ 1995 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1996 struct stmmac_dma_conf *dma_conf, 1997 u32 queue) 1998 { 1999 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 2000 struct stmmac_channel *ch = &priv->channel[queue]; 2001 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2002 struct page_pool_params pp_params = { 0 }; 2003 unsigned int num_pages; 2004 unsigned int napi_id; 2005 int ret; 2006 2007 rx_q->queue_index = queue; 2008 rx_q->priv_data = priv; 2009 2010 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2011 pp_params.pool_size = dma_conf->dma_rx_size; 2012 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2013 pp_params.order = ilog2(num_pages); 2014 pp_params.nid = dev_to_node(priv->device); 2015 pp_params.dev = priv->device; 2016 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2017 pp_params.offset = stmmac_rx_offset(priv); 2018 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2019 2020 rx_q->page_pool = page_pool_create(&pp_params); 2021 if (IS_ERR(rx_q->page_pool)) { 2022 ret = PTR_ERR(rx_q->page_pool); 2023 rx_q->page_pool = NULL; 2024 return ret; 2025 } 2026 2027 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2028 sizeof(*rx_q->buf_pool), 2029 GFP_KERNEL); 2030 if (!rx_q->buf_pool) 2031 return -ENOMEM; 2032 2033 if (priv->extend_desc) { 2034 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2035 dma_conf->dma_rx_size * 2036 sizeof(struct dma_extended_desc), 2037 &rx_q->dma_rx_phy, 2038 GFP_KERNEL); 2039 if (!rx_q->dma_erx) 2040 return -ENOMEM; 2041 2042 } else { 2043 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2044 dma_conf->dma_rx_size * 2045 sizeof(struct dma_desc), 2046 &rx_q->dma_rx_phy, 2047 GFP_KERNEL); 2048 if (!rx_q->dma_rx) 2049 return -ENOMEM; 2050 } 2051 2052 if (stmmac_xdp_is_enabled(priv) && 2053 test_bit(queue, priv->af_xdp_zc_qps)) 2054 napi_id = ch->rxtx_napi.napi_id; 2055 else 2056 napi_id = ch->rx_napi.napi_id; 2057 2058 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2059 rx_q->queue_index, 2060 napi_id); 2061 if (ret) { 2062 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2063 return -EINVAL; 2064 } 2065 2066 return 0; 2067 } 2068 2069 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2070 struct stmmac_dma_conf *dma_conf) 2071 { 2072 u32 rx_count = priv->plat->rx_queues_to_use; 2073 u32 queue; 2074 int ret; 2075 2076 /* RX queues buffers and DMA */ 2077 for (queue = 0; queue < rx_count; queue++) { 2078 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2079 if (ret) 2080 goto err_dma; 2081 } 2082 2083 return 0; 2084 2085 err_dma: 2086 free_dma_rx_desc_resources(priv, dma_conf); 2087 2088 return ret; 2089 } 2090 2091 /** 2092 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2093 * @priv: private structure 2094 * @dma_conf: structure to take the dma data 2095 * @queue: TX queue index 2096 * Description: according to which descriptor can be used (extend or basic) 2097 * this function allocates the resources for TX and RX paths. In case of 2098 * reception, for example, it pre-allocated the RX socket buffer in order to 2099 * allow zero-copy mechanism. 2100 */ 2101 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2102 struct stmmac_dma_conf *dma_conf, 2103 u32 queue) 2104 { 2105 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2106 size_t size; 2107 void *addr; 2108 2109 tx_q->queue_index = queue; 2110 tx_q->priv_data = priv; 2111 2112 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2113 sizeof(*tx_q->tx_skbuff_dma), 2114 GFP_KERNEL); 2115 if (!tx_q->tx_skbuff_dma) 2116 return -ENOMEM; 2117 2118 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2119 sizeof(struct sk_buff *), 2120 GFP_KERNEL); 2121 if (!tx_q->tx_skbuff) 2122 return -ENOMEM; 2123 2124 if (priv->extend_desc) 2125 size = sizeof(struct dma_extended_desc); 2126 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2127 size = sizeof(struct dma_edesc); 2128 else 2129 size = sizeof(struct dma_desc); 2130 2131 size *= dma_conf->dma_tx_size; 2132 2133 addr = dma_alloc_coherent(priv->device, size, 2134 &tx_q->dma_tx_phy, GFP_KERNEL); 2135 if (!addr) 2136 return -ENOMEM; 2137 2138 if (priv->extend_desc) 2139 tx_q->dma_etx = addr; 2140 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2141 tx_q->dma_entx = addr; 2142 else 2143 tx_q->dma_tx = addr; 2144 2145 return 0; 2146 } 2147 2148 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2149 struct stmmac_dma_conf *dma_conf) 2150 { 2151 u32 tx_count = priv->plat->tx_queues_to_use; 2152 u32 queue; 2153 int ret; 2154 2155 /* TX queues buffers and DMA */ 2156 for (queue = 0; queue < tx_count; queue++) { 2157 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2158 if (ret) 2159 goto err_dma; 2160 } 2161 2162 return 0; 2163 2164 err_dma: 2165 free_dma_tx_desc_resources(priv, dma_conf); 2166 return ret; 2167 } 2168 2169 /** 2170 * alloc_dma_desc_resources - alloc TX/RX resources. 2171 * @priv: private structure 2172 * @dma_conf: structure to take the dma data 2173 * Description: according to which descriptor can be used (extend or basic) 2174 * this function allocates the resources for TX and RX paths. In case of 2175 * reception, for example, it pre-allocated the RX socket buffer in order to 2176 * allow zero-copy mechanism. 2177 */ 2178 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2179 struct stmmac_dma_conf *dma_conf) 2180 { 2181 /* RX Allocation */ 2182 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2183 2184 if (ret) 2185 return ret; 2186 2187 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2188 2189 return ret; 2190 } 2191 2192 /** 2193 * free_dma_desc_resources - free dma desc resources 2194 * @priv: private structure 2195 * @dma_conf: structure to take the dma data 2196 */ 2197 static void free_dma_desc_resources(struct stmmac_priv *priv, 2198 struct stmmac_dma_conf *dma_conf) 2199 { 2200 /* Release the DMA TX socket buffers */ 2201 free_dma_tx_desc_resources(priv, dma_conf); 2202 2203 /* Release the DMA RX socket buffers later 2204 * to ensure all pending XDP_TX buffers are returned. 2205 */ 2206 free_dma_rx_desc_resources(priv, dma_conf); 2207 } 2208 2209 /** 2210 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2211 * @priv: driver private structure 2212 * Description: It is used for enabling the rx queues in the MAC 2213 */ 2214 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2215 { 2216 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2217 int queue; 2218 u8 mode; 2219 2220 for (queue = 0; queue < rx_queues_count; queue++) { 2221 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2222 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2223 } 2224 } 2225 2226 /** 2227 * stmmac_start_rx_dma - start RX DMA channel 2228 * @priv: driver private structure 2229 * @chan: RX channel index 2230 * Description: 2231 * This starts a RX DMA channel 2232 */ 2233 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2234 { 2235 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2236 stmmac_start_rx(priv, priv->ioaddr, chan); 2237 } 2238 2239 /** 2240 * stmmac_start_tx_dma - start TX DMA channel 2241 * @priv: driver private structure 2242 * @chan: TX channel index 2243 * Description: 2244 * This starts a TX DMA channel 2245 */ 2246 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2247 { 2248 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2249 stmmac_start_tx(priv, priv->ioaddr, chan); 2250 } 2251 2252 /** 2253 * stmmac_stop_rx_dma - stop RX DMA channel 2254 * @priv: driver private structure 2255 * @chan: RX channel index 2256 * Description: 2257 * This stops a RX DMA channel 2258 */ 2259 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2260 { 2261 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2262 stmmac_stop_rx(priv, priv->ioaddr, chan); 2263 } 2264 2265 /** 2266 * stmmac_stop_tx_dma - stop TX DMA channel 2267 * @priv: driver private structure 2268 * @chan: TX channel index 2269 * Description: 2270 * This stops a TX DMA channel 2271 */ 2272 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2273 { 2274 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2275 stmmac_stop_tx(priv, priv->ioaddr, chan); 2276 } 2277 2278 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2279 { 2280 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2281 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2282 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2283 u32 chan; 2284 2285 for (chan = 0; chan < dma_csr_ch; chan++) { 2286 struct stmmac_channel *ch = &priv->channel[chan]; 2287 unsigned long flags; 2288 2289 spin_lock_irqsave(&ch->lock, flags); 2290 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2291 spin_unlock_irqrestore(&ch->lock, flags); 2292 } 2293 } 2294 2295 /** 2296 * stmmac_start_all_dma - start all RX and TX DMA channels 2297 * @priv: driver private structure 2298 * Description: 2299 * This starts all the RX and TX DMA channels 2300 */ 2301 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2302 { 2303 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2304 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2305 u32 chan = 0; 2306 2307 for (chan = 0; chan < rx_channels_count; chan++) 2308 stmmac_start_rx_dma(priv, chan); 2309 2310 for (chan = 0; chan < tx_channels_count; chan++) 2311 stmmac_start_tx_dma(priv, chan); 2312 } 2313 2314 /** 2315 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2316 * @priv: driver private structure 2317 * Description: 2318 * This stops the RX and TX DMA channels 2319 */ 2320 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2321 { 2322 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2323 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2324 u32 chan = 0; 2325 2326 for (chan = 0; chan < rx_channels_count; chan++) 2327 stmmac_stop_rx_dma(priv, chan); 2328 2329 for (chan = 0; chan < tx_channels_count; chan++) 2330 stmmac_stop_tx_dma(priv, chan); 2331 } 2332 2333 /** 2334 * stmmac_dma_operation_mode - HW DMA operation mode 2335 * @priv: driver private structure 2336 * Description: it is used for configuring the DMA operation mode register in 2337 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2338 */ 2339 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2340 { 2341 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2342 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2343 int rxfifosz = priv->plat->rx_fifo_size; 2344 int txfifosz = priv->plat->tx_fifo_size; 2345 u32 txmode = 0; 2346 u32 rxmode = 0; 2347 u32 chan = 0; 2348 u8 qmode = 0; 2349 2350 if (rxfifosz == 0) 2351 rxfifosz = priv->dma_cap.rx_fifo_size; 2352 if (txfifosz == 0) 2353 txfifosz = priv->dma_cap.tx_fifo_size; 2354 2355 /* Adjust for real per queue fifo size */ 2356 rxfifosz /= rx_channels_count; 2357 txfifosz /= tx_channels_count; 2358 2359 if (priv->plat->force_thresh_dma_mode) { 2360 txmode = tc; 2361 rxmode = tc; 2362 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2363 /* 2364 * In case of GMAC, SF mode can be enabled 2365 * to perform the TX COE in HW. This depends on: 2366 * 1) TX COE if actually supported 2367 * 2) There is no bugged Jumbo frame support 2368 * that needs to not insert csum in the TDES. 2369 */ 2370 txmode = SF_DMA_MODE; 2371 rxmode = SF_DMA_MODE; 2372 priv->xstats.threshold = SF_DMA_MODE; 2373 } else { 2374 txmode = tc; 2375 rxmode = SF_DMA_MODE; 2376 } 2377 2378 /* configure all channels */ 2379 for (chan = 0; chan < rx_channels_count; chan++) { 2380 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2381 u32 buf_size; 2382 2383 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2384 2385 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2386 rxfifosz, qmode); 2387 2388 if (rx_q->xsk_pool) { 2389 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2390 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2391 buf_size, 2392 chan); 2393 } else { 2394 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2395 priv->dma_conf.dma_buf_sz, 2396 chan); 2397 } 2398 } 2399 2400 for (chan = 0; chan < tx_channels_count; chan++) { 2401 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2402 2403 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2404 txfifosz, qmode); 2405 } 2406 } 2407 2408 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2409 { 2410 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2411 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2412 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2413 unsigned int entry = tx_q->cur_tx; 2414 struct dma_desc *tx_desc = NULL; 2415 struct xdp_desc xdp_desc; 2416 bool work_done = true; 2417 2418 /* Avoids TX time-out as we are sharing with slow path */ 2419 txq_trans_cond_update(nq); 2420 2421 budget = min(budget, stmmac_tx_avail(priv, queue)); 2422 2423 while (budget-- > 0) { 2424 dma_addr_t dma_addr; 2425 bool set_ic; 2426 2427 /* We are sharing with slow path and stop XSK TX desc submission when 2428 * available TX ring is less than threshold. 2429 */ 2430 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2431 !netif_carrier_ok(priv->dev)) { 2432 work_done = false; 2433 break; 2434 } 2435 2436 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2437 break; 2438 2439 if (likely(priv->extend_desc)) 2440 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2441 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2442 tx_desc = &tx_q->dma_entx[entry].basic; 2443 else 2444 tx_desc = tx_q->dma_tx + entry; 2445 2446 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2447 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2448 2449 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2450 2451 /* To return XDP buffer to XSK pool, we simple call 2452 * xsk_tx_completed(), so we don't need to fill up 2453 * 'buf' and 'xdpf'. 2454 */ 2455 tx_q->tx_skbuff_dma[entry].buf = 0; 2456 tx_q->xdpf[entry] = NULL; 2457 2458 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2459 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2460 tx_q->tx_skbuff_dma[entry].last_segment = true; 2461 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2462 2463 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2464 2465 tx_q->tx_count_frames++; 2466 2467 if (!priv->tx_coal_frames[queue]) 2468 set_ic = false; 2469 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2470 set_ic = true; 2471 else 2472 set_ic = false; 2473 2474 if (set_ic) { 2475 tx_q->tx_count_frames = 0; 2476 stmmac_set_tx_ic(priv, tx_desc); 2477 priv->xstats.tx_set_ic_bit++; 2478 } 2479 2480 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2481 true, priv->mode, true, true, 2482 xdp_desc.len); 2483 2484 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2485 2486 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2487 entry = tx_q->cur_tx; 2488 } 2489 2490 if (tx_desc) { 2491 stmmac_flush_tx_descriptors(priv, queue); 2492 xsk_tx_release(pool); 2493 } 2494 2495 /* Return true if all of the 3 conditions are met 2496 * a) TX Budget is still available 2497 * b) work_done = true when XSK TX desc peek is empty (no more 2498 * pending XSK TX for transmission) 2499 */ 2500 return !!budget && work_done; 2501 } 2502 2503 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2504 { 2505 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2506 tc += 64; 2507 2508 if (priv->plat->force_thresh_dma_mode) 2509 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2510 else 2511 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2512 chan); 2513 2514 priv->xstats.threshold = tc; 2515 } 2516 } 2517 2518 /** 2519 * stmmac_tx_clean - to manage the transmission completion 2520 * @priv: driver private structure 2521 * @budget: napi budget limiting this functions packet handling 2522 * @queue: TX queue index 2523 * Description: it reclaims the transmit resources after transmission completes. 2524 */ 2525 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2526 { 2527 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2528 unsigned int bytes_compl = 0, pkts_compl = 0; 2529 unsigned int entry, xmits = 0, count = 0; 2530 2531 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2532 2533 priv->xstats.tx_clean++; 2534 2535 tx_q->xsk_frames_done = 0; 2536 2537 entry = tx_q->dirty_tx; 2538 2539 /* Try to clean all TX complete frame in 1 shot */ 2540 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2541 struct xdp_frame *xdpf; 2542 struct sk_buff *skb; 2543 struct dma_desc *p; 2544 int status; 2545 2546 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2547 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2548 xdpf = tx_q->xdpf[entry]; 2549 skb = NULL; 2550 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2551 xdpf = NULL; 2552 skb = tx_q->tx_skbuff[entry]; 2553 } else { 2554 xdpf = NULL; 2555 skb = NULL; 2556 } 2557 2558 if (priv->extend_desc) 2559 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2560 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2561 p = &tx_q->dma_entx[entry].basic; 2562 else 2563 p = tx_q->dma_tx + entry; 2564 2565 status = stmmac_tx_status(priv, &priv->dev->stats, 2566 &priv->xstats, p, priv->ioaddr); 2567 /* Check if the descriptor is owned by the DMA */ 2568 if (unlikely(status & tx_dma_own)) 2569 break; 2570 2571 count++; 2572 2573 /* Make sure descriptor fields are read after reading 2574 * the own bit. 2575 */ 2576 dma_rmb(); 2577 2578 /* Just consider the last segment and ...*/ 2579 if (likely(!(status & tx_not_ls))) { 2580 /* ... verify the status error condition */ 2581 if (unlikely(status & tx_err)) { 2582 priv->dev->stats.tx_errors++; 2583 if (unlikely(status & tx_err_bump_tc)) 2584 stmmac_bump_dma_threshold(priv, queue); 2585 } else { 2586 priv->dev->stats.tx_packets++; 2587 priv->xstats.tx_pkt_n++; 2588 priv->xstats.txq_stats[queue].tx_pkt_n++; 2589 } 2590 if (skb) 2591 stmmac_get_tx_hwtstamp(priv, p, skb); 2592 } 2593 2594 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2595 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2596 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2597 dma_unmap_page(priv->device, 2598 tx_q->tx_skbuff_dma[entry].buf, 2599 tx_q->tx_skbuff_dma[entry].len, 2600 DMA_TO_DEVICE); 2601 else 2602 dma_unmap_single(priv->device, 2603 tx_q->tx_skbuff_dma[entry].buf, 2604 tx_q->tx_skbuff_dma[entry].len, 2605 DMA_TO_DEVICE); 2606 tx_q->tx_skbuff_dma[entry].buf = 0; 2607 tx_q->tx_skbuff_dma[entry].len = 0; 2608 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2609 } 2610 2611 stmmac_clean_desc3(priv, tx_q, p); 2612 2613 tx_q->tx_skbuff_dma[entry].last_segment = false; 2614 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2615 2616 if (xdpf && 2617 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2618 xdp_return_frame_rx_napi(xdpf); 2619 tx_q->xdpf[entry] = NULL; 2620 } 2621 2622 if (xdpf && 2623 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2624 xdp_return_frame(xdpf); 2625 tx_q->xdpf[entry] = NULL; 2626 } 2627 2628 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2629 tx_q->xsk_frames_done++; 2630 2631 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2632 if (likely(skb)) { 2633 pkts_compl++; 2634 bytes_compl += skb->len; 2635 dev_consume_skb_any(skb); 2636 tx_q->tx_skbuff[entry] = NULL; 2637 } 2638 } 2639 2640 stmmac_release_tx_desc(priv, p, priv->mode); 2641 2642 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2643 } 2644 tx_q->dirty_tx = entry; 2645 2646 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2647 pkts_compl, bytes_compl); 2648 2649 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2650 queue))) && 2651 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2652 2653 netif_dbg(priv, tx_done, priv->dev, 2654 "%s: restart transmit\n", __func__); 2655 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2656 } 2657 2658 if (tx_q->xsk_pool) { 2659 bool work_done; 2660 2661 if (tx_q->xsk_frames_done) 2662 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2663 2664 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2665 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2666 2667 /* For XSK TX, we try to send as many as possible. 2668 * If XSK work done (XSK TX desc empty and budget still 2669 * available), return "budget - 1" to reenable TX IRQ. 2670 * Else, return "budget" to make NAPI continue polling. 2671 */ 2672 work_done = stmmac_xdp_xmit_zc(priv, queue, 2673 STMMAC_XSK_TX_BUDGET_MAX); 2674 if (work_done) 2675 xmits = budget - 1; 2676 else 2677 xmits = budget; 2678 } 2679 2680 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2681 priv->eee_sw_timer_en) { 2682 if (stmmac_enable_eee_mode(priv)) 2683 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2684 } 2685 2686 /* We still have pending packets, let's call for a new scheduling */ 2687 if (tx_q->dirty_tx != tx_q->cur_tx) 2688 hrtimer_start(&tx_q->txtimer, 2689 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2690 HRTIMER_MODE_REL); 2691 2692 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2693 2694 /* Combine decisions from TX clean and XSK TX */ 2695 return max(count, xmits); 2696 } 2697 2698 /** 2699 * stmmac_tx_err - to manage the tx error 2700 * @priv: driver private structure 2701 * @chan: channel index 2702 * Description: it cleans the descriptors and restarts the transmission 2703 * in case of transmission errors. 2704 */ 2705 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2706 { 2707 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2708 2709 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2710 2711 stmmac_stop_tx_dma(priv, chan); 2712 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2713 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2714 stmmac_reset_tx_queue(priv, chan); 2715 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2716 tx_q->dma_tx_phy, chan); 2717 stmmac_start_tx_dma(priv, chan); 2718 2719 priv->dev->stats.tx_errors++; 2720 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2721 } 2722 2723 /** 2724 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2725 * @priv: driver private structure 2726 * @txmode: TX operating mode 2727 * @rxmode: RX operating mode 2728 * @chan: channel index 2729 * Description: it is used for configuring of the DMA operation mode in 2730 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2731 * mode. 2732 */ 2733 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2734 u32 rxmode, u32 chan) 2735 { 2736 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2737 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2738 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2739 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2740 int rxfifosz = priv->plat->rx_fifo_size; 2741 int txfifosz = priv->plat->tx_fifo_size; 2742 2743 if (rxfifosz == 0) 2744 rxfifosz = priv->dma_cap.rx_fifo_size; 2745 if (txfifosz == 0) 2746 txfifosz = priv->dma_cap.tx_fifo_size; 2747 2748 /* Adjust for real per queue fifo size */ 2749 rxfifosz /= rx_channels_count; 2750 txfifosz /= tx_channels_count; 2751 2752 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2753 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2754 } 2755 2756 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2757 { 2758 int ret; 2759 2760 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2761 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2762 if (ret && (ret != -EINVAL)) { 2763 stmmac_global_err(priv); 2764 return true; 2765 } 2766 2767 return false; 2768 } 2769 2770 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2771 { 2772 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2773 &priv->xstats, chan, dir); 2774 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2775 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2776 struct stmmac_channel *ch = &priv->channel[chan]; 2777 struct napi_struct *rx_napi; 2778 struct napi_struct *tx_napi; 2779 unsigned long flags; 2780 2781 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2782 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2783 2784 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2785 if (napi_schedule_prep(rx_napi)) { 2786 spin_lock_irqsave(&ch->lock, flags); 2787 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2788 spin_unlock_irqrestore(&ch->lock, flags); 2789 __napi_schedule(rx_napi); 2790 } 2791 } 2792 2793 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2794 if (napi_schedule_prep(tx_napi)) { 2795 spin_lock_irqsave(&ch->lock, flags); 2796 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2797 spin_unlock_irqrestore(&ch->lock, flags); 2798 __napi_schedule(tx_napi); 2799 } 2800 } 2801 2802 return status; 2803 } 2804 2805 /** 2806 * stmmac_dma_interrupt - DMA ISR 2807 * @priv: driver private structure 2808 * Description: this is the DMA ISR. It is called by the main ISR. 2809 * It calls the dwmac dma routine and schedule poll method in case of some 2810 * work can be done. 2811 */ 2812 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2813 { 2814 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2815 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2816 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2817 tx_channel_count : rx_channel_count; 2818 u32 chan; 2819 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2820 2821 /* Make sure we never check beyond our status buffer. */ 2822 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2823 channels_to_check = ARRAY_SIZE(status); 2824 2825 for (chan = 0; chan < channels_to_check; chan++) 2826 status[chan] = stmmac_napi_check(priv, chan, 2827 DMA_DIR_RXTX); 2828 2829 for (chan = 0; chan < tx_channel_count; chan++) { 2830 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2831 /* Try to bump up the dma threshold on this failure */ 2832 stmmac_bump_dma_threshold(priv, chan); 2833 } else if (unlikely(status[chan] == tx_hard_error)) { 2834 stmmac_tx_err(priv, chan); 2835 } 2836 } 2837 } 2838 2839 /** 2840 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2841 * @priv: driver private structure 2842 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2843 */ 2844 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2845 { 2846 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2847 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2848 2849 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2850 2851 if (priv->dma_cap.rmon) { 2852 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2853 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2854 } else 2855 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2856 } 2857 2858 /** 2859 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2860 * @priv: driver private structure 2861 * Description: 2862 * new GMAC chip generations have a new register to indicate the 2863 * presence of the optional feature/functions. 2864 * This can be also used to override the value passed through the 2865 * platform and necessary for old MAC10/100 and GMAC chips. 2866 */ 2867 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2868 { 2869 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2870 } 2871 2872 /** 2873 * stmmac_check_ether_addr - check if the MAC addr is valid 2874 * @priv: driver private structure 2875 * Description: 2876 * it is to verify if the MAC address is valid, in case of failures it 2877 * generates a random MAC address 2878 */ 2879 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2880 { 2881 u8 addr[ETH_ALEN]; 2882 2883 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2884 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2885 if (is_valid_ether_addr(addr)) 2886 eth_hw_addr_set(priv->dev, addr); 2887 else 2888 eth_hw_addr_random(priv->dev); 2889 dev_info(priv->device, "device MAC address %pM\n", 2890 priv->dev->dev_addr); 2891 } 2892 } 2893 2894 /** 2895 * stmmac_init_dma_engine - DMA init. 2896 * @priv: driver private structure 2897 * Description: 2898 * It inits the DMA invoking the specific MAC/GMAC callback. 2899 * Some DMA parameters can be passed from the platform; 2900 * in case of these are not passed a default is kept for the MAC or GMAC. 2901 */ 2902 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2903 { 2904 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2905 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2906 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2907 struct stmmac_rx_queue *rx_q; 2908 struct stmmac_tx_queue *tx_q; 2909 u32 chan = 0; 2910 int atds = 0; 2911 int ret = 0; 2912 2913 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2914 dev_err(priv->device, "Invalid DMA configuration\n"); 2915 return -EINVAL; 2916 } 2917 2918 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2919 atds = 1; 2920 2921 ret = stmmac_reset(priv, priv->ioaddr); 2922 if (ret) { 2923 dev_err(priv->device, "Failed to reset the dma\n"); 2924 return ret; 2925 } 2926 2927 /* DMA Configuration */ 2928 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2929 2930 if (priv->plat->axi) 2931 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2932 2933 /* DMA CSR Channel configuration */ 2934 for (chan = 0; chan < dma_csr_ch; chan++) { 2935 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2936 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2937 } 2938 2939 /* DMA RX Channel Configuration */ 2940 for (chan = 0; chan < rx_channels_count; chan++) { 2941 rx_q = &priv->dma_conf.rx_queue[chan]; 2942 2943 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2944 rx_q->dma_rx_phy, chan); 2945 2946 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2947 (rx_q->buf_alloc_num * 2948 sizeof(struct dma_desc)); 2949 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2950 rx_q->rx_tail_addr, chan); 2951 } 2952 2953 /* DMA TX Channel Configuration */ 2954 for (chan = 0; chan < tx_channels_count; chan++) { 2955 tx_q = &priv->dma_conf.tx_queue[chan]; 2956 2957 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2958 tx_q->dma_tx_phy, chan); 2959 2960 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2961 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2962 tx_q->tx_tail_addr, chan); 2963 } 2964 2965 return ret; 2966 } 2967 2968 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2969 { 2970 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2971 2972 hrtimer_start(&tx_q->txtimer, 2973 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2974 HRTIMER_MODE_REL); 2975 } 2976 2977 /** 2978 * stmmac_tx_timer - mitigation sw timer for tx. 2979 * @t: data pointer 2980 * Description: 2981 * This is the timer handler to directly invoke the stmmac_tx_clean. 2982 */ 2983 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2984 { 2985 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2986 struct stmmac_priv *priv = tx_q->priv_data; 2987 struct stmmac_channel *ch; 2988 struct napi_struct *napi; 2989 2990 ch = &priv->channel[tx_q->queue_index]; 2991 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2992 2993 if (likely(napi_schedule_prep(napi))) { 2994 unsigned long flags; 2995 2996 spin_lock_irqsave(&ch->lock, flags); 2997 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2998 spin_unlock_irqrestore(&ch->lock, flags); 2999 __napi_schedule(napi); 3000 } 3001 3002 return HRTIMER_NORESTART; 3003 } 3004 3005 /** 3006 * stmmac_init_coalesce - init mitigation options. 3007 * @priv: driver private structure 3008 * Description: 3009 * This inits the coalesce parameters: i.e. timer rate, 3010 * timer handler and default threshold used for enabling the 3011 * interrupt on completion bit. 3012 */ 3013 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3014 { 3015 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3016 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3017 u32 chan; 3018 3019 for (chan = 0; chan < tx_channel_count; chan++) { 3020 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3021 3022 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3023 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3024 3025 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3026 tx_q->txtimer.function = stmmac_tx_timer; 3027 } 3028 3029 for (chan = 0; chan < rx_channel_count; chan++) 3030 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3031 } 3032 3033 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3034 { 3035 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3036 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3037 u32 chan; 3038 3039 /* set TX ring length */ 3040 for (chan = 0; chan < tx_channels_count; chan++) 3041 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3042 (priv->dma_conf.dma_tx_size - 1), chan); 3043 3044 /* set RX ring length */ 3045 for (chan = 0; chan < rx_channels_count; chan++) 3046 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3047 (priv->dma_conf.dma_rx_size - 1), chan); 3048 } 3049 3050 /** 3051 * stmmac_set_tx_queue_weight - Set TX queue weight 3052 * @priv: driver private structure 3053 * Description: It is used for setting TX queues weight 3054 */ 3055 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3056 { 3057 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3058 u32 weight; 3059 u32 queue; 3060 3061 for (queue = 0; queue < tx_queues_count; queue++) { 3062 weight = priv->plat->tx_queues_cfg[queue].weight; 3063 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3064 } 3065 } 3066 3067 /** 3068 * stmmac_configure_cbs - Configure CBS in TX queue 3069 * @priv: driver private structure 3070 * Description: It is used for configuring CBS in AVB TX queues 3071 */ 3072 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3073 { 3074 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3075 u32 mode_to_use; 3076 u32 queue; 3077 3078 /* queue 0 is reserved for legacy traffic */ 3079 for (queue = 1; queue < tx_queues_count; queue++) { 3080 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3081 if (mode_to_use == MTL_QUEUE_DCB) 3082 continue; 3083 3084 stmmac_config_cbs(priv, priv->hw, 3085 priv->plat->tx_queues_cfg[queue].send_slope, 3086 priv->plat->tx_queues_cfg[queue].idle_slope, 3087 priv->plat->tx_queues_cfg[queue].high_credit, 3088 priv->plat->tx_queues_cfg[queue].low_credit, 3089 queue); 3090 } 3091 } 3092 3093 /** 3094 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3095 * @priv: driver private structure 3096 * Description: It is used for mapping RX queues to RX dma channels 3097 */ 3098 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3099 { 3100 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3101 u32 queue; 3102 u32 chan; 3103 3104 for (queue = 0; queue < rx_queues_count; queue++) { 3105 chan = priv->plat->rx_queues_cfg[queue].chan; 3106 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3107 } 3108 } 3109 3110 /** 3111 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3112 * @priv: driver private structure 3113 * Description: It is used for configuring the RX Queue Priority 3114 */ 3115 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3116 { 3117 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3118 u32 queue; 3119 u32 prio; 3120 3121 for (queue = 0; queue < rx_queues_count; queue++) { 3122 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3123 continue; 3124 3125 prio = priv->plat->rx_queues_cfg[queue].prio; 3126 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3127 } 3128 } 3129 3130 /** 3131 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3132 * @priv: driver private structure 3133 * Description: It is used for configuring the TX Queue Priority 3134 */ 3135 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3136 { 3137 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3138 u32 queue; 3139 u32 prio; 3140 3141 for (queue = 0; queue < tx_queues_count; queue++) { 3142 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3143 continue; 3144 3145 prio = priv->plat->tx_queues_cfg[queue].prio; 3146 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3147 } 3148 } 3149 3150 /** 3151 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3152 * @priv: driver private structure 3153 * Description: It is used for configuring the RX queue routing 3154 */ 3155 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3156 { 3157 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3158 u32 queue; 3159 u8 packet; 3160 3161 for (queue = 0; queue < rx_queues_count; queue++) { 3162 /* no specific packet type routing specified for the queue */ 3163 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3164 continue; 3165 3166 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3167 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3168 } 3169 } 3170 3171 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3172 { 3173 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3174 priv->rss.enable = false; 3175 return; 3176 } 3177 3178 if (priv->dev->features & NETIF_F_RXHASH) 3179 priv->rss.enable = true; 3180 else 3181 priv->rss.enable = false; 3182 3183 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3184 priv->plat->rx_queues_to_use); 3185 } 3186 3187 /** 3188 * stmmac_mtl_configuration - Configure MTL 3189 * @priv: driver private structure 3190 * Description: It is used for configurring MTL 3191 */ 3192 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3193 { 3194 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3195 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3196 3197 if (tx_queues_count > 1) 3198 stmmac_set_tx_queue_weight(priv); 3199 3200 /* Configure MTL RX algorithms */ 3201 if (rx_queues_count > 1) 3202 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3203 priv->plat->rx_sched_algorithm); 3204 3205 /* Configure MTL TX algorithms */ 3206 if (tx_queues_count > 1) 3207 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3208 priv->plat->tx_sched_algorithm); 3209 3210 /* Configure CBS in AVB TX queues */ 3211 if (tx_queues_count > 1) 3212 stmmac_configure_cbs(priv); 3213 3214 /* Map RX MTL to DMA channels */ 3215 stmmac_rx_queue_dma_chan_map(priv); 3216 3217 /* Enable MAC RX Queues */ 3218 stmmac_mac_enable_rx_queues(priv); 3219 3220 /* Set RX priorities */ 3221 if (rx_queues_count > 1) 3222 stmmac_mac_config_rx_queues_prio(priv); 3223 3224 /* Set TX priorities */ 3225 if (tx_queues_count > 1) 3226 stmmac_mac_config_tx_queues_prio(priv); 3227 3228 /* Set RX routing */ 3229 if (rx_queues_count > 1) 3230 stmmac_mac_config_rx_queues_routing(priv); 3231 3232 /* Receive Side Scaling */ 3233 if (rx_queues_count > 1) 3234 stmmac_mac_config_rss(priv); 3235 } 3236 3237 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3238 { 3239 if (priv->dma_cap.asp) { 3240 netdev_info(priv->dev, "Enabling Safety Features\n"); 3241 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3242 priv->plat->safety_feat_cfg); 3243 } else { 3244 netdev_info(priv->dev, "No Safety Features support found\n"); 3245 } 3246 } 3247 3248 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3249 { 3250 char *name; 3251 3252 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3253 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3254 3255 name = priv->wq_name; 3256 sprintf(name, "%s-fpe", priv->dev->name); 3257 3258 priv->fpe_wq = create_singlethread_workqueue(name); 3259 if (!priv->fpe_wq) { 3260 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3261 3262 return -ENOMEM; 3263 } 3264 netdev_info(priv->dev, "FPE workqueue start"); 3265 3266 return 0; 3267 } 3268 3269 /** 3270 * stmmac_hw_setup - setup mac in a usable state. 3271 * @dev : pointer to the device structure. 3272 * @ptp_register: register PTP if set 3273 * Description: 3274 * this is the main function to setup the HW in a usable state because the 3275 * dma engine is reset, the core registers are configured (e.g. AXI, 3276 * Checksum features, timers). The DMA is ready to start receiving and 3277 * transmitting. 3278 * Return value: 3279 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3280 * file on failure. 3281 */ 3282 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3283 { 3284 struct stmmac_priv *priv = netdev_priv(dev); 3285 u32 rx_cnt = priv->plat->rx_queues_to_use; 3286 u32 tx_cnt = priv->plat->tx_queues_to_use; 3287 bool sph_en; 3288 u32 chan; 3289 int ret; 3290 3291 /* DMA initialization and SW reset */ 3292 ret = stmmac_init_dma_engine(priv); 3293 if (ret < 0) { 3294 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3295 __func__); 3296 return ret; 3297 } 3298 3299 /* Copy the MAC addr into the HW */ 3300 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3301 3302 /* PS and related bits will be programmed according to the speed */ 3303 if (priv->hw->pcs) { 3304 int speed = priv->plat->mac_port_sel_speed; 3305 3306 if ((speed == SPEED_10) || (speed == SPEED_100) || 3307 (speed == SPEED_1000)) { 3308 priv->hw->ps = speed; 3309 } else { 3310 dev_warn(priv->device, "invalid port speed\n"); 3311 priv->hw->ps = 0; 3312 } 3313 } 3314 3315 /* Initialize the MAC Core */ 3316 stmmac_core_init(priv, priv->hw, dev); 3317 3318 /* Initialize MTL*/ 3319 stmmac_mtl_configuration(priv); 3320 3321 /* Initialize Safety Features */ 3322 stmmac_safety_feat_configuration(priv); 3323 3324 ret = stmmac_rx_ipc(priv, priv->hw); 3325 if (!ret) { 3326 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3327 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3328 priv->hw->rx_csum = 0; 3329 } 3330 3331 /* Enable the MAC Rx/Tx */ 3332 stmmac_mac_set(priv, priv->ioaddr, true); 3333 3334 /* Set the HW DMA mode and the COE */ 3335 stmmac_dma_operation_mode(priv); 3336 3337 stmmac_mmc_setup(priv); 3338 3339 if (ptp_register) { 3340 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3341 if (ret < 0) 3342 netdev_warn(priv->dev, 3343 "failed to enable PTP reference clock: %pe\n", 3344 ERR_PTR(ret)); 3345 } 3346 3347 ret = stmmac_init_ptp(priv); 3348 if (ret == -EOPNOTSUPP) 3349 netdev_info(priv->dev, "PTP not supported by HW\n"); 3350 else if (ret) 3351 netdev_warn(priv->dev, "PTP init failed\n"); 3352 else if (ptp_register) 3353 stmmac_ptp_register(priv); 3354 3355 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3356 3357 /* Convert the timer from msec to usec */ 3358 if (!priv->tx_lpi_timer) 3359 priv->tx_lpi_timer = eee_timer * 1000; 3360 3361 if (priv->use_riwt) { 3362 u32 queue; 3363 3364 for (queue = 0; queue < rx_cnt; queue++) { 3365 if (!priv->rx_riwt[queue]) 3366 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3367 3368 stmmac_rx_watchdog(priv, priv->ioaddr, 3369 priv->rx_riwt[queue], queue); 3370 } 3371 } 3372 3373 if (priv->hw->pcs) 3374 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3375 3376 /* set TX and RX rings length */ 3377 stmmac_set_rings_length(priv); 3378 3379 /* Enable TSO */ 3380 if (priv->tso) { 3381 for (chan = 0; chan < tx_cnt; chan++) { 3382 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3383 3384 /* TSO and TBS cannot co-exist */ 3385 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3386 continue; 3387 3388 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3389 } 3390 } 3391 3392 /* Enable Split Header */ 3393 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3394 for (chan = 0; chan < rx_cnt; chan++) 3395 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3396 3397 3398 /* VLAN Tag Insertion */ 3399 if (priv->dma_cap.vlins) 3400 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3401 3402 /* TBS */ 3403 for (chan = 0; chan < tx_cnt; chan++) { 3404 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3405 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3406 3407 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3408 } 3409 3410 /* Configure real RX and TX queues */ 3411 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3412 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3413 3414 /* Start the ball rolling... */ 3415 stmmac_start_all_dma(priv); 3416 3417 if (priv->dma_cap.fpesel) { 3418 stmmac_fpe_start_wq(priv); 3419 3420 if (priv->plat->fpe_cfg->enable) 3421 stmmac_fpe_handshake(priv, true); 3422 } 3423 3424 return 0; 3425 } 3426 3427 static void stmmac_hw_teardown(struct net_device *dev) 3428 { 3429 struct stmmac_priv *priv = netdev_priv(dev); 3430 3431 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3432 } 3433 3434 static void stmmac_free_irq(struct net_device *dev, 3435 enum request_irq_err irq_err, int irq_idx) 3436 { 3437 struct stmmac_priv *priv = netdev_priv(dev); 3438 int j; 3439 3440 switch (irq_err) { 3441 case REQ_IRQ_ERR_ALL: 3442 irq_idx = priv->plat->tx_queues_to_use; 3443 fallthrough; 3444 case REQ_IRQ_ERR_TX: 3445 for (j = irq_idx - 1; j >= 0; j--) { 3446 if (priv->tx_irq[j] > 0) { 3447 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3448 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3449 } 3450 } 3451 irq_idx = priv->plat->rx_queues_to_use; 3452 fallthrough; 3453 case REQ_IRQ_ERR_RX: 3454 for (j = irq_idx - 1; j >= 0; j--) { 3455 if (priv->rx_irq[j] > 0) { 3456 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3457 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3458 } 3459 } 3460 3461 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3462 free_irq(priv->sfty_ue_irq, dev); 3463 fallthrough; 3464 case REQ_IRQ_ERR_SFTY_UE: 3465 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3466 free_irq(priv->sfty_ce_irq, dev); 3467 fallthrough; 3468 case REQ_IRQ_ERR_SFTY_CE: 3469 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3470 free_irq(priv->lpi_irq, dev); 3471 fallthrough; 3472 case REQ_IRQ_ERR_LPI: 3473 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3474 free_irq(priv->wol_irq, dev); 3475 fallthrough; 3476 case REQ_IRQ_ERR_WOL: 3477 free_irq(dev->irq, dev); 3478 fallthrough; 3479 case REQ_IRQ_ERR_MAC: 3480 case REQ_IRQ_ERR_NO: 3481 /* If MAC IRQ request error, no more IRQ to free */ 3482 break; 3483 } 3484 } 3485 3486 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3487 { 3488 struct stmmac_priv *priv = netdev_priv(dev); 3489 enum request_irq_err irq_err; 3490 cpumask_t cpu_mask; 3491 int irq_idx = 0; 3492 char *int_name; 3493 int ret; 3494 int i; 3495 3496 /* For common interrupt */ 3497 int_name = priv->int_name_mac; 3498 sprintf(int_name, "%s:%s", dev->name, "mac"); 3499 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3500 0, int_name, dev); 3501 if (unlikely(ret < 0)) { 3502 netdev_err(priv->dev, 3503 "%s: alloc mac MSI %d (error: %d)\n", 3504 __func__, dev->irq, ret); 3505 irq_err = REQ_IRQ_ERR_MAC; 3506 goto irq_error; 3507 } 3508 3509 /* Request the Wake IRQ in case of another line 3510 * is used for WoL 3511 */ 3512 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3513 int_name = priv->int_name_wol; 3514 sprintf(int_name, "%s:%s", dev->name, "wol"); 3515 ret = request_irq(priv->wol_irq, 3516 stmmac_mac_interrupt, 3517 0, int_name, dev); 3518 if (unlikely(ret < 0)) { 3519 netdev_err(priv->dev, 3520 "%s: alloc wol MSI %d (error: %d)\n", 3521 __func__, priv->wol_irq, ret); 3522 irq_err = REQ_IRQ_ERR_WOL; 3523 goto irq_error; 3524 } 3525 } 3526 3527 /* Request the LPI IRQ in case of another line 3528 * is used for LPI 3529 */ 3530 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3531 int_name = priv->int_name_lpi; 3532 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3533 ret = request_irq(priv->lpi_irq, 3534 stmmac_mac_interrupt, 3535 0, int_name, dev); 3536 if (unlikely(ret < 0)) { 3537 netdev_err(priv->dev, 3538 "%s: alloc lpi MSI %d (error: %d)\n", 3539 __func__, priv->lpi_irq, ret); 3540 irq_err = REQ_IRQ_ERR_LPI; 3541 goto irq_error; 3542 } 3543 } 3544 3545 /* Request the Safety Feature Correctible Error line in 3546 * case of another line is used 3547 */ 3548 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3549 int_name = priv->int_name_sfty_ce; 3550 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3551 ret = request_irq(priv->sfty_ce_irq, 3552 stmmac_safety_interrupt, 3553 0, int_name, dev); 3554 if (unlikely(ret < 0)) { 3555 netdev_err(priv->dev, 3556 "%s: alloc sfty ce MSI %d (error: %d)\n", 3557 __func__, priv->sfty_ce_irq, ret); 3558 irq_err = REQ_IRQ_ERR_SFTY_CE; 3559 goto irq_error; 3560 } 3561 } 3562 3563 /* Request the Safety Feature Uncorrectible Error line in 3564 * case of another line is used 3565 */ 3566 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3567 int_name = priv->int_name_sfty_ue; 3568 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3569 ret = request_irq(priv->sfty_ue_irq, 3570 stmmac_safety_interrupt, 3571 0, int_name, dev); 3572 if (unlikely(ret < 0)) { 3573 netdev_err(priv->dev, 3574 "%s: alloc sfty ue MSI %d (error: %d)\n", 3575 __func__, priv->sfty_ue_irq, ret); 3576 irq_err = REQ_IRQ_ERR_SFTY_UE; 3577 goto irq_error; 3578 } 3579 } 3580 3581 /* Request Rx MSI irq */ 3582 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3583 if (i >= MTL_MAX_RX_QUEUES) 3584 break; 3585 if (priv->rx_irq[i] == 0) 3586 continue; 3587 3588 int_name = priv->int_name_rx_irq[i]; 3589 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3590 ret = request_irq(priv->rx_irq[i], 3591 stmmac_msi_intr_rx, 3592 0, int_name, &priv->dma_conf.rx_queue[i]); 3593 if (unlikely(ret < 0)) { 3594 netdev_err(priv->dev, 3595 "%s: alloc rx-%d MSI %d (error: %d)\n", 3596 __func__, i, priv->rx_irq[i], ret); 3597 irq_err = REQ_IRQ_ERR_RX; 3598 irq_idx = i; 3599 goto irq_error; 3600 } 3601 cpumask_clear(&cpu_mask); 3602 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3603 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3604 } 3605 3606 /* Request Tx MSI irq */ 3607 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3608 if (i >= MTL_MAX_TX_QUEUES) 3609 break; 3610 if (priv->tx_irq[i] == 0) 3611 continue; 3612 3613 int_name = priv->int_name_tx_irq[i]; 3614 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3615 ret = request_irq(priv->tx_irq[i], 3616 stmmac_msi_intr_tx, 3617 0, int_name, &priv->dma_conf.tx_queue[i]); 3618 if (unlikely(ret < 0)) { 3619 netdev_err(priv->dev, 3620 "%s: alloc tx-%d MSI %d (error: %d)\n", 3621 __func__, i, priv->tx_irq[i], ret); 3622 irq_err = REQ_IRQ_ERR_TX; 3623 irq_idx = i; 3624 goto irq_error; 3625 } 3626 cpumask_clear(&cpu_mask); 3627 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3628 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3629 } 3630 3631 return 0; 3632 3633 irq_error: 3634 stmmac_free_irq(dev, irq_err, irq_idx); 3635 return ret; 3636 } 3637 3638 static int stmmac_request_irq_single(struct net_device *dev) 3639 { 3640 struct stmmac_priv *priv = netdev_priv(dev); 3641 enum request_irq_err irq_err; 3642 int ret; 3643 3644 ret = request_irq(dev->irq, stmmac_interrupt, 3645 IRQF_SHARED, dev->name, dev); 3646 if (unlikely(ret < 0)) { 3647 netdev_err(priv->dev, 3648 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3649 __func__, dev->irq, ret); 3650 irq_err = REQ_IRQ_ERR_MAC; 3651 goto irq_error; 3652 } 3653 3654 /* Request the Wake IRQ in case of another line 3655 * is used for WoL 3656 */ 3657 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3658 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3659 IRQF_SHARED, dev->name, dev); 3660 if (unlikely(ret < 0)) { 3661 netdev_err(priv->dev, 3662 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3663 __func__, priv->wol_irq, ret); 3664 irq_err = REQ_IRQ_ERR_WOL; 3665 goto irq_error; 3666 } 3667 } 3668 3669 /* Request the IRQ lines */ 3670 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3671 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3672 IRQF_SHARED, dev->name, dev); 3673 if (unlikely(ret < 0)) { 3674 netdev_err(priv->dev, 3675 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3676 __func__, priv->lpi_irq, ret); 3677 irq_err = REQ_IRQ_ERR_LPI; 3678 goto irq_error; 3679 } 3680 } 3681 3682 return 0; 3683 3684 irq_error: 3685 stmmac_free_irq(dev, irq_err, 0); 3686 return ret; 3687 } 3688 3689 static int stmmac_request_irq(struct net_device *dev) 3690 { 3691 struct stmmac_priv *priv = netdev_priv(dev); 3692 int ret; 3693 3694 /* Request the IRQ lines */ 3695 if (priv->plat->multi_msi_en) 3696 ret = stmmac_request_irq_multi_msi(dev); 3697 else 3698 ret = stmmac_request_irq_single(dev); 3699 3700 return ret; 3701 } 3702 3703 /** 3704 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3705 * @priv: driver private structure 3706 * @mtu: MTU to setup the dma queue and buf with 3707 * Description: Allocate and generate a dma_conf based on the provided MTU. 3708 * Allocate the Tx/Rx DMA queue and init them. 3709 * Return value: 3710 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3711 */ 3712 static struct stmmac_dma_conf * 3713 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3714 { 3715 struct stmmac_dma_conf *dma_conf; 3716 int chan, bfsize, ret; 3717 3718 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3719 if (!dma_conf) { 3720 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3721 __func__); 3722 return ERR_PTR(-ENOMEM); 3723 } 3724 3725 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3726 if (bfsize < 0) 3727 bfsize = 0; 3728 3729 if (bfsize < BUF_SIZE_16KiB) 3730 bfsize = stmmac_set_bfsize(mtu, 0); 3731 3732 dma_conf->dma_buf_sz = bfsize; 3733 /* Chose the tx/rx size from the already defined one in the 3734 * priv struct. (if defined) 3735 */ 3736 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3737 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3738 3739 if (!dma_conf->dma_tx_size) 3740 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3741 if (!dma_conf->dma_rx_size) 3742 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3743 3744 /* Earlier check for TBS */ 3745 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3746 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3747 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3748 3749 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3750 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3751 } 3752 3753 ret = alloc_dma_desc_resources(priv, dma_conf); 3754 if (ret < 0) { 3755 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3756 __func__); 3757 goto alloc_error; 3758 } 3759 3760 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3761 if (ret < 0) { 3762 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3763 __func__); 3764 goto init_error; 3765 } 3766 3767 return dma_conf; 3768 3769 init_error: 3770 free_dma_desc_resources(priv, dma_conf); 3771 alloc_error: 3772 kfree(dma_conf); 3773 return ERR_PTR(ret); 3774 } 3775 3776 /** 3777 * __stmmac_open - open entry point of the driver 3778 * @dev : pointer to the device structure. 3779 * @dma_conf : structure to take the dma data 3780 * Description: 3781 * This function is the open entry point of the driver. 3782 * Return value: 3783 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3784 * file on failure. 3785 */ 3786 static int __stmmac_open(struct net_device *dev, 3787 struct stmmac_dma_conf *dma_conf) 3788 { 3789 struct stmmac_priv *priv = netdev_priv(dev); 3790 int mode = priv->plat->phy_interface; 3791 u32 chan; 3792 int ret; 3793 3794 ret = pm_runtime_resume_and_get(priv->device); 3795 if (ret < 0) 3796 return ret; 3797 3798 if (priv->hw->pcs != STMMAC_PCS_TBI && 3799 priv->hw->pcs != STMMAC_PCS_RTBI && 3800 (!priv->hw->xpcs || 3801 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3802 ret = stmmac_init_phy(dev); 3803 if (ret) { 3804 netdev_err(priv->dev, 3805 "%s: Cannot attach to PHY (error: %d)\n", 3806 __func__, ret); 3807 goto init_phy_error; 3808 } 3809 } 3810 3811 /* Extra statistics */ 3812 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3813 priv->xstats.threshold = tc; 3814 3815 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3816 3817 buf_sz = dma_conf->dma_buf_sz; 3818 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3819 3820 stmmac_reset_queues_param(priv); 3821 3822 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 3823 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3824 if (ret < 0) { 3825 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3826 __func__); 3827 goto init_error; 3828 } 3829 } 3830 3831 ret = stmmac_hw_setup(dev, true); 3832 if (ret < 0) { 3833 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3834 goto init_error; 3835 } 3836 3837 stmmac_init_coalesce(priv); 3838 3839 phylink_start(priv->phylink); 3840 /* We may have called phylink_speed_down before */ 3841 phylink_speed_up(priv->phylink); 3842 3843 ret = stmmac_request_irq(dev); 3844 if (ret) 3845 goto irq_error; 3846 3847 stmmac_enable_all_queues(priv); 3848 netif_tx_start_all_queues(priv->dev); 3849 stmmac_enable_all_dma_irq(priv); 3850 3851 return 0; 3852 3853 irq_error: 3854 phylink_stop(priv->phylink); 3855 3856 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3857 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3858 3859 stmmac_hw_teardown(dev); 3860 init_error: 3861 free_dma_desc_resources(priv, &priv->dma_conf); 3862 phylink_disconnect_phy(priv->phylink); 3863 init_phy_error: 3864 pm_runtime_put(priv->device); 3865 return ret; 3866 } 3867 3868 static int stmmac_open(struct net_device *dev) 3869 { 3870 struct stmmac_priv *priv = netdev_priv(dev); 3871 struct stmmac_dma_conf *dma_conf; 3872 int ret; 3873 3874 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3875 if (IS_ERR(dma_conf)) 3876 return PTR_ERR(dma_conf); 3877 3878 ret = __stmmac_open(dev, dma_conf); 3879 kfree(dma_conf); 3880 return ret; 3881 } 3882 3883 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3884 { 3885 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3886 3887 if (priv->fpe_wq) 3888 destroy_workqueue(priv->fpe_wq); 3889 3890 netdev_info(priv->dev, "FPE workqueue stop"); 3891 } 3892 3893 /** 3894 * stmmac_release - close entry point of the driver 3895 * @dev : device pointer. 3896 * Description: 3897 * This is the stop entry point of the driver. 3898 */ 3899 static int stmmac_release(struct net_device *dev) 3900 { 3901 struct stmmac_priv *priv = netdev_priv(dev); 3902 u32 chan; 3903 3904 if (device_may_wakeup(priv->device)) 3905 phylink_speed_down(priv->phylink, false); 3906 /* Stop and disconnect the PHY */ 3907 phylink_stop(priv->phylink); 3908 phylink_disconnect_phy(priv->phylink); 3909 3910 stmmac_disable_all_queues(priv); 3911 3912 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3913 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3914 3915 netif_tx_disable(dev); 3916 3917 /* Free the IRQ lines */ 3918 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3919 3920 if (priv->eee_enabled) { 3921 priv->tx_path_in_lpi_mode = false; 3922 del_timer_sync(&priv->eee_ctrl_timer); 3923 } 3924 3925 /* Stop TX/RX DMA and clear the descriptors */ 3926 stmmac_stop_all_dma(priv); 3927 3928 /* Release and free the Rx/Tx resources */ 3929 free_dma_desc_resources(priv, &priv->dma_conf); 3930 3931 /* Disable the MAC Rx/Tx */ 3932 stmmac_mac_set(priv, priv->ioaddr, false); 3933 3934 /* Powerdown Serdes if there is */ 3935 if (priv->plat->serdes_powerdown) 3936 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3937 3938 netif_carrier_off(dev); 3939 3940 stmmac_release_ptp(priv); 3941 3942 pm_runtime_put(priv->device); 3943 3944 if (priv->dma_cap.fpesel) 3945 stmmac_fpe_stop_wq(priv); 3946 3947 return 0; 3948 } 3949 3950 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3951 struct stmmac_tx_queue *tx_q) 3952 { 3953 u16 tag = 0x0, inner_tag = 0x0; 3954 u32 inner_type = 0x0; 3955 struct dma_desc *p; 3956 3957 if (!priv->dma_cap.vlins) 3958 return false; 3959 if (!skb_vlan_tag_present(skb)) 3960 return false; 3961 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3962 inner_tag = skb_vlan_tag_get(skb); 3963 inner_type = STMMAC_VLAN_INSERT; 3964 } 3965 3966 tag = skb_vlan_tag_get(skb); 3967 3968 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3969 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3970 else 3971 p = &tx_q->dma_tx[tx_q->cur_tx]; 3972 3973 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3974 return false; 3975 3976 stmmac_set_tx_owner(priv, p); 3977 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3978 return true; 3979 } 3980 3981 /** 3982 * stmmac_tso_allocator - close entry point of the driver 3983 * @priv: driver private structure 3984 * @des: buffer start address 3985 * @total_len: total length to fill in descriptors 3986 * @last_segment: condition for the last descriptor 3987 * @queue: TX queue index 3988 * Description: 3989 * This function fills descriptor and request new descriptors according to 3990 * buffer length to fill 3991 */ 3992 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3993 int total_len, bool last_segment, u32 queue) 3994 { 3995 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3996 struct dma_desc *desc; 3997 u32 buff_size; 3998 int tmp_len; 3999 4000 tmp_len = total_len; 4001 4002 while (tmp_len > 0) { 4003 dma_addr_t curr_addr; 4004 4005 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4006 priv->dma_conf.dma_tx_size); 4007 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4008 4009 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4010 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4011 else 4012 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4013 4014 curr_addr = des + (total_len - tmp_len); 4015 if (priv->dma_cap.addr64 <= 32) 4016 desc->des0 = cpu_to_le32(curr_addr); 4017 else 4018 stmmac_set_desc_addr(priv, desc, curr_addr); 4019 4020 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4021 TSO_MAX_BUFF_SIZE : tmp_len; 4022 4023 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4024 0, 1, 4025 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4026 0, 0); 4027 4028 tmp_len -= TSO_MAX_BUFF_SIZE; 4029 } 4030 } 4031 4032 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4033 { 4034 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4035 int desc_size; 4036 4037 if (likely(priv->extend_desc)) 4038 desc_size = sizeof(struct dma_extended_desc); 4039 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4040 desc_size = sizeof(struct dma_edesc); 4041 else 4042 desc_size = sizeof(struct dma_desc); 4043 4044 /* The own bit must be the latest setting done when prepare the 4045 * descriptor and then barrier is needed to make sure that 4046 * all is coherent before granting the DMA engine. 4047 */ 4048 wmb(); 4049 4050 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4051 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4052 } 4053 4054 /** 4055 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4056 * @skb : the socket buffer 4057 * @dev : device pointer 4058 * Description: this is the transmit function that is called on TSO frames 4059 * (support available on GMAC4 and newer chips). 4060 * Diagram below show the ring programming in case of TSO frames: 4061 * 4062 * First Descriptor 4063 * -------- 4064 * | DES0 |---> buffer1 = L2/L3/L4 header 4065 * | DES1 |---> TCP Payload (can continue on next descr...) 4066 * | DES2 |---> buffer 1 and 2 len 4067 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4068 * -------- 4069 * | 4070 * ... 4071 * | 4072 * -------- 4073 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4074 * | DES1 | --| 4075 * | DES2 | --> buffer 1 and 2 len 4076 * | DES3 | 4077 * -------- 4078 * 4079 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4080 */ 4081 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4082 { 4083 struct dma_desc *desc, *first, *mss_desc = NULL; 4084 struct stmmac_priv *priv = netdev_priv(dev); 4085 int nfrags = skb_shinfo(skb)->nr_frags; 4086 u32 queue = skb_get_queue_mapping(skb); 4087 unsigned int first_entry, tx_packets; 4088 int tmp_pay_len = 0, first_tx; 4089 struct stmmac_tx_queue *tx_q; 4090 bool has_vlan, set_ic; 4091 u8 proto_hdr_len, hdr; 4092 u32 pay_len, mss; 4093 dma_addr_t des; 4094 int i; 4095 4096 tx_q = &priv->dma_conf.tx_queue[queue]; 4097 first_tx = tx_q->cur_tx; 4098 4099 /* Compute header lengths */ 4100 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4101 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4102 hdr = sizeof(struct udphdr); 4103 } else { 4104 proto_hdr_len = skb_tcp_all_headers(skb); 4105 hdr = tcp_hdrlen(skb); 4106 } 4107 4108 /* Desc availability based on threshold should be enough safe */ 4109 if (unlikely(stmmac_tx_avail(priv, queue) < 4110 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4111 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4112 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4113 queue)); 4114 /* This is a hard error, log it. */ 4115 netdev_err(priv->dev, 4116 "%s: Tx Ring full when queue awake\n", 4117 __func__); 4118 } 4119 return NETDEV_TX_BUSY; 4120 } 4121 4122 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4123 4124 mss = skb_shinfo(skb)->gso_size; 4125 4126 /* set new MSS value if needed */ 4127 if (mss != tx_q->mss) { 4128 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4129 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4130 else 4131 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4132 4133 stmmac_set_mss(priv, mss_desc, mss); 4134 tx_q->mss = mss; 4135 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4136 priv->dma_conf.dma_tx_size); 4137 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4138 } 4139 4140 if (netif_msg_tx_queued(priv)) { 4141 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4142 __func__, hdr, proto_hdr_len, pay_len, mss); 4143 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4144 skb->data_len); 4145 } 4146 4147 /* Check if VLAN can be inserted by HW */ 4148 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4149 4150 first_entry = tx_q->cur_tx; 4151 WARN_ON(tx_q->tx_skbuff[first_entry]); 4152 4153 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4154 desc = &tx_q->dma_entx[first_entry].basic; 4155 else 4156 desc = &tx_q->dma_tx[first_entry]; 4157 first = desc; 4158 4159 if (has_vlan) 4160 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4161 4162 /* first descriptor: fill Headers on Buf1 */ 4163 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4164 DMA_TO_DEVICE); 4165 if (dma_mapping_error(priv->device, des)) 4166 goto dma_map_err; 4167 4168 tx_q->tx_skbuff_dma[first_entry].buf = des; 4169 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4170 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4171 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4172 4173 if (priv->dma_cap.addr64 <= 32) { 4174 first->des0 = cpu_to_le32(des); 4175 4176 /* Fill start of payload in buff2 of first descriptor */ 4177 if (pay_len) 4178 first->des1 = cpu_to_le32(des + proto_hdr_len); 4179 4180 /* If needed take extra descriptors to fill the remaining payload */ 4181 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4182 } else { 4183 stmmac_set_desc_addr(priv, first, des); 4184 tmp_pay_len = pay_len; 4185 des += proto_hdr_len; 4186 pay_len = 0; 4187 } 4188 4189 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4190 4191 /* Prepare fragments */ 4192 for (i = 0; i < nfrags; i++) { 4193 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4194 4195 des = skb_frag_dma_map(priv->device, frag, 0, 4196 skb_frag_size(frag), 4197 DMA_TO_DEVICE); 4198 if (dma_mapping_error(priv->device, des)) 4199 goto dma_map_err; 4200 4201 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4202 (i == nfrags - 1), queue); 4203 4204 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4205 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4206 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4207 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4208 } 4209 4210 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4211 4212 /* Only the last descriptor gets to point to the skb. */ 4213 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4214 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4215 4216 /* Manage tx mitigation */ 4217 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4218 tx_q->tx_count_frames += tx_packets; 4219 4220 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4221 set_ic = true; 4222 else if (!priv->tx_coal_frames[queue]) 4223 set_ic = false; 4224 else if (tx_packets > priv->tx_coal_frames[queue]) 4225 set_ic = true; 4226 else if ((tx_q->tx_count_frames % 4227 priv->tx_coal_frames[queue]) < tx_packets) 4228 set_ic = true; 4229 else 4230 set_ic = false; 4231 4232 if (set_ic) { 4233 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4234 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4235 else 4236 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4237 4238 tx_q->tx_count_frames = 0; 4239 stmmac_set_tx_ic(priv, desc); 4240 priv->xstats.tx_set_ic_bit++; 4241 } 4242 4243 /* We've used all descriptors we need for this skb, however, 4244 * advance cur_tx so that it references a fresh descriptor. 4245 * ndo_start_xmit will fill this descriptor the next time it's 4246 * called and stmmac_tx_clean may clean up to this descriptor. 4247 */ 4248 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4249 4250 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4251 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4252 __func__); 4253 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4254 } 4255 4256 dev->stats.tx_bytes += skb->len; 4257 priv->xstats.tx_tso_frames++; 4258 priv->xstats.tx_tso_nfrags += nfrags; 4259 4260 if (priv->sarc_type) 4261 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4262 4263 skb_tx_timestamp(skb); 4264 4265 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4266 priv->hwts_tx_en)) { 4267 /* declare that device is doing timestamping */ 4268 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4269 stmmac_enable_tx_timestamp(priv, first); 4270 } 4271 4272 /* Complete the first descriptor before granting the DMA */ 4273 stmmac_prepare_tso_tx_desc(priv, first, 1, 4274 proto_hdr_len, 4275 pay_len, 4276 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4277 hdr / 4, (skb->len - proto_hdr_len)); 4278 4279 /* If context desc is used to change MSS */ 4280 if (mss_desc) { 4281 /* Make sure that first descriptor has been completely 4282 * written, including its own bit. This is because MSS is 4283 * actually before first descriptor, so we need to make 4284 * sure that MSS's own bit is the last thing written. 4285 */ 4286 dma_wmb(); 4287 stmmac_set_tx_owner(priv, mss_desc); 4288 } 4289 4290 if (netif_msg_pktdata(priv)) { 4291 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4292 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4293 tx_q->cur_tx, first, nfrags); 4294 pr_info(">>> frame to be transmitted: "); 4295 print_pkt(skb->data, skb_headlen(skb)); 4296 } 4297 4298 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4299 4300 stmmac_flush_tx_descriptors(priv, queue); 4301 stmmac_tx_timer_arm(priv, queue); 4302 4303 return NETDEV_TX_OK; 4304 4305 dma_map_err: 4306 dev_err(priv->device, "Tx dma map failed\n"); 4307 dev_kfree_skb(skb); 4308 priv->dev->stats.tx_dropped++; 4309 return NETDEV_TX_OK; 4310 } 4311 4312 /** 4313 * stmmac_xmit - Tx entry point of the driver 4314 * @skb : the socket buffer 4315 * @dev : device pointer 4316 * Description : this is the tx entry point of the driver. 4317 * It programs the chain or the ring and supports oversized frames 4318 * and SG feature. 4319 */ 4320 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4321 { 4322 unsigned int first_entry, tx_packets, enh_desc; 4323 struct stmmac_priv *priv = netdev_priv(dev); 4324 unsigned int nopaged_len = skb_headlen(skb); 4325 int i, csum_insertion = 0, is_jumbo = 0; 4326 u32 queue = skb_get_queue_mapping(skb); 4327 int nfrags = skb_shinfo(skb)->nr_frags; 4328 int gso = skb_shinfo(skb)->gso_type; 4329 struct dma_edesc *tbs_desc = NULL; 4330 struct dma_desc *desc, *first; 4331 struct stmmac_tx_queue *tx_q; 4332 bool has_vlan, set_ic; 4333 int entry, first_tx; 4334 dma_addr_t des; 4335 4336 tx_q = &priv->dma_conf.tx_queue[queue]; 4337 first_tx = tx_q->cur_tx; 4338 4339 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4340 stmmac_disable_eee_mode(priv); 4341 4342 /* Manage oversized TCP frames for GMAC4 device */ 4343 if (skb_is_gso(skb) && priv->tso) { 4344 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4345 return stmmac_tso_xmit(skb, dev); 4346 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4347 return stmmac_tso_xmit(skb, dev); 4348 } 4349 4350 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4351 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4352 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4353 queue)); 4354 /* This is a hard error, log it. */ 4355 netdev_err(priv->dev, 4356 "%s: Tx Ring full when queue awake\n", 4357 __func__); 4358 } 4359 return NETDEV_TX_BUSY; 4360 } 4361 4362 /* Check if VLAN can be inserted by HW */ 4363 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4364 4365 entry = tx_q->cur_tx; 4366 first_entry = entry; 4367 WARN_ON(tx_q->tx_skbuff[first_entry]); 4368 4369 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4370 4371 if (likely(priv->extend_desc)) 4372 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4373 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4374 desc = &tx_q->dma_entx[entry].basic; 4375 else 4376 desc = tx_q->dma_tx + entry; 4377 4378 first = desc; 4379 4380 if (has_vlan) 4381 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4382 4383 enh_desc = priv->plat->enh_desc; 4384 /* To program the descriptors according to the size of the frame */ 4385 if (enh_desc) 4386 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4387 4388 if (unlikely(is_jumbo)) { 4389 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4390 if (unlikely(entry < 0) && (entry != -EINVAL)) 4391 goto dma_map_err; 4392 } 4393 4394 for (i = 0; i < nfrags; i++) { 4395 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4396 int len = skb_frag_size(frag); 4397 bool last_segment = (i == (nfrags - 1)); 4398 4399 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4400 WARN_ON(tx_q->tx_skbuff[entry]); 4401 4402 if (likely(priv->extend_desc)) 4403 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4404 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4405 desc = &tx_q->dma_entx[entry].basic; 4406 else 4407 desc = tx_q->dma_tx + entry; 4408 4409 des = skb_frag_dma_map(priv->device, frag, 0, len, 4410 DMA_TO_DEVICE); 4411 if (dma_mapping_error(priv->device, des)) 4412 goto dma_map_err; /* should reuse desc w/o issues */ 4413 4414 tx_q->tx_skbuff_dma[entry].buf = des; 4415 4416 stmmac_set_desc_addr(priv, desc, des); 4417 4418 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4419 tx_q->tx_skbuff_dma[entry].len = len; 4420 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4421 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4422 4423 /* Prepare the descriptor and set the own bit too */ 4424 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4425 priv->mode, 1, last_segment, skb->len); 4426 } 4427 4428 /* Only the last descriptor gets to point to the skb. */ 4429 tx_q->tx_skbuff[entry] = skb; 4430 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4431 4432 /* According to the coalesce parameter the IC bit for the latest 4433 * segment is reset and the timer re-started to clean the tx status. 4434 * This approach takes care about the fragments: desc is the first 4435 * element in case of no SG. 4436 */ 4437 tx_packets = (entry + 1) - first_tx; 4438 tx_q->tx_count_frames += tx_packets; 4439 4440 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4441 set_ic = true; 4442 else if (!priv->tx_coal_frames[queue]) 4443 set_ic = false; 4444 else if (tx_packets > priv->tx_coal_frames[queue]) 4445 set_ic = true; 4446 else if ((tx_q->tx_count_frames % 4447 priv->tx_coal_frames[queue]) < tx_packets) 4448 set_ic = true; 4449 else 4450 set_ic = false; 4451 4452 if (set_ic) { 4453 if (likely(priv->extend_desc)) 4454 desc = &tx_q->dma_etx[entry].basic; 4455 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4456 desc = &tx_q->dma_entx[entry].basic; 4457 else 4458 desc = &tx_q->dma_tx[entry]; 4459 4460 tx_q->tx_count_frames = 0; 4461 stmmac_set_tx_ic(priv, desc); 4462 priv->xstats.tx_set_ic_bit++; 4463 } 4464 4465 /* We've used all descriptors we need for this skb, however, 4466 * advance cur_tx so that it references a fresh descriptor. 4467 * ndo_start_xmit will fill this descriptor the next time it's 4468 * called and stmmac_tx_clean may clean up to this descriptor. 4469 */ 4470 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4471 tx_q->cur_tx = entry; 4472 4473 if (netif_msg_pktdata(priv)) { 4474 netdev_dbg(priv->dev, 4475 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4476 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4477 entry, first, nfrags); 4478 4479 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4480 print_pkt(skb->data, skb->len); 4481 } 4482 4483 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4484 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4485 __func__); 4486 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4487 } 4488 4489 dev->stats.tx_bytes += skb->len; 4490 4491 if (priv->sarc_type) 4492 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4493 4494 skb_tx_timestamp(skb); 4495 4496 /* Ready to fill the first descriptor and set the OWN bit w/o any 4497 * problems because all the descriptors are actually ready to be 4498 * passed to the DMA engine. 4499 */ 4500 if (likely(!is_jumbo)) { 4501 bool last_segment = (nfrags == 0); 4502 4503 des = dma_map_single(priv->device, skb->data, 4504 nopaged_len, DMA_TO_DEVICE); 4505 if (dma_mapping_error(priv->device, des)) 4506 goto dma_map_err; 4507 4508 tx_q->tx_skbuff_dma[first_entry].buf = des; 4509 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4510 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4511 4512 stmmac_set_desc_addr(priv, first, des); 4513 4514 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4515 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4516 4517 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4518 priv->hwts_tx_en)) { 4519 /* declare that device is doing timestamping */ 4520 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4521 stmmac_enable_tx_timestamp(priv, first); 4522 } 4523 4524 /* Prepare the first descriptor setting the OWN bit too */ 4525 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4526 csum_insertion, priv->mode, 0, last_segment, 4527 skb->len); 4528 } 4529 4530 if (tx_q->tbs & STMMAC_TBS_EN) { 4531 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4532 4533 tbs_desc = &tx_q->dma_entx[first_entry]; 4534 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4535 } 4536 4537 stmmac_set_tx_owner(priv, first); 4538 4539 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4540 4541 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4542 4543 stmmac_flush_tx_descriptors(priv, queue); 4544 stmmac_tx_timer_arm(priv, queue); 4545 4546 return NETDEV_TX_OK; 4547 4548 dma_map_err: 4549 netdev_err(priv->dev, "Tx DMA map failed\n"); 4550 dev_kfree_skb(skb); 4551 priv->dev->stats.tx_dropped++; 4552 return NETDEV_TX_OK; 4553 } 4554 4555 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4556 { 4557 struct vlan_ethhdr *veth; 4558 __be16 vlan_proto; 4559 u16 vlanid; 4560 4561 veth = (struct vlan_ethhdr *)skb->data; 4562 vlan_proto = veth->h_vlan_proto; 4563 4564 if ((vlan_proto == htons(ETH_P_8021Q) && 4565 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4566 (vlan_proto == htons(ETH_P_8021AD) && 4567 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4568 /* pop the vlan tag */ 4569 vlanid = ntohs(veth->h_vlan_TCI); 4570 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4571 skb_pull(skb, VLAN_HLEN); 4572 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4573 } 4574 } 4575 4576 /** 4577 * stmmac_rx_refill - refill used skb preallocated buffers 4578 * @priv: driver private structure 4579 * @queue: RX queue index 4580 * Description : this is to reallocate the skb for the reception process 4581 * that is based on zero-copy. 4582 */ 4583 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4584 { 4585 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4586 int dirty = stmmac_rx_dirty(priv, queue); 4587 unsigned int entry = rx_q->dirty_rx; 4588 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4589 4590 if (priv->dma_cap.addr64 <= 32) 4591 gfp |= GFP_DMA32; 4592 4593 while (dirty-- > 0) { 4594 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4595 struct dma_desc *p; 4596 bool use_rx_wd; 4597 4598 if (priv->extend_desc) 4599 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4600 else 4601 p = rx_q->dma_rx + entry; 4602 4603 if (!buf->page) { 4604 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4605 if (!buf->page) 4606 break; 4607 } 4608 4609 if (priv->sph && !buf->sec_page) { 4610 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4611 if (!buf->sec_page) 4612 break; 4613 4614 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4615 } 4616 4617 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4618 4619 stmmac_set_desc_addr(priv, p, buf->addr); 4620 if (priv->sph) 4621 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4622 else 4623 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4624 stmmac_refill_desc3(priv, rx_q, p); 4625 4626 rx_q->rx_count_frames++; 4627 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4628 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4629 rx_q->rx_count_frames = 0; 4630 4631 use_rx_wd = !priv->rx_coal_frames[queue]; 4632 use_rx_wd |= rx_q->rx_count_frames > 0; 4633 if (!priv->use_riwt) 4634 use_rx_wd = false; 4635 4636 dma_wmb(); 4637 stmmac_set_rx_owner(priv, p, use_rx_wd); 4638 4639 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4640 } 4641 rx_q->dirty_rx = entry; 4642 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4643 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4644 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4645 } 4646 4647 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4648 struct dma_desc *p, 4649 int status, unsigned int len) 4650 { 4651 unsigned int plen = 0, hlen = 0; 4652 int coe = priv->hw->rx_csum; 4653 4654 /* Not first descriptor, buffer is always zero */ 4655 if (priv->sph && len) 4656 return 0; 4657 4658 /* First descriptor, get split header length */ 4659 stmmac_get_rx_header_len(priv, p, &hlen); 4660 if (priv->sph && hlen) { 4661 priv->xstats.rx_split_hdr_pkt_n++; 4662 return hlen; 4663 } 4664 4665 /* First descriptor, not last descriptor and not split header */ 4666 if (status & rx_not_ls) 4667 return priv->dma_conf.dma_buf_sz; 4668 4669 plen = stmmac_get_rx_frame_len(priv, p, coe); 4670 4671 /* First descriptor and last descriptor and not split header */ 4672 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4673 } 4674 4675 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4676 struct dma_desc *p, 4677 int status, unsigned int len) 4678 { 4679 int coe = priv->hw->rx_csum; 4680 unsigned int plen = 0; 4681 4682 /* Not split header, buffer is not available */ 4683 if (!priv->sph) 4684 return 0; 4685 4686 /* Not last descriptor */ 4687 if (status & rx_not_ls) 4688 return priv->dma_conf.dma_buf_sz; 4689 4690 plen = stmmac_get_rx_frame_len(priv, p, coe); 4691 4692 /* Last descriptor */ 4693 return plen - len; 4694 } 4695 4696 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4697 struct xdp_frame *xdpf, bool dma_map) 4698 { 4699 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4700 unsigned int entry = tx_q->cur_tx; 4701 struct dma_desc *tx_desc; 4702 dma_addr_t dma_addr; 4703 bool set_ic; 4704 4705 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4706 return STMMAC_XDP_CONSUMED; 4707 4708 if (likely(priv->extend_desc)) 4709 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4710 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4711 tx_desc = &tx_q->dma_entx[entry].basic; 4712 else 4713 tx_desc = tx_q->dma_tx + entry; 4714 4715 if (dma_map) { 4716 dma_addr = dma_map_single(priv->device, xdpf->data, 4717 xdpf->len, DMA_TO_DEVICE); 4718 if (dma_mapping_error(priv->device, dma_addr)) 4719 return STMMAC_XDP_CONSUMED; 4720 4721 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4722 } else { 4723 struct page *page = virt_to_page(xdpf->data); 4724 4725 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4726 xdpf->headroom; 4727 dma_sync_single_for_device(priv->device, dma_addr, 4728 xdpf->len, DMA_BIDIRECTIONAL); 4729 4730 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4731 } 4732 4733 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4734 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4735 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4736 tx_q->tx_skbuff_dma[entry].last_segment = true; 4737 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4738 4739 tx_q->xdpf[entry] = xdpf; 4740 4741 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4742 4743 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4744 true, priv->mode, true, true, 4745 xdpf->len); 4746 4747 tx_q->tx_count_frames++; 4748 4749 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4750 set_ic = true; 4751 else 4752 set_ic = false; 4753 4754 if (set_ic) { 4755 tx_q->tx_count_frames = 0; 4756 stmmac_set_tx_ic(priv, tx_desc); 4757 priv->xstats.tx_set_ic_bit++; 4758 } 4759 4760 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4761 4762 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4763 tx_q->cur_tx = entry; 4764 4765 return STMMAC_XDP_TX; 4766 } 4767 4768 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4769 int cpu) 4770 { 4771 int index = cpu; 4772 4773 if (unlikely(index < 0)) 4774 index = 0; 4775 4776 while (index >= priv->plat->tx_queues_to_use) 4777 index -= priv->plat->tx_queues_to_use; 4778 4779 return index; 4780 } 4781 4782 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4783 struct xdp_buff *xdp) 4784 { 4785 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4786 int cpu = smp_processor_id(); 4787 struct netdev_queue *nq; 4788 int queue; 4789 int res; 4790 4791 if (unlikely(!xdpf)) 4792 return STMMAC_XDP_CONSUMED; 4793 4794 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4795 nq = netdev_get_tx_queue(priv->dev, queue); 4796 4797 __netif_tx_lock(nq, cpu); 4798 /* Avoids TX time-out as we are sharing with slow path */ 4799 txq_trans_cond_update(nq); 4800 4801 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4802 if (res == STMMAC_XDP_TX) 4803 stmmac_flush_tx_descriptors(priv, queue); 4804 4805 __netif_tx_unlock(nq); 4806 4807 return res; 4808 } 4809 4810 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4811 struct bpf_prog *prog, 4812 struct xdp_buff *xdp) 4813 { 4814 u32 act; 4815 int res; 4816 4817 act = bpf_prog_run_xdp(prog, xdp); 4818 switch (act) { 4819 case XDP_PASS: 4820 res = STMMAC_XDP_PASS; 4821 break; 4822 case XDP_TX: 4823 res = stmmac_xdp_xmit_back(priv, xdp); 4824 break; 4825 case XDP_REDIRECT: 4826 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4827 res = STMMAC_XDP_CONSUMED; 4828 else 4829 res = STMMAC_XDP_REDIRECT; 4830 break; 4831 default: 4832 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4833 fallthrough; 4834 case XDP_ABORTED: 4835 trace_xdp_exception(priv->dev, prog, act); 4836 fallthrough; 4837 case XDP_DROP: 4838 res = STMMAC_XDP_CONSUMED; 4839 break; 4840 } 4841 4842 return res; 4843 } 4844 4845 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4846 struct xdp_buff *xdp) 4847 { 4848 struct bpf_prog *prog; 4849 int res; 4850 4851 prog = READ_ONCE(priv->xdp_prog); 4852 if (!prog) { 4853 res = STMMAC_XDP_PASS; 4854 goto out; 4855 } 4856 4857 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4858 out: 4859 return ERR_PTR(-res); 4860 } 4861 4862 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4863 int xdp_status) 4864 { 4865 int cpu = smp_processor_id(); 4866 int queue; 4867 4868 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4869 4870 if (xdp_status & STMMAC_XDP_TX) 4871 stmmac_tx_timer_arm(priv, queue); 4872 4873 if (xdp_status & STMMAC_XDP_REDIRECT) 4874 xdp_do_flush(); 4875 } 4876 4877 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4878 struct xdp_buff *xdp) 4879 { 4880 unsigned int metasize = xdp->data - xdp->data_meta; 4881 unsigned int datasize = xdp->data_end - xdp->data; 4882 struct sk_buff *skb; 4883 4884 skb = __napi_alloc_skb(&ch->rxtx_napi, 4885 xdp->data_end - xdp->data_hard_start, 4886 GFP_ATOMIC | __GFP_NOWARN); 4887 if (unlikely(!skb)) 4888 return NULL; 4889 4890 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4891 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4892 if (metasize) 4893 skb_metadata_set(skb, metasize); 4894 4895 return skb; 4896 } 4897 4898 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4899 struct dma_desc *p, struct dma_desc *np, 4900 struct xdp_buff *xdp) 4901 { 4902 struct stmmac_channel *ch = &priv->channel[queue]; 4903 unsigned int len = xdp->data_end - xdp->data; 4904 enum pkt_hash_types hash_type; 4905 int coe = priv->hw->rx_csum; 4906 struct sk_buff *skb; 4907 u32 hash; 4908 4909 skb = stmmac_construct_skb_zc(ch, xdp); 4910 if (!skb) { 4911 priv->dev->stats.rx_dropped++; 4912 return; 4913 } 4914 4915 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4916 stmmac_rx_vlan(priv->dev, skb); 4917 skb->protocol = eth_type_trans(skb, priv->dev); 4918 4919 if (unlikely(!coe)) 4920 skb_checksum_none_assert(skb); 4921 else 4922 skb->ip_summed = CHECKSUM_UNNECESSARY; 4923 4924 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4925 skb_set_hash(skb, hash, hash_type); 4926 4927 skb_record_rx_queue(skb, queue); 4928 napi_gro_receive(&ch->rxtx_napi, skb); 4929 4930 priv->dev->stats.rx_packets++; 4931 priv->dev->stats.rx_bytes += len; 4932 } 4933 4934 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4935 { 4936 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4937 unsigned int entry = rx_q->dirty_rx; 4938 struct dma_desc *rx_desc = NULL; 4939 bool ret = true; 4940 4941 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4942 4943 while (budget-- > 0 && entry != rx_q->cur_rx) { 4944 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4945 dma_addr_t dma_addr; 4946 bool use_rx_wd; 4947 4948 if (!buf->xdp) { 4949 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4950 if (!buf->xdp) { 4951 ret = false; 4952 break; 4953 } 4954 } 4955 4956 if (priv->extend_desc) 4957 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4958 else 4959 rx_desc = rx_q->dma_rx + entry; 4960 4961 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4962 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4963 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4964 stmmac_refill_desc3(priv, rx_q, rx_desc); 4965 4966 rx_q->rx_count_frames++; 4967 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4968 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4969 rx_q->rx_count_frames = 0; 4970 4971 use_rx_wd = !priv->rx_coal_frames[queue]; 4972 use_rx_wd |= rx_q->rx_count_frames > 0; 4973 if (!priv->use_riwt) 4974 use_rx_wd = false; 4975 4976 dma_wmb(); 4977 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4978 4979 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4980 } 4981 4982 if (rx_desc) { 4983 rx_q->dirty_rx = entry; 4984 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4985 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4986 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4987 } 4988 4989 return ret; 4990 } 4991 4992 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4993 { 4994 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4995 unsigned int count = 0, error = 0, len = 0; 4996 int dirty = stmmac_rx_dirty(priv, queue); 4997 unsigned int next_entry = rx_q->cur_rx; 4998 unsigned int desc_size; 4999 struct bpf_prog *prog; 5000 bool failure = false; 5001 int xdp_status = 0; 5002 int status = 0; 5003 5004 if (netif_msg_rx_status(priv)) { 5005 void *rx_head; 5006 5007 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5008 if (priv->extend_desc) { 5009 rx_head = (void *)rx_q->dma_erx; 5010 desc_size = sizeof(struct dma_extended_desc); 5011 } else { 5012 rx_head = (void *)rx_q->dma_rx; 5013 desc_size = sizeof(struct dma_desc); 5014 } 5015 5016 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5017 rx_q->dma_rx_phy, desc_size); 5018 } 5019 while (count < limit) { 5020 struct stmmac_rx_buffer *buf; 5021 unsigned int buf1_len = 0; 5022 struct dma_desc *np, *p; 5023 int entry; 5024 int res; 5025 5026 if (!count && rx_q->state_saved) { 5027 error = rx_q->state.error; 5028 len = rx_q->state.len; 5029 } else { 5030 rx_q->state_saved = false; 5031 error = 0; 5032 len = 0; 5033 } 5034 5035 if (count >= limit) 5036 break; 5037 5038 read_again: 5039 buf1_len = 0; 5040 entry = next_entry; 5041 buf = &rx_q->buf_pool[entry]; 5042 5043 if (dirty >= STMMAC_RX_FILL_BATCH) { 5044 failure = failure || 5045 !stmmac_rx_refill_zc(priv, queue, dirty); 5046 dirty = 0; 5047 } 5048 5049 if (priv->extend_desc) 5050 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5051 else 5052 p = rx_q->dma_rx + entry; 5053 5054 /* read the status of the incoming frame */ 5055 status = stmmac_rx_status(priv, &priv->dev->stats, 5056 &priv->xstats, p); 5057 /* check if managed by the DMA otherwise go ahead */ 5058 if (unlikely(status & dma_own)) 5059 break; 5060 5061 /* Prefetch the next RX descriptor */ 5062 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5063 priv->dma_conf.dma_rx_size); 5064 next_entry = rx_q->cur_rx; 5065 5066 if (priv->extend_desc) 5067 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5068 else 5069 np = rx_q->dma_rx + next_entry; 5070 5071 prefetch(np); 5072 5073 /* Ensure a valid XSK buffer before proceed */ 5074 if (!buf->xdp) 5075 break; 5076 5077 if (priv->extend_desc) 5078 stmmac_rx_extended_status(priv, &priv->dev->stats, 5079 &priv->xstats, 5080 rx_q->dma_erx + entry); 5081 if (unlikely(status == discard_frame)) { 5082 xsk_buff_free(buf->xdp); 5083 buf->xdp = NULL; 5084 dirty++; 5085 error = 1; 5086 if (!priv->hwts_rx_en) 5087 priv->dev->stats.rx_errors++; 5088 } 5089 5090 if (unlikely(error && (status & rx_not_ls))) 5091 goto read_again; 5092 if (unlikely(error)) { 5093 count++; 5094 continue; 5095 } 5096 5097 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5098 if (likely(status & rx_not_ls)) { 5099 xsk_buff_free(buf->xdp); 5100 buf->xdp = NULL; 5101 dirty++; 5102 count++; 5103 goto read_again; 5104 } 5105 5106 /* XDP ZC Frame only support primary buffers for now */ 5107 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5108 len += buf1_len; 5109 5110 /* ACS is disabled; strip manually. */ 5111 if (likely(!(status & rx_not_ls))) { 5112 buf1_len -= ETH_FCS_LEN; 5113 len -= ETH_FCS_LEN; 5114 } 5115 5116 /* RX buffer is good and fit into a XSK pool buffer */ 5117 buf->xdp->data_end = buf->xdp->data + buf1_len; 5118 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5119 5120 prog = READ_ONCE(priv->xdp_prog); 5121 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5122 5123 switch (res) { 5124 case STMMAC_XDP_PASS: 5125 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5126 xsk_buff_free(buf->xdp); 5127 break; 5128 case STMMAC_XDP_CONSUMED: 5129 xsk_buff_free(buf->xdp); 5130 priv->dev->stats.rx_dropped++; 5131 break; 5132 case STMMAC_XDP_TX: 5133 case STMMAC_XDP_REDIRECT: 5134 xdp_status |= res; 5135 break; 5136 } 5137 5138 buf->xdp = NULL; 5139 dirty++; 5140 count++; 5141 } 5142 5143 if (status & rx_not_ls) { 5144 rx_q->state_saved = true; 5145 rx_q->state.error = error; 5146 rx_q->state.len = len; 5147 } 5148 5149 stmmac_finalize_xdp_rx(priv, xdp_status); 5150 5151 priv->xstats.rx_pkt_n += count; 5152 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5153 5154 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5155 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5156 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5157 else 5158 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5159 5160 return (int)count; 5161 } 5162 5163 return failure ? limit : (int)count; 5164 } 5165 5166 /** 5167 * stmmac_rx - manage the receive process 5168 * @priv: driver private structure 5169 * @limit: napi bugget 5170 * @queue: RX queue index. 5171 * Description : this the function called by the napi poll method. 5172 * It gets all the frames inside the ring. 5173 */ 5174 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5175 { 5176 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5177 struct stmmac_channel *ch = &priv->channel[queue]; 5178 unsigned int count = 0, error = 0, len = 0; 5179 int status = 0, coe = priv->hw->rx_csum; 5180 unsigned int next_entry = rx_q->cur_rx; 5181 enum dma_data_direction dma_dir; 5182 unsigned int desc_size; 5183 struct sk_buff *skb = NULL; 5184 struct xdp_buff xdp; 5185 int xdp_status = 0; 5186 int buf_sz; 5187 5188 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5189 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5190 5191 if (netif_msg_rx_status(priv)) { 5192 void *rx_head; 5193 5194 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5195 if (priv->extend_desc) { 5196 rx_head = (void *)rx_q->dma_erx; 5197 desc_size = sizeof(struct dma_extended_desc); 5198 } else { 5199 rx_head = (void *)rx_q->dma_rx; 5200 desc_size = sizeof(struct dma_desc); 5201 } 5202 5203 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5204 rx_q->dma_rx_phy, desc_size); 5205 } 5206 while (count < limit) { 5207 unsigned int buf1_len = 0, buf2_len = 0; 5208 enum pkt_hash_types hash_type; 5209 struct stmmac_rx_buffer *buf; 5210 struct dma_desc *np, *p; 5211 int entry; 5212 u32 hash; 5213 5214 if (!count && rx_q->state_saved) { 5215 skb = rx_q->state.skb; 5216 error = rx_q->state.error; 5217 len = rx_q->state.len; 5218 } else { 5219 rx_q->state_saved = false; 5220 skb = NULL; 5221 error = 0; 5222 len = 0; 5223 } 5224 5225 if (count >= limit) 5226 break; 5227 5228 read_again: 5229 buf1_len = 0; 5230 buf2_len = 0; 5231 entry = next_entry; 5232 buf = &rx_q->buf_pool[entry]; 5233 5234 if (priv->extend_desc) 5235 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5236 else 5237 p = rx_q->dma_rx + entry; 5238 5239 /* read the status of the incoming frame */ 5240 status = stmmac_rx_status(priv, &priv->dev->stats, 5241 &priv->xstats, p); 5242 /* check if managed by the DMA otherwise go ahead */ 5243 if (unlikely(status & dma_own)) 5244 break; 5245 5246 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5247 priv->dma_conf.dma_rx_size); 5248 next_entry = rx_q->cur_rx; 5249 5250 if (priv->extend_desc) 5251 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5252 else 5253 np = rx_q->dma_rx + next_entry; 5254 5255 prefetch(np); 5256 5257 if (priv->extend_desc) 5258 stmmac_rx_extended_status(priv, &priv->dev->stats, 5259 &priv->xstats, rx_q->dma_erx + entry); 5260 if (unlikely(status == discard_frame)) { 5261 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5262 buf->page = NULL; 5263 error = 1; 5264 if (!priv->hwts_rx_en) 5265 priv->dev->stats.rx_errors++; 5266 } 5267 5268 if (unlikely(error && (status & rx_not_ls))) 5269 goto read_again; 5270 if (unlikely(error)) { 5271 dev_kfree_skb(skb); 5272 skb = NULL; 5273 count++; 5274 continue; 5275 } 5276 5277 /* Buffer is good. Go on. */ 5278 5279 prefetch(page_address(buf->page) + buf->page_offset); 5280 if (buf->sec_page) 5281 prefetch(page_address(buf->sec_page)); 5282 5283 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5284 len += buf1_len; 5285 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5286 len += buf2_len; 5287 5288 /* ACS is disabled; strip manually. */ 5289 if (likely(!(status & rx_not_ls))) { 5290 if (buf2_len) { 5291 buf2_len -= ETH_FCS_LEN; 5292 len -= ETH_FCS_LEN; 5293 } else if (buf1_len) { 5294 buf1_len -= ETH_FCS_LEN; 5295 len -= ETH_FCS_LEN; 5296 } 5297 } 5298 5299 if (!skb) { 5300 unsigned int pre_len, sync_len; 5301 5302 dma_sync_single_for_cpu(priv->device, buf->addr, 5303 buf1_len, dma_dir); 5304 5305 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5306 xdp_prepare_buff(&xdp, page_address(buf->page), 5307 buf->page_offset, buf1_len, false); 5308 5309 pre_len = xdp.data_end - xdp.data_hard_start - 5310 buf->page_offset; 5311 skb = stmmac_xdp_run_prog(priv, &xdp); 5312 /* Due xdp_adjust_tail: DMA sync for_device 5313 * cover max len CPU touch 5314 */ 5315 sync_len = xdp.data_end - xdp.data_hard_start - 5316 buf->page_offset; 5317 sync_len = max(sync_len, pre_len); 5318 5319 /* For Not XDP_PASS verdict */ 5320 if (IS_ERR(skb)) { 5321 unsigned int xdp_res = -PTR_ERR(skb); 5322 5323 if (xdp_res & STMMAC_XDP_CONSUMED) { 5324 page_pool_put_page(rx_q->page_pool, 5325 virt_to_head_page(xdp.data), 5326 sync_len, true); 5327 buf->page = NULL; 5328 priv->dev->stats.rx_dropped++; 5329 5330 /* Clear skb as it was set as 5331 * status by XDP program. 5332 */ 5333 skb = NULL; 5334 5335 if (unlikely((status & rx_not_ls))) 5336 goto read_again; 5337 5338 count++; 5339 continue; 5340 } else if (xdp_res & (STMMAC_XDP_TX | 5341 STMMAC_XDP_REDIRECT)) { 5342 xdp_status |= xdp_res; 5343 buf->page = NULL; 5344 skb = NULL; 5345 count++; 5346 continue; 5347 } 5348 } 5349 } 5350 5351 if (!skb) { 5352 /* XDP program may expand or reduce tail */ 5353 buf1_len = xdp.data_end - xdp.data; 5354 5355 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5356 if (!skb) { 5357 priv->dev->stats.rx_dropped++; 5358 count++; 5359 goto drain_data; 5360 } 5361 5362 /* XDP program may adjust header */ 5363 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5364 skb_put(skb, buf1_len); 5365 5366 /* Data payload copied into SKB, page ready for recycle */ 5367 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5368 buf->page = NULL; 5369 } else if (buf1_len) { 5370 dma_sync_single_for_cpu(priv->device, buf->addr, 5371 buf1_len, dma_dir); 5372 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5373 buf->page, buf->page_offset, buf1_len, 5374 priv->dma_conf.dma_buf_sz); 5375 5376 /* Data payload appended into SKB */ 5377 page_pool_release_page(rx_q->page_pool, buf->page); 5378 buf->page = NULL; 5379 } 5380 5381 if (buf2_len) { 5382 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5383 buf2_len, dma_dir); 5384 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5385 buf->sec_page, 0, buf2_len, 5386 priv->dma_conf.dma_buf_sz); 5387 5388 /* Data payload appended into SKB */ 5389 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5390 buf->sec_page = NULL; 5391 } 5392 5393 drain_data: 5394 if (likely(status & rx_not_ls)) 5395 goto read_again; 5396 if (!skb) 5397 continue; 5398 5399 /* Got entire packet into SKB. Finish it. */ 5400 5401 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5402 stmmac_rx_vlan(priv->dev, skb); 5403 skb->protocol = eth_type_trans(skb, priv->dev); 5404 5405 if (unlikely(!coe)) 5406 skb_checksum_none_assert(skb); 5407 else 5408 skb->ip_summed = CHECKSUM_UNNECESSARY; 5409 5410 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5411 skb_set_hash(skb, hash, hash_type); 5412 5413 skb_record_rx_queue(skb, queue); 5414 napi_gro_receive(&ch->rx_napi, skb); 5415 skb = NULL; 5416 5417 priv->dev->stats.rx_packets++; 5418 priv->dev->stats.rx_bytes += len; 5419 count++; 5420 } 5421 5422 if (status & rx_not_ls || skb) { 5423 rx_q->state_saved = true; 5424 rx_q->state.skb = skb; 5425 rx_q->state.error = error; 5426 rx_q->state.len = len; 5427 } 5428 5429 stmmac_finalize_xdp_rx(priv, xdp_status); 5430 5431 stmmac_rx_refill(priv, queue); 5432 5433 priv->xstats.rx_pkt_n += count; 5434 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5435 5436 return count; 5437 } 5438 5439 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5440 { 5441 struct stmmac_channel *ch = 5442 container_of(napi, struct stmmac_channel, rx_napi); 5443 struct stmmac_priv *priv = ch->priv_data; 5444 u32 chan = ch->index; 5445 int work_done; 5446 5447 priv->xstats.napi_poll++; 5448 5449 work_done = stmmac_rx(priv, budget, chan); 5450 if (work_done < budget && napi_complete_done(napi, work_done)) { 5451 unsigned long flags; 5452 5453 spin_lock_irqsave(&ch->lock, flags); 5454 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5455 spin_unlock_irqrestore(&ch->lock, flags); 5456 } 5457 5458 return work_done; 5459 } 5460 5461 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5462 { 5463 struct stmmac_channel *ch = 5464 container_of(napi, struct stmmac_channel, tx_napi); 5465 struct stmmac_priv *priv = ch->priv_data; 5466 u32 chan = ch->index; 5467 int work_done; 5468 5469 priv->xstats.napi_poll++; 5470 5471 work_done = stmmac_tx_clean(priv, budget, chan); 5472 work_done = min(work_done, budget); 5473 5474 if (work_done < budget && napi_complete_done(napi, work_done)) { 5475 unsigned long flags; 5476 5477 spin_lock_irqsave(&ch->lock, flags); 5478 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5479 spin_unlock_irqrestore(&ch->lock, flags); 5480 } 5481 5482 return work_done; 5483 } 5484 5485 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5486 { 5487 struct stmmac_channel *ch = 5488 container_of(napi, struct stmmac_channel, rxtx_napi); 5489 struct stmmac_priv *priv = ch->priv_data; 5490 int rx_done, tx_done, rxtx_done; 5491 u32 chan = ch->index; 5492 5493 priv->xstats.napi_poll++; 5494 5495 tx_done = stmmac_tx_clean(priv, budget, chan); 5496 tx_done = min(tx_done, budget); 5497 5498 rx_done = stmmac_rx_zc(priv, budget, chan); 5499 5500 rxtx_done = max(tx_done, rx_done); 5501 5502 /* If either TX or RX work is not complete, return budget 5503 * and keep pooling 5504 */ 5505 if (rxtx_done >= budget) 5506 return budget; 5507 5508 /* all work done, exit the polling mode */ 5509 if (napi_complete_done(napi, rxtx_done)) { 5510 unsigned long flags; 5511 5512 spin_lock_irqsave(&ch->lock, flags); 5513 /* Both RX and TX work done are compelte, 5514 * so enable both RX & TX IRQs. 5515 */ 5516 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5517 spin_unlock_irqrestore(&ch->lock, flags); 5518 } 5519 5520 return min(rxtx_done, budget - 1); 5521 } 5522 5523 /** 5524 * stmmac_tx_timeout 5525 * @dev : Pointer to net device structure 5526 * @txqueue: the index of the hanging transmit queue 5527 * Description: this function is called when a packet transmission fails to 5528 * complete within a reasonable time. The driver will mark the error in the 5529 * netdev structure and arrange for the device to be reset to a sane state 5530 * in order to transmit a new packet. 5531 */ 5532 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5533 { 5534 struct stmmac_priv *priv = netdev_priv(dev); 5535 5536 stmmac_global_err(priv); 5537 } 5538 5539 /** 5540 * stmmac_set_rx_mode - entry point for multicast addressing 5541 * @dev : pointer to the device structure 5542 * Description: 5543 * This function is a driver entry point which gets called by the kernel 5544 * whenever multicast addresses must be enabled/disabled. 5545 * Return value: 5546 * void. 5547 */ 5548 static void stmmac_set_rx_mode(struct net_device *dev) 5549 { 5550 struct stmmac_priv *priv = netdev_priv(dev); 5551 5552 stmmac_set_filter(priv, priv->hw, dev); 5553 } 5554 5555 /** 5556 * stmmac_change_mtu - entry point to change MTU size for the device. 5557 * @dev : device pointer. 5558 * @new_mtu : the new MTU size for the device. 5559 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5560 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5561 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5562 * Return value: 5563 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5564 * file on failure. 5565 */ 5566 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5567 { 5568 struct stmmac_priv *priv = netdev_priv(dev); 5569 int txfifosz = priv->plat->tx_fifo_size; 5570 struct stmmac_dma_conf *dma_conf; 5571 const int mtu = new_mtu; 5572 int ret; 5573 5574 if (txfifosz == 0) 5575 txfifosz = priv->dma_cap.tx_fifo_size; 5576 5577 txfifosz /= priv->plat->tx_queues_to_use; 5578 5579 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5580 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5581 return -EINVAL; 5582 } 5583 5584 new_mtu = STMMAC_ALIGN(new_mtu); 5585 5586 /* If condition true, FIFO is too small or MTU too large */ 5587 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5588 return -EINVAL; 5589 5590 if (netif_running(dev)) { 5591 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5592 /* Try to allocate the new DMA conf with the new mtu */ 5593 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5594 if (IS_ERR(dma_conf)) { 5595 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5596 mtu); 5597 return PTR_ERR(dma_conf); 5598 } 5599 5600 stmmac_release(dev); 5601 5602 ret = __stmmac_open(dev, dma_conf); 5603 kfree(dma_conf); 5604 if (ret) { 5605 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5606 return ret; 5607 } 5608 5609 stmmac_set_rx_mode(dev); 5610 } 5611 5612 dev->mtu = mtu; 5613 netdev_update_features(dev); 5614 5615 return 0; 5616 } 5617 5618 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5619 netdev_features_t features) 5620 { 5621 struct stmmac_priv *priv = netdev_priv(dev); 5622 5623 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5624 features &= ~NETIF_F_RXCSUM; 5625 5626 if (!priv->plat->tx_coe) 5627 features &= ~NETIF_F_CSUM_MASK; 5628 5629 /* Some GMAC devices have a bugged Jumbo frame support that 5630 * needs to have the Tx COE disabled for oversized frames 5631 * (due to limited buffer sizes). In this case we disable 5632 * the TX csum insertion in the TDES and not use SF. 5633 */ 5634 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5635 features &= ~NETIF_F_CSUM_MASK; 5636 5637 /* Disable tso if asked by ethtool */ 5638 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5639 if (features & NETIF_F_TSO) 5640 priv->tso = true; 5641 else 5642 priv->tso = false; 5643 } 5644 5645 return features; 5646 } 5647 5648 static int stmmac_set_features(struct net_device *netdev, 5649 netdev_features_t features) 5650 { 5651 struct stmmac_priv *priv = netdev_priv(netdev); 5652 5653 /* Keep the COE Type in case of csum is supporting */ 5654 if (features & NETIF_F_RXCSUM) 5655 priv->hw->rx_csum = priv->plat->rx_coe; 5656 else 5657 priv->hw->rx_csum = 0; 5658 /* No check needed because rx_coe has been set before and it will be 5659 * fixed in case of issue. 5660 */ 5661 stmmac_rx_ipc(priv, priv->hw); 5662 5663 if (priv->sph_cap) { 5664 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5665 u32 chan; 5666 5667 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5668 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5669 } 5670 5671 return 0; 5672 } 5673 5674 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5675 { 5676 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5677 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5678 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5679 bool *hs_enable = &fpe_cfg->hs_enable; 5680 5681 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5682 return; 5683 5684 /* If LP has sent verify mPacket, LP is FPE capable */ 5685 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5686 if (*lp_state < FPE_STATE_CAPABLE) 5687 *lp_state = FPE_STATE_CAPABLE; 5688 5689 /* If user has requested FPE enable, quickly response */ 5690 if (*hs_enable) 5691 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5692 MPACKET_RESPONSE); 5693 } 5694 5695 /* If Local has sent verify mPacket, Local is FPE capable */ 5696 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5697 if (*lo_state < FPE_STATE_CAPABLE) 5698 *lo_state = FPE_STATE_CAPABLE; 5699 } 5700 5701 /* If LP has sent response mPacket, LP is entering FPE ON */ 5702 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5703 *lp_state = FPE_STATE_ENTERING_ON; 5704 5705 /* If Local has sent response mPacket, Local is entering FPE ON */ 5706 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5707 *lo_state = FPE_STATE_ENTERING_ON; 5708 5709 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5710 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5711 priv->fpe_wq) { 5712 queue_work(priv->fpe_wq, &priv->fpe_task); 5713 } 5714 } 5715 5716 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5717 { 5718 u32 rx_cnt = priv->plat->rx_queues_to_use; 5719 u32 tx_cnt = priv->plat->tx_queues_to_use; 5720 u32 queues_count; 5721 u32 queue; 5722 bool xmac; 5723 5724 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5725 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5726 5727 if (priv->irq_wake) 5728 pm_wakeup_event(priv->device, 0); 5729 5730 if (priv->dma_cap.estsel) 5731 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5732 &priv->xstats, tx_cnt); 5733 5734 if (priv->dma_cap.fpesel) { 5735 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5736 priv->dev); 5737 5738 stmmac_fpe_event_status(priv, status); 5739 } 5740 5741 /* To handle GMAC own interrupts */ 5742 if ((priv->plat->has_gmac) || xmac) { 5743 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5744 5745 if (unlikely(status)) { 5746 /* For LPI we need to save the tx status */ 5747 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5748 priv->tx_path_in_lpi_mode = true; 5749 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5750 priv->tx_path_in_lpi_mode = false; 5751 } 5752 5753 for (queue = 0; queue < queues_count; queue++) { 5754 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5755 queue); 5756 } 5757 5758 /* PCS link status */ 5759 if (priv->hw->pcs) { 5760 if (priv->xstats.pcs_link) 5761 netif_carrier_on(priv->dev); 5762 else 5763 netif_carrier_off(priv->dev); 5764 } 5765 5766 stmmac_timestamp_interrupt(priv, priv); 5767 } 5768 } 5769 5770 /** 5771 * stmmac_interrupt - main ISR 5772 * @irq: interrupt number. 5773 * @dev_id: to pass the net device pointer. 5774 * Description: this is the main driver interrupt service routine. 5775 * It can call: 5776 * o DMA service routine (to manage incoming frame reception and transmission 5777 * status) 5778 * o Core interrupts to manage: remote wake-up, management counter, LPI 5779 * interrupts. 5780 */ 5781 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5782 { 5783 struct net_device *dev = (struct net_device *)dev_id; 5784 struct stmmac_priv *priv = netdev_priv(dev); 5785 5786 /* Check if adapter is up */ 5787 if (test_bit(STMMAC_DOWN, &priv->state)) 5788 return IRQ_HANDLED; 5789 5790 /* Check if a fatal error happened */ 5791 if (stmmac_safety_feat_interrupt(priv)) 5792 return IRQ_HANDLED; 5793 5794 /* To handle Common interrupts */ 5795 stmmac_common_interrupt(priv); 5796 5797 /* To handle DMA interrupts */ 5798 stmmac_dma_interrupt(priv); 5799 5800 return IRQ_HANDLED; 5801 } 5802 5803 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5804 { 5805 struct net_device *dev = (struct net_device *)dev_id; 5806 struct stmmac_priv *priv = netdev_priv(dev); 5807 5808 if (unlikely(!dev)) { 5809 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5810 return IRQ_NONE; 5811 } 5812 5813 /* Check if adapter is up */ 5814 if (test_bit(STMMAC_DOWN, &priv->state)) 5815 return IRQ_HANDLED; 5816 5817 /* To handle Common interrupts */ 5818 stmmac_common_interrupt(priv); 5819 5820 return IRQ_HANDLED; 5821 } 5822 5823 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5824 { 5825 struct net_device *dev = (struct net_device *)dev_id; 5826 struct stmmac_priv *priv = netdev_priv(dev); 5827 5828 if (unlikely(!dev)) { 5829 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5830 return IRQ_NONE; 5831 } 5832 5833 /* Check if adapter is up */ 5834 if (test_bit(STMMAC_DOWN, &priv->state)) 5835 return IRQ_HANDLED; 5836 5837 /* Check if a fatal error happened */ 5838 stmmac_safety_feat_interrupt(priv); 5839 5840 return IRQ_HANDLED; 5841 } 5842 5843 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5844 { 5845 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5846 struct stmmac_dma_conf *dma_conf; 5847 int chan = tx_q->queue_index; 5848 struct stmmac_priv *priv; 5849 int status; 5850 5851 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5852 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5853 5854 if (unlikely(!data)) { 5855 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5856 return IRQ_NONE; 5857 } 5858 5859 /* Check if adapter is up */ 5860 if (test_bit(STMMAC_DOWN, &priv->state)) 5861 return IRQ_HANDLED; 5862 5863 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5864 5865 if (unlikely(status & tx_hard_error_bump_tc)) { 5866 /* Try to bump up the dma threshold on this failure */ 5867 stmmac_bump_dma_threshold(priv, chan); 5868 } else if (unlikely(status == tx_hard_error)) { 5869 stmmac_tx_err(priv, chan); 5870 } 5871 5872 return IRQ_HANDLED; 5873 } 5874 5875 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5876 { 5877 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5878 struct stmmac_dma_conf *dma_conf; 5879 int chan = rx_q->queue_index; 5880 struct stmmac_priv *priv; 5881 5882 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5883 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5884 5885 if (unlikely(!data)) { 5886 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5887 return IRQ_NONE; 5888 } 5889 5890 /* Check if adapter is up */ 5891 if (test_bit(STMMAC_DOWN, &priv->state)) 5892 return IRQ_HANDLED; 5893 5894 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5895 5896 return IRQ_HANDLED; 5897 } 5898 5899 #ifdef CONFIG_NET_POLL_CONTROLLER 5900 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5901 * to allow network I/O with interrupts disabled. 5902 */ 5903 static void stmmac_poll_controller(struct net_device *dev) 5904 { 5905 struct stmmac_priv *priv = netdev_priv(dev); 5906 int i; 5907 5908 /* If adapter is down, do nothing */ 5909 if (test_bit(STMMAC_DOWN, &priv->state)) 5910 return; 5911 5912 if (priv->plat->multi_msi_en) { 5913 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5914 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5915 5916 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5917 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5918 } else { 5919 disable_irq(dev->irq); 5920 stmmac_interrupt(dev->irq, dev); 5921 enable_irq(dev->irq); 5922 } 5923 } 5924 #endif 5925 5926 /** 5927 * stmmac_ioctl - Entry point for the Ioctl 5928 * @dev: Device pointer. 5929 * @rq: An IOCTL specefic structure, that can contain a pointer to 5930 * a proprietary structure used to pass information to the driver. 5931 * @cmd: IOCTL command 5932 * Description: 5933 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5934 */ 5935 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5936 { 5937 struct stmmac_priv *priv = netdev_priv (dev); 5938 int ret = -EOPNOTSUPP; 5939 5940 if (!netif_running(dev)) 5941 return -EINVAL; 5942 5943 switch (cmd) { 5944 case SIOCGMIIPHY: 5945 case SIOCGMIIREG: 5946 case SIOCSMIIREG: 5947 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5948 break; 5949 case SIOCSHWTSTAMP: 5950 ret = stmmac_hwtstamp_set(dev, rq); 5951 break; 5952 case SIOCGHWTSTAMP: 5953 ret = stmmac_hwtstamp_get(dev, rq); 5954 break; 5955 default: 5956 break; 5957 } 5958 5959 return ret; 5960 } 5961 5962 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5963 void *cb_priv) 5964 { 5965 struct stmmac_priv *priv = cb_priv; 5966 int ret = -EOPNOTSUPP; 5967 5968 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5969 return ret; 5970 5971 __stmmac_disable_all_queues(priv); 5972 5973 switch (type) { 5974 case TC_SETUP_CLSU32: 5975 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5976 break; 5977 case TC_SETUP_CLSFLOWER: 5978 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5979 break; 5980 default: 5981 break; 5982 } 5983 5984 stmmac_enable_all_queues(priv); 5985 return ret; 5986 } 5987 5988 static LIST_HEAD(stmmac_block_cb_list); 5989 5990 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5991 void *type_data) 5992 { 5993 struct stmmac_priv *priv = netdev_priv(ndev); 5994 5995 switch (type) { 5996 case TC_QUERY_CAPS: 5997 return stmmac_tc_query_caps(priv, priv, type_data); 5998 case TC_SETUP_BLOCK: 5999 return flow_block_cb_setup_simple(type_data, 6000 &stmmac_block_cb_list, 6001 stmmac_setup_tc_block_cb, 6002 priv, priv, true); 6003 case TC_SETUP_QDISC_CBS: 6004 return stmmac_tc_setup_cbs(priv, priv, type_data); 6005 case TC_SETUP_QDISC_TAPRIO: 6006 return stmmac_tc_setup_taprio(priv, priv, type_data); 6007 case TC_SETUP_QDISC_ETF: 6008 return stmmac_tc_setup_etf(priv, priv, type_data); 6009 default: 6010 return -EOPNOTSUPP; 6011 } 6012 } 6013 6014 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6015 struct net_device *sb_dev) 6016 { 6017 int gso = skb_shinfo(skb)->gso_type; 6018 6019 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6020 /* 6021 * There is no way to determine the number of TSO/USO 6022 * capable Queues. Let's use always the Queue 0 6023 * because if TSO/USO is supported then at least this 6024 * one will be capable. 6025 */ 6026 return 0; 6027 } 6028 6029 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6030 } 6031 6032 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6033 { 6034 struct stmmac_priv *priv = netdev_priv(ndev); 6035 int ret = 0; 6036 6037 ret = pm_runtime_resume_and_get(priv->device); 6038 if (ret < 0) 6039 return ret; 6040 6041 ret = eth_mac_addr(ndev, addr); 6042 if (ret) 6043 goto set_mac_error; 6044 6045 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6046 6047 set_mac_error: 6048 pm_runtime_put(priv->device); 6049 6050 return ret; 6051 } 6052 6053 #ifdef CONFIG_DEBUG_FS 6054 static struct dentry *stmmac_fs_dir; 6055 6056 static void sysfs_display_ring(void *head, int size, int extend_desc, 6057 struct seq_file *seq, dma_addr_t dma_phy_addr) 6058 { 6059 int i; 6060 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6061 struct dma_desc *p = (struct dma_desc *)head; 6062 dma_addr_t dma_addr; 6063 6064 for (i = 0; i < size; i++) { 6065 if (extend_desc) { 6066 dma_addr = dma_phy_addr + i * sizeof(*ep); 6067 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6068 i, &dma_addr, 6069 le32_to_cpu(ep->basic.des0), 6070 le32_to_cpu(ep->basic.des1), 6071 le32_to_cpu(ep->basic.des2), 6072 le32_to_cpu(ep->basic.des3)); 6073 ep++; 6074 } else { 6075 dma_addr = dma_phy_addr + i * sizeof(*p); 6076 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6077 i, &dma_addr, 6078 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6079 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6080 p++; 6081 } 6082 seq_printf(seq, "\n"); 6083 } 6084 } 6085 6086 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6087 { 6088 struct net_device *dev = seq->private; 6089 struct stmmac_priv *priv = netdev_priv(dev); 6090 u32 rx_count = priv->plat->rx_queues_to_use; 6091 u32 tx_count = priv->plat->tx_queues_to_use; 6092 u32 queue; 6093 6094 if ((dev->flags & IFF_UP) == 0) 6095 return 0; 6096 6097 for (queue = 0; queue < rx_count; queue++) { 6098 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6099 6100 seq_printf(seq, "RX Queue %d:\n", queue); 6101 6102 if (priv->extend_desc) { 6103 seq_printf(seq, "Extended descriptor ring:\n"); 6104 sysfs_display_ring((void *)rx_q->dma_erx, 6105 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6106 } else { 6107 seq_printf(seq, "Descriptor ring:\n"); 6108 sysfs_display_ring((void *)rx_q->dma_rx, 6109 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6110 } 6111 } 6112 6113 for (queue = 0; queue < tx_count; queue++) { 6114 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6115 6116 seq_printf(seq, "TX Queue %d:\n", queue); 6117 6118 if (priv->extend_desc) { 6119 seq_printf(seq, "Extended descriptor ring:\n"); 6120 sysfs_display_ring((void *)tx_q->dma_etx, 6121 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6122 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6123 seq_printf(seq, "Descriptor ring:\n"); 6124 sysfs_display_ring((void *)tx_q->dma_tx, 6125 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6126 } 6127 } 6128 6129 return 0; 6130 } 6131 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6132 6133 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6134 { 6135 struct net_device *dev = seq->private; 6136 struct stmmac_priv *priv = netdev_priv(dev); 6137 6138 if (!priv->hw_cap_support) { 6139 seq_printf(seq, "DMA HW features not supported\n"); 6140 return 0; 6141 } 6142 6143 seq_printf(seq, "==============================\n"); 6144 seq_printf(seq, "\tDMA HW features\n"); 6145 seq_printf(seq, "==============================\n"); 6146 6147 seq_printf(seq, "\t10/100 Mbps: %s\n", 6148 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6149 seq_printf(seq, "\t1000 Mbps: %s\n", 6150 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6151 seq_printf(seq, "\tHalf duplex: %s\n", 6152 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6153 seq_printf(seq, "\tHash Filter: %s\n", 6154 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6155 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6156 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6157 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6158 (priv->dma_cap.pcs) ? "Y" : "N"); 6159 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6160 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6161 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6162 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6163 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6164 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6165 seq_printf(seq, "\tRMON module: %s\n", 6166 (priv->dma_cap.rmon) ? "Y" : "N"); 6167 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6168 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6169 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6170 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6171 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6172 (priv->dma_cap.eee) ? "Y" : "N"); 6173 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6174 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6175 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6176 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6177 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6178 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6179 } else { 6180 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6181 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6182 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6183 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6184 } 6185 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6186 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6187 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6188 priv->dma_cap.number_rx_channel); 6189 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6190 priv->dma_cap.number_tx_channel); 6191 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6192 priv->dma_cap.number_rx_queues); 6193 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6194 priv->dma_cap.number_tx_queues); 6195 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6196 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6197 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6198 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6199 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6200 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6201 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6202 priv->dma_cap.pps_out_num); 6203 seq_printf(seq, "\tSafety Features: %s\n", 6204 priv->dma_cap.asp ? "Y" : "N"); 6205 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6206 priv->dma_cap.frpsel ? "Y" : "N"); 6207 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6208 priv->dma_cap.addr64); 6209 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6210 priv->dma_cap.rssen ? "Y" : "N"); 6211 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6212 priv->dma_cap.vlhash ? "Y" : "N"); 6213 seq_printf(seq, "\tSplit Header: %s\n", 6214 priv->dma_cap.sphen ? "Y" : "N"); 6215 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6216 priv->dma_cap.vlins ? "Y" : "N"); 6217 seq_printf(seq, "\tDouble VLAN: %s\n", 6218 priv->dma_cap.dvlan ? "Y" : "N"); 6219 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6220 priv->dma_cap.l3l4fnum); 6221 seq_printf(seq, "\tARP Offloading: %s\n", 6222 priv->dma_cap.arpoffsel ? "Y" : "N"); 6223 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6224 priv->dma_cap.estsel ? "Y" : "N"); 6225 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6226 priv->dma_cap.fpesel ? "Y" : "N"); 6227 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6228 priv->dma_cap.tbssel ? "Y" : "N"); 6229 return 0; 6230 } 6231 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6232 6233 /* Use network device events to rename debugfs file entries. 6234 */ 6235 static int stmmac_device_event(struct notifier_block *unused, 6236 unsigned long event, void *ptr) 6237 { 6238 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6239 struct stmmac_priv *priv = netdev_priv(dev); 6240 6241 if (dev->netdev_ops != &stmmac_netdev_ops) 6242 goto done; 6243 6244 switch (event) { 6245 case NETDEV_CHANGENAME: 6246 if (priv->dbgfs_dir) 6247 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6248 priv->dbgfs_dir, 6249 stmmac_fs_dir, 6250 dev->name); 6251 break; 6252 } 6253 done: 6254 return NOTIFY_DONE; 6255 } 6256 6257 static struct notifier_block stmmac_notifier = { 6258 .notifier_call = stmmac_device_event, 6259 }; 6260 6261 static void stmmac_init_fs(struct net_device *dev) 6262 { 6263 struct stmmac_priv *priv = netdev_priv(dev); 6264 6265 rtnl_lock(); 6266 6267 /* Create per netdev entries */ 6268 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6269 6270 /* Entry to report DMA RX/TX rings */ 6271 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6272 &stmmac_rings_status_fops); 6273 6274 /* Entry to report the DMA HW features */ 6275 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6276 &stmmac_dma_cap_fops); 6277 6278 rtnl_unlock(); 6279 } 6280 6281 static void stmmac_exit_fs(struct net_device *dev) 6282 { 6283 struct stmmac_priv *priv = netdev_priv(dev); 6284 6285 debugfs_remove_recursive(priv->dbgfs_dir); 6286 } 6287 #endif /* CONFIG_DEBUG_FS */ 6288 6289 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6290 { 6291 unsigned char *data = (unsigned char *)&vid_le; 6292 unsigned char data_byte = 0; 6293 u32 crc = ~0x0; 6294 u32 temp = 0; 6295 int i, bits; 6296 6297 bits = get_bitmask_order(VLAN_VID_MASK); 6298 for (i = 0; i < bits; i++) { 6299 if ((i % 8) == 0) 6300 data_byte = data[i / 8]; 6301 6302 temp = ((crc & 1) ^ data_byte) & 1; 6303 crc >>= 1; 6304 data_byte >>= 1; 6305 6306 if (temp) 6307 crc ^= 0xedb88320; 6308 } 6309 6310 return crc; 6311 } 6312 6313 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6314 { 6315 u32 crc, hash = 0; 6316 __le16 pmatch = 0; 6317 int count = 0; 6318 u16 vid = 0; 6319 6320 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6321 __le16 vid_le = cpu_to_le16(vid); 6322 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6323 hash |= (1 << crc); 6324 count++; 6325 } 6326 6327 if (!priv->dma_cap.vlhash) { 6328 if (count > 2) /* VID = 0 always passes filter */ 6329 return -EOPNOTSUPP; 6330 6331 pmatch = cpu_to_le16(vid); 6332 hash = 0; 6333 } 6334 6335 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6336 } 6337 6338 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6339 { 6340 struct stmmac_priv *priv = netdev_priv(ndev); 6341 bool is_double = false; 6342 int ret; 6343 6344 if (be16_to_cpu(proto) == ETH_P_8021AD) 6345 is_double = true; 6346 6347 set_bit(vid, priv->active_vlans); 6348 ret = stmmac_vlan_update(priv, is_double); 6349 if (ret) { 6350 clear_bit(vid, priv->active_vlans); 6351 return ret; 6352 } 6353 6354 if (priv->hw->num_vlan) { 6355 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6356 if (ret) 6357 return ret; 6358 } 6359 6360 return 0; 6361 } 6362 6363 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6364 { 6365 struct stmmac_priv *priv = netdev_priv(ndev); 6366 bool is_double = false; 6367 int ret; 6368 6369 ret = pm_runtime_resume_and_get(priv->device); 6370 if (ret < 0) 6371 return ret; 6372 6373 if (be16_to_cpu(proto) == ETH_P_8021AD) 6374 is_double = true; 6375 6376 clear_bit(vid, priv->active_vlans); 6377 6378 if (priv->hw->num_vlan) { 6379 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6380 if (ret) 6381 goto del_vlan_error; 6382 } 6383 6384 ret = stmmac_vlan_update(priv, is_double); 6385 6386 del_vlan_error: 6387 pm_runtime_put(priv->device); 6388 6389 return ret; 6390 } 6391 6392 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6393 { 6394 struct stmmac_priv *priv = netdev_priv(dev); 6395 6396 switch (bpf->command) { 6397 case XDP_SETUP_PROG: 6398 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6399 case XDP_SETUP_XSK_POOL: 6400 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6401 bpf->xsk.queue_id); 6402 default: 6403 return -EOPNOTSUPP; 6404 } 6405 } 6406 6407 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6408 struct xdp_frame **frames, u32 flags) 6409 { 6410 struct stmmac_priv *priv = netdev_priv(dev); 6411 int cpu = smp_processor_id(); 6412 struct netdev_queue *nq; 6413 int i, nxmit = 0; 6414 int queue; 6415 6416 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6417 return -ENETDOWN; 6418 6419 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6420 return -EINVAL; 6421 6422 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6423 nq = netdev_get_tx_queue(priv->dev, queue); 6424 6425 __netif_tx_lock(nq, cpu); 6426 /* Avoids TX time-out as we are sharing with slow path */ 6427 txq_trans_cond_update(nq); 6428 6429 for (i = 0; i < num_frames; i++) { 6430 int res; 6431 6432 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6433 if (res == STMMAC_XDP_CONSUMED) 6434 break; 6435 6436 nxmit++; 6437 } 6438 6439 if (flags & XDP_XMIT_FLUSH) { 6440 stmmac_flush_tx_descriptors(priv, queue); 6441 stmmac_tx_timer_arm(priv, queue); 6442 } 6443 6444 __netif_tx_unlock(nq); 6445 6446 return nxmit; 6447 } 6448 6449 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6450 { 6451 struct stmmac_channel *ch = &priv->channel[queue]; 6452 unsigned long flags; 6453 6454 spin_lock_irqsave(&ch->lock, flags); 6455 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6456 spin_unlock_irqrestore(&ch->lock, flags); 6457 6458 stmmac_stop_rx_dma(priv, queue); 6459 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6460 } 6461 6462 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6463 { 6464 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6465 struct stmmac_channel *ch = &priv->channel[queue]; 6466 unsigned long flags; 6467 u32 buf_size; 6468 int ret; 6469 6470 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6471 if (ret) { 6472 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6473 return; 6474 } 6475 6476 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6477 if (ret) { 6478 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6479 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6480 return; 6481 } 6482 6483 stmmac_reset_rx_queue(priv, queue); 6484 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6485 6486 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6487 rx_q->dma_rx_phy, rx_q->queue_index); 6488 6489 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6490 sizeof(struct dma_desc)); 6491 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6492 rx_q->rx_tail_addr, rx_q->queue_index); 6493 6494 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6495 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6496 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6497 buf_size, 6498 rx_q->queue_index); 6499 } else { 6500 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6501 priv->dma_conf.dma_buf_sz, 6502 rx_q->queue_index); 6503 } 6504 6505 stmmac_start_rx_dma(priv, queue); 6506 6507 spin_lock_irqsave(&ch->lock, flags); 6508 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6509 spin_unlock_irqrestore(&ch->lock, flags); 6510 } 6511 6512 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6513 { 6514 struct stmmac_channel *ch = &priv->channel[queue]; 6515 unsigned long flags; 6516 6517 spin_lock_irqsave(&ch->lock, flags); 6518 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6519 spin_unlock_irqrestore(&ch->lock, flags); 6520 6521 stmmac_stop_tx_dma(priv, queue); 6522 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6523 } 6524 6525 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6526 { 6527 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6528 struct stmmac_channel *ch = &priv->channel[queue]; 6529 unsigned long flags; 6530 int ret; 6531 6532 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6533 if (ret) { 6534 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6535 return; 6536 } 6537 6538 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6539 if (ret) { 6540 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6541 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6542 return; 6543 } 6544 6545 stmmac_reset_tx_queue(priv, queue); 6546 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6547 6548 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6549 tx_q->dma_tx_phy, tx_q->queue_index); 6550 6551 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6552 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6553 6554 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6555 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6556 tx_q->tx_tail_addr, tx_q->queue_index); 6557 6558 stmmac_start_tx_dma(priv, queue); 6559 6560 spin_lock_irqsave(&ch->lock, flags); 6561 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6562 spin_unlock_irqrestore(&ch->lock, flags); 6563 } 6564 6565 void stmmac_xdp_release(struct net_device *dev) 6566 { 6567 struct stmmac_priv *priv = netdev_priv(dev); 6568 u32 chan; 6569 6570 /* Ensure tx function is not running */ 6571 netif_tx_disable(dev); 6572 6573 /* Disable NAPI process */ 6574 stmmac_disable_all_queues(priv); 6575 6576 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6577 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6578 6579 /* Free the IRQ lines */ 6580 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6581 6582 /* Stop TX/RX DMA channels */ 6583 stmmac_stop_all_dma(priv); 6584 6585 /* Release and free the Rx/Tx resources */ 6586 free_dma_desc_resources(priv, &priv->dma_conf); 6587 6588 /* Disable the MAC Rx/Tx */ 6589 stmmac_mac_set(priv, priv->ioaddr, false); 6590 6591 /* set trans_start so we don't get spurious 6592 * watchdogs during reset 6593 */ 6594 netif_trans_update(dev); 6595 netif_carrier_off(dev); 6596 } 6597 6598 int stmmac_xdp_open(struct net_device *dev) 6599 { 6600 struct stmmac_priv *priv = netdev_priv(dev); 6601 u32 rx_cnt = priv->plat->rx_queues_to_use; 6602 u32 tx_cnt = priv->plat->tx_queues_to_use; 6603 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6604 struct stmmac_rx_queue *rx_q; 6605 struct stmmac_tx_queue *tx_q; 6606 u32 buf_size; 6607 bool sph_en; 6608 u32 chan; 6609 int ret; 6610 6611 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6612 if (ret < 0) { 6613 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6614 __func__); 6615 goto dma_desc_error; 6616 } 6617 6618 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6619 if (ret < 0) { 6620 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6621 __func__); 6622 goto init_error; 6623 } 6624 6625 /* DMA CSR Channel configuration */ 6626 for (chan = 0; chan < dma_csr_ch; chan++) { 6627 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6628 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6629 } 6630 6631 /* Adjust Split header */ 6632 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6633 6634 /* DMA RX Channel Configuration */ 6635 for (chan = 0; chan < rx_cnt; chan++) { 6636 rx_q = &priv->dma_conf.rx_queue[chan]; 6637 6638 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6639 rx_q->dma_rx_phy, chan); 6640 6641 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6642 (rx_q->buf_alloc_num * 6643 sizeof(struct dma_desc)); 6644 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6645 rx_q->rx_tail_addr, chan); 6646 6647 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6648 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6649 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6650 buf_size, 6651 rx_q->queue_index); 6652 } else { 6653 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6654 priv->dma_conf.dma_buf_sz, 6655 rx_q->queue_index); 6656 } 6657 6658 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6659 } 6660 6661 /* DMA TX Channel Configuration */ 6662 for (chan = 0; chan < tx_cnt; chan++) { 6663 tx_q = &priv->dma_conf.tx_queue[chan]; 6664 6665 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6666 tx_q->dma_tx_phy, chan); 6667 6668 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6669 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6670 tx_q->tx_tail_addr, chan); 6671 6672 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6673 tx_q->txtimer.function = stmmac_tx_timer; 6674 } 6675 6676 /* Enable the MAC Rx/Tx */ 6677 stmmac_mac_set(priv, priv->ioaddr, true); 6678 6679 /* Start Rx & Tx DMA Channels */ 6680 stmmac_start_all_dma(priv); 6681 6682 ret = stmmac_request_irq(dev); 6683 if (ret) 6684 goto irq_error; 6685 6686 /* Enable NAPI process*/ 6687 stmmac_enable_all_queues(priv); 6688 netif_carrier_on(dev); 6689 netif_tx_start_all_queues(dev); 6690 stmmac_enable_all_dma_irq(priv); 6691 6692 return 0; 6693 6694 irq_error: 6695 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6696 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6697 6698 stmmac_hw_teardown(dev); 6699 init_error: 6700 free_dma_desc_resources(priv, &priv->dma_conf); 6701 dma_desc_error: 6702 return ret; 6703 } 6704 6705 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6706 { 6707 struct stmmac_priv *priv = netdev_priv(dev); 6708 struct stmmac_rx_queue *rx_q; 6709 struct stmmac_tx_queue *tx_q; 6710 struct stmmac_channel *ch; 6711 6712 if (test_bit(STMMAC_DOWN, &priv->state) || 6713 !netif_carrier_ok(priv->dev)) 6714 return -ENETDOWN; 6715 6716 if (!stmmac_xdp_is_enabled(priv)) 6717 return -EINVAL; 6718 6719 if (queue >= priv->plat->rx_queues_to_use || 6720 queue >= priv->plat->tx_queues_to_use) 6721 return -EINVAL; 6722 6723 rx_q = &priv->dma_conf.rx_queue[queue]; 6724 tx_q = &priv->dma_conf.tx_queue[queue]; 6725 ch = &priv->channel[queue]; 6726 6727 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6728 return -EINVAL; 6729 6730 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6731 /* EQoS does not have per-DMA channel SW interrupt, 6732 * so we schedule RX Napi straight-away. 6733 */ 6734 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6735 __napi_schedule(&ch->rxtx_napi); 6736 } 6737 6738 return 0; 6739 } 6740 6741 static const struct net_device_ops stmmac_netdev_ops = { 6742 .ndo_open = stmmac_open, 6743 .ndo_start_xmit = stmmac_xmit, 6744 .ndo_stop = stmmac_release, 6745 .ndo_change_mtu = stmmac_change_mtu, 6746 .ndo_fix_features = stmmac_fix_features, 6747 .ndo_set_features = stmmac_set_features, 6748 .ndo_set_rx_mode = stmmac_set_rx_mode, 6749 .ndo_tx_timeout = stmmac_tx_timeout, 6750 .ndo_eth_ioctl = stmmac_ioctl, 6751 .ndo_setup_tc = stmmac_setup_tc, 6752 .ndo_select_queue = stmmac_select_queue, 6753 #ifdef CONFIG_NET_POLL_CONTROLLER 6754 .ndo_poll_controller = stmmac_poll_controller, 6755 #endif 6756 .ndo_set_mac_address = stmmac_set_mac_address, 6757 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6758 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6759 .ndo_bpf = stmmac_bpf, 6760 .ndo_xdp_xmit = stmmac_xdp_xmit, 6761 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6762 }; 6763 6764 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6765 { 6766 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6767 return; 6768 if (test_bit(STMMAC_DOWN, &priv->state)) 6769 return; 6770 6771 netdev_err(priv->dev, "Reset adapter.\n"); 6772 6773 rtnl_lock(); 6774 netif_trans_update(priv->dev); 6775 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6776 usleep_range(1000, 2000); 6777 6778 set_bit(STMMAC_DOWN, &priv->state); 6779 dev_close(priv->dev); 6780 dev_open(priv->dev, NULL); 6781 clear_bit(STMMAC_DOWN, &priv->state); 6782 clear_bit(STMMAC_RESETING, &priv->state); 6783 rtnl_unlock(); 6784 } 6785 6786 static void stmmac_service_task(struct work_struct *work) 6787 { 6788 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6789 service_task); 6790 6791 stmmac_reset_subtask(priv); 6792 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6793 } 6794 6795 /** 6796 * stmmac_hw_init - Init the MAC device 6797 * @priv: driver private structure 6798 * Description: this function is to configure the MAC device according to 6799 * some platform parameters or the HW capability register. It prepares the 6800 * driver to use either ring or chain modes and to setup either enhanced or 6801 * normal descriptors. 6802 */ 6803 static int stmmac_hw_init(struct stmmac_priv *priv) 6804 { 6805 int ret; 6806 6807 /* dwmac-sun8i only work in chain mode */ 6808 if (priv->plat->has_sun8i) 6809 chain_mode = 1; 6810 priv->chain_mode = chain_mode; 6811 6812 /* Initialize HW Interface */ 6813 ret = stmmac_hwif_init(priv); 6814 if (ret) 6815 return ret; 6816 6817 /* Get the HW capability (new GMAC newer than 3.50a) */ 6818 priv->hw_cap_support = stmmac_get_hw_features(priv); 6819 if (priv->hw_cap_support) { 6820 dev_info(priv->device, "DMA HW capability register supported\n"); 6821 6822 /* We can override some gmac/dma configuration fields: e.g. 6823 * enh_desc, tx_coe (e.g. that are passed through the 6824 * platform) with the values from the HW capability 6825 * register (if supported). 6826 */ 6827 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6828 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6829 !priv->plat->use_phy_wol; 6830 priv->hw->pmt = priv->plat->pmt; 6831 if (priv->dma_cap.hash_tb_sz) { 6832 priv->hw->multicast_filter_bins = 6833 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6834 priv->hw->mcast_bits_log2 = 6835 ilog2(priv->hw->multicast_filter_bins); 6836 } 6837 6838 /* TXCOE doesn't work in thresh DMA mode */ 6839 if (priv->plat->force_thresh_dma_mode) 6840 priv->plat->tx_coe = 0; 6841 else 6842 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6843 6844 /* In case of GMAC4 rx_coe is from HW cap register. */ 6845 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6846 6847 if (priv->dma_cap.rx_coe_type2) 6848 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6849 else if (priv->dma_cap.rx_coe_type1) 6850 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6851 6852 } else { 6853 dev_info(priv->device, "No HW DMA feature register supported\n"); 6854 } 6855 6856 if (priv->plat->rx_coe) { 6857 priv->hw->rx_csum = priv->plat->rx_coe; 6858 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6859 if (priv->synopsys_id < DWMAC_CORE_4_00) 6860 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6861 } 6862 if (priv->plat->tx_coe) 6863 dev_info(priv->device, "TX Checksum insertion supported\n"); 6864 6865 if (priv->plat->pmt) { 6866 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6867 device_set_wakeup_capable(priv->device, 1); 6868 } 6869 6870 if (priv->dma_cap.tsoen) 6871 dev_info(priv->device, "TSO supported\n"); 6872 6873 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6874 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6875 6876 /* Run HW quirks, if any */ 6877 if (priv->hwif_quirks) { 6878 ret = priv->hwif_quirks(priv); 6879 if (ret) 6880 return ret; 6881 } 6882 6883 /* Rx Watchdog is available in the COREs newer than the 3.40. 6884 * In some case, for example on bugged HW this feature 6885 * has to be disable and this can be done by passing the 6886 * riwt_off field from the platform. 6887 */ 6888 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6889 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6890 priv->use_riwt = 1; 6891 dev_info(priv->device, 6892 "Enable RX Mitigation via HW Watchdog Timer\n"); 6893 } 6894 6895 return 0; 6896 } 6897 6898 static void stmmac_napi_add(struct net_device *dev) 6899 { 6900 struct stmmac_priv *priv = netdev_priv(dev); 6901 u32 queue, maxq; 6902 6903 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6904 6905 for (queue = 0; queue < maxq; queue++) { 6906 struct stmmac_channel *ch = &priv->channel[queue]; 6907 6908 ch->priv_data = priv; 6909 ch->index = queue; 6910 spin_lock_init(&ch->lock); 6911 6912 if (queue < priv->plat->rx_queues_to_use) { 6913 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6914 } 6915 if (queue < priv->plat->tx_queues_to_use) { 6916 netif_napi_add_tx(dev, &ch->tx_napi, 6917 stmmac_napi_poll_tx); 6918 } 6919 if (queue < priv->plat->rx_queues_to_use && 6920 queue < priv->plat->tx_queues_to_use) { 6921 netif_napi_add(dev, &ch->rxtx_napi, 6922 stmmac_napi_poll_rxtx); 6923 } 6924 } 6925 } 6926 6927 static void stmmac_napi_del(struct net_device *dev) 6928 { 6929 struct stmmac_priv *priv = netdev_priv(dev); 6930 u32 queue, maxq; 6931 6932 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6933 6934 for (queue = 0; queue < maxq; queue++) { 6935 struct stmmac_channel *ch = &priv->channel[queue]; 6936 6937 if (queue < priv->plat->rx_queues_to_use) 6938 netif_napi_del(&ch->rx_napi); 6939 if (queue < priv->plat->tx_queues_to_use) 6940 netif_napi_del(&ch->tx_napi); 6941 if (queue < priv->plat->rx_queues_to_use && 6942 queue < priv->plat->tx_queues_to_use) { 6943 netif_napi_del(&ch->rxtx_napi); 6944 } 6945 } 6946 } 6947 6948 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6949 { 6950 struct stmmac_priv *priv = netdev_priv(dev); 6951 int ret = 0; 6952 6953 if (netif_running(dev)) 6954 stmmac_release(dev); 6955 6956 stmmac_napi_del(dev); 6957 6958 priv->plat->rx_queues_to_use = rx_cnt; 6959 priv->plat->tx_queues_to_use = tx_cnt; 6960 6961 stmmac_napi_add(dev); 6962 6963 if (netif_running(dev)) 6964 ret = stmmac_open(dev); 6965 6966 return ret; 6967 } 6968 6969 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6970 { 6971 struct stmmac_priv *priv = netdev_priv(dev); 6972 int ret = 0; 6973 6974 if (netif_running(dev)) 6975 stmmac_release(dev); 6976 6977 priv->dma_conf.dma_rx_size = rx_size; 6978 priv->dma_conf.dma_tx_size = tx_size; 6979 6980 if (netif_running(dev)) 6981 ret = stmmac_open(dev); 6982 6983 return ret; 6984 } 6985 6986 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6987 static void stmmac_fpe_lp_task(struct work_struct *work) 6988 { 6989 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6990 fpe_task); 6991 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6992 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6993 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6994 bool *hs_enable = &fpe_cfg->hs_enable; 6995 bool *enable = &fpe_cfg->enable; 6996 int retries = 20; 6997 6998 while (retries-- > 0) { 6999 /* Bail out immediately if FPE handshake is OFF */ 7000 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 7001 break; 7002 7003 if (*lo_state == FPE_STATE_ENTERING_ON && 7004 *lp_state == FPE_STATE_ENTERING_ON) { 7005 stmmac_fpe_configure(priv, priv->ioaddr, 7006 priv->plat->tx_queues_to_use, 7007 priv->plat->rx_queues_to_use, 7008 *enable); 7009 7010 netdev_info(priv->dev, "configured FPE\n"); 7011 7012 *lo_state = FPE_STATE_ON; 7013 *lp_state = FPE_STATE_ON; 7014 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7015 break; 7016 } 7017 7018 if ((*lo_state == FPE_STATE_CAPABLE || 7019 *lo_state == FPE_STATE_ENTERING_ON) && 7020 *lp_state != FPE_STATE_ON) { 7021 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7022 *lo_state, *lp_state); 7023 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7024 MPACKET_VERIFY); 7025 } 7026 /* Sleep then retry */ 7027 msleep(500); 7028 } 7029 7030 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7031 } 7032 7033 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7034 { 7035 if (priv->plat->fpe_cfg->hs_enable != enable) { 7036 if (enable) { 7037 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7038 MPACKET_VERIFY); 7039 } else { 7040 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7041 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7042 } 7043 7044 priv->plat->fpe_cfg->hs_enable = enable; 7045 } 7046 } 7047 7048 /** 7049 * stmmac_dvr_probe 7050 * @device: device pointer 7051 * @plat_dat: platform data pointer 7052 * @res: stmmac resource pointer 7053 * Description: this is the main probe function used to 7054 * call the alloc_etherdev, allocate the priv structure. 7055 * Return: 7056 * returns 0 on success, otherwise errno. 7057 */ 7058 int stmmac_dvr_probe(struct device *device, 7059 struct plat_stmmacenet_data *plat_dat, 7060 struct stmmac_resources *res) 7061 { 7062 struct net_device *ndev = NULL; 7063 struct stmmac_priv *priv; 7064 u32 rxq; 7065 int i, ret = 0; 7066 7067 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7068 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7069 if (!ndev) 7070 return -ENOMEM; 7071 7072 SET_NETDEV_DEV(ndev, device); 7073 7074 priv = netdev_priv(ndev); 7075 priv->device = device; 7076 priv->dev = ndev; 7077 7078 stmmac_set_ethtool_ops(ndev); 7079 priv->pause = pause; 7080 priv->plat = plat_dat; 7081 priv->ioaddr = res->addr; 7082 priv->dev->base_addr = (unsigned long)res->addr; 7083 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7084 7085 priv->dev->irq = res->irq; 7086 priv->wol_irq = res->wol_irq; 7087 priv->lpi_irq = res->lpi_irq; 7088 priv->sfty_ce_irq = res->sfty_ce_irq; 7089 priv->sfty_ue_irq = res->sfty_ue_irq; 7090 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7091 priv->rx_irq[i] = res->rx_irq[i]; 7092 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7093 priv->tx_irq[i] = res->tx_irq[i]; 7094 7095 if (!is_zero_ether_addr(res->mac)) 7096 eth_hw_addr_set(priv->dev, res->mac); 7097 7098 dev_set_drvdata(device, priv->dev); 7099 7100 /* Verify driver arguments */ 7101 stmmac_verify_args(); 7102 7103 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7104 if (!priv->af_xdp_zc_qps) 7105 return -ENOMEM; 7106 7107 /* Allocate workqueue */ 7108 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7109 if (!priv->wq) { 7110 dev_err(priv->device, "failed to create workqueue\n"); 7111 ret = -ENOMEM; 7112 goto error_wq_init; 7113 } 7114 7115 INIT_WORK(&priv->service_task, stmmac_service_task); 7116 7117 /* Initialize Link Partner FPE workqueue */ 7118 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7119 7120 /* Override with kernel parameters if supplied XXX CRS XXX 7121 * this needs to have multiple instances 7122 */ 7123 if ((phyaddr >= 0) && (phyaddr <= 31)) 7124 priv->plat->phy_addr = phyaddr; 7125 7126 if (priv->plat->stmmac_rst) { 7127 ret = reset_control_assert(priv->plat->stmmac_rst); 7128 reset_control_deassert(priv->plat->stmmac_rst); 7129 /* Some reset controllers have only reset callback instead of 7130 * assert + deassert callbacks pair. 7131 */ 7132 if (ret == -ENOTSUPP) 7133 reset_control_reset(priv->plat->stmmac_rst); 7134 } 7135 7136 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7137 if (ret == -ENOTSUPP) 7138 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7139 ERR_PTR(ret)); 7140 7141 /* Init MAC and get the capabilities */ 7142 ret = stmmac_hw_init(priv); 7143 if (ret) 7144 goto error_hw_init; 7145 7146 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7147 */ 7148 if (priv->synopsys_id < DWMAC_CORE_5_20) 7149 priv->plat->dma_cfg->dche = false; 7150 7151 stmmac_check_ether_addr(priv); 7152 7153 ndev->netdev_ops = &stmmac_netdev_ops; 7154 7155 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7156 NETIF_F_RXCSUM; 7157 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7158 NETDEV_XDP_ACT_XSK_ZEROCOPY | 7159 NETDEV_XDP_ACT_NDO_XMIT; 7160 7161 ret = stmmac_tc_init(priv, priv); 7162 if (!ret) { 7163 ndev->hw_features |= NETIF_F_HW_TC; 7164 } 7165 7166 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7167 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7168 if (priv->plat->has_gmac4) 7169 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7170 priv->tso = true; 7171 dev_info(priv->device, "TSO feature enabled\n"); 7172 } 7173 7174 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7175 ndev->hw_features |= NETIF_F_GRO; 7176 priv->sph_cap = true; 7177 priv->sph = priv->sph_cap; 7178 dev_info(priv->device, "SPH feature enabled\n"); 7179 } 7180 7181 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7182 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7183 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7184 * So overwrite dma_cap.addr64 according to HW real design. 7185 */ 7186 if (priv->plat->addr64) 7187 priv->dma_cap.addr64 = priv->plat->addr64; 7188 7189 if (priv->dma_cap.addr64) { 7190 ret = dma_set_mask_and_coherent(device, 7191 DMA_BIT_MASK(priv->dma_cap.addr64)); 7192 if (!ret) { 7193 dev_info(priv->device, "Using %d bits DMA width\n", 7194 priv->dma_cap.addr64); 7195 7196 /* 7197 * If more than 32 bits can be addressed, make sure to 7198 * enable enhanced addressing mode. 7199 */ 7200 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7201 priv->plat->dma_cfg->eame = true; 7202 } else { 7203 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7204 if (ret) { 7205 dev_err(priv->device, "Failed to set DMA Mask\n"); 7206 goto error_hw_init; 7207 } 7208 7209 priv->dma_cap.addr64 = 32; 7210 } 7211 } 7212 7213 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7214 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7215 #ifdef STMMAC_VLAN_TAG_USED 7216 /* Both mac100 and gmac support receive VLAN tag detection */ 7217 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7218 if (priv->dma_cap.vlhash) { 7219 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7220 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7221 } 7222 if (priv->dma_cap.vlins) { 7223 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7224 if (priv->dma_cap.dvlan) 7225 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7226 } 7227 #endif 7228 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7229 7230 /* Initialize RSS */ 7231 rxq = priv->plat->rx_queues_to_use; 7232 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7233 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7234 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7235 7236 if (priv->dma_cap.rssen && priv->plat->rss_en) 7237 ndev->features |= NETIF_F_RXHASH; 7238 7239 /* MTU range: 46 - hw-specific max */ 7240 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7241 if (priv->plat->has_xgmac) 7242 ndev->max_mtu = XGMAC_JUMBO_LEN; 7243 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7244 ndev->max_mtu = JUMBO_LEN; 7245 else 7246 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7247 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7248 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7249 */ 7250 if ((priv->plat->maxmtu < ndev->max_mtu) && 7251 (priv->plat->maxmtu >= ndev->min_mtu)) 7252 ndev->max_mtu = priv->plat->maxmtu; 7253 else if (priv->plat->maxmtu < ndev->min_mtu) 7254 dev_warn(priv->device, 7255 "%s: warning: maxmtu having invalid value (%d)\n", 7256 __func__, priv->plat->maxmtu); 7257 7258 if (flow_ctrl) 7259 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7260 7261 /* Setup channels NAPI */ 7262 stmmac_napi_add(ndev); 7263 7264 mutex_init(&priv->lock); 7265 7266 /* If a specific clk_csr value is passed from the platform 7267 * this means that the CSR Clock Range selection cannot be 7268 * changed at run-time and it is fixed. Viceversa the driver'll try to 7269 * set the MDC clock dynamically according to the csr actual 7270 * clock input. 7271 */ 7272 if (priv->plat->clk_csr >= 0) 7273 priv->clk_csr = priv->plat->clk_csr; 7274 else 7275 stmmac_clk_csr_set(priv); 7276 7277 stmmac_check_pcs_mode(priv); 7278 7279 pm_runtime_get_noresume(device); 7280 pm_runtime_set_active(device); 7281 if (!pm_runtime_enabled(device)) 7282 pm_runtime_enable(device); 7283 7284 if (priv->hw->pcs != STMMAC_PCS_TBI && 7285 priv->hw->pcs != STMMAC_PCS_RTBI) { 7286 /* MDIO bus Registration */ 7287 ret = stmmac_mdio_register(ndev); 7288 if (ret < 0) { 7289 dev_err_probe(priv->device, ret, 7290 "%s: MDIO bus (id: %d) registration failed\n", 7291 __func__, priv->plat->bus_id); 7292 goto error_mdio_register; 7293 } 7294 } 7295 7296 if (priv->plat->speed_mode_2500) 7297 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7298 7299 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7300 ret = stmmac_xpcs_setup(priv->mii); 7301 if (ret) 7302 goto error_xpcs_setup; 7303 } 7304 7305 ret = stmmac_phy_setup(priv); 7306 if (ret) { 7307 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7308 goto error_phy_setup; 7309 } 7310 7311 ret = register_netdev(ndev); 7312 if (ret) { 7313 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7314 __func__, ret); 7315 goto error_netdev_register; 7316 } 7317 7318 #ifdef CONFIG_DEBUG_FS 7319 stmmac_init_fs(ndev); 7320 #endif 7321 7322 if (priv->plat->dump_debug_regs) 7323 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7324 7325 /* Let pm_runtime_put() disable the clocks. 7326 * If CONFIG_PM is not enabled, the clocks will stay powered. 7327 */ 7328 pm_runtime_put(device); 7329 7330 return ret; 7331 7332 error_netdev_register: 7333 phylink_destroy(priv->phylink); 7334 error_xpcs_setup: 7335 error_phy_setup: 7336 if (priv->hw->pcs != STMMAC_PCS_TBI && 7337 priv->hw->pcs != STMMAC_PCS_RTBI) 7338 stmmac_mdio_unregister(ndev); 7339 error_mdio_register: 7340 stmmac_napi_del(ndev); 7341 error_hw_init: 7342 destroy_workqueue(priv->wq); 7343 error_wq_init: 7344 bitmap_free(priv->af_xdp_zc_qps); 7345 7346 return ret; 7347 } 7348 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7349 7350 /** 7351 * stmmac_dvr_remove 7352 * @dev: device pointer 7353 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7354 * changes the link status, releases the DMA descriptor rings. 7355 */ 7356 void stmmac_dvr_remove(struct device *dev) 7357 { 7358 struct net_device *ndev = dev_get_drvdata(dev); 7359 struct stmmac_priv *priv = netdev_priv(ndev); 7360 7361 netdev_info(priv->dev, "%s: removing driver", __func__); 7362 7363 pm_runtime_get_sync(dev); 7364 7365 stmmac_stop_all_dma(priv); 7366 stmmac_mac_set(priv, priv->ioaddr, false); 7367 netif_carrier_off(ndev); 7368 unregister_netdev(ndev); 7369 7370 /* Serdes power down needs to happen after VLAN filter 7371 * is deleted that is triggered by unregister_netdev(). 7372 */ 7373 if (priv->plat->serdes_powerdown) 7374 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7375 7376 #ifdef CONFIG_DEBUG_FS 7377 stmmac_exit_fs(ndev); 7378 #endif 7379 phylink_destroy(priv->phylink); 7380 if (priv->plat->stmmac_rst) 7381 reset_control_assert(priv->plat->stmmac_rst); 7382 reset_control_assert(priv->plat->stmmac_ahb_rst); 7383 if (priv->hw->pcs != STMMAC_PCS_TBI && 7384 priv->hw->pcs != STMMAC_PCS_RTBI) 7385 stmmac_mdio_unregister(ndev); 7386 destroy_workqueue(priv->wq); 7387 mutex_destroy(&priv->lock); 7388 bitmap_free(priv->af_xdp_zc_qps); 7389 7390 pm_runtime_disable(dev); 7391 pm_runtime_put_noidle(dev); 7392 } 7393 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7394 7395 /** 7396 * stmmac_suspend - suspend callback 7397 * @dev: device pointer 7398 * Description: this is the function to suspend the device and it is called 7399 * by the platform driver to stop the network queue, release the resources, 7400 * program the PMT register (for WoL), clean and release driver resources. 7401 */ 7402 int stmmac_suspend(struct device *dev) 7403 { 7404 struct net_device *ndev = dev_get_drvdata(dev); 7405 struct stmmac_priv *priv = netdev_priv(ndev); 7406 u32 chan; 7407 7408 if (!ndev || !netif_running(ndev)) 7409 return 0; 7410 7411 mutex_lock(&priv->lock); 7412 7413 netif_device_detach(ndev); 7414 7415 stmmac_disable_all_queues(priv); 7416 7417 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7418 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7419 7420 if (priv->eee_enabled) { 7421 priv->tx_path_in_lpi_mode = false; 7422 del_timer_sync(&priv->eee_ctrl_timer); 7423 } 7424 7425 /* Stop TX/RX DMA */ 7426 stmmac_stop_all_dma(priv); 7427 7428 if (priv->plat->serdes_powerdown) 7429 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7430 7431 /* Enable Power down mode by programming the PMT regs */ 7432 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7433 stmmac_pmt(priv, priv->hw, priv->wolopts); 7434 priv->irq_wake = 1; 7435 } else { 7436 stmmac_mac_set(priv, priv->ioaddr, false); 7437 pinctrl_pm_select_sleep_state(priv->device); 7438 } 7439 7440 mutex_unlock(&priv->lock); 7441 7442 rtnl_lock(); 7443 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7444 phylink_suspend(priv->phylink, true); 7445 } else { 7446 if (device_may_wakeup(priv->device)) 7447 phylink_speed_down(priv->phylink, false); 7448 phylink_suspend(priv->phylink, false); 7449 } 7450 rtnl_unlock(); 7451 7452 if (priv->dma_cap.fpesel) { 7453 /* Disable FPE */ 7454 stmmac_fpe_configure(priv, priv->ioaddr, 7455 priv->plat->tx_queues_to_use, 7456 priv->plat->rx_queues_to_use, false); 7457 7458 stmmac_fpe_handshake(priv, false); 7459 stmmac_fpe_stop_wq(priv); 7460 } 7461 7462 priv->speed = SPEED_UNKNOWN; 7463 return 0; 7464 } 7465 EXPORT_SYMBOL_GPL(stmmac_suspend); 7466 7467 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7468 { 7469 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7470 7471 rx_q->cur_rx = 0; 7472 rx_q->dirty_rx = 0; 7473 } 7474 7475 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7476 { 7477 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7478 7479 tx_q->cur_tx = 0; 7480 tx_q->dirty_tx = 0; 7481 tx_q->mss = 0; 7482 7483 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7484 } 7485 7486 /** 7487 * stmmac_reset_queues_param - reset queue parameters 7488 * @priv: device pointer 7489 */ 7490 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7491 { 7492 u32 rx_cnt = priv->plat->rx_queues_to_use; 7493 u32 tx_cnt = priv->plat->tx_queues_to_use; 7494 u32 queue; 7495 7496 for (queue = 0; queue < rx_cnt; queue++) 7497 stmmac_reset_rx_queue(priv, queue); 7498 7499 for (queue = 0; queue < tx_cnt; queue++) 7500 stmmac_reset_tx_queue(priv, queue); 7501 } 7502 7503 /** 7504 * stmmac_resume - resume callback 7505 * @dev: device pointer 7506 * Description: when resume this function is invoked to setup the DMA and CORE 7507 * in a usable state. 7508 */ 7509 int stmmac_resume(struct device *dev) 7510 { 7511 struct net_device *ndev = dev_get_drvdata(dev); 7512 struct stmmac_priv *priv = netdev_priv(ndev); 7513 int ret; 7514 7515 if (!netif_running(ndev)) 7516 return 0; 7517 7518 /* Power Down bit, into the PM register, is cleared 7519 * automatically as soon as a magic packet or a Wake-up frame 7520 * is received. Anyway, it's better to manually clear 7521 * this bit because it can generate problems while resuming 7522 * from another devices (e.g. serial console). 7523 */ 7524 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7525 mutex_lock(&priv->lock); 7526 stmmac_pmt(priv, priv->hw, 0); 7527 mutex_unlock(&priv->lock); 7528 priv->irq_wake = 0; 7529 } else { 7530 pinctrl_pm_select_default_state(priv->device); 7531 /* reset the phy so that it's ready */ 7532 if (priv->mii) 7533 stmmac_mdio_reset(priv->mii); 7534 } 7535 7536 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 7537 ret = priv->plat->serdes_powerup(ndev, 7538 priv->plat->bsp_priv); 7539 7540 if (ret < 0) 7541 return ret; 7542 } 7543 7544 rtnl_lock(); 7545 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7546 phylink_resume(priv->phylink); 7547 } else { 7548 phylink_resume(priv->phylink); 7549 if (device_may_wakeup(priv->device)) 7550 phylink_speed_up(priv->phylink); 7551 } 7552 rtnl_unlock(); 7553 7554 rtnl_lock(); 7555 mutex_lock(&priv->lock); 7556 7557 stmmac_reset_queues_param(priv); 7558 7559 stmmac_free_tx_skbufs(priv); 7560 stmmac_clear_descriptors(priv, &priv->dma_conf); 7561 7562 stmmac_hw_setup(ndev, false); 7563 stmmac_init_coalesce(priv); 7564 stmmac_set_rx_mode(ndev); 7565 7566 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7567 7568 stmmac_enable_all_queues(priv); 7569 stmmac_enable_all_dma_irq(priv); 7570 7571 mutex_unlock(&priv->lock); 7572 rtnl_unlock(); 7573 7574 netif_device_attach(ndev); 7575 7576 return 0; 7577 } 7578 EXPORT_SYMBOL_GPL(stmmac_resume); 7579 7580 #ifndef MODULE 7581 static int __init stmmac_cmdline_opt(char *str) 7582 { 7583 char *opt; 7584 7585 if (!str || !*str) 7586 return 1; 7587 while ((opt = strsep(&str, ",")) != NULL) { 7588 if (!strncmp(opt, "debug:", 6)) { 7589 if (kstrtoint(opt + 6, 0, &debug)) 7590 goto err; 7591 } else if (!strncmp(opt, "phyaddr:", 8)) { 7592 if (kstrtoint(opt + 8, 0, &phyaddr)) 7593 goto err; 7594 } else if (!strncmp(opt, "buf_sz:", 7)) { 7595 if (kstrtoint(opt + 7, 0, &buf_sz)) 7596 goto err; 7597 } else if (!strncmp(opt, "tc:", 3)) { 7598 if (kstrtoint(opt + 3, 0, &tc)) 7599 goto err; 7600 } else if (!strncmp(opt, "watchdog:", 9)) { 7601 if (kstrtoint(opt + 9, 0, &watchdog)) 7602 goto err; 7603 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7604 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7605 goto err; 7606 } else if (!strncmp(opt, "pause:", 6)) { 7607 if (kstrtoint(opt + 6, 0, &pause)) 7608 goto err; 7609 } else if (!strncmp(opt, "eee_timer:", 10)) { 7610 if (kstrtoint(opt + 10, 0, &eee_timer)) 7611 goto err; 7612 } else if (!strncmp(opt, "chain_mode:", 11)) { 7613 if (kstrtoint(opt + 11, 0, &chain_mode)) 7614 goto err; 7615 } 7616 } 7617 return 1; 7618 7619 err: 7620 pr_err("%s: ERROR broken module parameter conversion", __func__); 7621 return 1; 7622 } 7623 7624 __setup("stmmaceth=", stmmac_cmdline_opt); 7625 #endif /* MODULE */ 7626 7627 static int __init stmmac_init(void) 7628 { 7629 #ifdef CONFIG_DEBUG_FS 7630 /* Create debugfs main directory if it doesn't exist yet */ 7631 if (!stmmac_fs_dir) 7632 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7633 register_netdevice_notifier(&stmmac_notifier); 7634 #endif 7635 7636 return 0; 7637 } 7638 7639 static void __exit stmmac_exit(void) 7640 { 7641 #ifdef CONFIG_DEBUG_FS 7642 unregister_netdevice_notifier(&stmmac_notifier); 7643 debugfs_remove_recursive(stmmac_fs_dir); 7644 #endif 7645 } 7646 7647 module_init(stmmac_init) 7648 module_exit(stmmac_exit) 7649 7650 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7651 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7652 MODULE_LICENSE("GPL"); 7653