1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 #include <linux/of_mdio.h> 56 #include "dwmac1000.h" 57 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 60 61 /* Module parameters */ 62 #define TX_TIMEO 5000 63 static int watchdog = TX_TIMEO; 64 module_param(watchdog, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 66 67 static int debug = -1; 68 module_param(debug, int, S_IRUGO | S_IWUSR); 69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 70 71 static int phyaddr = -1; 72 module_param(phyaddr, int, S_IRUGO); 73 MODULE_PARM_DESC(phyaddr, "Physical device address"); 74 75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 77 78 static int flow_ctrl = FLOW_OFF; 79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 81 82 static int pause = PAUSE_TIME; 83 module_param(pause, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 85 86 #define TC_DEFAULT 64 87 static int tc = TC_DEFAULT; 88 module_param(tc, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(tc, "DMA threshold control value"); 90 91 #define DEFAULT_BUFSIZE 1536 92 static int buf_sz = DEFAULT_BUFSIZE; 93 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 94 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 95 96 #define STMMAC_RX_COPYBREAK 256 97 98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 99 NETIF_MSG_LINK | NETIF_MSG_IFUP | 100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 101 102 #define STMMAC_DEFAULT_LPI_TIMER 1000 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 107 108 /* By default the driver will use the ring mode to manage tx and rx descriptors, 109 * but allow user to force to use the chain instead of the ring 110 */ 111 static unsigned int chain_mode; 112 module_param(chain_mode, int, S_IRUGO); 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 114 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 116 117 #ifdef CONFIG_DEBUG_FS 118 static int stmmac_init_fs(struct net_device *dev); 119 static void stmmac_exit_fs(struct net_device *dev); 120 #endif 121 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 123 124 /** 125 * stmmac_verify_args - verify the driver parameters. 126 * Description: it checks the driver parameters and set a default in case of 127 * errors. 128 */ 129 static void stmmac_verify_args(void) 130 { 131 if (unlikely(watchdog < 0)) 132 watchdog = TX_TIMEO; 133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 134 buf_sz = DEFAULT_BUFSIZE; 135 if (unlikely(flow_ctrl > 1)) 136 flow_ctrl = FLOW_AUTO; 137 else if (likely(flow_ctrl < 0)) 138 flow_ctrl = FLOW_OFF; 139 if (unlikely((pause < 0) || (pause > 0xffff))) 140 pause = PAUSE_TIME; 141 if (eee_timer < 0) 142 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 143 } 144 145 /** 146 * stmmac_clk_csr_set - dynamically set the MDC clock 147 * @priv: driver private structure 148 * Description: this is to dynamically set the MDC clock according to the csr 149 * clock input. 150 * Note: 151 * If a specific clk_csr value is passed from the platform 152 * this means that the CSR Clock Range selection cannot be 153 * changed at run-time and it is fixed (as reported in the driver 154 * documentation). Viceversa the driver will try to set the MDC 155 * clock dynamically according to the actual clock input. 156 */ 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 158 { 159 u32 clk_rate; 160 161 clk_rate = clk_get_rate(priv->stmmac_clk); 162 163 /* Platform provided default clk_csr would be assumed valid 164 * for all other cases except for the below mentioned ones. 165 * For values higher than the IEEE 802.3 specified frequency 166 * we can not estimate the proper divider as it is not known 167 * the frequency of clk_csr_i. So we do not change the default 168 * divider. 169 */ 170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 171 if (clk_rate < CSR_F_35M) 172 priv->clk_csr = STMMAC_CSR_20_35M; 173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 174 priv->clk_csr = STMMAC_CSR_35_60M; 175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 176 priv->clk_csr = STMMAC_CSR_60_100M; 177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 178 priv->clk_csr = STMMAC_CSR_100_150M; 179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 180 priv->clk_csr = STMMAC_CSR_150_250M; 181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 182 priv->clk_csr = STMMAC_CSR_250_300M; 183 } 184 } 185 186 static void print_pkt(unsigned char *buf, int len) 187 { 188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 190 } 191 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 193 { 194 unsigned avail; 195 196 if (priv->dirty_tx > priv->cur_tx) 197 avail = priv->dirty_tx - priv->cur_tx - 1; 198 else 199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; 200 201 return avail; 202 } 203 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) 205 { 206 unsigned dirty; 207 208 if (priv->dirty_rx <= priv->cur_rx) 209 dirty = priv->cur_rx - priv->dirty_rx; 210 else 211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; 212 213 return dirty; 214 } 215 216 /** 217 * stmmac_hw_fix_mac_speed - callback for speed selection 218 * @priv: driver private structure 219 * Description: on some platforms (e.g. ST), some HW system configuraton 220 * registers have to be set according to the link speed negotiated. 221 */ 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 223 { 224 struct net_device *ndev = priv->dev; 225 struct phy_device *phydev = ndev->phydev; 226 227 if (likely(priv->plat->fix_mac_speed)) 228 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 229 } 230 231 /** 232 * stmmac_enable_eee_mode - check and enter in LPI mode 233 * @priv: driver private structure 234 * Description: this function is to verify and enter in LPI mode in case of 235 * EEE. 236 */ 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 238 { 239 /* Check and enter in LPI mode */ 240 if ((priv->dirty_tx == priv->cur_tx) && 241 (priv->tx_path_in_lpi_mode == false)) 242 priv->hw->mac->set_eee_mode(priv->hw); 243 } 244 245 /** 246 * stmmac_disable_eee_mode - disable and exit from LPI mode 247 * @priv: driver private structure 248 * Description: this function is to exit and disable EEE in case of 249 * LPI state is true. This is called by the xmit. 250 */ 251 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 252 { 253 priv->hw->mac->reset_eee_mode(priv->hw); 254 del_timer_sync(&priv->eee_ctrl_timer); 255 priv->tx_path_in_lpi_mode = false; 256 } 257 258 /** 259 * stmmac_eee_ctrl_timer - EEE TX SW timer. 260 * @arg : data hook 261 * Description: 262 * if there is no data transfer and if we are not in LPI state, 263 * then MAC Transmitter can be moved to LPI state. 264 */ 265 static void stmmac_eee_ctrl_timer(unsigned long arg) 266 { 267 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 268 269 stmmac_enable_eee_mode(priv); 270 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 271 } 272 273 /** 274 * stmmac_eee_init - init EEE 275 * @priv: driver private structure 276 * Description: 277 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 278 * can also manage EEE, this function enable the LPI state and start related 279 * timer. 280 */ 281 bool stmmac_eee_init(struct stmmac_priv *priv) 282 { 283 struct net_device *ndev = priv->dev; 284 unsigned long flags; 285 bool ret = false; 286 287 /* Using PCS we cannot dial with the phy registers at this stage 288 * so we do not support extra feature like EEE. 289 */ 290 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 291 (priv->hw->pcs == STMMAC_PCS_TBI) || 292 (priv->hw->pcs == STMMAC_PCS_RTBI)) 293 goto out; 294 295 /* MAC core supports the EEE feature. */ 296 if (priv->dma_cap.eee) { 297 int tx_lpi_timer = priv->tx_lpi_timer; 298 299 /* Check if the PHY supports EEE */ 300 if (phy_init_eee(ndev->phydev, 1)) { 301 /* To manage at run-time if the EEE cannot be supported 302 * anymore (for example because the lp caps have been 303 * changed). 304 * In that case the driver disable own timers. 305 */ 306 spin_lock_irqsave(&priv->lock, flags); 307 if (priv->eee_active) { 308 netdev_dbg(priv->dev, "disable EEE\n"); 309 del_timer_sync(&priv->eee_ctrl_timer); 310 priv->hw->mac->set_eee_timer(priv->hw, 0, 311 tx_lpi_timer); 312 } 313 priv->eee_active = 0; 314 spin_unlock_irqrestore(&priv->lock, flags); 315 goto out; 316 } 317 /* Activate the EEE and start timers */ 318 spin_lock_irqsave(&priv->lock, flags); 319 if (!priv->eee_active) { 320 priv->eee_active = 1; 321 setup_timer(&priv->eee_ctrl_timer, 322 stmmac_eee_ctrl_timer, 323 (unsigned long)priv); 324 mod_timer(&priv->eee_ctrl_timer, 325 STMMAC_LPI_T(eee_timer)); 326 327 priv->hw->mac->set_eee_timer(priv->hw, 328 STMMAC_DEFAULT_LIT_LS, 329 tx_lpi_timer); 330 } 331 /* Set HW EEE according to the speed */ 332 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); 333 334 ret = true; 335 spin_unlock_irqrestore(&priv->lock, flags); 336 337 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 338 } 339 out: 340 return ret; 341 } 342 343 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 344 * @priv: driver private structure 345 * @p : descriptor pointer 346 * @skb : the socket buffer 347 * Description : 348 * This function will read timestamp from the descriptor & pass it to stack. 349 * and also perform some sanity checks. 350 */ 351 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 352 struct dma_desc *p, struct sk_buff *skb) 353 { 354 struct skb_shared_hwtstamps shhwtstamp; 355 u64 ns; 356 357 if (!priv->hwts_tx_en) 358 return; 359 360 /* exit if skb doesn't support hw tstamp */ 361 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 362 return; 363 364 /* check tx tstamp status */ 365 if (!priv->hw->desc->get_tx_timestamp_status(p)) { 366 /* get the valid tstamp */ 367 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); 368 369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 370 shhwtstamp.hwtstamp = ns_to_ktime(ns); 371 372 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); 373 /* pass tstamp to stack */ 374 skb_tstamp_tx(skb, &shhwtstamp); 375 } 376 377 return; 378 } 379 380 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 381 * @priv: driver private structure 382 * @p : descriptor pointer 383 * @np : next descriptor pointer 384 * @skb : the socket buffer 385 * Description : 386 * This function will read received packet's timestamp from the descriptor 387 * and pass it to stack. It also perform some sanity checks. 388 */ 389 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 390 struct dma_desc *np, struct sk_buff *skb) 391 { 392 struct skb_shared_hwtstamps *shhwtstamp = NULL; 393 u64 ns; 394 395 if (!priv->hwts_rx_en) 396 return; 397 398 /* Check if timestamp is available */ 399 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { 400 /* For GMAC4, the valid timestamp is from CTX next desc. */ 401 if (priv->plat->has_gmac4) 402 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); 403 else 404 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); 405 406 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); 407 shhwtstamp = skb_hwtstamps(skb); 408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 409 shhwtstamp->hwtstamp = ns_to_ktime(ns); 410 } else { 411 netdev_err(priv->dev, "cannot get RX hw timestamp\n"); 412 } 413 } 414 415 /** 416 * stmmac_hwtstamp_ioctl - control hardware timestamping. 417 * @dev: device pointer. 418 * @ifr: An IOCTL specefic structure, that can contain a pointer to 419 * a proprietary structure used to pass information to the driver. 420 * Description: 421 * This function configures the MAC to enable/disable both outgoing(TX) 422 * and incoming(RX) packets time stamping based on user input. 423 * Return Value: 424 * 0 on success and an appropriate -ve integer on failure. 425 */ 426 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 427 { 428 struct stmmac_priv *priv = netdev_priv(dev); 429 struct hwtstamp_config config; 430 struct timespec64 now; 431 u64 temp = 0; 432 u32 ptp_v2 = 0; 433 u32 tstamp_all = 0; 434 u32 ptp_over_ipv4_udp = 0; 435 u32 ptp_over_ipv6_udp = 0; 436 u32 ptp_over_ethernet = 0; 437 u32 snap_type_sel = 0; 438 u32 ts_master_en = 0; 439 u32 ts_event_en = 0; 440 u32 value = 0; 441 u32 sec_inc; 442 443 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 444 netdev_alert(priv->dev, "No support for HW time stamping\n"); 445 priv->hwts_tx_en = 0; 446 priv->hwts_rx_en = 0; 447 448 return -EOPNOTSUPP; 449 } 450 451 if (copy_from_user(&config, ifr->ifr_data, 452 sizeof(struct hwtstamp_config))) 453 return -EFAULT; 454 455 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 456 __func__, config.flags, config.tx_type, config.rx_filter); 457 458 /* reserved for future extensions */ 459 if (config.flags) 460 return -EINVAL; 461 462 if (config.tx_type != HWTSTAMP_TX_OFF && 463 config.tx_type != HWTSTAMP_TX_ON) 464 return -ERANGE; 465 466 if (priv->adv_ts) { 467 switch (config.rx_filter) { 468 case HWTSTAMP_FILTER_NONE: 469 /* time stamp no incoming packet at all */ 470 config.rx_filter = HWTSTAMP_FILTER_NONE; 471 break; 472 473 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 474 /* PTP v1, UDP, any kind of event packet */ 475 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 476 /* take time stamp for all event messages */ 477 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 478 479 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 480 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 481 break; 482 483 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 484 /* PTP v1, UDP, Sync packet */ 485 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 486 /* take time stamp for SYNC messages only */ 487 ts_event_en = PTP_TCR_TSEVNTENA; 488 489 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 490 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 491 break; 492 493 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 494 /* PTP v1, UDP, Delay_req packet */ 495 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 496 /* take time stamp for Delay_Req messages only */ 497 ts_master_en = PTP_TCR_TSMSTRENA; 498 ts_event_en = PTP_TCR_TSEVNTENA; 499 500 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 501 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 502 break; 503 504 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 505 /* PTP v2, UDP, any kind of event packet */ 506 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 507 ptp_v2 = PTP_TCR_TSVER2ENA; 508 /* take time stamp for all event messages */ 509 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 510 511 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 512 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 513 break; 514 515 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 516 /* PTP v2, UDP, Sync packet */ 517 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 518 ptp_v2 = PTP_TCR_TSVER2ENA; 519 /* take time stamp for SYNC messages only */ 520 ts_event_en = PTP_TCR_TSEVNTENA; 521 522 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 523 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 524 break; 525 526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 527 /* PTP v2, UDP, Delay_req packet */ 528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 529 ptp_v2 = PTP_TCR_TSVER2ENA; 530 /* take time stamp for Delay_Req messages only */ 531 ts_master_en = PTP_TCR_TSMSTRENA; 532 ts_event_en = PTP_TCR_TSEVNTENA; 533 534 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 535 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 536 break; 537 538 case HWTSTAMP_FILTER_PTP_V2_EVENT: 539 /* PTP v2/802.AS1 any layer, any kind of event packet */ 540 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 541 ptp_v2 = PTP_TCR_TSVER2ENA; 542 /* take time stamp for all event messages */ 543 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 544 545 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 546 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 547 ptp_over_ethernet = PTP_TCR_TSIPENA; 548 break; 549 550 case HWTSTAMP_FILTER_PTP_V2_SYNC: 551 /* PTP v2/802.AS1, any layer, Sync packet */ 552 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 553 ptp_v2 = PTP_TCR_TSVER2ENA; 554 /* take time stamp for SYNC messages only */ 555 ts_event_en = PTP_TCR_TSEVNTENA; 556 557 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 558 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 559 ptp_over_ethernet = PTP_TCR_TSIPENA; 560 break; 561 562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 563 /* PTP v2/802.AS1, any layer, Delay_req packet */ 564 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 565 ptp_v2 = PTP_TCR_TSVER2ENA; 566 /* take time stamp for Delay_Req messages only */ 567 ts_master_en = PTP_TCR_TSMSTRENA; 568 ts_event_en = PTP_TCR_TSEVNTENA; 569 570 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 571 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 572 ptp_over_ethernet = PTP_TCR_TSIPENA; 573 break; 574 575 case HWTSTAMP_FILTER_ALL: 576 /* time stamp any incoming packet */ 577 config.rx_filter = HWTSTAMP_FILTER_ALL; 578 tstamp_all = PTP_TCR_TSENALL; 579 break; 580 581 default: 582 return -ERANGE; 583 } 584 } else { 585 switch (config.rx_filter) { 586 case HWTSTAMP_FILTER_NONE: 587 config.rx_filter = HWTSTAMP_FILTER_NONE; 588 break; 589 default: 590 /* PTP v1, UDP, any kind of event packet */ 591 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 592 break; 593 } 594 } 595 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 596 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 597 598 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 599 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); 600 else { 601 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 602 tstamp_all | ptp_v2 | ptp_over_ethernet | 603 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 604 ts_master_en | snap_type_sel); 605 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); 606 607 /* program Sub Second Increment reg */ 608 sec_inc = priv->hw->ptp->config_sub_second_increment( 609 priv->ptpaddr, priv->clk_ptp_rate, 610 priv->plat->has_gmac4); 611 temp = div_u64(1000000000ULL, sec_inc); 612 613 /* calculate default added value: 614 * formula is : 615 * addend = (2^32)/freq_div_ratio; 616 * where, freq_div_ratio = 1e9ns/sec_inc 617 */ 618 temp = (u64)(temp << 32); 619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 620 priv->hw->ptp->config_addend(priv->ptpaddr, 621 priv->default_addend); 622 623 /* initialize system time */ 624 ktime_get_real_ts64(&now); 625 626 /* lower 32 bits of tv_sec are safe until y2106 */ 627 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, 628 now.tv_nsec); 629 } 630 631 return copy_to_user(ifr->ifr_data, &config, 632 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 633 } 634 635 /** 636 * stmmac_init_ptp - init PTP 637 * @priv: driver private structure 638 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 639 * This is done by looking at the HW cap. register. 640 * This function also registers the ptp driver. 641 */ 642 static int stmmac_init_ptp(struct stmmac_priv *priv) 643 { 644 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 645 return -EOPNOTSUPP; 646 647 /* Fall-back to main clock in case of no PTP ref is passed */ 648 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 649 if (IS_ERR(priv->clk_ptp_ref)) { 650 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 651 priv->clk_ptp_ref = NULL; 652 netdev_dbg(priv->dev, "PTP uses main clock\n"); 653 } else { 654 clk_prepare_enable(priv->clk_ptp_ref); 655 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 656 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); 657 } 658 659 priv->adv_ts = 0; 660 /* Check if adv_ts can be enabled for dwmac 4.x core */ 661 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) 662 priv->adv_ts = 1; 663 /* Dwmac 3.x core with extend_desc can support adv_ts */ 664 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 665 priv->adv_ts = 1; 666 667 if (priv->dma_cap.time_stamp) 668 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 669 670 if (priv->adv_ts) 671 netdev_info(priv->dev, 672 "IEEE 1588-2008 Advanced Timestamp supported\n"); 673 674 priv->hw->ptp = &stmmac_ptp; 675 priv->hwts_tx_en = 0; 676 priv->hwts_rx_en = 0; 677 678 stmmac_ptp_register(priv); 679 680 return 0; 681 } 682 683 static void stmmac_release_ptp(struct stmmac_priv *priv) 684 { 685 if (priv->clk_ptp_ref) 686 clk_disable_unprepare(priv->clk_ptp_ref); 687 stmmac_ptp_unregister(priv); 688 } 689 690 /** 691 * stmmac_adjust_link - adjusts the link parameters 692 * @dev: net device structure 693 * Description: this is the helper called by the physical abstraction layer 694 * drivers to communicate the phy link status. According the speed and duplex 695 * this driver can invoke registered glue-logic as well. 696 * It also invoke the eee initialization because it could happen when switch 697 * on different networks (that are eee capable). 698 */ 699 static void stmmac_adjust_link(struct net_device *dev) 700 { 701 struct stmmac_priv *priv = netdev_priv(dev); 702 struct phy_device *phydev = dev->phydev; 703 unsigned long flags; 704 int new_state = 0; 705 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 706 707 if (phydev == NULL) 708 return; 709 710 spin_lock_irqsave(&priv->lock, flags); 711 712 if (phydev->link) { 713 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 714 715 /* Now we make sure that we can be in full duplex mode. 716 * If not, we operate in half-duplex mode. */ 717 if (phydev->duplex != priv->oldduplex) { 718 new_state = 1; 719 if (!(phydev->duplex)) 720 ctrl &= ~priv->hw->link.duplex; 721 else 722 ctrl |= priv->hw->link.duplex; 723 priv->oldduplex = phydev->duplex; 724 } 725 /* Flow Control operation */ 726 if (phydev->pause) 727 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 728 fc, pause_time); 729 730 if (phydev->speed != priv->speed) { 731 new_state = 1; 732 switch (phydev->speed) { 733 case 1000: 734 if (likely((priv->plat->has_gmac) || 735 (priv->plat->has_gmac4))) 736 ctrl &= ~priv->hw->link.port; 737 stmmac_hw_fix_mac_speed(priv); 738 break; 739 case 100: 740 case 10: 741 if (likely((priv->plat->has_gmac) || 742 (priv->plat->has_gmac4))) { 743 ctrl |= priv->hw->link.port; 744 if (phydev->speed == SPEED_100) { 745 ctrl |= priv->hw->link.speed; 746 } else { 747 ctrl &= ~(priv->hw->link.speed); 748 } 749 } else { 750 ctrl &= ~priv->hw->link.port; 751 } 752 stmmac_hw_fix_mac_speed(priv); 753 break; 754 default: 755 netif_warn(priv, link, priv->dev, 756 "Speed (%d) not 10/100\n", 757 phydev->speed); 758 break; 759 } 760 761 priv->speed = phydev->speed; 762 } 763 764 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 765 766 if (!priv->oldlink) { 767 new_state = 1; 768 priv->oldlink = 1; 769 } 770 } else if (priv->oldlink) { 771 new_state = 1; 772 priv->oldlink = 0; 773 priv->speed = 0; 774 priv->oldduplex = -1; 775 } 776 777 if (new_state && netif_msg_link(priv)) 778 phy_print_status(phydev); 779 780 spin_unlock_irqrestore(&priv->lock, flags); 781 782 if (phydev->is_pseudo_fixed_link) 783 /* Stop PHY layer to call the hook to adjust the link in case 784 * of a switch is attached to the stmmac driver. 785 */ 786 phydev->irq = PHY_IGNORE_INTERRUPT; 787 else 788 /* At this stage, init the EEE if supported. 789 * Never called in case of fixed_link. 790 */ 791 priv->eee_enabled = stmmac_eee_init(priv); 792 } 793 794 /** 795 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 796 * @priv: driver private structure 797 * Description: this is to verify if the HW supports the PCS. 798 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 799 * configured for the TBI, RTBI, or SGMII PHY interface. 800 */ 801 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 802 { 803 int interface = priv->plat->interface; 804 805 if (priv->dma_cap.pcs) { 806 if ((interface == PHY_INTERFACE_MODE_RGMII) || 807 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 808 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 809 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 810 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 811 priv->hw->pcs = STMMAC_PCS_RGMII; 812 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 813 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 814 priv->hw->pcs = STMMAC_PCS_SGMII; 815 } 816 } 817 } 818 819 /** 820 * stmmac_init_phy - PHY initialization 821 * @dev: net device structure 822 * Description: it initializes the driver's PHY state, and attaches the PHY 823 * to the mac driver. 824 * Return value: 825 * 0 on success 826 */ 827 static int stmmac_init_phy(struct net_device *dev) 828 { 829 struct stmmac_priv *priv = netdev_priv(dev); 830 struct phy_device *phydev; 831 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 832 char bus_id[MII_BUS_ID_SIZE]; 833 int interface = priv->plat->interface; 834 int max_speed = priv->plat->max_speed; 835 priv->oldlink = 0; 836 priv->speed = 0; 837 priv->oldduplex = -1; 838 839 if (priv->plat->phy_node) { 840 phydev = of_phy_connect(dev, priv->plat->phy_node, 841 &stmmac_adjust_link, 0, interface); 842 } else { 843 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 844 priv->plat->bus_id); 845 846 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 847 priv->plat->phy_addr); 848 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, 849 phy_id_fmt); 850 851 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 852 interface); 853 } 854 855 if (IS_ERR_OR_NULL(phydev)) { 856 netdev_err(priv->dev, "Could not attach to PHY\n"); 857 if (!phydev) 858 return -ENODEV; 859 860 return PTR_ERR(phydev); 861 } 862 863 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 864 if ((interface == PHY_INTERFACE_MODE_MII) || 865 (interface == PHY_INTERFACE_MODE_RMII) || 866 (max_speed < 1000 && max_speed > 0)) 867 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 868 SUPPORTED_1000baseT_Full); 869 870 /* 871 * Broken HW is sometimes missing the pull-up resistor on the 872 * MDIO line, which results in reads to non-existent devices returning 873 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 874 * device as well. 875 * Note: phydev->phy_id is the result of reading the UID PHY registers. 876 */ 877 if (!priv->plat->phy_node && phydev->phy_id == 0) { 878 phy_disconnect(phydev); 879 return -ENODEV; 880 } 881 882 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid 883 * subsequent PHY polling, make sure we force a link transition if 884 * we have a UP/DOWN/UP transition 885 */ 886 if (phydev->is_pseudo_fixed_link) 887 phydev->irq = PHY_POLL; 888 889 netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n", 890 __func__, phydev->phy_id, phydev->link); 891 892 return 0; 893 } 894 895 static void stmmac_display_rings(struct stmmac_priv *priv) 896 { 897 void *head_rx, *head_tx; 898 899 if (priv->extend_desc) { 900 head_rx = (void *)priv->dma_erx; 901 head_tx = (void *)priv->dma_etx; 902 } else { 903 head_rx = (void *)priv->dma_rx; 904 head_tx = (void *)priv->dma_tx; 905 } 906 907 /* Display Rx ring */ 908 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); 909 /* Display Tx ring */ 910 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); 911 } 912 913 static int stmmac_set_bfsize(int mtu, int bufsize) 914 { 915 int ret = bufsize; 916 917 if (mtu >= BUF_SIZE_4KiB) 918 ret = BUF_SIZE_8KiB; 919 else if (mtu >= BUF_SIZE_2KiB) 920 ret = BUF_SIZE_4KiB; 921 else if (mtu > DEFAULT_BUFSIZE) 922 ret = BUF_SIZE_2KiB; 923 else 924 ret = DEFAULT_BUFSIZE; 925 926 return ret; 927 } 928 929 /** 930 * stmmac_clear_descriptors - clear descriptors 931 * @priv: driver private structure 932 * Description: this function is called to clear the tx and rx descriptors 933 * in case of both basic and extended descriptors are used. 934 */ 935 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 936 { 937 int i; 938 939 /* Clear the Rx/Tx descriptors */ 940 for (i = 0; i < DMA_RX_SIZE; i++) 941 if (priv->extend_desc) 942 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 943 priv->use_riwt, priv->mode, 944 (i == DMA_RX_SIZE - 1)); 945 else 946 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 947 priv->use_riwt, priv->mode, 948 (i == DMA_RX_SIZE - 1)); 949 for (i = 0; i < DMA_TX_SIZE; i++) 950 if (priv->extend_desc) 951 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 952 priv->mode, 953 (i == DMA_TX_SIZE - 1)); 954 else 955 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 956 priv->mode, 957 (i == DMA_TX_SIZE - 1)); 958 } 959 960 /** 961 * stmmac_init_rx_buffers - init the RX descriptor buffer. 962 * @priv: driver private structure 963 * @p: descriptor pointer 964 * @i: descriptor index 965 * @flags: gfp flag. 966 * Description: this function is called to allocate a receive buffer, perform 967 * the DMA mapping and init the descriptor. 968 */ 969 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 970 int i, gfp_t flags) 971 { 972 struct sk_buff *skb; 973 974 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 975 if (!skb) { 976 netdev_err(priv->dev, 977 "%s: Rx init fails; skb is NULL\n", __func__); 978 return -ENOMEM; 979 } 980 priv->rx_skbuff[i] = skb; 981 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 982 priv->dma_buf_sz, 983 DMA_FROM_DEVICE); 984 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 985 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 986 dev_kfree_skb_any(skb); 987 return -EINVAL; 988 } 989 990 if (priv->synopsys_id >= DWMAC_CORE_4_00) 991 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]); 992 else 993 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]); 994 995 if ((priv->hw->mode->init_desc3) && 996 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 997 priv->hw->mode->init_desc3(p); 998 999 return 0; 1000 } 1001 1002 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 1003 { 1004 if (priv->rx_skbuff[i]) { 1005 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1006 priv->dma_buf_sz, DMA_FROM_DEVICE); 1007 dev_kfree_skb_any(priv->rx_skbuff[i]); 1008 } 1009 priv->rx_skbuff[i] = NULL; 1010 } 1011 1012 /** 1013 * init_dma_desc_rings - init the RX/TX descriptor rings 1014 * @dev: net device structure 1015 * @flags: gfp flag. 1016 * Description: this function initializes the DMA RX/TX descriptors 1017 * and allocates the socket buffers. It suppors the chained and ring 1018 * modes. 1019 */ 1020 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1021 { 1022 int i; 1023 struct stmmac_priv *priv = netdev_priv(dev); 1024 unsigned int bfsize = 0; 1025 int ret = -ENOMEM; 1026 1027 if (priv->hw->mode->set_16kib_bfsize) 1028 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1029 1030 if (bfsize < BUF_SIZE_16KiB) 1031 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1032 1033 priv->dma_buf_sz = bfsize; 1034 1035 netif_dbg(priv, probe, priv->dev, 1036 "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", 1037 __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy); 1038 1039 /* RX INITIALIZATION */ 1040 netif_dbg(priv, probe, priv->dev, 1041 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1042 1043 for (i = 0; i < DMA_RX_SIZE; i++) { 1044 struct dma_desc *p; 1045 if (priv->extend_desc) 1046 p = &((priv->dma_erx + i)->basic); 1047 else 1048 p = priv->dma_rx + i; 1049 1050 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1051 if (ret) 1052 goto err_init_rx_buffers; 1053 1054 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", 1055 priv->rx_skbuff[i], priv->rx_skbuff[i]->data, 1056 (unsigned int)priv->rx_skbuff_dma[i]); 1057 } 1058 priv->cur_rx = 0; 1059 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1060 buf_sz = bfsize; 1061 1062 /* Setup the chained descriptor addresses */ 1063 if (priv->mode == STMMAC_CHAIN_MODE) { 1064 if (priv->extend_desc) { 1065 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1066 DMA_RX_SIZE, 1); 1067 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1068 DMA_TX_SIZE, 1); 1069 } else { 1070 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1071 DMA_RX_SIZE, 0); 1072 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1073 DMA_TX_SIZE, 0); 1074 } 1075 } 1076 1077 /* TX INITIALIZATION */ 1078 for (i = 0; i < DMA_TX_SIZE; i++) { 1079 struct dma_desc *p; 1080 if (priv->extend_desc) 1081 p = &((priv->dma_etx + i)->basic); 1082 else 1083 p = priv->dma_tx + i; 1084 1085 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1086 p->des0 = 0; 1087 p->des1 = 0; 1088 p->des2 = 0; 1089 p->des3 = 0; 1090 } else { 1091 p->des2 = 0; 1092 } 1093 1094 priv->tx_skbuff_dma[i].buf = 0; 1095 priv->tx_skbuff_dma[i].map_as_page = false; 1096 priv->tx_skbuff_dma[i].len = 0; 1097 priv->tx_skbuff_dma[i].last_segment = false; 1098 priv->tx_skbuff[i] = NULL; 1099 } 1100 1101 priv->dirty_tx = 0; 1102 priv->cur_tx = 0; 1103 netdev_reset_queue(priv->dev); 1104 1105 stmmac_clear_descriptors(priv); 1106 1107 if (netif_msg_hw(priv)) 1108 stmmac_display_rings(priv); 1109 1110 return 0; 1111 err_init_rx_buffers: 1112 while (--i >= 0) 1113 stmmac_free_rx_buffers(priv, i); 1114 return ret; 1115 } 1116 1117 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1118 { 1119 int i; 1120 1121 for (i = 0; i < DMA_RX_SIZE; i++) 1122 stmmac_free_rx_buffers(priv, i); 1123 } 1124 1125 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1126 { 1127 int i; 1128 1129 for (i = 0; i < DMA_TX_SIZE; i++) { 1130 struct dma_desc *p; 1131 1132 if (priv->extend_desc) 1133 p = &((priv->dma_etx + i)->basic); 1134 else 1135 p = priv->dma_tx + i; 1136 1137 if (priv->tx_skbuff_dma[i].buf) { 1138 if (priv->tx_skbuff_dma[i].map_as_page) 1139 dma_unmap_page(priv->device, 1140 priv->tx_skbuff_dma[i].buf, 1141 priv->tx_skbuff_dma[i].len, 1142 DMA_TO_DEVICE); 1143 else 1144 dma_unmap_single(priv->device, 1145 priv->tx_skbuff_dma[i].buf, 1146 priv->tx_skbuff_dma[i].len, 1147 DMA_TO_DEVICE); 1148 } 1149 1150 if (priv->tx_skbuff[i] != NULL) { 1151 dev_kfree_skb_any(priv->tx_skbuff[i]); 1152 priv->tx_skbuff[i] = NULL; 1153 priv->tx_skbuff_dma[i].buf = 0; 1154 priv->tx_skbuff_dma[i].map_as_page = false; 1155 } 1156 } 1157 } 1158 1159 /** 1160 * alloc_dma_desc_resources - alloc TX/RX resources. 1161 * @priv: private structure 1162 * Description: according to which descriptor can be used (extend or basic) 1163 * this function allocates the resources for TX and RX paths. In case of 1164 * reception, for example, it pre-allocated the RX socket buffer in order to 1165 * allow zero-copy mechanism. 1166 */ 1167 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1168 { 1169 int ret = -ENOMEM; 1170 1171 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), 1172 GFP_KERNEL); 1173 if (!priv->rx_skbuff_dma) 1174 return -ENOMEM; 1175 1176 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), 1177 GFP_KERNEL); 1178 if (!priv->rx_skbuff) 1179 goto err_rx_skbuff; 1180 1181 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1182 sizeof(*priv->tx_skbuff_dma), 1183 GFP_KERNEL); 1184 if (!priv->tx_skbuff_dma) 1185 goto err_tx_skbuff_dma; 1186 1187 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), 1188 GFP_KERNEL); 1189 if (!priv->tx_skbuff) 1190 goto err_tx_skbuff; 1191 1192 if (priv->extend_desc) { 1193 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1194 sizeof(struct 1195 dma_extended_desc), 1196 &priv->dma_rx_phy, 1197 GFP_KERNEL); 1198 if (!priv->dma_erx) 1199 goto err_dma; 1200 1201 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1202 sizeof(struct 1203 dma_extended_desc), 1204 &priv->dma_tx_phy, 1205 GFP_KERNEL); 1206 if (!priv->dma_etx) { 1207 dma_free_coherent(priv->device, DMA_RX_SIZE * 1208 sizeof(struct dma_extended_desc), 1209 priv->dma_erx, priv->dma_rx_phy); 1210 goto err_dma; 1211 } 1212 } else { 1213 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1214 sizeof(struct dma_desc), 1215 &priv->dma_rx_phy, 1216 GFP_KERNEL); 1217 if (!priv->dma_rx) 1218 goto err_dma; 1219 1220 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1221 sizeof(struct dma_desc), 1222 &priv->dma_tx_phy, 1223 GFP_KERNEL); 1224 if (!priv->dma_tx) { 1225 dma_free_coherent(priv->device, DMA_RX_SIZE * 1226 sizeof(struct dma_desc), 1227 priv->dma_rx, priv->dma_rx_phy); 1228 goto err_dma; 1229 } 1230 } 1231 1232 return 0; 1233 1234 err_dma: 1235 kfree(priv->tx_skbuff); 1236 err_tx_skbuff: 1237 kfree(priv->tx_skbuff_dma); 1238 err_tx_skbuff_dma: 1239 kfree(priv->rx_skbuff); 1240 err_rx_skbuff: 1241 kfree(priv->rx_skbuff_dma); 1242 return ret; 1243 } 1244 1245 static void free_dma_desc_resources(struct stmmac_priv *priv) 1246 { 1247 /* Release the DMA TX/RX socket buffers */ 1248 dma_free_rx_skbufs(priv); 1249 dma_free_tx_skbufs(priv); 1250 1251 /* Free DMA regions of consistent memory previously allocated */ 1252 if (!priv->extend_desc) { 1253 dma_free_coherent(priv->device, 1254 DMA_TX_SIZE * sizeof(struct dma_desc), 1255 priv->dma_tx, priv->dma_tx_phy); 1256 dma_free_coherent(priv->device, 1257 DMA_RX_SIZE * sizeof(struct dma_desc), 1258 priv->dma_rx, priv->dma_rx_phy); 1259 } else { 1260 dma_free_coherent(priv->device, DMA_TX_SIZE * 1261 sizeof(struct dma_extended_desc), 1262 priv->dma_etx, priv->dma_tx_phy); 1263 dma_free_coherent(priv->device, DMA_RX_SIZE * 1264 sizeof(struct dma_extended_desc), 1265 priv->dma_erx, priv->dma_rx_phy); 1266 } 1267 kfree(priv->rx_skbuff_dma); 1268 kfree(priv->rx_skbuff); 1269 kfree(priv->tx_skbuff_dma); 1270 kfree(priv->tx_skbuff); 1271 } 1272 1273 /** 1274 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1275 * @priv: driver private structure 1276 * Description: It is used for enabling the rx queues in the MAC 1277 */ 1278 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1279 { 1280 int rx_count = priv->dma_cap.number_rx_queues; 1281 int queue = 0; 1282 1283 /* If GMAC does not have multiple queues, then this is not necessary*/ 1284 if (rx_count == 1) 1285 return; 1286 1287 /** 1288 * If the core is synthesized with multiple rx queues / multiple 1289 * dma channels, then rx queues will be disabled by default. 1290 * For now only rx queue 0 is enabled. 1291 */ 1292 priv->hw->mac->rx_queue_enable(priv->hw, queue); 1293 } 1294 1295 /** 1296 * stmmac_dma_operation_mode - HW DMA operation mode 1297 * @priv: driver private structure 1298 * Description: it is used for configuring the DMA operation mode register in 1299 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1300 */ 1301 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1302 { 1303 int rxfifosz = priv->plat->rx_fifo_size; 1304 1305 if (priv->plat->force_thresh_dma_mode) 1306 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); 1307 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1308 /* 1309 * In case of GMAC, SF mode can be enabled 1310 * to perform the TX COE in HW. This depends on: 1311 * 1) TX COE if actually supported 1312 * 2) There is no bugged Jumbo frame support 1313 * that needs to not insert csum in the TDES. 1314 */ 1315 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, 1316 rxfifosz); 1317 priv->xstats.threshold = SF_DMA_MODE; 1318 } else 1319 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, 1320 rxfifosz); 1321 } 1322 1323 /** 1324 * stmmac_tx_clean - to manage the transmission completion 1325 * @priv: driver private structure 1326 * Description: it reclaims the transmit resources after transmission completes. 1327 */ 1328 static void stmmac_tx_clean(struct stmmac_priv *priv) 1329 { 1330 unsigned int bytes_compl = 0, pkts_compl = 0; 1331 unsigned int entry = priv->dirty_tx; 1332 1333 netif_tx_lock(priv->dev); 1334 1335 priv->xstats.tx_clean++; 1336 1337 while (entry != priv->cur_tx) { 1338 struct sk_buff *skb = priv->tx_skbuff[entry]; 1339 struct dma_desc *p; 1340 int status; 1341 1342 if (priv->extend_desc) 1343 p = (struct dma_desc *)(priv->dma_etx + entry); 1344 else 1345 p = priv->dma_tx + entry; 1346 1347 status = priv->hw->desc->tx_status(&priv->dev->stats, 1348 &priv->xstats, p, 1349 priv->ioaddr); 1350 /* Check if the descriptor is owned by the DMA */ 1351 if (unlikely(status & tx_dma_own)) 1352 break; 1353 1354 /* Just consider the last segment and ...*/ 1355 if (likely(!(status & tx_not_ls))) { 1356 /* ... verify the status error condition */ 1357 if (unlikely(status & tx_err)) { 1358 priv->dev->stats.tx_errors++; 1359 } else { 1360 priv->dev->stats.tx_packets++; 1361 priv->xstats.tx_pkt_n++; 1362 } 1363 stmmac_get_tx_hwtstamp(priv, p, skb); 1364 } 1365 1366 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1367 if (priv->tx_skbuff_dma[entry].map_as_page) 1368 dma_unmap_page(priv->device, 1369 priv->tx_skbuff_dma[entry].buf, 1370 priv->tx_skbuff_dma[entry].len, 1371 DMA_TO_DEVICE); 1372 else 1373 dma_unmap_single(priv->device, 1374 priv->tx_skbuff_dma[entry].buf, 1375 priv->tx_skbuff_dma[entry].len, 1376 DMA_TO_DEVICE); 1377 priv->tx_skbuff_dma[entry].buf = 0; 1378 priv->tx_skbuff_dma[entry].len = 0; 1379 priv->tx_skbuff_dma[entry].map_as_page = false; 1380 } 1381 1382 if (priv->hw->mode->clean_desc3) 1383 priv->hw->mode->clean_desc3(priv, p); 1384 1385 priv->tx_skbuff_dma[entry].last_segment = false; 1386 priv->tx_skbuff_dma[entry].is_jumbo = false; 1387 1388 if (likely(skb != NULL)) { 1389 pkts_compl++; 1390 bytes_compl += skb->len; 1391 dev_consume_skb_any(skb); 1392 priv->tx_skbuff[entry] = NULL; 1393 } 1394 1395 priv->hw->desc->release_tx_desc(p, priv->mode); 1396 1397 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1398 } 1399 priv->dirty_tx = entry; 1400 1401 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1402 1403 if (unlikely(netif_queue_stopped(priv->dev) && 1404 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { 1405 netif_dbg(priv, tx_done, priv->dev, 1406 "%s: restart transmit\n", __func__); 1407 netif_wake_queue(priv->dev); 1408 } 1409 1410 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1411 stmmac_enable_eee_mode(priv); 1412 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1413 } 1414 netif_tx_unlock(priv->dev); 1415 } 1416 1417 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1418 { 1419 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1420 } 1421 1422 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1423 { 1424 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1425 } 1426 1427 /** 1428 * stmmac_tx_err - to manage the tx error 1429 * @priv: driver private structure 1430 * Description: it cleans the descriptors and restarts the transmission 1431 * in case of transmission errors. 1432 */ 1433 static void stmmac_tx_err(struct stmmac_priv *priv) 1434 { 1435 int i; 1436 netif_stop_queue(priv->dev); 1437 1438 priv->hw->dma->stop_tx(priv->ioaddr); 1439 dma_free_tx_skbufs(priv); 1440 for (i = 0; i < DMA_TX_SIZE; i++) 1441 if (priv->extend_desc) 1442 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1443 priv->mode, 1444 (i == DMA_TX_SIZE - 1)); 1445 else 1446 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1447 priv->mode, 1448 (i == DMA_TX_SIZE - 1)); 1449 priv->dirty_tx = 0; 1450 priv->cur_tx = 0; 1451 netdev_reset_queue(priv->dev); 1452 priv->hw->dma->start_tx(priv->ioaddr); 1453 1454 priv->dev->stats.tx_errors++; 1455 netif_wake_queue(priv->dev); 1456 } 1457 1458 /** 1459 * stmmac_dma_interrupt - DMA ISR 1460 * @priv: driver private structure 1461 * Description: this is the DMA ISR. It is called by the main ISR. 1462 * It calls the dwmac dma routine and schedule poll method in case of some 1463 * work can be done. 1464 */ 1465 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1466 { 1467 int status; 1468 int rxfifosz = priv->plat->rx_fifo_size; 1469 1470 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1471 if (likely((status & handle_rx)) || (status & handle_tx)) { 1472 if (likely(napi_schedule_prep(&priv->napi))) { 1473 stmmac_disable_dma_irq(priv); 1474 __napi_schedule(&priv->napi); 1475 } 1476 } 1477 if (unlikely(status & tx_hard_error_bump_tc)) { 1478 /* Try to bump up the dma threshold on this failure */ 1479 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1480 (tc <= 256)) { 1481 tc += 64; 1482 if (priv->plat->force_thresh_dma_mode) 1483 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, 1484 rxfifosz); 1485 else 1486 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1487 SF_DMA_MODE, rxfifosz); 1488 priv->xstats.threshold = tc; 1489 } 1490 } else if (unlikely(status == tx_hard_error)) 1491 stmmac_tx_err(priv); 1492 } 1493 1494 /** 1495 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1496 * @priv: driver private structure 1497 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1498 */ 1499 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1500 { 1501 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1502 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1503 1504 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1505 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; 1506 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; 1507 } else { 1508 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; 1509 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; 1510 } 1511 1512 dwmac_mmc_intr_all_mask(priv->mmcaddr); 1513 1514 if (priv->dma_cap.rmon) { 1515 dwmac_mmc_ctrl(priv->mmcaddr, mode); 1516 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1517 } else 1518 netdev_info(priv->dev, "No MAC Management Counters available\n"); 1519 } 1520 1521 /** 1522 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1523 * @priv: driver private structure 1524 * Description: select the Enhanced/Alternate or Normal descriptors. 1525 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1526 * supported by the HW capability register. 1527 */ 1528 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1529 { 1530 if (priv->plat->enh_desc) { 1531 dev_info(priv->device, "Enhanced/Alternate descriptors\n"); 1532 1533 /* GMAC older than 3.50 has no extended descriptors */ 1534 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1535 dev_info(priv->device, "Enabled extended descriptors\n"); 1536 priv->extend_desc = 1; 1537 } else 1538 dev_warn(priv->device, "Extended descriptors not supported\n"); 1539 1540 priv->hw->desc = &enh_desc_ops; 1541 } else { 1542 dev_info(priv->device, "Normal descriptors\n"); 1543 priv->hw->desc = &ndesc_ops; 1544 } 1545 } 1546 1547 /** 1548 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1549 * @priv: driver private structure 1550 * Description: 1551 * new GMAC chip generations have a new register to indicate the 1552 * presence of the optional feature/functions. 1553 * This can be also used to override the value passed through the 1554 * platform and necessary for old MAC10/100 and GMAC chips. 1555 */ 1556 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1557 { 1558 u32 ret = 0; 1559 1560 if (priv->hw->dma->get_hw_feature) { 1561 priv->hw->dma->get_hw_feature(priv->ioaddr, 1562 &priv->dma_cap); 1563 ret = 1; 1564 } 1565 1566 return ret; 1567 } 1568 1569 /** 1570 * stmmac_check_ether_addr - check if the MAC addr is valid 1571 * @priv: driver private structure 1572 * Description: 1573 * it is to verify if the MAC address is valid, in case of failures it 1574 * generates a random MAC address 1575 */ 1576 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1577 { 1578 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1579 priv->hw->mac->get_umac_addr(priv->hw, 1580 priv->dev->dev_addr, 0); 1581 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1582 eth_hw_addr_random(priv->dev); 1583 netdev_info(priv->dev, "device MAC address %pM\n", 1584 priv->dev->dev_addr); 1585 } 1586 } 1587 1588 /** 1589 * stmmac_init_dma_engine - DMA init. 1590 * @priv: driver private structure 1591 * Description: 1592 * It inits the DMA invoking the specific MAC/GMAC callback. 1593 * Some DMA parameters can be passed from the platform; 1594 * in case of these are not passed a default is kept for the MAC or GMAC. 1595 */ 1596 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1597 { 1598 int atds = 0; 1599 int ret = 0; 1600 1601 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 1602 dev_err(priv->device, "Invalid DMA configuration\n"); 1603 return -EINVAL; 1604 } 1605 1606 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1607 atds = 1; 1608 1609 ret = priv->hw->dma->reset(priv->ioaddr); 1610 if (ret) { 1611 dev_err(priv->device, "Failed to reset the dma\n"); 1612 return ret; 1613 } 1614 1615 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg, 1616 priv->dma_tx_phy, priv->dma_rx_phy, atds); 1617 1618 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1619 priv->rx_tail_addr = priv->dma_rx_phy + 1620 (DMA_RX_SIZE * sizeof(struct dma_desc)); 1621 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, 1622 STMMAC_CHAN0); 1623 1624 priv->tx_tail_addr = priv->dma_tx_phy + 1625 (DMA_TX_SIZE * sizeof(struct dma_desc)); 1626 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 1627 STMMAC_CHAN0); 1628 } 1629 1630 if (priv->plat->axi && priv->hw->dma->axi) 1631 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); 1632 1633 return ret; 1634 } 1635 1636 /** 1637 * stmmac_tx_timer - mitigation sw timer for tx. 1638 * @data: data pointer 1639 * Description: 1640 * This is the timer handler to directly invoke the stmmac_tx_clean. 1641 */ 1642 static void stmmac_tx_timer(unsigned long data) 1643 { 1644 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1645 1646 stmmac_tx_clean(priv); 1647 } 1648 1649 /** 1650 * stmmac_init_tx_coalesce - init tx mitigation options. 1651 * @priv: driver private structure 1652 * Description: 1653 * This inits the transmit coalesce parameters: i.e. timer rate, 1654 * timer handler and default threshold used for enabling the 1655 * interrupt on completion bit. 1656 */ 1657 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1658 { 1659 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1660 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1661 init_timer(&priv->txtimer); 1662 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1663 priv->txtimer.data = (unsigned long)priv; 1664 priv->txtimer.function = stmmac_tx_timer; 1665 add_timer(&priv->txtimer); 1666 } 1667 1668 /** 1669 * stmmac_hw_setup - setup mac in a usable state. 1670 * @dev : pointer to the device structure. 1671 * Description: 1672 * this is the main function to setup the HW in a usable state because the 1673 * dma engine is reset, the core registers are configured (e.g. AXI, 1674 * Checksum features, timers). The DMA is ready to start receiving and 1675 * transmitting. 1676 * Return value: 1677 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1678 * file on failure. 1679 */ 1680 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1681 { 1682 struct stmmac_priv *priv = netdev_priv(dev); 1683 int ret; 1684 1685 /* DMA initialization and SW reset */ 1686 ret = stmmac_init_dma_engine(priv); 1687 if (ret < 0) { 1688 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 1689 __func__); 1690 return ret; 1691 } 1692 1693 /* Copy the MAC addr into the HW */ 1694 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1695 1696 /* If required, perform hw setup of the bus. */ 1697 if (priv->plat->bus_setup) 1698 priv->plat->bus_setup(priv->ioaddr); 1699 1700 /* PS and related bits will be programmed according to the speed */ 1701 if (priv->hw->pcs) { 1702 int speed = priv->plat->mac_port_sel_speed; 1703 1704 if ((speed == SPEED_10) || (speed == SPEED_100) || 1705 (speed == SPEED_1000)) { 1706 priv->hw->ps = speed; 1707 } else { 1708 dev_warn(priv->device, "invalid port speed\n"); 1709 priv->hw->ps = 0; 1710 } 1711 } 1712 1713 /* Initialize the MAC Core */ 1714 priv->hw->mac->core_init(priv->hw, dev->mtu); 1715 1716 /* Initialize MAC RX Queues */ 1717 if (priv->hw->mac->rx_queue_enable) 1718 stmmac_mac_enable_rx_queues(priv); 1719 1720 ret = priv->hw->mac->rx_ipc(priv->hw); 1721 if (!ret) { 1722 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 1723 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1724 priv->hw->rx_csum = 0; 1725 } 1726 1727 /* Enable the MAC Rx/Tx */ 1728 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1729 stmmac_dwmac4_set_mac(priv->ioaddr, true); 1730 else 1731 stmmac_set_mac(priv->ioaddr, true); 1732 1733 /* Set the HW DMA mode and the COE */ 1734 stmmac_dma_operation_mode(priv); 1735 1736 stmmac_mmc_setup(priv); 1737 1738 if (init_ptp) { 1739 ret = stmmac_init_ptp(priv); 1740 if (ret) 1741 netdev_warn(priv->dev, "fail to init PTP.\n"); 1742 } 1743 1744 #ifdef CONFIG_DEBUG_FS 1745 ret = stmmac_init_fs(dev); 1746 if (ret < 0) 1747 netdev_warn(priv->dev, "%s: failed debugFS registration\n", 1748 __func__); 1749 #endif 1750 /* Start the ball rolling... */ 1751 netdev_dbg(priv->dev, "DMA RX/TX processes started...\n"); 1752 priv->hw->dma->start_tx(priv->ioaddr); 1753 priv->hw->dma->start_rx(priv->ioaddr); 1754 1755 /* Dump DMA/MAC registers */ 1756 if (netif_msg_hw(priv)) { 1757 priv->hw->mac->dump_regs(priv->hw); 1758 priv->hw->dma->dump_regs(priv->ioaddr); 1759 } 1760 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1761 1762 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1763 priv->rx_riwt = MAX_DMA_RIWT; 1764 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1765 } 1766 1767 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) 1768 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); 1769 1770 /* set TX ring length */ 1771 if (priv->hw->dma->set_tx_ring_len) 1772 priv->hw->dma->set_tx_ring_len(priv->ioaddr, 1773 (DMA_TX_SIZE - 1)); 1774 /* set RX ring length */ 1775 if (priv->hw->dma->set_rx_ring_len) 1776 priv->hw->dma->set_rx_ring_len(priv->ioaddr, 1777 (DMA_RX_SIZE - 1)); 1778 /* Enable TSO */ 1779 if (priv->tso) 1780 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); 1781 1782 return 0; 1783 } 1784 1785 /** 1786 * stmmac_open - open entry point of the driver 1787 * @dev : pointer to the device structure. 1788 * Description: 1789 * This function is the open entry point of the driver. 1790 * Return value: 1791 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1792 * file on failure. 1793 */ 1794 static int stmmac_open(struct net_device *dev) 1795 { 1796 struct stmmac_priv *priv = netdev_priv(dev); 1797 int ret; 1798 1799 stmmac_check_ether_addr(priv); 1800 1801 if (priv->hw->pcs != STMMAC_PCS_RGMII && 1802 priv->hw->pcs != STMMAC_PCS_TBI && 1803 priv->hw->pcs != STMMAC_PCS_RTBI) { 1804 ret = stmmac_init_phy(dev); 1805 if (ret) { 1806 netdev_err(priv->dev, 1807 "%s: Cannot attach to PHY (error: %d)\n", 1808 __func__, ret); 1809 return ret; 1810 } 1811 } 1812 1813 /* Extra statistics */ 1814 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1815 priv->xstats.threshold = tc; 1816 1817 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1818 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 1819 1820 ret = alloc_dma_desc_resources(priv); 1821 if (ret < 0) { 1822 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 1823 __func__); 1824 goto dma_desc_error; 1825 } 1826 1827 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1828 if (ret < 0) { 1829 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 1830 __func__); 1831 goto init_error; 1832 } 1833 1834 ret = stmmac_hw_setup(dev, true); 1835 if (ret < 0) { 1836 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 1837 goto init_error; 1838 } 1839 1840 stmmac_init_tx_coalesce(priv); 1841 1842 if (dev->phydev) 1843 phy_start(dev->phydev); 1844 1845 /* Request the IRQ lines */ 1846 ret = request_irq(dev->irq, stmmac_interrupt, 1847 IRQF_SHARED, dev->name, dev); 1848 if (unlikely(ret < 0)) { 1849 netdev_err(priv->dev, 1850 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 1851 __func__, dev->irq, ret); 1852 goto init_error; 1853 } 1854 1855 /* Request the Wake IRQ in case of another line is used for WoL */ 1856 if (priv->wol_irq != dev->irq) { 1857 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1858 IRQF_SHARED, dev->name, dev); 1859 if (unlikely(ret < 0)) { 1860 netdev_err(priv->dev, 1861 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1862 __func__, priv->wol_irq, ret); 1863 goto wolirq_error; 1864 } 1865 } 1866 1867 /* Request the IRQ lines */ 1868 if (priv->lpi_irq > 0) { 1869 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1870 dev->name, dev); 1871 if (unlikely(ret < 0)) { 1872 netdev_err(priv->dev, 1873 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1874 __func__, priv->lpi_irq, ret); 1875 goto lpiirq_error; 1876 } 1877 } 1878 1879 napi_enable(&priv->napi); 1880 netif_start_queue(dev); 1881 1882 return 0; 1883 1884 lpiirq_error: 1885 if (priv->wol_irq != dev->irq) 1886 free_irq(priv->wol_irq, dev); 1887 wolirq_error: 1888 free_irq(dev->irq, dev); 1889 1890 init_error: 1891 free_dma_desc_resources(priv); 1892 dma_desc_error: 1893 if (dev->phydev) 1894 phy_disconnect(dev->phydev); 1895 1896 return ret; 1897 } 1898 1899 /** 1900 * stmmac_release - close entry point of the driver 1901 * @dev : device pointer. 1902 * Description: 1903 * This is the stop entry point of the driver. 1904 */ 1905 static int stmmac_release(struct net_device *dev) 1906 { 1907 struct stmmac_priv *priv = netdev_priv(dev); 1908 1909 if (priv->eee_enabled) 1910 del_timer_sync(&priv->eee_ctrl_timer); 1911 1912 /* Stop and disconnect the PHY */ 1913 if (dev->phydev) { 1914 phy_stop(dev->phydev); 1915 phy_disconnect(dev->phydev); 1916 } 1917 1918 netif_stop_queue(dev); 1919 1920 napi_disable(&priv->napi); 1921 1922 del_timer_sync(&priv->txtimer); 1923 1924 /* Free the IRQ lines */ 1925 free_irq(dev->irq, dev); 1926 if (priv->wol_irq != dev->irq) 1927 free_irq(priv->wol_irq, dev); 1928 if (priv->lpi_irq > 0) 1929 free_irq(priv->lpi_irq, dev); 1930 1931 /* Stop TX/RX DMA and clear the descriptors */ 1932 priv->hw->dma->stop_tx(priv->ioaddr); 1933 priv->hw->dma->stop_rx(priv->ioaddr); 1934 1935 /* Release and free the Rx/Tx resources */ 1936 free_dma_desc_resources(priv); 1937 1938 /* Disable the MAC Rx/Tx */ 1939 stmmac_set_mac(priv->ioaddr, false); 1940 1941 netif_carrier_off(dev); 1942 1943 #ifdef CONFIG_DEBUG_FS 1944 stmmac_exit_fs(dev); 1945 #endif 1946 1947 stmmac_release_ptp(priv); 1948 1949 return 0; 1950 } 1951 1952 /** 1953 * stmmac_tso_allocator - close entry point of the driver 1954 * @priv: driver private structure 1955 * @des: buffer start address 1956 * @total_len: total length to fill in descriptors 1957 * @last_segmant: condition for the last descriptor 1958 * Description: 1959 * This function fills descriptor and request new descriptors according to 1960 * buffer length to fill 1961 */ 1962 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, 1963 int total_len, bool last_segment) 1964 { 1965 struct dma_desc *desc; 1966 int tmp_len; 1967 u32 buff_size; 1968 1969 tmp_len = total_len; 1970 1971 while (tmp_len > 0) { 1972 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 1973 desc = priv->dma_tx + priv->cur_tx; 1974 1975 desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); 1976 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 1977 TSO_MAX_BUFF_SIZE : tmp_len; 1978 1979 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, 1980 0, 1, 1981 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), 1982 0, 0); 1983 1984 tmp_len -= TSO_MAX_BUFF_SIZE; 1985 } 1986 } 1987 1988 /** 1989 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 1990 * @skb : the socket buffer 1991 * @dev : device pointer 1992 * Description: this is the transmit function that is called on TSO frames 1993 * (support available on GMAC4 and newer chips). 1994 * Diagram below show the ring programming in case of TSO frames: 1995 * 1996 * First Descriptor 1997 * -------- 1998 * | DES0 |---> buffer1 = L2/L3/L4 header 1999 * | DES1 |---> TCP Payload (can continue on next descr...) 2000 * | DES2 |---> buffer 1 and 2 len 2001 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2002 * -------- 2003 * | 2004 * ... 2005 * | 2006 * -------- 2007 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2008 * | DES1 | --| 2009 * | DES2 | --> buffer 1 and 2 len 2010 * | DES3 | 2011 * -------- 2012 * 2013 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2014 */ 2015 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2016 { 2017 u32 pay_len, mss; 2018 int tmp_pay_len = 0; 2019 struct stmmac_priv *priv = netdev_priv(dev); 2020 int nfrags = skb_shinfo(skb)->nr_frags; 2021 unsigned int first_entry, des; 2022 struct dma_desc *desc, *first, *mss_desc = NULL; 2023 u8 proto_hdr_len; 2024 int i; 2025 2026 /* Compute header lengths */ 2027 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2028 2029 /* Desc availability based on threshold should be enough safe */ 2030 if (unlikely(stmmac_tx_avail(priv) < 2031 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2032 if (!netif_queue_stopped(dev)) { 2033 netif_stop_queue(dev); 2034 /* This is a hard error, log it. */ 2035 netdev_err(priv->dev, 2036 "%s: Tx Ring full when queue awake\n", 2037 __func__); 2038 } 2039 return NETDEV_TX_BUSY; 2040 } 2041 2042 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2043 2044 mss = skb_shinfo(skb)->gso_size; 2045 2046 /* set new MSS value if needed */ 2047 if (mss != priv->mss) { 2048 mss_desc = priv->dma_tx + priv->cur_tx; 2049 priv->hw->desc->set_mss(mss_desc, mss); 2050 priv->mss = mss; 2051 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2052 } 2053 2054 if (netif_msg_tx_queued(priv)) { 2055 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2056 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2057 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2058 skb->data_len); 2059 } 2060 2061 first_entry = priv->cur_tx; 2062 2063 desc = priv->dma_tx + first_entry; 2064 first = desc; 2065 2066 /* first descriptor: fill Headers on Buf1 */ 2067 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2068 DMA_TO_DEVICE); 2069 if (dma_mapping_error(priv->device, des)) 2070 goto dma_map_err; 2071 2072 priv->tx_skbuff_dma[first_entry].buf = des; 2073 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2074 priv->tx_skbuff[first_entry] = skb; 2075 2076 first->des0 = cpu_to_le32(des); 2077 2078 /* Fill start of payload in buff2 of first descriptor */ 2079 if (pay_len) 2080 first->des1 = cpu_to_le32(des + proto_hdr_len); 2081 2082 /* If needed take extra descriptors to fill the remaining payload */ 2083 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2084 2085 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); 2086 2087 /* Prepare fragments */ 2088 for (i = 0; i < nfrags; i++) { 2089 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2090 2091 des = skb_frag_dma_map(priv->device, frag, 0, 2092 skb_frag_size(frag), 2093 DMA_TO_DEVICE); 2094 2095 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2096 (i == nfrags - 1)); 2097 2098 priv->tx_skbuff_dma[priv->cur_tx].buf = des; 2099 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); 2100 priv->tx_skbuff[priv->cur_tx] = NULL; 2101 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; 2102 } 2103 2104 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; 2105 2106 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2107 2108 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2109 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2110 __func__); 2111 netif_stop_queue(dev); 2112 } 2113 2114 dev->stats.tx_bytes += skb->len; 2115 priv->xstats.tx_tso_frames++; 2116 priv->xstats.tx_tso_nfrags += nfrags; 2117 2118 /* Manage tx mitigation */ 2119 priv->tx_count_frames += nfrags + 1; 2120 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2121 mod_timer(&priv->txtimer, 2122 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2123 } else { 2124 priv->tx_count_frames = 0; 2125 priv->hw->desc->set_tx_ic(desc); 2126 priv->xstats.tx_set_ic_bit++; 2127 } 2128 2129 if (!priv->hwts_tx_en) 2130 skb_tx_timestamp(skb); 2131 2132 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2133 priv->hwts_tx_en)) { 2134 /* declare that device is doing timestamping */ 2135 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2136 priv->hw->desc->enable_tx_timestamp(first); 2137 } 2138 2139 /* Complete the first descriptor before granting the DMA */ 2140 priv->hw->desc->prepare_tso_tx_desc(first, 1, 2141 proto_hdr_len, 2142 pay_len, 2143 1, priv->tx_skbuff_dma[first_entry].last_segment, 2144 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2145 2146 /* If context desc is used to change MSS */ 2147 if (mss_desc) 2148 priv->hw->desc->set_tx_owner(mss_desc); 2149 2150 /* The own bit must be the latest setting done when prepare the 2151 * descriptor and then barrier is needed to make sure that 2152 * all is coherent before granting the DMA engine. 2153 */ 2154 dma_wmb(); 2155 2156 if (netif_msg_pktdata(priv)) { 2157 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 2158 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2159 priv->cur_tx, first, nfrags); 2160 2161 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 2162 0); 2163 2164 pr_info(">>> frame to be transmitted: "); 2165 print_pkt(skb->data, skb_headlen(skb)); 2166 } 2167 2168 netdev_sent_queue(dev, skb->len); 2169 2170 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2171 STMMAC_CHAN0); 2172 2173 return NETDEV_TX_OK; 2174 2175 dma_map_err: 2176 dev_err(priv->device, "Tx dma map failed\n"); 2177 dev_kfree_skb(skb); 2178 priv->dev->stats.tx_dropped++; 2179 return NETDEV_TX_OK; 2180 } 2181 2182 /** 2183 * stmmac_xmit - Tx entry point of the driver 2184 * @skb : the socket buffer 2185 * @dev : device pointer 2186 * Description : this is the tx entry point of the driver. 2187 * It programs the chain or the ring and supports oversized frames 2188 * and SG feature. 2189 */ 2190 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 2191 { 2192 struct stmmac_priv *priv = netdev_priv(dev); 2193 unsigned int nopaged_len = skb_headlen(skb); 2194 int i, csum_insertion = 0, is_jumbo = 0; 2195 int nfrags = skb_shinfo(skb)->nr_frags; 2196 unsigned int entry, first_entry; 2197 struct dma_desc *desc, *first; 2198 unsigned int enh_desc; 2199 unsigned int des; 2200 2201 /* Manage oversized TCP frames for GMAC4 device */ 2202 if (skb_is_gso(skb) && priv->tso) { 2203 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 2204 return stmmac_tso_xmit(skb, dev); 2205 } 2206 2207 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 2208 if (!netif_queue_stopped(dev)) { 2209 netif_stop_queue(dev); 2210 /* This is a hard error, log it. */ 2211 netdev_err(priv->dev, 2212 "%s: Tx Ring full when queue awake\n", 2213 __func__); 2214 } 2215 return NETDEV_TX_BUSY; 2216 } 2217 2218 if (priv->tx_path_in_lpi_mode) 2219 stmmac_disable_eee_mode(priv); 2220 2221 entry = priv->cur_tx; 2222 first_entry = entry; 2223 2224 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 2225 2226 if (likely(priv->extend_desc)) 2227 desc = (struct dma_desc *)(priv->dma_etx + entry); 2228 else 2229 desc = priv->dma_tx + entry; 2230 2231 first = desc; 2232 2233 priv->tx_skbuff[first_entry] = skb; 2234 2235 enh_desc = priv->plat->enh_desc; 2236 /* To program the descriptors according to the size of the frame */ 2237 if (enh_desc) 2238 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 2239 2240 if (unlikely(is_jumbo) && likely(priv->synopsys_id < 2241 DWMAC_CORE_4_00)) { 2242 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 2243 if (unlikely(entry < 0)) 2244 goto dma_map_err; 2245 } 2246 2247 for (i = 0; i < nfrags; i++) { 2248 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2249 int len = skb_frag_size(frag); 2250 bool last_segment = (i == (nfrags - 1)); 2251 2252 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2253 2254 if (likely(priv->extend_desc)) 2255 desc = (struct dma_desc *)(priv->dma_etx + entry); 2256 else 2257 desc = priv->dma_tx + entry; 2258 2259 des = skb_frag_dma_map(priv->device, frag, 0, len, 2260 DMA_TO_DEVICE); 2261 if (dma_mapping_error(priv->device, des)) 2262 goto dma_map_err; /* should reuse desc w/o issues */ 2263 2264 priv->tx_skbuff[entry] = NULL; 2265 2266 priv->tx_skbuff_dma[entry].buf = des; 2267 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2268 desc->des0 = cpu_to_le32(des); 2269 else 2270 desc->des2 = cpu_to_le32(des); 2271 2272 priv->tx_skbuff_dma[entry].map_as_page = true; 2273 priv->tx_skbuff_dma[entry].len = len; 2274 priv->tx_skbuff_dma[entry].last_segment = last_segment; 2275 2276 /* Prepare the descriptor and set the own bit too */ 2277 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2278 priv->mode, 1, last_segment); 2279 } 2280 2281 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2282 2283 priv->cur_tx = entry; 2284 2285 if (netif_msg_pktdata(priv)) { 2286 void *tx_head; 2287 2288 netdev_dbg(priv->dev, 2289 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 2290 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2291 entry, first, nfrags); 2292 2293 if (priv->extend_desc) 2294 tx_head = (void *)priv->dma_etx; 2295 else 2296 tx_head = (void *)priv->dma_tx; 2297 2298 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); 2299 2300 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 2301 print_pkt(skb->data, skb->len); 2302 } 2303 2304 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2305 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2306 __func__); 2307 netif_stop_queue(dev); 2308 } 2309 2310 dev->stats.tx_bytes += skb->len; 2311 2312 /* According to the coalesce parameter the IC bit for the latest 2313 * segment is reset and the timer re-started to clean the tx status. 2314 * This approach takes care about the fragments: desc is the first 2315 * element in case of no SG. 2316 */ 2317 priv->tx_count_frames += nfrags + 1; 2318 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2319 mod_timer(&priv->txtimer, 2320 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2321 } else { 2322 priv->tx_count_frames = 0; 2323 priv->hw->desc->set_tx_ic(desc); 2324 priv->xstats.tx_set_ic_bit++; 2325 } 2326 2327 if (!priv->hwts_tx_en) 2328 skb_tx_timestamp(skb); 2329 2330 /* Ready to fill the first descriptor and set the OWN bit w/o any 2331 * problems because all the descriptors are actually ready to be 2332 * passed to the DMA engine. 2333 */ 2334 if (likely(!is_jumbo)) { 2335 bool last_segment = (nfrags == 0); 2336 2337 des = dma_map_single(priv->device, skb->data, 2338 nopaged_len, DMA_TO_DEVICE); 2339 if (dma_mapping_error(priv->device, des)) 2340 goto dma_map_err; 2341 2342 priv->tx_skbuff_dma[first_entry].buf = des; 2343 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2344 first->des0 = cpu_to_le32(des); 2345 else 2346 first->des2 = cpu_to_le32(des); 2347 2348 priv->tx_skbuff_dma[first_entry].len = nopaged_len; 2349 priv->tx_skbuff_dma[first_entry].last_segment = last_segment; 2350 2351 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2352 priv->hwts_tx_en)) { 2353 /* declare that device is doing timestamping */ 2354 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2355 priv->hw->desc->enable_tx_timestamp(first); 2356 } 2357 2358 /* Prepare the first descriptor setting the OWN bit too */ 2359 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, 2360 csum_insertion, priv->mode, 1, 2361 last_segment); 2362 2363 /* The own bit must be the latest setting done when prepare the 2364 * descriptor and then barrier is needed to make sure that 2365 * all is coherent before granting the DMA engine. 2366 */ 2367 dma_wmb(); 2368 } 2369 2370 netdev_sent_queue(dev, skb->len); 2371 2372 if (priv->synopsys_id < DWMAC_CORE_4_00) 2373 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2374 else 2375 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2376 STMMAC_CHAN0); 2377 2378 return NETDEV_TX_OK; 2379 2380 dma_map_err: 2381 netdev_err(priv->dev, "Tx DMA map failed\n"); 2382 dev_kfree_skb(skb); 2383 priv->dev->stats.tx_dropped++; 2384 return NETDEV_TX_OK; 2385 } 2386 2387 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2388 { 2389 struct ethhdr *ehdr; 2390 u16 vlanid; 2391 2392 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2393 NETIF_F_HW_VLAN_CTAG_RX && 2394 !__vlan_get_tag(skb, &vlanid)) { 2395 /* pop the vlan tag */ 2396 ehdr = (struct ethhdr *)skb->data; 2397 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2398 skb_pull(skb, VLAN_HLEN); 2399 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2400 } 2401 } 2402 2403 2404 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) 2405 { 2406 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) 2407 return 0; 2408 2409 return 1; 2410 } 2411 2412 /** 2413 * stmmac_rx_refill - refill used skb preallocated buffers 2414 * @priv: driver private structure 2415 * Description : this is to reallocate the skb for the reception process 2416 * that is based on zero-copy. 2417 */ 2418 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2419 { 2420 int bfsize = priv->dma_buf_sz; 2421 unsigned int entry = priv->dirty_rx; 2422 int dirty = stmmac_rx_dirty(priv); 2423 2424 while (dirty-- > 0) { 2425 struct dma_desc *p; 2426 2427 if (priv->extend_desc) 2428 p = (struct dma_desc *)(priv->dma_erx + entry); 2429 else 2430 p = priv->dma_rx + entry; 2431 2432 if (likely(priv->rx_skbuff[entry] == NULL)) { 2433 struct sk_buff *skb; 2434 2435 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2436 if (unlikely(!skb)) { 2437 /* so for a while no zero-copy! */ 2438 priv->rx_zeroc_thresh = STMMAC_RX_THRESH; 2439 if (unlikely(net_ratelimit())) 2440 dev_err(priv->device, 2441 "fail to alloc skb entry %d\n", 2442 entry); 2443 break; 2444 } 2445 2446 priv->rx_skbuff[entry] = skb; 2447 priv->rx_skbuff_dma[entry] = 2448 dma_map_single(priv->device, skb->data, bfsize, 2449 DMA_FROM_DEVICE); 2450 if (dma_mapping_error(priv->device, 2451 priv->rx_skbuff_dma[entry])) { 2452 netdev_err(priv->dev, "Rx DMA map failed\n"); 2453 dev_kfree_skb(skb); 2454 break; 2455 } 2456 2457 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2458 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]); 2459 p->des1 = 0; 2460 } else { 2461 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]); 2462 } 2463 if (priv->hw->mode->refill_desc3) 2464 priv->hw->mode->refill_desc3(priv, p); 2465 2466 if (priv->rx_zeroc_thresh > 0) 2467 priv->rx_zeroc_thresh--; 2468 2469 netif_dbg(priv, rx_status, priv->dev, 2470 "refill entry #%d\n", entry); 2471 } 2472 dma_wmb(); 2473 2474 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2475 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); 2476 else 2477 priv->hw->desc->set_rx_owner(p); 2478 2479 dma_wmb(); 2480 2481 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 2482 } 2483 priv->dirty_rx = entry; 2484 } 2485 2486 /** 2487 * stmmac_rx - manage the receive process 2488 * @priv: driver private structure 2489 * @limit: napi bugget. 2490 * Description : this the function called by the napi poll method. 2491 * It gets all the frames inside the ring. 2492 */ 2493 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2494 { 2495 unsigned int entry = priv->cur_rx; 2496 unsigned int next_entry; 2497 unsigned int count = 0; 2498 int coe = priv->hw->rx_csum; 2499 2500 if (netif_msg_rx_status(priv)) { 2501 void *rx_head; 2502 2503 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 2504 if (priv->extend_desc) 2505 rx_head = (void *)priv->dma_erx; 2506 else 2507 rx_head = (void *)priv->dma_rx; 2508 2509 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); 2510 } 2511 while (count < limit) { 2512 int status; 2513 struct dma_desc *p; 2514 struct dma_desc *np; 2515 2516 if (priv->extend_desc) 2517 p = (struct dma_desc *)(priv->dma_erx + entry); 2518 else 2519 p = priv->dma_rx + entry; 2520 2521 /* read the status of the incoming frame */ 2522 status = priv->hw->desc->rx_status(&priv->dev->stats, 2523 &priv->xstats, p); 2524 /* check if managed by the DMA otherwise go ahead */ 2525 if (unlikely(status & dma_own)) 2526 break; 2527 2528 count++; 2529 2530 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); 2531 next_entry = priv->cur_rx; 2532 2533 if (priv->extend_desc) 2534 np = (struct dma_desc *)(priv->dma_erx + next_entry); 2535 else 2536 np = priv->dma_rx + next_entry; 2537 2538 prefetch(np); 2539 2540 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2541 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2542 &priv->xstats, 2543 priv->dma_erx + 2544 entry); 2545 if (unlikely(status == discard_frame)) { 2546 priv->dev->stats.rx_errors++; 2547 if (priv->hwts_rx_en && !priv->extend_desc) { 2548 /* DESC2 & DESC3 will be overwitten by device 2549 * with timestamp value, hence reinitialize 2550 * them in stmmac_rx_refill() function so that 2551 * device can reuse it. 2552 */ 2553 priv->rx_skbuff[entry] = NULL; 2554 dma_unmap_single(priv->device, 2555 priv->rx_skbuff_dma[entry], 2556 priv->dma_buf_sz, 2557 DMA_FROM_DEVICE); 2558 } 2559 } else { 2560 struct sk_buff *skb; 2561 int frame_len; 2562 unsigned int des; 2563 2564 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2565 des = le32_to_cpu(p->des0); 2566 else 2567 des = le32_to_cpu(p->des2); 2568 2569 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2570 2571 /* If frame length is greather than skb buffer size 2572 * (preallocated during init) then the packet is 2573 * ignored 2574 */ 2575 if (frame_len > priv->dma_buf_sz) { 2576 netdev_err(priv->dev, 2577 "len %d larger than size (%d)\n", 2578 frame_len, priv->dma_buf_sz); 2579 priv->dev->stats.rx_length_errors++; 2580 break; 2581 } 2582 2583 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2584 * Type frames (LLC/LLC-SNAP) 2585 */ 2586 if (unlikely(status != llc_snap)) 2587 frame_len -= ETH_FCS_LEN; 2588 2589 if (netif_msg_rx_status(priv)) { 2590 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", 2591 p, entry, des); 2592 if (frame_len > ETH_FRAME_LEN) 2593 netdev_dbg(priv->dev, "frame size %d, COE: %d\n", 2594 frame_len, status); 2595 } 2596 2597 /* The zero-copy is always used for all the sizes 2598 * in case of GMAC4 because it needs 2599 * to refill the used descriptors, always. 2600 */ 2601 if (unlikely(!priv->plat->has_gmac4 && 2602 ((frame_len < priv->rx_copybreak) || 2603 stmmac_rx_threshold_count(priv)))) { 2604 skb = netdev_alloc_skb_ip_align(priv->dev, 2605 frame_len); 2606 if (unlikely(!skb)) { 2607 if (net_ratelimit()) 2608 dev_warn(priv->device, 2609 "packet dropped\n"); 2610 priv->dev->stats.rx_dropped++; 2611 break; 2612 } 2613 2614 dma_sync_single_for_cpu(priv->device, 2615 priv->rx_skbuff_dma 2616 [entry], frame_len, 2617 DMA_FROM_DEVICE); 2618 skb_copy_to_linear_data(skb, 2619 priv-> 2620 rx_skbuff[entry]->data, 2621 frame_len); 2622 2623 skb_put(skb, frame_len); 2624 dma_sync_single_for_device(priv->device, 2625 priv->rx_skbuff_dma 2626 [entry], frame_len, 2627 DMA_FROM_DEVICE); 2628 } else { 2629 skb = priv->rx_skbuff[entry]; 2630 if (unlikely(!skb)) { 2631 netdev_err(priv->dev, 2632 "%s: Inconsistent Rx chain\n", 2633 priv->dev->name); 2634 priv->dev->stats.rx_dropped++; 2635 break; 2636 } 2637 prefetch(skb->data - NET_IP_ALIGN); 2638 priv->rx_skbuff[entry] = NULL; 2639 priv->rx_zeroc_thresh++; 2640 2641 skb_put(skb, frame_len); 2642 dma_unmap_single(priv->device, 2643 priv->rx_skbuff_dma[entry], 2644 priv->dma_buf_sz, 2645 DMA_FROM_DEVICE); 2646 } 2647 2648 if (netif_msg_pktdata(priv)) { 2649 netdev_dbg(priv->dev, "frame received (%dbytes)", 2650 frame_len); 2651 print_pkt(skb->data, frame_len); 2652 } 2653 2654 stmmac_get_rx_hwtstamp(priv, p, np, skb); 2655 2656 stmmac_rx_vlan(priv->dev, skb); 2657 2658 skb->protocol = eth_type_trans(skb, priv->dev); 2659 2660 if (unlikely(!coe)) 2661 skb_checksum_none_assert(skb); 2662 else 2663 skb->ip_summed = CHECKSUM_UNNECESSARY; 2664 2665 napi_gro_receive(&priv->napi, skb); 2666 2667 priv->dev->stats.rx_packets++; 2668 priv->dev->stats.rx_bytes += frame_len; 2669 } 2670 entry = next_entry; 2671 } 2672 2673 stmmac_rx_refill(priv); 2674 2675 priv->xstats.rx_pkt_n += count; 2676 2677 return count; 2678 } 2679 2680 /** 2681 * stmmac_poll - stmmac poll method (NAPI) 2682 * @napi : pointer to the napi structure. 2683 * @budget : maximum number of packets that the current CPU can receive from 2684 * all interfaces. 2685 * Description : 2686 * To look at the incoming frames and clear the tx resources. 2687 */ 2688 static int stmmac_poll(struct napi_struct *napi, int budget) 2689 { 2690 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2691 int work_done = 0; 2692 2693 priv->xstats.napi_poll++; 2694 stmmac_tx_clean(priv); 2695 2696 work_done = stmmac_rx(priv, budget); 2697 if (work_done < budget) { 2698 napi_complete(napi); 2699 stmmac_enable_dma_irq(priv); 2700 } 2701 return work_done; 2702 } 2703 2704 /** 2705 * stmmac_tx_timeout 2706 * @dev : Pointer to net device structure 2707 * Description: this function is called when a packet transmission fails to 2708 * complete within a reasonable time. The driver will mark the error in the 2709 * netdev structure and arrange for the device to be reset to a sane state 2710 * in order to transmit a new packet. 2711 */ 2712 static void stmmac_tx_timeout(struct net_device *dev) 2713 { 2714 struct stmmac_priv *priv = netdev_priv(dev); 2715 2716 /* Clear Tx resources and restart transmitting again */ 2717 stmmac_tx_err(priv); 2718 } 2719 2720 /** 2721 * stmmac_set_rx_mode - entry point for multicast addressing 2722 * @dev : pointer to the device structure 2723 * Description: 2724 * This function is a driver entry point which gets called by the kernel 2725 * whenever multicast addresses must be enabled/disabled. 2726 * Return value: 2727 * void. 2728 */ 2729 static void stmmac_set_rx_mode(struct net_device *dev) 2730 { 2731 struct stmmac_priv *priv = netdev_priv(dev); 2732 2733 priv->hw->mac->set_filter(priv->hw, dev); 2734 } 2735 2736 /** 2737 * stmmac_change_mtu - entry point to change MTU size for the device. 2738 * @dev : device pointer. 2739 * @new_mtu : the new MTU size for the device. 2740 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2741 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2742 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2743 * Return value: 2744 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2745 * file on failure. 2746 */ 2747 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2748 { 2749 struct stmmac_priv *priv = netdev_priv(dev); 2750 2751 if (netif_running(dev)) { 2752 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 2753 return -EBUSY; 2754 } 2755 2756 dev->mtu = new_mtu; 2757 2758 netdev_update_features(dev); 2759 2760 return 0; 2761 } 2762 2763 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2764 netdev_features_t features) 2765 { 2766 struct stmmac_priv *priv = netdev_priv(dev); 2767 2768 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2769 features &= ~NETIF_F_RXCSUM; 2770 2771 if (!priv->plat->tx_coe) 2772 features &= ~NETIF_F_CSUM_MASK; 2773 2774 /* Some GMAC devices have a bugged Jumbo frame support that 2775 * needs to have the Tx COE disabled for oversized frames 2776 * (due to limited buffer sizes). In this case we disable 2777 * the TX csum insertionin the TDES and not use SF. 2778 */ 2779 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2780 features &= ~NETIF_F_CSUM_MASK; 2781 2782 /* Disable tso if asked by ethtool */ 2783 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 2784 if (features & NETIF_F_TSO) 2785 priv->tso = true; 2786 else 2787 priv->tso = false; 2788 } 2789 2790 return features; 2791 } 2792 2793 static int stmmac_set_features(struct net_device *netdev, 2794 netdev_features_t features) 2795 { 2796 struct stmmac_priv *priv = netdev_priv(netdev); 2797 2798 /* Keep the COE Type in case of csum is supporting */ 2799 if (features & NETIF_F_RXCSUM) 2800 priv->hw->rx_csum = priv->plat->rx_coe; 2801 else 2802 priv->hw->rx_csum = 0; 2803 /* No check needed because rx_coe has been set before and it will be 2804 * fixed in case of issue. 2805 */ 2806 priv->hw->mac->rx_ipc(priv->hw); 2807 2808 return 0; 2809 } 2810 2811 /** 2812 * stmmac_interrupt - main ISR 2813 * @irq: interrupt number. 2814 * @dev_id: to pass the net device pointer. 2815 * Description: this is the main driver interrupt service routine. 2816 * It can call: 2817 * o DMA service routine (to manage incoming frame reception and transmission 2818 * status) 2819 * o Core interrupts to manage: remote wake-up, management counter, LPI 2820 * interrupts. 2821 */ 2822 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2823 { 2824 struct net_device *dev = (struct net_device *)dev_id; 2825 struct stmmac_priv *priv = netdev_priv(dev); 2826 2827 if (priv->irq_wake) 2828 pm_wakeup_event(priv->device, 0); 2829 2830 if (unlikely(!dev)) { 2831 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 2832 return IRQ_NONE; 2833 } 2834 2835 /* To handle GMAC own interrupts */ 2836 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { 2837 int status = priv->hw->mac->host_irq_status(priv->hw, 2838 &priv->xstats); 2839 if (unlikely(status)) { 2840 /* For LPI we need to save the tx status */ 2841 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2842 priv->tx_path_in_lpi_mode = true; 2843 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2844 priv->tx_path_in_lpi_mode = false; 2845 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) 2846 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, 2847 priv->rx_tail_addr, 2848 STMMAC_CHAN0); 2849 } 2850 2851 /* PCS link status */ 2852 if (priv->hw->pcs) { 2853 if (priv->xstats.pcs_link) 2854 netif_carrier_on(dev); 2855 else 2856 netif_carrier_off(dev); 2857 } 2858 } 2859 2860 /* To handle DMA interrupts */ 2861 stmmac_dma_interrupt(priv); 2862 2863 return IRQ_HANDLED; 2864 } 2865 2866 #ifdef CONFIG_NET_POLL_CONTROLLER 2867 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2868 * to allow network I/O with interrupts disabled. 2869 */ 2870 static void stmmac_poll_controller(struct net_device *dev) 2871 { 2872 disable_irq(dev->irq); 2873 stmmac_interrupt(dev->irq, dev); 2874 enable_irq(dev->irq); 2875 } 2876 #endif 2877 2878 /** 2879 * stmmac_ioctl - Entry point for the Ioctl 2880 * @dev: Device pointer. 2881 * @rq: An IOCTL specefic structure, that can contain a pointer to 2882 * a proprietary structure used to pass information to the driver. 2883 * @cmd: IOCTL command 2884 * Description: 2885 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2886 */ 2887 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2888 { 2889 int ret = -EOPNOTSUPP; 2890 2891 if (!netif_running(dev)) 2892 return -EINVAL; 2893 2894 switch (cmd) { 2895 case SIOCGMIIPHY: 2896 case SIOCGMIIREG: 2897 case SIOCSMIIREG: 2898 if (!dev->phydev) 2899 return -EINVAL; 2900 ret = phy_mii_ioctl(dev->phydev, rq, cmd); 2901 break; 2902 case SIOCSHWTSTAMP: 2903 ret = stmmac_hwtstamp_ioctl(dev, rq); 2904 break; 2905 default: 2906 break; 2907 } 2908 2909 return ret; 2910 } 2911 2912 #ifdef CONFIG_DEBUG_FS 2913 static struct dentry *stmmac_fs_dir; 2914 2915 static void sysfs_display_ring(void *head, int size, int extend_desc, 2916 struct seq_file *seq) 2917 { 2918 int i; 2919 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2920 struct dma_desc *p = (struct dma_desc *)head; 2921 2922 for (i = 0; i < size; i++) { 2923 u64 x; 2924 if (extend_desc) { 2925 x = *(u64 *) ep; 2926 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2927 i, (unsigned int)virt_to_phys(ep), 2928 le32_to_cpu(ep->basic.des0), 2929 le32_to_cpu(ep->basic.des1), 2930 le32_to_cpu(ep->basic.des2), 2931 le32_to_cpu(ep->basic.des3)); 2932 ep++; 2933 } else { 2934 x = *(u64 *) p; 2935 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2936 i, (unsigned int)virt_to_phys(ep), 2937 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 2938 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 2939 p++; 2940 } 2941 seq_printf(seq, "\n"); 2942 } 2943 } 2944 2945 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2946 { 2947 struct net_device *dev = seq->private; 2948 struct stmmac_priv *priv = netdev_priv(dev); 2949 2950 if (priv->extend_desc) { 2951 seq_printf(seq, "Extended RX descriptor ring:\n"); 2952 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); 2953 seq_printf(seq, "Extended TX descriptor ring:\n"); 2954 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); 2955 } else { 2956 seq_printf(seq, "RX descriptor ring:\n"); 2957 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); 2958 seq_printf(seq, "TX descriptor ring:\n"); 2959 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); 2960 } 2961 2962 return 0; 2963 } 2964 2965 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2966 { 2967 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2968 } 2969 2970 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */ 2971 2972 static const struct file_operations stmmac_rings_status_fops = { 2973 .owner = THIS_MODULE, 2974 .open = stmmac_sysfs_ring_open, 2975 .read = seq_read, 2976 .llseek = seq_lseek, 2977 .release = single_release, 2978 }; 2979 2980 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2981 { 2982 struct net_device *dev = seq->private; 2983 struct stmmac_priv *priv = netdev_priv(dev); 2984 2985 if (!priv->hw_cap_support) { 2986 seq_printf(seq, "DMA HW features not supported\n"); 2987 return 0; 2988 } 2989 2990 seq_printf(seq, "==============================\n"); 2991 seq_printf(seq, "\tDMA HW features\n"); 2992 seq_printf(seq, "==============================\n"); 2993 2994 seq_printf(seq, "\t10/100 Mbps: %s\n", 2995 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2996 seq_printf(seq, "\t1000 Mbps: %s\n", 2997 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2998 seq_printf(seq, "\tHalf duplex: %s\n", 2999 (priv->dma_cap.half_duplex) ? "Y" : "N"); 3000 seq_printf(seq, "\tHash Filter: %s\n", 3001 (priv->dma_cap.hash_filter) ? "Y" : "N"); 3002 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 3003 (priv->dma_cap.multi_addr) ? "Y" : "N"); 3004 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 3005 (priv->dma_cap.pcs) ? "Y" : "N"); 3006 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 3007 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 3008 seq_printf(seq, "\tPMT Remote wake up: %s\n", 3009 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 3010 seq_printf(seq, "\tPMT Magic Frame: %s\n", 3011 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 3012 seq_printf(seq, "\tRMON module: %s\n", 3013 (priv->dma_cap.rmon) ? "Y" : "N"); 3014 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 3015 (priv->dma_cap.time_stamp) ? "Y" : "N"); 3016 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 3017 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 3018 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 3019 (priv->dma_cap.eee) ? "Y" : "N"); 3020 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 3021 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3022 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3023 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3024 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3025 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3026 } else { 3027 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3028 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3029 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3030 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3031 } 3032 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3033 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3034 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3035 priv->dma_cap.number_rx_channel); 3036 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3037 priv->dma_cap.number_tx_channel); 3038 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3039 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3040 3041 return 0; 3042 } 3043 3044 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 3045 { 3046 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 3047 } 3048 3049 static const struct file_operations stmmac_dma_cap_fops = { 3050 .owner = THIS_MODULE, 3051 .open = stmmac_sysfs_dma_cap_open, 3052 .read = seq_read, 3053 .llseek = seq_lseek, 3054 .release = single_release, 3055 }; 3056 3057 static int stmmac_init_fs(struct net_device *dev) 3058 { 3059 struct stmmac_priv *priv = netdev_priv(dev); 3060 3061 /* Create per netdev entries */ 3062 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3063 3064 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3065 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); 3066 3067 return -ENOMEM; 3068 } 3069 3070 /* Entry to report DMA RX/TX rings */ 3071 priv->dbgfs_rings_status = 3072 debugfs_create_file("descriptors_status", S_IRUGO, 3073 priv->dbgfs_dir, dev, 3074 &stmmac_rings_status_fops); 3075 3076 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3077 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); 3078 debugfs_remove_recursive(priv->dbgfs_dir); 3079 3080 return -ENOMEM; 3081 } 3082 3083 /* Entry to report the DMA HW features */ 3084 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, 3085 priv->dbgfs_dir, 3086 dev, &stmmac_dma_cap_fops); 3087 3088 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3089 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); 3090 debugfs_remove_recursive(priv->dbgfs_dir); 3091 3092 return -ENOMEM; 3093 } 3094 3095 return 0; 3096 } 3097 3098 static void stmmac_exit_fs(struct net_device *dev) 3099 { 3100 struct stmmac_priv *priv = netdev_priv(dev); 3101 3102 debugfs_remove_recursive(priv->dbgfs_dir); 3103 } 3104 #endif /* CONFIG_DEBUG_FS */ 3105 3106 static const struct net_device_ops stmmac_netdev_ops = { 3107 .ndo_open = stmmac_open, 3108 .ndo_start_xmit = stmmac_xmit, 3109 .ndo_stop = stmmac_release, 3110 .ndo_change_mtu = stmmac_change_mtu, 3111 .ndo_fix_features = stmmac_fix_features, 3112 .ndo_set_features = stmmac_set_features, 3113 .ndo_set_rx_mode = stmmac_set_rx_mode, 3114 .ndo_tx_timeout = stmmac_tx_timeout, 3115 .ndo_do_ioctl = stmmac_ioctl, 3116 #ifdef CONFIG_NET_POLL_CONTROLLER 3117 .ndo_poll_controller = stmmac_poll_controller, 3118 #endif 3119 .ndo_set_mac_address = eth_mac_addr, 3120 }; 3121 3122 /** 3123 * stmmac_hw_init - Init the MAC device 3124 * @priv: driver private structure 3125 * Description: this function is to configure the MAC device according to 3126 * some platform parameters or the HW capability register. It prepares the 3127 * driver to use either ring or chain modes and to setup either enhanced or 3128 * normal descriptors. 3129 */ 3130 static int stmmac_hw_init(struct stmmac_priv *priv) 3131 { 3132 struct mac_device_info *mac; 3133 3134 /* Identify the MAC HW device */ 3135 if (priv->plat->has_gmac) { 3136 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3137 mac = dwmac1000_setup(priv->ioaddr, 3138 priv->plat->multicast_filter_bins, 3139 priv->plat->unicast_filter_entries, 3140 &priv->synopsys_id); 3141 } else if (priv->plat->has_gmac4) { 3142 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3143 mac = dwmac4_setup(priv->ioaddr, 3144 priv->plat->multicast_filter_bins, 3145 priv->plat->unicast_filter_entries, 3146 &priv->synopsys_id); 3147 } else { 3148 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); 3149 } 3150 if (!mac) 3151 return -ENOMEM; 3152 3153 priv->hw = mac; 3154 3155 /* To use the chained or ring mode */ 3156 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3157 priv->hw->mode = &dwmac4_ring_mode_ops; 3158 } else { 3159 if (chain_mode) { 3160 priv->hw->mode = &chain_mode_ops; 3161 dev_info(priv->device, "Chain mode enabled\n"); 3162 priv->mode = STMMAC_CHAIN_MODE; 3163 } else { 3164 priv->hw->mode = &ring_mode_ops; 3165 dev_info(priv->device, "Ring mode enabled\n"); 3166 priv->mode = STMMAC_RING_MODE; 3167 } 3168 } 3169 3170 /* Get the HW capability (new GMAC newer than 3.50a) */ 3171 priv->hw_cap_support = stmmac_get_hw_features(priv); 3172 if (priv->hw_cap_support) { 3173 dev_info(priv->device, "DMA HW capability register supported\n"); 3174 3175 /* We can override some gmac/dma configuration fields: e.g. 3176 * enh_desc, tx_coe (e.g. that are passed through the 3177 * platform) with the values from the HW capability 3178 * register (if supported). 3179 */ 3180 priv->plat->enh_desc = priv->dma_cap.enh_desc; 3181 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 3182 priv->hw->pmt = priv->plat->pmt; 3183 3184 /* TXCOE doesn't work in thresh DMA mode */ 3185 if (priv->plat->force_thresh_dma_mode) 3186 priv->plat->tx_coe = 0; 3187 else 3188 priv->plat->tx_coe = priv->dma_cap.tx_coe; 3189 3190 /* In case of GMAC4 rx_coe is from HW cap register. */ 3191 priv->plat->rx_coe = priv->dma_cap.rx_coe; 3192 3193 if (priv->dma_cap.rx_coe_type2) 3194 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 3195 else if (priv->dma_cap.rx_coe_type1) 3196 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 3197 3198 } else { 3199 dev_info(priv->device, "No HW DMA feature register supported\n"); 3200 } 3201 3202 /* To use alternate (extended), normal or GMAC4 descriptor structures */ 3203 if (priv->synopsys_id >= DWMAC_CORE_4_00) 3204 priv->hw->desc = &dwmac4_desc_ops; 3205 else 3206 stmmac_selec_desc_mode(priv); 3207 3208 if (priv->plat->rx_coe) { 3209 priv->hw->rx_csum = priv->plat->rx_coe; 3210 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 3211 if (priv->synopsys_id < DWMAC_CORE_4_00) 3212 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 3213 } 3214 if (priv->plat->tx_coe) 3215 dev_info(priv->device, "TX Checksum insertion supported\n"); 3216 3217 if (priv->plat->pmt) { 3218 dev_info(priv->device, "Wake-Up On Lan supported\n"); 3219 device_set_wakeup_capable(priv->device, 1); 3220 } 3221 3222 if (priv->dma_cap.tsoen) 3223 dev_info(priv->device, "TSO supported\n"); 3224 3225 return 0; 3226 } 3227 3228 /** 3229 * stmmac_dvr_probe 3230 * @device: device pointer 3231 * @plat_dat: platform data pointer 3232 * @res: stmmac resource pointer 3233 * Description: this is the main probe function used to 3234 * call the alloc_etherdev, allocate the priv structure. 3235 * Return: 3236 * returns 0 on success, otherwise errno. 3237 */ 3238 int stmmac_dvr_probe(struct device *device, 3239 struct plat_stmmacenet_data *plat_dat, 3240 struct stmmac_resources *res) 3241 { 3242 int ret = 0; 3243 struct net_device *ndev = NULL; 3244 struct stmmac_priv *priv; 3245 3246 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 3247 if (!ndev) 3248 return -ENOMEM; 3249 3250 SET_NETDEV_DEV(ndev, device); 3251 3252 priv = netdev_priv(ndev); 3253 priv->device = device; 3254 priv->dev = ndev; 3255 3256 stmmac_set_ethtool_ops(ndev); 3257 priv->pause = pause; 3258 priv->plat = plat_dat; 3259 priv->ioaddr = res->addr; 3260 priv->dev->base_addr = (unsigned long)res->addr; 3261 3262 priv->dev->irq = res->irq; 3263 priv->wol_irq = res->wol_irq; 3264 priv->lpi_irq = res->lpi_irq; 3265 3266 if (res->mac) 3267 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 3268 3269 dev_set_drvdata(device, priv->dev); 3270 3271 /* Verify driver arguments */ 3272 stmmac_verify_args(); 3273 3274 /* Override with kernel parameters if supplied XXX CRS XXX 3275 * this needs to have multiple instances 3276 */ 3277 if ((phyaddr >= 0) && (phyaddr <= 31)) 3278 priv->plat->phy_addr = phyaddr; 3279 3280 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 3281 if (IS_ERR(priv->stmmac_clk)) { 3282 netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n", 3283 __func__); 3284 /* If failed to obtain stmmac_clk and specific clk_csr value 3285 * is NOT passed from the platform, probe fail. 3286 */ 3287 if (!priv->plat->clk_csr) { 3288 ret = PTR_ERR(priv->stmmac_clk); 3289 goto error_clk_get; 3290 } else { 3291 priv->stmmac_clk = NULL; 3292 } 3293 } 3294 clk_prepare_enable(priv->stmmac_clk); 3295 3296 priv->pclk = devm_clk_get(priv->device, "pclk"); 3297 if (IS_ERR(priv->pclk)) { 3298 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { 3299 ret = -EPROBE_DEFER; 3300 goto error_pclk_get; 3301 } 3302 priv->pclk = NULL; 3303 } 3304 clk_prepare_enable(priv->pclk); 3305 3306 priv->stmmac_rst = devm_reset_control_get(priv->device, 3307 STMMAC_RESOURCE_NAME); 3308 if (IS_ERR(priv->stmmac_rst)) { 3309 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 3310 ret = -EPROBE_DEFER; 3311 goto error_hw_init; 3312 } 3313 dev_info(priv->device, "no reset control found\n"); 3314 priv->stmmac_rst = NULL; 3315 } 3316 if (priv->stmmac_rst) 3317 reset_control_deassert(priv->stmmac_rst); 3318 3319 /* Init MAC and get the capabilities */ 3320 ret = stmmac_hw_init(priv); 3321 if (ret) 3322 goto error_hw_init; 3323 3324 ndev->netdev_ops = &stmmac_netdev_ops; 3325 3326 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3327 NETIF_F_RXCSUM; 3328 3329 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3330 ndev->hw_features |= NETIF_F_TSO; 3331 priv->tso = true; 3332 dev_info(priv->device, "TSO feature enabled\n"); 3333 } 3334 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 3335 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 3336 #ifdef STMMAC_VLAN_TAG_USED 3337 /* Both mac100 and gmac support receive VLAN tag detection */ 3338 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3339 #endif 3340 priv->msg_enable = netif_msg_init(debug, default_msg_level); 3341 3342 /* MTU range: 46 - hw-specific max */ 3343 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 3344 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 3345 ndev->max_mtu = JUMBO_LEN; 3346 else 3347 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 3348 if (priv->plat->maxmtu < ndev->max_mtu) 3349 ndev->max_mtu = priv->plat->maxmtu; 3350 3351 if (flow_ctrl) 3352 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 3353 3354 /* Rx Watchdog is available in the COREs newer than the 3.40. 3355 * In some case, for example on bugged HW this feature 3356 * has to be disable and this can be done by passing the 3357 * riwt_off field from the platform. 3358 */ 3359 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 3360 priv->use_riwt = 1; 3361 netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n"); 3362 } 3363 3364 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 3365 3366 spin_lock_init(&priv->lock); 3367 3368 ret = register_netdev(ndev); 3369 if (ret) { 3370 netdev_err(priv->dev, "%s: ERROR %i registering the device\n", 3371 __func__, ret); 3372 goto error_netdev_register; 3373 } 3374 3375 /* If a specific clk_csr value is passed from the platform 3376 * this means that the CSR Clock Range selection cannot be 3377 * changed at run-time and it is fixed. Viceversa the driver'll try to 3378 * set the MDC clock dynamically according to the csr actual 3379 * clock input. 3380 */ 3381 if (!priv->plat->clk_csr) 3382 stmmac_clk_csr_set(priv); 3383 else 3384 priv->clk_csr = priv->plat->clk_csr; 3385 3386 stmmac_check_pcs_mode(priv); 3387 3388 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3389 priv->hw->pcs != STMMAC_PCS_TBI && 3390 priv->hw->pcs != STMMAC_PCS_RTBI) { 3391 /* MDIO bus Registration */ 3392 ret = stmmac_mdio_register(ndev); 3393 if (ret < 0) { 3394 netdev_err(priv->dev, 3395 "%s: MDIO bus (id: %d) registration failed", 3396 __func__, priv->plat->bus_id); 3397 goto error_mdio_register; 3398 } 3399 } 3400 3401 return 0; 3402 3403 error_mdio_register: 3404 unregister_netdev(ndev); 3405 error_netdev_register: 3406 netif_napi_del(&priv->napi); 3407 error_hw_init: 3408 clk_disable_unprepare(priv->pclk); 3409 error_pclk_get: 3410 clk_disable_unprepare(priv->stmmac_clk); 3411 error_clk_get: 3412 free_netdev(ndev); 3413 3414 return ret; 3415 } 3416 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 3417 3418 /** 3419 * stmmac_dvr_remove 3420 * @dev: device pointer 3421 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 3422 * changes the link status, releases the DMA descriptor rings. 3423 */ 3424 int stmmac_dvr_remove(struct device *dev) 3425 { 3426 struct net_device *ndev = dev_get_drvdata(dev); 3427 struct stmmac_priv *priv = netdev_priv(ndev); 3428 3429 netdev_info(priv->dev, "%s: removing driver", __func__); 3430 3431 priv->hw->dma->stop_rx(priv->ioaddr); 3432 priv->hw->dma->stop_tx(priv->ioaddr); 3433 3434 stmmac_set_mac(priv->ioaddr, false); 3435 netif_carrier_off(ndev); 3436 unregister_netdev(ndev); 3437 if (priv->stmmac_rst) 3438 reset_control_assert(priv->stmmac_rst); 3439 clk_disable_unprepare(priv->pclk); 3440 clk_disable_unprepare(priv->stmmac_clk); 3441 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3442 priv->hw->pcs != STMMAC_PCS_TBI && 3443 priv->hw->pcs != STMMAC_PCS_RTBI) 3444 stmmac_mdio_unregister(ndev); 3445 free_netdev(ndev); 3446 3447 return 0; 3448 } 3449 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 3450 3451 /** 3452 * stmmac_suspend - suspend callback 3453 * @dev: device pointer 3454 * Description: this is the function to suspend the device and it is called 3455 * by the platform driver to stop the network queue, release the resources, 3456 * program the PMT register (for WoL), clean and release driver resources. 3457 */ 3458 int stmmac_suspend(struct device *dev) 3459 { 3460 struct net_device *ndev = dev_get_drvdata(dev); 3461 struct stmmac_priv *priv = netdev_priv(ndev); 3462 unsigned long flags; 3463 3464 if (!ndev || !netif_running(ndev)) 3465 return 0; 3466 3467 if (ndev->phydev) 3468 phy_stop(ndev->phydev); 3469 3470 spin_lock_irqsave(&priv->lock, flags); 3471 3472 netif_device_detach(ndev); 3473 netif_stop_queue(ndev); 3474 3475 napi_disable(&priv->napi); 3476 3477 /* Stop TX/RX DMA */ 3478 priv->hw->dma->stop_tx(priv->ioaddr); 3479 priv->hw->dma->stop_rx(priv->ioaddr); 3480 3481 /* Enable Power down mode by programming the PMT regs */ 3482 if (device_may_wakeup(priv->device)) { 3483 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3484 priv->irq_wake = 1; 3485 } else { 3486 stmmac_set_mac(priv->ioaddr, false); 3487 pinctrl_pm_select_sleep_state(priv->device); 3488 /* Disable clock in case of PWM is off */ 3489 clk_disable(priv->pclk); 3490 clk_disable(priv->stmmac_clk); 3491 } 3492 spin_unlock_irqrestore(&priv->lock, flags); 3493 3494 priv->oldlink = 0; 3495 priv->speed = 0; 3496 priv->oldduplex = -1; 3497 return 0; 3498 } 3499 EXPORT_SYMBOL_GPL(stmmac_suspend); 3500 3501 /** 3502 * stmmac_resume - resume callback 3503 * @dev: device pointer 3504 * Description: when resume this function is invoked to setup the DMA and CORE 3505 * in a usable state. 3506 */ 3507 int stmmac_resume(struct device *dev) 3508 { 3509 struct net_device *ndev = dev_get_drvdata(dev); 3510 struct stmmac_priv *priv = netdev_priv(ndev); 3511 unsigned long flags; 3512 3513 if (!netif_running(ndev)) 3514 return 0; 3515 3516 /* Power Down bit, into the PM register, is cleared 3517 * automatically as soon as a magic packet or a Wake-up frame 3518 * is received. Anyway, it's better to manually clear 3519 * this bit because it can generate problems while resuming 3520 * from another devices (e.g. serial console). 3521 */ 3522 if (device_may_wakeup(priv->device)) { 3523 spin_lock_irqsave(&priv->lock, flags); 3524 priv->hw->mac->pmt(priv->hw, 0); 3525 spin_unlock_irqrestore(&priv->lock, flags); 3526 priv->irq_wake = 0; 3527 } else { 3528 pinctrl_pm_select_default_state(priv->device); 3529 /* enable the clk prevously disabled */ 3530 clk_enable(priv->stmmac_clk); 3531 clk_enable(priv->pclk); 3532 /* reset the phy so that it's ready */ 3533 if (priv->mii) 3534 stmmac_mdio_reset(priv->mii); 3535 } 3536 3537 netif_device_attach(ndev); 3538 3539 spin_lock_irqsave(&priv->lock, flags); 3540 3541 priv->cur_rx = 0; 3542 priv->dirty_rx = 0; 3543 priv->dirty_tx = 0; 3544 priv->cur_tx = 0; 3545 /* reset private mss value to force mss context settings at 3546 * next tso xmit (only used for gmac4). 3547 */ 3548 priv->mss = 0; 3549 3550 stmmac_clear_descriptors(priv); 3551 3552 stmmac_hw_setup(ndev, false); 3553 stmmac_init_tx_coalesce(priv); 3554 stmmac_set_rx_mode(ndev); 3555 3556 napi_enable(&priv->napi); 3557 3558 netif_start_queue(ndev); 3559 3560 spin_unlock_irqrestore(&priv->lock, flags); 3561 3562 if (ndev->phydev) 3563 phy_start(ndev->phydev); 3564 3565 return 0; 3566 } 3567 EXPORT_SYMBOL_GPL(stmmac_resume); 3568 3569 #ifndef MODULE 3570 static int __init stmmac_cmdline_opt(char *str) 3571 { 3572 char *opt; 3573 3574 if (!str || !*str) 3575 return -EINVAL; 3576 while ((opt = strsep(&str, ",")) != NULL) { 3577 if (!strncmp(opt, "debug:", 6)) { 3578 if (kstrtoint(opt + 6, 0, &debug)) 3579 goto err; 3580 } else if (!strncmp(opt, "phyaddr:", 8)) { 3581 if (kstrtoint(opt + 8, 0, &phyaddr)) 3582 goto err; 3583 } else if (!strncmp(opt, "buf_sz:", 7)) { 3584 if (kstrtoint(opt + 7, 0, &buf_sz)) 3585 goto err; 3586 } else if (!strncmp(opt, "tc:", 3)) { 3587 if (kstrtoint(opt + 3, 0, &tc)) 3588 goto err; 3589 } else if (!strncmp(opt, "watchdog:", 9)) { 3590 if (kstrtoint(opt + 9, 0, &watchdog)) 3591 goto err; 3592 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3593 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3594 goto err; 3595 } else if (!strncmp(opt, "pause:", 6)) { 3596 if (kstrtoint(opt + 6, 0, &pause)) 3597 goto err; 3598 } else if (!strncmp(opt, "eee_timer:", 10)) { 3599 if (kstrtoint(opt + 10, 0, &eee_timer)) 3600 goto err; 3601 } else if (!strncmp(opt, "chain_mode:", 11)) { 3602 if (kstrtoint(opt + 11, 0, &chain_mode)) 3603 goto err; 3604 } 3605 } 3606 return 0; 3607 3608 err: 3609 pr_err("%s: ERROR broken module parameter conversion", __func__); 3610 return -EINVAL; 3611 } 3612 3613 __setup("stmmaceth=", stmmac_cmdline_opt); 3614 #endif /* MODULE */ 3615 3616 static int __init stmmac_init(void) 3617 { 3618 #ifdef CONFIG_DEBUG_FS 3619 /* Create debugfs main directory if it doesn't exist yet */ 3620 if (!stmmac_fs_dir) { 3621 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 3622 3623 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 3624 pr_err("ERROR %s, debugfs create directory failed\n", 3625 STMMAC_RESOURCE_NAME); 3626 3627 return -ENOMEM; 3628 } 3629 } 3630 #endif 3631 3632 return 0; 3633 } 3634 3635 static void __exit stmmac_exit(void) 3636 { 3637 #ifdef CONFIG_DEBUG_FS 3638 debugfs_remove_recursive(stmmac_fs_dir); 3639 #endif 3640 } 3641 3642 module_init(stmmac_init) 3643 module_exit(stmmac_exit) 3644 3645 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3646 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3647 MODULE_LICENSE("GPL"); 3648