1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 992 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 993 994 if (interface == PHY_INTERFACE_MODE_USXGMII) { 995 switch (speed) { 996 case SPEED_10000: 997 ctrl |= priv->hw->link.xgmii.speed10000; 998 break; 999 case SPEED_5000: 1000 ctrl |= priv->hw->link.xgmii.speed5000; 1001 break; 1002 case SPEED_2500: 1003 ctrl |= priv->hw->link.xgmii.speed2500; 1004 break; 1005 default: 1006 return; 1007 } 1008 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1009 switch (speed) { 1010 case SPEED_100000: 1011 ctrl |= priv->hw->link.xlgmii.speed100000; 1012 break; 1013 case SPEED_50000: 1014 ctrl |= priv->hw->link.xlgmii.speed50000; 1015 break; 1016 case SPEED_40000: 1017 ctrl |= priv->hw->link.xlgmii.speed40000; 1018 break; 1019 case SPEED_25000: 1020 ctrl |= priv->hw->link.xlgmii.speed25000; 1021 break; 1022 case SPEED_10000: 1023 ctrl |= priv->hw->link.xgmii.speed10000; 1024 break; 1025 case SPEED_2500: 1026 ctrl |= priv->hw->link.speed2500; 1027 break; 1028 case SPEED_1000: 1029 ctrl |= priv->hw->link.speed1000; 1030 break; 1031 default: 1032 return; 1033 } 1034 } else { 1035 switch (speed) { 1036 case SPEED_2500: 1037 ctrl |= priv->hw->link.speed2500; 1038 break; 1039 case SPEED_1000: 1040 ctrl |= priv->hw->link.speed1000; 1041 break; 1042 case SPEED_100: 1043 ctrl |= priv->hw->link.speed100; 1044 break; 1045 case SPEED_10: 1046 ctrl |= priv->hw->link.speed10; 1047 break; 1048 default: 1049 return; 1050 } 1051 } 1052 1053 priv->speed = speed; 1054 1055 if (priv->plat->fix_mac_speed) 1056 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1057 1058 if (!duplex) 1059 ctrl &= ~priv->hw->link.duplex; 1060 else 1061 ctrl |= priv->hw->link.duplex; 1062 1063 /* Flow Control operation */ 1064 if (rx_pause && tx_pause) 1065 priv->flow_ctrl = FLOW_AUTO; 1066 else if (rx_pause && !tx_pause) 1067 priv->flow_ctrl = FLOW_RX; 1068 else if (!rx_pause && tx_pause) 1069 priv->flow_ctrl = FLOW_TX; 1070 else 1071 priv->flow_ctrl = FLOW_OFF; 1072 1073 stmmac_mac_flow_ctrl(priv, duplex); 1074 1075 if (ctrl != old_ctrl) 1076 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1077 1078 stmmac_mac_set(priv, priv->ioaddr, true); 1079 if (phy && priv->dma_cap.eee) { 1080 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1081 priv->eee_enabled = stmmac_eee_init(priv); 1082 priv->tx_lpi_enabled = priv->eee_enabled; 1083 stmmac_set_eee_pls(priv, priv->hw, true); 1084 } 1085 1086 if (priv->dma_cap.fpesel) 1087 stmmac_fpe_link_state_handle(priv, true); 1088 } 1089 1090 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1091 .validate = phylink_generic_validate, 1092 .mac_select_pcs = stmmac_mac_select_pcs, 1093 .mac_config = stmmac_mac_config, 1094 .mac_link_down = stmmac_mac_link_down, 1095 .mac_link_up = stmmac_mac_link_up, 1096 }; 1097 1098 /** 1099 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1100 * @priv: driver private structure 1101 * Description: this is to verify if the HW supports the PCS. 1102 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1103 * configured for the TBI, RTBI, or SGMII PHY interface. 1104 */ 1105 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1106 { 1107 int interface = priv->plat->interface; 1108 1109 if (priv->dma_cap.pcs) { 1110 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1111 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1112 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1113 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1114 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1115 priv->hw->pcs = STMMAC_PCS_RGMII; 1116 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1117 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1118 priv->hw->pcs = STMMAC_PCS_SGMII; 1119 } 1120 } 1121 } 1122 1123 /** 1124 * stmmac_init_phy - PHY initialization 1125 * @dev: net device structure 1126 * Description: it initializes the driver's PHY state, and attaches the PHY 1127 * to the mac driver. 1128 * Return value: 1129 * 0 on success 1130 */ 1131 static int stmmac_init_phy(struct net_device *dev) 1132 { 1133 struct stmmac_priv *priv = netdev_priv(dev); 1134 struct fwnode_handle *fwnode; 1135 int ret; 1136 1137 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1138 if (!fwnode) 1139 fwnode = dev_fwnode(priv->device); 1140 1141 if (fwnode) 1142 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1143 1144 /* Some DT bindings do not set-up the PHY handle. Let's try to 1145 * manually parse it 1146 */ 1147 if (!fwnode || ret) { 1148 int addr = priv->plat->phy_addr; 1149 struct phy_device *phydev; 1150 1151 phydev = mdiobus_get_phy(priv->mii, addr); 1152 if (!phydev) { 1153 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1154 return -ENODEV; 1155 } 1156 1157 ret = phylink_connect_phy(priv->phylink, phydev); 1158 } 1159 1160 if (!priv->plat->pmt) { 1161 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1162 1163 phylink_ethtool_get_wol(priv->phylink, &wol); 1164 device_set_wakeup_capable(priv->device, !!wol.supported); 1165 } 1166 1167 return ret; 1168 } 1169 1170 static int stmmac_phy_setup(struct stmmac_priv *priv) 1171 { 1172 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1173 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1174 int max_speed = priv->plat->max_speed; 1175 int mode = priv->plat->phy_interface; 1176 struct phylink *phylink; 1177 1178 priv->phylink_config.dev = &priv->dev->dev; 1179 priv->phylink_config.type = PHYLINK_NETDEV; 1180 if (priv->plat->mdio_bus_data) 1181 priv->phylink_config.ovr_an_inband = 1182 mdio_bus_data->xpcs_an_inband; 1183 1184 if (!fwnode) 1185 fwnode = dev_fwnode(priv->device); 1186 1187 /* Set the platform/firmware specified interface mode */ 1188 __set_bit(mode, priv->phylink_config.supported_interfaces); 1189 1190 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1191 if (priv->hw->xpcs) 1192 xpcs_get_interfaces(priv->hw->xpcs, 1193 priv->phylink_config.supported_interfaces); 1194 1195 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1196 MAC_10 | MAC_100; 1197 1198 if (!max_speed || max_speed >= 1000) 1199 priv->phylink_config.mac_capabilities |= MAC_1000; 1200 1201 if (priv->plat->has_gmac4) { 1202 if (!max_speed || max_speed >= 2500) 1203 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1204 } else if (priv->plat->has_xgmac) { 1205 if (!max_speed || max_speed >= 2500) 1206 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1207 if (!max_speed || max_speed >= 5000) 1208 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1209 if (!max_speed || max_speed >= 10000) 1210 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1211 if (!max_speed || max_speed >= 25000) 1212 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1213 if (!max_speed || max_speed >= 40000) 1214 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1215 if (!max_speed || max_speed >= 50000) 1216 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1217 if (!max_speed || max_speed >= 100000) 1218 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1219 } 1220 1221 /* Half-Duplex can only work with single queue */ 1222 if (priv->plat->tx_queues_to_use > 1) 1223 priv->phylink_config.mac_capabilities &= 1224 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1225 priv->phylink_config.mac_managed_pm = true; 1226 1227 phylink = phylink_create(&priv->phylink_config, fwnode, 1228 mode, &stmmac_phylink_mac_ops); 1229 if (IS_ERR(phylink)) 1230 return PTR_ERR(phylink); 1231 1232 priv->phylink = phylink; 1233 return 0; 1234 } 1235 1236 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1237 struct stmmac_dma_conf *dma_conf) 1238 { 1239 u32 rx_cnt = priv->plat->rx_queues_to_use; 1240 unsigned int desc_size; 1241 void *head_rx; 1242 u32 queue; 1243 1244 /* Display RX rings */ 1245 for (queue = 0; queue < rx_cnt; queue++) { 1246 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1247 1248 pr_info("\tRX Queue %u rings\n", queue); 1249 1250 if (priv->extend_desc) { 1251 head_rx = (void *)rx_q->dma_erx; 1252 desc_size = sizeof(struct dma_extended_desc); 1253 } else { 1254 head_rx = (void *)rx_q->dma_rx; 1255 desc_size = sizeof(struct dma_desc); 1256 } 1257 1258 /* Display RX ring */ 1259 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1260 rx_q->dma_rx_phy, desc_size); 1261 } 1262 } 1263 1264 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1265 struct stmmac_dma_conf *dma_conf) 1266 { 1267 u32 tx_cnt = priv->plat->tx_queues_to_use; 1268 unsigned int desc_size; 1269 void *head_tx; 1270 u32 queue; 1271 1272 /* Display TX rings */ 1273 for (queue = 0; queue < tx_cnt; queue++) { 1274 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1275 1276 pr_info("\tTX Queue %d rings\n", queue); 1277 1278 if (priv->extend_desc) { 1279 head_tx = (void *)tx_q->dma_etx; 1280 desc_size = sizeof(struct dma_extended_desc); 1281 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1282 head_tx = (void *)tx_q->dma_entx; 1283 desc_size = sizeof(struct dma_edesc); 1284 } else { 1285 head_tx = (void *)tx_q->dma_tx; 1286 desc_size = sizeof(struct dma_desc); 1287 } 1288 1289 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1290 tx_q->dma_tx_phy, desc_size); 1291 } 1292 } 1293 1294 static void stmmac_display_rings(struct stmmac_priv *priv, 1295 struct stmmac_dma_conf *dma_conf) 1296 { 1297 /* Display RX ring */ 1298 stmmac_display_rx_rings(priv, dma_conf); 1299 1300 /* Display TX ring */ 1301 stmmac_display_tx_rings(priv, dma_conf); 1302 } 1303 1304 static int stmmac_set_bfsize(int mtu, int bufsize) 1305 { 1306 int ret = bufsize; 1307 1308 if (mtu >= BUF_SIZE_8KiB) 1309 ret = BUF_SIZE_16KiB; 1310 else if (mtu >= BUF_SIZE_4KiB) 1311 ret = BUF_SIZE_8KiB; 1312 else if (mtu >= BUF_SIZE_2KiB) 1313 ret = BUF_SIZE_4KiB; 1314 else if (mtu > DEFAULT_BUFSIZE) 1315 ret = BUF_SIZE_2KiB; 1316 else 1317 ret = DEFAULT_BUFSIZE; 1318 1319 return ret; 1320 } 1321 1322 /** 1323 * stmmac_clear_rx_descriptors - clear RX descriptors 1324 * @priv: driver private structure 1325 * @dma_conf: structure to take the dma data 1326 * @queue: RX queue index 1327 * Description: this function is called to clear the RX descriptors 1328 * in case of both basic and extended descriptors are used. 1329 */ 1330 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1331 struct stmmac_dma_conf *dma_conf, 1332 u32 queue) 1333 { 1334 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1335 int i; 1336 1337 /* Clear the RX descriptors */ 1338 for (i = 0; i < dma_conf->dma_rx_size; i++) 1339 if (priv->extend_desc) 1340 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1341 priv->use_riwt, priv->mode, 1342 (i == dma_conf->dma_rx_size - 1), 1343 dma_conf->dma_buf_sz); 1344 else 1345 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1346 priv->use_riwt, priv->mode, 1347 (i == dma_conf->dma_rx_size - 1), 1348 dma_conf->dma_buf_sz); 1349 } 1350 1351 /** 1352 * stmmac_clear_tx_descriptors - clear tx descriptors 1353 * @priv: driver private structure 1354 * @dma_conf: structure to take the dma data 1355 * @queue: TX queue index. 1356 * Description: this function is called to clear the TX descriptors 1357 * in case of both basic and extended descriptors are used. 1358 */ 1359 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1360 struct stmmac_dma_conf *dma_conf, 1361 u32 queue) 1362 { 1363 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1364 int i; 1365 1366 /* Clear the TX descriptors */ 1367 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1368 int last = (i == (dma_conf->dma_tx_size - 1)); 1369 struct dma_desc *p; 1370 1371 if (priv->extend_desc) 1372 p = &tx_q->dma_etx[i].basic; 1373 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1374 p = &tx_q->dma_entx[i].basic; 1375 else 1376 p = &tx_q->dma_tx[i]; 1377 1378 stmmac_init_tx_desc(priv, p, priv->mode, last); 1379 } 1380 } 1381 1382 /** 1383 * stmmac_clear_descriptors - clear descriptors 1384 * @priv: driver private structure 1385 * @dma_conf: structure to take the dma data 1386 * Description: this function is called to clear the TX and RX descriptors 1387 * in case of both basic and extended descriptors are used. 1388 */ 1389 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1390 struct stmmac_dma_conf *dma_conf) 1391 { 1392 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1393 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1394 u32 queue; 1395 1396 /* Clear the RX descriptors */ 1397 for (queue = 0; queue < rx_queue_cnt; queue++) 1398 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1399 1400 /* Clear the TX descriptors */ 1401 for (queue = 0; queue < tx_queue_cnt; queue++) 1402 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1403 } 1404 1405 /** 1406 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1407 * @priv: driver private structure 1408 * @dma_conf: structure to take the dma data 1409 * @p: descriptor pointer 1410 * @i: descriptor index 1411 * @flags: gfp flag 1412 * @queue: RX queue index 1413 * Description: this function is called to allocate a receive buffer, perform 1414 * the DMA mapping and init the descriptor. 1415 */ 1416 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1417 struct stmmac_dma_conf *dma_conf, 1418 struct dma_desc *p, 1419 int i, gfp_t flags, u32 queue) 1420 { 1421 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1422 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1423 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1424 1425 if (priv->dma_cap.addr64 <= 32) 1426 gfp |= GFP_DMA32; 1427 1428 if (!buf->page) { 1429 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1430 if (!buf->page) 1431 return -ENOMEM; 1432 buf->page_offset = stmmac_rx_offset(priv); 1433 } 1434 1435 if (priv->sph && !buf->sec_page) { 1436 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1437 if (!buf->sec_page) 1438 return -ENOMEM; 1439 1440 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1441 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1442 } else { 1443 buf->sec_page = NULL; 1444 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1445 } 1446 1447 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1448 1449 stmmac_set_desc_addr(priv, p, buf->addr); 1450 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1451 stmmac_init_desc3(priv, p); 1452 1453 return 0; 1454 } 1455 1456 /** 1457 * stmmac_free_rx_buffer - free RX dma buffers 1458 * @priv: private structure 1459 * @rx_q: RX queue 1460 * @i: buffer index. 1461 */ 1462 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1463 struct stmmac_rx_queue *rx_q, 1464 int i) 1465 { 1466 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1467 1468 if (buf->page) 1469 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1470 buf->page = NULL; 1471 1472 if (buf->sec_page) 1473 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1474 buf->sec_page = NULL; 1475 } 1476 1477 /** 1478 * stmmac_free_tx_buffer - free RX dma buffers 1479 * @priv: private structure 1480 * @dma_conf: structure to take the dma data 1481 * @queue: RX queue index 1482 * @i: buffer index. 1483 */ 1484 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1485 struct stmmac_dma_conf *dma_conf, 1486 u32 queue, int i) 1487 { 1488 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1489 1490 if (tx_q->tx_skbuff_dma[i].buf && 1491 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1492 if (tx_q->tx_skbuff_dma[i].map_as_page) 1493 dma_unmap_page(priv->device, 1494 tx_q->tx_skbuff_dma[i].buf, 1495 tx_q->tx_skbuff_dma[i].len, 1496 DMA_TO_DEVICE); 1497 else 1498 dma_unmap_single(priv->device, 1499 tx_q->tx_skbuff_dma[i].buf, 1500 tx_q->tx_skbuff_dma[i].len, 1501 DMA_TO_DEVICE); 1502 } 1503 1504 if (tx_q->xdpf[i] && 1505 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1506 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1507 xdp_return_frame(tx_q->xdpf[i]); 1508 tx_q->xdpf[i] = NULL; 1509 } 1510 1511 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1512 tx_q->xsk_frames_done++; 1513 1514 if (tx_q->tx_skbuff[i] && 1515 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1516 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1517 tx_q->tx_skbuff[i] = NULL; 1518 } 1519 1520 tx_q->tx_skbuff_dma[i].buf = 0; 1521 tx_q->tx_skbuff_dma[i].map_as_page = false; 1522 } 1523 1524 /** 1525 * dma_free_rx_skbufs - free RX dma buffers 1526 * @priv: private structure 1527 * @dma_conf: structure to take the dma data 1528 * @queue: RX queue index 1529 */ 1530 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1531 struct stmmac_dma_conf *dma_conf, 1532 u32 queue) 1533 { 1534 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1535 int i; 1536 1537 for (i = 0; i < dma_conf->dma_rx_size; i++) 1538 stmmac_free_rx_buffer(priv, rx_q, i); 1539 } 1540 1541 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1542 struct stmmac_dma_conf *dma_conf, 1543 u32 queue, gfp_t flags) 1544 { 1545 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1546 int i; 1547 1548 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1549 struct dma_desc *p; 1550 int ret; 1551 1552 if (priv->extend_desc) 1553 p = &((rx_q->dma_erx + i)->basic); 1554 else 1555 p = rx_q->dma_rx + i; 1556 1557 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1558 queue); 1559 if (ret) 1560 return ret; 1561 1562 rx_q->buf_alloc_num++; 1563 } 1564 1565 return 0; 1566 } 1567 1568 /** 1569 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1570 * @priv: private structure 1571 * @dma_conf: structure to take the dma data 1572 * @queue: RX queue index 1573 */ 1574 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1575 struct stmmac_dma_conf *dma_conf, 1576 u32 queue) 1577 { 1578 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1579 int i; 1580 1581 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1582 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1583 1584 if (!buf->xdp) 1585 continue; 1586 1587 xsk_buff_free(buf->xdp); 1588 buf->xdp = NULL; 1589 } 1590 } 1591 1592 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1593 struct stmmac_dma_conf *dma_conf, 1594 u32 queue) 1595 { 1596 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1597 int i; 1598 1599 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1600 struct stmmac_rx_buffer *buf; 1601 dma_addr_t dma_addr; 1602 struct dma_desc *p; 1603 1604 if (priv->extend_desc) 1605 p = (struct dma_desc *)(rx_q->dma_erx + i); 1606 else 1607 p = rx_q->dma_rx + i; 1608 1609 buf = &rx_q->buf_pool[i]; 1610 1611 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1612 if (!buf->xdp) 1613 return -ENOMEM; 1614 1615 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1616 stmmac_set_desc_addr(priv, p, dma_addr); 1617 rx_q->buf_alloc_num++; 1618 } 1619 1620 return 0; 1621 } 1622 1623 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1624 { 1625 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1626 return NULL; 1627 1628 return xsk_get_pool_from_qid(priv->dev, queue); 1629 } 1630 1631 /** 1632 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1633 * @priv: driver private structure 1634 * @dma_conf: structure to take the dma data 1635 * @queue: RX queue index 1636 * @flags: gfp flag. 1637 * Description: this function initializes the DMA RX descriptors 1638 * and allocates the socket buffers. It supports the chained and ring 1639 * modes. 1640 */ 1641 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1642 struct stmmac_dma_conf *dma_conf, 1643 u32 queue, gfp_t flags) 1644 { 1645 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1646 int ret; 1647 1648 netif_dbg(priv, probe, priv->dev, 1649 "(%s) dma_rx_phy=0x%08x\n", __func__, 1650 (u32)rx_q->dma_rx_phy); 1651 1652 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1653 1654 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1655 1656 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1657 1658 if (rx_q->xsk_pool) { 1659 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1660 MEM_TYPE_XSK_BUFF_POOL, 1661 NULL)); 1662 netdev_info(priv->dev, 1663 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1664 rx_q->queue_index); 1665 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1666 } else { 1667 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1668 MEM_TYPE_PAGE_POOL, 1669 rx_q->page_pool)); 1670 netdev_info(priv->dev, 1671 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1672 rx_q->queue_index); 1673 } 1674 1675 if (rx_q->xsk_pool) { 1676 /* RX XDP ZC buffer pool may not be populated, e.g. 1677 * xdpsock TX-only. 1678 */ 1679 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1680 } else { 1681 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1682 if (ret < 0) 1683 return -ENOMEM; 1684 } 1685 1686 /* Setup the chained descriptor addresses */ 1687 if (priv->mode == STMMAC_CHAIN_MODE) { 1688 if (priv->extend_desc) 1689 stmmac_mode_init(priv, rx_q->dma_erx, 1690 rx_q->dma_rx_phy, 1691 dma_conf->dma_rx_size, 1); 1692 else 1693 stmmac_mode_init(priv, rx_q->dma_rx, 1694 rx_q->dma_rx_phy, 1695 dma_conf->dma_rx_size, 0); 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int init_dma_rx_desc_rings(struct net_device *dev, 1702 struct stmmac_dma_conf *dma_conf, 1703 gfp_t flags) 1704 { 1705 struct stmmac_priv *priv = netdev_priv(dev); 1706 u32 rx_count = priv->plat->rx_queues_to_use; 1707 int queue; 1708 int ret; 1709 1710 /* RX INITIALIZATION */ 1711 netif_dbg(priv, probe, priv->dev, 1712 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1713 1714 for (queue = 0; queue < rx_count; queue++) { 1715 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1716 if (ret) 1717 goto err_init_rx_buffers; 1718 } 1719 1720 return 0; 1721 1722 err_init_rx_buffers: 1723 while (queue >= 0) { 1724 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1725 1726 if (rx_q->xsk_pool) 1727 dma_free_rx_xskbufs(priv, dma_conf, queue); 1728 else 1729 dma_free_rx_skbufs(priv, dma_conf, queue); 1730 1731 rx_q->buf_alloc_num = 0; 1732 rx_q->xsk_pool = NULL; 1733 1734 queue--; 1735 } 1736 1737 return ret; 1738 } 1739 1740 /** 1741 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1742 * @priv: driver private structure 1743 * @dma_conf: structure to take the dma data 1744 * @queue: TX queue index 1745 * Description: this function initializes the DMA TX descriptors 1746 * and allocates the socket buffers. It supports the chained and ring 1747 * modes. 1748 */ 1749 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1750 struct stmmac_dma_conf *dma_conf, 1751 u32 queue) 1752 { 1753 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1754 int i; 1755 1756 netif_dbg(priv, probe, priv->dev, 1757 "(%s) dma_tx_phy=0x%08x\n", __func__, 1758 (u32)tx_q->dma_tx_phy); 1759 1760 /* Setup the chained descriptor addresses */ 1761 if (priv->mode == STMMAC_CHAIN_MODE) { 1762 if (priv->extend_desc) 1763 stmmac_mode_init(priv, tx_q->dma_etx, 1764 tx_q->dma_tx_phy, 1765 dma_conf->dma_tx_size, 1); 1766 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1767 stmmac_mode_init(priv, tx_q->dma_tx, 1768 tx_q->dma_tx_phy, 1769 dma_conf->dma_tx_size, 0); 1770 } 1771 1772 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1773 1774 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1775 struct dma_desc *p; 1776 1777 if (priv->extend_desc) 1778 p = &((tx_q->dma_etx + i)->basic); 1779 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1780 p = &((tx_q->dma_entx + i)->basic); 1781 else 1782 p = tx_q->dma_tx + i; 1783 1784 stmmac_clear_desc(priv, p); 1785 1786 tx_q->tx_skbuff_dma[i].buf = 0; 1787 tx_q->tx_skbuff_dma[i].map_as_page = false; 1788 tx_q->tx_skbuff_dma[i].len = 0; 1789 tx_q->tx_skbuff_dma[i].last_segment = false; 1790 tx_q->tx_skbuff[i] = NULL; 1791 } 1792 1793 return 0; 1794 } 1795 1796 static int init_dma_tx_desc_rings(struct net_device *dev, 1797 struct stmmac_dma_conf *dma_conf) 1798 { 1799 struct stmmac_priv *priv = netdev_priv(dev); 1800 u32 tx_queue_cnt; 1801 u32 queue; 1802 1803 tx_queue_cnt = priv->plat->tx_queues_to_use; 1804 1805 for (queue = 0; queue < tx_queue_cnt; queue++) 1806 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1807 1808 return 0; 1809 } 1810 1811 /** 1812 * init_dma_desc_rings - init the RX/TX descriptor rings 1813 * @dev: net device structure 1814 * @dma_conf: structure to take the dma data 1815 * @flags: gfp flag. 1816 * Description: this function initializes the DMA RX/TX descriptors 1817 * and allocates the socket buffers. It supports the chained and ring 1818 * modes. 1819 */ 1820 static int init_dma_desc_rings(struct net_device *dev, 1821 struct stmmac_dma_conf *dma_conf, 1822 gfp_t flags) 1823 { 1824 struct stmmac_priv *priv = netdev_priv(dev); 1825 int ret; 1826 1827 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1828 if (ret) 1829 return ret; 1830 1831 ret = init_dma_tx_desc_rings(dev, dma_conf); 1832 1833 stmmac_clear_descriptors(priv, dma_conf); 1834 1835 if (netif_msg_hw(priv)) 1836 stmmac_display_rings(priv, dma_conf); 1837 1838 return ret; 1839 } 1840 1841 /** 1842 * dma_free_tx_skbufs - free TX dma buffers 1843 * @priv: private structure 1844 * @dma_conf: structure to take the dma data 1845 * @queue: TX queue index 1846 */ 1847 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1848 struct stmmac_dma_conf *dma_conf, 1849 u32 queue) 1850 { 1851 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1852 int i; 1853 1854 tx_q->xsk_frames_done = 0; 1855 1856 for (i = 0; i < dma_conf->dma_tx_size; i++) 1857 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1858 1859 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1860 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1861 tx_q->xsk_frames_done = 0; 1862 tx_q->xsk_pool = NULL; 1863 } 1864 } 1865 1866 /** 1867 * stmmac_free_tx_skbufs - free TX skb buffers 1868 * @priv: private structure 1869 */ 1870 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1871 { 1872 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1873 u32 queue; 1874 1875 for (queue = 0; queue < tx_queue_cnt; queue++) 1876 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1877 } 1878 1879 /** 1880 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1881 * @priv: private structure 1882 * @dma_conf: structure to take the dma data 1883 * @queue: RX queue index 1884 */ 1885 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1886 struct stmmac_dma_conf *dma_conf, 1887 u32 queue) 1888 { 1889 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1890 1891 /* Release the DMA RX socket buffers */ 1892 if (rx_q->xsk_pool) 1893 dma_free_rx_xskbufs(priv, dma_conf, queue); 1894 else 1895 dma_free_rx_skbufs(priv, dma_conf, queue); 1896 1897 rx_q->buf_alloc_num = 0; 1898 rx_q->xsk_pool = NULL; 1899 1900 /* Free DMA regions of consistent memory previously allocated */ 1901 if (!priv->extend_desc) 1902 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1903 sizeof(struct dma_desc), 1904 rx_q->dma_rx, rx_q->dma_rx_phy); 1905 else 1906 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1907 sizeof(struct dma_extended_desc), 1908 rx_q->dma_erx, rx_q->dma_rx_phy); 1909 1910 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1911 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1912 1913 kfree(rx_q->buf_pool); 1914 if (rx_q->page_pool) 1915 page_pool_destroy(rx_q->page_pool); 1916 } 1917 1918 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1919 struct stmmac_dma_conf *dma_conf) 1920 { 1921 u32 rx_count = priv->plat->rx_queues_to_use; 1922 u32 queue; 1923 1924 /* Free RX queue resources */ 1925 for (queue = 0; queue < rx_count; queue++) 1926 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1927 } 1928 1929 /** 1930 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1931 * @priv: private structure 1932 * @dma_conf: structure to take the dma data 1933 * @queue: TX queue index 1934 */ 1935 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1936 struct stmmac_dma_conf *dma_conf, 1937 u32 queue) 1938 { 1939 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1940 size_t size; 1941 void *addr; 1942 1943 /* Release the DMA TX socket buffers */ 1944 dma_free_tx_skbufs(priv, dma_conf, queue); 1945 1946 if (priv->extend_desc) { 1947 size = sizeof(struct dma_extended_desc); 1948 addr = tx_q->dma_etx; 1949 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1950 size = sizeof(struct dma_edesc); 1951 addr = tx_q->dma_entx; 1952 } else { 1953 size = sizeof(struct dma_desc); 1954 addr = tx_q->dma_tx; 1955 } 1956 1957 size *= dma_conf->dma_tx_size; 1958 1959 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1960 1961 kfree(tx_q->tx_skbuff_dma); 1962 kfree(tx_q->tx_skbuff); 1963 } 1964 1965 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1966 struct stmmac_dma_conf *dma_conf) 1967 { 1968 u32 tx_count = priv->plat->tx_queues_to_use; 1969 u32 queue; 1970 1971 /* Free TX queue resources */ 1972 for (queue = 0; queue < tx_count; queue++) 1973 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1974 } 1975 1976 /** 1977 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1978 * @priv: private structure 1979 * @dma_conf: structure to take the dma data 1980 * @queue: RX queue index 1981 * Description: according to which descriptor can be used (extend or basic) 1982 * this function allocates the resources for TX and RX paths. In case of 1983 * reception, for example, it pre-allocated the RX socket buffer in order to 1984 * allow zero-copy mechanism. 1985 */ 1986 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1987 struct stmmac_dma_conf *dma_conf, 1988 u32 queue) 1989 { 1990 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1991 struct stmmac_channel *ch = &priv->channel[queue]; 1992 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1993 struct page_pool_params pp_params = { 0 }; 1994 unsigned int num_pages; 1995 unsigned int napi_id; 1996 int ret; 1997 1998 rx_q->queue_index = queue; 1999 rx_q->priv_data = priv; 2000 2001 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2002 pp_params.pool_size = dma_conf->dma_rx_size; 2003 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2004 pp_params.order = ilog2(num_pages); 2005 pp_params.nid = dev_to_node(priv->device); 2006 pp_params.dev = priv->device; 2007 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2008 pp_params.offset = stmmac_rx_offset(priv); 2009 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2010 2011 rx_q->page_pool = page_pool_create(&pp_params); 2012 if (IS_ERR(rx_q->page_pool)) { 2013 ret = PTR_ERR(rx_q->page_pool); 2014 rx_q->page_pool = NULL; 2015 return ret; 2016 } 2017 2018 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2019 sizeof(*rx_q->buf_pool), 2020 GFP_KERNEL); 2021 if (!rx_q->buf_pool) 2022 return -ENOMEM; 2023 2024 if (priv->extend_desc) { 2025 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2026 dma_conf->dma_rx_size * 2027 sizeof(struct dma_extended_desc), 2028 &rx_q->dma_rx_phy, 2029 GFP_KERNEL); 2030 if (!rx_q->dma_erx) 2031 return -ENOMEM; 2032 2033 } else { 2034 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2035 dma_conf->dma_rx_size * 2036 sizeof(struct dma_desc), 2037 &rx_q->dma_rx_phy, 2038 GFP_KERNEL); 2039 if (!rx_q->dma_rx) 2040 return -ENOMEM; 2041 } 2042 2043 if (stmmac_xdp_is_enabled(priv) && 2044 test_bit(queue, priv->af_xdp_zc_qps)) 2045 napi_id = ch->rxtx_napi.napi_id; 2046 else 2047 napi_id = ch->rx_napi.napi_id; 2048 2049 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2050 rx_q->queue_index, 2051 napi_id); 2052 if (ret) { 2053 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2054 return -EINVAL; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2061 struct stmmac_dma_conf *dma_conf) 2062 { 2063 u32 rx_count = priv->plat->rx_queues_to_use; 2064 u32 queue; 2065 int ret; 2066 2067 /* RX queues buffers and DMA */ 2068 for (queue = 0; queue < rx_count; queue++) { 2069 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2070 if (ret) 2071 goto err_dma; 2072 } 2073 2074 return 0; 2075 2076 err_dma: 2077 free_dma_rx_desc_resources(priv, dma_conf); 2078 2079 return ret; 2080 } 2081 2082 /** 2083 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2084 * @priv: private structure 2085 * @dma_conf: structure to take the dma data 2086 * @queue: TX queue index 2087 * Description: according to which descriptor can be used (extend or basic) 2088 * this function allocates the resources for TX and RX paths. In case of 2089 * reception, for example, it pre-allocated the RX socket buffer in order to 2090 * allow zero-copy mechanism. 2091 */ 2092 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2093 struct stmmac_dma_conf *dma_conf, 2094 u32 queue) 2095 { 2096 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2097 size_t size; 2098 void *addr; 2099 2100 tx_q->queue_index = queue; 2101 tx_q->priv_data = priv; 2102 2103 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2104 sizeof(*tx_q->tx_skbuff_dma), 2105 GFP_KERNEL); 2106 if (!tx_q->tx_skbuff_dma) 2107 return -ENOMEM; 2108 2109 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2110 sizeof(struct sk_buff *), 2111 GFP_KERNEL); 2112 if (!tx_q->tx_skbuff) 2113 return -ENOMEM; 2114 2115 if (priv->extend_desc) 2116 size = sizeof(struct dma_extended_desc); 2117 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2118 size = sizeof(struct dma_edesc); 2119 else 2120 size = sizeof(struct dma_desc); 2121 2122 size *= dma_conf->dma_tx_size; 2123 2124 addr = dma_alloc_coherent(priv->device, size, 2125 &tx_q->dma_tx_phy, GFP_KERNEL); 2126 if (!addr) 2127 return -ENOMEM; 2128 2129 if (priv->extend_desc) 2130 tx_q->dma_etx = addr; 2131 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2132 tx_q->dma_entx = addr; 2133 else 2134 tx_q->dma_tx = addr; 2135 2136 return 0; 2137 } 2138 2139 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2140 struct stmmac_dma_conf *dma_conf) 2141 { 2142 u32 tx_count = priv->plat->tx_queues_to_use; 2143 u32 queue; 2144 int ret; 2145 2146 /* TX queues buffers and DMA */ 2147 for (queue = 0; queue < tx_count; queue++) { 2148 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2149 if (ret) 2150 goto err_dma; 2151 } 2152 2153 return 0; 2154 2155 err_dma: 2156 free_dma_tx_desc_resources(priv, dma_conf); 2157 return ret; 2158 } 2159 2160 /** 2161 * alloc_dma_desc_resources - alloc TX/RX resources. 2162 * @priv: private structure 2163 * @dma_conf: structure to take the dma data 2164 * Description: according to which descriptor can be used (extend or basic) 2165 * this function allocates the resources for TX and RX paths. In case of 2166 * reception, for example, it pre-allocated the RX socket buffer in order to 2167 * allow zero-copy mechanism. 2168 */ 2169 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2170 struct stmmac_dma_conf *dma_conf) 2171 { 2172 /* RX Allocation */ 2173 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2174 2175 if (ret) 2176 return ret; 2177 2178 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2179 2180 return ret; 2181 } 2182 2183 /** 2184 * free_dma_desc_resources - free dma desc resources 2185 * @priv: private structure 2186 * @dma_conf: structure to take the dma data 2187 */ 2188 static void free_dma_desc_resources(struct stmmac_priv *priv, 2189 struct stmmac_dma_conf *dma_conf) 2190 { 2191 /* Release the DMA TX socket buffers */ 2192 free_dma_tx_desc_resources(priv, dma_conf); 2193 2194 /* Release the DMA RX socket buffers later 2195 * to ensure all pending XDP_TX buffers are returned. 2196 */ 2197 free_dma_rx_desc_resources(priv, dma_conf); 2198 } 2199 2200 /** 2201 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2202 * @priv: driver private structure 2203 * Description: It is used for enabling the rx queues in the MAC 2204 */ 2205 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2206 { 2207 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2208 int queue; 2209 u8 mode; 2210 2211 for (queue = 0; queue < rx_queues_count; queue++) { 2212 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2213 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2214 } 2215 } 2216 2217 /** 2218 * stmmac_start_rx_dma - start RX DMA channel 2219 * @priv: driver private structure 2220 * @chan: RX channel index 2221 * Description: 2222 * This starts a RX DMA channel 2223 */ 2224 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2225 { 2226 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2227 stmmac_start_rx(priv, priv->ioaddr, chan); 2228 } 2229 2230 /** 2231 * stmmac_start_tx_dma - start TX DMA channel 2232 * @priv: driver private structure 2233 * @chan: TX channel index 2234 * Description: 2235 * This starts a TX DMA channel 2236 */ 2237 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2238 { 2239 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2240 stmmac_start_tx(priv, priv->ioaddr, chan); 2241 } 2242 2243 /** 2244 * stmmac_stop_rx_dma - stop RX DMA channel 2245 * @priv: driver private structure 2246 * @chan: RX channel index 2247 * Description: 2248 * This stops a RX DMA channel 2249 */ 2250 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2251 { 2252 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2253 stmmac_stop_rx(priv, priv->ioaddr, chan); 2254 } 2255 2256 /** 2257 * stmmac_stop_tx_dma - stop TX DMA channel 2258 * @priv: driver private structure 2259 * @chan: TX channel index 2260 * Description: 2261 * This stops a TX DMA channel 2262 */ 2263 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2264 { 2265 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2266 stmmac_stop_tx(priv, priv->ioaddr, chan); 2267 } 2268 2269 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2270 { 2271 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2272 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2273 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2274 u32 chan; 2275 2276 for (chan = 0; chan < dma_csr_ch; chan++) { 2277 struct stmmac_channel *ch = &priv->channel[chan]; 2278 unsigned long flags; 2279 2280 spin_lock_irqsave(&ch->lock, flags); 2281 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2282 spin_unlock_irqrestore(&ch->lock, flags); 2283 } 2284 } 2285 2286 /** 2287 * stmmac_start_all_dma - start all RX and TX DMA channels 2288 * @priv: driver private structure 2289 * Description: 2290 * This starts all the RX and TX DMA channels 2291 */ 2292 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2293 { 2294 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2295 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2296 u32 chan = 0; 2297 2298 for (chan = 0; chan < rx_channels_count; chan++) 2299 stmmac_start_rx_dma(priv, chan); 2300 2301 for (chan = 0; chan < tx_channels_count; chan++) 2302 stmmac_start_tx_dma(priv, chan); 2303 } 2304 2305 /** 2306 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2307 * @priv: driver private structure 2308 * Description: 2309 * This stops the RX and TX DMA channels 2310 */ 2311 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2312 { 2313 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2314 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2315 u32 chan = 0; 2316 2317 for (chan = 0; chan < rx_channels_count; chan++) 2318 stmmac_stop_rx_dma(priv, chan); 2319 2320 for (chan = 0; chan < tx_channels_count; chan++) 2321 stmmac_stop_tx_dma(priv, chan); 2322 } 2323 2324 /** 2325 * stmmac_dma_operation_mode - HW DMA operation mode 2326 * @priv: driver private structure 2327 * Description: it is used for configuring the DMA operation mode register in 2328 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2329 */ 2330 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2331 { 2332 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2333 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2334 int rxfifosz = priv->plat->rx_fifo_size; 2335 int txfifosz = priv->plat->tx_fifo_size; 2336 u32 txmode = 0; 2337 u32 rxmode = 0; 2338 u32 chan = 0; 2339 u8 qmode = 0; 2340 2341 if (rxfifosz == 0) 2342 rxfifosz = priv->dma_cap.rx_fifo_size; 2343 if (txfifosz == 0) 2344 txfifosz = priv->dma_cap.tx_fifo_size; 2345 2346 /* Adjust for real per queue fifo size */ 2347 rxfifosz /= rx_channels_count; 2348 txfifosz /= tx_channels_count; 2349 2350 if (priv->plat->force_thresh_dma_mode) { 2351 txmode = tc; 2352 rxmode = tc; 2353 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2354 /* 2355 * In case of GMAC, SF mode can be enabled 2356 * to perform the TX COE in HW. This depends on: 2357 * 1) TX COE if actually supported 2358 * 2) There is no bugged Jumbo frame support 2359 * that needs to not insert csum in the TDES. 2360 */ 2361 txmode = SF_DMA_MODE; 2362 rxmode = SF_DMA_MODE; 2363 priv->xstats.threshold = SF_DMA_MODE; 2364 } else { 2365 txmode = tc; 2366 rxmode = SF_DMA_MODE; 2367 } 2368 2369 /* configure all channels */ 2370 for (chan = 0; chan < rx_channels_count; chan++) { 2371 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2372 u32 buf_size; 2373 2374 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2375 2376 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2377 rxfifosz, qmode); 2378 2379 if (rx_q->xsk_pool) { 2380 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2381 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2382 buf_size, 2383 chan); 2384 } else { 2385 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2386 priv->dma_conf.dma_buf_sz, 2387 chan); 2388 } 2389 } 2390 2391 for (chan = 0; chan < tx_channels_count; chan++) { 2392 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2393 2394 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2395 txfifosz, qmode); 2396 } 2397 } 2398 2399 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2400 { 2401 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2402 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2403 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2404 unsigned int entry = tx_q->cur_tx; 2405 struct dma_desc *tx_desc = NULL; 2406 struct xdp_desc xdp_desc; 2407 bool work_done = true; 2408 2409 /* Avoids TX time-out as we are sharing with slow path */ 2410 txq_trans_cond_update(nq); 2411 2412 budget = min(budget, stmmac_tx_avail(priv, queue)); 2413 2414 while (budget-- > 0) { 2415 dma_addr_t dma_addr; 2416 bool set_ic; 2417 2418 /* We are sharing with slow path and stop XSK TX desc submission when 2419 * available TX ring is less than threshold. 2420 */ 2421 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2422 !netif_carrier_ok(priv->dev)) { 2423 work_done = false; 2424 break; 2425 } 2426 2427 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2428 break; 2429 2430 if (likely(priv->extend_desc)) 2431 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2432 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2433 tx_desc = &tx_q->dma_entx[entry].basic; 2434 else 2435 tx_desc = tx_q->dma_tx + entry; 2436 2437 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2438 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2439 2440 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2441 2442 /* To return XDP buffer to XSK pool, we simple call 2443 * xsk_tx_completed(), so we don't need to fill up 2444 * 'buf' and 'xdpf'. 2445 */ 2446 tx_q->tx_skbuff_dma[entry].buf = 0; 2447 tx_q->xdpf[entry] = NULL; 2448 2449 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2450 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2451 tx_q->tx_skbuff_dma[entry].last_segment = true; 2452 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2453 2454 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2455 2456 tx_q->tx_count_frames++; 2457 2458 if (!priv->tx_coal_frames[queue]) 2459 set_ic = false; 2460 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2461 set_ic = true; 2462 else 2463 set_ic = false; 2464 2465 if (set_ic) { 2466 tx_q->tx_count_frames = 0; 2467 stmmac_set_tx_ic(priv, tx_desc); 2468 priv->xstats.tx_set_ic_bit++; 2469 } 2470 2471 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2472 true, priv->mode, true, true, 2473 xdp_desc.len); 2474 2475 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2476 2477 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2478 entry = tx_q->cur_tx; 2479 } 2480 2481 if (tx_desc) { 2482 stmmac_flush_tx_descriptors(priv, queue); 2483 xsk_tx_release(pool); 2484 } 2485 2486 /* Return true if all of the 3 conditions are met 2487 * a) TX Budget is still available 2488 * b) work_done = true when XSK TX desc peek is empty (no more 2489 * pending XSK TX for transmission) 2490 */ 2491 return !!budget && work_done; 2492 } 2493 2494 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2495 { 2496 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2497 tc += 64; 2498 2499 if (priv->plat->force_thresh_dma_mode) 2500 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2501 else 2502 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2503 chan); 2504 2505 priv->xstats.threshold = tc; 2506 } 2507 } 2508 2509 /** 2510 * stmmac_tx_clean - to manage the transmission completion 2511 * @priv: driver private structure 2512 * @budget: napi budget limiting this functions packet handling 2513 * @queue: TX queue index 2514 * Description: it reclaims the transmit resources after transmission completes. 2515 */ 2516 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2517 { 2518 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2519 unsigned int bytes_compl = 0, pkts_compl = 0; 2520 unsigned int entry, xmits = 0, count = 0; 2521 2522 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2523 2524 priv->xstats.tx_clean++; 2525 2526 tx_q->xsk_frames_done = 0; 2527 2528 entry = tx_q->dirty_tx; 2529 2530 /* Try to clean all TX complete frame in 1 shot */ 2531 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2532 struct xdp_frame *xdpf; 2533 struct sk_buff *skb; 2534 struct dma_desc *p; 2535 int status; 2536 2537 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2538 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2539 xdpf = tx_q->xdpf[entry]; 2540 skb = NULL; 2541 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2542 xdpf = NULL; 2543 skb = tx_q->tx_skbuff[entry]; 2544 } else { 2545 xdpf = NULL; 2546 skb = NULL; 2547 } 2548 2549 if (priv->extend_desc) 2550 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2551 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2552 p = &tx_q->dma_entx[entry].basic; 2553 else 2554 p = tx_q->dma_tx + entry; 2555 2556 status = stmmac_tx_status(priv, &priv->dev->stats, 2557 &priv->xstats, p, priv->ioaddr); 2558 /* Check if the descriptor is owned by the DMA */ 2559 if (unlikely(status & tx_dma_own)) 2560 break; 2561 2562 count++; 2563 2564 /* Make sure descriptor fields are read after reading 2565 * the own bit. 2566 */ 2567 dma_rmb(); 2568 2569 /* Just consider the last segment and ...*/ 2570 if (likely(!(status & tx_not_ls))) { 2571 /* ... verify the status error condition */ 2572 if (unlikely(status & tx_err)) { 2573 priv->dev->stats.tx_errors++; 2574 if (unlikely(status & tx_err_bump_tc)) 2575 stmmac_bump_dma_threshold(priv, queue); 2576 } else { 2577 priv->dev->stats.tx_packets++; 2578 priv->xstats.tx_pkt_n++; 2579 priv->xstats.txq_stats[queue].tx_pkt_n++; 2580 } 2581 if (skb) 2582 stmmac_get_tx_hwtstamp(priv, p, skb); 2583 } 2584 2585 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2586 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2587 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2588 dma_unmap_page(priv->device, 2589 tx_q->tx_skbuff_dma[entry].buf, 2590 tx_q->tx_skbuff_dma[entry].len, 2591 DMA_TO_DEVICE); 2592 else 2593 dma_unmap_single(priv->device, 2594 tx_q->tx_skbuff_dma[entry].buf, 2595 tx_q->tx_skbuff_dma[entry].len, 2596 DMA_TO_DEVICE); 2597 tx_q->tx_skbuff_dma[entry].buf = 0; 2598 tx_q->tx_skbuff_dma[entry].len = 0; 2599 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2600 } 2601 2602 stmmac_clean_desc3(priv, tx_q, p); 2603 2604 tx_q->tx_skbuff_dma[entry].last_segment = false; 2605 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2606 2607 if (xdpf && 2608 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2609 xdp_return_frame_rx_napi(xdpf); 2610 tx_q->xdpf[entry] = NULL; 2611 } 2612 2613 if (xdpf && 2614 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2615 xdp_return_frame(xdpf); 2616 tx_q->xdpf[entry] = NULL; 2617 } 2618 2619 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2620 tx_q->xsk_frames_done++; 2621 2622 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2623 if (likely(skb)) { 2624 pkts_compl++; 2625 bytes_compl += skb->len; 2626 dev_consume_skb_any(skb); 2627 tx_q->tx_skbuff[entry] = NULL; 2628 } 2629 } 2630 2631 stmmac_release_tx_desc(priv, p, priv->mode); 2632 2633 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2634 } 2635 tx_q->dirty_tx = entry; 2636 2637 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2638 pkts_compl, bytes_compl); 2639 2640 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2641 queue))) && 2642 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2643 2644 netif_dbg(priv, tx_done, priv->dev, 2645 "%s: restart transmit\n", __func__); 2646 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2647 } 2648 2649 if (tx_q->xsk_pool) { 2650 bool work_done; 2651 2652 if (tx_q->xsk_frames_done) 2653 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2654 2655 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2656 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2657 2658 /* For XSK TX, we try to send as many as possible. 2659 * If XSK work done (XSK TX desc empty and budget still 2660 * available), return "budget - 1" to reenable TX IRQ. 2661 * Else, return "budget" to make NAPI continue polling. 2662 */ 2663 work_done = stmmac_xdp_xmit_zc(priv, queue, 2664 STMMAC_XSK_TX_BUDGET_MAX); 2665 if (work_done) 2666 xmits = budget - 1; 2667 else 2668 xmits = budget; 2669 } 2670 2671 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2672 priv->eee_sw_timer_en) { 2673 if (stmmac_enable_eee_mode(priv)) 2674 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2675 } 2676 2677 /* We still have pending packets, let's call for a new scheduling */ 2678 if (tx_q->dirty_tx != tx_q->cur_tx) 2679 hrtimer_start(&tx_q->txtimer, 2680 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2681 HRTIMER_MODE_REL); 2682 2683 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2684 2685 /* Combine decisions from TX clean and XSK TX */ 2686 return max(count, xmits); 2687 } 2688 2689 /** 2690 * stmmac_tx_err - to manage the tx error 2691 * @priv: driver private structure 2692 * @chan: channel index 2693 * Description: it cleans the descriptors and restarts the transmission 2694 * in case of transmission errors. 2695 */ 2696 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2697 { 2698 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2699 2700 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2701 2702 stmmac_stop_tx_dma(priv, chan); 2703 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2704 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2705 stmmac_reset_tx_queue(priv, chan); 2706 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2707 tx_q->dma_tx_phy, chan); 2708 stmmac_start_tx_dma(priv, chan); 2709 2710 priv->dev->stats.tx_errors++; 2711 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2712 } 2713 2714 /** 2715 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2716 * @priv: driver private structure 2717 * @txmode: TX operating mode 2718 * @rxmode: RX operating mode 2719 * @chan: channel index 2720 * Description: it is used for configuring of the DMA operation mode in 2721 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2722 * mode. 2723 */ 2724 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2725 u32 rxmode, u32 chan) 2726 { 2727 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2728 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2729 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2730 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2731 int rxfifosz = priv->plat->rx_fifo_size; 2732 int txfifosz = priv->plat->tx_fifo_size; 2733 2734 if (rxfifosz == 0) 2735 rxfifosz = priv->dma_cap.rx_fifo_size; 2736 if (txfifosz == 0) 2737 txfifosz = priv->dma_cap.tx_fifo_size; 2738 2739 /* Adjust for real per queue fifo size */ 2740 rxfifosz /= rx_channels_count; 2741 txfifosz /= tx_channels_count; 2742 2743 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2744 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2745 } 2746 2747 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2748 { 2749 int ret; 2750 2751 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2752 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2753 if (ret && (ret != -EINVAL)) { 2754 stmmac_global_err(priv); 2755 return true; 2756 } 2757 2758 return false; 2759 } 2760 2761 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2762 { 2763 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2764 &priv->xstats, chan, dir); 2765 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2766 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2767 struct stmmac_channel *ch = &priv->channel[chan]; 2768 struct napi_struct *rx_napi; 2769 struct napi_struct *tx_napi; 2770 unsigned long flags; 2771 2772 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2773 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2774 2775 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2776 if (napi_schedule_prep(rx_napi)) { 2777 spin_lock_irqsave(&ch->lock, flags); 2778 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2779 spin_unlock_irqrestore(&ch->lock, flags); 2780 __napi_schedule(rx_napi); 2781 } 2782 } 2783 2784 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2785 if (napi_schedule_prep(tx_napi)) { 2786 spin_lock_irqsave(&ch->lock, flags); 2787 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2788 spin_unlock_irqrestore(&ch->lock, flags); 2789 __napi_schedule(tx_napi); 2790 } 2791 } 2792 2793 return status; 2794 } 2795 2796 /** 2797 * stmmac_dma_interrupt - DMA ISR 2798 * @priv: driver private structure 2799 * Description: this is the DMA ISR. It is called by the main ISR. 2800 * It calls the dwmac dma routine and schedule poll method in case of some 2801 * work can be done. 2802 */ 2803 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2804 { 2805 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2806 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2807 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2808 tx_channel_count : rx_channel_count; 2809 u32 chan; 2810 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2811 2812 /* Make sure we never check beyond our status buffer. */ 2813 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2814 channels_to_check = ARRAY_SIZE(status); 2815 2816 for (chan = 0; chan < channels_to_check; chan++) 2817 status[chan] = stmmac_napi_check(priv, chan, 2818 DMA_DIR_RXTX); 2819 2820 for (chan = 0; chan < tx_channel_count; chan++) { 2821 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2822 /* Try to bump up the dma threshold on this failure */ 2823 stmmac_bump_dma_threshold(priv, chan); 2824 } else if (unlikely(status[chan] == tx_hard_error)) { 2825 stmmac_tx_err(priv, chan); 2826 } 2827 } 2828 } 2829 2830 /** 2831 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2832 * @priv: driver private structure 2833 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2834 */ 2835 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2836 { 2837 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2838 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2839 2840 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2841 2842 if (priv->dma_cap.rmon) { 2843 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2844 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2845 } else 2846 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2847 } 2848 2849 /** 2850 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2851 * @priv: driver private structure 2852 * Description: 2853 * new GMAC chip generations have a new register to indicate the 2854 * presence of the optional feature/functions. 2855 * This can be also used to override the value passed through the 2856 * platform and necessary for old MAC10/100 and GMAC chips. 2857 */ 2858 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2859 { 2860 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2861 } 2862 2863 /** 2864 * stmmac_check_ether_addr - check if the MAC addr is valid 2865 * @priv: driver private structure 2866 * Description: 2867 * it is to verify if the MAC address is valid, in case of failures it 2868 * generates a random MAC address 2869 */ 2870 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2871 { 2872 u8 addr[ETH_ALEN]; 2873 2874 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2875 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2876 if (is_valid_ether_addr(addr)) 2877 eth_hw_addr_set(priv->dev, addr); 2878 else 2879 eth_hw_addr_random(priv->dev); 2880 dev_info(priv->device, "device MAC address %pM\n", 2881 priv->dev->dev_addr); 2882 } 2883 } 2884 2885 /** 2886 * stmmac_init_dma_engine - DMA init. 2887 * @priv: driver private structure 2888 * Description: 2889 * It inits the DMA invoking the specific MAC/GMAC callback. 2890 * Some DMA parameters can be passed from the platform; 2891 * in case of these are not passed a default is kept for the MAC or GMAC. 2892 */ 2893 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2894 { 2895 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2896 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2897 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2898 struct stmmac_rx_queue *rx_q; 2899 struct stmmac_tx_queue *tx_q; 2900 u32 chan = 0; 2901 int atds = 0; 2902 int ret = 0; 2903 2904 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2905 dev_err(priv->device, "Invalid DMA configuration\n"); 2906 return -EINVAL; 2907 } 2908 2909 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2910 atds = 1; 2911 2912 ret = stmmac_reset(priv, priv->ioaddr); 2913 if (ret) { 2914 dev_err(priv->device, "Failed to reset the dma\n"); 2915 return ret; 2916 } 2917 2918 /* DMA Configuration */ 2919 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2920 2921 if (priv->plat->axi) 2922 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2923 2924 /* DMA CSR Channel configuration */ 2925 for (chan = 0; chan < dma_csr_ch; chan++) { 2926 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2927 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2928 } 2929 2930 /* DMA RX Channel Configuration */ 2931 for (chan = 0; chan < rx_channels_count; chan++) { 2932 rx_q = &priv->dma_conf.rx_queue[chan]; 2933 2934 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2935 rx_q->dma_rx_phy, chan); 2936 2937 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2938 (rx_q->buf_alloc_num * 2939 sizeof(struct dma_desc)); 2940 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2941 rx_q->rx_tail_addr, chan); 2942 } 2943 2944 /* DMA TX Channel Configuration */ 2945 for (chan = 0; chan < tx_channels_count; chan++) { 2946 tx_q = &priv->dma_conf.tx_queue[chan]; 2947 2948 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2949 tx_q->dma_tx_phy, chan); 2950 2951 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2952 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2953 tx_q->tx_tail_addr, chan); 2954 } 2955 2956 return ret; 2957 } 2958 2959 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2960 { 2961 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2962 2963 hrtimer_start(&tx_q->txtimer, 2964 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2965 HRTIMER_MODE_REL); 2966 } 2967 2968 /** 2969 * stmmac_tx_timer - mitigation sw timer for tx. 2970 * @t: data pointer 2971 * Description: 2972 * This is the timer handler to directly invoke the stmmac_tx_clean. 2973 */ 2974 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2975 { 2976 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2977 struct stmmac_priv *priv = tx_q->priv_data; 2978 struct stmmac_channel *ch; 2979 struct napi_struct *napi; 2980 2981 ch = &priv->channel[tx_q->queue_index]; 2982 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2983 2984 if (likely(napi_schedule_prep(napi))) { 2985 unsigned long flags; 2986 2987 spin_lock_irqsave(&ch->lock, flags); 2988 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2989 spin_unlock_irqrestore(&ch->lock, flags); 2990 __napi_schedule(napi); 2991 } 2992 2993 return HRTIMER_NORESTART; 2994 } 2995 2996 /** 2997 * stmmac_init_coalesce - init mitigation options. 2998 * @priv: driver private structure 2999 * Description: 3000 * This inits the coalesce parameters: i.e. timer rate, 3001 * timer handler and default threshold used for enabling the 3002 * interrupt on completion bit. 3003 */ 3004 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3005 { 3006 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3007 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3008 u32 chan; 3009 3010 for (chan = 0; chan < tx_channel_count; chan++) { 3011 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3012 3013 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3014 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3015 3016 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3017 tx_q->txtimer.function = stmmac_tx_timer; 3018 } 3019 3020 for (chan = 0; chan < rx_channel_count; chan++) 3021 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3022 } 3023 3024 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3025 { 3026 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3027 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3028 u32 chan; 3029 3030 /* set TX ring length */ 3031 for (chan = 0; chan < tx_channels_count; chan++) 3032 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3033 (priv->dma_conf.dma_tx_size - 1), chan); 3034 3035 /* set RX ring length */ 3036 for (chan = 0; chan < rx_channels_count; chan++) 3037 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3038 (priv->dma_conf.dma_rx_size - 1), chan); 3039 } 3040 3041 /** 3042 * stmmac_set_tx_queue_weight - Set TX queue weight 3043 * @priv: driver private structure 3044 * Description: It is used for setting TX queues weight 3045 */ 3046 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3047 { 3048 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3049 u32 weight; 3050 u32 queue; 3051 3052 for (queue = 0; queue < tx_queues_count; queue++) { 3053 weight = priv->plat->tx_queues_cfg[queue].weight; 3054 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3055 } 3056 } 3057 3058 /** 3059 * stmmac_configure_cbs - Configure CBS in TX queue 3060 * @priv: driver private structure 3061 * Description: It is used for configuring CBS in AVB TX queues 3062 */ 3063 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3064 { 3065 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3066 u32 mode_to_use; 3067 u32 queue; 3068 3069 /* queue 0 is reserved for legacy traffic */ 3070 for (queue = 1; queue < tx_queues_count; queue++) { 3071 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3072 if (mode_to_use == MTL_QUEUE_DCB) 3073 continue; 3074 3075 stmmac_config_cbs(priv, priv->hw, 3076 priv->plat->tx_queues_cfg[queue].send_slope, 3077 priv->plat->tx_queues_cfg[queue].idle_slope, 3078 priv->plat->tx_queues_cfg[queue].high_credit, 3079 priv->plat->tx_queues_cfg[queue].low_credit, 3080 queue); 3081 } 3082 } 3083 3084 /** 3085 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3086 * @priv: driver private structure 3087 * Description: It is used for mapping RX queues to RX dma channels 3088 */ 3089 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3090 { 3091 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3092 u32 queue; 3093 u32 chan; 3094 3095 for (queue = 0; queue < rx_queues_count; queue++) { 3096 chan = priv->plat->rx_queues_cfg[queue].chan; 3097 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3098 } 3099 } 3100 3101 /** 3102 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3103 * @priv: driver private structure 3104 * Description: It is used for configuring the RX Queue Priority 3105 */ 3106 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3107 { 3108 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3109 u32 queue; 3110 u32 prio; 3111 3112 for (queue = 0; queue < rx_queues_count; queue++) { 3113 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3114 continue; 3115 3116 prio = priv->plat->rx_queues_cfg[queue].prio; 3117 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3118 } 3119 } 3120 3121 /** 3122 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3123 * @priv: driver private structure 3124 * Description: It is used for configuring the TX Queue Priority 3125 */ 3126 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3127 { 3128 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3129 u32 queue; 3130 u32 prio; 3131 3132 for (queue = 0; queue < tx_queues_count; queue++) { 3133 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3134 continue; 3135 3136 prio = priv->plat->tx_queues_cfg[queue].prio; 3137 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3138 } 3139 } 3140 3141 /** 3142 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3143 * @priv: driver private structure 3144 * Description: It is used for configuring the RX queue routing 3145 */ 3146 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3147 { 3148 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3149 u32 queue; 3150 u8 packet; 3151 3152 for (queue = 0; queue < rx_queues_count; queue++) { 3153 /* no specific packet type routing specified for the queue */ 3154 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3155 continue; 3156 3157 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3158 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3159 } 3160 } 3161 3162 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3163 { 3164 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3165 priv->rss.enable = false; 3166 return; 3167 } 3168 3169 if (priv->dev->features & NETIF_F_RXHASH) 3170 priv->rss.enable = true; 3171 else 3172 priv->rss.enable = false; 3173 3174 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3175 priv->plat->rx_queues_to_use); 3176 } 3177 3178 /** 3179 * stmmac_mtl_configuration - Configure MTL 3180 * @priv: driver private structure 3181 * Description: It is used for configurring MTL 3182 */ 3183 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3184 { 3185 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3186 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3187 3188 if (tx_queues_count > 1) 3189 stmmac_set_tx_queue_weight(priv); 3190 3191 /* Configure MTL RX algorithms */ 3192 if (rx_queues_count > 1) 3193 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3194 priv->plat->rx_sched_algorithm); 3195 3196 /* Configure MTL TX algorithms */ 3197 if (tx_queues_count > 1) 3198 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3199 priv->plat->tx_sched_algorithm); 3200 3201 /* Configure CBS in AVB TX queues */ 3202 if (tx_queues_count > 1) 3203 stmmac_configure_cbs(priv); 3204 3205 /* Map RX MTL to DMA channels */ 3206 stmmac_rx_queue_dma_chan_map(priv); 3207 3208 /* Enable MAC RX Queues */ 3209 stmmac_mac_enable_rx_queues(priv); 3210 3211 /* Set RX priorities */ 3212 if (rx_queues_count > 1) 3213 stmmac_mac_config_rx_queues_prio(priv); 3214 3215 /* Set TX priorities */ 3216 if (tx_queues_count > 1) 3217 stmmac_mac_config_tx_queues_prio(priv); 3218 3219 /* Set RX routing */ 3220 if (rx_queues_count > 1) 3221 stmmac_mac_config_rx_queues_routing(priv); 3222 3223 /* Receive Side Scaling */ 3224 if (rx_queues_count > 1) 3225 stmmac_mac_config_rss(priv); 3226 } 3227 3228 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3229 { 3230 if (priv->dma_cap.asp) { 3231 netdev_info(priv->dev, "Enabling Safety Features\n"); 3232 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3233 priv->plat->safety_feat_cfg); 3234 } else { 3235 netdev_info(priv->dev, "No Safety Features support found\n"); 3236 } 3237 } 3238 3239 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3240 { 3241 char *name; 3242 3243 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3244 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3245 3246 name = priv->wq_name; 3247 sprintf(name, "%s-fpe", priv->dev->name); 3248 3249 priv->fpe_wq = create_singlethread_workqueue(name); 3250 if (!priv->fpe_wq) { 3251 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3252 3253 return -ENOMEM; 3254 } 3255 netdev_info(priv->dev, "FPE workqueue start"); 3256 3257 return 0; 3258 } 3259 3260 /** 3261 * stmmac_hw_setup - setup mac in a usable state. 3262 * @dev : pointer to the device structure. 3263 * @ptp_register: register PTP if set 3264 * Description: 3265 * this is the main function to setup the HW in a usable state because the 3266 * dma engine is reset, the core registers are configured (e.g. AXI, 3267 * Checksum features, timers). The DMA is ready to start receiving and 3268 * transmitting. 3269 * Return value: 3270 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3271 * file on failure. 3272 */ 3273 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3274 { 3275 struct stmmac_priv *priv = netdev_priv(dev); 3276 u32 rx_cnt = priv->plat->rx_queues_to_use; 3277 u32 tx_cnt = priv->plat->tx_queues_to_use; 3278 bool sph_en; 3279 u32 chan; 3280 int ret; 3281 3282 /* DMA initialization and SW reset */ 3283 ret = stmmac_init_dma_engine(priv); 3284 if (ret < 0) { 3285 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3286 __func__); 3287 return ret; 3288 } 3289 3290 /* Copy the MAC addr into the HW */ 3291 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3292 3293 /* PS and related bits will be programmed according to the speed */ 3294 if (priv->hw->pcs) { 3295 int speed = priv->plat->mac_port_sel_speed; 3296 3297 if ((speed == SPEED_10) || (speed == SPEED_100) || 3298 (speed == SPEED_1000)) { 3299 priv->hw->ps = speed; 3300 } else { 3301 dev_warn(priv->device, "invalid port speed\n"); 3302 priv->hw->ps = 0; 3303 } 3304 } 3305 3306 /* Initialize the MAC Core */ 3307 stmmac_core_init(priv, priv->hw, dev); 3308 3309 /* Initialize MTL*/ 3310 stmmac_mtl_configuration(priv); 3311 3312 /* Initialize Safety Features */ 3313 stmmac_safety_feat_configuration(priv); 3314 3315 ret = stmmac_rx_ipc(priv, priv->hw); 3316 if (!ret) { 3317 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3318 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3319 priv->hw->rx_csum = 0; 3320 } 3321 3322 /* Enable the MAC Rx/Tx */ 3323 stmmac_mac_set(priv, priv->ioaddr, true); 3324 3325 /* Set the HW DMA mode and the COE */ 3326 stmmac_dma_operation_mode(priv); 3327 3328 stmmac_mmc_setup(priv); 3329 3330 if (ptp_register) { 3331 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3332 if (ret < 0) 3333 netdev_warn(priv->dev, 3334 "failed to enable PTP reference clock: %pe\n", 3335 ERR_PTR(ret)); 3336 } 3337 3338 ret = stmmac_init_ptp(priv); 3339 if (ret == -EOPNOTSUPP) 3340 netdev_info(priv->dev, "PTP not supported by HW\n"); 3341 else if (ret) 3342 netdev_warn(priv->dev, "PTP init failed\n"); 3343 else if (ptp_register) 3344 stmmac_ptp_register(priv); 3345 3346 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3347 3348 /* Convert the timer from msec to usec */ 3349 if (!priv->tx_lpi_timer) 3350 priv->tx_lpi_timer = eee_timer * 1000; 3351 3352 if (priv->use_riwt) { 3353 u32 queue; 3354 3355 for (queue = 0; queue < rx_cnt; queue++) { 3356 if (!priv->rx_riwt[queue]) 3357 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3358 3359 stmmac_rx_watchdog(priv, priv->ioaddr, 3360 priv->rx_riwt[queue], queue); 3361 } 3362 } 3363 3364 if (priv->hw->pcs) 3365 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3366 3367 /* set TX and RX rings length */ 3368 stmmac_set_rings_length(priv); 3369 3370 /* Enable TSO */ 3371 if (priv->tso) { 3372 for (chan = 0; chan < tx_cnt; chan++) { 3373 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3374 3375 /* TSO and TBS cannot co-exist */ 3376 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3377 continue; 3378 3379 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3380 } 3381 } 3382 3383 /* Enable Split Header */ 3384 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3385 for (chan = 0; chan < rx_cnt; chan++) 3386 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3387 3388 3389 /* VLAN Tag Insertion */ 3390 if (priv->dma_cap.vlins) 3391 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3392 3393 /* TBS */ 3394 for (chan = 0; chan < tx_cnt; chan++) { 3395 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3396 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3397 3398 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3399 } 3400 3401 /* Configure real RX and TX queues */ 3402 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3403 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3404 3405 /* Start the ball rolling... */ 3406 stmmac_start_all_dma(priv); 3407 3408 if (priv->dma_cap.fpesel) { 3409 stmmac_fpe_start_wq(priv); 3410 3411 if (priv->plat->fpe_cfg->enable) 3412 stmmac_fpe_handshake(priv, true); 3413 } 3414 3415 return 0; 3416 } 3417 3418 static void stmmac_hw_teardown(struct net_device *dev) 3419 { 3420 struct stmmac_priv *priv = netdev_priv(dev); 3421 3422 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3423 } 3424 3425 static void stmmac_free_irq(struct net_device *dev, 3426 enum request_irq_err irq_err, int irq_idx) 3427 { 3428 struct stmmac_priv *priv = netdev_priv(dev); 3429 int j; 3430 3431 switch (irq_err) { 3432 case REQ_IRQ_ERR_ALL: 3433 irq_idx = priv->plat->tx_queues_to_use; 3434 fallthrough; 3435 case REQ_IRQ_ERR_TX: 3436 for (j = irq_idx - 1; j >= 0; j--) { 3437 if (priv->tx_irq[j] > 0) { 3438 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3439 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3440 } 3441 } 3442 irq_idx = priv->plat->rx_queues_to_use; 3443 fallthrough; 3444 case REQ_IRQ_ERR_RX: 3445 for (j = irq_idx - 1; j >= 0; j--) { 3446 if (priv->rx_irq[j] > 0) { 3447 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3448 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3449 } 3450 } 3451 3452 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3453 free_irq(priv->sfty_ue_irq, dev); 3454 fallthrough; 3455 case REQ_IRQ_ERR_SFTY_UE: 3456 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3457 free_irq(priv->sfty_ce_irq, dev); 3458 fallthrough; 3459 case REQ_IRQ_ERR_SFTY_CE: 3460 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3461 free_irq(priv->lpi_irq, dev); 3462 fallthrough; 3463 case REQ_IRQ_ERR_LPI: 3464 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3465 free_irq(priv->wol_irq, dev); 3466 fallthrough; 3467 case REQ_IRQ_ERR_WOL: 3468 free_irq(dev->irq, dev); 3469 fallthrough; 3470 case REQ_IRQ_ERR_MAC: 3471 case REQ_IRQ_ERR_NO: 3472 /* If MAC IRQ request error, no more IRQ to free */ 3473 break; 3474 } 3475 } 3476 3477 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3478 { 3479 struct stmmac_priv *priv = netdev_priv(dev); 3480 enum request_irq_err irq_err; 3481 cpumask_t cpu_mask; 3482 int irq_idx = 0; 3483 char *int_name; 3484 int ret; 3485 int i; 3486 3487 /* For common interrupt */ 3488 int_name = priv->int_name_mac; 3489 sprintf(int_name, "%s:%s", dev->name, "mac"); 3490 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3491 0, int_name, dev); 3492 if (unlikely(ret < 0)) { 3493 netdev_err(priv->dev, 3494 "%s: alloc mac MSI %d (error: %d)\n", 3495 __func__, dev->irq, ret); 3496 irq_err = REQ_IRQ_ERR_MAC; 3497 goto irq_error; 3498 } 3499 3500 /* Request the Wake IRQ in case of another line 3501 * is used for WoL 3502 */ 3503 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3504 int_name = priv->int_name_wol; 3505 sprintf(int_name, "%s:%s", dev->name, "wol"); 3506 ret = request_irq(priv->wol_irq, 3507 stmmac_mac_interrupt, 3508 0, int_name, dev); 3509 if (unlikely(ret < 0)) { 3510 netdev_err(priv->dev, 3511 "%s: alloc wol MSI %d (error: %d)\n", 3512 __func__, priv->wol_irq, ret); 3513 irq_err = REQ_IRQ_ERR_WOL; 3514 goto irq_error; 3515 } 3516 } 3517 3518 /* Request the LPI IRQ in case of another line 3519 * is used for LPI 3520 */ 3521 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3522 int_name = priv->int_name_lpi; 3523 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3524 ret = request_irq(priv->lpi_irq, 3525 stmmac_mac_interrupt, 3526 0, int_name, dev); 3527 if (unlikely(ret < 0)) { 3528 netdev_err(priv->dev, 3529 "%s: alloc lpi MSI %d (error: %d)\n", 3530 __func__, priv->lpi_irq, ret); 3531 irq_err = REQ_IRQ_ERR_LPI; 3532 goto irq_error; 3533 } 3534 } 3535 3536 /* Request the Safety Feature Correctible Error line in 3537 * case of another line is used 3538 */ 3539 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3540 int_name = priv->int_name_sfty_ce; 3541 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3542 ret = request_irq(priv->sfty_ce_irq, 3543 stmmac_safety_interrupt, 3544 0, int_name, dev); 3545 if (unlikely(ret < 0)) { 3546 netdev_err(priv->dev, 3547 "%s: alloc sfty ce MSI %d (error: %d)\n", 3548 __func__, priv->sfty_ce_irq, ret); 3549 irq_err = REQ_IRQ_ERR_SFTY_CE; 3550 goto irq_error; 3551 } 3552 } 3553 3554 /* Request the Safety Feature Uncorrectible Error line in 3555 * case of another line is used 3556 */ 3557 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3558 int_name = priv->int_name_sfty_ue; 3559 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3560 ret = request_irq(priv->sfty_ue_irq, 3561 stmmac_safety_interrupt, 3562 0, int_name, dev); 3563 if (unlikely(ret < 0)) { 3564 netdev_err(priv->dev, 3565 "%s: alloc sfty ue MSI %d (error: %d)\n", 3566 __func__, priv->sfty_ue_irq, ret); 3567 irq_err = REQ_IRQ_ERR_SFTY_UE; 3568 goto irq_error; 3569 } 3570 } 3571 3572 /* Request Rx MSI irq */ 3573 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3574 if (i >= MTL_MAX_RX_QUEUES) 3575 break; 3576 if (priv->rx_irq[i] == 0) 3577 continue; 3578 3579 int_name = priv->int_name_rx_irq[i]; 3580 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3581 ret = request_irq(priv->rx_irq[i], 3582 stmmac_msi_intr_rx, 3583 0, int_name, &priv->dma_conf.rx_queue[i]); 3584 if (unlikely(ret < 0)) { 3585 netdev_err(priv->dev, 3586 "%s: alloc rx-%d MSI %d (error: %d)\n", 3587 __func__, i, priv->rx_irq[i], ret); 3588 irq_err = REQ_IRQ_ERR_RX; 3589 irq_idx = i; 3590 goto irq_error; 3591 } 3592 cpumask_clear(&cpu_mask); 3593 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3594 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3595 } 3596 3597 /* Request Tx MSI irq */ 3598 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3599 if (i >= MTL_MAX_TX_QUEUES) 3600 break; 3601 if (priv->tx_irq[i] == 0) 3602 continue; 3603 3604 int_name = priv->int_name_tx_irq[i]; 3605 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3606 ret = request_irq(priv->tx_irq[i], 3607 stmmac_msi_intr_tx, 3608 0, int_name, &priv->dma_conf.tx_queue[i]); 3609 if (unlikely(ret < 0)) { 3610 netdev_err(priv->dev, 3611 "%s: alloc tx-%d MSI %d (error: %d)\n", 3612 __func__, i, priv->tx_irq[i], ret); 3613 irq_err = REQ_IRQ_ERR_TX; 3614 irq_idx = i; 3615 goto irq_error; 3616 } 3617 cpumask_clear(&cpu_mask); 3618 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3619 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3620 } 3621 3622 return 0; 3623 3624 irq_error: 3625 stmmac_free_irq(dev, irq_err, irq_idx); 3626 return ret; 3627 } 3628 3629 static int stmmac_request_irq_single(struct net_device *dev) 3630 { 3631 struct stmmac_priv *priv = netdev_priv(dev); 3632 enum request_irq_err irq_err; 3633 int ret; 3634 3635 ret = request_irq(dev->irq, stmmac_interrupt, 3636 IRQF_SHARED, dev->name, dev); 3637 if (unlikely(ret < 0)) { 3638 netdev_err(priv->dev, 3639 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3640 __func__, dev->irq, ret); 3641 irq_err = REQ_IRQ_ERR_MAC; 3642 goto irq_error; 3643 } 3644 3645 /* Request the Wake IRQ in case of another line 3646 * is used for WoL 3647 */ 3648 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3649 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3650 IRQF_SHARED, dev->name, dev); 3651 if (unlikely(ret < 0)) { 3652 netdev_err(priv->dev, 3653 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3654 __func__, priv->wol_irq, ret); 3655 irq_err = REQ_IRQ_ERR_WOL; 3656 goto irq_error; 3657 } 3658 } 3659 3660 /* Request the IRQ lines */ 3661 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3662 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3663 IRQF_SHARED, dev->name, dev); 3664 if (unlikely(ret < 0)) { 3665 netdev_err(priv->dev, 3666 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3667 __func__, priv->lpi_irq, ret); 3668 irq_err = REQ_IRQ_ERR_LPI; 3669 goto irq_error; 3670 } 3671 } 3672 3673 return 0; 3674 3675 irq_error: 3676 stmmac_free_irq(dev, irq_err, 0); 3677 return ret; 3678 } 3679 3680 static int stmmac_request_irq(struct net_device *dev) 3681 { 3682 struct stmmac_priv *priv = netdev_priv(dev); 3683 int ret; 3684 3685 /* Request the IRQ lines */ 3686 if (priv->plat->multi_msi_en) 3687 ret = stmmac_request_irq_multi_msi(dev); 3688 else 3689 ret = stmmac_request_irq_single(dev); 3690 3691 return ret; 3692 } 3693 3694 /** 3695 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3696 * @priv: driver private structure 3697 * @mtu: MTU to setup the dma queue and buf with 3698 * Description: Allocate and generate a dma_conf based on the provided MTU. 3699 * Allocate the Tx/Rx DMA queue and init them. 3700 * Return value: 3701 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3702 */ 3703 static struct stmmac_dma_conf * 3704 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3705 { 3706 struct stmmac_dma_conf *dma_conf; 3707 int chan, bfsize, ret; 3708 3709 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3710 if (!dma_conf) { 3711 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3712 __func__); 3713 return ERR_PTR(-ENOMEM); 3714 } 3715 3716 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3717 if (bfsize < 0) 3718 bfsize = 0; 3719 3720 if (bfsize < BUF_SIZE_16KiB) 3721 bfsize = stmmac_set_bfsize(mtu, 0); 3722 3723 dma_conf->dma_buf_sz = bfsize; 3724 /* Chose the tx/rx size from the already defined one in the 3725 * priv struct. (if defined) 3726 */ 3727 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3728 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3729 3730 if (!dma_conf->dma_tx_size) 3731 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3732 if (!dma_conf->dma_rx_size) 3733 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3734 3735 /* Earlier check for TBS */ 3736 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3737 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3738 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3739 3740 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3741 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3742 } 3743 3744 ret = alloc_dma_desc_resources(priv, dma_conf); 3745 if (ret < 0) { 3746 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3747 __func__); 3748 goto alloc_error; 3749 } 3750 3751 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3752 if (ret < 0) { 3753 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3754 __func__); 3755 goto init_error; 3756 } 3757 3758 return dma_conf; 3759 3760 init_error: 3761 free_dma_desc_resources(priv, dma_conf); 3762 alloc_error: 3763 kfree(dma_conf); 3764 return ERR_PTR(ret); 3765 } 3766 3767 /** 3768 * __stmmac_open - open entry point of the driver 3769 * @dev : pointer to the device structure. 3770 * @dma_conf : structure to take the dma data 3771 * Description: 3772 * This function is the open entry point of the driver. 3773 * Return value: 3774 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3775 * file on failure. 3776 */ 3777 static int __stmmac_open(struct net_device *dev, 3778 struct stmmac_dma_conf *dma_conf) 3779 { 3780 struct stmmac_priv *priv = netdev_priv(dev); 3781 int mode = priv->plat->phy_interface; 3782 u32 chan; 3783 int ret; 3784 3785 ret = pm_runtime_resume_and_get(priv->device); 3786 if (ret < 0) 3787 return ret; 3788 3789 if (priv->hw->pcs != STMMAC_PCS_TBI && 3790 priv->hw->pcs != STMMAC_PCS_RTBI && 3791 (!priv->hw->xpcs || 3792 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3793 ret = stmmac_init_phy(dev); 3794 if (ret) { 3795 netdev_err(priv->dev, 3796 "%s: Cannot attach to PHY (error: %d)\n", 3797 __func__, ret); 3798 goto init_phy_error; 3799 } 3800 } 3801 3802 /* Extra statistics */ 3803 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3804 priv->xstats.threshold = tc; 3805 3806 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3807 3808 buf_sz = dma_conf->dma_buf_sz; 3809 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3810 3811 stmmac_reset_queues_param(priv); 3812 3813 if (priv->plat->serdes_powerup) { 3814 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3815 if (ret < 0) { 3816 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3817 __func__); 3818 goto init_error; 3819 } 3820 } 3821 3822 ret = stmmac_hw_setup(dev, true); 3823 if (ret < 0) { 3824 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3825 goto init_error; 3826 } 3827 3828 stmmac_init_coalesce(priv); 3829 3830 phylink_start(priv->phylink); 3831 /* We may have called phylink_speed_down before */ 3832 phylink_speed_up(priv->phylink); 3833 3834 ret = stmmac_request_irq(dev); 3835 if (ret) 3836 goto irq_error; 3837 3838 stmmac_enable_all_queues(priv); 3839 netif_tx_start_all_queues(priv->dev); 3840 stmmac_enable_all_dma_irq(priv); 3841 3842 return 0; 3843 3844 irq_error: 3845 phylink_stop(priv->phylink); 3846 3847 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3848 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3849 3850 stmmac_hw_teardown(dev); 3851 init_error: 3852 free_dma_desc_resources(priv, &priv->dma_conf); 3853 phylink_disconnect_phy(priv->phylink); 3854 init_phy_error: 3855 pm_runtime_put(priv->device); 3856 return ret; 3857 } 3858 3859 static int stmmac_open(struct net_device *dev) 3860 { 3861 struct stmmac_priv *priv = netdev_priv(dev); 3862 struct stmmac_dma_conf *dma_conf; 3863 int ret; 3864 3865 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3866 if (IS_ERR(dma_conf)) 3867 return PTR_ERR(dma_conf); 3868 3869 ret = __stmmac_open(dev, dma_conf); 3870 kfree(dma_conf); 3871 return ret; 3872 } 3873 3874 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3875 { 3876 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3877 3878 if (priv->fpe_wq) 3879 destroy_workqueue(priv->fpe_wq); 3880 3881 netdev_info(priv->dev, "FPE workqueue stop"); 3882 } 3883 3884 /** 3885 * stmmac_release - close entry point of the driver 3886 * @dev : device pointer. 3887 * Description: 3888 * This is the stop entry point of the driver. 3889 */ 3890 static int stmmac_release(struct net_device *dev) 3891 { 3892 struct stmmac_priv *priv = netdev_priv(dev); 3893 u32 chan; 3894 3895 if (device_may_wakeup(priv->device)) 3896 phylink_speed_down(priv->phylink, false); 3897 /* Stop and disconnect the PHY */ 3898 phylink_stop(priv->phylink); 3899 phylink_disconnect_phy(priv->phylink); 3900 3901 stmmac_disable_all_queues(priv); 3902 3903 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3904 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3905 3906 netif_tx_disable(dev); 3907 3908 /* Free the IRQ lines */ 3909 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3910 3911 if (priv->eee_enabled) { 3912 priv->tx_path_in_lpi_mode = false; 3913 del_timer_sync(&priv->eee_ctrl_timer); 3914 } 3915 3916 /* Stop TX/RX DMA and clear the descriptors */ 3917 stmmac_stop_all_dma(priv); 3918 3919 /* Release and free the Rx/Tx resources */ 3920 free_dma_desc_resources(priv, &priv->dma_conf); 3921 3922 /* Disable the MAC Rx/Tx */ 3923 stmmac_mac_set(priv, priv->ioaddr, false); 3924 3925 /* Powerdown Serdes if there is */ 3926 if (priv->plat->serdes_powerdown) 3927 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3928 3929 netif_carrier_off(dev); 3930 3931 stmmac_release_ptp(priv); 3932 3933 pm_runtime_put(priv->device); 3934 3935 if (priv->dma_cap.fpesel) 3936 stmmac_fpe_stop_wq(priv); 3937 3938 return 0; 3939 } 3940 3941 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3942 struct stmmac_tx_queue *tx_q) 3943 { 3944 u16 tag = 0x0, inner_tag = 0x0; 3945 u32 inner_type = 0x0; 3946 struct dma_desc *p; 3947 3948 if (!priv->dma_cap.vlins) 3949 return false; 3950 if (!skb_vlan_tag_present(skb)) 3951 return false; 3952 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3953 inner_tag = skb_vlan_tag_get(skb); 3954 inner_type = STMMAC_VLAN_INSERT; 3955 } 3956 3957 tag = skb_vlan_tag_get(skb); 3958 3959 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3960 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3961 else 3962 p = &tx_q->dma_tx[tx_q->cur_tx]; 3963 3964 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3965 return false; 3966 3967 stmmac_set_tx_owner(priv, p); 3968 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3969 return true; 3970 } 3971 3972 /** 3973 * stmmac_tso_allocator - close entry point of the driver 3974 * @priv: driver private structure 3975 * @des: buffer start address 3976 * @total_len: total length to fill in descriptors 3977 * @last_segment: condition for the last descriptor 3978 * @queue: TX queue index 3979 * Description: 3980 * This function fills descriptor and request new descriptors according to 3981 * buffer length to fill 3982 */ 3983 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3984 int total_len, bool last_segment, u32 queue) 3985 { 3986 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3987 struct dma_desc *desc; 3988 u32 buff_size; 3989 int tmp_len; 3990 3991 tmp_len = total_len; 3992 3993 while (tmp_len > 0) { 3994 dma_addr_t curr_addr; 3995 3996 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3997 priv->dma_conf.dma_tx_size); 3998 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3999 4000 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4001 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4002 else 4003 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4004 4005 curr_addr = des + (total_len - tmp_len); 4006 if (priv->dma_cap.addr64 <= 32) 4007 desc->des0 = cpu_to_le32(curr_addr); 4008 else 4009 stmmac_set_desc_addr(priv, desc, curr_addr); 4010 4011 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4012 TSO_MAX_BUFF_SIZE : tmp_len; 4013 4014 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4015 0, 1, 4016 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4017 0, 0); 4018 4019 tmp_len -= TSO_MAX_BUFF_SIZE; 4020 } 4021 } 4022 4023 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4024 { 4025 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4026 int desc_size; 4027 4028 if (likely(priv->extend_desc)) 4029 desc_size = sizeof(struct dma_extended_desc); 4030 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4031 desc_size = sizeof(struct dma_edesc); 4032 else 4033 desc_size = sizeof(struct dma_desc); 4034 4035 /* The own bit must be the latest setting done when prepare the 4036 * descriptor and then barrier is needed to make sure that 4037 * all is coherent before granting the DMA engine. 4038 */ 4039 wmb(); 4040 4041 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4042 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4043 } 4044 4045 /** 4046 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4047 * @skb : the socket buffer 4048 * @dev : device pointer 4049 * Description: this is the transmit function that is called on TSO frames 4050 * (support available on GMAC4 and newer chips). 4051 * Diagram below show the ring programming in case of TSO frames: 4052 * 4053 * First Descriptor 4054 * -------- 4055 * | DES0 |---> buffer1 = L2/L3/L4 header 4056 * | DES1 |---> TCP Payload (can continue on next descr...) 4057 * | DES2 |---> buffer 1 and 2 len 4058 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4059 * -------- 4060 * | 4061 * ... 4062 * | 4063 * -------- 4064 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4065 * | DES1 | --| 4066 * | DES2 | --> buffer 1 and 2 len 4067 * | DES3 | 4068 * -------- 4069 * 4070 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4071 */ 4072 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4073 { 4074 struct dma_desc *desc, *first, *mss_desc = NULL; 4075 struct stmmac_priv *priv = netdev_priv(dev); 4076 int nfrags = skb_shinfo(skb)->nr_frags; 4077 u32 queue = skb_get_queue_mapping(skb); 4078 unsigned int first_entry, tx_packets; 4079 int tmp_pay_len = 0, first_tx; 4080 struct stmmac_tx_queue *tx_q; 4081 bool has_vlan, set_ic; 4082 u8 proto_hdr_len, hdr; 4083 u32 pay_len, mss; 4084 dma_addr_t des; 4085 int i; 4086 4087 tx_q = &priv->dma_conf.tx_queue[queue]; 4088 first_tx = tx_q->cur_tx; 4089 4090 /* Compute header lengths */ 4091 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4092 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4093 hdr = sizeof(struct udphdr); 4094 } else { 4095 proto_hdr_len = skb_tcp_all_headers(skb); 4096 hdr = tcp_hdrlen(skb); 4097 } 4098 4099 /* Desc availability based on threshold should be enough safe */ 4100 if (unlikely(stmmac_tx_avail(priv, queue) < 4101 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4102 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4103 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4104 queue)); 4105 /* This is a hard error, log it. */ 4106 netdev_err(priv->dev, 4107 "%s: Tx Ring full when queue awake\n", 4108 __func__); 4109 } 4110 return NETDEV_TX_BUSY; 4111 } 4112 4113 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4114 4115 mss = skb_shinfo(skb)->gso_size; 4116 4117 /* set new MSS value if needed */ 4118 if (mss != tx_q->mss) { 4119 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4120 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4121 else 4122 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4123 4124 stmmac_set_mss(priv, mss_desc, mss); 4125 tx_q->mss = mss; 4126 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4127 priv->dma_conf.dma_tx_size); 4128 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4129 } 4130 4131 if (netif_msg_tx_queued(priv)) { 4132 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4133 __func__, hdr, proto_hdr_len, pay_len, mss); 4134 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4135 skb->data_len); 4136 } 4137 4138 /* Check if VLAN can be inserted by HW */ 4139 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4140 4141 first_entry = tx_q->cur_tx; 4142 WARN_ON(tx_q->tx_skbuff[first_entry]); 4143 4144 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4145 desc = &tx_q->dma_entx[first_entry].basic; 4146 else 4147 desc = &tx_q->dma_tx[first_entry]; 4148 first = desc; 4149 4150 if (has_vlan) 4151 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4152 4153 /* first descriptor: fill Headers on Buf1 */ 4154 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4155 DMA_TO_DEVICE); 4156 if (dma_mapping_error(priv->device, des)) 4157 goto dma_map_err; 4158 4159 tx_q->tx_skbuff_dma[first_entry].buf = des; 4160 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4161 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4162 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4163 4164 if (priv->dma_cap.addr64 <= 32) { 4165 first->des0 = cpu_to_le32(des); 4166 4167 /* Fill start of payload in buff2 of first descriptor */ 4168 if (pay_len) 4169 first->des1 = cpu_to_le32(des + proto_hdr_len); 4170 4171 /* If needed take extra descriptors to fill the remaining payload */ 4172 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4173 } else { 4174 stmmac_set_desc_addr(priv, first, des); 4175 tmp_pay_len = pay_len; 4176 des += proto_hdr_len; 4177 pay_len = 0; 4178 } 4179 4180 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4181 4182 /* Prepare fragments */ 4183 for (i = 0; i < nfrags; i++) { 4184 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4185 4186 des = skb_frag_dma_map(priv->device, frag, 0, 4187 skb_frag_size(frag), 4188 DMA_TO_DEVICE); 4189 if (dma_mapping_error(priv->device, des)) 4190 goto dma_map_err; 4191 4192 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4193 (i == nfrags - 1), queue); 4194 4195 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4196 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4197 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4198 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4199 } 4200 4201 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4202 4203 /* Only the last descriptor gets to point to the skb. */ 4204 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4205 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4206 4207 /* Manage tx mitigation */ 4208 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4209 tx_q->tx_count_frames += tx_packets; 4210 4211 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4212 set_ic = true; 4213 else if (!priv->tx_coal_frames[queue]) 4214 set_ic = false; 4215 else if (tx_packets > priv->tx_coal_frames[queue]) 4216 set_ic = true; 4217 else if ((tx_q->tx_count_frames % 4218 priv->tx_coal_frames[queue]) < tx_packets) 4219 set_ic = true; 4220 else 4221 set_ic = false; 4222 4223 if (set_ic) { 4224 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4225 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4226 else 4227 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4228 4229 tx_q->tx_count_frames = 0; 4230 stmmac_set_tx_ic(priv, desc); 4231 priv->xstats.tx_set_ic_bit++; 4232 } 4233 4234 /* We've used all descriptors we need for this skb, however, 4235 * advance cur_tx so that it references a fresh descriptor. 4236 * ndo_start_xmit will fill this descriptor the next time it's 4237 * called and stmmac_tx_clean may clean up to this descriptor. 4238 */ 4239 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4240 4241 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4242 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4243 __func__); 4244 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4245 } 4246 4247 dev->stats.tx_bytes += skb->len; 4248 priv->xstats.tx_tso_frames++; 4249 priv->xstats.tx_tso_nfrags += nfrags; 4250 4251 if (priv->sarc_type) 4252 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4253 4254 skb_tx_timestamp(skb); 4255 4256 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4257 priv->hwts_tx_en)) { 4258 /* declare that device is doing timestamping */ 4259 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4260 stmmac_enable_tx_timestamp(priv, first); 4261 } 4262 4263 /* Complete the first descriptor before granting the DMA */ 4264 stmmac_prepare_tso_tx_desc(priv, first, 1, 4265 proto_hdr_len, 4266 pay_len, 4267 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4268 hdr / 4, (skb->len - proto_hdr_len)); 4269 4270 /* If context desc is used to change MSS */ 4271 if (mss_desc) { 4272 /* Make sure that first descriptor has been completely 4273 * written, including its own bit. This is because MSS is 4274 * actually before first descriptor, so we need to make 4275 * sure that MSS's own bit is the last thing written. 4276 */ 4277 dma_wmb(); 4278 stmmac_set_tx_owner(priv, mss_desc); 4279 } 4280 4281 if (netif_msg_pktdata(priv)) { 4282 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4283 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4284 tx_q->cur_tx, first, nfrags); 4285 pr_info(">>> frame to be transmitted: "); 4286 print_pkt(skb->data, skb_headlen(skb)); 4287 } 4288 4289 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4290 4291 stmmac_flush_tx_descriptors(priv, queue); 4292 stmmac_tx_timer_arm(priv, queue); 4293 4294 return NETDEV_TX_OK; 4295 4296 dma_map_err: 4297 dev_err(priv->device, "Tx dma map failed\n"); 4298 dev_kfree_skb(skb); 4299 priv->dev->stats.tx_dropped++; 4300 return NETDEV_TX_OK; 4301 } 4302 4303 /** 4304 * stmmac_xmit - Tx entry point of the driver 4305 * @skb : the socket buffer 4306 * @dev : device pointer 4307 * Description : this is the tx entry point of the driver. 4308 * It programs the chain or the ring and supports oversized frames 4309 * and SG feature. 4310 */ 4311 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4312 { 4313 unsigned int first_entry, tx_packets, enh_desc; 4314 struct stmmac_priv *priv = netdev_priv(dev); 4315 unsigned int nopaged_len = skb_headlen(skb); 4316 int i, csum_insertion = 0, is_jumbo = 0; 4317 u32 queue = skb_get_queue_mapping(skb); 4318 int nfrags = skb_shinfo(skb)->nr_frags; 4319 int gso = skb_shinfo(skb)->gso_type; 4320 struct dma_edesc *tbs_desc = NULL; 4321 struct dma_desc *desc, *first; 4322 struct stmmac_tx_queue *tx_q; 4323 bool has_vlan, set_ic; 4324 int entry, first_tx; 4325 dma_addr_t des; 4326 4327 tx_q = &priv->dma_conf.tx_queue[queue]; 4328 first_tx = tx_q->cur_tx; 4329 4330 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4331 stmmac_disable_eee_mode(priv); 4332 4333 /* Manage oversized TCP frames for GMAC4 device */ 4334 if (skb_is_gso(skb) && priv->tso) { 4335 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4336 return stmmac_tso_xmit(skb, dev); 4337 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4338 return stmmac_tso_xmit(skb, dev); 4339 } 4340 4341 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4342 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4343 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4344 queue)); 4345 /* This is a hard error, log it. */ 4346 netdev_err(priv->dev, 4347 "%s: Tx Ring full when queue awake\n", 4348 __func__); 4349 } 4350 return NETDEV_TX_BUSY; 4351 } 4352 4353 /* Check if VLAN can be inserted by HW */ 4354 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4355 4356 entry = tx_q->cur_tx; 4357 first_entry = entry; 4358 WARN_ON(tx_q->tx_skbuff[first_entry]); 4359 4360 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4361 4362 if (likely(priv->extend_desc)) 4363 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4364 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4365 desc = &tx_q->dma_entx[entry].basic; 4366 else 4367 desc = tx_q->dma_tx + entry; 4368 4369 first = desc; 4370 4371 if (has_vlan) 4372 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4373 4374 enh_desc = priv->plat->enh_desc; 4375 /* To program the descriptors according to the size of the frame */ 4376 if (enh_desc) 4377 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4378 4379 if (unlikely(is_jumbo)) { 4380 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4381 if (unlikely(entry < 0) && (entry != -EINVAL)) 4382 goto dma_map_err; 4383 } 4384 4385 for (i = 0; i < nfrags; i++) { 4386 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4387 int len = skb_frag_size(frag); 4388 bool last_segment = (i == (nfrags - 1)); 4389 4390 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4391 WARN_ON(tx_q->tx_skbuff[entry]); 4392 4393 if (likely(priv->extend_desc)) 4394 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4395 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4396 desc = &tx_q->dma_entx[entry].basic; 4397 else 4398 desc = tx_q->dma_tx + entry; 4399 4400 des = skb_frag_dma_map(priv->device, frag, 0, len, 4401 DMA_TO_DEVICE); 4402 if (dma_mapping_error(priv->device, des)) 4403 goto dma_map_err; /* should reuse desc w/o issues */ 4404 4405 tx_q->tx_skbuff_dma[entry].buf = des; 4406 4407 stmmac_set_desc_addr(priv, desc, des); 4408 4409 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4410 tx_q->tx_skbuff_dma[entry].len = len; 4411 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4412 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4413 4414 /* Prepare the descriptor and set the own bit too */ 4415 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4416 priv->mode, 1, last_segment, skb->len); 4417 } 4418 4419 /* Only the last descriptor gets to point to the skb. */ 4420 tx_q->tx_skbuff[entry] = skb; 4421 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4422 4423 /* According to the coalesce parameter the IC bit for the latest 4424 * segment is reset and the timer re-started to clean the tx status. 4425 * This approach takes care about the fragments: desc is the first 4426 * element in case of no SG. 4427 */ 4428 tx_packets = (entry + 1) - first_tx; 4429 tx_q->tx_count_frames += tx_packets; 4430 4431 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4432 set_ic = true; 4433 else if (!priv->tx_coal_frames[queue]) 4434 set_ic = false; 4435 else if (tx_packets > priv->tx_coal_frames[queue]) 4436 set_ic = true; 4437 else if ((tx_q->tx_count_frames % 4438 priv->tx_coal_frames[queue]) < tx_packets) 4439 set_ic = true; 4440 else 4441 set_ic = false; 4442 4443 if (set_ic) { 4444 if (likely(priv->extend_desc)) 4445 desc = &tx_q->dma_etx[entry].basic; 4446 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4447 desc = &tx_q->dma_entx[entry].basic; 4448 else 4449 desc = &tx_q->dma_tx[entry]; 4450 4451 tx_q->tx_count_frames = 0; 4452 stmmac_set_tx_ic(priv, desc); 4453 priv->xstats.tx_set_ic_bit++; 4454 } 4455 4456 /* We've used all descriptors we need for this skb, however, 4457 * advance cur_tx so that it references a fresh descriptor. 4458 * ndo_start_xmit will fill this descriptor the next time it's 4459 * called and stmmac_tx_clean may clean up to this descriptor. 4460 */ 4461 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4462 tx_q->cur_tx = entry; 4463 4464 if (netif_msg_pktdata(priv)) { 4465 netdev_dbg(priv->dev, 4466 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4467 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4468 entry, first, nfrags); 4469 4470 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4471 print_pkt(skb->data, skb->len); 4472 } 4473 4474 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4475 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4476 __func__); 4477 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4478 } 4479 4480 dev->stats.tx_bytes += skb->len; 4481 4482 if (priv->sarc_type) 4483 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4484 4485 skb_tx_timestamp(skb); 4486 4487 /* Ready to fill the first descriptor and set the OWN bit w/o any 4488 * problems because all the descriptors are actually ready to be 4489 * passed to the DMA engine. 4490 */ 4491 if (likely(!is_jumbo)) { 4492 bool last_segment = (nfrags == 0); 4493 4494 des = dma_map_single(priv->device, skb->data, 4495 nopaged_len, DMA_TO_DEVICE); 4496 if (dma_mapping_error(priv->device, des)) 4497 goto dma_map_err; 4498 4499 tx_q->tx_skbuff_dma[first_entry].buf = des; 4500 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4501 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4502 4503 stmmac_set_desc_addr(priv, first, des); 4504 4505 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4506 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4507 4508 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4509 priv->hwts_tx_en)) { 4510 /* declare that device is doing timestamping */ 4511 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4512 stmmac_enable_tx_timestamp(priv, first); 4513 } 4514 4515 /* Prepare the first descriptor setting the OWN bit too */ 4516 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4517 csum_insertion, priv->mode, 0, last_segment, 4518 skb->len); 4519 } 4520 4521 if (tx_q->tbs & STMMAC_TBS_EN) { 4522 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4523 4524 tbs_desc = &tx_q->dma_entx[first_entry]; 4525 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4526 } 4527 4528 stmmac_set_tx_owner(priv, first); 4529 4530 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4531 4532 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4533 4534 stmmac_flush_tx_descriptors(priv, queue); 4535 stmmac_tx_timer_arm(priv, queue); 4536 4537 return NETDEV_TX_OK; 4538 4539 dma_map_err: 4540 netdev_err(priv->dev, "Tx DMA map failed\n"); 4541 dev_kfree_skb(skb); 4542 priv->dev->stats.tx_dropped++; 4543 return NETDEV_TX_OK; 4544 } 4545 4546 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4547 { 4548 struct vlan_ethhdr *veth; 4549 __be16 vlan_proto; 4550 u16 vlanid; 4551 4552 veth = (struct vlan_ethhdr *)skb->data; 4553 vlan_proto = veth->h_vlan_proto; 4554 4555 if ((vlan_proto == htons(ETH_P_8021Q) && 4556 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4557 (vlan_proto == htons(ETH_P_8021AD) && 4558 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4559 /* pop the vlan tag */ 4560 vlanid = ntohs(veth->h_vlan_TCI); 4561 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4562 skb_pull(skb, VLAN_HLEN); 4563 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4564 } 4565 } 4566 4567 /** 4568 * stmmac_rx_refill - refill used skb preallocated buffers 4569 * @priv: driver private structure 4570 * @queue: RX queue index 4571 * Description : this is to reallocate the skb for the reception process 4572 * that is based on zero-copy. 4573 */ 4574 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4575 { 4576 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4577 int dirty = stmmac_rx_dirty(priv, queue); 4578 unsigned int entry = rx_q->dirty_rx; 4579 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4580 4581 if (priv->dma_cap.addr64 <= 32) 4582 gfp |= GFP_DMA32; 4583 4584 while (dirty-- > 0) { 4585 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4586 struct dma_desc *p; 4587 bool use_rx_wd; 4588 4589 if (priv->extend_desc) 4590 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4591 else 4592 p = rx_q->dma_rx + entry; 4593 4594 if (!buf->page) { 4595 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4596 if (!buf->page) 4597 break; 4598 } 4599 4600 if (priv->sph && !buf->sec_page) { 4601 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4602 if (!buf->sec_page) 4603 break; 4604 4605 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4606 } 4607 4608 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4609 4610 stmmac_set_desc_addr(priv, p, buf->addr); 4611 if (priv->sph) 4612 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4613 else 4614 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4615 stmmac_refill_desc3(priv, rx_q, p); 4616 4617 rx_q->rx_count_frames++; 4618 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4619 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4620 rx_q->rx_count_frames = 0; 4621 4622 use_rx_wd = !priv->rx_coal_frames[queue]; 4623 use_rx_wd |= rx_q->rx_count_frames > 0; 4624 if (!priv->use_riwt) 4625 use_rx_wd = false; 4626 4627 dma_wmb(); 4628 stmmac_set_rx_owner(priv, p, use_rx_wd); 4629 4630 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4631 } 4632 rx_q->dirty_rx = entry; 4633 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4634 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4635 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4636 } 4637 4638 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4639 struct dma_desc *p, 4640 int status, unsigned int len) 4641 { 4642 unsigned int plen = 0, hlen = 0; 4643 int coe = priv->hw->rx_csum; 4644 4645 /* Not first descriptor, buffer is always zero */ 4646 if (priv->sph && len) 4647 return 0; 4648 4649 /* First descriptor, get split header length */ 4650 stmmac_get_rx_header_len(priv, p, &hlen); 4651 if (priv->sph && hlen) { 4652 priv->xstats.rx_split_hdr_pkt_n++; 4653 return hlen; 4654 } 4655 4656 /* First descriptor, not last descriptor and not split header */ 4657 if (status & rx_not_ls) 4658 return priv->dma_conf.dma_buf_sz; 4659 4660 plen = stmmac_get_rx_frame_len(priv, p, coe); 4661 4662 /* First descriptor and last descriptor and not split header */ 4663 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4664 } 4665 4666 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4667 struct dma_desc *p, 4668 int status, unsigned int len) 4669 { 4670 int coe = priv->hw->rx_csum; 4671 unsigned int plen = 0; 4672 4673 /* Not split header, buffer is not available */ 4674 if (!priv->sph) 4675 return 0; 4676 4677 /* Not last descriptor */ 4678 if (status & rx_not_ls) 4679 return priv->dma_conf.dma_buf_sz; 4680 4681 plen = stmmac_get_rx_frame_len(priv, p, coe); 4682 4683 /* Last descriptor */ 4684 return plen - len; 4685 } 4686 4687 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4688 struct xdp_frame *xdpf, bool dma_map) 4689 { 4690 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4691 unsigned int entry = tx_q->cur_tx; 4692 struct dma_desc *tx_desc; 4693 dma_addr_t dma_addr; 4694 bool set_ic; 4695 4696 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4697 return STMMAC_XDP_CONSUMED; 4698 4699 if (likely(priv->extend_desc)) 4700 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4701 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4702 tx_desc = &tx_q->dma_entx[entry].basic; 4703 else 4704 tx_desc = tx_q->dma_tx + entry; 4705 4706 if (dma_map) { 4707 dma_addr = dma_map_single(priv->device, xdpf->data, 4708 xdpf->len, DMA_TO_DEVICE); 4709 if (dma_mapping_error(priv->device, dma_addr)) 4710 return STMMAC_XDP_CONSUMED; 4711 4712 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4713 } else { 4714 struct page *page = virt_to_page(xdpf->data); 4715 4716 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4717 xdpf->headroom; 4718 dma_sync_single_for_device(priv->device, dma_addr, 4719 xdpf->len, DMA_BIDIRECTIONAL); 4720 4721 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4722 } 4723 4724 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4725 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4726 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4727 tx_q->tx_skbuff_dma[entry].last_segment = true; 4728 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4729 4730 tx_q->xdpf[entry] = xdpf; 4731 4732 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4733 4734 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4735 true, priv->mode, true, true, 4736 xdpf->len); 4737 4738 tx_q->tx_count_frames++; 4739 4740 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4741 set_ic = true; 4742 else 4743 set_ic = false; 4744 4745 if (set_ic) { 4746 tx_q->tx_count_frames = 0; 4747 stmmac_set_tx_ic(priv, tx_desc); 4748 priv->xstats.tx_set_ic_bit++; 4749 } 4750 4751 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4752 4753 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4754 tx_q->cur_tx = entry; 4755 4756 return STMMAC_XDP_TX; 4757 } 4758 4759 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4760 int cpu) 4761 { 4762 int index = cpu; 4763 4764 if (unlikely(index < 0)) 4765 index = 0; 4766 4767 while (index >= priv->plat->tx_queues_to_use) 4768 index -= priv->plat->tx_queues_to_use; 4769 4770 return index; 4771 } 4772 4773 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4774 struct xdp_buff *xdp) 4775 { 4776 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4777 int cpu = smp_processor_id(); 4778 struct netdev_queue *nq; 4779 int queue; 4780 int res; 4781 4782 if (unlikely(!xdpf)) 4783 return STMMAC_XDP_CONSUMED; 4784 4785 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4786 nq = netdev_get_tx_queue(priv->dev, queue); 4787 4788 __netif_tx_lock(nq, cpu); 4789 /* Avoids TX time-out as we are sharing with slow path */ 4790 txq_trans_cond_update(nq); 4791 4792 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4793 if (res == STMMAC_XDP_TX) 4794 stmmac_flush_tx_descriptors(priv, queue); 4795 4796 __netif_tx_unlock(nq); 4797 4798 return res; 4799 } 4800 4801 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4802 struct bpf_prog *prog, 4803 struct xdp_buff *xdp) 4804 { 4805 u32 act; 4806 int res; 4807 4808 act = bpf_prog_run_xdp(prog, xdp); 4809 switch (act) { 4810 case XDP_PASS: 4811 res = STMMAC_XDP_PASS; 4812 break; 4813 case XDP_TX: 4814 res = stmmac_xdp_xmit_back(priv, xdp); 4815 break; 4816 case XDP_REDIRECT: 4817 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4818 res = STMMAC_XDP_CONSUMED; 4819 else 4820 res = STMMAC_XDP_REDIRECT; 4821 break; 4822 default: 4823 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4824 fallthrough; 4825 case XDP_ABORTED: 4826 trace_xdp_exception(priv->dev, prog, act); 4827 fallthrough; 4828 case XDP_DROP: 4829 res = STMMAC_XDP_CONSUMED; 4830 break; 4831 } 4832 4833 return res; 4834 } 4835 4836 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4837 struct xdp_buff *xdp) 4838 { 4839 struct bpf_prog *prog; 4840 int res; 4841 4842 prog = READ_ONCE(priv->xdp_prog); 4843 if (!prog) { 4844 res = STMMAC_XDP_PASS; 4845 goto out; 4846 } 4847 4848 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4849 out: 4850 return ERR_PTR(-res); 4851 } 4852 4853 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4854 int xdp_status) 4855 { 4856 int cpu = smp_processor_id(); 4857 int queue; 4858 4859 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4860 4861 if (xdp_status & STMMAC_XDP_TX) 4862 stmmac_tx_timer_arm(priv, queue); 4863 4864 if (xdp_status & STMMAC_XDP_REDIRECT) 4865 xdp_do_flush(); 4866 } 4867 4868 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4869 struct xdp_buff *xdp) 4870 { 4871 unsigned int metasize = xdp->data - xdp->data_meta; 4872 unsigned int datasize = xdp->data_end - xdp->data; 4873 struct sk_buff *skb; 4874 4875 skb = __napi_alloc_skb(&ch->rxtx_napi, 4876 xdp->data_end - xdp->data_hard_start, 4877 GFP_ATOMIC | __GFP_NOWARN); 4878 if (unlikely(!skb)) 4879 return NULL; 4880 4881 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4882 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4883 if (metasize) 4884 skb_metadata_set(skb, metasize); 4885 4886 return skb; 4887 } 4888 4889 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4890 struct dma_desc *p, struct dma_desc *np, 4891 struct xdp_buff *xdp) 4892 { 4893 struct stmmac_channel *ch = &priv->channel[queue]; 4894 unsigned int len = xdp->data_end - xdp->data; 4895 enum pkt_hash_types hash_type; 4896 int coe = priv->hw->rx_csum; 4897 struct sk_buff *skb; 4898 u32 hash; 4899 4900 skb = stmmac_construct_skb_zc(ch, xdp); 4901 if (!skb) { 4902 priv->dev->stats.rx_dropped++; 4903 return; 4904 } 4905 4906 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4907 stmmac_rx_vlan(priv->dev, skb); 4908 skb->protocol = eth_type_trans(skb, priv->dev); 4909 4910 if (unlikely(!coe)) 4911 skb_checksum_none_assert(skb); 4912 else 4913 skb->ip_summed = CHECKSUM_UNNECESSARY; 4914 4915 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4916 skb_set_hash(skb, hash, hash_type); 4917 4918 skb_record_rx_queue(skb, queue); 4919 napi_gro_receive(&ch->rxtx_napi, skb); 4920 4921 priv->dev->stats.rx_packets++; 4922 priv->dev->stats.rx_bytes += len; 4923 } 4924 4925 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4926 { 4927 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4928 unsigned int entry = rx_q->dirty_rx; 4929 struct dma_desc *rx_desc = NULL; 4930 bool ret = true; 4931 4932 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4933 4934 while (budget-- > 0 && entry != rx_q->cur_rx) { 4935 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4936 dma_addr_t dma_addr; 4937 bool use_rx_wd; 4938 4939 if (!buf->xdp) { 4940 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4941 if (!buf->xdp) { 4942 ret = false; 4943 break; 4944 } 4945 } 4946 4947 if (priv->extend_desc) 4948 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4949 else 4950 rx_desc = rx_q->dma_rx + entry; 4951 4952 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4953 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4954 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4955 stmmac_refill_desc3(priv, rx_q, rx_desc); 4956 4957 rx_q->rx_count_frames++; 4958 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4959 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4960 rx_q->rx_count_frames = 0; 4961 4962 use_rx_wd = !priv->rx_coal_frames[queue]; 4963 use_rx_wd |= rx_q->rx_count_frames > 0; 4964 if (!priv->use_riwt) 4965 use_rx_wd = false; 4966 4967 dma_wmb(); 4968 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4969 4970 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4971 } 4972 4973 if (rx_desc) { 4974 rx_q->dirty_rx = entry; 4975 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4976 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4977 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4978 } 4979 4980 return ret; 4981 } 4982 4983 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4984 { 4985 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4986 unsigned int count = 0, error = 0, len = 0; 4987 int dirty = stmmac_rx_dirty(priv, queue); 4988 unsigned int next_entry = rx_q->cur_rx; 4989 unsigned int desc_size; 4990 struct bpf_prog *prog; 4991 bool failure = false; 4992 int xdp_status = 0; 4993 int status = 0; 4994 4995 if (netif_msg_rx_status(priv)) { 4996 void *rx_head; 4997 4998 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4999 if (priv->extend_desc) { 5000 rx_head = (void *)rx_q->dma_erx; 5001 desc_size = sizeof(struct dma_extended_desc); 5002 } else { 5003 rx_head = (void *)rx_q->dma_rx; 5004 desc_size = sizeof(struct dma_desc); 5005 } 5006 5007 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5008 rx_q->dma_rx_phy, desc_size); 5009 } 5010 while (count < limit) { 5011 struct stmmac_rx_buffer *buf; 5012 unsigned int buf1_len = 0; 5013 struct dma_desc *np, *p; 5014 int entry; 5015 int res; 5016 5017 if (!count && rx_q->state_saved) { 5018 error = rx_q->state.error; 5019 len = rx_q->state.len; 5020 } else { 5021 rx_q->state_saved = false; 5022 error = 0; 5023 len = 0; 5024 } 5025 5026 if (count >= limit) 5027 break; 5028 5029 read_again: 5030 buf1_len = 0; 5031 entry = next_entry; 5032 buf = &rx_q->buf_pool[entry]; 5033 5034 if (dirty >= STMMAC_RX_FILL_BATCH) { 5035 failure = failure || 5036 !stmmac_rx_refill_zc(priv, queue, dirty); 5037 dirty = 0; 5038 } 5039 5040 if (priv->extend_desc) 5041 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5042 else 5043 p = rx_q->dma_rx + entry; 5044 5045 /* read the status of the incoming frame */ 5046 status = stmmac_rx_status(priv, &priv->dev->stats, 5047 &priv->xstats, p); 5048 /* check if managed by the DMA otherwise go ahead */ 5049 if (unlikely(status & dma_own)) 5050 break; 5051 5052 /* Prefetch the next RX descriptor */ 5053 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5054 priv->dma_conf.dma_rx_size); 5055 next_entry = rx_q->cur_rx; 5056 5057 if (priv->extend_desc) 5058 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5059 else 5060 np = rx_q->dma_rx + next_entry; 5061 5062 prefetch(np); 5063 5064 /* Ensure a valid XSK buffer before proceed */ 5065 if (!buf->xdp) 5066 break; 5067 5068 if (priv->extend_desc) 5069 stmmac_rx_extended_status(priv, &priv->dev->stats, 5070 &priv->xstats, 5071 rx_q->dma_erx + entry); 5072 if (unlikely(status == discard_frame)) { 5073 xsk_buff_free(buf->xdp); 5074 buf->xdp = NULL; 5075 dirty++; 5076 error = 1; 5077 if (!priv->hwts_rx_en) 5078 priv->dev->stats.rx_errors++; 5079 } 5080 5081 if (unlikely(error && (status & rx_not_ls))) 5082 goto read_again; 5083 if (unlikely(error)) { 5084 count++; 5085 continue; 5086 } 5087 5088 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5089 if (likely(status & rx_not_ls)) { 5090 xsk_buff_free(buf->xdp); 5091 buf->xdp = NULL; 5092 dirty++; 5093 count++; 5094 goto read_again; 5095 } 5096 5097 /* XDP ZC Frame only support primary buffers for now */ 5098 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5099 len += buf1_len; 5100 5101 /* ACS is disabled; strip manually. */ 5102 if (likely(!(status & rx_not_ls))) { 5103 buf1_len -= ETH_FCS_LEN; 5104 len -= ETH_FCS_LEN; 5105 } 5106 5107 /* RX buffer is good and fit into a XSK pool buffer */ 5108 buf->xdp->data_end = buf->xdp->data + buf1_len; 5109 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5110 5111 prog = READ_ONCE(priv->xdp_prog); 5112 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5113 5114 switch (res) { 5115 case STMMAC_XDP_PASS: 5116 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5117 xsk_buff_free(buf->xdp); 5118 break; 5119 case STMMAC_XDP_CONSUMED: 5120 xsk_buff_free(buf->xdp); 5121 priv->dev->stats.rx_dropped++; 5122 break; 5123 case STMMAC_XDP_TX: 5124 case STMMAC_XDP_REDIRECT: 5125 xdp_status |= res; 5126 break; 5127 } 5128 5129 buf->xdp = NULL; 5130 dirty++; 5131 count++; 5132 } 5133 5134 if (status & rx_not_ls) { 5135 rx_q->state_saved = true; 5136 rx_q->state.error = error; 5137 rx_q->state.len = len; 5138 } 5139 5140 stmmac_finalize_xdp_rx(priv, xdp_status); 5141 5142 priv->xstats.rx_pkt_n += count; 5143 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5144 5145 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5146 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5147 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5148 else 5149 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5150 5151 return (int)count; 5152 } 5153 5154 return failure ? limit : (int)count; 5155 } 5156 5157 /** 5158 * stmmac_rx - manage the receive process 5159 * @priv: driver private structure 5160 * @limit: napi bugget 5161 * @queue: RX queue index. 5162 * Description : this the function called by the napi poll method. 5163 * It gets all the frames inside the ring. 5164 */ 5165 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5166 { 5167 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5168 struct stmmac_channel *ch = &priv->channel[queue]; 5169 unsigned int count = 0, error = 0, len = 0; 5170 int status = 0, coe = priv->hw->rx_csum; 5171 unsigned int next_entry = rx_q->cur_rx; 5172 enum dma_data_direction dma_dir; 5173 unsigned int desc_size; 5174 struct sk_buff *skb = NULL; 5175 struct xdp_buff xdp; 5176 int xdp_status = 0; 5177 int buf_sz; 5178 5179 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5180 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5181 5182 if (netif_msg_rx_status(priv)) { 5183 void *rx_head; 5184 5185 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5186 if (priv->extend_desc) { 5187 rx_head = (void *)rx_q->dma_erx; 5188 desc_size = sizeof(struct dma_extended_desc); 5189 } else { 5190 rx_head = (void *)rx_q->dma_rx; 5191 desc_size = sizeof(struct dma_desc); 5192 } 5193 5194 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5195 rx_q->dma_rx_phy, desc_size); 5196 } 5197 while (count < limit) { 5198 unsigned int buf1_len = 0, buf2_len = 0; 5199 enum pkt_hash_types hash_type; 5200 struct stmmac_rx_buffer *buf; 5201 struct dma_desc *np, *p; 5202 int entry; 5203 u32 hash; 5204 5205 if (!count && rx_q->state_saved) { 5206 skb = rx_q->state.skb; 5207 error = rx_q->state.error; 5208 len = rx_q->state.len; 5209 } else { 5210 rx_q->state_saved = false; 5211 skb = NULL; 5212 error = 0; 5213 len = 0; 5214 } 5215 5216 if (count >= limit) 5217 break; 5218 5219 read_again: 5220 buf1_len = 0; 5221 buf2_len = 0; 5222 entry = next_entry; 5223 buf = &rx_q->buf_pool[entry]; 5224 5225 if (priv->extend_desc) 5226 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5227 else 5228 p = rx_q->dma_rx + entry; 5229 5230 /* read the status of the incoming frame */ 5231 status = stmmac_rx_status(priv, &priv->dev->stats, 5232 &priv->xstats, p); 5233 /* check if managed by the DMA otherwise go ahead */ 5234 if (unlikely(status & dma_own)) 5235 break; 5236 5237 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5238 priv->dma_conf.dma_rx_size); 5239 next_entry = rx_q->cur_rx; 5240 5241 if (priv->extend_desc) 5242 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5243 else 5244 np = rx_q->dma_rx + next_entry; 5245 5246 prefetch(np); 5247 5248 if (priv->extend_desc) 5249 stmmac_rx_extended_status(priv, &priv->dev->stats, 5250 &priv->xstats, rx_q->dma_erx + entry); 5251 if (unlikely(status == discard_frame)) { 5252 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5253 buf->page = NULL; 5254 error = 1; 5255 if (!priv->hwts_rx_en) 5256 priv->dev->stats.rx_errors++; 5257 } 5258 5259 if (unlikely(error && (status & rx_not_ls))) 5260 goto read_again; 5261 if (unlikely(error)) { 5262 dev_kfree_skb(skb); 5263 skb = NULL; 5264 count++; 5265 continue; 5266 } 5267 5268 /* Buffer is good. Go on. */ 5269 5270 prefetch(page_address(buf->page) + buf->page_offset); 5271 if (buf->sec_page) 5272 prefetch(page_address(buf->sec_page)); 5273 5274 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5275 len += buf1_len; 5276 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5277 len += buf2_len; 5278 5279 /* ACS is disabled; strip manually. */ 5280 if (likely(!(status & rx_not_ls))) { 5281 if (buf2_len) { 5282 buf2_len -= ETH_FCS_LEN; 5283 len -= ETH_FCS_LEN; 5284 } else if (buf1_len) { 5285 buf1_len -= ETH_FCS_LEN; 5286 len -= ETH_FCS_LEN; 5287 } 5288 } 5289 5290 if (!skb) { 5291 unsigned int pre_len, sync_len; 5292 5293 dma_sync_single_for_cpu(priv->device, buf->addr, 5294 buf1_len, dma_dir); 5295 5296 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5297 xdp_prepare_buff(&xdp, page_address(buf->page), 5298 buf->page_offset, buf1_len, false); 5299 5300 pre_len = xdp.data_end - xdp.data_hard_start - 5301 buf->page_offset; 5302 skb = stmmac_xdp_run_prog(priv, &xdp); 5303 /* Due xdp_adjust_tail: DMA sync for_device 5304 * cover max len CPU touch 5305 */ 5306 sync_len = xdp.data_end - xdp.data_hard_start - 5307 buf->page_offset; 5308 sync_len = max(sync_len, pre_len); 5309 5310 /* For Not XDP_PASS verdict */ 5311 if (IS_ERR(skb)) { 5312 unsigned int xdp_res = -PTR_ERR(skb); 5313 5314 if (xdp_res & STMMAC_XDP_CONSUMED) { 5315 page_pool_put_page(rx_q->page_pool, 5316 virt_to_head_page(xdp.data), 5317 sync_len, true); 5318 buf->page = NULL; 5319 priv->dev->stats.rx_dropped++; 5320 5321 /* Clear skb as it was set as 5322 * status by XDP program. 5323 */ 5324 skb = NULL; 5325 5326 if (unlikely((status & rx_not_ls))) 5327 goto read_again; 5328 5329 count++; 5330 continue; 5331 } else if (xdp_res & (STMMAC_XDP_TX | 5332 STMMAC_XDP_REDIRECT)) { 5333 xdp_status |= xdp_res; 5334 buf->page = NULL; 5335 skb = NULL; 5336 count++; 5337 continue; 5338 } 5339 } 5340 } 5341 5342 if (!skb) { 5343 /* XDP program may expand or reduce tail */ 5344 buf1_len = xdp.data_end - xdp.data; 5345 5346 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5347 if (!skb) { 5348 priv->dev->stats.rx_dropped++; 5349 count++; 5350 goto drain_data; 5351 } 5352 5353 /* XDP program may adjust header */ 5354 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5355 skb_put(skb, buf1_len); 5356 5357 /* Data payload copied into SKB, page ready for recycle */ 5358 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5359 buf->page = NULL; 5360 } else if (buf1_len) { 5361 dma_sync_single_for_cpu(priv->device, buf->addr, 5362 buf1_len, dma_dir); 5363 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5364 buf->page, buf->page_offset, buf1_len, 5365 priv->dma_conf.dma_buf_sz); 5366 5367 /* Data payload appended into SKB */ 5368 page_pool_release_page(rx_q->page_pool, buf->page); 5369 buf->page = NULL; 5370 } 5371 5372 if (buf2_len) { 5373 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5374 buf2_len, dma_dir); 5375 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5376 buf->sec_page, 0, buf2_len, 5377 priv->dma_conf.dma_buf_sz); 5378 5379 /* Data payload appended into SKB */ 5380 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5381 buf->sec_page = NULL; 5382 } 5383 5384 drain_data: 5385 if (likely(status & rx_not_ls)) 5386 goto read_again; 5387 if (!skb) 5388 continue; 5389 5390 /* Got entire packet into SKB. Finish it. */ 5391 5392 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5393 stmmac_rx_vlan(priv->dev, skb); 5394 skb->protocol = eth_type_trans(skb, priv->dev); 5395 5396 if (unlikely(!coe)) 5397 skb_checksum_none_assert(skb); 5398 else 5399 skb->ip_summed = CHECKSUM_UNNECESSARY; 5400 5401 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5402 skb_set_hash(skb, hash, hash_type); 5403 5404 skb_record_rx_queue(skb, queue); 5405 napi_gro_receive(&ch->rx_napi, skb); 5406 skb = NULL; 5407 5408 priv->dev->stats.rx_packets++; 5409 priv->dev->stats.rx_bytes += len; 5410 count++; 5411 } 5412 5413 if (status & rx_not_ls || skb) { 5414 rx_q->state_saved = true; 5415 rx_q->state.skb = skb; 5416 rx_q->state.error = error; 5417 rx_q->state.len = len; 5418 } 5419 5420 stmmac_finalize_xdp_rx(priv, xdp_status); 5421 5422 stmmac_rx_refill(priv, queue); 5423 5424 priv->xstats.rx_pkt_n += count; 5425 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5426 5427 return count; 5428 } 5429 5430 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5431 { 5432 struct stmmac_channel *ch = 5433 container_of(napi, struct stmmac_channel, rx_napi); 5434 struct stmmac_priv *priv = ch->priv_data; 5435 u32 chan = ch->index; 5436 int work_done; 5437 5438 priv->xstats.napi_poll++; 5439 5440 work_done = stmmac_rx(priv, budget, chan); 5441 if (work_done < budget && napi_complete_done(napi, work_done)) { 5442 unsigned long flags; 5443 5444 spin_lock_irqsave(&ch->lock, flags); 5445 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5446 spin_unlock_irqrestore(&ch->lock, flags); 5447 } 5448 5449 return work_done; 5450 } 5451 5452 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5453 { 5454 struct stmmac_channel *ch = 5455 container_of(napi, struct stmmac_channel, tx_napi); 5456 struct stmmac_priv *priv = ch->priv_data; 5457 u32 chan = ch->index; 5458 int work_done; 5459 5460 priv->xstats.napi_poll++; 5461 5462 work_done = stmmac_tx_clean(priv, budget, chan); 5463 work_done = min(work_done, budget); 5464 5465 if (work_done < budget && napi_complete_done(napi, work_done)) { 5466 unsigned long flags; 5467 5468 spin_lock_irqsave(&ch->lock, flags); 5469 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5470 spin_unlock_irqrestore(&ch->lock, flags); 5471 } 5472 5473 return work_done; 5474 } 5475 5476 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5477 { 5478 struct stmmac_channel *ch = 5479 container_of(napi, struct stmmac_channel, rxtx_napi); 5480 struct stmmac_priv *priv = ch->priv_data; 5481 int rx_done, tx_done, rxtx_done; 5482 u32 chan = ch->index; 5483 5484 priv->xstats.napi_poll++; 5485 5486 tx_done = stmmac_tx_clean(priv, budget, chan); 5487 tx_done = min(tx_done, budget); 5488 5489 rx_done = stmmac_rx_zc(priv, budget, chan); 5490 5491 rxtx_done = max(tx_done, rx_done); 5492 5493 /* If either TX or RX work is not complete, return budget 5494 * and keep pooling 5495 */ 5496 if (rxtx_done >= budget) 5497 return budget; 5498 5499 /* all work done, exit the polling mode */ 5500 if (napi_complete_done(napi, rxtx_done)) { 5501 unsigned long flags; 5502 5503 spin_lock_irqsave(&ch->lock, flags); 5504 /* Both RX and TX work done are compelte, 5505 * so enable both RX & TX IRQs. 5506 */ 5507 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5508 spin_unlock_irqrestore(&ch->lock, flags); 5509 } 5510 5511 return min(rxtx_done, budget - 1); 5512 } 5513 5514 /** 5515 * stmmac_tx_timeout 5516 * @dev : Pointer to net device structure 5517 * @txqueue: the index of the hanging transmit queue 5518 * Description: this function is called when a packet transmission fails to 5519 * complete within a reasonable time. The driver will mark the error in the 5520 * netdev structure and arrange for the device to be reset to a sane state 5521 * in order to transmit a new packet. 5522 */ 5523 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5524 { 5525 struct stmmac_priv *priv = netdev_priv(dev); 5526 5527 stmmac_global_err(priv); 5528 } 5529 5530 /** 5531 * stmmac_set_rx_mode - entry point for multicast addressing 5532 * @dev : pointer to the device structure 5533 * Description: 5534 * This function is a driver entry point which gets called by the kernel 5535 * whenever multicast addresses must be enabled/disabled. 5536 * Return value: 5537 * void. 5538 */ 5539 static void stmmac_set_rx_mode(struct net_device *dev) 5540 { 5541 struct stmmac_priv *priv = netdev_priv(dev); 5542 5543 stmmac_set_filter(priv, priv->hw, dev); 5544 } 5545 5546 /** 5547 * stmmac_change_mtu - entry point to change MTU size for the device. 5548 * @dev : device pointer. 5549 * @new_mtu : the new MTU size for the device. 5550 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5551 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5552 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5553 * Return value: 5554 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5555 * file on failure. 5556 */ 5557 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5558 { 5559 struct stmmac_priv *priv = netdev_priv(dev); 5560 int txfifosz = priv->plat->tx_fifo_size; 5561 struct stmmac_dma_conf *dma_conf; 5562 const int mtu = new_mtu; 5563 int ret; 5564 5565 if (txfifosz == 0) 5566 txfifosz = priv->dma_cap.tx_fifo_size; 5567 5568 txfifosz /= priv->plat->tx_queues_to_use; 5569 5570 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5571 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5572 return -EINVAL; 5573 } 5574 5575 new_mtu = STMMAC_ALIGN(new_mtu); 5576 5577 /* If condition true, FIFO is too small or MTU too large */ 5578 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5579 return -EINVAL; 5580 5581 if (netif_running(dev)) { 5582 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5583 /* Try to allocate the new DMA conf with the new mtu */ 5584 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5585 if (IS_ERR(dma_conf)) { 5586 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5587 mtu); 5588 return PTR_ERR(dma_conf); 5589 } 5590 5591 stmmac_release(dev); 5592 5593 ret = __stmmac_open(dev, dma_conf); 5594 kfree(dma_conf); 5595 if (ret) { 5596 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5597 return ret; 5598 } 5599 5600 stmmac_set_rx_mode(dev); 5601 } 5602 5603 dev->mtu = mtu; 5604 netdev_update_features(dev); 5605 5606 return 0; 5607 } 5608 5609 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5610 netdev_features_t features) 5611 { 5612 struct stmmac_priv *priv = netdev_priv(dev); 5613 5614 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5615 features &= ~NETIF_F_RXCSUM; 5616 5617 if (!priv->plat->tx_coe) 5618 features &= ~NETIF_F_CSUM_MASK; 5619 5620 /* Some GMAC devices have a bugged Jumbo frame support that 5621 * needs to have the Tx COE disabled for oversized frames 5622 * (due to limited buffer sizes). In this case we disable 5623 * the TX csum insertion in the TDES and not use SF. 5624 */ 5625 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5626 features &= ~NETIF_F_CSUM_MASK; 5627 5628 /* Disable tso if asked by ethtool */ 5629 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5630 if (features & NETIF_F_TSO) 5631 priv->tso = true; 5632 else 5633 priv->tso = false; 5634 } 5635 5636 return features; 5637 } 5638 5639 static int stmmac_set_features(struct net_device *netdev, 5640 netdev_features_t features) 5641 { 5642 struct stmmac_priv *priv = netdev_priv(netdev); 5643 5644 /* Keep the COE Type in case of csum is supporting */ 5645 if (features & NETIF_F_RXCSUM) 5646 priv->hw->rx_csum = priv->plat->rx_coe; 5647 else 5648 priv->hw->rx_csum = 0; 5649 /* No check needed because rx_coe has been set before and it will be 5650 * fixed in case of issue. 5651 */ 5652 stmmac_rx_ipc(priv, priv->hw); 5653 5654 if (priv->sph_cap) { 5655 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5656 u32 chan; 5657 5658 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5659 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5660 } 5661 5662 return 0; 5663 } 5664 5665 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5666 { 5667 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5668 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5669 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5670 bool *hs_enable = &fpe_cfg->hs_enable; 5671 5672 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5673 return; 5674 5675 /* If LP has sent verify mPacket, LP is FPE capable */ 5676 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5677 if (*lp_state < FPE_STATE_CAPABLE) 5678 *lp_state = FPE_STATE_CAPABLE; 5679 5680 /* If user has requested FPE enable, quickly response */ 5681 if (*hs_enable) 5682 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5683 MPACKET_RESPONSE); 5684 } 5685 5686 /* If Local has sent verify mPacket, Local is FPE capable */ 5687 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5688 if (*lo_state < FPE_STATE_CAPABLE) 5689 *lo_state = FPE_STATE_CAPABLE; 5690 } 5691 5692 /* If LP has sent response mPacket, LP is entering FPE ON */ 5693 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5694 *lp_state = FPE_STATE_ENTERING_ON; 5695 5696 /* If Local has sent response mPacket, Local is entering FPE ON */ 5697 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5698 *lo_state = FPE_STATE_ENTERING_ON; 5699 5700 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5701 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5702 priv->fpe_wq) { 5703 queue_work(priv->fpe_wq, &priv->fpe_task); 5704 } 5705 } 5706 5707 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5708 { 5709 u32 rx_cnt = priv->plat->rx_queues_to_use; 5710 u32 tx_cnt = priv->plat->tx_queues_to_use; 5711 u32 queues_count; 5712 u32 queue; 5713 bool xmac; 5714 5715 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5716 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5717 5718 if (priv->irq_wake) 5719 pm_wakeup_event(priv->device, 0); 5720 5721 if (priv->dma_cap.estsel) 5722 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5723 &priv->xstats, tx_cnt); 5724 5725 if (priv->dma_cap.fpesel) { 5726 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5727 priv->dev); 5728 5729 stmmac_fpe_event_status(priv, status); 5730 } 5731 5732 /* To handle GMAC own interrupts */ 5733 if ((priv->plat->has_gmac) || xmac) { 5734 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5735 5736 if (unlikely(status)) { 5737 /* For LPI we need to save the tx status */ 5738 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5739 priv->tx_path_in_lpi_mode = true; 5740 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5741 priv->tx_path_in_lpi_mode = false; 5742 } 5743 5744 for (queue = 0; queue < queues_count; queue++) { 5745 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5746 queue); 5747 } 5748 5749 /* PCS link status */ 5750 if (priv->hw->pcs) { 5751 if (priv->xstats.pcs_link) 5752 netif_carrier_on(priv->dev); 5753 else 5754 netif_carrier_off(priv->dev); 5755 } 5756 5757 stmmac_timestamp_interrupt(priv, priv); 5758 } 5759 } 5760 5761 /** 5762 * stmmac_interrupt - main ISR 5763 * @irq: interrupt number. 5764 * @dev_id: to pass the net device pointer. 5765 * Description: this is the main driver interrupt service routine. 5766 * It can call: 5767 * o DMA service routine (to manage incoming frame reception and transmission 5768 * status) 5769 * o Core interrupts to manage: remote wake-up, management counter, LPI 5770 * interrupts. 5771 */ 5772 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5773 { 5774 struct net_device *dev = (struct net_device *)dev_id; 5775 struct stmmac_priv *priv = netdev_priv(dev); 5776 5777 /* Check if adapter is up */ 5778 if (test_bit(STMMAC_DOWN, &priv->state)) 5779 return IRQ_HANDLED; 5780 5781 /* Check if a fatal error happened */ 5782 if (stmmac_safety_feat_interrupt(priv)) 5783 return IRQ_HANDLED; 5784 5785 /* To handle Common interrupts */ 5786 stmmac_common_interrupt(priv); 5787 5788 /* To handle DMA interrupts */ 5789 stmmac_dma_interrupt(priv); 5790 5791 return IRQ_HANDLED; 5792 } 5793 5794 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5795 { 5796 struct net_device *dev = (struct net_device *)dev_id; 5797 struct stmmac_priv *priv = netdev_priv(dev); 5798 5799 if (unlikely(!dev)) { 5800 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5801 return IRQ_NONE; 5802 } 5803 5804 /* Check if adapter is up */ 5805 if (test_bit(STMMAC_DOWN, &priv->state)) 5806 return IRQ_HANDLED; 5807 5808 /* To handle Common interrupts */ 5809 stmmac_common_interrupt(priv); 5810 5811 return IRQ_HANDLED; 5812 } 5813 5814 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5815 { 5816 struct net_device *dev = (struct net_device *)dev_id; 5817 struct stmmac_priv *priv = netdev_priv(dev); 5818 5819 if (unlikely(!dev)) { 5820 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5821 return IRQ_NONE; 5822 } 5823 5824 /* Check if adapter is up */ 5825 if (test_bit(STMMAC_DOWN, &priv->state)) 5826 return IRQ_HANDLED; 5827 5828 /* Check if a fatal error happened */ 5829 stmmac_safety_feat_interrupt(priv); 5830 5831 return IRQ_HANDLED; 5832 } 5833 5834 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5835 { 5836 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5837 struct stmmac_dma_conf *dma_conf; 5838 int chan = tx_q->queue_index; 5839 struct stmmac_priv *priv; 5840 int status; 5841 5842 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5843 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5844 5845 if (unlikely(!data)) { 5846 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5847 return IRQ_NONE; 5848 } 5849 5850 /* Check if adapter is up */ 5851 if (test_bit(STMMAC_DOWN, &priv->state)) 5852 return IRQ_HANDLED; 5853 5854 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5855 5856 if (unlikely(status & tx_hard_error_bump_tc)) { 5857 /* Try to bump up the dma threshold on this failure */ 5858 stmmac_bump_dma_threshold(priv, chan); 5859 } else if (unlikely(status == tx_hard_error)) { 5860 stmmac_tx_err(priv, chan); 5861 } 5862 5863 return IRQ_HANDLED; 5864 } 5865 5866 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5867 { 5868 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5869 struct stmmac_dma_conf *dma_conf; 5870 int chan = rx_q->queue_index; 5871 struct stmmac_priv *priv; 5872 5873 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5874 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5875 5876 if (unlikely(!data)) { 5877 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5878 return IRQ_NONE; 5879 } 5880 5881 /* Check if adapter is up */ 5882 if (test_bit(STMMAC_DOWN, &priv->state)) 5883 return IRQ_HANDLED; 5884 5885 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5886 5887 return IRQ_HANDLED; 5888 } 5889 5890 #ifdef CONFIG_NET_POLL_CONTROLLER 5891 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5892 * to allow network I/O with interrupts disabled. 5893 */ 5894 static void stmmac_poll_controller(struct net_device *dev) 5895 { 5896 struct stmmac_priv *priv = netdev_priv(dev); 5897 int i; 5898 5899 /* If adapter is down, do nothing */ 5900 if (test_bit(STMMAC_DOWN, &priv->state)) 5901 return; 5902 5903 if (priv->plat->multi_msi_en) { 5904 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5905 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5906 5907 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5908 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5909 } else { 5910 disable_irq(dev->irq); 5911 stmmac_interrupt(dev->irq, dev); 5912 enable_irq(dev->irq); 5913 } 5914 } 5915 #endif 5916 5917 /** 5918 * stmmac_ioctl - Entry point for the Ioctl 5919 * @dev: Device pointer. 5920 * @rq: An IOCTL specefic structure, that can contain a pointer to 5921 * a proprietary structure used to pass information to the driver. 5922 * @cmd: IOCTL command 5923 * Description: 5924 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5925 */ 5926 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5927 { 5928 struct stmmac_priv *priv = netdev_priv (dev); 5929 int ret = -EOPNOTSUPP; 5930 5931 if (!netif_running(dev)) 5932 return -EINVAL; 5933 5934 switch (cmd) { 5935 case SIOCGMIIPHY: 5936 case SIOCGMIIREG: 5937 case SIOCSMIIREG: 5938 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5939 break; 5940 case SIOCSHWTSTAMP: 5941 ret = stmmac_hwtstamp_set(dev, rq); 5942 break; 5943 case SIOCGHWTSTAMP: 5944 ret = stmmac_hwtstamp_get(dev, rq); 5945 break; 5946 default: 5947 break; 5948 } 5949 5950 return ret; 5951 } 5952 5953 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5954 void *cb_priv) 5955 { 5956 struct stmmac_priv *priv = cb_priv; 5957 int ret = -EOPNOTSUPP; 5958 5959 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5960 return ret; 5961 5962 __stmmac_disable_all_queues(priv); 5963 5964 switch (type) { 5965 case TC_SETUP_CLSU32: 5966 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5967 break; 5968 case TC_SETUP_CLSFLOWER: 5969 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5970 break; 5971 default: 5972 break; 5973 } 5974 5975 stmmac_enable_all_queues(priv); 5976 return ret; 5977 } 5978 5979 static LIST_HEAD(stmmac_block_cb_list); 5980 5981 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5982 void *type_data) 5983 { 5984 struct stmmac_priv *priv = netdev_priv(ndev); 5985 5986 switch (type) { 5987 case TC_SETUP_BLOCK: 5988 return flow_block_cb_setup_simple(type_data, 5989 &stmmac_block_cb_list, 5990 stmmac_setup_tc_block_cb, 5991 priv, priv, true); 5992 case TC_SETUP_QDISC_CBS: 5993 return stmmac_tc_setup_cbs(priv, priv, type_data); 5994 case TC_SETUP_QDISC_TAPRIO: 5995 return stmmac_tc_setup_taprio(priv, priv, type_data); 5996 case TC_SETUP_QDISC_ETF: 5997 return stmmac_tc_setup_etf(priv, priv, type_data); 5998 default: 5999 return -EOPNOTSUPP; 6000 } 6001 } 6002 6003 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6004 struct net_device *sb_dev) 6005 { 6006 int gso = skb_shinfo(skb)->gso_type; 6007 6008 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6009 /* 6010 * There is no way to determine the number of TSO/USO 6011 * capable Queues. Let's use always the Queue 0 6012 * because if TSO/USO is supported then at least this 6013 * one will be capable. 6014 */ 6015 return 0; 6016 } 6017 6018 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6019 } 6020 6021 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6022 { 6023 struct stmmac_priv *priv = netdev_priv(ndev); 6024 int ret = 0; 6025 6026 ret = pm_runtime_resume_and_get(priv->device); 6027 if (ret < 0) 6028 return ret; 6029 6030 ret = eth_mac_addr(ndev, addr); 6031 if (ret) 6032 goto set_mac_error; 6033 6034 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6035 6036 set_mac_error: 6037 pm_runtime_put(priv->device); 6038 6039 return ret; 6040 } 6041 6042 #ifdef CONFIG_DEBUG_FS 6043 static struct dentry *stmmac_fs_dir; 6044 6045 static void sysfs_display_ring(void *head, int size, int extend_desc, 6046 struct seq_file *seq, dma_addr_t dma_phy_addr) 6047 { 6048 int i; 6049 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6050 struct dma_desc *p = (struct dma_desc *)head; 6051 dma_addr_t dma_addr; 6052 6053 for (i = 0; i < size; i++) { 6054 if (extend_desc) { 6055 dma_addr = dma_phy_addr + i * sizeof(*ep); 6056 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6057 i, &dma_addr, 6058 le32_to_cpu(ep->basic.des0), 6059 le32_to_cpu(ep->basic.des1), 6060 le32_to_cpu(ep->basic.des2), 6061 le32_to_cpu(ep->basic.des3)); 6062 ep++; 6063 } else { 6064 dma_addr = dma_phy_addr + i * sizeof(*p); 6065 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6066 i, &dma_addr, 6067 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6068 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6069 p++; 6070 } 6071 seq_printf(seq, "\n"); 6072 } 6073 } 6074 6075 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6076 { 6077 struct net_device *dev = seq->private; 6078 struct stmmac_priv *priv = netdev_priv(dev); 6079 u32 rx_count = priv->plat->rx_queues_to_use; 6080 u32 tx_count = priv->plat->tx_queues_to_use; 6081 u32 queue; 6082 6083 if ((dev->flags & IFF_UP) == 0) 6084 return 0; 6085 6086 for (queue = 0; queue < rx_count; queue++) { 6087 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6088 6089 seq_printf(seq, "RX Queue %d:\n", queue); 6090 6091 if (priv->extend_desc) { 6092 seq_printf(seq, "Extended descriptor ring:\n"); 6093 sysfs_display_ring((void *)rx_q->dma_erx, 6094 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6095 } else { 6096 seq_printf(seq, "Descriptor ring:\n"); 6097 sysfs_display_ring((void *)rx_q->dma_rx, 6098 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6099 } 6100 } 6101 6102 for (queue = 0; queue < tx_count; queue++) { 6103 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6104 6105 seq_printf(seq, "TX Queue %d:\n", queue); 6106 6107 if (priv->extend_desc) { 6108 seq_printf(seq, "Extended descriptor ring:\n"); 6109 sysfs_display_ring((void *)tx_q->dma_etx, 6110 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6111 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6112 seq_printf(seq, "Descriptor ring:\n"); 6113 sysfs_display_ring((void *)tx_q->dma_tx, 6114 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6115 } 6116 } 6117 6118 return 0; 6119 } 6120 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6121 6122 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6123 { 6124 struct net_device *dev = seq->private; 6125 struct stmmac_priv *priv = netdev_priv(dev); 6126 6127 if (!priv->hw_cap_support) { 6128 seq_printf(seq, "DMA HW features not supported\n"); 6129 return 0; 6130 } 6131 6132 seq_printf(seq, "==============================\n"); 6133 seq_printf(seq, "\tDMA HW features\n"); 6134 seq_printf(seq, "==============================\n"); 6135 6136 seq_printf(seq, "\t10/100 Mbps: %s\n", 6137 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6138 seq_printf(seq, "\t1000 Mbps: %s\n", 6139 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6140 seq_printf(seq, "\tHalf duplex: %s\n", 6141 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6142 seq_printf(seq, "\tHash Filter: %s\n", 6143 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6144 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6145 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6146 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6147 (priv->dma_cap.pcs) ? "Y" : "N"); 6148 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6149 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6150 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6151 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6152 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6153 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6154 seq_printf(seq, "\tRMON module: %s\n", 6155 (priv->dma_cap.rmon) ? "Y" : "N"); 6156 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6157 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6158 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6159 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6160 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6161 (priv->dma_cap.eee) ? "Y" : "N"); 6162 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6163 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6164 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6165 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6166 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6167 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6168 } else { 6169 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6170 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6171 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6172 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6173 } 6174 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6175 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6176 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6177 priv->dma_cap.number_rx_channel); 6178 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6179 priv->dma_cap.number_tx_channel); 6180 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6181 priv->dma_cap.number_rx_queues); 6182 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6183 priv->dma_cap.number_tx_queues); 6184 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6185 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6186 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6187 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6188 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6189 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6190 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6191 priv->dma_cap.pps_out_num); 6192 seq_printf(seq, "\tSafety Features: %s\n", 6193 priv->dma_cap.asp ? "Y" : "N"); 6194 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6195 priv->dma_cap.frpsel ? "Y" : "N"); 6196 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6197 priv->dma_cap.addr64); 6198 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6199 priv->dma_cap.rssen ? "Y" : "N"); 6200 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6201 priv->dma_cap.vlhash ? "Y" : "N"); 6202 seq_printf(seq, "\tSplit Header: %s\n", 6203 priv->dma_cap.sphen ? "Y" : "N"); 6204 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6205 priv->dma_cap.vlins ? "Y" : "N"); 6206 seq_printf(seq, "\tDouble VLAN: %s\n", 6207 priv->dma_cap.dvlan ? "Y" : "N"); 6208 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6209 priv->dma_cap.l3l4fnum); 6210 seq_printf(seq, "\tARP Offloading: %s\n", 6211 priv->dma_cap.arpoffsel ? "Y" : "N"); 6212 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6213 priv->dma_cap.estsel ? "Y" : "N"); 6214 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6215 priv->dma_cap.fpesel ? "Y" : "N"); 6216 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6217 priv->dma_cap.tbssel ? "Y" : "N"); 6218 return 0; 6219 } 6220 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6221 6222 /* Use network device events to rename debugfs file entries. 6223 */ 6224 static int stmmac_device_event(struct notifier_block *unused, 6225 unsigned long event, void *ptr) 6226 { 6227 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6228 struct stmmac_priv *priv = netdev_priv(dev); 6229 6230 if (dev->netdev_ops != &stmmac_netdev_ops) 6231 goto done; 6232 6233 switch (event) { 6234 case NETDEV_CHANGENAME: 6235 if (priv->dbgfs_dir) 6236 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6237 priv->dbgfs_dir, 6238 stmmac_fs_dir, 6239 dev->name); 6240 break; 6241 } 6242 done: 6243 return NOTIFY_DONE; 6244 } 6245 6246 static struct notifier_block stmmac_notifier = { 6247 .notifier_call = stmmac_device_event, 6248 }; 6249 6250 static void stmmac_init_fs(struct net_device *dev) 6251 { 6252 struct stmmac_priv *priv = netdev_priv(dev); 6253 6254 rtnl_lock(); 6255 6256 /* Create per netdev entries */ 6257 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6258 6259 /* Entry to report DMA RX/TX rings */ 6260 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6261 &stmmac_rings_status_fops); 6262 6263 /* Entry to report the DMA HW features */ 6264 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6265 &stmmac_dma_cap_fops); 6266 6267 rtnl_unlock(); 6268 } 6269 6270 static void stmmac_exit_fs(struct net_device *dev) 6271 { 6272 struct stmmac_priv *priv = netdev_priv(dev); 6273 6274 debugfs_remove_recursive(priv->dbgfs_dir); 6275 } 6276 #endif /* CONFIG_DEBUG_FS */ 6277 6278 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6279 { 6280 unsigned char *data = (unsigned char *)&vid_le; 6281 unsigned char data_byte = 0; 6282 u32 crc = ~0x0; 6283 u32 temp = 0; 6284 int i, bits; 6285 6286 bits = get_bitmask_order(VLAN_VID_MASK); 6287 for (i = 0; i < bits; i++) { 6288 if ((i % 8) == 0) 6289 data_byte = data[i / 8]; 6290 6291 temp = ((crc & 1) ^ data_byte) & 1; 6292 crc >>= 1; 6293 data_byte >>= 1; 6294 6295 if (temp) 6296 crc ^= 0xedb88320; 6297 } 6298 6299 return crc; 6300 } 6301 6302 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6303 { 6304 u32 crc, hash = 0; 6305 __le16 pmatch = 0; 6306 int count = 0; 6307 u16 vid = 0; 6308 6309 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6310 __le16 vid_le = cpu_to_le16(vid); 6311 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6312 hash |= (1 << crc); 6313 count++; 6314 } 6315 6316 if (!priv->dma_cap.vlhash) { 6317 if (count > 2) /* VID = 0 always passes filter */ 6318 return -EOPNOTSUPP; 6319 6320 pmatch = cpu_to_le16(vid); 6321 hash = 0; 6322 } 6323 6324 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6325 } 6326 6327 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6328 { 6329 struct stmmac_priv *priv = netdev_priv(ndev); 6330 bool is_double = false; 6331 int ret; 6332 6333 if (be16_to_cpu(proto) == ETH_P_8021AD) 6334 is_double = true; 6335 6336 set_bit(vid, priv->active_vlans); 6337 ret = stmmac_vlan_update(priv, is_double); 6338 if (ret) { 6339 clear_bit(vid, priv->active_vlans); 6340 return ret; 6341 } 6342 6343 if (priv->hw->num_vlan) { 6344 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6345 if (ret) 6346 return ret; 6347 } 6348 6349 return 0; 6350 } 6351 6352 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6353 { 6354 struct stmmac_priv *priv = netdev_priv(ndev); 6355 bool is_double = false; 6356 int ret; 6357 6358 ret = pm_runtime_resume_and_get(priv->device); 6359 if (ret < 0) 6360 return ret; 6361 6362 if (be16_to_cpu(proto) == ETH_P_8021AD) 6363 is_double = true; 6364 6365 clear_bit(vid, priv->active_vlans); 6366 6367 if (priv->hw->num_vlan) { 6368 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6369 if (ret) 6370 goto del_vlan_error; 6371 } 6372 6373 ret = stmmac_vlan_update(priv, is_double); 6374 6375 del_vlan_error: 6376 pm_runtime_put(priv->device); 6377 6378 return ret; 6379 } 6380 6381 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6382 { 6383 struct stmmac_priv *priv = netdev_priv(dev); 6384 6385 switch (bpf->command) { 6386 case XDP_SETUP_PROG: 6387 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6388 case XDP_SETUP_XSK_POOL: 6389 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6390 bpf->xsk.queue_id); 6391 default: 6392 return -EOPNOTSUPP; 6393 } 6394 } 6395 6396 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6397 struct xdp_frame **frames, u32 flags) 6398 { 6399 struct stmmac_priv *priv = netdev_priv(dev); 6400 int cpu = smp_processor_id(); 6401 struct netdev_queue *nq; 6402 int i, nxmit = 0; 6403 int queue; 6404 6405 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6406 return -ENETDOWN; 6407 6408 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6409 return -EINVAL; 6410 6411 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6412 nq = netdev_get_tx_queue(priv->dev, queue); 6413 6414 __netif_tx_lock(nq, cpu); 6415 /* Avoids TX time-out as we are sharing with slow path */ 6416 txq_trans_cond_update(nq); 6417 6418 for (i = 0; i < num_frames; i++) { 6419 int res; 6420 6421 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6422 if (res == STMMAC_XDP_CONSUMED) 6423 break; 6424 6425 nxmit++; 6426 } 6427 6428 if (flags & XDP_XMIT_FLUSH) { 6429 stmmac_flush_tx_descriptors(priv, queue); 6430 stmmac_tx_timer_arm(priv, queue); 6431 } 6432 6433 __netif_tx_unlock(nq); 6434 6435 return nxmit; 6436 } 6437 6438 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6439 { 6440 struct stmmac_channel *ch = &priv->channel[queue]; 6441 unsigned long flags; 6442 6443 spin_lock_irqsave(&ch->lock, flags); 6444 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6445 spin_unlock_irqrestore(&ch->lock, flags); 6446 6447 stmmac_stop_rx_dma(priv, queue); 6448 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6449 } 6450 6451 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6452 { 6453 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6454 struct stmmac_channel *ch = &priv->channel[queue]; 6455 unsigned long flags; 6456 u32 buf_size; 6457 int ret; 6458 6459 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6460 if (ret) { 6461 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6462 return; 6463 } 6464 6465 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6466 if (ret) { 6467 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6468 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6469 return; 6470 } 6471 6472 stmmac_reset_rx_queue(priv, queue); 6473 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6474 6475 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6476 rx_q->dma_rx_phy, rx_q->queue_index); 6477 6478 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6479 sizeof(struct dma_desc)); 6480 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6481 rx_q->rx_tail_addr, rx_q->queue_index); 6482 6483 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6484 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6485 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6486 buf_size, 6487 rx_q->queue_index); 6488 } else { 6489 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6490 priv->dma_conf.dma_buf_sz, 6491 rx_q->queue_index); 6492 } 6493 6494 stmmac_start_rx_dma(priv, queue); 6495 6496 spin_lock_irqsave(&ch->lock, flags); 6497 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6498 spin_unlock_irqrestore(&ch->lock, flags); 6499 } 6500 6501 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6502 { 6503 struct stmmac_channel *ch = &priv->channel[queue]; 6504 unsigned long flags; 6505 6506 spin_lock_irqsave(&ch->lock, flags); 6507 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6508 spin_unlock_irqrestore(&ch->lock, flags); 6509 6510 stmmac_stop_tx_dma(priv, queue); 6511 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6512 } 6513 6514 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6515 { 6516 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6517 struct stmmac_channel *ch = &priv->channel[queue]; 6518 unsigned long flags; 6519 int ret; 6520 6521 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6522 if (ret) { 6523 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6524 return; 6525 } 6526 6527 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6528 if (ret) { 6529 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6530 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6531 return; 6532 } 6533 6534 stmmac_reset_tx_queue(priv, queue); 6535 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6536 6537 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6538 tx_q->dma_tx_phy, tx_q->queue_index); 6539 6540 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6541 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6542 6543 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6544 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6545 tx_q->tx_tail_addr, tx_q->queue_index); 6546 6547 stmmac_start_tx_dma(priv, queue); 6548 6549 spin_lock_irqsave(&ch->lock, flags); 6550 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6551 spin_unlock_irqrestore(&ch->lock, flags); 6552 } 6553 6554 void stmmac_xdp_release(struct net_device *dev) 6555 { 6556 struct stmmac_priv *priv = netdev_priv(dev); 6557 u32 chan; 6558 6559 /* Ensure tx function is not running */ 6560 netif_tx_disable(dev); 6561 6562 /* Disable NAPI process */ 6563 stmmac_disable_all_queues(priv); 6564 6565 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6566 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6567 6568 /* Free the IRQ lines */ 6569 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6570 6571 /* Stop TX/RX DMA channels */ 6572 stmmac_stop_all_dma(priv); 6573 6574 /* Release and free the Rx/Tx resources */ 6575 free_dma_desc_resources(priv, &priv->dma_conf); 6576 6577 /* Disable the MAC Rx/Tx */ 6578 stmmac_mac_set(priv, priv->ioaddr, false); 6579 6580 /* set trans_start so we don't get spurious 6581 * watchdogs during reset 6582 */ 6583 netif_trans_update(dev); 6584 netif_carrier_off(dev); 6585 } 6586 6587 int stmmac_xdp_open(struct net_device *dev) 6588 { 6589 struct stmmac_priv *priv = netdev_priv(dev); 6590 u32 rx_cnt = priv->plat->rx_queues_to_use; 6591 u32 tx_cnt = priv->plat->tx_queues_to_use; 6592 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6593 struct stmmac_rx_queue *rx_q; 6594 struct stmmac_tx_queue *tx_q; 6595 u32 buf_size; 6596 bool sph_en; 6597 u32 chan; 6598 int ret; 6599 6600 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6601 if (ret < 0) { 6602 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6603 __func__); 6604 goto dma_desc_error; 6605 } 6606 6607 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6608 if (ret < 0) { 6609 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6610 __func__); 6611 goto init_error; 6612 } 6613 6614 /* DMA CSR Channel configuration */ 6615 for (chan = 0; chan < dma_csr_ch; chan++) { 6616 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6617 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6618 } 6619 6620 /* Adjust Split header */ 6621 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6622 6623 /* DMA RX Channel Configuration */ 6624 for (chan = 0; chan < rx_cnt; chan++) { 6625 rx_q = &priv->dma_conf.rx_queue[chan]; 6626 6627 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6628 rx_q->dma_rx_phy, chan); 6629 6630 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6631 (rx_q->buf_alloc_num * 6632 sizeof(struct dma_desc)); 6633 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6634 rx_q->rx_tail_addr, chan); 6635 6636 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6637 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6638 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6639 buf_size, 6640 rx_q->queue_index); 6641 } else { 6642 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6643 priv->dma_conf.dma_buf_sz, 6644 rx_q->queue_index); 6645 } 6646 6647 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6648 } 6649 6650 /* DMA TX Channel Configuration */ 6651 for (chan = 0; chan < tx_cnt; chan++) { 6652 tx_q = &priv->dma_conf.tx_queue[chan]; 6653 6654 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6655 tx_q->dma_tx_phy, chan); 6656 6657 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6658 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6659 tx_q->tx_tail_addr, chan); 6660 6661 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6662 tx_q->txtimer.function = stmmac_tx_timer; 6663 } 6664 6665 /* Enable the MAC Rx/Tx */ 6666 stmmac_mac_set(priv, priv->ioaddr, true); 6667 6668 /* Start Rx & Tx DMA Channels */ 6669 stmmac_start_all_dma(priv); 6670 6671 ret = stmmac_request_irq(dev); 6672 if (ret) 6673 goto irq_error; 6674 6675 /* Enable NAPI process*/ 6676 stmmac_enable_all_queues(priv); 6677 netif_carrier_on(dev); 6678 netif_tx_start_all_queues(dev); 6679 stmmac_enable_all_dma_irq(priv); 6680 6681 return 0; 6682 6683 irq_error: 6684 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6685 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6686 6687 stmmac_hw_teardown(dev); 6688 init_error: 6689 free_dma_desc_resources(priv, &priv->dma_conf); 6690 dma_desc_error: 6691 return ret; 6692 } 6693 6694 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6695 { 6696 struct stmmac_priv *priv = netdev_priv(dev); 6697 struct stmmac_rx_queue *rx_q; 6698 struct stmmac_tx_queue *tx_q; 6699 struct stmmac_channel *ch; 6700 6701 if (test_bit(STMMAC_DOWN, &priv->state) || 6702 !netif_carrier_ok(priv->dev)) 6703 return -ENETDOWN; 6704 6705 if (!stmmac_xdp_is_enabled(priv)) 6706 return -EINVAL; 6707 6708 if (queue >= priv->plat->rx_queues_to_use || 6709 queue >= priv->plat->tx_queues_to_use) 6710 return -EINVAL; 6711 6712 rx_q = &priv->dma_conf.rx_queue[queue]; 6713 tx_q = &priv->dma_conf.tx_queue[queue]; 6714 ch = &priv->channel[queue]; 6715 6716 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6717 return -EINVAL; 6718 6719 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6720 /* EQoS does not have per-DMA channel SW interrupt, 6721 * so we schedule RX Napi straight-away. 6722 */ 6723 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6724 __napi_schedule(&ch->rxtx_napi); 6725 } 6726 6727 return 0; 6728 } 6729 6730 static const struct net_device_ops stmmac_netdev_ops = { 6731 .ndo_open = stmmac_open, 6732 .ndo_start_xmit = stmmac_xmit, 6733 .ndo_stop = stmmac_release, 6734 .ndo_change_mtu = stmmac_change_mtu, 6735 .ndo_fix_features = stmmac_fix_features, 6736 .ndo_set_features = stmmac_set_features, 6737 .ndo_set_rx_mode = stmmac_set_rx_mode, 6738 .ndo_tx_timeout = stmmac_tx_timeout, 6739 .ndo_eth_ioctl = stmmac_ioctl, 6740 .ndo_setup_tc = stmmac_setup_tc, 6741 .ndo_select_queue = stmmac_select_queue, 6742 #ifdef CONFIG_NET_POLL_CONTROLLER 6743 .ndo_poll_controller = stmmac_poll_controller, 6744 #endif 6745 .ndo_set_mac_address = stmmac_set_mac_address, 6746 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6747 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6748 .ndo_bpf = stmmac_bpf, 6749 .ndo_xdp_xmit = stmmac_xdp_xmit, 6750 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6751 }; 6752 6753 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6754 { 6755 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6756 return; 6757 if (test_bit(STMMAC_DOWN, &priv->state)) 6758 return; 6759 6760 netdev_err(priv->dev, "Reset adapter.\n"); 6761 6762 rtnl_lock(); 6763 netif_trans_update(priv->dev); 6764 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6765 usleep_range(1000, 2000); 6766 6767 set_bit(STMMAC_DOWN, &priv->state); 6768 dev_close(priv->dev); 6769 dev_open(priv->dev, NULL); 6770 clear_bit(STMMAC_DOWN, &priv->state); 6771 clear_bit(STMMAC_RESETING, &priv->state); 6772 rtnl_unlock(); 6773 } 6774 6775 static void stmmac_service_task(struct work_struct *work) 6776 { 6777 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6778 service_task); 6779 6780 stmmac_reset_subtask(priv); 6781 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6782 } 6783 6784 /** 6785 * stmmac_hw_init - Init the MAC device 6786 * @priv: driver private structure 6787 * Description: this function is to configure the MAC device according to 6788 * some platform parameters or the HW capability register. It prepares the 6789 * driver to use either ring or chain modes and to setup either enhanced or 6790 * normal descriptors. 6791 */ 6792 static int stmmac_hw_init(struct stmmac_priv *priv) 6793 { 6794 int ret; 6795 6796 /* dwmac-sun8i only work in chain mode */ 6797 if (priv->plat->has_sun8i) 6798 chain_mode = 1; 6799 priv->chain_mode = chain_mode; 6800 6801 /* Initialize HW Interface */ 6802 ret = stmmac_hwif_init(priv); 6803 if (ret) 6804 return ret; 6805 6806 /* Get the HW capability (new GMAC newer than 3.50a) */ 6807 priv->hw_cap_support = stmmac_get_hw_features(priv); 6808 if (priv->hw_cap_support) { 6809 dev_info(priv->device, "DMA HW capability register supported\n"); 6810 6811 /* We can override some gmac/dma configuration fields: e.g. 6812 * enh_desc, tx_coe (e.g. that are passed through the 6813 * platform) with the values from the HW capability 6814 * register (if supported). 6815 */ 6816 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6817 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6818 !priv->plat->use_phy_wol; 6819 priv->hw->pmt = priv->plat->pmt; 6820 if (priv->dma_cap.hash_tb_sz) { 6821 priv->hw->multicast_filter_bins = 6822 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6823 priv->hw->mcast_bits_log2 = 6824 ilog2(priv->hw->multicast_filter_bins); 6825 } 6826 6827 /* TXCOE doesn't work in thresh DMA mode */ 6828 if (priv->plat->force_thresh_dma_mode) 6829 priv->plat->tx_coe = 0; 6830 else 6831 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6832 6833 /* In case of GMAC4 rx_coe is from HW cap register. */ 6834 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6835 6836 if (priv->dma_cap.rx_coe_type2) 6837 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6838 else if (priv->dma_cap.rx_coe_type1) 6839 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6840 6841 } else { 6842 dev_info(priv->device, "No HW DMA feature register supported\n"); 6843 } 6844 6845 if (priv->plat->rx_coe) { 6846 priv->hw->rx_csum = priv->plat->rx_coe; 6847 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6848 if (priv->synopsys_id < DWMAC_CORE_4_00) 6849 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6850 } 6851 if (priv->plat->tx_coe) 6852 dev_info(priv->device, "TX Checksum insertion supported\n"); 6853 6854 if (priv->plat->pmt) { 6855 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6856 device_set_wakeup_capable(priv->device, 1); 6857 } 6858 6859 if (priv->dma_cap.tsoen) 6860 dev_info(priv->device, "TSO supported\n"); 6861 6862 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6863 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6864 6865 /* Run HW quirks, if any */ 6866 if (priv->hwif_quirks) { 6867 ret = priv->hwif_quirks(priv); 6868 if (ret) 6869 return ret; 6870 } 6871 6872 /* Rx Watchdog is available in the COREs newer than the 3.40. 6873 * In some case, for example on bugged HW this feature 6874 * has to be disable and this can be done by passing the 6875 * riwt_off field from the platform. 6876 */ 6877 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6878 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6879 priv->use_riwt = 1; 6880 dev_info(priv->device, 6881 "Enable RX Mitigation via HW Watchdog Timer\n"); 6882 } 6883 6884 return 0; 6885 } 6886 6887 static void stmmac_napi_add(struct net_device *dev) 6888 { 6889 struct stmmac_priv *priv = netdev_priv(dev); 6890 u32 queue, maxq; 6891 6892 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6893 6894 for (queue = 0; queue < maxq; queue++) { 6895 struct stmmac_channel *ch = &priv->channel[queue]; 6896 6897 ch->priv_data = priv; 6898 ch->index = queue; 6899 spin_lock_init(&ch->lock); 6900 6901 if (queue < priv->plat->rx_queues_to_use) { 6902 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6903 } 6904 if (queue < priv->plat->tx_queues_to_use) { 6905 netif_napi_add_tx(dev, &ch->tx_napi, 6906 stmmac_napi_poll_tx); 6907 } 6908 if (queue < priv->plat->rx_queues_to_use && 6909 queue < priv->plat->tx_queues_to_use) { 6910 netif_napi_add(dev, &ch->rxtx_napi, 6911 stmmac_napi_poll_rxtx); 6912 } 6913 } 6914 } 6915 6916 static void stmmac_napi_del(struct net_device *dev) 6917 { 6918 struct stmmac_priv *priv = netdev_priv(dev); 6919 u32 queue, maxq; 6920 6921 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6922 6923 for (queue = 0; queue < maxq; queue++) { 6924 struct stmmac_channel *ch = &priv->channel[queue]; 6925 6926 if (queue < priv->plat->rx_queues_to_use) 6927 netif_napi_del(&ch->rx_napi); 6928 if (queue < priv->plat->tx_queues_to_use) 6929 netif_napi_del(&ch->tx_napi); 6930 if (queue < priv->plat->rx_queues_to_use && 6931 queue < priv->plat->tx_queues_to_use) { 6932 netif_napi_del(&ch->rxtx_napi); 6933 } 6934 } 6935 } 6936 6937 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6938 { 6939 struct stmmac_priv *priv = netdev_priv(dev); 6940 int ret = 0; 6941 6942 if (netif_running(dev)) 6943 stmmac_release(dev); 6944 6945 stmmac_napi_del(dev); 6946 6947 priv->plat->rx_queues_to_use = rx_cnt; 6948 priv->plat->tx_queues_to_use = tx_cnt; 6949 6950 stmmac_napi_add(dev); 6951 6952 if (netif_running(dev)) 6953 ret = stmmac_open(dev); 6954 6955 return ret; 6956 } 6957 6958 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6959 { 6960 struct stmmac_priv *priv = netdev_priv(dev); 6961 int ret = 0; 6962 6963 if (netif_running(dev)) 6964 stmmac_release(dev); 6965 6966 priv->dma_conf.dma_rx_size = rx_size; 6967 priv->dma_conf.dma_tx_size = tx_size; 6968 6969 if (netif_running(dev)) 6970 ret = stmmac_open(dev); 6971 6972 return ret; 6973 } 6974 6975 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6976 static void stmmac_fpe_lp_task(struct work_struct *work) 6977 { 6978 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6979 fpe_task); 6980 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6981 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6982 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6983 bool *hs_enable = &fpe_cfg->hs_enable; 6984 bool *enable = &fpe_cfg->enable; 6985 int retries = 20; 6986 6987 while (retries-- > 0) { 6988 /* Bail out immediately if FPE handshake is OFF */ 6989 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6990 break; 6991 6992 if (*lo_state == FPE_STATE_ENTERING_ON && 6993 *lp_state == FPE_STATE_ENTERING_ON) { 6994 stmmac_fpe_configure(priv, priv->ioaddr, 6995 priv->plat->tx_queues_to_use, 6996 priv->plat->rx_queues_to_use, 6997 *enable); 6998 6999 netdev_info(priv->dev, "configured FPE\n"); 7000 7001 *lo_state = FPE_STATE_ON; 7002 *lp_state = FPE_STATE_ON; 7003 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7004 break; 7005 } 7006 7007 if ((*lo_state == FPE_STATE_CAPABLE || 7008 *lo_state == FPE_STATE_ENTERING_ON) && 7009 *lp_state != FPE_STATE_ON) { 7010 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7011 *lo_state, *lp_state); 7012 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7013 MPACKET_VERIFY); 7014 } 7015 /* Sleep then retry */ 7016 msleep(500); 7017 } 7018 7019 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7020 } 7021 7022 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7023 { 7024 if (priv->plat->fpe_cfg->hs_enable != enable) { 7025 if (enable) { 7026 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7027 MPACKET_VERIFY); 7028 } else { 7029 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7030 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7031 } 7032 7033 priv->plat->fpe_cfg->hs_enable = enable; 7034 } 7035 } 7036 7037 /** 7038 * stmmac_dvr_probe 7039 * @device: device pointer 7040 * @plat_dat: platform data pointer 7041 * @res: stmmac resource pointer 7042 * Description: this is the main probe function used to 7043 * call the alloc_etherdev, allocate the priv structure. 7044 * Return: 7045 * returns 0 on success, otherwise errno. 7046 */ 7047 int stmmac_dvr_probe(struct device *device, 7048 struct plat_stmmacenet_data *plat_dat, 7049 struct stmmac_resources *res) 7050 { 7051 struct net_device *ndev = NULL; 7052 struct stmmac_priv *priv; 7053 u32 rxq; 7054 int i, ret = 0; 7055 7056 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7057 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7058 if (!ndev) 7059 return -ENOMEM; 7060 7061 SET_NETDEV_DEV(ndev, device); 7062 7063 priv = netdev_priv(ndev); 7064 priv->device = device; 7065 priv->dev = ndev; 7066 7067 stmmac_set_ethtool_ops(ndev); 7068 priv->pause = pause; 7069 priv->plat = plat_dat; 7070 priv->ioaddr = res->addr; 7071 priv->dev->base_addr = (unsigned long)res->addr; 7072 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7073 7074 priv->dev->irq = res->irq; 7075 priv->wol_irq = res->wol_irq; 7076 priv->lpi_irq = res->lpi_irq; 7077 priv->sfty_ce_irq = res->sfty_ce_irq; 7078 priv->sfty_ue_irq = res->sfty_ue_irq; 7079 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7080 priv->rx_irq[i] = res->rx_irq[i]; 7081 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7082 priv->tx_irq[i] = res->tx_irq[i]; 7083 7084 if (!is_zero_ether_addr(res->mac)) 7085 eth_hw_addr_set(priv->dev, res->mac); 7086 7087 dev_set_drvdata(device, priv->dev); 7088 7089 /* Verify driver arguments */ 7090 stmmac_verify_args(); 7091 7092 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7093 if (!priv->af_xdp_zc_qps) 7094 return -ENOMEM; 7095 7096 /* Allocate workqueue */ 7097 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7098 if (!priv->wq) { 7099 dev_err(priv->device, "failed to create workqueue\n"); 7100 return -ENOMEM; 7101 } 7102 7103 INIT_WORK(&priv->service_task, stmmac_service_task); 7104 7105 /* Initialize Link Partner FPE workqueue */ 7106 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7107 7108 /* Override with kernel parameters if supplied XXX CRS XXX 7109 * this needs to have multiple instances 7110 */ 7111 if ((phyaddr >= 0) && (phyaddr <= 31)) 7112 priv->plat->phy_addr = phyaddr; 7113 7114 if (priv->plat->stmmac_rst) { 7115 ret = reset_control_assert(priv->plat->stmmac_rst); 7116 reset_control_deassert(priv->plat->stmmac_rst); 7117 /* Some reset controllers have only reset callback instead of 7118 * assert + deassert callbacks pair. 7119 */ 7120 if (ret == -ENOTSUPP) 7121 reset_control_reset(priv->plat->stmmac_rst); 7122 } 7123 7124 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7125 if (ret == -ENOTSUPP) 7126 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7127 ERR_PTR(ret)); 7128 7129 /* Init MAC and get the capabilities */ 7130 ret = stmmac_hw_init(priv); 7131 if (ret) 7132 goto error_hw_init; 7133 7134 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7135 */ 7136 if (priv->synopsys_id < DWMAC_CORE_5_20) 7137 priv->plat->dma_cfg->dche = false; 7138 7139 stmmac_check_ether_addr(priv); 7140 7141 ndev->netdev_ops = &stmmac_netdev_ops; 7142 7143 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7144 NETIF_F_RXCSUM; 7145 7146 ret = stmmac_tc_init(priv, priv); 7147 if (!ret) { 7148 ndev->hw_features |= NETIF_F_HW_TC; 7149 } 7150 7151 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7152 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7153 if (priv->plat->has_gmac4) 7154 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7155 priv->tso = true; 7156 dev_info(priv->device, "TSO feature enabled\n"); 7157 } 7158 7159 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7160 ndev->hw_features |= NETIF_F_GRO; 7161 priv->sph_cap = true; 7162 priv->sph = priv->sph_cap; 7163 dev_info(priv->device, "SPH feature enabled\n"); 7164 } 7165 7166 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7167 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7168 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7169 * So overwrite dma_cap.addr64 according to HW real design. 7170 */ 7171 if (priv->plat->addr64) 7172 priv->dma_cap.addr64 = priv->plat->addr64; 7173 7174 if (priv->dma_cap.addr64) { 7175 ret = dma_set_mask_and_coherent(device, 7176 DMA_BIT_MASK(priv->dma_cap.addr64)); 7177 if (!ret) { 7178 dev_info(priv->device, "Using %d bits DMA width\n", 7179 priv->dma_cap.addr64); 7180 7181 /* 7182 * If more than 32 bits can be addressed, make sure to 7183 * enable enhanced addressing mode. 7184 */ 7185 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7186 priv->plat->dma_cfg->eame = true; 7187 } else { 7188 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7189 if (ret) { 7190 dev_err(priv->device, "Failed to set DMA Mask\n"); 7191 goto error_hw_init; 7192 } 7193 7194 priv->dma_cap.addr64 = 32; 7195 } 7196 } 7197 7198 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7199 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7200 #ifdef STMMAC_VLAN_TAG_USED 7201 /* Both mac100 and gmac support receive VLAN tag detection */ 7202 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7203 if (priv->dma_cap.vlhash) { 7204 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7205 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7206 } 7207 if (priv->dma_cap.vlins) { 7208 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7209 if (priv->dma_cap.dvlan) 7210 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7211 } 7212 #endif 7213 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7214 7215 /* Initialize RSS */ 7216 rxq = priv->plat->rx_queues_to_use; 7217 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7218 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7219 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7220 7221 if (priv->dma_cap.rssen && priv->plat->rss_en) 7222 ndev->features |= NETIF_F_RXHASH; 7223 7224 /* MTU range: 46 - hw-specific max */ 7225 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7226 if (priv->plat->has_xgmac) 7227 ndev->max_mtu = XGMAC_JUMBO_LEN; 7228 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7229 ndev->max_mtu = JUMBO_LEN; 7230 else 7231 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7232 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7233 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7234 */ 7235 if ((priv->plat->maxmtu < ndev->max_mtu) && 7236 (priv->plat->maxmtu >= ndev->min_mtu)) 7237 ndev->max_mtu = priv->plat->maxmtu; 7238 else if (priv->plat->maxmtu < ndev->min_mtu) 7239 dev_warn(priv->device, 7240 "%s: warning: maxmtu having invalid value (%d)\n", 7241 __func__, priv->plat->maxmtu); 7242 7243 if (flow_ctrl) 7244 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7245 7246 /* Setup channels NAPI */ 7247 stmmac_napi_add(ndev); 7248 7249 mutex_init(&priv->lock); 7250 7251 /* If a specific clk_csr value is passed from the platform 7252 * this means that the CSR Clock Range selection cannot be 7253 * changed at run-time and it is fixed. Viceversa the driver'll try to 7254 * set the MDC clock dynamically according to the csr actual 7255 * clock input. 7256 */ 7257 if (priv->plat->clk_csr >= 0) 7258 priv->clk_csr = priv->plat->clk_csr; 7259 else 7260 stmmac_clk_csr_set(priv); 7261 7262 stmmac_check_pcs_mode(priv); 7263 7264 pm_runtime_get_noresume(device); 7265 pm_runtime_set_active(device); 7266 if (!pm_runtime_enabled(device)) 7267 pm_runtime_enable(device); 7268 7269 if (priv->hw->pcs != STMMAC_PCS_TBI && 7270 priv->hw->pcs != STMMAC_PCS_RTBI) { 7271 /* MDIO bus Registration */ 7272 ret = stmmac_mdio_register(ndev); 7273 if (ret < 0) { 7274 dev_err_probe(priv->device, ret, 7275 "%s: MDIO bus (id: %d) registration failed\n", 7276 __func__, priv->plat->bus_id); 7277 goto error_mdio_register; 7278 } 7279 } 7280 7281 if (priv->plat->speed_mode_2500) 7282 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7283 7284 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7285 ret = stmmac_xpcs_setup(priv->mii); 7286 if (ret) 7287 goto error_xpcs_setup; 7288 } 7289 7290 ret = stmmac_phy_setup(priv); 7291 if (ret) { 7292 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7293 goto error_phy_setup; 7294 } 7295 7296 ret = register_netdev(ndev); 7297 if (ret) { 7298 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7299 __func__, ret); 7300 goto error_netdev_register; 7301 } 7302 7303 #ifdef CONFIG_DEBUG_FS 7304 stmmac_init_fs(ndev); 7305 #endif 7306 7307 if (priv->plat->dump_debug_regs) 7308 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7309 7310 /* Let pm_runtime_put() disable the clocks. 7311 * If CONFIG_PM is not enabled, the clocks will stay powered. 7312 */ 7313 pm_runtime_put(device); 7314 7315 return ret; 7316 7317 error_netdev_register: 7318 phylink_destroy(priv->phylink); 7319 error_xpcs_setup: 7320 error_phy_setup: 7321 if (priv->hw->pcs != STMMAC_PCS_TBI && 7322 priv->hw->pcs != STMMAC_PCS_RTBI) 7323 stmmac_mdio_unregister(ndev); 7324 error_mdio_register: 7325 stmmac_napi_del(ndev); 7326 error_hw_init: 7327 destroy_workqueue(priv->wq); 7328 bitmap_free(priv->af_xdp_zc_qps); 7329 7330 return ret; 7331 } 7332 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7333 7334 /** 7335 * stmmac_dvr_remove 7336 * @dev: device pointer 7337 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7338 * changes the link status, releases the DMA descriptor rings. 7339 */ 7340 int stmmac_dvr_remove(struct device *dev) 7341 { 7342 struct net_device *ndev = dev_get_drvdata(dev); 7343 struct stmmac_priv *priv = netdev_priv(ndev); 7344 7345 netdev_info(priv->dev, "%s: removing driver", __func__); 7346 7347 pm_runtime_get_sync(dev); 7348 7349 stmmac_stop_all_dma(priv); 7350 stmmac_mac_set(priv, priv->ioaddr, false); 7351 netif_carrier_off(ndev); 7352 unregister_netdev(ndev); 7353 7354 /* Serdes power down needs to happen after VLAN filter 7355 * is deleted that is triggered by unregister_netdev(). 7356 */ 7357 if (priv->plat->serdes_powerdown) 7358 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7359 7360 #ifdef CONFIG_DEBUG_FS 7361 stmmac_exit_fs(ndev); 7362 #endif 7363 phylink_destroy(priv->phylink); 7364 if (priv->plat->stmmac_rst) 7365 reset_control_assert(priv->plat->stmmac_rst); 7366 reset_control_assert(priv->plat->stmmac_ahb_rst); 7367 if (priv->hw->pcs != STMMAC_PCS_TBI && 7368 priv->hw->pcs != STMMAC_PCS_RTBI) 7369 stmmac_mdio_unregister(ndev); 7370 destroy_workqueue(priv->wq); 7371 mutex_destroy(&priv->lock); 7372 bitmap_free(priv->af_xdp_zc_qps); 7373 7374 pm_runtime_disable(dev); 7375 pm_runtime_put_noidle(dev); 7376 7377 return 0; 7378 } 7379 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7380 7381 /** 7382 * stmmac_suspend - suspend callback 7383 * @dev: device pointer 7384 * Description: this is the function to suspend the device and it is called 7385 * by the platform driver to stop the network queue, release the resources, 7386 * program the PMT register (for WoL), clean and release driver resources. 7387 */ 7388 int stmmac_suspend(struct device *dev) 7389 { 7390 struct net_device *ndev = dev_get_drvdata(dev); 7391 struct stmmac_priv *priv = netdev_priv(ndev); 7392 u32 chan; 7393 7394 if (!ndev || !netif_running(ndev)) 7395 return 0; 7396 7397 mutex_lock(&priv->lock); 7398 7399 netif_device_detach(ndev); 7400 7401 stmmac_disable_all_queues(priv); 7402 7403 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7404 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7405 7406 if (priv->eee_enabled) { 7407 priv->tx_path_in_lpi_mode = false; 7408 del_timer_sync(&priv->eee_ctrl_timer); 7409 } 7410 7411 /* Stop TX/RX DMA */ 7412 stmmac_stop_all_dma(priv); 7413 7414 if (priv->plat->serdes_powerdown) 7415 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7416 7417 /* Enable Power down mode by programming the PMT regs */ 7418 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7419 stmmac_pmt(priv, priv->hw, priv->wolopts); 7420 priv->irq_wake = 1; 7421 } else { 7422 stmmac_mac_set(priv, priv->ioaddr, false); 7423 pinctrl_pm_select_sleep_state(priv->device); 7424 } 7425 7426 mutex_unlock(&priv->lock); 7427 7428 rtnl_lock(); 7429 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7430 phylink_suspend(priv->phylink, true); 7431 } else { 7432 if (device_may_wakeup(priv->device)) 7433 phylink_speed_down(priv->phylink, false); 7434 phylink_suspend(priv->phylink, false); 7435 } 7436 rtnl_unlock(); 7437 7438 if (priv->dma_cap.fpesel) { 7439 /* Disable FPE */ 7440 stmmac_fpe_configure(priv, priv->ioaddr, 7441 priv->plat->tx_queues_to_use, 7442 priv->plat->rx_queues_to_use, false); 7443 7444 stmmac_fpe_handshake(priv, false); 7445 stmmac_fpe_stop_wq(priv); 7446 } 7447 7448 priv->speed = SPEED_UNKNOWN; 7449 return 0; 7450 } 7451 EXPORT_SYMBOL_GPL(stmmac_suspend); 7452 7453 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7454 { 7455 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7456 7457 rx_q->cur_rx = 0; 7458 rx_q->dirty_rx = 0; 7459 } 7460 7461 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7462 { 7463 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7464 7465 tx_q->cur_tx = 0; 7466 tx_q->dirty_tx = 0; 7467 tx_q->mss = 0; 7468 7469 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7470 } 7471 7472 /** 7473 * stmmac_reset_queues_param - reset queue parameters 7474 * @priv: device pointer 7475 */ 7476 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7477 { 7478 u32 rx_cnt = priv->plat->rx_queues_to_use; 7479 u32 tx_cnt = priv->plat->tx_queues_to_use; 7480 u32 queue; 7481 7482 for (queue = 0; queue < rx_cnt; queue++) 7483 stmmac_reset_rx_queue(priv, queue); 7484 7485 for (queue = 0; queue < tx_cnt; queue++) 7486 stmmac_reset_tx_queue(priv, queue); 7487 } 7488 7489 /** 7490 * stmmac_resume - resume callback 7491 * @dev: device pointer 7492 * Description: when resume this function is invoked to setup the DMA and CORE 7493 * in a usable state. 7494 */ 7495 int stmmac_resume(struct device *dev) 7496 { 7497 struct net_device *ndev = dev_get_drvdata(dev); 7498 struct stmmac_priv *priv = netdev_priv(ndev); 7499 int ret; 7500 7501 if (!netif_running(ndev)) 7502 return 0; 7503 7504 /* Power Down bit, into the PM register, is cleared 7505 * automatically as soon as a magic packet or a Wake-up frame 7506 * is received. Anyway, it's better to manually clear 7507 * this bit because it can generate problems while resuming 7508 * from another devices (e.g. serial console). 7509 */ 7510 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7511 mutex_lock(&priv->lock); 7512 stmmac_pmt(priv, priv->hw, 0); 7513 mutex_unlock(&priv->lock); 7514 priv->irq_wake = 0; 7515 } else { 7516 pinctrl_pm_select_default_state(priv->device); 7517 /* reset the phy so that it's ready */ 7518 if (priv->mii) 7519 stmmac_mdio_reset(priv->mii); 7520 } 7521 7522 if (priv->plat->serdes_powerup) { 7523 ret = priv->plat->serdes_powerup(ndev, 7524 priv->plat->bsp_priv); 7525 7526 if (ret < 0) 7527 return ret; 7528 } 7529 7530 rtnl_lock(); 7531 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7532 phylink_resume(priv->phylink); 7533 } else { 7534 phylink_resume(priv->phylink); 7535 if (device_may_wakeup(priv->device)) 7536 phylink_speed_up(priv->phylink); 7537 } 7538 rtnl_unlock(); 7539 7540 rtnl_lock(); 7541 mutex_lock(&priv->lock); 7542 7543 stmmac_reset_queues_param(priv); 7544 7545 stmmac_free_tx_skbufs(priv); 7546 stmmac_clear_descriptors(priv, &priv->dma_conf); 7547 7548 stmmac_hw_setup(ndev, false); 7549 stmmac_init_coalesce(priv); 7550 stmmac_set_rx_mode(ndev); 7551 7552 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7553 7554 stmmac_enable_all_queues(priv); 7555 stmmac_enable_all_dma_irq(priv); 7556 7557 mutex_unlock(&priv->lock); 7558 rtnl_unlock(); 7559 7560 netif_device_attach(ndev); 7561 7562 return 0; 7563 } 7564 EXPORT_SYMBOL_GPL(stmmac_resume); 7565 7566 #ifndef MODULE 7567 static int __init stmmac_cmdline_opt(char *str) 7568 { 7569 char *opt; 7570 7571 if (!str || !*str) 7572 return 1; 7573 while ((opt = strsep(&str, ",")) != NULL) { 7574 if (!strncmp(opt, "debug:", 6)) { 7575 if (kstrtoint(opt + 6, 0, &debug)) 7576 goto err; 7577 } else if (!strncmp(opt, "phyaddr:", 8)) { 7578 if (kstrtoint(opt + 8, 0, &phyaddr)) 7579 goto err; 7580 } else if (!strncmp(opt, "buf_sz:", 7)) { 7581 if (kstrtoint(opt + 7, 0, &buf_sz)) 7582 goto err; 7583 } else if (!strncmp(opt, "tc:", 3)) { 7584 if (kstrtoint(opt + 3, 0, &tc)) 7585 goto err; 7586 } else if (!strncmp(opt, "watchdog:", 9)) { 7587 if (kstrtoint(opt + 9, 0, &watchdog)) 7588 goto err; 7589 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7590 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7591 goto err; 7592 } else if (!strncmp(opt, "pause:", 6)) { 7593 if (kstrtoint(opt + 6, 0, &pause)) 7594 goto err; 7595 } else if (!strncmp(opt, "eee_timer:", 10)) { 7596 if (kstrtoint(opt + 10, 0, &eee_timer)) 7597 goto err; 7598 } else if (!strncmp(opt, "chain_mode:", 11)) { 7599 if (kstrtoint(opt + 11, 0, &chain_mode)) 7600 goto err; 7601 } 7602 } 7603 return 1; 7604 7605 err: 7606 pr_err("%s: ERROR broken module parameter conversion", __func__); 7607 return 1; 7608 } 7609 7610 __setup("stmmaceth=", stmmac_cmdline_opt); 7611 #endif /* MODULE */ 7612 7613 static int __init stmmac_init(void) 7614 { 7615 #ifdef CONFIG_DEBUG_FS 7616 /* Create debugfs main directory if it doesn't exist yet */ 7617 if (!stmmac_fs_dir) 7618 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7619 register_netdevice_notifier(&stmmac_notifier); 7620 #endif 7621 7622 return 0; 7623 } 7624 7625 static void __exit stmmac_exit(void) 7626 { 7627 #ifdef CONFIG_DEBUG_FS 7628 unregister_netdevice_notifier(&stmmac_notifier); 7629 debugfs_remove_recursive(stmmac_fs_dir); 7630 #endif 7631 } 7632 7633 module_init(stmmac_init) 7634 module_exit(stmmac_exit) 7635 7636 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7637 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7638 MODULE_LICENSE("GPL"); 7639