1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 55 56 /* Module parameters */ 57 #define TX_TIMEO 5000 58 static int watchdog = TX_TIMEO; 59 module_param(watchdog, int, 0644); 60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 61 62 static int debug = -1; 63 module_param(debug, int, 0644); 64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 65 66 static int phyaddr = -1; 67 module_param(phyaddr, int, 0444); 68 MODULE_PARM_DESC(phyaddr, "Physical device address"); 69 70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 72 73 /* Limit to make sure XDP TX and slow path can coexist */ 74 #define STMMAC_XSK_TX_BUDGET_MAX 256 75 #define STMMAC_TX_XSK_AVAIL 16 76 #define STMMAC_RX_FILL_BATCH 16 77 78 #define STMMAC_XDP_PASS 0 79 #define STMMAC_XDP_CONSUMED BIT(0) 80 #define STMMAC_XDP_TX BIT(1) 81 #define STMMAC_XDP_REDIRECT BIT(2) 82 83 static int flow_ctrl = FLOW_AUTO; 84 module_param(flow_ctrl, int, 0644); 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 86 87 static int pause = PAUSE_TIME; 88 module_param(pause, int, 0644); 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 90 91 #define TC_DEFAULT 64 92 static int tc = TC_DEFAULT; 93 module_param(tc, int, 0644); 94 MODULE_PARM_DESC(tc, "DMA threshold control value"); 95 96 #define DEFAULT_BUFSIZE 1536 97 static int buf_sz = DEFAULT_BUFSIZE; 98 module_param(buf_sz, int, 0644); 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 100 101 #define STMMAC_RX_COPYBREAK 256 102 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 104 NETIF_MSG_LINK | NETIF_MSG_IFUP | 105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 106 107 #define STMMAC_DEFAULT_LPI_TIMER 1000 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 109 module_param(eee_timer, int, 0644); 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 112 113 /* By default the driver will use the ring mode to manage tx and rx descriptors, 114 * but allow user to force to use the chain instead of the ring 115 */ 116 static unsigned int chain_mode; 117 module_param(chain_mode, int, 0444); 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 119 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 121 /* For MSI interrupts handling */ 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 128 129 #ifdef CONFIG_DEBUG_FS 130 static const struct net_device_ops stmmac_netdev_ops; 131 static void stmmac_init_fs(struct net_device *dev); 132 static void stmmac_exit_fs(struct net_device *dev); 133 #endif 134 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 136 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 138 { 139 int ret = 0; 140 141 if (enabled) { 142 ret = clk_prepare_enable(priv->plat->stmmac_clk); 143 if (ret) 144 return ret; 145 ret = clk_prepare_enable(priv->plat->pclk); 146 if (ret) { 147 clk_disable_unprepare(priv->plat->stmmac_clk); 148 return ret; 149 } 150 if (priv->plat->clks_config) { 151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 152 if (ret) { 153 clk_disable_unprepare(priv->plat->stmmac_clk); 154 clk_disable_unprepare(priv->plat->pclk); 155 return ret; 156 } 157 } 158 } else { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 clk_disable_unprepare(priv->plat->pclk); 161 if (priv->plat->clks_config) 162 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 163 } 164 165 return ret; 166 } 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 168 169 /** 170 * stmmac_verify_args - verify the driver parameters. 171 * Description: it checks the driver parameters and set a default in case of 172 * errors. 173 */ 174 static void stmmac_verify_args(void) 175 { 176 if (unlikely(watchdog < 0)) 177 watchdog = TX_TIMEO; 178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 179 buf_sz = DEFAULT_BUFSIZE; 180 if (unlikely(flow_ctrl > 1)) 181 flow_ctrl = FLOW_AUTO; 182 else if (likely(flow_ctrl < 0)) 183 flow_ctrl = FLOW_OFF; 184 if (unlikely((pause < 0) || (pause > 0xffff))) 185 pause = PAUSE_TIME; 186 if (eee_timer < 0) 187 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 188 } 189 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 191 { 192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 195 u32 queue; 196 197 for (queue = 0; queue < maxq; queue++) { 198 struct stmmac_channel *ch = &priv->channel[queue]; 199 200 if (stmmac_xdp_is_enabled(priv) && 201 test_bit(queue, priv->af_xdp_zc_qps)) { 202 napi_disable(&ch->rxtx_napi); 203 continue; 204 } 205 206 if (queue < rx_queues_cnt) 207 napi_disable(&ch->rx_napi); 208 if (queue < tx_queues_cnt) 209 napi_disable(&ch->tx_napi); 210 } 211 } 212 213 /** 214 * stmmac_disable_all_queues - Disable all queues 215 * @priv: driver private structure 216 */ 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 218 { 219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 220 struct stmmac_rx_queue *rx_q; 221 u32 queue; 222 223 /* synchronize_rcu() needed for pending XDP buffers to drain */ 224 for (queue = 0; queue < rx_queues_cnt; queue++) { 225 rx_q = &priv->rx_queue[queue]; 226 if (rx_q->xsk_pool) { 227 synchronize_rcu(); 228 break; 229 } 230 } 231 232 __stmmac_disable_all_queues(priv); 233 } 234 235 /** 236 * stmmac_enable_all_queues - Enable all queues 237 * @priv: driver private structure 238 */ 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 240 { 241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 244 u32 queue; 245 246 for (queue = 0; queue < maxq; queue++) { 247 struct stmmac_channel *ch = &priv->channel[queue]; 248 249 if (stmmac_xdp_is_enabled(priv) && 250 test_bit(queue, priv->af_xdp_zc_qps)) { 251 napi_enable(&ch->rxtx_napi); 252 continue; 253 } 254 255 if (queue < rx_queues_cnt) 256 napi_enable(&ch->rx_napi); 257 if (queue < tx_queues_cnt) 258 napi_enable(&ch->tx_napi); 259 } 260 } 261 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 263 { 264 if (!test_bit(STMMAC_DOWN, &priv->state) && 265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 266 queue_work(priv->wq, &priv->service_task); 267 } 268 269 static void stmmac_global_err(struct stmmac_priv *priv) 270 { 271 netif_carrier_off(priv->dev); 272 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 273 stmmac_service_event_schedule(priv); 274 } 275 276 /** 277 * stmmac_clk_csr_set - dynamically set the MDC clock 278 * @priv: driver private structure 279 * Description: this is to dynamically set the MDC clock according to the csr 280 * clock input. 281 * Note: 282 * If a specific clk_csr value is passed from the platform 283 * this means that the CSR Clock Range selection cannot be 284 * changed at run-time and it is fixed (as reported in the driver 285 * documentation). Viceversa the driver will try to set the MDC 286 * clock dynamically according to the actual clock input. 287 */ 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 289 { 290 u32 clk_rate; 291 292 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 293 294 /* Platform provided default clk_csr would be assumed valid 295 * for all other cases except for the below mentioned ones. 296 * For values higher than the IEEE 802.3 specified frequency 297 * we can not estimate the proper divider as it is not known 298 * the frequency of clk_csr_i. So we do not change the default 299 * divider. 300 */ 301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 302 if (clk_rate < CSR_F_35M) 303 priv->clk_csr = STMMAC_CSR_20_35M; 304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 305 priv->clk_csr = STMMAC_CSR_35_60M; 306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 307 priv->clk_csr = STMMAC_CSR_60_100M; 308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 309 priv->clk_csr = STMMAC_CSR_100_150M; 310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 311 priv->clk_csr = STMMAC_CSR_150_250M; 312 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 313 priv->clk_csr = STMMAC_CSR_250_300M; 314 } 315 316 if (priv->plat->has_sun8i) { 317 if (clk_rate > 160000000) 318 priv->clk_csr = 0x03; 319 else if (clk_rate > 80000000) 320 priv->clk_csr = 0x02; 321 else if (clk_rate > 40000000) 322 priv->clk_csr = 0x01; 323 else 324 priv->clk_csr = 0; 325 } 326 327 if (priv->plat->has_xgmac) { 328 if (clk_rate > 400000000) 329 priv->clk_csr = 0x5; 330 else if (clk_rate > 350000000) 331 priv->clk_csr = 0x4; 332 else if (clk_rate > 300000000) 333 priv->clk_csr = 0x3; 334 else if (clk_rate > 250000000) 335 priv->clk_csr = 0x2; 336 else if (clk_rate > 150000000) 337 priv->clk_csr = 0x1; 338 else 339 priv->clk_csr = 0x0; 340 } 341 } 342 343 static void print_pkt(unsigned char *buf, int len) 344 { 345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 347 } 348 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 350 { 351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 352 u32 avail; 353 354 if (tx_q->dirty_tx > tx_q->cur_tx) 355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 356 else 357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 358 359 return avail; 360 } 361 362 /** 363 * stmmac_rx_dirty - Get RX queue dirty 364 * @priv: driver private structure 365 * @queue: RX queue index 366 */ 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 368 { 369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 370 u32 dirty; 371 372 if (rx_q->dirty_rx <= rx_q->cur_rx) 373 dirty = rx_q->cur_rx - rx_q->dirty_rx; 374 else 375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 376 377 return dirty; 378 } 379 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 381 { 382 int tx_lpi_timer; 383 384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 385 priv->eee_sw_timer_en = en ? 0 : 1; 386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 388 } 389 390 /** 391 * stmmac_enable_eee_mode - check and enter in LPI mode 392 * @priv: driver private structure 393 * Description: this function is to verify and enter in LPI mode in case of 394 * EEE. 395 */ 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 397 { 398 u32 tx_cnt = priv->plat->tx_queues_to_use; 399 u32 queue; 400 401 /* check if all TX queues have the work finished */ 402 for (queue = 0; queue < tx_cnt; queue++) { 403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 404 405 if (tx_q->dirty_tx != tx_q->cur_tx) 406 return; /* still unfinished work */ 407 } 408 409 /* Check and enter in LPI mode */ 410 if (!priv->tx_path_in_lpi_mode) 411 stmmac_set_eee_mode(priv, priv->hw, 412 priv->plat->en_tx_lpi_clockgating); 413 } 414 415 /** 416 * stmmac_disable_eee_mode - disable and exit from LPI mode 417 * @priv: driver private structure 418 * Description: this function is to exit and disable EEE in case of 419 * LPI state is true. This is called by the xmit. 420 */ 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 422 { 423 if (!priv->eee_sw_timer_en) { 424 stmmac_lpi_entry_timer_config(priv, 0); 425 return; 426 } 427 428 stmmac_reset_eee_mode(priv, priv->hw); 429 del_timer_sync(&priv->eee_ctrl_timer); 430 priv->tx_path_in_lpi_mode = false; 431 } 432 433 /** 434 * stmmac_eee_ctrl_timer - EEE TX SW timer. 435 * @t: timer_list struct containing private info 436 * Description: 437 * if there is no data transfer and if we are not in LPI state, 438 * then MAC Transmitter can be moved to LPI state. 439 */ 440 static void stmmac_eee_ctrl_timer(struct timer_list *t) 441 { 442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 443 444 stmmac_enable_eee_mode(priv); 445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 446 } 447 448 /** 449 * stmmac_eee_init - init EEE 450 * @priv: driver private structure 451 * Description: 452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 453 * can also manage EEE, this function enable the LPI state and start related 454 * timer. 455 */ 456 bool stmmac_eee_init(struct stmmac_priv *priv) 457 { 458 int eee_tw_timer = priv->eee_tw_timer; 459 460 /* Using PCS we cannot dial with the phy registers at this stage 461 * so we do not support extra feature like EEE. 462 */ 463 if (priv->hw->pcs == STMMAC_PCS_TBI || 464 priv->hw->pcs == STMMAC_PCS_RTBI) 465 return false; 466 467 /* Check if MAC core supports the EEE feature. */ 468 if (!priv->dma_cap.eee) 469 return false; 470 471 mutex_lock(&priv->lock); 472 473 /* Check if it needs to be deactivated */ 474 if (!priv->eee_active) { 475 if (priv->eee_enabled) { 476 netdev_dbg(priv->dev, "disable EEE\n"); 477 stmmac_lpi_entry_timer_config(priv, 0); 478 del_timer_sync(&priv->eee_ctrl_timer); 479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 480 } 481 mutex_unlock(&priv->lock); 482 return false; 483 } 484 485 if (priv->eee_active && !priv->eee_enabled) { 486 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 487 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 488 eee_tw_timer); 489 } 490 491 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 492 del_timer_sync(&priv->eee_ctrl_timer); 493 priv->tx_path_in_lpi_mode = false; 494 stmmac_lpi_entry_timer_config(priv, 1); 495 } else { 496 stmmac_lpi_entry_timer_config(priv, 0); 497 mod_timer(&priv->eee_ctrl_timer, 498 STMMAC_LPI_T(priv->tx_lpi_timer)); 499 } 500 501 mutex_unlock(&priv->lock); 502 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 503 return true; 504 } 505 506 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 507 * @priv: driver private structure 508 * @p : descriptor pointer 509 * @skb : the socket buffer 510 * Description : 511 * This function will read timestamp from the descriptor & pass it to stack. 512 * and also perform some sanity checks. 513 */ 514 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 515 struct dma_desc *p, struct sk_buff *skb) 516 { 517 struct skb_shared_hwtstamps shhwtstamp; 518 bool found = false; 519 s64 adjust = 0; 520 u64 ns = 0; 521 522 if (!priv->hwts_tx_en) 523 return; 524 525 /* exit if skb doesn't support hw tstamp */ 526 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 527 return; 528 529 /* check tx tstamp status */ 530 if (stmmac_get_tx_timestamp_status(priv, p)) { 531 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 532 found = true; 533 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 534 found = true; 535 } 536 537 if (found) { 538 /* Correct the clk domain crossing(CDC) error */ 539 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 540 adjust += -(2 * (NSEC_PER_SEC / 541 priv->plat->clk_ptp_rate)); 542 ns += adjust; 543 } 544 545 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 546 shhwtstamp.hwtstamp = ns_to_ktime(ns); 547 548 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 549 /* pass tstamp to stack */ 550 skb_tstamp_tx(skb, &shhwtstamp); 551 } 552 } 553 554 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 555 * @priv: driver private structure 556 * @p : descriptor pointer 557 * @np : next descriptor pointer 558 * @skb : the socket buffer 559 * Description : 560 * This function will read received packet's timestamp from the descriptor 561 * and pass it to stack. It also perform some sanity checks. 562 */ 563 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 564 struct dma_desc *np, struct sk_buff *skb) 565 { 566 struct skb_shared_hwtstamps *shhwtstamp = NULL; 567 struct dma_desc *desc = p; 568 u64 adjust = 0; 569 u64 ns = 0; 570 571 if (!priv->hwts_rx_en) 572 return; 573 /* For GMAC4, the valid timestamp is from CTX next desc. */ 574 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 575 desc = np; 576 577 /* Check if timestamp is available */ 578 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 579 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 580 581 /* Correct the clk domain crossing(CDC) error */ 582 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 583 adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate); 584 ns -= adjust; 585 } 586 587 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 588 shhwtstamp = skb_hwtstamps(skb); 589 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 590 shhwtstamp->hwtstamp = ns_to_ktime(ns); 591 } else { 592 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 593 } 594 } 595 596 /** 597 * stmmac_hwtstamp_set - control hardware timestamping. 598 * @dev: device pointer. 599 * @ifr: An IOCTL specific structure, that can contain a pointer to 600 * a proprietary structure used to pass information to the driver. 601 * Description: 602 * This function configures the MAC to enable/disable both outgoing(TX) 603 * and incoming(RX) packets time stamping based on user input. 604 * Return Value: 605 * 0 on success and an appropriate -ve integer on failure. 606 */ 607 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 608 { 609 struct stmmac_priv *priv = netdev_priv(dev); 610 struct hwtstamp_config config; 611 struct timespec64 now; 612 u64 temp = 0; 613 u32 ptp_v2 = 0; 614 u32 tstamp_all = 0; 615 u32 ptp_over_ipv4_udp = 0; 616 u32 ptp_over_ipv6_udp = 0; 617 u32 ptp_over_ethernet = 0; 618 u32 snap_type_sel = 0; 619 u32 ts_master_en = 0; 620 u32 ts_event_en = 0; 621 u32 sec_inc = 0; 622 u32 value = 0; 623 bool xmac; 624 625 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 626 627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 628 netdev_alert(priv->dev, "No support for HW time stamping\n"); 629 priv->hwts_tx_en = 0; 630 priv->hwts_rx_en = 0; 631 632 return -EOPNOTSUPP; 633 } 634 635 if (copy_from_user(&config, ifr->ifr_data, 636 sizeof(config))) 637 return -EFAULT; 638 639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 640 __func__, config.flags, config.tx_type, config.rx_filter); 641 642 /* reserved for future extensions */ 643 if (config.flags) 644 return -EINVAL; 645 646 if (config.tx_type != HWTSTAMP_TX_OFF && 647 config.tx_type != HWTSTAMP_TX_ON) 648 return -ERANGE; 649 650 if (priv->adv_ts) { 651 switch (config.rx_filter) { 652 case HWTSTAMP_FILTER_NONE: 653 /* time stamp no incoming packet at all */ 654 config.rx_filter = HWTSTAMP_FILTER_NONE; 655 break; 656 657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 658 /* PTP v1, UDP, any kind of event packet */ 659 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 660 /* 'xmac' hardware can support Sync, Pdelay_Req and 661 * Pdelay_resp by setting bit14 and bits17/16 to 01 662 * This leaves Delay_Req timestamps out. 663 * Enable all events *and* general purpose message 664 * timestamping 665 */ 666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 669 break; 670 671 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 672 /* PTP v1, UDP, Sync packet */ 673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 674 /* take time stamp for SYNC messages only */ 675 ts_event_en = PTP_TCR_TSEVNTENA; 676 677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 679 break; 680 681 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 682 /* PTP v1, UDP, Delay_req packet */ 683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 684 /* take time stamp for Delay_Req messages only */ 685 ts_master_en = PTP_TCR_TSMSTRENA; 686 ts_event_en = PTP_TCR_TSEVNTENA; 687 688 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 689 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 690 break; 691 692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 693 /* PTP v2, UDP, any kind of event packet */ 694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 695 ptp_v2 = PTP_TCR_TSVER2ENA; 696 /* take time stamp for all event messages */ 697 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 698 699 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 700 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 701 break; 702 703 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 704 /* PTP v2, UDP, Sync packet */ 705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 706 ptp_v2 = PTP_TCR_TSVER2ENA; 707 /* take time stamp for SYNC messages only */ 708 ts_event_en = PTP_TCR_TSEVNTENA; 709 710 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 711 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 712 break; 713 714 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 715 /* PTP v2, UDP, Delay_req packet */ 716 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 717 ptp_v2 = PTP_TCR_TSVER2ENA; 718 /* take time stamp for Delay_Req messages only */ 719 ts_master_en = PTP_TCR_TSMSTRENA; 720 ts_event_en = PTP_TCR_TSEVNTENA; 721 722 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 723 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 724 break; 725 726 case HWTSTAMP_FILTER_PTP_V2_EVENT: 727 /* PTP v2/802.AS1 any layer, any kind of event packet */ 728 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 729 ptp_v2 = PTP_TCR_TSVER2ENA; 730 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 731 if (priv->synopsys_id != DWMAC_CORE_5_10) 732 ts_event_en = PTP_TCR_TSEVNTENA; 733 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 734 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 735 ptp_over_ethernet = PTP_TCR_TSIPENA; 736 break; 737 738 case HWTSTAMP_FILTER_PTP_V2_SYNC: 739 /* PTP v2/802.AS1, any layer, Sync packet */ 740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 741 ptp_v2 = PTP_TCR_TSVER2ENA; 742 /* take time stamp for SYNC messages only */ 743 ts_event_en = PTP_TCR_TSEVNTENA; 744 745 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 746 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 747 ptp_over_ethernet = PTP_TCR_TSIPENA; 748 break; 749 750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 751 /* PTP v2/802.AS1, any layer, Delay_req packet */ 752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 753 ptp_v2 = PTP_TCR_TSVER2ENA; 754 /* take time stamp for Delay_Req messages only */ 755 ts_master_en = PTP_TCR_TSMSTRENA; 756 ts_event_en = PTP_TCR_TSEVNTENA; 757 758 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 759 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 760 ptp_over_ethernet = PTP_TCR_TSIPENA; 761 break; 762 763 case HWTSTAMP_FILTER_NTP_ALL: 764 case HWTSTAMP_FILTER_ALL: 765 /* time stamp any incoming packet */ 766 config.rx_filter = HWTSTAMP_FILTER_ALL; 767 tstamp_all = PTP_TCR_TSENALL; 768 break; 769 770 default: 771 return -ERANGE; 772 } 773 } else { 774 switch (config.rx_filter) { 775 case HWTSTAMP_FILTER_NONE: 776 config.rx_filter = HWTSTAMP_FILTER_NONE; 777 break; 778 default: 779 /* PTP v1, UDP, any kind of event packet */ 780 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 781 break; 782 } 783 } 784 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 785 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 786 787 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 788 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 789 else { 790 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 791 tstamp_all | ptp_v2 | ptp_over_ethernet | 792 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 793 ts_master_en | snap_type_sel); 794 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 795 796 /* program Sub Second Increment reg */ 797 stmmac_config_sub_second_increment(priv, 798 priv->ptpaddr, priv->plat->clk_ptp_rate, 799 xmac, &sec_inc); 800 temp = div_u64(1000000000ULL, sec_inc); 801 802 /* Store sub second increment and flags for later use */ 803 priv->sub_second_inc = sec_inc; 804 priv->systime_flags = value; 805 806 /* calculate default added value: 807 * formula is : 808 * addend = (2^32)/freq_div_ratio; 809 * where, freq_div_ratio = 1e9ns/sec_inc 810 */ 811 temp = (u64)(temp << 32); 812 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 813 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 814 815 /* initialize system time */ 816 ktime_get_real_ts64(&now); 817 818 /* lower 32 bits of tv_sec are safe until y2106 */ 819 stmmac_init_systime(priv, priv->ptpaddr, 820 (u32)now.tv_sec, now.tv_nsec); 821 } 822 823 memcpy(&priv->tstamp_config, &config, sizeof(config)); 824 825 return copy_to_user(ifr->ifr_data, &config, 826 sizeof(config)) ? -EFAULT : 0; 827 } 828 829 /** 830 * stmmac_hwtstamp_get - read hardware timestamping. 831 * @dev: device pointer. 832 * @ifr: An IOCTL specific structure, that can contain a pointer to 833 * a proprietary structure used to pass information to the driver. 834 * Description: 835 * This function obtain the current hardware timestamping settings 836 * as requested. 837 */ 838 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 839 { 840 struct stmmac_priv *priv = netdev_priv(dev); 841 struct hwtstamp_config *config = &priv->tstamp_config; 842 843 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 844 return -EOPNOTSUPP; 845 846 return copy_to_user(ifr->ifr_data, config, 847 sizeof(*config)) ? -EFAULT : 0; 848 } 849 850 /** 851 * stmmac_init_ptp - init PTP 852 * @priv: driver private structure 853 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 854 * This is done by looking at the HW cap. register. 855 * This function also registers the ptp driver. 856 */ 857 static int stmmac_init_ptp(struct stmmac_priv *priv) 858 { 859 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 860 861 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 862 return -EOPNOTSUPP; 863 864 priv->adv_ts = 0; 865 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 866 if (xmac && priv->dma_cap.atime_stamp) 867 priv->adv_ts = 1; 868 /* Dwmac 3.x core with extend_desc can support adv_ts */ 869 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 870 priv->adv_ts = 1; 871 872 if (priv->dma_cap.time_stamp) 873 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 874 875 if (priv->adv_ts) 876 netdev_info(priv->dev, 877 "IEEE 1588-2008 Advanced Timestamp supported\n"); 878 879 priv->hwts_tx_en = 0; 880 priv->hwts_rx_en = 0; 881 882 stmmac_ptp_register(priv); 883 884 return 0; 885 } 886 887 static void stmmac_release_ptp(struct stmmac_priv *priv) 888 { 889 clk_disable_unprepare(priv->plat->clk_ptp_ref); 890 stmmac_ptp_unregister(priv); 891 } 892 893 /** 894 * stmmac_mac_flow_ctrl - Configure flow control in all queues 895 * @priv: driver private structure 896 * @duplex: duplex passed to the next function 897 * Description: It is used for configuring the flow control in all queues 898 */ 899 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 900 { 901 u32 tx_cnt = priv->plat->tx_queues_to_use; 902 903 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 904 priv->pause, tx_cnt); 905 } 906 907 static void stmmac_validate(struct phylink_config *config, 908 unsigned long *supported, 909 struct phylink_link_state *state) 910 { 911 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 912 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 913 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 914 int tx_cnt = priv->plat->tx_queues_to_use; 915 int max_speed = priv->plat->max_speed; 916 917 phylink_set(mac_supported, 10baseT_Half); 918 phylink_set(mac_supported, 10baseT_Full); 919 phylink_set(mac_supported, 100baseT_Half); 920 phylink_set(mac_supported, 100baseT_Full); 921 phylink_set(mac_supported, 1000baseT_Half); 922 phylink_set(mac_supported, 1000baseT_Full); 923 phylink_set(mac_supported, 1000baseKX_Full); 924 925 phylink_set(mac_supported, Autoneg); 926 phylink_set(mac_supported, Pause); 927 phylink_set(mac_supported, Asym_Pause); 928 phylink_set_port_modes(mac_supported); 929 930 /* Cut down 1G if asked to */ 931 if ((max_speed > 0) && (max_speed < 1000)) { 932 phylink_set(mask, 1000baseT_Full); 933 phylink_set(mask, 1000baseX_Full); 934 } else if (priv->plat->has_xgmac) { 935 if (!max_speed || (max_speed >= 2500)) { 936 phylink_set(mac_supported, 2500baseT_Full); 937 phylink_set(mac_supported, 2500baseX_Full); 938 } 939 if (!max_speed || (max_speed >= 5000)) { 940 phylink_set(mac_supported, 5000baseT_Full); 941 } 942 if (!max_speed || (max_speed >= 10000)) { 943 phylink_set(mac_supported, 10000baseSR_Full); 944 phylink_set(mac_supported, 10000baseLR_Full); 945 phylink_set(mac_supported, 10000baseER_Full); 946 phylink_set(mac_supported, 10000baseLRM_Full); 947 phylink_set(mac_supported, 10000baseT_Full); 948 phylink_set(mac_supported, 10000baseKX4_Full); 949 phylink_set(mac_supported, 10000baseKR_Full); 950 } 951 if (!max_speed || (max_speed >= 25000)) { 952 phylink_set(mac_supported, 25000baseCR_Full); 953 phylink_set(mac_supported, 25000baseKR_Full); 954 phylink_set(mac_supported, 25000baseSR_Full); 955 } 956 if (!max_speed || (max_speed >= 40000)) { 957 phylink_set(mac_supported, 40000baseKR4_Full); 958 phylink_set(mac_supported, 40000baseCR4_Full); 959 phylink_set(mac_supported, 40000baseSR4_Full); 960 phylink_set(mac_supported, 40000baseLR4_Full); 961 } 962 if (!max_speed || (max_speed >= 50000)) { 963 phylink_set(mac_supported, 50000baseCR2_Full); 964 phylink_set(mac_supported, 50000baseKR2_Full); 965 phylink_set(mac_supported, 50000baseSR2_Full); 966 phylink_set(mac_supported, 50000baseKR_Full); 967 phylink_set(mac_supported, 50000baseSR_Full); 968 phylink_set(mac_supported, 50000baseCR_Full); 969 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 970 phylink_set(mac_supported, 50000baseDR_Full); 971 } 972 if (!max_speed || (max_speed >= 100000)) { 973 phylink_set(mac_supported, 100000baseKR4_Full); 974 phylink_set(mac_supported, 100000baseSR4_Full); 975 phylink_set(mac_supported, 100000baseCR4_Full); 976 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 977 phylink_set(mac_supported, 100000baseKR2_Full); 978 phylink_set(mac_supported, 100000baseSR2_Full); 979 phylink_set(mac_supported, 100000baseCR2_Full); 980 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 981 phylink_set(mac_supported, 100000baseDR2_Full); 982 } 983 } 984 985 /* Half-Duplex can only work with single queue */ 986 if (tx_cnt > 1) { 987 phylink_set(mask, 10baseT_Half); 988 phylink_set(mask, 100baseT_Half); 989 phylink_set(mask, 1000baseT_Half); 990 } 991 992 linkmode_and(supported, supported, mac_supported); 993 linkmode_andnot(supported, supported, mask); 994 995 linkmode_and(state->advertising, state->advertising, mac_supported); 996 linkmode_andnot(state->advertising, state->advertising, mask); 997 998 /* If PCS is supported, check which modes it supports. */ 999 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 1000 } 1001 1002 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 1003 struct phylink_link_state *state) 1004 { 1005 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1006 1007 state->link = 0; 1008 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 1009 } 1010 1011 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 1012 const struct phylink_link_state *state) 1013 { 1014 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1015 1016 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 1017 } 1018 1019 static void stmmac_mac_an_restart(struct phylink_config *config) 1020 { 1021 /* Not Supported */ 1022 } 1023 1024 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 1025 { 1026 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 1027 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 1028 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 1029 bool *hs_enable = &fpe_cfg->hs_enable; 1030 1031 if (is_up && *hs_enable) { 1032 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 1033 } else { 1034 *lo_state = FPE_EVENT_UNKNOWN; 1035 *lp_state = FPE_EVENT_UNKNOWN; 1036 } 1037 } 1038 1039 static void stmmac_mac_link_down(struct phylink_config *config, 1040 unsigned int mode, phy_interface_t interface) 1041 { 1042 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1043 1044 stmmac_mac_set(priv, priv->ioaddr, false); 1045 priv->eee_active = false; 1046 priv->tx_lpi_enabled = false; 1047 stmmac_eee_init(priv); 1048 stmmac_set_eee_pls(priv, priv->hw, false); 1049 1050 if (priv->dma_cap.fpesel) 1051 stmmac_fpe_link_state_handle(priv, false); 1052 } 1053 1054 static void stmmac_mac_link_up(struct phylink_config *config, 1055 struct phy_device *phy, 1056 unsigned int mode, phy_interface_t interface, 1057 int speed, int duplex, 1058 bool tx_pause, bool rx_pause) 1059 { 1060 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1061 u32 ctrl; 1062 1063 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 1064 1065 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 1066 ctrl &= ~priv->hw->link.speed_mask; 1067 1068 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1069 switch (speed) { 1070 case SPEED_10000: 1071 ctrl |= priv->hw->link.xgmii.speed10000; 1072 break; 1073 case SPEED_5000: 1074 ctrl |= priv->hw->link.xgmii.speed5000; 1075 break; 1076 case SPEED_2500: 1077 ctrl |= priv->hw->link.xgmii.speed2500; 1078 break; 1079 default: 1080 return; 1081 } 1082 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1083 switch (speed) { 1084 case SPEED_100000: 1085 ctrl |= priv->hw->link.xlgmii.speed100000; 1086 break; 1087 case SPEED_50000: 1088 ctrl |= priv->hw->link.xlgmii.speed50000; 1089 break; 1090 case SPEED_40000: 1091 ctrl |= priv->hw->link.xlgmii.speed40000; 1092 break; 1093 case SPEED_25000: 1094 ctrl |= priv->hw->link.xlgmii.speed25000; 1095 break; 1096 case SPEED_10000: 1097 ctrl |= priv->hw->link.xgmii.speed10000; 1098 break; 1099 case SPEED_2500: 1100 ctrl |= priv->hw->link.speed2500; 1101 break; 1102 case SPEED_1000: 1103 ctrl |= priv->hw->link.speed1000; 1104 break; 1105 default: 1106 return; 1107 } 1108 } else { 1109 switch (speed) { 1110 case SPEED_2500: 1111 ctrl |= priv->hw->link.speed2500; 1112 break; 1113 case SPEED_1000: 1114 ctrl |= priv->hw->link.speed1000; 1115 break; 1116 case SPEED_100: 1117 ctrl |= priv->hw->link.speed100; 1118 break; 1119 case SPEED_10: 1120 ctrl |= priv->hw->link.speed10; 1121 break; 1122 default: 1123 return; 1124 } 1125 } 1126 1127 priv->speed = speed; 1128 1129 if (priv->plat->fix_mac_speed) 1130 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1131 1132 if (!duplex) 1133 ctrl &= ~priv->hw->link.duplex; 1134 else 1135 ctrl |= priv->hw->link.duplex; 1136 1137 /* Flow Control operation */ 1138 if (tx_pause && rx_pause) 1139 stmmac_mac_flow_ctrl(priv, duplex); 1140 1141 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1142 1143 stmmac_mac_set(priv, priv->ioaddr, true); 1144 if (phy && priv->dma_cap.eee) { 1145 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1146 priv->eee_enabled = stmmac_eee_init(priv); 1147 priv->tx_lpi_enabled = priv->eee_enabled; 1148 stmmac_set_eee_pls(priv, priv->hw, true); 1149 } 1150 1151 if (priv->dma_cap.fpesel) 1152 stmmac_fpe_link_state_handle(priv, true); 1153 } 1154 1155 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1156 .validate = stmmac_validate, 1157 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1158 .mac_config = stmmac_mac_config, 1159 .mac_an_restart = stmmac_mac_an_restart, 1160 .mac_link_down = stmmac_mac_link_down, 1161 .mac_link_up = stmmac_mac_link_up, 1162 }; 1163 1164 /** 1165 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1166 * @priv: driver private structure 1167 * Description: this is to verify if the HW supports the PCS. 1168 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1169 * configured for the TBI, RTBI, or SGMII PHY interface. 1170 */ 1171 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1172 { 1173 int interface = priv->plat->interface; 1174 1175 if (priv->dma_cap.pcs) { 1176 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1177 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1178 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1179 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1180 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1181 priv->hw->pcs = STMMAC_PCS_RGMII; 1182 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1183 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1184 priv->hw->pcs = STMMAC_PCS_SGMII; 1185 } 1186 } 1187 } 1188 1189 /** 1190 * stmmac_init_phy - PHY initialization 1191 * @dev: net device structure 1192 * Description: it initializes the driver's PHY state, and attaches the PHY 1193 * to the mac driver. 1194 * Return value: 1195 * 0 on success 1196 */ 1197 static int stmmac_init_phy(struct net_device *dev) 1198 { 1199 struct stmmac_priv *priv = netdev_priv(dev); 1200 struct device_node *node; 1201 int ret; 1202 1203 node = priv->plat->phylink_node; 1204 1205 if (node) 1206 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1207 1208 /* Some DT bindings do not set-up the PHY handle. Let's try to 1209 * manually parse it 1210 */ 1211 if (!node || ret) { 1212 int addr = priv->plat->phy_addr; 1213 struct phy_device *phydev; 1214 1215 phydev = mdiobus_get_phy(priv->mii, addr); 1216 if (!phydev) { 1217 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1218 return -ENODEV; 1219 } 1220 1221 ret = phylink_connect_phy(priv->phylink, phydev); 1222 } 1223 1224 if (!priv->plat->pmt) { 1225 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1226 1227 phylink_ethtool_get_wol(priv->phylink, &wol); 1228 device_set_wakeup_capable(priv->device, !!wol.supported); 1229 } 1230 1231 return ret; 1232 } 1233 1234 static int stmmac_phy_setup(struct stmmac_priv *priv) 1235 { 1236 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1237 int mode = priv->plat->phy_interface; 1238 struct phylink *phylink; 1239 1240 priv->phylink_config.dev = &priv->dev->dev; 1241 priv->phylink_config.type = PHYLINK_NETDEV; 1242 priv->phylink_config.pcs_poll = true; 1243 priv->phylink_config.ovr_an_inband = 1244 priv->plat->mdio_bus_data->xpcs_an_inband; 1245 1246 if (!fwnode) 1247 fwnode = dev_fwnode(priv->device); 1248 1249 phylink = phylink_create(&priv->phylink_config, fwnode, 1250 mode, &stmmac_phylink_mac_ops); 1251 if (IS_ERR(phylink)) 1252 return PTR_ERR(phylink); 1253 1254 priv->phylink = phylink; 1255 return 0; 1256 } 1257 1258 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1259 { 1260 u32 rx_cnt = priv->plat->rx_queues_to_use; 1261 unsigned int desc_size; 1262 void *head_rx; 1263 u32 queue; 1264 1265 /* Display RX rings */ 1266 for (queue = 0; queue < rx_cnt; queue++) { 1267 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1268 1269 pr_info("\tRX Queue %u rings\n", queue); 1270 1271 if (priv->extend_desc) { 1272 head_rx = (void *)rx_q->dma_erx; 1273 desc_size = sizeof(struct dma_extended_desc); 1274 } else { 1275 head_rx = (void *)rx_q->dma_rx; 1276 desc_size = sizeof(struct dma_desc); 1277 } 1278 1279 /* Display RX ring */ 1280 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1281 rx_q->dma_rx_phy, desc_size); 1282 } 1283 } 1284 1285 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1286 { 1287 u32 tx_cnt = priv->plat->tx_queues_to_use; 1288 unsigned int desc_size; 1289 void *head_tx; 1290 u32 queue; 1291 1292 /* Display TX rings */ 1293 for (queue = 0; queue < tx_cnt; queue++) { 1294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1295 1296 pr_info("\tTX Queue %d rings\n", queue); 1297 1298 if (priv->extend_desc) { 1299 head_tx = (void *)tx_q->dma_etx; 1300 desc_size = sizeof(struct dma_extended_desc); 1301 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1302 head_tx = (void *)tx_q->dma_entx; 1303 desc_size = sizeof(struct dma_edesc); 1304 } else { 1305 head_tx = (void *)tx_q->dma_tx; 1306 desc_size = sizeof(struct dma_desc); 1307 } 1308 1309 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1310 tx_q->dma_tx_phy, desc_size); 1311 } 1312 } 1313 1314 static void stmmac_display_rings(struct stmmac_priv *priv) 1315 { 1316 /* Display RX ring */ 1317 stmmac_display_rx_rings(priv); 1318 1319 /* Display TX ring */ 1320 stmmac_display_tx_rings(priv); 1321 } 1322 1323 static int stmmac_set_bfsize(int mtu, int bufsize) 1324 { 1325 int ret = bufsize; 1326 1327 if (mtu >= BUF_SIZE_8KiB) 1328 ret = BUF_SIZE_16KiB; 1329 else if (mtu >= BUF_SIZE_4KiB) 1330 ret = BUF_SIZE_8KiB; 1331 else if (mtu >= BUF_SIZE_2KiB) 1332 ret = BUF_SIZE_4KiB; 1333 else if (mtu > DEFAULT_BUFSIZE) 1334 ret = BUF_SIZE_2KiB; 1335 else 1336 ret = DEFAULT_BUFSIZE; 1337 1338 return ret; 1339 } 1340 1341 /** 1342 * stmmac_clear_rx_descriptors - clear RX descriptors 1343 * @priv: driver private structure 1344 * @queue: RX queue index 1345 * Description: this function is called to clear the RX descriptors 1346 * in case of both basic and extended descriptors are used. 1347 */ 1348 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1349 { 1350 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1351 int i; 1352 1353 /* Clear the RX descriptors */ 1354 for (i = 0; i < priv->dma_rx_size; i++) 1355 if (priv->extend_desc) 1356 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1357 priv->use_riwt, priv->mode, 1358 (i == priv->dma_rx_size - 1), 1359 priv->dma_buf_sz); 1360 else 1361 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1362 priv->use_riwt, priv->mode, 1363 (i == priv->dma_rx_size - 1), 1364 priv->dma_buf_sz); 1365 } 1366 1367 /** 1368 * stmmac_clear_tx_descriptors - clear tx descriptors 1369 * @priv: driver private structure 1370 * @queue: TX queue index. 1371 * Description: this function is called to clear the TX descriptors 1372 * in case of both basic and extended descriptors are used. 1373 */ 1374 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1375 { 1376 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1377 int i; 1378 1379 /* Clear the TX descriptors */ 1380 for (i = 0; i < priv->dma_tx_size; i++) { 1381 int last = (i == (priv->dma_tx_size - 1)); 1382 struct dma_desc *p; 1383 1384 if (priv->extend_desc) 1385 p = &tx_q->dma_etx[i].basic; 1386 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1387 p = &tx_q->dma_entx[i].basic; 1388 else 1389 p = &tx_q->dma_tx[i]; 1390 1391 stmmac_init_tx_desc(priv, p, priv->mode, last); 1392 } 1393 } 1394 1395 /** 1396 * stmmac_clear_descriptors - clear descriptors 1397 * @priv: driver private structure 1398 * Description: this function is called to clear the TX and RX descriptors 1399 * in case of both basic and extended descriptors are used. 1400 */ 1401 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1402 { 1403 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1404 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1405 u32 queue; 1406 1407 /* Clear the RX descriptors */ 1408 for (queue = 0; queue < rx_queue_cnt; queue++) 1409 stmmac_clear_rx_descriptors(priv, queue); 1410 1411 /* Clear the TX descriptors */ 1412 for (queue = 0; queue < tx_queue_cnt; queue++) 1413 stmmac_clear_tx_descriptors(priv, queue); 1414 } 1415 1416 /** 1417 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1418 * @priv: driver private structure 1419 * @p: descriptor pointer 1420 * @i: descriptor index 1421 * @flags: gfp flag 1422 * @queue: RX queue index 1423 * Description: this function is called to allocate a receive buffer, perform 1424 * the DMA mapping and init the descriptor. 1425 */ 1426 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1427 int i, gfp_t flags, u32 queue) 1428 { 1429 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1430 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1431 1432 if (!buf->page) { 1433 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1434 if (!buf->page) 1435 return -ENOMEM; 1436 buf->page_offset = stmmac_rx_offset(priv); 1437 } 1438 1439 if (priv->sph && !buf->sec_page) { 1440 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1441 if (!buf->sec_page) 1442 return -ENOMEM; 1443 1444 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1445 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1446 } else { 1447 buf->sec_page = NULL; 1448 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1449 } 1450 1451 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1452 1453 stmmac_set_desc_addr(priv, p, buf->addr); 1454 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1455 stmmac_init_desc3(priv, p); 1456 1457 return 0; 1458 } 1459 1460 /** 1461 * stmmac_free_rx_buffer - free RX dma buffers 1462 * @priv: private structure 1463 * @queue: RX queue index 1464 * @i: buffer index. 1465 */ 1466 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1467 { 1468 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1469 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1470 1471 if (buf->page) 1472 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1473 buf->page = NULL; 1474 1475 if (buf->sec_page) 1476 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1477 buf->sec_page = NULL; 1478 } 1479 1480 /** 1481 * stmmac_free_tx_buffer - free RX dma buffers 1482 * @priv: private structure 1483 * @queue: RX queue index 1484 * @i: buffer index. 1485 */ 1486 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1487 { 1488 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1489 1490 if (tx_q->tx_skbuff_dma[i].buf && 1491 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1492 if (tx_q->tx_skbuff_dma[i].map_as_page) 1493 dma_unmap_page(priv->device, 1494 tx_q->tx_skbuff_dma[i].buf, 1495 tx_q->tx_skbuff_dma[i].len, 1496 DMA_TO_DEVICE); 1497 else 1498 dma_unmap_single(priv->device, 1499 tx_q->tx_skbuff_dma[i].buf, 1500 tx_q->tx_skbuff_dma[i].len, 1501 DMA_TO_DEVICE); 1502 } 1503 1504 if (tx_q->xdpf[i] && 1505 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1506 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1507 xdp_return_frame(tx_q->xdpf[i]); 1508 tx_q->xdpf[i] = NULL; 1509 } 1510 1511 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1512 tx_q->xsk_frames_done++; 1513 1514 if (tx_q->tx_skbuff[i] && 1515 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1516 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1517 tx_q->tx_skbuff[i] = NULL; 1518 } 1519 1520 tx_q->tx_skbuff_dma[i].buf = 0; 1521 tx_q->tx_skbuff_dma[i].map_as_page = false; 1522 } 1523 1524 /** 1525 * dma_free_rx_skbufs - free RX dma buffers 1526 * @priv: private structure 1527 * @queue: RX queue index 1528 */ 1529 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1530 { 1531 int i; 1532 1533 for (i = 0; i < priv->dma_rx_size; i++) 1534 stmmac_free_rx_buffer(priv, queue, i); 1535 } 1536 1537 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, 1538 gfp_t flags) 1539 { 1540 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1541 int i; 1542 1543 for (i = 0; i < priv->dma_rx_size; i++) { 1544 struct dma_desc *p; 1545 int ret; 1546 1547 if (priv->extend_desc) 1548 p = &((rx_q->dma_erx + i)->basic); 1549 else 1550 p = rx_q->dma_rx + i; 1551 1552 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1553 queue); 1554 if (ret) 1555 return ret; 1556 1557 rx_q->buf_alloc_num++; 1558 } 1559 1560 return 0; 1561 } 1562 1563 /** 1564 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1565 * @priv: private structure 1566 * @queue: RX queue index 1567 */ 1568 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) 1569 { 1570 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1571 int i; 1572 1573 for (i = 0; i < priv->dma_rx_size; i++) { 1574 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1575 1576 if (!buf->xdp) 1577 continue; 1578 1579 xsk_buff_free(buf->xdp); 1580 buf->xdp = NULL; 1581 } 1582 } 1583 1584 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) 1585 { 1586 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1587 int i; 1588 1589 for (i = 0; i < priv->dma_rx_size; i++) { 1590 struct stmmac_rx_buffer *buf; 1591 dma_addr_t dma_addr; 1592 struct dma_desc *p; 1593 1594 if (priv->extend_desc) 1595 p = (struct dma_desc *)(rx_q->dma_erx + i); 1596 else 1597 p = rx_q->dma_rx + i; 1598 1599 buf = &rx_q->buf_pool[i]; 1600 1601 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1602 if (!buf->xdp) 1603 return -ENOMEM; 1604 1605 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1606 stmmac_set_desc_addr(priv, p, dma_addr); 1607 rx_q->buf_alloc_num++; 1608 } 1609 1610 return 0; 1611 } 1612 1613 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1614 { 1615 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1616 return NULL; 1617 1618 return xsk_get_pool_from_qid(priv->dev, queue); 1619 } 1620 1621 /** 1622 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1623 * @priv: driver private structure 1624 * @queue: RX queue index 1625 * @flags: gfp flag. 1626 * Description: this function initializes the DMA RX descriptors 1627 * and allocates the socket buffers. It supports the chained and ring 1628 * modes. 1629 */ 1630 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) 1631 { 1632 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1633 int ret; 1634 1635 netif_dbg(priv, probe, priv->dev, 1636 "(%s) dma_rx_phy=0x%08x\n", __func__, 1637 (u32)rx_q->dma_rx_phy); 1638 1639 stmmac_clear_rx_descriptors(priv, queue); 1640 1641 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1642 1643 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1644 1645 if (rx_q->xsk_pool) { 1646 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1647 MEM_TYPE_XSK_BUFF_POOL, 1648 NULL)); 1649 netdev_info(priv->dev, 1650 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1651 rx_q->queue_index); 1652 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1653 } else { 1654 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1655 MEM_TYPE_PAGE_POOL, 1656 rx_q->page_pool)); 1657 netdev_info(priv->dev, 1658 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1659 rx_q->queue_index); 1660 } 1661 1662 if (rx_q->xsk_pool) { 1663 /* RX XDP ZC buffer pool may not be populated, e.g. 1664 * xdpsock TX-only. 1665 */ 1666 stmmac_alloc_rx_buffers_zc(priv, queue); 1667 } else { 1668 ret = stmmac_alloc_rx_buffers(priv, queue, flags); 1669 if (ret < 0) 1670 return -ENOMEM; 1671 } 1672 1673 rx_q->cur_rx = 0; 1674 rx_q->dirty_rx = 0; 1675 1676 /* Setup the chained descriptor addresses */ 1677 if (priv->mode == STMMAC_CHAIN_MODE) { 1678 if (priv->extend_desc) 1679 stmmac_mode_init(priv, rx_q->dma_erx, 1680 rx_q->dma_rx_phy, 1681 priv->dma_rx_size, 1); 1682 else 1683 stmmac_mode_init(priv, rx_q->dma_rx, 1684 rx_q->dma_rx_phy, 1685 priv->dma_rx_size, 0); 1686 } 1687 1688 return 0; 1689 } 1690 1691 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1692 { 1693 struct stmmac_priv *priv = netdev_priv(dev); 1694 u32 rx_count = priv->plat->rx_queues_to_use; 1695 u32 queue; 1696 int ret; 1697 1698 /* RX INITIALIZATION */ 1699 netif_dbg(priv, probe, priv->dev, 1700 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1701 1702 for (queue = 0; queue < rx_count; queue++) { 1703 ret = __init_dma_rx_desc_rings(priv, queue, flags); 1704 if (ret) 1705 goto err_init_rx_buffers; 1706 } 1707 1708 return 0; 1709 1710 err_init_rx_buffers: 1711 while (queue >= 0) { 1712 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1713 1714 if (rx_q->xsk_pool) 1715 dma_free_rx_xskbufs(priv, queue); 1716 else 1717 dma_free_rx_skbufs(priv, queue); 1718 1719 rx_q->buf_alloc_num = 0; 1720 rx_q->xsk_pool = NULL; 1721 1722 if (queue == 0) 1723 break; 1724 1725 queue--; 1726 } 1727 1728 return ret; 1729 } 1730 1731 /** 1732 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1733 * @priv: driver private structure 1734 * @queue : TX queue index 1735 * Description: this function initializes the DMA TX descriptors 1736 * and allocates the socket buffers. It supports the chained and ring 1737 * modes. 1738 */ 1739 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) 1740 { 1741 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1742 int i; 1743 1744 netif_dbg(priv, probe, priv->dev, 1745 "(%s) dma_tx_phy=0x%08x\n", __func__, 1746 (u32)tx_q->dma_tx_phy); 1747 1748 /* Setup the chained descriptor addresses */ 1749 if (priv->mode == STMMAC_CHAIN_MODE) { 1750 if (priv->extend_desc) 1751 stmmac_mode_init(priv, tx_q->dma_etx, 1752 tx_q->dma_tx_phy, 1753 priv->dma_tx_size, 1); 1754 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1755 stmmac_mode_init(priv, tx_q->dma_tx, 1756 tx_q->dma_tx_phy, 1757 priv->dma_tx_size, 0); 1758 } 1759 1760 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1761 1762 for (i = 0; i < priv->dma_tx_size; i++) { 1763 struct dma_desc *p; 1764 1765 if (priv->extend_desc) 1766 p = &((tx_q->dma_etx + i)->basic); 1767 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1768 p = &((tx_q->dma_entx + i)->basic); 1769 else 1770 p = tx_q->dma_tx + i; 1771 1772 stmmac_clear_desc(priv, p); 1773 1774 tx_q->tx_skbuff_dma[i].buf = 0; 1775 tx_q->tx_skbuff_dma[i].map_as_page = false; 1776 tx_q->tx_skbuff_dma[i].len = 0; 1777 tx_q->tx_skbuff_dma[i].last_segment = false; 1778 tx_q->tx_skbuff[i] = NULL; 1779 } 1780 1781 tx_q->dirty_tx = 0; 1782 tx_q->cur_tx = 0; 1783 tx_q->mss = 0; 1784 1785 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1786 1787 return 0; 1788 } 1789 1790 static int init_dma_tx_desc_rings(struct net_device *dev) 1791 { 1792 struct stmmac_priv *priv = netdev_priv(dev); 1793 u32 tx_queue_cnt; 1794 u32 queue; 1795 1796 tx_queue_cnt = priv->plat->tx_queues_to_use; 1797 1798 for (queue = 0; queue < tx_queue_cnt; queue++) 1799 __init_dma_tx_desc_rings(priv, queue); 1800 1801 return 0; 1802 } 1803 1804 /** 1805 * init_dma_desc_rings - init the RX/TX descriptor rings 1806 * @dev: net device structure 1807 * @flags: gfp flag. 1808 * Description: this function initializes the DMA RX/TX descriptors 1809 * and allocates the socket buffers. It supports the chained and ring 1810 * modes. 1811 */ 1812 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1813 { 1814 struct stmmac_priv *priv = netdev_priv(dev); 1815 int ret; 1816 1817 ret = init_dma_rx_desc_rings(dev, flags); 1818 if (ret) 1819 return ret; 1820 1821 ret = init_dma_tx_desc_rings(dev); 1822 1823 stmmac_clear_descriptors(priv); 1824 1825 if (netif_msg_hw(priv)) 1826 stmmac_display_rings(priv); 1827 1828 return ret; 1829 } 1830 1831 /** 1832 * dma_free_tx_skbufs - free TX dma buffers 1833 * @priv: private structure 1834 * @queue: TX queue index 1835 */ 1836 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1837 { 1838 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1839 int i; 1840 1841 tx_q->xsk_frames_done = 0; 1842 1843 for (i = 0; i < priv->dma_tx_size; i++) 1844 stmmac_free_tx_buffer(priv, queue, i); 1845 1846 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1847 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1848 tx_q->xsk_frames_done = 0; 1849 tx_q->xsk_pool = NULL; 1850 } 1851 } 1852 1853 /** 1854 * stmmac_free_tx_skbufs - free TX skb buffers 1855 * @priv: private structure 1856 */ 1857 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1858 { 1859 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1860 u32 queue; 1861 1862 for (queue = 0; queue < tx_queue_cnt; queue++) 1863 dma_free_tx_skbufs(priv, queue); 1864 } 1865 1866 /** 1867 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1868 * @priv: private structure 1869 * @queue: RX queue index 1870 */ 1871 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1872 { 1873 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1874 1875 /* Release the DMA RX socket buffers */ 1876 if (rx_q->xsk_pool) 1877 dma_free_rx_xskbufs(priv, queue); 1878 else 1879 dma_free_rx_skbufs(priv, queue); 1880 1881 rx_q->buf_alloc_num = 0; 1882 rx_q->xsk_pool = NULL; 1883 1884 /* Free DMA regions of consistent memory previously allocated */ 1885 if (!priv->extend_desc) 1886 dma_free_coherent(priv->device, priv->dma_rx_size * 1887 sizeof(struct dma_desc), 1888 rx_q->dma_rx, rx_q->dma_rx_phy); 1889 else 1890 dma_free_coherent(priv->device, priv->dma_rx_size * 1891 sizeof(struct dma_extended_desc), 1892 rx_q->dma_erx, rx_q->dma_rx_phy); 1893 1894 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1895 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1896 1897 kfree(rx_q->buf_pool); 1898 if (rx_q->page_pool) 1899 page_pool_destroy(rx_q->page_pool); 1900 } 1901 1902 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1903 { 1904 u32 rx_count = priv->plat->rx_queues_to_use; 1905 u32 queue; 1906 1907 /* Free RX queue resources */ 1908 for (queue = 0; queue < rx_count; queue++) 1909 __free_dma_rx_desc_resources(priv, queue); 1910 } 1911 1912 /** 1913 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1914 * @priv: private structure 1915 * @queue: TX queue index 1916 */ 1917 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 1918 { 1919 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1920 size_t size; 1921 void *addr; 1922 1923 /* Release the DMA TX socket buffers */ 1924 dma_free_tx_skbufs(priv, queue); 1925 1926 if (priv->extend_desc) { 1927 size = sizeof(struct dma_extended_desc); 1928 addr = tx_q->dma_etx; 1929 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1930 size = sizeof(struct dma_edesc); 1931 addr = tx_q->dma_entx; 1932 } else { 1933 size = sizeof(struct dma_desc); 1934 addr = tx_q->dma_tx; 1935 } 1936 1937 size *= priv->dma_tx_size; 1938 1939 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1940 1941 kfree(tx_q->tx_skbuff_dma); 1942 kfree(tx_q->tx_skbuff); 1943 } 1944 1945 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1946 { 1947 u32 tx_count = priv->plat->tx_queues_to_use; 1948 u32 queue; 1949 1950 /* Free TX queue resources */ 1951 for (queue = 0; queue < tx_count; queue++) 1952 __free_dma_tx_desc_resources(priv, queue); 1953 } 1954 1955 /** 1956 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1957 * @priv: private structure 1958 * @queue: RX queue index 1959 * Description: according to which descriptor can be used (extend or basic) 1960 * this function allocates the resources for TX and RX paths. In case of 1961 * reception, for example, it pre-allocated the RX socket buffer in order to 1962 * allow zero-copy mechanism. 1963 */ 1964 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1965 { 1966 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1967 struct stmmac_channel *ch = &priv->channel[queue]; 1968 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1969 struct page_pool_params pp_params = { 0 }; 1970 unsigned int num_pages; 1971 unsigned int napi_id; 1972 int ret; 1973 1974 rx_q->queue_index = queue; 1975 rx_q->priv_data = priv; 1976 1977 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1978 pp_params.pool_size = priv->dma_rx_size; 1979 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1980 pp_params.order = ilog2(num_pages); 1981 pp_params.nid = dev_to_node(priv->device); 1982 pp_params.dev = priv->device; 1983 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1984 pp_params.offset = stmmac_rx_offset(priv); 1985 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 1986 1987 rx_q->page_pool = page_pool_create(&pp_params); 1988 if (IS_ERR(rx_q->page_pool)) { 1989 ret = PTR_ERR(rx_q->page_pool); 1990 rx_q->page_pool = NULL; 1991 return ret; 1992 } 1993 1994 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1995 sizeof(*rx_q->buf_pool), 1996 GFP_KERNEL); 1997 if (!rx_q->buf_pool) 1998 return -ENOMEM; 1999 2000 if (priv->extend_desc) { 2001 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2002 priv->dma_rx_size * 2003 sizeof(struct dma_extended_desc), 2004 &rx_q->dma_rx_phy, 2005 GFP_KERNEL); 2006 if (!rx_q->dma_erx) 2007 return -ENOMEM; 2008 2009 } else { 2010 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2011 priv->dma_rx_size * 2012 sizeof(struct dma_desc), 2013 &rx_q->dma_rx_phy, 2014 GFP_KERNEL); 2015 if (!rx_q->dma_rx) 2016 return -ENOMEM; 2017 } 2018 2019 if (stmmac_xdp_is_enabled(priv) && 2020 test_bit(queue, priv->af_xdp_zc_qps)) 2021 napi_id = ch->rxtx_napi.napi_id; 2022 else 2023 napi_id = ch->rx_napi.napi_id; 2024 2025 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2026 rx_q->queue_index, 2027 napi_id); 2028 if (ret) { 2029 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2030 return -EINVAL; 2031 } 2032 2033 return 0; 2034 } 2035 2036 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 2037 { 2038 u32 rx_count = priv->plat->rx_queues_to_use; 2039 u32 queue; 2040 int ret; 2041 2042 /* RX queues buffers and DMA */ 2043 for (queue = 0; queue < rx_count; queue++) { 2044 ret = __alloc_dma_rx_desc_resources(priv, queue); 2045 if (ret) 2046 goto err_dma; 2047 } 2048 2049 return 0; 2050 2051 err_dma: 2052 free_dma_rx_desc_resources(priv); 2053 2054 return ret; 2055 } 2056 2057 /** 2058 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2059 * @priv: private structure 2060 * @queue: TX queue index 2061 * Description: according to which descriptor can be used (extend or basic) 2062 * this function allocates the resources for TX and RX paths. In case of 2063 * reception, for example, it pre-allocated the RX socket buffer in order to 2064 * allow zero-copy mechanism. 2065 */ 2066 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 2067 { 2068 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2069 size_t size; 2070 void *addr; 2071 2072 tx_q->queue_index = queue; 2073 tx_q->priv_data = priv; 2074 2075 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 2076 sizeof(*tx_q->tx_skbuff_dma), 2077 GFP_KERNEL); 2078 if (!tx_q->tx_skbuff_dma) 2079 return -ENOMEM; 2080 2081 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 2082 sizeof(struct sk_buff *), 2083 GFP_KERNEL); 2084 if (!tx_q->tx_skbuff) 2085 return -ENOMEM; 2086 2087 if (priv->extend_desc) 2088 size = sizeof(struct dma_extended_desc); 2089 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2090 size = sizeof(struct dma_edesc); 2091 else 2092 size = sizeof(struct dma_desc); 2093 2094 size *= priv->dma_tx_size; 2095 2096 addr = dma_alloc_coherent(priv->device, size, 2097 &tx_q->dma_tx_phy, GFP_KERNEL); 2098 if (!addr) 2099 return -ENOMEM; 2100 2101 if (priv->extend_desc) 2102 tx_q->dma_etx = addr; 2103 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2104 tx_q->dma_entx = addr; 2105 else 2106 tx_q->dma_tx = addr; 2107 2108 return 0; 2109 } 2110 2111 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 2112 { 2113 u32 tx_count = priv->plat->tx_queues_to_use; 2114 u32 queue; 2115 int ret; 2116 2117 /* TX queues buffers and DMA */ 2118 for (queue = 0; queue < tx_count; queue++) { 2119 ret = __alloc_dma_tx_desc_resources(priv, queue); 2120 if (ret) 2121 goto err_dma; 2122 } 2123 2124 return 0; 2125 2126 err_dma: 2127 free_dma_tx_desc_resources(priv); 2128 return ret; 2129 } 2130 2131 /** 2132 * alloc_dma_desc_resources - alloc TX/RX resources. 2133 * @priv: private structure 2134 * Description: according to which descriptor can be used (extend or basic) 2135 * this function allocates the resources for TX and RX paths. In case of 2136 * reception, for example, it pre-allocated the RX socket buffer in order to 2137 * allow zero-copy mechanism. 2138 */ 2139 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 2140 { 2141 /* RX Allocation */ 2142 int ret = alloc_dma_rx_desc_resources(priv); 2143 2144 if (ret) 2145 return ret; 2146 2147 ret = alloc_dma_tx_desc_resources(priv); 2148 2149 return ret; 2150 } 2151 2152 /** 2153 * free_dma_desc_resources - free dma desc resources 2154 * @priv: private structure 2155 */ 2156 static void free_dma_desc_resources(struct stmmac_priv *priv) 2157 { 2158 /* Release the DMA TX socket buffers */ 2159 free_dma_tx_desc_resources(priv); 2160 2161 /* Release the DMA RX socket buffers later 2162 * to ensure all pending XDP_TX buffers are returned. 2163 */ 2164 free_dma_rx_desc_resources(priv); 2165 } 2166 2167 /** 2168 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2169 * @priv: driver private structure 2170 * Description: It is used for enabling the rx queues in the MAC 2171 */ 2172 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2173 { 2174 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2175 int queue; 2176 u8 mode; 2177 2178 for (queue = 0; queue < rx_queues_count; queue++) { 2179 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2180 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2181 } 2182 } 2183 2184 /** 2185 * stmmac_start_rx_dma - start RX DMA channel 2186 * @priv: driver private structure 2187 * @chan: RX channel index 2188 * Description: 2189 * This starts a RX DMA channel 2190 */ 2191 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2192 { 2193 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2194 stmmac_start_rx(priv, priv->ioaddr, chan); 2195 } 2196 2197 /** 2198 * stmmac_start_tx_dma - start TX DMA channel 2199 * @priv: driver private structure 2200 * @chan: TX channel index 2201 * Description: 2202 * This starts a TX DMA channel 2203 */ 2204 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2205 { 2206 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2207 stmmac_start_tx(priv, priv->ioaddr, chan); 2208 } 2209 2210 /** 2211 * stmmac_stop_rx_dma - stop RX DMA channel 2212 * @priv: driver private structure 2213 * @chan: RX channel index 2214 * Description: 2215 * This stops a RX DMA channel 2216 */ 2217 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2218 { 2219 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2220 stmmac_stop_rx(priv, priv->ioaddr, chan); 2221 } 2222 2223 /** 2224 * stmmac_stop_tx_dma - stop TX DMA channel 2225 * @priv: driver private structure 2226 * @chan: TX channel index 2227 * Description: 2228 * This stops a TX DMA channel 2229 */ 2230 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2231 { 2232 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2233 stmmac_stop_tx(priv, priv->ioaddr, chan); 2234 } 2235 2236 /** 2237 * stmmac_start_all_dma - start all RX and TX DMA channels 2238 * @priv: driver private structure 2239 * Description: 2240 * This starts all the RX and TX DMA channels 2241 */ 2242 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2243 { 2244 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2245 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2246 u32 chan = 0; 2247 2248 for (chan = 0; chan < rx_channels_count; chan++) 2249 stmmac_start_rx_dma(priv, chan); 2250 2251 for (chan = 0; chan < tx_channels_count; chan++) 2252 stmmac_start_tx_dma(priv, chan); 2253 } 2254 2255 /** 2256 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2257 * @priv: driver private structure 2258 * Description: 2259 * This stops the RX and TX DMA channels 2260 */ 2261 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2262 { 2263 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2264 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2265 u32 chan = 0; 2266 2267 for (chan = 0; chan < rx_channels_count; chan++) 2268 stmmac_stop_rx_dma(priv, chan); 2269 2270 for (chan = 0; chan < tx_channels_count; chan++) 2271 stmmac_stop_tx_dma(priv, chan); 2272 } 2273 2274 /** 2275 * stmmac_dma_operation_mode - HW DMA operation mode 2276 * @priv: driver private structure 2277 * Description: it is used for configuring the DMA operation mode register in 2278 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2279 */ 2280 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2281 { 2282 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2283 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2284 int rxfifosz = priv->plat->rx_fifo_size; 2285 int txfifosz = priv->plat->tx_fifo_size; 2286 u32 txmode = 0; 2287 u32 rxmode = 0; 2288 u32 chan = 0; 2289 u8 qmode = 0; 2290 2291 if (rxfifosz == 0) 2292 rxfifosz = priv->dma_cap.rx_fifo_size; 2293 if (txfifosz == 0) 2294 txfifosz = priv->dma_cap.tx_fifo_size; 2295 2296 /* Adjust for real per queue fifo size */ 2297 rxfifosz /= rx_channels_count; 2298 txfifosz /= tx_channels_count; 2299 2300 if (priv->plat->force_thresh_dma_mode) { 2301 txmode = tc; 2302 rxmode = tc; 2303 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2304 /* 2305 * In case of GMAC, SF mode can be enabled 2306 * to perform the TX COE in HW. This depends on: 2307 * 1) TX COE if actually supported 2308 * 2) There is no bugged Jumbo frame support 2309 * that needs to not insert csum in the TDES. 2310 */ 2311 txmode = SF_DMA_MODE; 2312 rxmode = SF_DMA_MODE; 2313 priv->xstats.threshold = SF_DMA_MODE; 2314 } else { 2315 txmode = tc; 2316 rxmode = SF_DMA_MODE; 2317 } 2318 2319 /* configure all channels */ 2320 for (chan = 0; chan < rx_channels_count; chan++) { 2321 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2322 u32 buf_size; 2323 2324 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2325 2326 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2327 rxfifosz, qmode); 2328 2329 if (rx_q->xsk_pool) { 2330 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2331 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2332 buf_size, 2333 chan); 2334 } else { 2335 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2336 priv->dma_buf_sz, 2337 chan); 2338 } 2339 } 2340 2341 for (chan = 0; chan < tx_channels_count; chan++) { 2342 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2343 2344 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2345 txfifosz, qmode); 2346 } 2347 } 2348 2349 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2350 { 2351 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2352 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2353 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2354 unsigned int entry = tx_q->cur_tx; 2355 struct dma_desc *tx_desc = NULL; 2356 struct xdp_desc xdp_desc; 2357 bool work_done = true; 2358 2359 /* Avoids TX time-out as we are sharing with slow path */ 2360 nq->trans_start = jiffies; 2361 2362 budget = min(budget, stmmac_tx_avail(priv, queue)); 2363 2364 while (budget-- > 0) { 2365 dma_addr_t dma_addr; 2366 bool set_ic; 2367 2368 /* We are sharing with slow path and stop XSK TX desc submission when 2369 * available TX ring is less than threshold. 2370 */ 2371 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2372 !netif_carrier_ok(priv->dev)) { 2373 work_done = false; 2374 break; 2375 } 2376 2377 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2378 break; 2379 2380 if (likely(priv->extend_desc)) 2381 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2382 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2383 tx_desc = &tx_q->dma_entx[entry].basic; 2384 else 2385 tx_desc = tx_q->dma_tx + entry; 2386 2387 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2388 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2389 2390 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2391 2392 /* To return XDP buffer to XSK pool, we simple call 2393 * xsk_tx_completed(), so we don't need to fill up 2394 * 'buf' and 'xdpf'. 2395 */ 2396 tx_q->tx_skbuff_dma[entry].buf = 0; 2397 tx_q->xdpf[entry] = NULL; 2398 2399 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2400 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2401 tx_q->tx_skbuff_dma[entry].last_segment = true; 2402 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2403 2404 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2405 2406 tx_q->tx_count_frames++; 2407 2408 if (!priv->tx_coal_frames[queue]) 2409 set_ic = false; 2410 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2411 set_ic = true; 2412 else 2413 set_ic = false; 2414 2415 if (set_ic) { 2416 tx_q->tx_count_frames = 0; 2417 stmmac_set_tx_ic(priv, tx_desc); 2418 priv->xstats.tx_set_ic_bit++; 2419 } 2420 2421 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2422 true, priv->mode, true, true, 2423 xdp_desc.len); 2424 2425 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2426 2427 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2428 entry = tx_q->cur_tx; 2429 } 2430 2431 if (tx_desc) { 2432 stmmac_flush_tx_descriptors(priv, queue); 2433 xsk_tx_release(pool); 2434 } 2435 2436 /* Return true if all of the 3 conditions are met 2437 * a) TX Budget is still available 2438 * b) work_done = true when XSK TX desc peek is empty (no more 2439 * pending XSK TX for transmission) 2440 */ 2441 return !!budget && work_done; 2442 } 2443 2444 /** 2445 * stmmac_tx_clean - to manage the transmission completion 2446 * @priv: driver private structure 2447 * @budget: napi budget limiting this functions packet handling 2448 * @queue: TX queue index 2449 * Description: it reclaims the transmit resources after transmission completes. 2450 */ 2451 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2452 { 2453 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2454 unsigned int bytes_compl = 0, pkts_compl = 0; 2455 unsigned int entry, xmits = 0, count = 0; 2456 2457 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2458 2459 priv->xstats.tx_clean++; 2460 2461 tx_q->xsk_frames_done = 0; 2462 2463 entry = tx_q->dirty_tx; 2464 2465 /* Try to clean all TX complete frame in 1 shot */ 2466 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { 2467 struct xdp_frame *xdpf; 2468 struct sk_buff *skb; 2469 struct dma_desc *p; 2470 int status; 2471 2472 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2473 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2474 xdpf = tx_q->xdpf[entry]; 2475 skb = NULL; 2476 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2477 xdpf = NULL; 2478 skb = tx_q->tx_skbuff[entry]; 2479 } else { 2480 xdpf = NULL; 2481 skb = NULL; 2482 } 2483 2484 if (priv->extend_desc) 2485 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2486 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2487 p = &tx_q->dma_entx[entry].basic; 2488 else 2489 p = tx_q->dma_tx + entry; 2490 2491 status = stmmac_tx_status(priv, &priv->dev->stats, 2492 &priv->xstats, p, priv->ioaddr); 2493 /* Check if the descriptor is owned by the DMA */ 2494 if (unlikely(status & tx_dma_own)) 2495 break; 2496 2497 count++; 2498 2499 /* Make sure descriptor fields are read after reading 2500 * the own bit. 2501 */ 2502 dma_rmb(); 2503 2504 /* Just consider the last segment and ...*/ 2505 if (likely(!(status & tx_not_ls))) { 2506 /* ... verify the status error condition */ 2507 if (unlikely(status & tx_err)) { 2508 priv->dev->stats.tx_errors++; 2509 } else { 2510 priv->dev->stats.tx_packets++; 2511 priv->xstats.tx_pkt_n++; 2512 } 2513 if (skb) 2514 stmmac_get_tx_hwtstamp(priv, p, skb); 2515 } 2516 2517 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2518 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2519 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2520 dma_unmap_page(priv->device, 2521 tx_q->tx_skbuff_dma[entry].buf, 2522 tx_q->tx_skbuff_dma[entry].len, 2523 DMA_TO_DEVICE); 2524 else 2525 dma_unmap_single(priv->device, 2526 tx_q->tx_skbuff_dma[entry].buf, 2527 tx_q->tx_skbuff_dma[entry].len, 2528 DMA_TO_DEVICE); 2529 tx_q->tx_skbuff_dma[entry].buf = 0; 2530 tx_q->tx_skbuff_dma[entry].len = 0; 2531 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2532 } 2533 2534 stmmac_clean_desc3(priv, tx_q, p); 2535 2536 tx_q->tx_skbuff_dma[entry].last_segment = false; 2537 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2538 2539 if (xdpf && 2540 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2541 xdp_return_frame_rx_napi(xdpf); 2542 tx_q->xdpf[entry] = NULL; 2543 } 2544 2545 if (xdpf && 2546 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2547 xdp_return_frame(xdpf); 2548 tx_q->xdpf[entry] = NULL; 2549 } 2550 2551 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2552 tx_q->xsk_frames_done++; 2553 2554 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2555 if (likely(skb)) { 2556 pkts_compl++; 2557 bytes_compl += skb->len; 2558 dev_consume_skb_any(skb); 2559 tx_q->tx_skbuff[entry] = NULL; 2560 } 2561 } 2562 2563 stmmac_release_tx_desc(priv, p, priv->mode); 2564 2565 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2566 } 2567 tx_q->dirty_tx = entry; 2568 2569 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2570 pkts_compl, bytes_compl); 2571 2572 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2573 queue))) && 2574 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2575 2576 netif_dbg(priv, tx_done, priv->dev, 2577 "%s: restart transmit\n", __func__); 2578 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2579 } 2580 2581 if (tx_q->xsk_pool) { 2582 bool work_done; 2583 2584 if (tx_q->xsk_frames_done) 2585 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2586 2587 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2588 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2589 2590 /* For XSK TX, we try to send as many as possible. 2591 * If XSK work done (XSK TX desc empty and budget still 2592 * available), return "budget - 1" to reenable TX IRQ. 2593 * Else, return "budget" to make NAPI continue polling. 2594 */ 2595 work_done = stmmac_xdp_xmit_zc(priv, queue, 2596 STMMAC_XSK_TX_BUDGET_MAX); 2597 if (work_done) 2598 xmits = budget - 1; 2599 else 2600 xmits = budget; 2601 } 2602 2603 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2604 priv->eee_sw_timer_en) { 2605 stmmac_enable_eee_mode(priv); 2606 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2607 } 2608 2609 /* We still have pending packets, let's call for a new scheduling */ 2610 if (tx_q->dirty_tx != tx_q->cur_tx) 2611 hrtimer_start(&tx_q->txtimer, 2612 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2613 HRTIMER_MODE_REL); 2614 2615 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2616 2617 /* Combine decisions from TX clean and XSK TX */ 2618 return max(count, xmits); 2619 } 2620 2621 /** 2622 * stmmac_tx_err - to manage the tx error 2623 * @priv: driver private structure 2624 * @chan: channel index 2625 * Description: it cleans the descriptors and restarts the transmission 2626 * in case of transmission errors. 2627 */ 2628 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2629 { 2630 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2631 2632 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2633 2634 stmmac_stop_tx_dma(priv, chan); 2635 dma_free_tx_skbufs(priv, chan); 2636 stmmac_clear_tx_descriptors(priv, chan); 2637 tx_q->dirty_tx = 0; 2638 tx_q->cur_tx = 0; 2639 tx_q->mss = 0; 2640 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2641 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2642 tx_q->dma_tx_phy, chan); 2643 stmmac_start_tx_dma(priv, chan); 2644 2645 priv->dev->stats.tx_errors++; 2646 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2647 } 2648 2649 /** 2650 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2651 * @priv: driver private structure 2652 * @txmode: TX operating mode 2653 * @rxmode: RX operating mode 2654 * @chan: channel index 2655 * Description: it is used for configuring of the DMA operation mode in 2656 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2657 * mode. 2658 */ 2659 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2660 u32 rxmode, u32 chan) 2661 { 2662 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2663 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2664 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2665 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2666 int rxfifosz = priv->plat->rx_fifo_size; 2667 int txfifosz = priv->plat->tx_fifo_size; 2668 2669 if (rxfifosz == 0) 2670 rxfifosz = priv->dma_cap.rx_fifo_size; 2671 if (txfifosz == 0) 2672 txfifosz = priv->dma_cap.tx_fifo_size; 2673 2674 /* Adjust for real per queue fifo size */ 2675 rxfifosz /= rx_channels_count; 2676 txfifosz /= tx_channels_count; 2677 2678 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2679 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2680 } 2681 2682 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2683 { 2684 int ret; 2685 2686 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2687 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2688 if (ret && (ret != -EINVAL)) { 2689 stmmac_global_err(priv); 2690 return true; 2691 } 2692 2693 return false; 2694 } 2695 2696 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2697 { 2698 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2699 &priv->xstats, chan, dir); 2700 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2701 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2702 struct stmmac_channel *ch = &priv->channel[chan]; 2703 struct napi_struct *rx_napi; 2704 struct napi_struct *tx_napi; 2705 unsigned long flags; 2706 2707 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2708 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2709 2710 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2711 if (napi_schedule_prep(rx_napi)) { 2712 spin_lock_irqsave(&ch->lock, flags); 2713 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2714 spin_unlock_irqrestore(&ch->lock, flags); 2715 __napi_schedule(rx_napi); 2716 } 2717 } 2718 2719 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2720 if (napi_schedule_prep(tx_napi)) { 2721 spin_lock_irqsave(&ch->lock, flags); 2722 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2723 spin_unlock_irqrestore(&ch->lock, flags); 2724 __napi_schedule(tx_napi); 2725 } 2726 } 2727 2728 return status; 2729 } 2730 2731 /** 2732 * stmmac_dma_interrupt - DMA ISR 2733 * @priv: driver private structure 2734 * Description: this is the DMA ISR. It is called by the main ISR. 2735 * It calls the dwmac dma routine and schedule poll method in case of some 2736 * work can be done. 2737 */ 2738 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2739 { 2740 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2741 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2742 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2743 tx_channel_count : rx_channel_count; 2744 u32 chan; 2745 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2746 2747 /* Make sure we never check beyond our status buffer. */ 2748 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2749 channels_to_check = ARRAY_SIZE(status); 2750 2751 for (chan = 0; chan < channels_to_check; chan++) 2752 status[chan] = stmmac_napi_check(priv, chan, 2753 DMA_DIR_RXTX); 2754 2755 for (chan = 0; chan < tx_channel_count; chan++) { 2756 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2757 /* Try to bump up the dma threshold on this failure */ 2758 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2759 (tc <= 256)) { 2760 tc += 64; 2761 if (priv->plat->force_thresh_dma_mode) 2762 stmmac_set_dma_operation_mode(priv, 2763 tc, 2764 tc, 2765 chan); 2766 else 2767 stmmac_set_dma_operation_mode(priv, 2768 tc, 2769 SF_DMA_MODE, 2770 chan); 2771 priv->xstats.threshold = tc; 2772 } 2773 } else if (unlikely(status[chan] == tx_hard_error)) { 2774 stmmac_tx_err(priv, chan); 2775 } 2776 } 2777 } 2778 2779 /** 2780 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2781 * @priv: driver private structure 2782 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2783 */ 2784 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2785 { 2786 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2787 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2788 2789 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2790 2791 if (priv->dma_cap.rmon) { 2792 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2793 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2794 } else 2795 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2796 } 2797 2798 /** 2799 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2800 * @priv: driver private structure 2801 * Description: 2802 * new GMAC chip generations have a new register to indicate the 2803 * presence of the optional feature/functions. 2804 * This can be also used to override the value passed through the 2805 * platform and necessary for old MAC10/100 and GMAC chips. 2806 */ 2807 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2808 { 2809 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2810 } 2811 2812 /** 2813 * stmmac_check_ether_addr - check if the MAC addr is valid 2814 * @priv: driver private structure 2815 * Description: 2816 * it is to verify if the MAC address is valid, in case of failures it 2817 * generates a random MAC address 2818 */ 2819 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2820 { 2821 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2822 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2823 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2824 eth_hw_addr_random(priv->dev); 2825 dev_info(priv->device, "device MAC address %pM\n", 2826 priv->dev->dev_addr); 2827 } 2828 } 2829 2830 /** 2831 * stmmac_init_dma_engine - DMA init. 2832 * @priv: driver private structure 2833 * Description: 2834 * It inits the DMA invoking the specific MAC/GMAC callback. 2835 * Some DMA parameters can be passed from the platform; 2836 * in case of these are not passed a default is kept for the MAC or GMAC. 2837 */ 2838 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2839 { 2840 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2841 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2842 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2843 struct stmmac_rx_queue *rx_q; 2844 struct stmmac_tx_queue *tx_q; 2845 u32 chan = 0; 2846 int atds = 0; 2847 int ret = 0; 2848 2849 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2850 dev_err(priv->device, "Invalid DMA configuration\n"); 2851 return -EINVAL; 2852 } 2853 2854 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2855 atds = 1; 2856 2857 ret = stmmac_reset(priv, priv->ioaddr); 2858 if (ret) { 2859 dev_err(priv->device, "Failed to reset the dma\n"); 2860 return ret; 2861 } 2862 2863 /* DMA Configuration */ 2864 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2865 2866 if (priv->plat->axi) 2867 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2868 2869 /* DMA CSR Channel configuration */ 2870 for (chan = 0; chan < dma_csr_ch; chan++) 2871 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2872 2873 /* DMA RX Channel Configuration */ 2874 for (chan = 0; chan < rx_channels_count; chan++) { 2875 rx_q = &priv->rx_queue[chan]; 2876 2877 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2878 rx_q->dma_rx_phy, chan); 2879 2880 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2881 (rx_q->buf_alloc_num * 2882 sizeof(struct dma_desc)); 2883 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2884 rx_q->rx_tail_addr, chan); 2885 } 2886 2887 /* DMA TX Channel Configuration */ 2888 for (chan = 0; chan < tx_channels_count; chan++) { 2889 tx_q = &priv->tx_queue[chan]; 2890 2891 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2892 tx_q->dma_tx_phy, chan); 2893 2894 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2895 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2896 tx_q->tx_tail_addr, chan); 2897 } 2898 2899 return ret; 2900 } 2901 2902 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2903 { 2904 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2905 2906 hrtimer_start(&tx_q->txtimer, 2907 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2908 HRTIMER_MODE_REL); 2909 } 2910 2911 /** 2912 * stmmac_tx_timer - mitigation sw timer for tx. 2913 * @t: data pointer 2914 * Description: 2915 * This is the timer handler to directly invoke the stmmac_tx_clean. 2916 */ 2917 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2918 { 2919 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2920 struct stmmac_priv *priv = tx_q->priv_data; 2921 struct stmmac_channel *ch; 2922 struct napi_struct *napi; 2923 2924 ch = &priv->channel[tx_q->queue_index]; 2925 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2926 2927 if (likely(napi_schedule_prep(napi))) { 2928 unsigned long flags; 2929 2930 spin_lock_irqsave(&ch->lock, flags); 2931 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2932 spin_unlock_irqrestore(&ch->lock, flags); 2933 __napi_schedule(napi); 2934 } 2935 2936 return HRTIMER_NORESTART; 2937 } 2938 2939 /** 2940 * stmmac_init_coalesce - init mitigation options. 2941 * @priv: driver private structure 2942 * Description: 2943 * This inits the coalesce parameters: i.e. timer rate, 2944 * timer handler and default threshold used for enabling the 2945 * interrupt on completion bit. 2946 */ 2947 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2948 { 2949 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2950 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2951 u32 chan; 2952 2953 for (chan = 0; chan < tx_channel_count; chan++) { 2954 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2955 2956 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 2957 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 2958 2959 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2960 tx_q->txtimer.function = stmmac_tx_timer; 2961 } 2962 2963 for (chan = 0; chan < rx_channel_count; chan++) 2964 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 2965 } 2966 2967 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2968 { 2969 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2970 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2971 u32 chan; 2972 2973 /* set TX ring length */ 2974 for (chan = 0; chan < tx_channels_count; chan++) 2975 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2976 (priv->dma_tx_size - 1), chan); 2977 2978 /* set RX ring length */ 2979 for (chan = 0; chan < rx_channels_count; chan++) 2980 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2981 (priv->dma_rx_size - 1), chan); 2982 } 2983 2984 /** 2985 * stmmac_set_tx_queue_weight - Set TX queue weight 2986 * @priv: driver private structure 2987 * Description: It is used for setting TX queues weight 2988 */ 2989 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2990 { 2991 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2992 u32 weight; 2993 u32 queue; 2994 2995 for (queue = 0; queue < tx_queues_count; queue++) { 2996 weight = priv->plat->tx_queues_cfg[queue].weight; 2997 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2998 } 2999 } 3000 3001 /** 3002 * stmmac_configure_cbs - Configure CBS in TX queue 3003 * @priv: driver private structure 3004 * Description: It is used for configuring CBS in AVB TX queues 3005 */ 3006 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3007 { 3008 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3009 u32 mode_to_use; 3010 u32 queue; 3011 3012 /* queue 0 is reserved for legacy traffic */ 3013 for (queue = 1; queue < tx_queues_count; queue++) { 3014 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3015 if (mode_to_use == MTL_QUEUE_DCB) 3016 continue; 3017 3018 stmmac_config_cbs(priv, priv->hw, 3019 priv->plat->tx_queues_cfg[queue].send_slope, 3020 priv->plat->tx_queues_cfg[queue].idle_slope, 3021 priv->plat->tx_queues_cfg[queue].high_credit, 3022 priv->plat->tx_queues_cfg[queue].low_credit, 3023 queue); 3024 } 3025 } 3026 3027 /** 3028 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3029 * @priv: driver private structure 3030 * Description: It is used for mapping RX queues to RX dma channels 3031 */ 3032 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3033 { 3034 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3035 u32 queue; 3036 u32 chan; 3037 3038 for (queue = 0; queue < rx_queues_count; queue++) { 3039 chan = priv->plat->rx_queues_cfg[queue].chan; 3040 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3041 } 3042 } 3043 3044 /** 3045 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3046 * @priv: driver private structure 3047 * Description: It is used for configuring the RX Queue Priority 3048 */ 3049 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3050 { 3051 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3052 u32 queue; 3053 u32 prio; 3054 3055 for (queue = 0; queue < rx_queues_count; queue++) { 3056 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3057 continue; 3058 3059 prio = priv->plat->rx_queues_cfg[queue].prio; 3060 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3061 } 3062 } 3063 3064 /** 3065 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3066 * @priv: driver private structure 3067 * Description: It is used for configuring the TX Queue Priority 3068 */ 3069 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3070 { 3071 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3072 u32 queue; 3073 u32 prio; 3074 3075 for (queue = 0; queue < tx_queues_count; queue++) { 3076 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3077 continue; 3078 3079 prio = priv->plat->tx_queues_cfg[queue].prio; 3080 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3081 } 3082 } 3083 3084 /** 3085 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3086 * @priv: driver private structure 3087 * Description: It is used for configuring the RX queue routing 3088 */ 3089 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3090 { 3091 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3092 u32 queue; 3093 u8 packet; 3094 3095 for (queue = 0; queue < rx_queues_count; queue++) { 3096 /* no specific packet type routing specified for the queue */ 3097 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3098 continue; 3099 3100 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3101 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3102 } 3103 } 3104 3105 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3106 { 3107 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3108 priv->rss.enable = false; 3109 return; 3110 } 3111 3112 if (priv->dev->features & NETIF_F_RXHASH) 3113 priv->rss.enable = true; 3114 else 3115 priv->rss.enable = false; 3116 3117 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3118 priv->plat->rx_queues_to_use); 3119 } 3120 3121 /** 3122 * stmmac_mtl_configuration - Configure MTL 3123 * @priv: driver private structure 3124 * Description: It is used for configurring MTL 3125 */ 3126 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3127 { 3128 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3129 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3130 3131 if (tx_queues_count > 1) 3132 stmmac_set_tx_queue_weight(priv); 3133 3134 /* Configure MTL RX algorithms */ 3135 if (rx_queues_count > 1) 3136 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3137 priv->plat->rx_sched_algorithm); 3138 3139 /* Configure MTL TX algorithms */ 3140 if (tx_queues_count > 1) 3141 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3142 priv->plat->tx_sched_algorithm); 3143 3144 /* Configure CBS in AVB TX queues */ 3145 if (tx_queues_count > 1) 3146 stmmac_configure_cbs(priv); 3147 3148 /* Map RX MTL to DMA channels */ 3149 stmmac_rx_queue_dma_chan_map(priv); 3150 3151 /* Enable MAC RX Queues */ 3152 stmmac_mac_enable_rx_queues(priv); 3153 3154 /* Set RX priorities */ 3155 if (rx_queues_count > 1) 3156 stmmac_mac_config_rx_queues_prio(priv); 3157 3158 /* Set TX priorities */ 3159 if (tx_queues_count > 1) 3160 stmmac_mac_config_tx_queues_prio(priv); 3161 3162 /* Set RX routing */ 3163 if (rx_queues_count > 1) 3164 stmmac_mac_config_rx_queues_routing(priv); 3165 3166 /* Receive Side Scaling */ 3167 if (rx_queues_count > 1) 3168 stmmac_mac_config_rss(priv); 3169 } 3170 3171 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3172 { 3173 if (priv->dma_cap.asp) { 3174 netdev_info(priv->dev, "Enabling Safety Features\n"); 3175 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 3176 } else { 3177 netdev_info(priv->dev, "No Safety Features support found\n"); 3178 } 3179 } 3180 3181 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3182 { 3183 char *name; 3184 3185 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3186 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3187 3188 name = priv->wq_name; 3189 sprintf(name, "%s-fpe", priv->dev->name); 3190 3191 priv->fpe_wq = create_singlethread_workqueue(name); 3192 if (!priv->fpe_wq) { 3193 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3194 3195 return -ENOMEM; 3196 } 3197 netdev_info(priv->dev, "FPE workqueue start"); 3198 3199 return 0; 3200 } 3201 3202 /** 3203 * stmmac_hw_setup - setup mac in a usable state. 3204 * @dev : pointer to the device structure. 3205 * @init_ptp: initialize PTP if set 3206 * Description: 3207 * this is the main function to setup the HW in a usable state because the 3208 * dma engine is reset, the core registers are configured (e.g. AXI, 3209 * Checksum features, timers). The DMA is ready to start receiving and 3210 * transmitting. 3211 * Return value: 3212 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3213 * file on failure. 3214 */ 3215 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 3216 { 3217 struct stmmac_priv *priv = netdev_priv(dev); 3218 u32 rx_cnt = priv->plat->rx_queues_to_use; 3219 u32 tx_cnt = priv->plat->tx_queues_to_use; 3220 bool sph_en; 3221 u32 chan; 3222 int ret; 3223 3224 /* DMA initialization and SW reset */ 3225 ret = stmmac_init_dma_engine(priv); 3226 if (ret < 0) { 3227 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3228 __func__); 3229 return ret; 3230 } 3231 3232 /* Copy the MAC addr into the HW */ 3233 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3234 3235 /* PS and related bits will be programmed according to the speed */ 3236 if (priv->hw->pcs) { 3237 int speed = priv->plat->mac_port_sel_speed; 3238 3239 if ((speed == SPEED_10) || (speed == SPEED_100) || 3240 (speed == SPEED_1000)) { 3241 priv->hw->ps = speed; 3242 } else { 3243 dev_warn(priv->device, "invalid port speed\n"); 3244 priv->hw->ps = 0; 3245 } 3246 } 3247 3248 /* Initialize the MAC Core */ 3249 stmmac_core_init(priv, priv->hw, dev); 3250 3251 /* Initialize MTL*/ 3252 stmmac_mtl_configuration(priv); 3253 3254 /* Initialize Safety Features */ 3255 stmmac_safety_feat_configuration(priv); 3256 3257 ret = stmmac_rx_ipc(priv, priv->hw); 3258 if (!ret) { 3259 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3260 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3261 priv->hw->rx_csum = 0; 3262 } 3263 3264 /* Enable the MAC Rx/Tx */ 3265 stmmac_mac_set(priv, priv->ioaddr, true); 3266 3267 /* Set the HW DMA mode and the COE */ 3268 stmmac_dma_operation_mode(priv); 3269 3270 stmmac_mmc_setup(priv); 3271 3272 if (init_ptp) { 3273 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3274 if (ret < 0) 3275 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 3276 3277 ret = stmmac_init_ptp(priv); 3278 if (ret == -EOPNOTSUPP) 3279 netdev_warn(priv->dev, "PTP not supported by HW\n"); 3280 else if (ret) 3281 netdev_warn(priv->dev, "PTP init failed\n"); 3282 } 3283 3284 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3285 3286 /* Convert the timer from msec to usec */ 3287 if (!priv->tx_lpi_timer) 3288 priv->tx_lpi_timer = eee_timer * 1000; 3289 3290 if (priv->use_riwt) { 3291 u32 queue; 3292 3293 for (queue = 0; queue < rx_cnt; queue++) { 3294 if (!priv->rx_riwt[queue]) 3295 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3296 3297 stmmac_rx_watchdog(priv, priv->ioaddr, 3298 priv->rx_riwt[queue], queue); 3299 } 3300 } 3301 3302 if (priv->hw->pcs) 3303 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3304 3305 /* set TX and RX rings length */ 3306 stmmac_set_rings_length(priv); 3307 3308 /* Enable TSO */ 3309 if (priv->tso) { 3310 for (chan = 0; chan < tx_cnt; chan++) { 3311 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3312 3313 /* TSO and TBS cannot co-exist */ 3314 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3315 continue; 3316 3317 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3318 } 3319 } 3320 3321 /* Enable Split Header */ 3322 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3323 for (chan = 0; chan < rx_cnt; chan++) 3324 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3325 3326 3327 /* VLAN Tag Insertion */ 3328 if (priv->dma_cap.vlins) 3329 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3330 3331 /* TBS */ 3332 for (chan = 0; chan < tx_cnt; chan++) { 3333 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3334 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3335 3336 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3337 } 3338 3339 /* Configure real RX and TX queues */ 3340 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3341 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3342 3343 /* Start the ball rolling... */ 3344 stmmac_start_all_dma(priv); 3345 3346 if (priv->dma_cap.fpesel) { 3347 stmmac_fpe_start_wq(priv); 3348 3349 if (priv->plat->fpe_cfg->enable) 3350 stmmac_fpe_handshake(priv, true); 3351 } 3352 3353 return 0; 3354 } 3355 3356 static void stmmac_hw_teardown(struct net_device *dev) 3357 { 3358 struct stmmac_priv *priv = netdev_priv(dev); 3359 3360 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3361 } 3362 3363 static void stmmac_free_irq(struct net_device *dev, 3364 enum request_irq_err irq_err, int irq_idx) 3365 { 3366 struct stmmac_priv *priv = netdev_priv(dev); 3367 int j; 3368 3369 switch (irq_err) { 3370 case REQ_IRQ_ERR_ALL: 3371 irq_idx = priv->plat->tx_queues_to_use; 3372 fallthrough; 3373 case REQ_IRQ_ERR_TX: 3374 for (j = irq_idx - 1; j >= 0; j--) { 3375 if (priv->tx_irq[j] > 0) { 3376 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3377 free_irq(priv->tx_irq[j], &priv->tx_queue[j]); 3378 } 3379 } 3380 irq_idx = priv->plat->rx_queues_to_use; 3381 fallthrough; 3382 case REQ_IRQ_ERR_RX: 3383 for (j = irq_idx - 1; j >= 0; j--) { 3384 if (priv->rx_irq[j] > 0) { 3385 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3386 free_irq(priv->rx_irq[j], &priv->rx_queue[j]); 3387 } 3388 } 3389 3390 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3391 free_irq(priv->sfty_ue_irq, dev); 3392 fallthrough; 3393 case REQ_IRQ_ERR_SFTY_UE: 3394 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3395 free_irq(priv->sfty_ce_irq, dev); 3396 fallthrough; 3397 case REQ_IRQ_ERR_SFTY_CE: 3398 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3399 free_irq(priv->lpi_irq, dev); 3400 fallthrough; 3401 case REQ_IRQ_ERR_LPI: 3402 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3403 free_irq(priv->wol_irq, dev); 3404 fallthrough; 3405 case REQ_IRQ_ERR_WOL: 3406 free_irq(dev->irq, dev); 3407 fallthrough; 3408 case REQ_IRQ_ERR_MAC: 3409 case REQ_IRQ_ERR_NO: 3410 /* If MAC IRQ request error, no more IRQ to free */ 3411 break; 3412 } 3413 } 3414 3415 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3416 { 3417 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3418 struct stmmac_priv *priv = netdev_priv(dev); 3419 cpumask_t cpu_mask; 3420 int irq_idx = 0; 3421 char *int_name; 3422 int ret; 3423 int i; 3424 3425 /* For common interrupt */ 3426 int_name = priv->int_name_mac; 3427 sprintf(int_name, "%s:%s", dev->name, "mac"); 3428 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3429 0, int_name, dev); 3430 if (unlikely(ret < 0)) { 3431 netdev_err(priv->dev, 3432 "%s: alloc mac MSI %d (error: %d)\n", 3433 __func__, dev->irq, ret); 3434 irq_err = REQ_IRQ_ERR_MAC; 3435 goto irq_error; 3436 } 3437 3438 /* Request the Wake IRQ in case of another line 3439 * is used for WoL 3440 */ 3441 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3442 int_name = priv->int_name_wol; 3443 sprintf(int_name, "%s:%s", dev->name, "wol"); 3444 ret = request_irq(priv->wol_irq, 3445 stmmac_mac_interrupt, 3446 0, int_name, dev); 3447 if (unlikely(ret < 0)) { 3448 netdev_err(priv->dev, 3449 "%s: alloc wol MSI %d (error: %d)\n", 3450 __func__, priv->wol_irq, ret); 3451 irq_err = REQ_IRQ_ERR_WOL; 3452 goto irq_error; 3453 } 3454 } 3455 3456 /* Request the LPI IRQ in case of another line 3457 * is used for LPI 3458 */ 3459 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3460 int_name = priv->int_name_lpi; 3461 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3462 ret = request_irq(priv->lpi_irq, 3463 stmmac_mac_interrupt, 3464 0, int_name, dev); 3465 if (unlikely(ret < 0)) { 3466 netdev_err(priv->dev, 3467 "%s: alloc lpi MSI %d (error: %d)\n", 3468 __func__, priv->lpi_irq, ret); 3469 irq_err = REQ_IRQ_ERR_LPI; 3470 goto irq_error; 3471 } 3472 } 3473 3474 /* Request the Safety Feature Correctible Error line in 3475 * case of another line is used 3476 */ 3477 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3478 int_name = priv->int_name_sfty_ce; 3479 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3480 ret = request_irq(priv->sfty_ce_irq, 3481 stmmac_safety_interrupt, 3482 0, int_name, dev); 3483 if (unlikely(ret < 0)) { 3484 netdev_err(priv->dev, 3485 "%s: alloc sfty ce MSI %d (error: %d)\n", 3486 __func__, priv->sfty_ce_irq, ret); 3487 irq_err = REQ_IRQ_ERR_SFTY_CE; 3488 goto irq_error; 3489 } 3490 } 3491 3492 /* Request the Safety Feature Uncorrectible Error line in 3493 * case of another line is used 3494 */ 3495 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3496 int_name = priv->int_name_sfty_ue; 3497 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3498 ret = request_irq(priv->sfty_ue_irq, 3499 stmmac_safety_interrupt, 3500 0, int_name, dev); 3501 if (unlikely(ret < 0)) { 3502 netdev_err(priv->dev, 3503 "%s: alloc sfty ue MSI %d (error: %d)\n", 3504 __func__, priv->sfty_ue_irq, ret); 3505 irq_err = REQ_IRQ_ERR_SFTY_UE; 3506 goto irq_error; 3507 } 3508 } 3509 3510 /* Request Rx MSI irq */ 3511 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3512 if (priv->rx_irq[i] == 0) 3513 continue; 3514 3515 int_name = priv->int_name_rx_irq[i]; 3516 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3517 ret = request_irq(priv->rx_irq[i], 3518 stmmac_msi_intr_rx, 3519 0, int_name, &priv->rx_queue[i]); 3520 if (unlikely(ret < 0)) { 3521 netdev_err(priv->dev, 3522 "%s: alloc rx-%d MSI %d (error: %d)\n", 3523 __func__, i, priv->rx_irq[i], ret); 3524 irq_err = REQ_IRQ_ERR_RX; 3525 irq_idx = i; 3526 goto irq_error; 3527 } 3528 cpumask_clear(&cpu_mask); 3529 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3530 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3531 } 3532 3533 /* Request Tx MSI irq */ 3534 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3535 if (priv->tx_irq[i] == 0) 3536 continue; 3537 3538 int_name = priv->int_name_tx_irq[i]; 3539 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3540 ret = request_irq(priv->tx_irq[i], 3541 stmmac_msi_intr_tx, 3542 0, int_name, &priv->tx_queue[i]); 3543 if (unlikely(ret < 0)) { 3544 netdev_err(priv->dev, 3545 "%s: alloc tx-%d MSI %d (error: %d)\n", 3546 __func__, i, priv->tx_irq[i], ret); 3547 irq_err = REQ_IRQ_ERR_TX; 3548 irq_idx = i; 3549 goto irq_error; 3550 } 3551 cpumask_clear(&cpu_mask); 3552 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3553 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3554 } 3555 3556 return 0; 3557 3558 irq_error: 3559 stmmac_free_irq(dev, irq_err, irq_idx); 3560 return ret; 3561 } 3562 3563 static int stmmac_request_irq_single(struct net_device *dev) 3564 { 3565 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3566 struct stmmac_priv *priv = netdev_priv(dev); 3567 int ret; 3568 3569 ret = request_irq(dev->irq, stmmac_interrupt, 3570 IRQF_SHARED, dev->name, dev); 3571 if (unlikely(ret < 0)) { 3572 netdev_err(priv->dev, 3573 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3574 __func__, dev->irq, ret); 3575 irq_err = REQ_IRQ_ERR_MAC; 3576 return ret; 3577 } 3578 3579 /* Request the Wake IRQ in case of another line 3580 * is used for WoL 3581 */ 3582 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3583 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3584 IRQF_SHARED, dev->name, dev); 3585 if (unlikely(ret < 0)) { 3586 netdev_err(priv->dev, 3587 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3588 __func__, priv->wol_irq, ret); 3589 irq_err = REQ_IRQ_ERR_WOL; 3590 return ret; 3591 } 3592 } 3593 3594 /* Request the IRQ lines */ 3595 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3596 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3597 IRQF_SHARED, dev->name, dev); 3598 if (unlikely(ret < 0)) { 3599 netdev_err(priv->dev, 3600 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3601 __func__, priv->lpi_irq, ret); 3602 irq_err = REQ_IRQ_ERR_LPI; 3603 goto irq_error; 3604 } 3605 } 3606 3607 return 0; 3608 3609 irq_error: 3610 stmmac_free_irq(dev, irq_err, 0); 3611 return ret; 3612 } 3613 3614 static int stmmac_request_irq(struct net_device *dev) 3615 { 3616 struct stmmac_priv *priv = netdev_priv(dev); 3617 int ret; 3618 3619 /* Request the IRQ lines */ 3620 if (priv->plat->multi_msi_en) 3621 ret = stmmac_request_irq_multi_msi(dev); 3622 else 3623 ret = stmmac_request_irq_single(dev); 3624 3625 return ret; 3626 } 3627 3628 /** 3629 * stmmac_open - open entry point of the driver 3630 * @dev : pointer to the device structure. 3631 * Description: 3632 * This function is the open entry point of the driver. 3633 * Return value: 3634 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3635 * file on failure. 3636 */ 3637 int stmmac_open(struct net_device *dev) 3638 { 3639 struct stmmac_priv *priv = netdev_priv(dev); 3640 int bfsize = 0; 3641 u32 chan; 3642 int ret; 3643 3644 ret = pm_runtime_get_sync(priv->device); 3645 if (ret < 0) { 3646 pm_runtime_put_noidle(priv->device); 3647 return ret; 3648 } 3649 3650 if (priv->hw->pcs != STMMAC_PCS_TBI && 3651 priv->hw->pcs != STMMAC_PCS_RTBI && 3652 priv->hw->xpcs_args.an_mode != DW_AN_C73) { 3653 ret = stmmac_init_phy(dev); 3654 if (ret) { 3655 netdev_err(priv->dev, 3656 "%s: Cannot attach to PHY (error: %d)\n", 3657 __func__, ret); 3658 goto init_phy_error; 3659 } 3660 } 3661 3662 /* Extra statistics */ 3663 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3664 priv->xstats.threshold = tc; 3665 3666 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 3667 if (bfsize < 0) 3668 bfsize = 0; 3669 3670 if (bfsize < BUF_SIZE_16KiB) 3671 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 3672 3673 priv->dma_buf_sz = bfsize; 3674 buf_sz = bfsize; 3675 3676 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3677 3678 if (!priv->dma_tx_size) 3679 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3680 if (!priv->dma_rx_size) 3681 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3682 3683 /* Earlier check for TBS */ 3684 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3685 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3686 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3687 3688 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3689 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3690 } 3691 3692 ret = alloc_dma_desc_resources(priv); 3693 if (ret < 0) { 3694 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3695 __func__); 3696 goto dma_desc_error; 3697 } 3698 3699 ret = init_dma_desc_rings(dev, GFP_KERNEL); 3700 if (ret < 0) { 3701 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3702 __func__); 3703 goto init_error; 3704 } 3705 3706 ret = stmmac_hw_setup(dev, true); 3707 if (ret < 0) { 3708 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3709 goto init_error; 3710 } 3711 3712 stmmac_init_coalesce(priv); 3713 3714 phylink_start(priv->phylink); 3715 /* We may have called phylink_speed_down before */ 3716 phylink_speed_up(priv->phylink); 3717 3718 ret = stmmac_request_irq(dev); 3719 if (ret) 3720 goto irq_error; 3721 3722 stmmac_enable_all_queues(priv); 3723 netif_tx_start_all_queues(priv->dev); 3724 3725 return 0; 3726 3727 irq_error: 3728 phylink_stop(priv->phylink); 3729 3730 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3731 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3732 3733 stmmac_hw_teardown(dev); 3734 init_error: 3735 free_dma_desc_resources(priv); 3736 dma_desc_error: 3737 phylink_disconnect_phy(priv->phylink); 3738 init_phy_error: 3739 pm_runtime_put(priv->device); 3740 return ret; 3741 } 3742 3743 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3744 { 3745 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3746 3747 if (priv->fpe_wq) 3748 destroy_workqueue(priv->fpe_wq); 3749 3750 netdev_info(priv->dev, "FPE workqueue stop"); 3751 } 3752 3753 /** 3754 * stmmac_release - close entry point of the driver 3755 * @dev : device pointer. 3756 * Description: 3757 * This is the stop entry point of the driver. 3758 */ 3759 int stmmac_release(struct net_device *dev) 3760 { 3761 struct stmmac_priv *priv = netdev_priv(dev); 3762 u32 chan; 3763 3764 if (device_may_wakeup(priv->device)) 3765 phylink_speed_down(priv->phylink, false); 3766 /* Stop and disconnect the PHY */ 3767 phylink_stop(priv->phylink); 3768 phylink_disconnect_phy(priv->phylink); 3769 3770 stmmac_disable_all_queues(priv); 3771 3772 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3773 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3774 3775 /* Free the IRQ lines */ 3776 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3777 3778 if (priv->eee_enabled) { 3779 priv->tx_path_in_lpi_mode = false; 3780 del_timer_sync(&priv->eee_ctrl_timer); 3781 } 3782 3783 /* Stop TX/RX DMA and clear the descriptors */ 3784 stmmac_stop_all_dma(priv); 3785 3786 /* Release and free the Rx/Tx resources */ 3787 free_dma_desc_resources(priv); 3788 3789 /* Disable the MAC Rx/Tx */ 3790 stmmac_mac_set(priv, priv->ioaddr, false); 3791 3792 netif_carrier_off(dev); 3793 3794 stmmac_release_ptp(priv); 3795 3796 pm_runtime_put(priv->device); 3797 3798 if (priv->dma_cap.fpesel) 3799 stmmac_fpe_stop_wq(priv); 3800 3801 return 0; 3802 } 3803 3804 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3805 struct stmmac_tx_queue *tx_q) 3806 { 3807 u16 tag = 0x0, inner_tag = 0x0; 3808 u32 inner_type = 0x0; 3809 struct dma_desc *p; 3810 3811 if (!priv->dma_cap.vlins) 3812 return false; 3813 if (!skb_vlan_tag_present(skb)) 3814 return false; 3815 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3816 inner_tag = skb_vlan_tag_get(skb); 3817 inner_type = STMMAC_VLAN_INSERT; 3818 } 3819 3820 tag = skb_vlan_tag_get(skb); 3821 3822 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3823 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3824 else 3825 p = &tx_q->dma_tx[tx_q->cur_tx]; 3826 3827 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3828 return false; 3829 3830 stmmac_set_tx_owner(priv, p); 3831 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3832 return true; 3833 } 3834 3835 /** 3836 * stmmac_tso_allocator - close entry point of the driver 3837 * @priv: driver private structure 3838 * @des: buffer start address 3839 * @total_len: total length to fill in descriptors 3840 * @last_segment: condition for the last descriptor 3841 * @queue: TX queue index 3842 * Description: 3843 * This function fills descriptor and request new descriptors according to 3844 * buffer length to fill 3845 */ 3846 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3847 int total_len, bool last_segment, u32 queue) 3848 { 3849 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3850 struct dma_desc *desc; 3851 u32 buff_size; 3852 int tmp_len; 3853 3854 tmp_len = total_len; 3855 3856 while (tmp_len > 0) { 3857 dma_addr_t curr_addr; 3858 3859 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3860 priv->dma_tx_size); 3861 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3862 3863 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3864 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3865 else 3866 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3867 3868 curr_addr = des + (total_len - tmp_len); 3869 if (priv->dma_cap.addr64 <= 32) 3870 desc->des0 = cpu_to_le32(curr_addr); 3871 else 3872 stmmac_set_desc_addr(priv, desc, curr_addr); 3873 3874 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3875 TSO_MAX_BUFF_SIZE : tmp_len; 3876 3877 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3878 0, 1, 3879 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3880 0, 0); 3881 3882 tmp_len -= TSO_MAX_BUFF_SIZE; 3883 } 3884 } 3885 3886 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 3887 { 3888 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3889 int desc_size; 3890 3891 if (likely(priv->extend_desc)) 3892 desc_size = sizeof(struct dma_extended_desc); 3893 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3894 desc_size = sizeof(struct dma_edesc); 3895 else 3896 desc_size = sizeof(struct dma_desc); 3897 3898 /* The own bit must be the latest setting done when prepare the 3899 * descriptor and then barrier is needed to make sure that 3900 * all is coherent before granting the DMA engine. 3901 */ 3902 wmb(); 3903 3904 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3905 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3906 } 3907 3908 /** 3909 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3910 * @skb : the socket buffer 3911 * @dev : device pointer 3912 * Description: this is the transmit function that is called on TSO frames 3913 * (support available on GMAC4 and newer chips). 3914 * Diagram below show the ring programming in case of TSO frames: 3915 * 3916 * First Descriptor 3917 * -------- 3918 * | DES0 |---> buffer1 = L2/L3/L4 header 3919 * | DES1 |---> TCP Payload (can continue on next descr...) 3920 * | DES2 |---> buffer 1 and 2 len 3921 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3922 * -------- 3923 * | 3924 * ... 3925 * | 3926 * -------- 3927 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3928 * | DES1 | --| 3929 * | DES2 | --> buffer 1 and 2 len 3930 * | DES3 | 3931 * -------- 3932 * 3933 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3934 */ 3935 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3936 { 3937 struct dma_desc *desc, *first, *mss_desc = NULL; 3938 struct stmmac_priv *priv = netdev_priv(dev); 3939 int nfrags = skb_shinfo(skb)->nr_frags; 3940 u32 queue = skb_get_queue_mapping(skb); 3941 unsigned int first_entry, tx_packets; 3942 int tmp_pay_len = 0, first_tx; 3943 struct stmmac_tx_queue *tx_q; 3944 bool has_vlan, set_ic; 3945 u8 proto_hdr_len, hdr; 3946 u32 pay_len, mss; 3947 dma_addr_t des; 3948 int i; 3949 3950 tx_q = &priv->tx_queue[queue]; 3951 first_tx = tx_q->cur_tx; 3952 3953 /* Compute header lengths */ 3954 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3955 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3956 hdr = sizeof(struct udphdr); 3957 } else { 3958 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3959 hdr = tcp_hdrlen(skb); 3960 } 3961 3962 /* Desc availability based on threshold should be enough safe */ 3963 if (unlikely(stmmac_tx_avail(priv, queue) < 3964 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3965 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3966 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3967 queue)); 3968 /* This is a hard error, log it. */ 3969 netdev_err(priv->dev, 3970 "%s: Tx Ring full when queue awake\n", 3971 __func__); 3972 } 3973 return NETDEV_TX_BUSY; 3974 } 3975 3976 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3977 3978 mss = skb_shinfo(skb)->gso_size; 3979 3980 /* set new MSS value if needed */ 3981 if (mss != tx_q->mss) { 3982 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3983 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3984 else 3985 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3986 3987 stmmac_set_mss(priv, mss_desc, mss); 3988 tx_q->mss = mss; 3989 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3990 priv->dma_tx_size); 3991 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3992 } 3993 3994 if (netif_msg_tx_queued(priv)) { 3995 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3996 __func__, hdr, proto_hdr_len, pay_len, mss); 3997 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3998 skb->data_len); 3999 } 4000 4001 /* Check if VLAN can be inserted by HW */ 4002 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4003 4004 first_entry = tx_q->cur_tx; 4005 WARN_ON(tx_q->tx_skbuff[first_entry]); 4006 4007 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4008 desc = &tx_q->dma_entx[first_entry].basic; 4009 else 4010 desc = &tx_q->dma_tx[first_entry]; 4011 first = desc; 4012 4013 if (has_vlan) 4014 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4015 4016 /* first descriptor: fill Headers on Buf1 */ 4017 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4018 DMA_TO_DEVICE); 4019 if (dma_mapping_error(priv->device, des)) 4020 goto dma_map_err; 4021 4022 tx_q->tx_skbuff_dma[first_entry].buf = des; 4023 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4024 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4025 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4026 4027 if (priv->dma_cap.addr64 <= 32) { 4028 first->des0 = cpu_to_le32(des); 4029 4030 /* Fill start of payload in buff2 of first descriptor */ 4031 if (pay_len) 4032 first->des1 = cpu_to_le32(des + proto_hdr_len); 4033 4034 /* If needed take extra descriptors to fill the remaining payload */ 4035 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4036 } else { 4037 stmmac_set_desc_addr(priv, first, des); 4038 tmp_pay_len = pay_len; 4039 des += proto_hdr_len; 4040 pay_len = 0; 4041 } 4042 4043 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4044 4045 /* Prepare fragments */ 4046 for (i = 0; i < nfrags; i++) { 4047 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4048 4049 des = skb_frag_dma_map(priv->device, frag, 0, 4050 skb_frag_size(frag), 4051 DMA_TO_DEVICE); 4052 if (dma_mapping_error(priv->device, des)) 4053 goto dma_map_err; 4054 4055 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4056 (i == nfrags - 1), queue); 4057 4058 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4059 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4060 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4061 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4062 } 4063 4064 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4065 4066 /* Only the last descriptor gets to point to the skb. */ 4067 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4068 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4069 4070 /* Manage tx mitigation */ 4071 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4072 tx_q->tx_count_frames += tx_packets; 4073 4074 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4075 set_ic = true; 4076 else if (!priv->tx_coal_frames[queue]) 4077 set_ic = false; 4078 else if (tx_packets > priv->tx_coal_frames[queue]) 4079 set_ic = true; 4080 else if ((tx_q->tx_count_frames % 4081 priv->tx_coal_frames[queue]) < tx_packets) 4082 set_ic = true; 4083 else 4084 set_ic = false; 4085 4086 if (set_ic) { 4087 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4088 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4089 else 4090 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4091 4092 tx_q->tx_count_frames = 0; 4093 stmmac_set_tx_ic(priv, desc); 4094 priv->xstats.tx_set_ic_bit++; 4095 } 4096 4097 /* We've used all descriptors we need for this skb, however, 4098 * advance cur_tx so that it references a fresh descriptor. 4099 * ndo_start_xmit will fill this descriptor the next time it's 4100 * called and stmmac_tx_clean may clean up to this descriptor. 4101 */ 4102 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 4103 4104 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4105 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4106 __func__); 4107 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4108 } 4109 4110 dev->stats.tx_bytes += skb->len; 4111 priv->xstats.tx_tso_frames++; 4112 priv->xstats.tx_tso_nfrags += nfrags; 4113 4114 if (priv->sarc_type) 4115 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4116 4117 skb_tx_timestamp(skb); 4118 4119 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4120 priv->hwts_tx_en)) { 4121 /* declare that device is doing timestamping */ 4122 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4123 stmmac_enable_tx_timestamp(priv, first); 4124 } 4125 4126 /* Complete the first descriptor before granting the DMA */ 4127 stmmac_prepare_tso_tx_desc(priv, first, 1, 4128 proto_hdr_len, 4129 pay_len, 4130 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4131 hdr / 4, (skb->len - proto_hdr_len)); 4132 4133 /* If context desc is used to change MSS */ 4134 if (mss_desc) { 4135 /* Make sure that first descriptor has been completely 4136 * written, including its own bit. This is because MSS is 4137 * actually before first descriptor, so we need to make 4138 * sure that MSS's own bit is the last thing written. 4139 */ 4140 dma_wmb(); 4141 stmmac_set_tx_owner(priv, mss_desc); 4142 } 4143 4144 if (netif_msg_pktdata(priv)) { 4145 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4146 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4147 tx_q->cur_tx, first, nfrags); 4148 pr_info(">>> frame to be transmitted: "); 4149 print_pkt(skb->data, skb_headlen(skb)); 4150 } 4151 4152 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4153 4154 stmmac_flush_tx_descriptors(priv, queue); 4155 stmmac_tx_timer_arm(priv, queue); 4156 4157 return NETDEV_TX_OK; 4158 4159 dma_map_err: 4160 dev_err(priv->device, "Tx dma map failed\n"); 4161 dev_kfree_skb(skb); 4162 priv->dev->stats.tx_dropped++; 4163 return NETDEV_TX_OK; 4164 } 4165 4166 /** 4167 * stmmac_xmit - Tx entry point of the driver 4168 * @skb : the socket buffer 4169 * @dev : device pointer 4170 * Description : this is the tx entry point of the driver. 4171 * It programs the chain or the ring and supports oversized frames 4172 * and SG feature. 4173 */ 4174 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4175 { 4176 unsigned int first_entry, tx_packets, enh_desc; 4177 struct stmmac_priv *priv = netdev_priv(dev); 4178 unsigned int nopaged_len = skb_headlen(skb); 4179 int i, csum_insertion = 0, is_jumbo = 0; 4180 u32 queue = skb_get_queue_mapping(skb); 4181 int nfrags = skb_shinfo(skb)->nr_frags; 4182 int gso = skb_shinfo(skb)->gso_type; 4183 struct dma_edesc *tbs_desc = NULL; 4184 struct dma_desc *desc, *first; 4185 struct stmmac_tx_queue *tx_q; 4186 bool has_vlan, set_ic; 4187 int entry, first_tx; 4188 dma_addr_t des; 4189 4190 tx_q = &priv->tx_queue[queue]; 4191 first_tx = tx_q->cur_tx; 4192 4193 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4194 stmmac_disable_eee_mode(priv); 4195 4196 /* Manage oversized TCP frames for GMAC4 device */ 4197 if (skb_is_gso(skb) && priv->tso) { 4198 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4199 return stmmac_tso_xmit(skb, dev); 4200 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4201 return stmmac_tso_xmit(skb, dev); 4202 } 4203 4204 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4205 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4206 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4207 queue)); 4208 /* This is a hard error, log it. */ 4209 netdev_err(priv->dev, 4210 "%s: Tx Ring full when queue awake\n", 4211 __func__); 4212 } 4213 return NETDEV_TX_BUSY; 4214 } 4215 4216 /* Check if VLAN can be inserted by HW */ 4217 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4218 4219 entry = tx_q->cur_tx; 4220 first_entry = entry; 4221 WARN_ON(tx_q->tx_skbuff[first_entry]); 4222 4223 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4224 4225 if (likely(priv->extend_desc)) 4226 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4227 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4228 desc = &tx_q->dma_entx[entry].basic; 4229 else 4230 desc = tx_q->dma_tx + entry; 4231 4232 first = desc; 4233 4234 if (has_vlan) 4235 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4236 4237 enh_desc = priv->plat->enh_desc; 4238 /* To program the descriptors according to the size of the frame */ 4239 if (enh_desc) 4240 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4241 4242 if (unlikely(is_jumbo)) { 4243 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4244 if (unlikely(entry < 0) && (entry != -EINVAL)) 4245 goto dma_map_err; 4246 } 4247 4248 for (i = 0; i < nfrags; i++) { 4249 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4250 int len = skb_frag_size(frag); 4251 bool last_segment = (i == (nfrags - 1)); 4252 4253 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4254 WARN_ON(tx_q->tx_skbuff[entry]); 4255 4256 if (likely(priv->extend_desc)) 4257 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4258 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4259 desc = &tx_q->dma_entx[entry].basic; 4260 else 4261 desc = tx_q->dma_tx + entry; 4262 4263 des = skb_frag_dma_map(priv->device, frag, 0, len, 4264 DMA_TO_DEVICE); 4265 if (dma_mapping_error(priv->device, des)) 4266 goto dma_map_err; /* should reuse desc w/o issues */ 4267 4268 tx_q->tx_skbuff_dma[entry].buf = des; 4269 4270 stmmac_set_desc_addr(priv, desc, des); 4271 4272 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4273 tx_q->tx_skbuff_dma[entry].len = len; 4274 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4275 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4276 4277 /* Prepare the descriptor and set the own bit too */ 4278 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4279 priv->mode, 1, last_segment, skb->len); 4280 } 4281 4282 /* Only the last descriptor gets to point to the skb. */ 4283 tx_q->tx_skbuff[entry] = skb; 4284 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4285 4286 /* According to the coalesce parameter the IC bit for the latest 4287 * segment is reset and the timer re-started to clean the tx status. 4288 * This approach takes care about the fragments: desc is the first 4289 * element in case of no SG. 4290 */ 4291 tx_packets = (entry + 1) - first_tx; 4292 tx_q->tx_count_frames += tx_packets; 4293 4294 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4295 set_ic = true; 4296 else if (!priv->tx_coal_frames[queue]) 4297 set_ic = false; 4298 else if (tx_packets > priv->tx_coal_frames[queue]) 4299 set_ic = true; 4300 else if ((tx_q->tx_count_frames % 4301 priv->tx_coal_frames[queue]) < tx_packets) 4302 set_ic = true; 4303 else 4304 set_ic = false; 4305 4306 if (set_ic) { 4307 if (likely(priv->extend_desc)) 4308 desc = &tx_q->dma_etx[entry].basic; 4309 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4310 desc = &tx_q->dma_entx[entry].basic; 4311 else 4312 desc = &tx_q->dma_tx[entry]; 4313 4314 tx_q->tx_count_frames = 0; 4315 stmmac_set_tx_ic(priv, desc); 4316 priv->xstats.tx_set_ic_bit++; 4317 } 4318 4319 /* We've used all descriptors we need for this skb, however, 4320 * advance cur_tx so that it references a fresh descriptor. 4321 * ndo_start_xmit will fill this descriptor the next time it's 4322 * called and stmmac_tx_clean may clean up to this descriptor. 4323 */ 4324 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4325 tx_q->cur_tx = entry; 4326 4327 if (netif_msg_pktdata(priv)) { 4328 netdev_dbg(priv->dev, 4329 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4330 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4331 entry, first, nfrags); 4332 4333 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4334 print_pkt(skb->data, skb->len); 4335 } 4336 4337 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4338 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4339 __func__); 4340 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4341 } 4342 4343 dev->stats.tx_bytes += skb->len; 4344 4345 if (priv->sarc_type) 4346 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4347 4348 skb_tx_timestamp(skb); 4349 4350 /* Ready to fill the first descriptor and set the OWN bit w/o any 4351 * problems because all the descriptors are actually ready to be 4352 * passed to the DMA engine. 4353 */ 4354 if (likely(!is_jumbo)) { 4355 bool last_segment = (nfrags == 0); 4356 4357 des = dma_map_single(priv->device, skb->data, 4358 nopaged_len, DMA_TO_DEVICE); 4359 if (dma_mapping_error(priv->device, des)) 4360 goto dma_map_err; 4361 4362 tx_q->tx_skbuff_dma[first_entry].buf = des; 4363 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4364 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4365 4366 stmmac_set_desc_addr(priv, first, des); 4367 4368 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4369 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4370 4371 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4372 priv->hwts_tx_en)) { 4373 /* declare that device is doing timestamping */ 4374 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4375 stmmac_enable_tx_timestamp(priv, first); 4376 } 4377 4378 /* Prepare the first descriptor setting the OWN bit too */ 4379 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4380 csum_insertion, priv->mode, 0, last_segment, 4381 skb->len); 4382 } 4383 4384 if (tx_q->tbs & STMMAC_TBS_EN) { 4385 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4386 4387 tbs_desc = &tx_q->dma_entx[first_entry]; 4388 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4389 } 4390 4391 stmmac_set_tx_owner(priv, first); 4392 4393 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4394 4395 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4396 4397 stmmac_flush_tx_descriptors(priv, queue); 4398 stmmac_tx_timer_arm(priv, queue); 4399 4400 return NETDEV_TX_OK; 4401 4402 dma_map_err: 4403 netdev_err(priv->dev, "Tx DMA map failed\n"); 4404 dev_kfree_skb(skb); 4405 priv->dev->stats.tx_dropped++; 4406 return NETDEV_TX_OK; 4407 } 4408 4409 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4410 { 4411 struct vlan_ethhdr *veth; 4412 __be16 vlan_proto; 4413 u16 vlanid; 4414 4415 veth = (struct vlan_ethhdr *)skb->data; 4416 vlan_proto = veth->h_vlan_proto; 4417 4418 if ((vlan_proto == htons(ETH_P_8021Q) && 4419 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4420 (vlan_proto == htons(ETH_P_8021AD) && 4421 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4422 /* pop the vlan tag */ 4423 vlanid = ntohs(veth->h_vlan_TCI); 4424 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4425 skb_pull(skb, VLAN_HLEN); 4426 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4427 } 4428 } 4429 4430 /** 4431 * stmmac_rx_refill - refill used skb preallocated buffers 4432 * @priv: driver private structure 4433 * @queue: RX queue index 4434 * Description : this is to reallocate the skb for the reception process 4435 * that is based on zero-copy. 4436 */ 4437 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4438 { 4439 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4440 int dirty = stmmac_rx_dirty(priv, queue); 4441 unsigned int entry = rx_q->dirty_rx; 4442 4443 while (dirty-- > 0) { 4444 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4445 struct dma_desc *p; 4446 bool use_rx_wd; 4447 4448 if (priv->extend_desc) 4449 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4450 else 4451 p = rx_q->dma_rx + entry; 4452 4453 if (!buf->page) { 4454 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 4455 if (!buf->page) 4456 break; 4457 } 4458 4459 if (priv->sph && !buf->sec_page) { 4460 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 4461 if (!buf->sec_page) 4462 break; 4463 4464 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4465 } 4466 4467 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4468 4469 stmmac_set_desc_addr(priv, p, buf->addr); 4470 if (priv->sph) 4471 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4472 else 4473 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4474 stmmac_refill_desc3(priv, rx_q, p); 4475 4476 rx_q->rx_count_frames++; 4477 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4478 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4479 rx_q->rx_count_frames = 0; 4480 4481 use_rx_wd = !priv->rx_coal_frames[queue]; 4482 use_rx_wd |= rx_q->rx_count_frames > 0; 4483 if (!priv->use_riwt) 4484 use_rx_wd = false; 4485 4486 dma_wmb(); 4487 stmmac_set_rx_owner(priv, p, use_rx_wd); 4488 4489 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4490 } 4491 rx_q->dirty_rx = entry; 4492 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4493 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4494 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4495 } 4496 4497 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4498 struct dma_desc *p, 4499 int status, unsigned int len) 4500 { 4501 unsigned int plen = 0, hlen = 0; 4502 int coe = priv->hw->rx_csum; 4503 4504 /* Not first descriptor, buffer is always zero */ 4505 if (priv->sph && len) 4506 return 0; 4507 4508 /* First descriptor, get split header length */ 4509 stmmac_get_rx_header_len(priv, p, &hlen); 4510 if (priv->sph && hlen) { 4511 priv->xstats.rx_split_hdr_pkt_n++; 4512 return hlen; 4513 } 4514 4515 /* First descriptor, not last descriptor and not split header */ 4516 if (status & rx_not_ls) 4517 return priv->dma_buf_sz; 4518 4519 plen = stmmac_get_rx_frame_len(priv, p, coe); 4520 4521 /* First descriptor and last descriptor and not split header */ 4522 return min_t(unsigned int, priv->dma_buf_sz, plen); 4523 } 4524 4525 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4526 struct dma_desc *p, 4527 int status, unsigned int len) 4528 { 4529 int coe = priv->hw->rx_csum; 4530 unsigned int plen = 0; 4531 4532 /* Not split header, buffer is not available */ 4533 if (!priv->sph) 4534 return 0; 4535 4536 /* Not last descriptor */ 4537 if (status & rx_not_ls) 4538 return priv->dma_buf_sz; 4539 4540 plen = stmmac_get_rx_frame_len(priv, p, coe); 4541 4542 /* Last descriptor */ 4543 return plen - len; 4544 } 4545 4546 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4547 struct xdp_frame *xdpf, bool dma_map) 4548 { 4549 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4550 unsigned int entry = tx_q->cur_tx; 4551 struct dma_desc *tx_desc; 4552 dma_addr_t dma_addr; 4553 bool set_ic; 4554 4555 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4556 return STMMAC_XDP_CONSUMED; 4557 4558 if (likely(priv->extend_desc)) 4559 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4560 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4561 tx_desc = &tx_q->dma_entx[entry].basic; 4562 else 4563 tx_desc = tx_q->dma_tx + entry; 4564 4565 if (dma_map) { 4566 dma_addr = dma_map_single(priv->device, xdpf->data, 4567 xdpf->len, DMA_TO_DEVICE); 4568 if (dma_mapping_error(priv->device, dma_addr)) 4569 return STMMAC_XDP_CONSUMED; 4570 4571 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4572 } else { 4573 struct page *page = virt_to_page(xdpf->data); 4574 4575 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4576 xdpf->headroom; 4577 dma_sync_single_for_device(priv->device, dma_addr, 4578 xdpf->len, DMA_BIDIRECTIONAL); 4579 4580 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4581 } 4582 4583 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4584 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4585 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4586 tx_q->tx_skbuff_dma[entry].last_segment = true; 4587 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4588 4589 tx_q->xdpf[entry] = xdpf; 4590 4591 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4592 4593 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4594 true, priv->mode, true, true, 4595 xdpf->len); 4596 4597 tx_q->tx_count_frames++; 4598 4599 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4600 set_ic = true; 4601 else 4602 set_ic = false; 4603 4604 if (set_ic) { 4605 tx_q->tx_count_frames = 0; 4606 stmmac_set_tx_ic(priv, tx_desc); 4607 priv->xstats.tx_set_ic_bit++; 4608 } 4609 4610 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4611 4612 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4613 tx_q->cur_tx = entry; 4614 4615 return STMMAC_XDP_TX; 4616 } 4617 4618 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4619 int cpu) 4620 { 4621 int index = cpu; 4622 4623 if (unlikely(index < 0)) 4624 index = 0; 4625 4626 while (index >= priv->plat->tx_queues_to_use) 4627 index -= priv->plat->tx_queues_to_use; 4628 4629 return index; 4630 } 4631 4632 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4633 struct xdp_buff *xdp) 4634 { 4635 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4636 int cpu = smp_processor_id(); 4637 struct netdev_queue *nq; 4638 int queue; 4639 int res; 4640 4641 if (unlikely(!xdpf)) 4642 return STMMAC_XDP_CONSUMED; 4643 4644 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4645 nq = netdev_get_tx_queue(priv->dev, queue); 4646 4647 __netif_tx_lock(nq, cpu); 4648 /* Avoids TX time-out as we are sharing with slow path */ 4649 nq->trans_start = jiffies; 4650 4651 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4652 if (res == STMMAC_XDP_TX) 4653 stmmac_flush_tx_descriptors(priv, queue); 4654 4655 __netif_tx_unlock(nq); 4656 4657 return res; 4658 } 4659 4660 /* This function assumes rcu_read_lock() is held by the caller. */ 4661 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4662 struct bpf_prog *prog, 4663 struct xdp_buff *xdp) 4664 { 4665 u32 act; 4666 int res; 4667 4668 act = bpf_prog_run_xdp(prog, xdp); 4669 switch (act) { 4670 case XDP_PASS: 4671 res = STMMAC_XDP_PASS; 4672 break; 4673 case XDP_TX: 4674 res = stmmac_xdp_xmit_back(priv, xdp); 4675 break; 4676 case XDP_REDIRECT: 4677 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4678 res = STMMAC_XDP_CONSUMED; 4679 else 4680 res = STMMAC_XDP_REDIRECT; 4681 break; 4682 default: 4683 bpf_warn_invalid_xdp_action(act); 4684 fallthrough; 4685 case XDP_ABORTED: 4686 trace_xdp_exception(priv->dev, prog, act); 4687 fallthrough; 4688 case XDP_DROP: 4689 res = STMMAC_XDP_CONSUMED; 4690 break; 4691 } 4692 4693 return res; 4694 } 4695 4696 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4697 struct xdp_buff *xdp) 4698 { 4699 struct bpf_prog *prog; 4700 int res; 4701 4702 rcu_read_lock(); 4703 4704 prog = READ_ONCE(priv->xdp_prog); 4705 if (!prog) { 4706 res = STMMAC_XDP_PASS; 4707 goto unlock; 4708 } 4709 4710 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4711 unlock: 4712 rcu_read_unlock(); 4713 return ERR_PTR(-res); 4714 } 4715 4716 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4717 int xdp_status) 4718 { 4719 int cpu = smp_processor_id(); 4720 int queue; 4721 4722 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4723 4724 if (xdp_status & STMMAC_XDP_TX) 4725 stmmac_tx_timer_arm(priv, queue); 4726 4727 if (xdp_status & STMMAC_XDP_REDIRECT) 4728 xdp_do_flush(); 4729 } 4730 4731 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4732 struct xdp_buff *xdp) 4733 { 4734 unsigned int metasize = xdp->data - xdp->data_meta; 4735 unsigned int datasize = xdp->data_end - xdp->data; 4736 struct sk_buff *skb; 4737 4738 skb = __napi_alloc_skb(&ch->rxtx_napi, 4739 xdp->data_end - xdp->data_hard_start, 4740 GFP_ATOMIC | __GFP_NOWARN); 4741 if (unlikely(!skb)) 4742 return NULL; 4743 4744 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4745 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4746 if (metasize) 4747 skb_metadata_set(skb, metasize); 4748 4749 return skb; 4750 } 4751 4752 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4753 struct dma_desc *p, struct dma_desc *np, 4754 struct xdp_buff *xdp) 4755 { 4756 struct stmmac_channel *ch = &priv->channel[queue]; 4757 unsigned int len = xdp->data_end - xdp->data; 4758 enum pkt_hash_types hash_type; 4759 int coe = priv->hw->rx_csum; 4760 struct sk_buff *skb; 4761 u32 hash; 4762 4763 skb = stmmac_construct_skb_zc(ch, xdp); 4764 if (!skb) { 4765 priv->dev->stats.rx_dropped++; 4766 return; 4767 } 4768 4769 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4770 stmmac_rx_vlan(priv->dev, skb); 4771 skb->protocol = eth_type_trans(skb, priv->dev); 4772 4773 if (unlikely(!coe)) 4774 skb_checksum_none_assert(skb); 4775 else 4776 skb->ip_summed = CHECKSUM_UNNECESSARY; 4777 4778 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4779 skb_set_hash(skb, hash, hash_type); 4780 4781 skb_record_rx_queue(skb, queue); 4782 napi_gro_receive(&ch->rxtx_napi, skb); 4783 4784 priv->dev->stats.rx_packets++; 4785 priv->dev->stats.rx_bytes += len; 4786 } 4787 4788 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4789 { 4790 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4791 unsigned int entry = rx_q->dirty_rx; 4792 struct dma_desc *rx_desc = NULL; 4793 bool ret = true; 4794 4795 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4796 4797 while (budget-- > 0 && entry != rx_q->cur_rx) { 4798 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4799 dma_addr_t dma_addr; 4800 bool use_rx_wd; 4801 4802 if (!buf->xdp) { 4803 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4804 if (!buf->xdp) { 4805 ret = false; 4806 break; 4807 } 4808 } 4809 4810 if (priv->extend_desc) 4811 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4812 else 4813 rx_desc = rx_q->dma_rx + entry; 4814 4815 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4816 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4817 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4818 stmmac_refill_desc3(priv, rx_q, rx_desc); 4819 4820 rx_q->rx_count_frames++; 4821 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4822 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4823 rx_q->rx_count_frames = 0; 4824 4825 use_rx_wd = !priv->rx_coal_frames[queue]; 4826 use_rx_wd |= rx_q->rx_count_frames > 0; 4827 if (!priv->use_riwt) 4828 use_rx_wd = false; 4829 4830 dma_wmb(); 4831 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4832 4833 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4834 } 4835 4836 if (rx_desc) { 4837 rx_q->dirty_rx = entry; 4838 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4839 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4840 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4841 } 4842 4843 return ret; 4844 } 4845 4846 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4847 { 4848 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4849 unsigned int count = 0, error = 0, len = 0; 4850 int dirty = stmmac_rx_dirty(priv, queue); 4851 unsigned int next_entry = rx_q->cur_rx; 4852 unsigned int desc_size; 4853 struct bpf_prog *prog; 4854 bool failure = false; 4855 int xdp_status = 0; 4856 int status = 0; 4857 4858 if (netif_msg_rx_status(priv)) { 4859 void *rx_head; 4860 4861 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4862 if (priv->extend_desc) { 4863 rx_head = (void *)rx_q->dma_erx; 4864 desc_size = sizeof(struct dma_extended_desc); 4865 } else { 4866 rx_head = (void *)rx_q->dma_rx; 4867 desc_size = sizeof(struct dma_desc); 4868 } 4869 4870 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 4871 rx_q->dma_rx_phy, desc_size); 4872 } 4873 while (count < limit) { 4874 struct stmmac_rx_buffer *buf; 4875 unsigned int buf1_len = 0; 4876 struct dma_desc *np, *p; 4877 int entry; 4878 int res; 4879 4880 if (!count && rx_q->state_saved) { 4881 error = rx_q->state.error; 4882 len = rx_q->state.len; 4883 } else { 4884 rx_q->state_saved = false; 4885 error = 0; 4886 len = 0; 4887 } 4888 4889 if (count >= limit) 4890 break; 4891 4892 read_again: 4893 buf1_len = 0; 4894 entry = next_entry; 4895 buf = &rx_q->buf_pool[entry]; 4896 4897 if (dirty >= STMMAC_RX_FILL_BATCH) { 4898 failure = failure || 4899 !stmmac_rx_refill_zc(priv, queue, dirty); 4900 dirty = 0; 4901 } 4902 4903 if (priv->extend_desc) 4904 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4905 else 4906 p = rx_q->dma_rx + entry; 4907 4908 /* read the status of the incoming frame */ 4909 status = stmmac_rx_status(priv, &priv->dev->stats, 4910 &priv->xstats, p); 4911 /* check if managed by the DMA otherwise go ahead */ 4912 if (unlikely(status & dma_own)) 4913 break; 4914 4915 /* Prefetch the next RX descriptor */ 4916 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 4917 priv->dma_rx_size); 4918 next_entry = rx_q->cur_rx; 4919 4920 if (priv->extend_desc) 4921 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 4922 else 4923 np = rx_q->dma_rx + next_entry; 4924 4925 prefetch(np); 4926 4927 if (priv->extend_desc) 4928 stmmac_rx_extended_status(priv, &priv->dev->stats, 4929 &priv->xstats, 4930 rx_q->dma_erx + entry); 4931 if (unlikely(status == discard_frame)) { 4932 xsk_buff_free(buf->xdp); 4933 buf->xdp = NULL; 4934 dirty++; 4935 error = 1; 4936 if (!priv->hwts_rx_en) 4937 priv->dev->stats.rx_errors++; 4938 } 4939 4940 if (unlikely(error && (status & rx_not_ls))) 4941 goto read_again; 4942 if (unlikely(error)) { 4943 count++; 4944 continue; 4945 } 4946 4947 /* Ensure a valid XSK buffer before proceed */ 4948 if (!buf->xdp) 4949 break; 4950 4951 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 4952 if (likely(status & rx_not_ls)) { 4953 xsk_buff_free(buf->xdp); 4954 buf->xdp = NULL; 4955 dirty++; 4956 count++; 4957 goto read_again; 4958 } 4959 4960 /* XDP ZC Frame only support primary buffers for now */ 4961 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 4962 len += buf1_len; 4963 4964 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 4965 * Type frames (LLC/LLC-SNAP) 4966 * 4967 * llc_snap is never checked in GMAC >= 4, so this ACS 4968 * feature is always disabled and packets need to be 4969 * stripped manually. 4970 */ 4971 if (likely(!(status & rx_not_ls)) && 4972 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 4973 unlikely(status != llc_snap))) { 4974 buf1_len -= ETH_FCS_LEN; 4975 len -= ETH_FCS_LEN; 4976 } 4977 4978 /* RX buffer is good and fit into a XSK pool buffer */ 4979 buf->xdp->data_end = buf->xdp->data + buf1_len; 4980 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 4981 4982 rcu_read_lock(); 4983 prog = READ_ONCE(priv->xdp_prog); 4984 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 4985 rcu_read_unlock(); 4986 4987 switch (res) { 4988 case STMMAC_XDP_PASS: 4989 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 4990 xsk_buff_free(buf->xdp); 4991 break; 4992 case STMMAC_XDP_CONSUMED: 4993 xsk_buff_free(buf->xdp); 4994 priv->dev->stats.rx_dropped++; 4995 break; 4996 case STMMAC_XDP_TX: 4997 case STMMAC_XDP_REDIRECT: 4998 xdp_status |= res; 4999 break; 5000 } 5001 5002 buf->xdp = NULL; 5003 dirty++; 5004 count++; 5005 } 5006 5007 if (status & rx_not_ls) { 5008 rx_q->state_saved = true; 5009 rx_q->state.error = error; 5010 rx_q->state.len = len; 5011 } 5012 5013 stmmac_finalize_xdp_rx(priv, xdp_status); 5014 5015 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5016 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5017 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5018 else 5019 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5020 5021 return (int)count; 5022 } 5023 5024 return failure ? limit : (int)count; 5025 } 5026 5027 /** 5028 * stmmac_rx - manage the receive process 5029 * @priv: driver private structure 5030 * @limit: napi bugget 5031 * @queue: RX queue index. 5032 * Description : this the function called by the napi poll method. 5033 * It gets all the frames inside the ring. 5034 */ 5035 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5036 { 5037 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5038 struct stmmac_channel *ch = &priv->channel[queue]; 5039 unsigned int count = 0, error = 0, len = 0; 5040 int status = 0, coe = priv->hw->rx_csum; 5041 unsigned int next_entry = rx_q->cur_rx; 5042 enum dma_data_direction dma_dir; 5043 unsigned int desc_size; 5044 struct sk_buff *skb = NULL; 5045 struct xdp_buff xdp; 5046 int xdp_status = 0; 5047 int buf_sz; 5048 5049 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5050 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5051 5052 if (netif_msg_rx_status(priv)) { 5053 void *rx_head; 5054 5055 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5056 if (priv->extend_desc) { 5057 rx_head = (void *)rx_q->dma_erx; 5058 desc_size = sizeof(struct dma_extended_desc); 5059 } else { 5060 rx_head = (void *)rx_q->dma_rx; 5061 desc_size = sizeof(struct dma_desc); 5062 } 5063 5064 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 5065 rx_q->dma_rx_phy, desc_size); 5066 } 5067 while (count < limit) { 5068 unsigned int buf1_len = 0, buf2_len = 0; 5069 enum pkt_hash_types hash_type; 5070 struct stmmac_rx_buffer *buf; 5071 struct dma_desc *np, *p; 5072 int entry; 5073 u32 hash; 5074 5075 if (!count && rx_q->state_saved) { 5076 skb = rx_q->state.skb; 5077 error = rx_q->state.error; 5078 len = rx_q->state.len; 5079 } else { 5080 rx_q->state_saved = false; 5081 skb = NULL; 5082 error = 0; 5083 len = 0; 5084 } 5085 5086 if (count >= limit) 5087 break; 5088 5089 read_again: 5090 buf1_len = 0; 5091 buf2_len = 0; 5092 entry = next_entry; 5093 buf = &rx_q->buf_pool[entry]; 5094 5095 if (priv->extend_desc) 5096 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5097 else 5098 p = rx_q->dma_rx + entry; 5099 5100 /* read the status of the incoming frame */ 5101 status = stmmac_rx_status(priv, &priv->dev->stats, 5102 &priv->xstats, p); 5103 /* check if managed by the DMA otherwise go ahead */ 5104 if (unlikely(status & dma_own)) 5105 break; 5106 5107 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5108 priv->dma_rx_size); 5109 next_entry = rx_q->cur_rx; 5110 5111 if (priv->extend_desc) 5112 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5113 else 5114 np = rx_q->dma_rx + next_entry; 5115 5116 prefetch(np); 5117 5118 if (priv->extend_desc) 5119 stmmac_rx_extended_status(priv, &priv->dev->stats, 5120 &priv->xstats, rx_q->dma_erx + entry); 5121 if (unlikely(status == discard_frame)) { 5122 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5123 buf->page = NULL; 5124 error = 1; 5125 if (!priv->hwts_rx_en) 5126 priv->dev->stats.rx_errors++; 5127 } 5128 5129 if (unlikely(error && (status & rx_not_ls))) 5130 goto read_again; 5131 if (unlikely(error)) { 5132 dev_kfree_skb(skb); 5133 skb = NULL; 5134 count++; 5135 continue; 5136 } 5137 5138 /* Buffer is good. Go on. */ 5139 5140 prefetch(page_address(buf->page)); 5141 if (buf->sec_page) 5142 prefetch(page_address(buf->sec_page)); 5143 5144 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5145 len += buf1_len; 5146 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5147 len += buf2_len; 5148 5149 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 5150 * Type frames (LLC/LLC-SNAP) 5151 * 5152 * llc_snap is never checked in GMAC >= 4, so this ACS 5153 * feature is always disabled and packets need to be 5154 * stripped manually. 5155 */ 5156 if (likely(!(status & rx_not_ls)) && 5157 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 5158 unlikely(status != llc_snap))) { 5159 if (buf2_len) 5160 buf2_len -= ETH_FCS_LEN; 5161 else 5162 buf1_len -= ETH_FCS_LEN; 5163 5164 len -= ETH_FCS_LEN; 5165 } 5166 5167 if (!skb) { 5168 unsigned int pre_len, sync_len; 5169 5170 dma_sync_single_for_cpu(priv->device, buf->addr, 5171 buf1_len, dma_dir); 5172 5173 xdp.data = page_address(buf->page) + buf->page_offset; 5174 xdp.data_end = xdp.data + buf1_len; 5175 xdp.data_hard_start = page_address(buf->page); 5176 xdp_set_data_meta_invalid(&xdp); 5177 xdp.frame_sz = buf_sz; 5178 xdp.rxq = &rx_q->xdp_rxq; 5179 5180 pre_len = xdp.data_end - xdp.data_hard_start - 5181 buf->page_offset; 5182 skb = stmmac_xdp_run_prog(priv, &xdp); 5183 /* Due xdp_adjust_tail: DMA sync for_device 5184 * cover max len CPU touch 5185 */ 5186 sync_len = xdp.data_end - xdp.data_hard_start - 5187 buf->page_offset; 5188 sync_len = max(sync_len, pre_len); 5189 5190 /* For Not XDP_PASS verdict */ 5191 if (IS_ERR(skb)) { 5192 unsigned int xdp_res = -PTR_ERR(skb); 5193 5194 if (xdp_res & STMMAC_XDP_CONSUMED) { 5195 page_pool_put_page(rx_q->page_pool, 5196 virt_to_head_page(xdp.data), 5197 sync_len, true); 5198 buf->page = NULL; 5199 priv->dev->stats.rx_dropped++; 5200 5201 /* Clear skb as it was set as 5202 * status by XDP program. 5203 */ 5204 skb = NULL; 5205 5206 if (unlikely((status & rx_not_ls))) 5207 goto read_again; 5208 5209 count++; 5210 continue; 5211 } else if (xdp_res & (STMMAC_XDP_TX | 5212 STMMAC_XDP_REDIRECT)) { 5213 xdp_status |= xdp_res; 5214 buf->page = NULL; 5215 skb = NULL; 5216 count++; 5217 continue; 5218 } 5219 } 5220 } 5221 5222 if (!skb) { 5223 /* XDP program may expand or reduce tail */ 5224 buf1_len = xdp.data_end - xdp.data; 5225 5226 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5227 if (!skb) { 5228 priv->dev->stats.rx_dropped++; 5229 count++; 5230 goto drain_data; 5231 } 5232 5233 /* XDP program may adjust header */ 5234 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5235 skb_put(skb, buf1_len); 5236 5237 /* Data payload copied into SKB, page ready for recycle */ 5238 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5239 buf->page = NULL; 5240 } else if (buf1_len) { 5241 dma_sync_single_for_cpu(priv->device, buf->addr, 5242 buf1_len, dma_dir); 5243 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5244 buf->page, buf->page_offset, buf1_len, 5245 priv->dma_buf_sz); 5246 5247 /* Data payload appended into SKB */ 5248 page_pool_release_page(rx_q->page_pool, buf->page); 5249 buf->page = NULL; 5250 } 5251 5252 if (buf2_len) { 5253 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5254 buf2_len, dma_dir); 5255 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5256 buf->sec_page, 0, buf2_len, 5257 priv->dma_buf_sz); 5258 5259 /* Data payload appended into SKB */ 5260 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5261 buf->sec_page = NULL; 5262 } 5263 5264 drain_data: 5265 if (likely(status & rx_not_ls)) 5266 goto read_again; 5267 if (!skb) 5268 continue; 5269 5270 /* Got entire packet into SKB. Finish it. */ 5271 5272 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5273 stmmac_rx_vlan(priv->dev, skb); 5274 skb->protocol = eth_type_trans(skb, priv->dev); 5275 5276 if (unlikely(!coe)) 5277 skb_checksum_none_assert(skb); 5278 else 5279 skb->ip_summed = CHECKSUM_UNNECESSARY; 5280 5281 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5282 skb_set_hash(skb, hash, hash_type); 5283 5284 skb_record_rx_queue(skb, queue); 5285 napi_gro_receive(&ch->rx_napi, skb); 5286 skb = NULL; 5287 5288 priv->dev->stats.rx_packets++; 5289 priv->dev->stats.rx_bytes += len; 5290 count++; 5291 } 5292 5293 if (status & rx_not_ls || skb) { 5294 rx_q->state_saved = true; 5295 rx_q->state.skb = skb; 5296 rx_q->state.error = error; 5297 rx_q->state.len = len; 5298 } 5299 5300 stmmac_finalize_xdp_rx(priv, xdp_status); 5301 5302 stmmac_rx_refill(priv, queue); 5303 5304 priv->xstats.rx_pkt_n += count; 5305 5306 return count; 5307 } 5308 5309 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5310 { 5311 struct stmmac_channel *ch = 5312 container_of(napi, struct stmmac_channel, rx_napi); 5313 struct stmmac_priv *priv = ch->priv_data; 5314 u32 chan = ch->index; 5315 int work_done; 5316 5317 priv->xstats.napi_poll++; 5318 5319 work_done = stmmac_rx(priv, budget, chan); 5320 if (work_done < budget && napi_complete_done(napi, work_done)) { 5321 unsigned long flags; 5322 5323 spin_lock_irqsave(&ch->lock, flags); 5324 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5325 spin_unlock_irqrestore(&ch->lock, flags); 5326 } 5327 5328 return work_done; 5329 } 5330 5331 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5332 { 5333 struct stmmac_channel *ch = 5334 container_of(napi, struct stmmac_channel, tx_napi); 5335 struct stmmac_priv *priv = ch->priv_data; 5336 u32 chan = ch->index; 5337 int work_done; 5338 5339 priv->xstats.napi_poll++; 5340 5341 work_done = stmmac_tx_clean(priv, budget, chan); 5342 work_done = min(work_done, budget); 5343 5344 if (work_done < budget && napi_complete_done(napi, work_done)) { 5345 unsigned long flags; 5346 5347 spin_lock_irqsave(&ch->lock, flags); 5348 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5349 spin_unlock_irqrestore(&ch->lock, flags); 5350 } 5351 5352 return work_done; 5353 } 5354 5355 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5356 { 5357 struct stmmac_channel *ch = 5358 container_of(napi, struct stmmac_channel, rxtx_napi); 5359 struct stmmac_priv *priv = ch->priv_data; 5360 int rx_done, tx_done; 5361 u32 chan = ch->index; 5362 5363 priv->xstats.napi_poll++; 5364 5365 tx_done = stmmac_tx_clean(priv, budget, chan); 5366 tx_done = min(tx_done, budget); 5367 5368 rx_done = stmmac_rx_zc(priv, budget, chan); 5369 5370 /* If either TX or RX work is not complete, return budget 5371 * and keep pooling 5372 */ 5373 if (tx_done >= budget || rx_done >= budget) 5374 return budget; 5375 5376 /* all work done, exit the polling mode */ 5377 if (napi_complete_done(napi, rx_done)) { 5378 unsigned long flags; 5379 5380 spin_lock_irqsave(&ch->lock, flags); 5381 /* Both RX and TX work done are compelte, 5382 * so enable both RX & TX IRQs. 5383 */ 5384 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5385 spin_unlock_irqrestore(&ch->lock, flags); 5386 } 5387 5388 return min(rx_done, budget - 1); 5389 } 5390 5391 /** 5392 * stmmac_tx_timeout 5393 * @dev : Pointer to net device structure 5394 * @txqueue: the index of the hanging transmit queue 5395 * Description: this function is called when a packet transmission fails to 5396 * complete within a reasonable time. The driver will mark the error in the 5397 * netdev structure and arrange for the device to be reset to a sane state 5398 * in order to transmit a new packet. 5399 */ 5400 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5401 { 5402 struct stmmac_priv *priv = netdev_priv(dev); 5403 5404 stmmac_global_err(priv); 5405 } 5406 5407 /** 5408 * stmmac_set_rx_mode - entry point for multicast addressing 5409 * @dev : pointer to the device structure 5410 * Description: 5411 * This function is a driver entry point which gets called by the kernel 5412 * whenever multicast addresses must be enabled/disabled. 5413 * Return value: 5414 * void. 5415 */ 5416 static void stmmac_set_rx_mode(struct net_device *dev) 5417 { 5418 struct stmmac_priv *priv = netdev_priv(dev); 5419 5420 stmmac_set_filter(priv, priv->hw, dev); 5421 } 5422 5423 /** 5424 * stmmac_change_mtu - entry point to change MTU size for the device. 5425 * @dev : device pointer. 5426 * @new_mtu : the new MTU size for the device. 5427 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5428 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5429 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5430 * Return value: 5431 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5432 * file on failure. 5433 */ 5434 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5435 { 5436 struct stmmac_priv *priv = netdev_priv(dev); 5437 int txfifosz = priv->plat->tx_fifo_size; 5438 const int mtu = new_mtu; 5439 5440 if (txfifosz == 0) 5441 txfifosz = priv->dma_cap.tx_fifo_size; 5442 5443 txfifosz /= priv->plat->tx_queues_to_use; 5444 5445 if (netif_running(dev)) { 5446 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 5447 return -EBUSY; 5448 } 5449 5450 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5451 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5452 return -EINVAL; 5453 } 5454 5455 new_mtu = STMMAC_ALIGN(new_mtu); 5456 5457 /* If condition true, FIFO is too small or MTU too large */ 5458 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5459 return -EINVAL; 5460 5461 dev->mtu = mtu; 5462 5463 netdev_update_features(dev); 5464 5465 return 0; 5466 } 5467 5468 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5469 netdev_features_t features) 5470 { 5471 struct stmmac_priv *priv = netdev_priv(dev); 5472 5473 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5474 features &= ~NETIF_F_RXCSUM; 5475 5476 if (!priv->plat->tx_coe) 5477 features &= ~NETIF_F_CSUM_MASK; 5478 5479 /* Some GMAC devices have a bugged Jumbo frame support that 5480 * needs to have the Tx COE disabled for oversized frames 5481 * (due to limited buffer sizes). In this case we disable 5482 * the TX csum insertion in the TDES and not use SF. 5483 */ 5484 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5485 features &= ~NETIF_F_CSUM_MASK; 5486 5487 /* Disable tso if asked by ethtool */ 5488 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5489 if (features & NETIF_F_TSO) 5490 priv->tso = true; 5491 else 5492 priv->tso = false; 5493 } 5494 5495 return features; 5496 } 5497 5498 static int stmmac_set_features(struct net_device *netdev, 5499 netdev_features_t features) 5500 { 5501 struct stmmac_priv *priv = netdev_priv(netdev); 5502 bool sph_en; 5503 u32 chan; 5504 5505 /* Keep the COE Type in case of csum is supporting */ 5506 if (features & NETIF_F_RXCSUM) 5507 priv->hw->rx_csum = priv->plat->rx_coe; 5508 else 5509 priv->hw->rx_csum = 0; 5510 /* No check needed because rx_coe has been set before and it will be 5511 * fixed in case of issue. 5512 */ 5513 stmmac_rx_ipc(priv, priv->hw); 5514 5515 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5516 5517 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5518 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5519 5520 return 0; 5521 } 5522 5523 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5524 { 5525 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5526 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5527 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5528 bool *hs_enable = &fpe_cfg->hs_enable; 5529 5530 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5531 return; 5532 5533 /* If LP has sent verify mPacket, LP is FPE capable */ 5534 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5535 if (*lp_state < FPE_STATE_CAPABLE) 5536 *lp_state = FPE_STATE_CAPABLE; 5537 5538 /* If user has requested FPE enable, quickly response */ 5539 if (*hs_enable) 5540 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5541 MPACKET_RESPONSE); 5542 } 5543 5544 /* If Local has sent verify mPacket, Local is FPE capable */ 5545 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5546 if (*lo_state < FPE_STATE_CAPABLE) 5547 *lo_state = FPE_STATE_CAPABLE; 5548 } 5549 5550 /* If LP has sent response mPacket, LP is entering FPE ON */ 5551 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5552 *lp_state = FPE_STATE_ENTERING_ON; 5553 5554 /* If Local has sent response mPacket, Local is entering FPE ON */ 5555 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5556 *lo_state = FPE_STATE_ENTERING_ON; 5557 5558 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5559 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5560 priv->fpe_wq) { 5561 queue_work(priv->fpe_wq, &priv->fpe_task); 5562 } 5563 } 5564 5565 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5566 { 5567 u32 rx_cnt = priv->plat->rx_queues_to_use; 5568 u32 tx_cnt = priv->plat->tx_queues_to_use; 5569 u32 queues_count; 5570 u32 queue; 5571 bool xmac; 5572 5573 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5574 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5575 5576 if (priv->irq_wake) 5577 pm_wakeup_event(priv->device, 0); 5578 5579 if (priv->dma_cap.estsel) 5580 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5581 &priv->xstats, tx_cnt); 5582 5583 if (priv->dma_cap.fpesel) { 5584 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5585 priv->dev); 5586 5587 stmmac_fpe_event_status(priv, status); 5588 } 5589 5590 /* To handle GMAC own interrupts */ 5591 if ((priv->plat->has_gmac) || xmac) { 5592 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5593 5594 if (unlikely(status)) { 5595 /* For LPI we need to save the tx status */ 5596 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5597 priv->tx_path_in_lpi_mode = true; 5598 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5599 priv->tx_path_in_lpi_mode = false; 5600 } 5601 5602 for (queue = 0; queue < queues_count; queue++) { 5603 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5604 queue); 5605 } 5606 5607 /* PCS link status */ 5608 if (priv->hw->pcs) { 5609 if (priv->xstats.pcs_link) 5610 netif_carrier_on(priv->dev); 5611 else 5612 netif_carrier_off(priv->dev); 5613 } 5614 5615 stmmac_timestamp_interrupt(priv, priv); 5616 } 5617 } 5618 5619 /** 5620 * stmmac_interrupt - main ISR 5621 * @irq: interrupt number. 5622 * @dev_id: to pass the net device pointer. 5623 * Description: this is the main driver interrupt service routine. 5624 * It can call: 5625 * o DMA service routine (to manage incoming frame reception and transmission 5626 * status) 5627 * o Core interrupts to manage: remote wake-up, management counter, LPI 5628 * interrupts. 5629 */ 5630 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5631 { 5632 struct net_device *dev = (struct net_device *)dev_id; 5633 struct stmmac_priv *priv = netdev_priv(dev); 5634 5635 /* Check if adapter is up */ 5636 if (test_bit(STMMAC_DOWN, &priv->state)) 5637 return IRQ_HANDLED; 5638 5639 /* Check if a fatal error happened */ 5640 if (stmmac_safety_feat_interrupt(priv)) 5641 return IRQ_HANDLED; 5642 5643 /* To handle Common interrupts */ 5644 stmmac_common_interrupt(priv); 5645 5646 /* To handle DMA interrupts */ 5647 stmmac_dma_interrupt(priv); 5648 5649 return IRQ_HANDLED; 5650 } 5651 5652 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5653 { 5654 struct net_device *dev = (struct net_device *)dev_id; 5655 struct stmmac_priv *priv = netdev_priv(dev); 5656 5657 if (unlikely(!dev)) { 5658 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5659 return IRQ_NONE; 5660 } 5661 5662 /* Check if adapter is up */ 5663 if (test_bit(STMMAC_DOWN, &priv->state)) 5664 return IRQ_HANDLED; 5665 5666 /* To handle Common interrupts */ 5667 stmmac_common_interrupt(priv); 5668 5669 return IRQ_HANDLED; 5670 } 5671 5672 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5673 { 5674 struct net_device *dev = (struct net_device *)dev_id; 5675 struct stmmac_priv *priv = netdev_priv(dev); 5676 5677 if (unlikely(!dev)) { 5678 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5679 return IRQ_NONE; 5680 } 5681 5682 /* Check if adapter is up */ 5683 if (test_bit(STMMAC_DOWN, &priv->state)) 5684 return IRQ_HANDLED; 5685 5686 /* Check if a fatal error happened */ 5687 stmmac_safety_feat_interrupt(priv); 5688 5689 return IRQ_HANDLED; 5690 } 5691 5692 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5693 { 5694 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5695 int chan = tx_q->queue_index; 5696 struct stmmac_priv *priv; 5697 int status; 5698 5699 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); 5700 5701 if (unlikely(!data)) { 5702 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5703 return IRQ_NONE; 5704 } 5705 5706 /* Check if adapter is up */ 5707 if (test_bit(STMMAC_DOWN, &priv->state)) 5708 return IRQ_HANDLED; 5709 5710 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5711 5712 if (unlikely(status & tx_hard_error_bump_tc)) { 5713 /* Try to bump up the dma threshold on this failure */ 5714 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 5715 tc <= 256) { 5716 tc += 64; 5717 if (priv->plat->force_thresh_dma_mode) 5718 stmmac_set_dma_operation_mode(priv, 5719 tc, 5720 tc, 5721 chan); 5722 else 5723 stmmac_set_dma_operation_mode(priv, 5724 tc, 5725 SF_DMA_MODE, 5726 chan); 5727 priv->xstats.threshold = tc; 5728 } 5729 } else if (unlikely(status == tx_hard_error)) { 5730 stmmac_tx_err(priv, chan); 5731 } 5732 5733 return IRQ_HANDLED; 5734 } 5735 5736 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5737 { 5738 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5739 int chan = rx_q->queue_index; 5740 struct stmmac_priv *priv; 5741 5742 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); 5743 5744 if (unlikely(!data)) { 5745 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5746 return IRQ_NONE; 5747 } 5748 5749 /* Check if adapter is up */ 5750 if (test_bit(STMMAC_DOWN, &priv->state)) 5751 return IRQ_HANDLED; 5752 5753 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5754 5755 return IRQ_HANDLED; 5756 } 5757 5758 #ifdef CONFIG_NET_POLL_CONTROLLER 5759 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5760 * to allow network I/O with interrupts disabled. 5761 */ 5762 static void stmmac_poll_controller(struct net_device *dev) 5763 { 5764 struct stmmac_priv *priv = netdev_priv(dev); 5765 int i; 5766 5767 /* If adapter is down, do nothing */ 5768 if (test_bit(STMMAC_DOWN, &priv->state)) 5769 return; 5770 5771 if (priv->plat->multi_msi_en) { 5772 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5773 stmmac_msi_intr_rx(0, &priv->rx_queue[i]); 5774 5775 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5776 stmmac_msi_intr_tx(0, &priv->tx_queue[i]); 5777 } else { 5778 disable_irq(dev->irq); 5779 stmmac_interrupt(dev->irq, dev); 5780 enable_irq(dev->irq); 5781 } 5782 } 5783 #endif 5784 5785 /** 5786 * stmmac_ioctl - Entry point for the Ioctl 5787 * @dev: Device pointer. 5788 * @rq: An IOCTL specefic structure, that can contain a pointer to 5789 * a proprietary structure used to pass information to the driver. 5790 * @cmd: IOCTL command 5791 * Description: 5792 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5793 */ 5794 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5795 { 5796 struct stmmac_priv *priv = netdev_priv (dev); 5797 int ret = -EOPNOTSUPP; 5798 5799 if (!netif_running(dev)) 5800 return -EINVAL; 5801 5802 switch (cmd) { 5803 case SIOCGMIIPHY: 5804 case SIOCGMIIREG: 5805 case SIOCSMIIREG: 5806 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5807 break; 5808 case SIOCSHWTSTAMP: 5809 ret = stmmac_hwtstamp_set(dev, rq); 5810 break; 5811 case SIOCGHWTSTAMP: 5812 ret = stmmac_hwtstamp_get(dev, rq); 5813 break; 5814 default: 5815 break; 5816 } 5817 5818 return ret; 5819 } 5820 5821 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5822 void *cb_priv) 5823 { 5824 struct stmmac_priv *priv = cb_priv; 5825 int ret = -EOPNOTSUPP; 5826 5827 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5828 return ret; 5829 5830 __stmmac_disable_all_queues(priv); 5831 5832 switch (type) { 5833 case TC_SETUP_CLSU32: 5834 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5835 break; 5836 case TC_SETUP_CLSFLOWER: 5837 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5838 break; 5839 default: 5840 break; 5841 } 5842 5843 stmmac_enable_all_queues(priv); 5844 return ret; 5845 } 5846 5847 static LIST_HEAD(stmmac_block_cb_list); 5848 5849 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5850 void *type_data) 5851 { 5852 struct stmmac_priv *priv = netdev_priv(ndev); 5853 5854 switch (type) { 5855 case TC_SETUP_BLOCK: 5856 return flow_block_cb_setup_simple(type_data, 5857 &stmmac_block_cb_list, 5858 stmmac_setup_tc_block_cb, 5859 priv, priv, true); 5860 case TC_SETUP_QDISC_CBS: 5861 return stmmac_tc_setup_cbs(priv, priv, type_data); 5862 case TC_SETUP_QDISC_TAPRIO: 5863 return stmmac_tc_setup_taprio(priv, priv, type_data); 5864 case TC_SETUP_QDISC_ETF: 5865 return stmmac_tc_setup_etf(priv, priv, type_data); 5866 default: 5867 return -EOPNOTSUPP; 5868 } 5869 } 5870 5871 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5872 struct net_device *sb_dev) 5873 { 5874 int gso = skb_shinfo(skb)->gso_type; 5875 5876 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5877 /* 5878 * There is no way to determine the number of TSO/USO 5879 * capable Queues. Let's use always the Queue 0 5880 * because if TSO/USO is supported then at least this 5881 * one will be capable. 5882 */ 5883 return 0; 5884 } 5885 5886 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5887 } 5888 5889 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 5890 { 5891 struct stmmac_priv *priv = netdev_priv(ndev); 5892 int ret = 0; 5893 5894 ret = pm_runtime_get_sync(priv->device); 5895 if (ret < 0) { 5896 pm_runtime_put_noidle(priv->device); 5897 return ret; 5898 } 5899 5900 ret = eth_mac_addr(ndev, addr); 5901 if (ret) 5902 goto set_mac_error; 5903 5904 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 5905 5906 set_mac_error: 5907 pm_runtime_put(priv->device); 5908 5909 return ret; 5910 } 5911 5912 #ifdef CONFIG_DEBUG_FS 5913 static struct dentry *stmmac_fs_dir; 5914 5915 static void sysfs_display_ring(void *head, int size, int extend_desc, 5916 struct seq_file *seq, dma_addr_t dma_phy_addr) 5917 { 5918 int i; 5919 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 5920 struct dma_desc *p = (struct dma_desc *)head; 5921 dma_addr_t dma_addr; 5922 5923 for (i = 0; i < size; i++) { 5924 if (extend_desc) { 5925 dma_addr = dma_phy_addr + i * sizeof(*ep); 5926 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5927 i, &dma_addr, 5928 le32_to_cpu(ep->basic.des0), 5929 le32_to_cpu(ep->basic.des1), 5930 le32_to_cpu(ep->basic.des2), 5931 le32_to_cpu(ep->basic.des3)); 5932 ep++; 5933 } else { 5934 dma_addr = dma_phy_addr + i * sizeof(*p); 5935 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5936 i, &dma_addr, 5937 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 5938 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 5939 p++; 5940 } 5941 seq_printf(seq, "\n"); 5942 } 5943 } 5944 5945 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 5946 { 5947 struct net_device *dev = seq->private; 5948 struct stmmac_priv *priv = netdev_priv(dev); 5949 u32 rx_count = priv->plat->rx_queues_to_use; 5950 u32 tx_count = priv->plat->tx_queues_to_use; 5951 u32 queue; 5952 5953 if ((dev->flags & IFF_UP) == 0) 5954 return 0; 5955 5956 for (queue = 0; queue < rx_count; queue++) { 5957 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5958 5959 seq_printf(seq, "RX Queue %d:\n", queue); 5960 5961 if (priv->extend_desc) { 5962 seq_printf(seq, "Extended descriptor ring:\n"); 5963 sysfs_display_ring((void *)rx_q->dma_erx, 5964 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 5965 } else { 5966 seq_printf(seq, "Descriptor ring:\n"); 5967 sysfs_display_ring((void *)rx_q->dma_rx, 5968 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 5969 } 5970 } 5971 5972 for (queue = 0; queue < tx_count; queue++) { 5973 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5974 5975 seq_printf(seq, "TX Queue %d:\n", queue); 5976 5977 if (priv->extend_desc) { 5978 seq_printf(seq, "Extended descriptor ring:\n"); 5979 sysfs_display_ring((void *)tx_q->dma_etx, 5980 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 5981 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 5982 seq_printf(seq, "Descriptor ring:\n"); 5983 sysfs_display_ring((void *)tx_q->dma_tx, 5984 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 5985 } 5986 } 5987 5988 return 0; 5989 } 5990 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 5991 5992 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 5993 { 5994 struct net_device *dev = seq->private; 5995 struct stmmac_priv *priv = netdev_priv(dev); 5996 5997 if (!priv->hw_cap_support) { 5998 seq_printf(seq, "DMA HW features not supported\n"); 5999 return 0; 6000 } 6001 6002 seq_printf(seq, "==============================\n"); 6003 seq_printf(seq, "\tDMA HW features\n"); 6004 seq_printf(seq, "==============================\n"); 6005 6006 seq_printf(seq, "\t10/100 Mbps: %s\n", 6007 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6008 seq_printf(seq, "\t1000 Mbps: %s\n", 6009 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6010 seq_printf(seq, "\tHalf duplex: %s\n", 6011 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6012 seq_printf(seq, "\tHash Filter: %s\n", 6013 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6014 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6015 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6016 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6017 (priv->dma_cap.pcs) ? "Y" : "N"); 6018 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6019 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6020 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6021 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6022 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6023 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6024 seq_printf(seq, "\tRMON module: %s\n", 6025 (priv->dma_cap.rmon) ? "Y" : "N"); 6026 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6027 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6028 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6029 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6030 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6031 (priv->dma_cap.eee) ? "Y" : "N"); 6032 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6033 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6034 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6035 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6036 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6037 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6038 } else { 6039 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6040 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6041 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6042 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6043 } 6044 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6045 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6046 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6047 priv->dma_cap.number_rx_channel); 6048 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6049 priv->dma_cap.number_tx_channel); 6050 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6051 priv->dma_cap.number_rx_queues); 6052 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6053 priv->dma_cap.number_tx_queues); 6054 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6055 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6056 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6057 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6058 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6059 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6060 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6061 priv->dma_cap.pps_out_num); 6062 seq_printf(seq, "\tSafety Features: %s\n", 6063 priv->dma_cap.asp ? "Y" : "N"); 6064 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6065 priv->dma_cap.frpsel ? "Y" : "N"); 6066 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6067 priv->dma_cap.addr64); 6068 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6069 priv->dma_cap.rssen ? "Y" : "N"); 6070 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6071 priv->dma_cap.vlhash ? "Y" : "N"); 6072 seq_printf(seq, "\tSplit Header: %s\n", 6073 priv->dma_cap.sphen ? "Y" : "N"); 6074 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6075 priv->dma_cap.vlins ? "Y" : "N"); 6076 seq_printf(seq, "\tDouble VLAN: %s\n", 6077 priv->dma_cap.dvlan ? "Y" : "N"); 6078 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6079 priv->dma_cap.l3l4fnum); 6080 seq_printf(seq, "\tARP Offloading: %s\n", 6081 priv->dma_cap.arpoffsel ? "Y" : "N"); 6082 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6083 priv->dma_cap.estsel ? "Y" : "N"); 6084 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6085 priv->dma_cap.fpesel ? "Y" : "N"); 6086 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6087 priv->dma_cap.tbssel ? "Y" : "N"); 6088 return 0; 6089 } 6090 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6091 6092 /* Use network device events to rename debugfs file entries. 6093 */ 6094 static int stmmac_device_event(struct notifier_block *unused, 6095 unsigned long event, void *ptr) 6096 { 6097 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6098 struct stmmac_priv *priv = netdev_priv(dev); 6099 6100 if (dev->netdev_ops != &stmmac_netdev_ops) 6101 goto done; 6102 6103 switch (event) { 6104 case NETDEV_CHANGENAME: 6105 if (priv->dbgfs_dir) 6106 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6107 priv->dbgfs_dir, 6108 stmmac_fs_dir, 6109 dev->name); 6110 break; 6111 } 6112 done: 6113 return NOTIFY_DONE; 6114 } 6115 6116 static struct notifier_block stmmac_notifier = { 6117 .notifier_call = stmmac_device_event, 6118 }; 6119 6120 static void stmmac_init_fs(struct net_device *dev) 6121 { 6122 struct stmmac_priv *priv = netdev_priv(dev); 6123 6124 rtnl_lock(); 6125 6126 /* Create per netdev entries */ 6127 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6128 6129 /* Entry to report DMA RX/TX rings */ 6130 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6131 &stmmac_rings_status_fops); 6132 6133 /* Entry to report the DMA HW features */ 6134 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6135 &stmmac_dma_cap_fops); 6136 6137 rtnl_unlock(); 6138 } 6139 6140 static void stmmac_exit_fs(struct net_device *dev) 6141 { 6142 struct stmmac_priv *priv = netdev_priv(dev); 6143 6144 debugfs_remove_recursive(priv->dbgfs_dir); 6145 } 6146 #endif /* CONFIG_DEBUG_FS */ 6147 6148 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6149 { 6150 unsigned char *data = (unsigned char *)&vid_le; 6151 unsigned char data_byte = 0; 6152 u32 crc = ~0x0; 6153 u32 temp = 0; 6154 int i, bits; 6155 6156 bits = get_bitmask_order(VLAN_VID_MASK); 6157 for (i = 0; i < bits; i++) { 6158 if ((i % 8) == 0) 6159 data_byte = data[i / 8]; 6160 6161 temp = ((crc & 1) ^ data_byte) & 1; 6162 crc >>= 1; 6163 data_byte >>= 1; 6164 6165 if (temp) 6166 crc ^= 0xedb88320; 6167 } 6168 6169 return crc; 6170 } 6171 6172 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6173 { 6174 u32 crc, hash = 0; 6175 __le16 pmatch = 0; 6176 int count = 0; 6177 u16 vid = 0; 6178 6179 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6180 __le16 vid_le = cpu_to_le16(vid); 6181 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6182 hash |= (1 << crc); 6183 count++; 6184 } 6185 6186 if (!priv->dma_cap.vlhash) { 6187 if (count > 2) /* VID = 0 always passes filter */ 6188 return -EOPNOTSUPP; 6189 6190 pmatch = cpu_to_le16(vid); 6191 hash = 0; 6192 } 6193 6194 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6195 } 6196 6197 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6198 { 6199 struct stmmac_priv *priv = netdev_priv(ndev); 6200 bool is_double = false; 6201 int ret; 6202 6203 if (be16_to_cpu(proto) == ETH_P_8021AD) 6204 is_double = true; 6205 6206 set_bit(vid, priv->active_vlans); 6207 ret = stmmac_vlan_update(priv, is_double); 6208 if (ret) { 6209 clear_bit(vid, priv->active_vlans); 6210 return ret; 6211 } 6212 6213 if (priv->hw->num_vlan) { 6214 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6215 if (ret) 6216 return ret; 6217 } 6218 6219 return 0; 6220 } 6221 6222 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6223 { 6224 struct stmmac_priv *priv = netdev_priv(ndev); 6225 bool is_double = false; 6226 int ret; 6227 6228 ret = pm_runtime_get_sync(priv->device); 6229 if (ret < 0) { 6230 pm_runtime_put_noidle(priv->device); 6231 return ret; 6232 } 6233 6234 if (be16_to_cpu(proto) == ETH_P_8021AD) 6235 is_double = true; 6236 6237 clear_bit(vid, priv->active_vlans); 6238 6239 if (priv->hw->num_vlan) { 6240 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6241 if (ret) 6242 goto del_vlan_error; 6243 } 6244 6245 ret = stmmac_vlan_update(priv, is_double); 6246 6247 del_vlan_error: 6248 pm_runtime_put(priv->device); 6249 6250 return ret; 6251 } 6252 6253 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6254 { 6255 struct stmmac_priv *priv = netdev_priv(dev); 6256 6257 switch (bpf->command) { 6258 case XDP_SETUP_PROG: 6259 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6260 case XDP_SETUP_XSK_POOL: 6261 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6262 bpf->xsk.queue_id); 6263 default: 6264 return -EOPNOTSUPP; 6265 } 6266 } 6267 6268 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6269 struct xdp_frame **frames, u32 flags) 6270 { 6271 struct stmmac_priv *priv = netdev_priv(dev); 6272 int cpu = smp_processor_id(); 6273 struct netdev_queue *nq; 6274 int i, nxmit = 0; 6275 int queue; 6276 6277 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6278 return -ENETDOWN; 6279 6280 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6281 return -EINVAL; 6282 6283 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6284 nq = netdev_get_tx_queue(priv->dev, queue); 6285 6286 __netif_tx_lock(nq, cpu); 6287 /* Avoids TX time-out as we are sharing with slow path */ 6288 nq->trans_start = jiffies; 6289 6290 for (i = 0; i < num_frames; i++) { 6291 int res; 6292 6293 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6294 if (res == STMMAC_XDP_CONSUMED) 6295 break; 6296 6297 nxmit++; 6298 } 6299 6300 if (flags & XDP_XMIT_FLUSH) { 6301 stmmac_flush_tx_descriptors(priv, queue); 6302 stmmac_tx_timer_arm(priv, queue); 6303 } 6304 6305 __netif_tx_unlock(nq); 6306 6307 return nxmit; 6308 } 6309 6310 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6311 { 6312 struct stmmac_channel *ch = &priv->channel[queue]; 6313 unsigned long flags; 6314 6315 spin_lock_irqsave(&ch->lock, flags); 6316 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6317 spin_unlock_irqrestore(&ch->lock, flags); 6318 6319 stmmac_stop_rx_dma(priv, queue); 6320 __free_dma_rx_desc_resources(priv, queue); 6321 } 6322 6323 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6324 { 6325 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 6326 struct stmmac_channel *ch = &priv->channel[queue]; 6327 unsigned long flags; 6328 u32 buf_size; 6329 int ret; 6330 6331 ret = __alloc_dma_rx_desc_resources(priv, queue); 6332 if (ret) { 6333 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6334 return; 6335 } 6336 6337 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); 6338 if (ret) { 6339 __free_dma_rx_desc_resources(priv, queue); 6340 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6341 return; 6342 } 6343 6344 stmmac_clear_rx_descriptors(priv, queue); 6345 6346 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6347 rx_q->dma_rx_phy, rx_q->queue_index); 6348 6349 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6350 sizeof(struct dma_desc)); 6351 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6352 rx_q->rx_tail_addr, rx_q->queue_index); 6353 6354 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6355 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6356 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6357 buf_size, 6358 rx_q->queue_index); 6359 } else { 6360 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6361 priv->dma_buf_sz, 6362 rx_q->queue_index); 6363 } 6364 6365 stmmac_start_rx_dma(priv, queue); 6366 6367 spin_lock_irqsave(&ch->lock, flags); 6368 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6369 spin_unlock_irqrestore(&ch->lock, flags); 6370 } 6371 6372 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6373 { 6374 struct stmmac_channel *ch = &priv->channel[queue]; 6375 unsigned long flags; 6376 6377 spin_lock_irqsave(&ch->lock, flags); 6378 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6379 spin_unlock_irqrestore(&ch->lock, flags); 6380 6381 stmmac_stop_tx_dma(priv, queue); 6382 __free_dma_tx_desc_resources(priv, queue); 6383 } 6384 6385 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6386 { 6387 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 6388 struct stmmac_channel *ch = &priv->channel[queue]; 6389 unsigned long flags; 6390 int ret; 6391 6392 ret = __alloc_dma_tx_desc_resources(priv, queue); 6393 if (ret) { 6394 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6395 return; 6396 } 6397 6398 ret = __init_dma_tx_desc_rings(priv, queue); 6399 if (ret) { 6400 __free_dma_tx_desc_resources(priv, queue); 6401 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6402 return; 6403 } 6404 6405 stmmac_clear_tx_descriptors(priv, queue); 6406 6407 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6408 tx_q->dma_tx_phy, tx_q->queue_index); 6409 6410 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6411 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6412 6413 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6414 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6415 tx_q->tx_tail_addr, tx_q->queue_index); 6416 6417 stmmac_start_tx_dma(priv, queue); 6418 6419 spin_lock_irqsave(&ch->lock, flags); 6420 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6421 spin_unlock_irqrestore(&ch->lock, flags); 6422 } 6423 6424 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6425 { 6426 struct stmmac_priv *priv = netdev_priv(dev); 6427 struct stmmac_rx_queue *rx_q; 6428 struct stmmac_tx_queue *tx_q; 6429 struct stmmac_channel *ch; 6430 6431 if (test_bit(STMMAC_DOWN, &priv->state) || 6432 !netif_carrier_ok(priv->dev)) 6433 return -ENETDOWN; 6434 6435 if (!stmmac_xdp_is_enabled(priv)) 6436 return -ENXIO; 6437 6438 if (queue >= priv->plat->rx_queues_to_use || 6439 queue >= priv->plat->tx_queues_to_use) 6440 return -EINVAL; 6441 6442 rx_q = &priv->rx_queue[queue]; 6443 tx_q = &priv->tx_queue[queue]; 6444 ch = &priv->channel[queue]; 6445 6446 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6447 return -ENXIO; 6448 6449 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6450 /* EQoS does not have per-DMA channel SW interrupt, 6451 * so we schedule RX Napi straight-away. 6452 */ 6453 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6454 __napi_schedule(&ch->rxtx_napi); 6455 } 6456 6457 return 0; 6458 } 6459 6460 static const struct net_device_ops stmmac_netdev_ops = { 6461 .ndo_open = stmmac_open, 6462 .ndo_start_xmit = stmmac_xmit, 6463 .ndo_stop = stmmac_release, 6464 .ndo_change_mtu = stmmac_change_mtu, 6465 .ndo_fix_features = stmmac_fix_features, 6466 .ndo_set_features = stmmac_set_features, 6467 .ndo_set_rx_mode = stmmac_set_rx_mode, 6468 .ndo_tx_timeout = stmmac_tx_timeout, 6469 .ndo_do_ioctl = stmmac_ioctl, 6470 .ndo_setup_tc = stmmac_setup_tc, 6471 .ndo_select_queue = stmmac_select_queue, 6472 #ifdef CONFIG_NET_POLL_CONTROLLER 6473 .ndo_poll_controller = stmmac_poll_controller, 6474 #endif 6475 .ndo_set_mac_address = stmmac_set_mac_address, 6476 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6477 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6478 .ndo_bpf = stmmac_bpf, 6479 .ndo_xdp_xmit = stmmac_xdp_xmit, 6480 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6481 }; 6482 6483 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6484 { 6485 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6486 return; 6487 if (test_bit(STMMAC_DOWN, &priv->state)) 6488 return; 6489 6490 netdev_err(priv->dev, "Reset adapter.\n"); 6491 6492 rtnl_lock(); 6493 netif_trans_update(priv->dev); 6494 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6495 usleep_range(1000, 2000); 6496 6497 set_bit(STMMAC_DOWN, &priv->state); 6498 dev_close(priv->dev); 6499 dev_open(priv->dev, NULL); 6500 clear_bit(STMMAC_DOWN, &priv->state); 6501 clear_bit(STMMAC_RESETING, &priv->state); 6502 rtnl_unlock(); 6503 } 6504 6505 static void stmmac_service_task(struct work_struct *work) 6506 { 6507 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6508 service_task); 6509 6510 stmmac_reset_subtask(priv); 6511 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6512 } 6513 6514 /** 6515 * stmmac_hw_init - Init the MAC device 6516 * @priv: driver private structure 6517 * Description: this function is to configure the MAC device according to 6518 * some platform parameters or the HW capability register. It prepares the 6519 * driver to use either ring or chain modes and to setup either enhanced or 6520 * normal descriptors. 6521 */ 6522 static int stmmac_hw_init(struct stmmac_priv *priv) 6523 { 6524 int ret; 6525 6526 /* dwmac-sun8i only work in chain mode */ 6527 if (priv->plat->has_sun8i) 6528 chain_mode = 1; 6529 priv->chain_mode = chain_mode; 6530 6531 /* Initialize HW Interface */ 6532 ret = stmmac_hwif_init(priv); 6533 if (ret) 6534 return ret; 6535 6536 /* Get the HW capability (new GMAC newer than 3.50a) */ 6537 priv->hw_cap_support = stmmac_get_hw_features(priv); 6538 if (priv->hw_cap_support) { 6539 dev_info(priv->device, "DMA HW capability register supported\n"); 6540 6541 /* We can override some gmac/dma configuration fields: e.g. 6542 * enh_desc, tx_coe (e.g. that are passed through the 6543 * platform) with the values from the HW capability 6544 * register (if supported). 6545 */ 6546 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6547 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 6548 priv->hw->pmt = priv->plat->pmt; 6549 if (priv->dma_cap.hash_tb_sz) { 6550 priv->hw->multicast_filter_bins = 6551 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6552 priv->hw->mcast_bits_log2 = 6553 ilog2(priv->hw->multicast_filter_bins); 6554 } 6555 6556 /* TXCOE doesn't work in thresh DMA mode */ 6557 if (priv->plat->force_thresh_dma_mode) 6558 priv->plat->tx_coe = 0; 6559 else 6560 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6561 6562 /* In case of GMAC4 rx_coe is from HW cap register. */ 6563 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6564 6565 if (priv->dma_cap.rx_coe_type2) 6566 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6567 else if (priv->dma_cap.rx_coe_type1) 6568 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6569 6570 } else { 6571 dev_info(priv->device, "No HW DMA feature register supported\n"); 6572 } 6573 6574 if (priv->plat->rx_coe) { 6575 priv->hw->rx_csum = priv->plat->rx_coe; 6576 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6577 if (priv->synopsys_id < DWMAC_CORE_4_00) 6578 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6579 } 6580 if (priv->plat->tx_coe) 6581 dev_info(priv->device, "TX Checksum insertion supported\n"); 6582 6583 if (priv->plat->pmt) { 6584 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6585 device_set_wakeup_capable(priv->device, 1); 6586 } 6587 6588 if (priv->dma_cap.tsoen) 6589 dev_info(priv->device, "TSO supported\n"); 6590 6591 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6592 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6593 6594 /* Run HW quirks, if any */ 6595 if (priv->hwif_quirks) { 6596 ret = priv->hwif_quirks(priv); 6597 if (ret) 6598 return ret; 6599 } 6600 6601 /* Rx Watchdog is available in the COREs newer than the 3.40. 6602 * In some case, for example on bugged HW this feature 6603 * has to be disable and this can be done by passing the 6604 * riwt_off field from the platform. 6605 */ 6606 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6607 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6608 priv->use_riwt = 1; 6609 dev_info(priv->device, 6610 "Enable RX Mitigation via HW Watchdog Timer\n"); 6611 } 6612 6613 return 0; 6614 } 6615 6616 static void stmmac_napi_add(struct net_device *dev) 6617 { 6618 struct stmmac_priv *priv = netdev_priv(dev); 6619 u32 queue, maxq; 6620 6621 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6622 6623 for (queue = 0; queue < maxq; queue++) { 6624 struct stmmac_channel *ch = &priv->channel[queue]; 6625 6626 ch->priv_data = priv; 6627 ch->index = queue; 6628 spin_lock_init(&ch->lock); 6629 6630 if (queue < priv->plat->rx_queues_to_use) { 6631 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6632 NAPI_POLL_WEIGHT); 6633 } 6634 if (queue < priv->plat->tx_queues_to_use) { 6635 netif_tx_napi_add(dev, &ch->tx_napi, 6636 stmmac_napi_poll_tx, 6637 NAPI_POLL_WEIGHT); 6638 } 6639 if (queue < priv->plat->rx_queues_to_use && 6640 queue < priv->plat->tx_queues_to_use) { 6641 netif_napi_add(dev, &ch->rxtx_napi, 6642 stmmac_napi_poll_rxtx, 6643 NAPI_POLL_WEIGHT); 6644 } 6645 } 6646 } 6647 6648 static void stmmac_napi_del(struct net_device *dev) 6649 { 6650 struct stmmac_priv *priv = netdev_priv(dev); 6651 u32 queue, maxq; 6652 6653 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6654 6655 for (queue = 0; queue < maxq; queue++) { 6656 struct stmmac_channel *ch = &priv->channel[queue]; 6657 6658 if (queue < priv->plat->rx_queues_to_use) 6659 netif_napi_del(&ch->rx_napi); 6660 if (queue < priv->plat->tx_queues_to_use) 6661 netif_napi_del(&ch->tx_napi); 6662 if (queue < priv->plat->rx_queues_to_use && 6663 queue < priv->plat->tx_queues_to_use) { 6664 netif_napi_del(&ch->rxtx_napi); 6665 } 6666 } 6667 } 6668 6669 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6670 { 6671 struct stmmac_priv *priv = netdev_priv(dev); 6672 int ret = 0; 6673 6674 if (netif_running(dev)) 6675 stmmac_release(dev); 6676 6677 stmmac_napi_del(dev); 6678 6679 priv->plat->rx_queues_to_use = rx_cnt; 6680 priv->plat->tx_queues_to_use = tx_cnt; 6681 6682 stmmac_napi_add(dev); 6683 6684 if (netif_running(dev)) 6685 ret = stmmac_open(dev); 6686 6687 return ret; 6688 } 6689 6690 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6691 { 6692 struct stmmac_priv *priv = netdev_priv(dev); 6693 int ret = 0; 6694 6695 if (netif_running(dev)) 6696 stmmac_release(dev); 6697 6698 priv->dma_rx_size = rx_size; 6699 priv->dma_tx_size = tx_size; 6700 6701 if (netif_running(dev)) 6702 ret = stmmac_open(dev); 6703 6704 return ret; 6705 } 6706 6707 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6708 static void stmmac_fpe_lp_task(struct work_struct *work) 6709 { 6710 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6711 fpe_task); 6712 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6713 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6714 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6715 bool *hs_enable = &fpe_cfg->hs_enable; 6716 bool *enable = &fpe_cfg->enable; 6717 int retries = 20; 6718 6719 while (retries-- > 0) { 6720 /* Bail out immediately if FPE handshake is OFF */ 6721 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6722 break; 6723 6724 if (*lo_state == FPE_STATE_ENTERING_ON && 6725 *lp_state == FPE_STATE_ENTERING_ON) { 6726 stmmac_fpe_configure(priv, priv->ioaddr, 6727 priv->plat->tx_queues_to_use, 6728 priv->plat->rx_queues_to_use, 6729 *enable); 6730 6731 netdev_info(priv->dev, "configured FPE\n"); 6732 6733 *lo_state = FPE_STATE_ON; 6734 *lp_state = FPE_STATE_ON; 6735 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6736 break; 6737 } 6738 6739 if ((*lo_state == FPE_STATE_CAPABLE || 6740 *lo_state == FPE_STATE_ENTERING_ON) && 6741 *lp_state != FPE_STATE_ON) { 6742 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6743 *lo_state, *lp_state); 6744 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6745 MPACKET_VERIFY); 6746 } 6747 /* Sleep then retry */ 6748 msleep(500); 6749 } 6750 6751 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6752 } 6753 6754 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 6755 { 6756 if (priv->plat->fpe_cfg->hs_enable != enable) { 6757 if (enable) { 6758 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6759 MPACKET_VERIFY); 6760 } else { 6761 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 6762 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 6763 } 6764 6765 priv->plat->fpe_cfg->hs_enable = enable; 6766 } 6767 } 6768 6769 /** 6770 * stmmac_dvr_probe 6771 * @device: device pointer 6772 * @plat_dat: platform data pointer 6773 * @res: stmmac resource pointer 6774 * Description: this is the main probe function used to 6775 * call the alloc_etherdev, allocate the priv structure. 6776 * Return: 6777 * returns 0 on success, otherwise errno. 6778 */ 6779 int stmmac_dvr_probe(struct device *device, 6780 struct plat_stmmacenet_data *plat_dat, 6781 struct stmmac_resources *res) 6782 { 6783 struct net_device *ndev = NULL; 6784 struct stmmac_priv *priv; 6785 u32 rxq; 6786 int i, ret = 0; 6787 6788 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 6789 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 6790 if (!ndev) 6791 return -ENOMEM; 6792 6793 SET_NETDEV_DEV(ndev, device); 6794 6795 priv = netdev_priv(ndev); 6796 priv->device = device; 6797 priv->dev = ndev; 6798 6799 stmmac_set_ethtool_ops(ndev); 6800 priv->pause = pause; 6801 priv->plat = plat_dat; 6802 priv->ioaddr = res->addr; 6803 priv->dev->base_addr = (unsigned long)res->addr; 6804 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 6805 6806 priv->dev->irq = res->irq; 6807 priv->wol_irq = res->wol_irq; 6808 priv->lpi_irq = res->lpi_irq; 6809 priv->sfty_ce_irq = res->sfty_ce_irq; 6810 priv->sfty_ue_irq = res->sfty_ue_irq; 6811 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 6812 priv->rx_irq[i] = res->rx_irq[i]; 6813 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 6814 priv->tx_irq[i] = res->tx_irq[i]; 6815 6816 if (!is_zero_ether_addr(res->mac)) 6817 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 6818 6819 dev_set_drvdata(device, priv->dev); 6820 6821 /* Verify driver arguments */ 6822 stmmac_verify_args(); 6823 6824 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 6825 if (!priv->af_xdp_zc_qps) 6826 return -ENOMEM; 6827 6828 /* Allocate workqueue */ 6829 priv->wq = create_singlethread_workqueue("stmmac_wq"); 6830 if (!priv->wq) { 6831 dev_err(priv->device, "failed to create workqueue\n"); 6832 return -ENOMEM; 6833 } 6834 6835 INIT_WORK(&priv->service_task, stmmac_service_task); 6836 6837 /* Initialize Link Partner FPE workqueue */ 6838 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 6839 6840 /* Override with kernel parameters if supplied XXX CRS XXX 6841 * this needs to have multiple instances 6842 */ 6843 if ((phyaddr >= 0) && (phyaddr <= 31)) 6844 priv->plat->phy_addr = phyaddr; 6845 6846 if (priv->plat->stmmac_rst) { 6847 ret = reset_control_assert(priv->plat->stmmac_rst); 6848 reset_control_deassert(priv->plat->stmmac_rst); 6849 /* Some reset controllers have only reset callback instead of 6850 * assert + deassert callbacks pair. 6851 */ 6852 if (ret == -ENOTSUPP) 6853 reset_control_reset(priv->plat->stmmac_rst); 6854 } 6855 6856 /* Init MAC and get the capabilities */ 6857 ret = stmmac_hw_init(priv); 6858 if (ret) 6859 goto error_hw_init; 6860 6861 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 6862 */ 6863 if (priv->synopsys_id < DWMAC_CORE_5_20) 6864 priv->plat->dma_cfg->dche = false; 6865 6866 stmmac_check_ether_addr(priv); 6867 6868 ndev->netdev_ops = &stmmac_netdev_ops; 6869 6870 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6871 NETIF_F_RXCSUM; 6872 6873 ret = stmmac_tc_init(priv, priv); 6874 if (!ret) { 6875 ndev->hw_features |= NETIF_F_HW_TC; 6876 } 6877 6878 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 6879 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 6880 if (priv->plat->has_gmac4) 6881 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 6882 priv->tso = true; 6883 dev_info(priv->device, "TSO feature enabled\n"); 6884 } 6885 6886 if (priv->dma_cap.sphen) { 6887 ndev->hw_features |= NETIF_F_GRO; 6888 priv->sph_cap = true; 6889 priv->sph = priv->sph_cap; 6890 dev_info(priv->device, "SPH feature enabled\n"); 6891 } 6892 6893 /* The current IP register MAC_HW_Feature1[ADDR64] only define 6894 * 32/40/64 bit width, but some SOC support others like i.MX8MP 6895 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 6896 * So overwrite dma_cap.addr64 according to HW real design. 6897 */ 6898 if (priv->plat->addr64) 6899 priv->dma_cap.addr64 = priv->plat->addr64; 6900 6901 if (priv->dma_cap.addr64) { 6902 ret = dma_set_mask_and_coherent(device, 6903 DMA_BIT_MASK(priv->dma_cap.addr64)); 6904 if (!ret) { 6905 dev_info(priv->device, "Using %d bits DMA width\n", 6906 priv->dma_cap.addr64); 6907 6908 /* 6909 * If more than 32 bits can be addressed, make sure to 6910 * enable enhanced addressing mode. 6911 */ 6912 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 6913 priv->plat->dma_cfg->eame = true; 6914 } else { 6915 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 6916 if (ret) { 6917 dev_err(priv->device, "Failed to set DMA Mask\n"); 6918 goto error_hw_init; 6919 } 6920 6921 priv->dma_cap.addr64 = 32; 6922 } 6923 } 6924 6925 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 6926 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 6927 #ifdef STMMAC_VLAN_TAG_USED 6928 /* Both mac100 and gmac support receive VLAN tag detection */ 6929 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 6930 if (priv->dma_cap.vlhash) { 6931 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6932 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 6933 } 6934 if (priv->dma_cap.vlins) { 6935 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 6936 if (priv->dma_cap.dvlan) 6937 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 6938 } 6939 #endif 6940 priv->msg_enable = netif_msg_init(debug, default_msg_level); 6941 6942 /* Initialize RSS */ 6943 rxq = priv->plat->rx_queues_to_use; 6944 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 6945 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 6946 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 6947 6948 if (priv->dma_cap.rssen && priv->plat->rss_en) 6949 ndev->features |= NETIF_F_RXHASH; 6950 6951 /* MTU range: 46 - hw-specific max */ 6952 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 6953 if (priv->plat->has_xgmac) 6954 ndev->max_mtu = XGMAC_JUMBO_LEN; 6955 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 6956 ndev->max_mtu = JUMBO_LEN; 6957 else 6958 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 6959 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 6960 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 6961 */ 6962 if ((priv->plat->maxmtu < ndev->max_mtu) && 6963 (priv->plat->maxmtu >= ndev->min_mtu)) 6964 ndev->max_mtu = priv->plat->maxmtu; 6965 else if (priv->plat->maxmtu < ndev->min_mtu) 6966 dev_warn(priv->device, 6967 "%s: warning: maxmtu having invalid value (%d)\n", 6968 __func__, priv->plat->maxmtu); 6969 6970 if (flow_ctrl) 6971 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 6972 6973 /* Setup channels NAPI */ 6974 stmmac_napi_add(ndev); 6975 6976 mutex_init(&priv->lock); 6977 6978 /* If a specific clk_csr value is passed from the platform 6979 * this means that the CSR Clock Range selection cannot be 6980 * changed at run-time and it is fixed. Viceversa the driver'll try to 6981 * set the MDC clock dynamically according to the csr actual 6982 * clock input. 6983 */ 6984 if (priv->plat->clk_csr >= 0) 6985 priv->clk_csr = priv->plat->clk_csr; 6986 else 6987 stmmac_clk_csr_set(priv); 6988 6989 stmmac_check_pcs_mode(priv); 6990 6991 pm_runtime_get_noresume(device); 6992 pm_runtime_set_active(device); 6993 pm_runtime_enable(device); 6994 6995 if (priv->hw->pcs != STMMAC_PCS_TBI && 6996 priv->hw->pcs != STMMAC_PCS_RTBI) { 6997 /* MDIO bus Registration */ 6998 ret = stmmac_mdio_register(ndev); 6999 if (ret < 0) { 7000 dev_err(priv->device, 7001 "%s: MDIO bus (id: %d) registration failed", 7002 __func__, priv->plat->bus_id); 7003 goto error_mdio_register; 7004 } 7005 } 7006 7007 ret = stmmac_phy_setup(priv); 7008 if (ret) { 7009 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7010 goto error_phy_setup; 7011 } 7012 7013 ret = register_netdev(ndev); 7014 if (ret) { 7015 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7016 __func__, ret); 7017 goto error_netdev_register; 7018 } 7019 7020 if (priv->plat->serdes_powerup) { 7021 ret = priv->plat->serdes_powerup(ndev, 7022 priv->plat->bsp_priv); 7023 7024 if (ret < 0) 7025 goto error_serdes_powerup; 7026 } 7027 7028 #ifdef CONFIG_DEBUG_FS 7029 stmmac_init_fs(ndev); 7030 #endif 7031 7032 /* Let pm_runtime_put() disable the clocks. 7033 * If CONFIG_PM is not enabled, the clocks will stay powered. 7034 */ 7035 pm_runtime_put(device); 7036 7037 return ret; 7038 7039 error_serdes_powerup: 7040 unregister_netdev(ndev); 7041 error_netdev_register: 7042 phylink_destroy(priv->phylink); 7043 error_phy_setup: 7044 if (priv->hw->pcs != STMMAC_PCS_TBI && 7045 priv->hw->pcs != STMMAC_PCS_RTBI) 7046 stmmac_mdio_unregister(ndev); 7047 error_mdio_register: 7048 stmmac_napi_del(ndev); 7049 error_hw_init: 7050 destroy_workqueue(priv->wq); 7051 stmmac_bus_clks_config(priv, false); 7052 bitmap_free(priv->af_xdp_zc_qps); 7053 7054 return ret; 7055 } 7056 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7057 7058 /** 7059 * stmmac_dvr_remove 7060 * @dev: device pointer 7061 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7062 * changes the link status, releases the DMA descriptor rings. 7063 */ 7064 int stmmac_dvr_remove(struct device *dev) 7065 { 7066 struct net_device *ndev = dev_get_drvdata(dev); 7067 struct stmmac_priv *priv = netdev_priv(ndev); 7068 7069 netdev_info(priv->dev, "%s: removing driver", __func__); 7070 7071 stmmac_stop_all_dma(priv); 7072 stmmac_mac_set(priv, priv->ioaddr, false); 7073 netif_carrier_off(ndev); 7074 unregister_netdev(ndev); 7075 7076 /* Serdes power down needs to happen after VLAN filter 7077 * is deleted that is triggered by unregister_netdev(). 7078 */ 7079 if (priv->plat->serdes_powerdown) 7080 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7081 7082 #ifdef CONFIG_DEBUG_FS 7083 stmmac_exit_fs(ndev); 7084 #endif 7085 phylink_destroy(priv->phylink); 7086 if (priv->plat->stmmac_rst) 7087 reset_control_assert(priv->plat->stmmac_rst); 7088 pm_runtime_put(dev); 7089 pm_runtime_disable(dev); 7090 if (priv->hw->pcs != STMMAC_PCS_TBI && 7091 priv->hw->pcs != STMMAC_PCS_RTBI) 7092 stmmac_mdio_unregister(ndev); 7093 destroy_workqueue(priv->wq); 7094 mutex_destroy(&priv->lock); 7095 bitmap_free(priv->af_xdp_zc_qps); 7096 7097 return 0; 7098 } 7099 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7100 7101 /** 7102 * stmmac_suspend - suspend callback 7103 * @dev: device pointer 7104 * Description: this is the function to suspend the device and it is called 7105 * by the platform driver to stop the network queue, release the resources, 7106 * program the PMT register (for WoL), clean and release driver resources. 7107 */ 7108 int stmmac_suspend(struct device *dev) 7109 { 7110 struct net_device *ndev = dev_get_drvdata(dev); 7111 struct stmmac_priv *priv = netdev_priv(ndev); 7112 u32 chan; 7113 int ret; 7114 7115 if (!ndev || !netif_running(ndev)) 7116 return 0; 7117 7118 phylink_mac_change(priv->phylink, false); 7119 7120 mutex_lock(&priv->lock); 7121 7122 netif_device_detach(ndev); 7123 7124 stmmac_disable_all_queues(priv); 7125 7126 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7127 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 7128 7129 if (priv->eee_enabled) { 7130 priv->tx_path_in_lpi_mode = false; 7131 del_timer_sync(&priv->eee_ctrl_timer); 7132 } 7133 7134 /* Stop TX/RX DMA */ 7135 stmmac_stop_all_dma(priv); 7136 7137 if (priv->plat->serdes_powerdown) 7138 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7139 7140 /* Enable Power down mode by programming the PMT regs */ 7141 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7142 stmmac_pmt(priv, priv->hw, priv->wolopts); 7143 priv->irq_wake = 1; 7144 } else { 7145 mutex_unlock(&priv->lock); 7146 rtnl_lock(); 7147 if (device_may_wakeup(priv->device)) 7148 phylink_speed_down(priv->phylink, false); 7149 phylink_stop(priv->phylink); 7150 rtnl_unlock(); 7151 mutex_lock(&priv->lock); 7152 7153 stmmac_mac_set(priv, priv->ioaddr, false); 7154 pinctrl_pm_select_sleep_state(priv->device); 7155 /* Disable clock in case of PWM is off */ 7156 clk_disable_unprepare(priv->plat->clk_ptp_ref); 7157 ret = pm_runtime_force_suspend(dev); 7158 if (ret) { 7159 mutex_unlock(&priv->lock); 7160 return ret; 7161 } 7162 } 7163 7164 mutex_unlock(&priv->lock); 7165 7166 if (priv->dma_cap.fpesel) { 7167 /* Disable FPE */ 7168 stmmac_fpe_configure(priv, priv->ioaddr, 7169 priv->plat->tx_queues_to_use, 7170 priv->plat->rx_queues_to_use, false); 7171 7172 stmmac_fpe_handshake(priv, false); 7173 } 7174 7175 priv->speed = SPEED_UNKNOWN; 7176 return 0; 7177 } 7178 EXPORT_SYMBOL_GPL(stmmac_suspend); 7179 7180 /** 7181 * stmmac_reset_queues_param - reset queue parameters 7182 * @priv: device pointer 7183 */ 7184 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7185 { 7186 u32 rx_cnt = priv->plat->rx_queues_to_use; 7187 u32 tx_cnt = priv->plat->tx_queues_to_use; 7188 u32 queue; 7189 7190 for (queue = 0; queue < rx_cnt; queue++) { 7191 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 7192 7193 rx_q->cur_rx = 0; 7194 rx_q->dirty_rx = 0; 7195 } 7196 7197 for (queue = 0; queue < tx_cnt; queue++) { 7198 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 7199 7200 tx_q->cur_tx = 0; 7201 tx_q->dirty_tx = 0; 7202 tx_q->mss = 0; 7203 7204 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7205 } 7206 } 7207 7208 /** 7209 * stmmac_resume - resume callback 7210 * @dev: device pointer 7211 * Description: when resume this function is invoked to setup the DMA and CORE 7212 * in a usable state. 7213 */ 7214 int stmmac_resume(struct device *dev) 7215 { 7216 struct net_device *ndev = dev_get_drvdata(dev); 7217 struct stmmac_priv *priv = netdev_priv(ndev); 7218 int ret; 7219 7220 if (!netif_running(ndev)) 7221 return 0; 7222 7223 /* Power Down bit, into the PM register, is cleared 7224 * automatically as soon as a magic packet or a Wake-up frame 7225 * is received. Anyway, it's better to manually clear 7226 * this bit because it can generate problems while resuming 7227 * from another devices (e.g. serial console). 7228 */ 7229 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7230 mutex_lock(&priv->lock); 7231 stmmac_pmt(priv, priv->hw, 0); 7232 mutex_unlock(&priv->lock); 7233 priv->irq_wake = 0; 7234 } else { 7235 pinctrl_pm_select_default_state(priv->device); 7236 /* enable the clk previously disabled */ 7237 ret = pm_runtime_force_resume(dev); 7238 if (ret) 7239 return ret; 7240 if (priv->plat->clk_ptp_ref) 7241 clk_prepare_enable(priv->plat->clk_ptp_ref); 7242 /* reset the phy so that it's ready */ 7243 if (priv->mii) 7244 stmmac_mdio_reset(priv->mii); 7245 } 7246 7247 if (priv->plat->serdes_powerup) { 7248 ret = priv->plat->serdes_powerup(ndev, 7249 priv->plat->bsp_priv); 7250 7251 if (ret < 0) 7252 return ret; 7253 } 7254 7255 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 7256 rtnl_lock(); 7257 phylink_start(priv->phylink); 7258 /* We may have called phylink_speed_down before */ 7259 phylink_speed_up(priv->phylink); 7260 rtnl_unlock(); 7261 } 7262 7263 rtnl_lock(); 7264 mutex_lock(&priv->lock); 7265 7266 stmmac_reset_queues_param(priv); 7267 7268 stmmac_free_tx_skbufs(priv); 7269 stmmac_clear_descriptors(priv); 7270 7271 stmmac_hw_setup(ndev, false); 7272 stmmac_init_coalesce(priv); 7273 stmmac_set_rx_mode(ndev); 7274 7275 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7276 7277 stmmac_enable_all_queues(priv); 7278 7279 mutex_unlock(&priv->lock); 7280 rtnl_unlock(); 7281 7282 phylink_mac_change(priv->phylink, true); 7283 7284 netif_device_attach(ndev); 7285 7286 return 0; 7287 } 7288 EXPORT_SYMBOL_GPL(stmmac_resume); 7289 7290 #ifndef MODULE 7291 static int __init stmmac_cmdline_opt(char *str) 7292 { 7293 char *opt; 7294 7295 if (!str || !*str) 7296 return -EINVAL; 7297 while ((opt = strsep(&str, ",")) != NULL) { 7298 if (!strncmp(opt, "debug:", 6)) { 7299 if (kstrtoint(opt + 6, 0, &debug)) 7300 goto err; 7301 } else if (!strncmp(opt, "phyaddr:", 8)) { 7302 if (kstrtoint(opt + 8, 0, &phyaddr)) 7303 goto err; 7304 } else if (!strncmp(opt, "buf_sz:", 7)) { 7305 if (kstrtoint(opt + 7, 0, &buf_sz)) 7306 goto err; 7307 } else if (!strncmp(opt, "tc:", 3)) { 7308 if (kstrtoint(opt + 3, 0, &tc)) 7309 goto err; 7310 } else if (!strncmp(opt, "watchdog:", 9)) { 7311 if (kstrtoint(opt + 9, 0, &watchdog)) 7312 goto err; 7313 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7314 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7315 goto err; 7316 } else if (!strncmp(opt, "pause:", 6)) { 7317 if (kstrtoint(opt + 6, 0, &pause)) 7318 goto err; 7319 } else if (!strncmp(opt, "eee_timer:", 10)) { 7320 if (kstrtoint(opt + 10, 0, &eee_timer)) 7321 goto err; 7322 } else if (!strncmp(opt, "chain_mode:", 11)) { 7323 if (kstrtoint(opt + 11, 0, &chain_mode)) 7324 goto err; 7325 } 7326 } 7327 return 0; 7328 7329 err: 7330 pr_err("%s: ERROR broken module parameter conversion", __func__); 7331 return -EINVAL; 7332 } 7333 7334 __setup("stmmaceth=", stmmac_cmdline_opt); 7335 #endif /* MODULE */ 7336 7337 static int __init stmmac_init(void) 7338 { 7339 #ifdef CONFIG_DEBUG_FS 7340 /* Create debugfs main directory if it doesn't exist yet */ 7341 if (!stmmac_fs_dir) 7342 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7343 register_netdevice_notifier(&stmmac_notifier); 7344 #endif 7345 7346 return 0; 7347 } 7348 7349 static void __exit stmmac_exit(void) 7350 { 7351 #ifdef CONFIG_DEBUG_FS 7352 unregister_netdevice_notifier(&stmmac_notifier); 7353 debugfs_remove_recursive(stmmac_fs_dir); 7354 #endif 7355 } 7356 7357 module_init(stmmac_init) 7358 module_exit(stmmac_exit) 7359 7360 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7361 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7362 MODULE_LICENSE("GPL"); 7363