1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 /** 180 * stmmac_stop_all_queues - Stop all queues 181 * @priv: driver private structure 182 */ 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 184 { 185 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 186 u32 queue; 187 188 for (queue = 0; queue < tx_queues_cnt; queue++) 189 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 190 } 191 192 /** 193 * stmmac_start_all_queues - Start all queues 194 * @priv: driver private structure 195 */ 196 static void stmmac_start_all_queues(struct stmmac_priv *priv) 197 { 198 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 199 u32 queue; 200 201 for (queue = 0; queue < tx_queues_cnt; queue++) 202 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 203 } 204 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 206 { 207 if (!test_bit(STMMAC_DOWN, &priv->state) && 208 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 209 queue_work(priv->wq, &priv->service_task); 210 } 211 212 static void stmmac_global_err(struct stmmac_priv *priv) 213 { 214 netif_carrier_off(priv->dev); 215 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 216 stmmac_service_event_schedule(priv); 217 } 218 219 /** 220 * stmmac_clk_csr_set - dynamically set the MDC clock 221 * @priv: driver private structure 222 * Description: this is to dynamically set the MDC clock according to the csr 223 * clock input. 224 * Note: 225 * If a specific clk_csr value is passed from the platform 226 * this means that the CSR Clock Range selection cannot be 227 * changed at run-time and it is fixed (as reported in the driver 228 * documentation). Viceversa the driver will try to set the MDC 229 * clock dynamically according to the actual clock input. 230 */ 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 232 { 233 u32 clk_rate; 234 235 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 236 237 /* Platform provided default clk_csr would be assumed valid 238 * for all other cases except for the below mentioned ones. 239 * For values higher than the IEEE 802.3 specified frequency 240 * we can not estimate the proper divider as it is not known 241 * the frequency of clk_csr_i. So we do not change the default 242 * divider. 243 */ 244 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 245 if (clk_rate < CSR_F_35M) 246 priv->clk_csr = STMMAC_CSR_20_35M; 247 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 248 priv->clk_csr = STMMAC_CSR_35_60M; 249 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 250 priv->clk_csr = STMMAC_CSR_60_100M; 251 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 252 priv->clk_csr = STMMAC_CSR_100_150M; 253 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 254 priv->clk_csr = STMMAC_CSR_150_250M; 255 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 256 priv->clk_csr = STMMAC_CSR_250_300M; 257 } 258 259 if (priv->plat->has_sun8i) { 260 if (clk_rate > 160000000) 261 priv->clk_csr = 0x03; 262 else if (clk_rate > 80000000) 263 priv->clk_csr = 0x02; 264 else if (clk_rate > 40000000) 265 priv->clk_csr = 0x01; 266 else 267 priv->clk_csr = 0; 268 } 269 270 if (priv->plat->has_xgmac) { 271 if (clk_rate > 400000000) 272 priv->clk_csr = 0x5; 273 else if (clk_rate > 350000000) 274 priv->clk_csr = 0x4; 275 else if (clk_rate > 300000000) 276 priv->clk_csr = 0x3; 277 else if (clk_rate > 250000000) 278 priv->clk_csr = 0x2; 279 else if (clk_rate > 150000000) 280 priv->clk_csr = 0x1; 281 else 282 priv->clk_csr = 0x0; 283 } 284 } 285 286 static void print_pkt(unsigned char *buf, int len) 287 { 288 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 289 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 290 } 291 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 293 { 294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 295 u32 avail; 296 297 if (tx_q->dirty_tx > tx_q->cur_tx) 298 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 299 else 300 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 301 302 return avail; 303 } 304 305 /** 306 * stmmac_rx_dirty - Get RX queue dirty 307 * @priv: driver private structure 308 * @queue: RX queue index 309 */ 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 311 { 312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 313 u32 dirty; 314 315 if (rx_q->dirty_rx <= rx_q->cur_rx) 316 dirty = rx_q->cur_rx - rx_q->dirty_rx; 317 else 318 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 319 320 return dirty; 321 } 322 323 /** 324 * stmmac_enable_eee_mode - check and enter in LPI mode 325 * @priv: driver private structure 326 * Description: this function is to verify and enter in LPI mode in case of 327 * EEE. 328 */ 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 330 { 331 u32 tx_cnt = priv->plat->tx_queues_to_use; 332 u32 queue; 333 334 /* check if all TX queues have the work finished */ 335 for (queue = 0; queue < tx_cnt; queue++) { 336 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 337 338 if (tx_q->dirty_tx != tx_q->cur_tx) 339 return; /* still unfinished work */ 340 } 341 342 /* Check and enter in LPI mode */ 343 if (!priv->tx_path_in_lpi_mode) 344 stmmac_set_eee_mode(priv, priv->hw, 345 priv->plat->en_tx_lpi_clockgating); 346 } 347 348 /** 349 * stmmac_disable_eee_mode - disable and exit from LPI mode 350 * @priv: driver private structure 351 * Description: this function is to exit and disable EEE in case of 352 * LPI state is true. This is called by the xmit. 353 */ 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 355 { 356 stmmac_reset_eee_mode(priv, priv->hw); 357 del_timer_sync(&priv->eee_ctrl_timer); 358 priv->tx_path_in_lpi_mode = false; 359 } 360 361 /** 362 * stmmac_eee_ctrl_timer - EEE TX SW timer. 363 * @arg : data hook 364 * Description: 365 * if there is no data transfer and if we are not in LPI state, 366 * then MAC Transmitter can be moved to LPI state. 367 */ 368 static void stmmac_eee_ctrl_timer(struct timer_list *t) 369 { 370 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 371 372 stmmac_enable_eee_mode(priv); 373 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 374 } 375 376 /** 377 * stmmac_eee_init - init EEE 378 * @priv: driver private structure 379 * Description: 380 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 381 * can also manage EEE, this function enable the LPI state and start related 382 * timer. 383 */ 384 bool stmmac_eee_init(struct stmmac_priv *priv) 385 { 386 int eee_tw_timer = priv->eee_tw_timer; 387 388 /* Using PCS we cannot dial with the phy registers at this stage 389 * so we do not support extra feature like EEE. 390 */ 391 if (priv->hw->pcs == STMMAC_PCS_TBI || 392 priv->hw->pcs == STMMAC_PCS_RTBI) 393 return false; 394 395 /* Check if MAC core supports the EEE feature. */ 396 if (!priv->dma_cap.eee) 397 return false; 398 399 mutex_lock(&priv->lock); 400 401 /* Check if it needs to be deactivated */ 402 if (!priv->eee_active) { 403 if (priv->eee_enabled) { 404 netdev_dbg(priv->dev, "disable EEE\n"); 405 del_timer_sync(&priv->eee_ctrl_timer); 406 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 407 } 408 mutex_unlock(&priv->lock); 409 return false; 410 } 411 412 if (priv->eee_active && !priv->eee_enabled) { 413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 415 eee_tw_timer); 416 } 417 418 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 419 420 mutex_unlock(&priv->lock); 421 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 422 return true; 423 } 424 425 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 426 * @priv: driver private structure 427 * @p : descriptor pointer 428 * @skb : the socket buffer 429 * Description : 430 * This function will read timestamp from the descriptor & pass it to stack. 431 * and also perform some sanity checks. 432 */ 433 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 434 struct dma_desc *p, struct sk_buff *skb) 435 { 436 struct skb_shared_hwtstamps shhwtstamp; 437 bool found = false; 438 u64 ns = 0; 439 440 if (!priv->hwts_tx_en) 441 return; 442 443 /* exit if skb doesn't support hw tstamp */ 444 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 445 return; 446 447 /* check tx tstamp status */ 448 if (stmmac_get_tx_timestamp_status(priv, p)) { 449 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 450 found = true; 451 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 452 found = true; 453 } 454 455 if (found) { 456 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 457 shhwtstamp.hwtstamp = ns_to_ktime(ns); 458 459 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 460 /* pass tstamp to stack */ 461 skb_tstamp_tx(skb, &shhwtstamp); 462 } 463 } 464 465 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 466 * @priv: driver private structure 467 * @p : descriptor pointer 468 * @np : next descriptor pointer 469 * @skb : the socket buffer 470 * Description : 471 * This function will read received packet's timestamp from the descriptor 472 * and pass it to stack. It also perform some sanity checks. 473 */ 474 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 475 struct dma_desc *np, struct sk_buff *skb) 476 { 477 struct skb_shared_hwtstamps *shhwtstamp = NULL; 478 struct dma_desc *desc = p; 479 u64 ns = 0; 480 481 if (!priv->hwts_rx_en) 482 return; 483 /* For GMAC4, the valid timestamp is from CTX next desc. */ 484 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 485 desc = np; 486 487 /* Check if timestamp is available */ 488 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 489 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 490 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 491 shhwtstamp = skb_hwtstamps(skb); 492 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 493 shhwtstamp->hwtstamp = ns_to_ktime(ns); 494 } else { 495 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 496 } 497 } 498 499 /** 500 * stmmac_hwtstamp_set - control hardware timestamping. 501 * @dev: device pointer. 502 * @ifr: An IOCTL specific structure, that can contain a pointer to 503 * a proprietary structure used to pass information to the driver. 504 * Description: 505 * This function configures the MAC to enable/disable both outgoing(TX) 506 * and incoming(RX) packets time stamping based on user input. 507 * Return Value: 508 * 0 on success and an appropriate -ve integer on failure. 509 */ 510 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 511 { 512 struct stmmac_priv *priv = netdev_priv(dev); 513 struct hwtstamp_config config; 514 struct timespec64 now; 515 u64 temp = 0; 516 u32 ptp_v2 = 0; 517 u32 tstamp_all = 0; 518 u32 ptp_over_ipv4_udp = 0; 519 u32 ptp_over_ipv6_udp = 0; 520 u32 ptp_over_ethernet = 0; 521 u32 snap_type_sel = 0; 522 u32 ts_master_en = 0; 523 u32 ts_event_en = 0; 524 u32 sec_inc = 0; 525 u32 value = 0; 526 bool xmac; 527 528 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 529 530 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 531 netdev_alert(priv->dev, "No support for HW time stamping\n"); 532 priv->hwts_tx_en = 0; 533 priv->hwts_rx_en = 0; 534 535 return -EOPNOTSUPP; 536 } 537 538 if (copy_from_user(&config, ifr->ifr_data, 539 sizeof(config))) 540 return -EFAULT; 541 542 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 543 __func__, config.flags, config.tx_type, config.rx_filter); 544 545 /* reserved for future extensions */ 546 if (config.flags) 547 return -EINVAL; 548 549 if (config.tx_type != HWTSTAMP_TX_OFF && 550 config.tx_type != HWTSTAMP_TX_ON) 551 return -ERANGE; 552 553 if (priv->adv_ts) { 554 switch (config.rx_filter) { 555 case HWTSTAMP_FILTER_NONE: 556 /* time stamp no incoming packet at all */ 557 config.rx_filter = HWTSTAMP_FILTER_NONE; 558 break; 559 560 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 561 /* PTP v1, UDP, any kind of event packet */ 562 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 563 /* 'xmac' hardware can support Sync, Pdelay_Req and 564 * Pdelay_resp by setting bit14 and bits17/16 to 01 565 * This leaves Delay_Req timestamps out. 566 * Enable all events *and* general purpose message 567 * timestamping 568 */ 569 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 570 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 571 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 572 break; 573 574 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 575 /* PTP v1, UDP, Sync packet */ 576 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 577 /* take time stamp for SYNC messages only */ 578 ts_event_en = PTP_TCR_TSEVNTENA; 579 580 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 581 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 582 break; 583 584 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 585 /* PTP v1, UDP, Delay_req packet */ 586 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 587 /* take time stamp for Delay_Req messages only */ 588 ts_master_en = PTP_TCR_TSMSTRENA; 589 ts_event_en = PTP_TCR_TSEVNTENA; 590 591 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 592 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 593 break; 594 595 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 596 /* PTP v2, UDP, any kind of event packet */ 597 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 598 ptp_v2 = PTP_TCR_TSVER2ENA; 599 /* take time stamp for all event messages */ 600 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 601 602 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 603 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 604 break; 605 606 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 607 /* PTP v2, UDP, Sync packet */ 608 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 609 ptp_v2 = PTP_TCR_TSVER2ENA; 610 /* take time stamp for SYNC messages only */ 611 ts_event_en = PTP_TCR_TSEVNTENA; 612 613 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 614 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 615 break; 616 617 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 618 /* PTP v2, UDP, Delay_req packet */ 619 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 620 ptp_v2 = PTP_TCR_TSVER2ENA; 621 /* take time stamp for Delay_Req messages only */ 622 ts_master_en = PTP_TCR_TSMSTRENA; 623 ts_event_en = PTP_TCR_TSEVNTENA; 624 625 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 626 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 627 break; 628 629 case HWTSTAMP_FILTER_PTP_V2_EVENT: 630 /* PTP v2/802.AS1 any layer, any kind of event packet */ 631 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 632 ptp_v2 = PTP_TCR_TSVER2ENA; 633 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 634 if (priv->synopsys_id != DWMAC_CORE_5_10) 635 ts_event_en = PTP_TCR_TSEVNTENA; 636 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 637 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 638 ptp_over_ethernet = PTP_TCR_TSIPENA; 639 break; 640 641 case HWTSTAMP_FILTER_PTP_V2_SYNC: 642 /* PTP v2/802.AS1, any layer, Sync packet */ 643 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 644 ptp_v2 = PTP_TCR_TSVER2ENA; 645 /* take time stamp for SYNC messages only */ 646 ts_event_en = PTP_TCR_TSEVNTENA; 647 648 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 649 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 650 ptp_over_ethernet = PTP_TCR_TSIPENA; 651 break; 652 653 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 654 /* PTP v2/802.AS1, any layer, Delay_req packet */ 655 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 656 ptp_v2 = PTP_TCR_TSVER2ENA; 657 /* take time stamp for Delay_Req messages only */ 658 ts_master_en = PTP_TCR_TSMSTRENA; 659 ts_event_en = PTP_TCR_TSEVNTENA; 660 661 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 662 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 663 ptp_over_ethernet = PTP_TCR_TSIPENA; 664 break; 665 666 case HWTSTAMP_FILTER_NTP_ALL: 667 case HWTSTAMP_FILTER_ALL: 668 /* time stamp any incoming packet */ 669 config.rx_filter = HWTSTAMP_FILTER_ALL; 670 tstamp_all = PTP_TCR_TSENALL; 671 break; 672 673 default: 674 return -ERANGE; 675 } 676 } else { 677 switch (config.rx_filter) { 678 case HWTSTAMP_FILTER_NONE: 679 config.rx_filter = HWTSTAMP_FILTER_NONE; 680 break; 681 default: 682 /* PTP v1, UDP, any kind of event packet */ 683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 684 break; 685 } 686 } 687 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 688 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 689 690 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 691 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 692 else { 693 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 694 tstamp_all | ptp_v2 | ptp_over_ethernet | 695 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 696 ts_master_en | snap_type_sel); 697 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 698 699 /* program Sub Second Increment reg */ 700 stmmac_config_sub_second_increment(priv, 701 priv->ptpaddr, priv->plat->clk_ptp_rate, 702 xmac, &sec_inc); 703 temp = div_u64(1000000000ULL, sec_inc); 704 705 /* Store sub second increment and flags for later use */ 706 priv->sub_second_inc = sec_inc; 707 priv->systime_flags = value; 708 709 /* calculate default added value: 710 * formula is : 711 * addend = (2^32)/freq_div_ratio; 712 * where, freq_div_ratio = 1e9ns/sec_inc 713 */ 714 temp = (u64)(temp << 32); 715 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 716 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 717 718 /* initialize system time */ 719 ktime_get_real_ts64(&now); 720 721 /* lower 32 bits of tv_sec are safe until y2106 */ 722 stmmac_init_systime(priv, priv->ptpaddr, 723 (u32)now.tv_sec, now.tv_nsec); 724 } 725 726 memcpy(&priv->tstamp_config, &config, sizeof(config)); 727 728 return copy_to_user(ifr->ifr_data, &config, 729 sizeof(config)) ? -EFAULT : 0; 730 } 731 732 /** 733 * stmmac_hwtstamp_get - read hardware timestamping. 734 * @dev: device pointer. 735 * @ifr: An IOCTL specific structure, that can contain a pointer to 736 * a proprietary structure used to pass information to the driver. 737 * Description: 738 * This function obtain the current hardware timestamping settings 739 as requested. 740 */ 741 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 742 { 743 struct stmmac_priv *priv = netdev_priv(dev); 744 struct hwtstamp_config *config = &priv->tstamp_config; 745 746 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 747 return -EOPNOTSUPP; 748 749 return copy_to_user(ifr->ifr_data, config, 750 sizeof(*config)) ? -EFAULT : 0; 751 } 752 753 /** 754 * stmmac_init_ptp - init PTP 755 * @priv: driver private structure 756 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 757 * This is done by looking at the HW cap. register. 758 * This function also registers the ptp driver. 759 */ 760 static int stmmac_init_ptp(struct stmmac_priv *priv) 761 { 762 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 763 764 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 765 return -EOPNOTSUPP; 766 767 priv->adv_ts = 0; 768 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 769 if (xmac && priv->dma_cap.atime_stamp) 770 priv->adv_ts = 1; 771 /* Dwmac 3.x core with extend_desc can support adv_ts */ 772 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 773 priv->adv_ts = 1; 774 775 if (priv->dma_cap.time_stamp) 776 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 777 778 if (priv->adv_ts) 779 netdev_info(priv->dev, 780 "IEEE 1588-2008 Advanced Timestamp supported\n"); 781 782 priv->hwts_tx_en = 0; 783 priv->hwts_rx_en = 0; 784 785 stmmac_ptp_register(priv); 786 787 return 0; 788 } 789 790 static void stmmac_release_ptp(struct stmmac_priv *priv) 791 { 792 if (priv->plat->clk_ptp_ref) 793 clk_disable_unprepare(priv->plat->clk_ptp_ref); 794 stmmac_ptp_unregister(priv); 795 } 796 797 /** 798 * stmmac_mac_flow_ctrl - Configure flow control in all queues 799 * @priv: driver private structure 800 * Description: It is used for configuring the flow control in all queues 801 */ 802 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 803 { 804 u32 tx_cnt = priv->plat->tx_queues_to_use; 805 806 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 807 priv->pause, tx_cnt); 808 } 809 810 static void stmmac_validate(struct phylink_config *config, 811 unsigned long *supported, 812 struct phylink_link_state *state) 813 { 814 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 815 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 816 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 817 int tx_cnt = priv->plat->tx_queues_to_use; 818 int max_speed = priv->plat->max_speed; 819 820 phylink_set(mac_supported, 10baseT_Half); 821 phylink_set(mac_supported, 10baseT_Full); 822 phylink_set(mac_supported, 100baseT_Half); 823 phylink_set(mac_supported, 100baseT_Full); 824 phylink_set(mac_supported, 1000baseT_Half); 825 phylink_set(mac_supported, 1000baseT_Full); 826 phylink_set(mac_supported, 1000baseKX_Full); 827 828 phylink_set(mac_supported, Autoneg); 829 phylink_set(mac_supported, Pause); 830 phylink_set(mac_supported, Asym_Pause); 831 phylink_set_port_modes(mac_supported); 832 833 /* Cut down 1G if asked to */ 834 if ((max_speed > 0) && (max_speed < 1000)) { 835 phylink_set(mask, 1000baseT_Full); 836 phylink_set(mask, 1000baseX_Full); 837 } else if (priv->plat->has_xgmac) { 838 if (!max_speed || (max_speed >= 2500)) { 839 phylink_set(mac_supported, 2500baseT_Full); 840 phylink_set(mac_supported, 2500baseX_Full); 841 } 842 if (!max_speed || (max_speed >= 5000)) { 843 phylink_set(mac_supported, 5000baseT_Full); 844 } 845 if (!max_speed || (max_speed >= 10000)) { 846 phylink_set(mac_supported, 10000baseSR_Full); 847 phylink_set(mac_supported, 10000baseLR_Full); 848 phylink_set(mac_supported, 10000baseER_Full); 849 phylink_set(mac_supported, 10000baseLRM_Full); 850 phylink_set(mac_supported, 10000baseT_Full); 851 phylink_set(mac_supported, 10000baseKX4_Full); 852 phylink_set(mac_supported, 10000baseKR_Full); 853 } 854 if (!max_speed || (max_speed >= 25000)) { 855 phylink_set(mac_supported, 25000baseCR_Full); 856 phylink_set(mac_supported, 25000baseKR_Full); 857 phylink_set(mac_supported, 25000baseSR_Full); 858 } 859 if (!max_speed || (max_speed >= 40000)) { 860 phylink_set(mac_supported, 40000baseKR4_Full); 861 phylink_set(mac_supported, 40000baseCR4_Full); 862 phylink_set(mac_supported, 40000baseSR4_Full); 863 phylink_set(mac_supported, 40000baseLR4_Full); 864 } 865 if (!max_speed || (max_speed >= 50000)) { 866 phylink_set(mac_supported, 50000baseCR2_Full); 867 phylink_set(mac_supported, 50000baseKR2_Full); 868 phylink_set(mac_supported, 50000baseSR2_Full); 869 phylink_set(mac_supported, 50000baseKR_Full); 870 phylink_set(mac_supported, 50000baseSR_Full); 871 phylink_set(mac_supported, 50000baseCR_Full); 872 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 873 phylink_set(mac_supported, 50000baseDR_Full); 874 } 875 if (!max_speed || (max_speed >= 100000)) { 876 phylink_set(mac_supported, 100000baseKR4_Full); 877 phylink_set(mac_supported, 100000baseSR4_Full); 878 phylink_set(mac_supported, 100000baseCR4_Full); 879 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 880 phylink_set(mac_supported, 100000baseKR2_Full); 881 phylink_set(mac_supported, 100000baseSR2_Full); 882 phylink_set(mac_supported, 100000baseCR2_Full); 883 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 884 phylink_set(mac_supported, 100000baseDR2_Full); 885 } 886 } 887 888 /* Half-Duplex can only work with single queue */ 889 if (tx_cnt > 1) { 890 phylink_set(mask, 10baseT_Half); 891 phylink_set(mask, 100baseT_Half); 892 phylink_set(mask, 1000baseT_Half); 893 } 894 895 linkmode_and(supported, supported, mac_supported); 896 linkmode_andnot(supported, supported, mask); 897 898 linkmode_and(state->advertising, state->advertising, mac_supported); 899 linkmode_andnot(state->advertising, state->advertising, mask); 900 901 /* If PCS is supported, check which modes it supports. */ 902 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 903 } 904 905 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 906 struct phylink_link_state *state) 907 { 908 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 909 910 state->link = 0; 911 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 912 } 913 914 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 915 const struct phylink_link_state *state) 916 { 917 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 918 919 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 920 } 921 922 static void stmmac_mac_an_restart(struct phylink_config *config) 923 { 924 /* Not Supported */ 925 } 926 927 static void stmmac_mac_link_down(struct phylink_config *config, 928 unsigned int mode, phy_interface_t interface) 929 { 930 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 931 932 stmmac_mac_set(priv, priv->ioaddr, false); 933 priv->eee_active = false; 934 priv->tx_lpi_enabled = false; 935 stmmac_eee_init(priv); 936 stmmac_set_eee_pls(priv, priv->hw, false); 937 } 938 939 static void stmmac_mac_link_up(struct phylink_config *config, 940 struct phy_device *phy, 941 unsigned int mode, phy_interface_t interface, 942 int speed, int duplex, 943 bool tx_pause, bool rx_pause) 944 { 945 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 946 u32 ctrl; 947 948 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 949 950 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 951 ctrl &= ~priv->hw->link.speed_mask; 952 953 if (interface == PHY_INTERFACE_MODE_USXGMII) { 954 switch (speed) { 955 case SPEED_10000: 956 ctrl |= priv->hw->link.xgmii.speed10000; 957 break; 958 case SPEED_5000: 959 ctrl |= priv->hw->link.xgmii.speed5000; 960 break; 961 case SPEED_2500: 962 ctrl |= priv->hw->link.xgmii.speed2500; 963 break; 964 default: 965 return; 966 } 967 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 968 switch (speed) { 969 case SPEED_100000: 970 ctrl |= priv->hw->link.xlgmii.speed100000; 971 break; 972 case SPEED_50000: 973 ctrl |= priv->hw->link.xlgmii.speed50000; 974 break; 975 case SPEED_40000: 976 ctrl |= priv->hw->link.xlgmii.speed40000; 977 break; 978 case SPEED_25000: 979 ctrl |= priv->hw->link.xlgmii.speed25000; 980 break; 981 case SPEED_10000: 982 ctrl |= priv->hw->link.xgmii.speed10000; 983 break; 984 case SPEED_2500: 985 ctrl |= priv->hw->link.speed2500; 986 break; 987 case SPEED_1000: 988 ctrl |= priv->hw->link.speed1000; 989 break; 990 default: 991 return; 992 } 993 } else { 994 switch (speed) { 995 case SPEED_2500: 996 ctrl |= priv->hw->link.speed2500; 997 break; 998 case SPEED_1000: 999 ctrl |= priv->hw->link.speed1000; 1000 break; 1001 case SPEED_100: 1002 ctrl |= priv->hw->link.speed100; 1003 break; 1004 case SPEED_10: 1005 ctrl |= priv->hw->link.speed10; 1006 break; 1007 default: 1008 return; 1009 } 1010 } 1011 1012 priv->speed = speed; 1013 1014 if (priv->plat->fix_mac_speed) 1015 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1016 1017 if (!duplex) 1018 ctrl &= ~priv->hw->link.duplex; 1019 else 1020 ctrl |= priv->hw->link.duplex; 1021 1022 /* Flow Control operation */ 1023 if (tx_pause && rx_pause) 1024 stmmac_mac_flow_ctrl(priv, duplex); 1025 1026 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1027 1028 stmmac_mac_set(priv, priv->ioaddr, true); 1029 if (phy && priv->dma_cap.eee) { 1030 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1031 priv->eee_enabled = stmmac_eee_init(priv); 1032 priv->tx_lpi_enabled = priv->eee_enabled; 1033 stmmac_set_eee_pls(priv, priv->hw, true); 1034 } 1035 } 1036 1037 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1038 .validate = stmmac_validate, 1039 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1040 .mac_config = stmmac_mac_config, 1041 .mac_an_restart = stmmac_mac_an_restart, 1042 .mac_link_down = stmmac_mac_link_down, 1043 .mac_link_up = stmmac_mac_link_up, 1044 }; 1045 1046 /** 1047 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1048 * @priv: driver private structure 1049 * Description: this is to verify if the HW supports the PCS. 1050 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1051 * configured for the TBI, RTBI, or SGMII PHY interface. 1052 */ 1053 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1054 { 1055 int interface = priv->plat->interface; 1056 1057 if (priv->dma_cap.pcs) { 1058 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1059 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1060 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1061 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1062 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1063 priv->hw->pcs = STMMAC_PCS_RGMII; 1064 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1065 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1066 priv->hw->pcs = STMMAC_PCS_SGMII; 1067 } 1068 } 1069 } 1070 1071 /** 1072 * stmmac_init_phy - PHY initialization 1073 * @dev: net device structure 1074 * Description: it initializes the driver's PHY state, and attaches the PHY 1075 * to the mac driver. 1076 * Return value: 1077 * 0 on success 1078 */ 1079 static int stmmac_init_phy(struct net_device *dev) 1080 { 1081 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1082 struct stmmac_priv *priv = netdev_priv(dev); 1083 struct device_node *node; 1084 int ret; 1085 1086 node = priv->plat->phylink_node; 1087 1088 if (node) 1089 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1090 1091 /* Some DT bindings do not set-up the PHY handle. Let's try to 1092 * manually parse it 1093 */ 1094 if (!node || ret) { 1095 int addr = priv->plat->phy_addr; 1096 struct phy_device *phydev; 1097 1098 phydev = mdiobus_get_phy(priv->mii, addr); 1099 if (!phydev) { 1100 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1101 return -ENODEV; 1102 } 1103 1104 ret = phylink_connect_phy(priv->phylink, phydev); 1105 } 1106 1107 phylink_ethtool_get_wol(priv->phylink, &wol); 1108 device_set_wakeup_capable(priv->device, !!wol.supported); 1109 1110 return ret; 1111 } 1112 1113 static int stmmac_phy_setup(struct stmmac_priv *priv) 1114 { 1115 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1116 int mode = priv->plat->phy_interface; 1117 struct phylink *phylink; 1118 1119 priv->phylink_config.dev = &priv->dev->dev; 1120 priv->phylink_config.type = PHYLINK_NETDEV; 1121 priv->phylink_config.pcs_poll = true; 1122 1123 if (!fwnode) 1124 fwnode = dev_fwnode(priv->device); 1125 1126 phylink = phylink_create(&priv->phylink_config, fwnode, 1127 mode, &stmmac_phylink_mac_ops); 1128 if (IS_ERR(phylink)) 1129 return PTR_ERR(phylink); 1130 1131 priv->phylink = phylink; 1132 return 0; 1133 } 1134 1135 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1136 { 1137 u32 rx_cnt = priv->plat->rx_queues_to_use; 1138 void *head_rx; 1139 u32 queue; 1140 1141 /* Display RX rings */ 1142 for (queue = 0; queue < rx_cnt; queue++) { 1143 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1144 1145 pr_info("\tRX Queue %u rings\n", queue); 1146 1147 if (priv->extend_desc) 1148 head_rx = (void *)rx_q->dma_erx; 1149 else 1150 head_rx = (void *)rx_q->dma_rx; 1151 1152 /* Display RX ring */ 1153 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1154 } 1155 } 1156 1157 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1158 { 1159 u32 tx_cnt = priv->plat->tx_queues_to_use; 1160 void *head_tx; 1161 u32 queue; 1162 1163 /* Display TX rings */ 1164 for (queue = 0; queue < tx_cnt; queue++) { 1165 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1166 1167 pr_info("\tTX Queue %d rings\n", queue); 1168 1169 if (priv->extend_desc) 1170 head_tx = (void *)tx_q->dma_etx; 1171 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1172 head_tx = (void *)tx_q->dma_entx; 1173 else 1174 head_tx = (void *)tx_q->dma_tx; 1175 1176 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1177 } 1178 } 1179 1180 static void stmmac_display_rings(struct stmmac_priv *priv) 1181 { 1182 /* Display RX ring */ 1183 stmmac_display_rx_rings(priv); 1184 1185 /* Display TX ring */ 1186 stmmac_display_tx_rings(priv); 1187 } 1188 1189 static int stmmac_set_bfsize(int mtu, int bufsize) 1190 { 1191 int ret = bufsize; 1192 1193 if (mtu >= BUF_SIZE_8KiB) 1194 ret = BUF_SIZE_16KiB; 1195 else if (mtu >= BUF_SIZE_4KiB) 1196 ret = BUF_SIZE_8KiB; 1197 else if (mtu >= BUF_SIZE_2KiB) 1198 ret = BUF_SIZE_4KiB; 1199 else if (mtu > DEFAULT_BUFSIZE) 1200 ret = BUF_SIZE_2KiB; 1201 else 1202 ret = DEFAULT_BUFSIZE; 1203 1204 return ret; 1205 } 1206 1207 /** 1208 * stmmac_clear_rx_descriptors - clear RX descriptors 1209 * @priv: driver private structure 1210 * @queue: RX queue index 1211 * Description: this function is called to clear the RX descriptors 1212 * in case of both basic and extended descriptors are used. 1213 */ 1214 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1215 { 1216 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1217 int i; 1218 1219 /* Clear the RX descriptors */ 1220 for (i = 0; i < DMA_RX_SIZE; i++) 1221 if (priv->extend_desc) 1222 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1223 priv->use_riwt, priv->mode, 1224 (i == DMA_RX_SIZE - 1), 1225 priv->dma_buf_sz); 1226 else 1227 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1228 priv->use_riwt, priv->mode, 1229 (i == DMA_RX_SIZE - 1), 1230 priv->dma_buf_sz); 1231 } 1232 1233 /** 1234 * stmmac_clear_tx_descriptors - clear tx descriptors 1235 * @priv: driver private structure 1236 * @queue: TX queue index. 1237 * Description: this function is called to clear the TX descriptors 1238 * in case of both basic and extended descriptors are used. 1239 */ 1240 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1241 { 1242 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1243 int i; 1244 1245 /* Clear the TX descriptors */ 1246 for (i = 0; i < DMA_TX_SIZE; i++) { 1247 int last = (i == (DMA_TX_SIZE - 1)); 1248 struct dma_desc *p; 1249 1250 if (priv->extend_desc) 1251 p = &tx_q->dma_etx[i].basic; 1252 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1253 p = &tx_q->dma_entx[i].basic; 1254 else 1255 p = &tx_q->dma_tx[i]; 1256 1257 stmmac_init_tx_desc(priv, p, priv->mode, last); 1258 } 1259 } 1260 1261 /** 1262 * stmmac_clear_descriptors - clear descriptors 1263 * @priv: driver private structure 1264 * Description: this function is called to clear the TX and RX descriptors 1265 * in case of both basic and extended descriptors are used. 1266 */ 1267 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1268 { 1269 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1270 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1271 u32 queue; 1272 1273 /* Clear the RX descriptors */ 1274 for (queue = 0; queue < rx_queue_cnt; queue++) 1275 stmmac_clear_rx_descriptors(priv, queue); 1276 1277 /* Clear the TX descriptors */ 1278 for (queue = 0; queue < tx_queue_cnt; queue++) 1279 stmmac_clear_tx_descriptors(priv, queue); 1280 } 1281 1282 /** 1283 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1284 * @priv: driver private structure 1285 * @p: descriptor pointer 1286 * @i: descriptor index 1287 * @flags: gfp flag 1288 * @queue: RX queue index 1289 * Description: this function is called to allocate a receive buffer, perform 1290 * the DMA mapping and init the descriptor. 1291 */ 1292 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1293 int i, gfp_t flags, u32 queue) 1294 { 1295 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1296 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1297 1298 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1299 if (!buf->page) 1300 return -ENOMEM; 1301 1302 if (priv->sph) { 1303 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1304 if (!buf->sec_page) 1305 return -ENOMEM; 1306 1307 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1308 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1309 } else { 1310 buf->sec_page = NULL; 1311 } 1312 1313 buf->addr = page_pool_get_dma_addr(buf->page); 1314 stmmac_set_desc_addr(priv, p, buf->addr); 1315 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1316 stmmac_init_desc3(priv, p); 1317 1318 return 0; 1319 } 1320 1321 /** 1322 * stmmac_free_rx_buffer - free RX dma buffers 1323 * @priv: private structure 1324 * @queue: RX queue index 1325 * @i: buffer index. 1326 */ 1327 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1328 { 1329 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1330 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1331 1332 if (buf->page) 1333 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1334 buf->page = NULL; 1335 1336 if (buf->sec_page) 1337 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1338 buf->sec_page = NULL; 1339 } 1340 1341 /** 1342 * stmmac_free_tx_buffer - free RX dma buffers 1343 * @priv: private structure 1344 * @queue: RX queue index 1345 * @i: buffer index. 1346 */ 1347 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1348 { 1349 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1350 1351 if (tx_q->tx_skbuff_dma[i].buf) { 1352 if (tx_q->tx_skbuff_dma[i].map_as_page) 1353 dma_unmap_page(priv->device, 1354 tx_q->tx_skbuff_dma[i].buf, 1355 tx_q->tx_skbuff_dma[i].len, 1356 DMA_TO_DEVICE); 1357 else 1358 dma_unmap_single(priv->device, 1359 tx_q->tx_skbuff_dma[i].buf, 1360 tx_q->tx_skbuff_dma[i].len, 1361 DMA_TO_DEVICE); 1362 } 1363 1364 if (tx_q->tx_skbuff[i]) { 1365 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1366 tx_q->tx_skbuff[i] = NULL; 1367 tx_q->tx_skbuff_dma[i].buf = 0; 1368 tx_q->tx_skbuff_dma[i].map_as_page = false; 1369 } 1370 } 1371 1372 /** 1373 * init_dma_rx_desc_rings - init the RX descriptor rings 1374 * @dev: net device structure 1375 * @flags: gfp flag. 1376 * Description: this function initializes the DMA RX descriptors 1377 * and allocates the socket buffers. It supports the chained and ring 1378 * modes. 1379 */ 1380 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1381 { 1382 struct stmmac_priv *priv = netdev_priv(dev); 1383 u32 rx_count = priv->plat->rx_queues_to_use; 1384 int ret = -ENOMEM; 1385 int queue; 1386 int i; 1387 1388 /* RX INITIALIZATION */ 1389 netif_dbg(priv, probe, priv->dev, 1390 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1391 1392 for (queue = 0; queue < rx_count; queue++) { 1393 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1394 1395 netif_dbg(priv, probe, priv->dev, 1396 "(%s) dma_rx_phy=0x%08x\n", __func__, 1397 (u32)rx_q->dma_rx_phy); 1398 1399 stmmac_clear_rx_descriptors(priv, queue); 1400 1401 for (i = 0; i < DMA_RX_SIZE; i++) { 1402 struct dma_desc *p; 1403 1404 if (priv->extend_desc) 1405 p = &((rx_q->dma_erx + i)->basic); 1406 else 1407 p = rx_q->dma_rx + i; 1408 1409 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1410 queue); 1411 if (ret) 1412 goto err_init_rx_buffers; 1413 } 1414 1415 rx_q->cur_rx = 0; 1416 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1417 1418 /* Setup the chained descriptor addresses */ 1419 if (priv->mode == STMMAC_CHAIN_MODE) { 1420 if (priv->extend_desc) 1421 stmmac_mode_init(priv, rx_q->dma_erx, 1422 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1423 else 1424 stmmac_mode_init(priv, rx_q->dma_rx, 1425 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1426 } 1427 } 1428 1429 return 0; 1430 1431 err_init_rx_buffers: 1432 while (queue >= 0) { 1433 while (--i >= 0) 1434 stmmac_free_rx_buffer(priv, queue, i); 1435 1436 if (queue == 0) 1437 break; 1438 1439 i = DMA_RX_SIZE; 1440 queue--; 1441 } 1442 1443 return ret; 1444 } 1445 1446 /** 1447 * init_dma_tx_desc_rings - init the TX descriptor rings 1448 * @dev: net device structure. 1449 * Description: this function initializes the DMA TX descriptors 1450 * and allocates the socket buffers. It supports the chained and ring 1451 * modes. 1452 */ 1453 static int init_dma_tx_desc_rings(struct net_device *dev) 1454 { 1455 struct stmmac_priv *priv = netdev_priv(dev); 1456 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1457 u32 queue; 1458 int i; 1459 1460 for (queue = 0; queue < tx_queue_cnt; queue++) { 1461 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1462 1463 netif_dbg(priv, probe, priv->dev, 1464 "(%s) dma_tx_phy=0x%08x\n", __func__, 1465 (u32)tx_q->dma_tx_phy); 1466 1467 /* Setup the chained descriptor addresses */ 1468 if (priv->mode == STMMAC_CHAIN_MODE) { 1469 if (priv->extend_desc) 1470 stmmac_mode_init(priv, tx_q->dma_etx, 1471 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1472 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1473 stmmac_mode_init(priv, tx_q->dma_tx, 1474 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1475 } 1476 1477 for (i = 0; i < DMA_TX_SIZE; i++) { 1478 struct dma_desc *p; 1479 if (priv->extend_desc) 1480 p = &((tx_q->dma_etx + i)->basic); 1481 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1482 p = &((tx_q->dma_entx + i)->basic); 1483 else 1484 p = tx_q->dma_tx + i; 1485 1486 stmmac_clear_desc(priv, p); 1487 1488 tx_q->tx_skbuff_dma[i].buf = 0; 1489 tx_q->tx_skbuff_dma[i].map_as_page = false; 1490 tx_q->tx_skbuff_dma[i].len = 0; 1491 tx_q->tx_skbuff_dma[i].last_segment = false; 1492 tx_q->tx_skbuff[i] = NULL; 1493 } 1494 1495 tx_q->dirty_tx = 0; 1496 tx_q->cur_tx = 0; 1497 tx_q->mss = 0; 1498 1499 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1500 } 1501 1502 return 0; 1503 } 1504 1505 /** 1506 * init_dma_desc_rings - init the RX/TX descriptor rings 1507 * @dev: net device structure 1508 * @flags: gfp flag. 1509 * Description: this function initializes the DMA RX/TX descriptors 1510 * and allocates the socket buffers. It supports the chained and ring 1511 * modes. 1512 */ 1513 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1514 { 1515 struct stmmac_priv *priv = netdev_priv(dev); 1516 int ret; 1517 1518 ret = init_dma_rx_desc_rings(dev, flags); 1519 if (ret) 1520 return ret; 1521 1522 ret = init_dma_tx_desc_rings(dev); 1523 1524 stmmac_clear_descriptors(priv); 1525 1526 if (netif_msg_hw(priv)) 1527 stmmac_display_rings(priv); 1528 1529 return ret; 1530 } 1531 1532 /** 1533 * dma_free_rx_skbufs - free RX dma buffers 1534 * @priv: private structure 1535 * @queue: RX queue index 1536 */ 1537 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1538 { 1539 int i; 1540 1541 for (i = 0; i < DMA_RX_SIZE; i++) 1542 stmmac_free_rx_buffer(priv, queue, i); 1543 } 1544 1545 /** 1546 * dma_free_tx_skbufs - free TX dma buffers 1547 * @priv: private structure 1548 * @queue: TX queue index 1549 */ 1550 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1551 { 1552 int i; 1553 1554 for (i = 0; i < DMA_TX_SIZE; i++) 1555 stmmac_free_tx_buffer(priv, queue, i); 1556 } 1557 1558 /** 1559 * free_dma_rx_desc_resources - free RX dma desc resources 1560 * @priv: private structure 1561 */ 1562 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1563 { 1564 u32 rx_count = priv->plat->rx_queues_to_use; 1565 u32 queue; 1566 1567 /* Free RX queue resources */ 1568 for (queue = 0; queue < rx_count; queue++) { 1569 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1570 1571 /* Release the DMA RX socket buffers */ 1572 dma_free_rx_skbufs(priv, queue); 1573 1574 /* Free DMA regions of consistent memory previously allocated */ 1575 if (!priv->extend_desc) 1576 dma_free_coherent(priv->device, 1577 DMA_RX_SIZE * sizeof(struct dma_desc), 1578 rx_q->dma_rx, rx_q->dma_rx_phy); 1579 else 1580 dma_free_coherent(priv->device, DMA_RX_SIZE * 1581 sizeof(struct dma_extended_desc), 1582 rx_q->dma_erx, rx_q->dma_rx_phy); 1583 1584 kfree(rx_q->buf_pool); 1585 if (rx_q->page_pool) 1586 page_pool_destroy(rx_q->page_pool); 1587 } 1588 } 1589 1590 /** 1591 * free_dma_tx_desc_resources - free TX dma desc resources 1592 * @priv: private structure 1593 */ 1594 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1595 { 1596 u32 tx_count = priv->plat->tx_queues_to_use; 1597 u32 queue; 1598 1599 /* Free TX queue resources */ 1600 for (queue = 0; queue < tx_count; queue++) { 1601 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1602 size_t size; 1603 void *addr; 1604 1605 /* Release the DMA TX socket buffers */ 1606 dma_free_tx_skbufs(priv, queue); 1607 1608 if (priv->extend_desc) { 1609 size = sizeof(struct dma_extended_desc); 1610 addr = tx_q->dma_etx; 1611 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1612 size = sizeof(struct dma_edesc); 1613 addr = tx_q->dma_entx; 1614 } else { 1615 size = sizeof(struct dma_desc); 1616 addr = tx_q->dma_tx; 1617 } 1618 1619 size *= DMA_TX_SIZE; 1620 1621 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1622 1623 kfree(tx_q->tx_skbuff_dma); 1624 kfree(tx_q->tx_skbuff); 1625 } 1626 } 1627 1628 /** 1629 * alloc_dma_rx_desc_resources - alloc RX resources. 1630 * @priv: private structure 1631 * Description: according to which descriptor can be used (extend or basic) 1632 * this function allocates the resources for TX and RX paths. In case of 1633 * reception, for example, it pre-allocated the RX socket buffer in order to 1634 * allow zero-copy mechanism. 1635 */ 1636 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1637 { 1638 u32 rx_count = priv->plat->rx_queues_to_use; 1639 int ret = -ENOMEM; 1640 u32 queue; 1641 1642 /* RX queues buffers and DMA */ 1643 for (queue = 0; queue < rx_count; queue++) { 1644 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1645 struct page_pool_params pp_params = { 0 }; 1646 unsigned int num_pages; 1647 1648 rx_q->queue_index = queue; 1649 rx_q->priv_data = priv; 1650 1651 pp_params.flags = PP_FLAG_DMA_MAP; 1652 pp_params.pool_size = DMA_RX_SIZE; 1653 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1654 pp_params.order = ilog2(num_pages); 1655 pp_params.nid = dev_to_node(priv->device); 1656 pp_params.dev = priv->device; 1657 pp_params.dma_dir = DMA_FROM_DEVICE; 1658 1659 rx_q->page_pool = page_pool_create(&pp_params); 1660 if (IS_ERR(rx_q->page_pool)) { 1661 ret = PTR_ERR(rx_q->page_pool); 1662 rx_q->page_pool = NULL; 1663 goto err_dma; 1664 } 1665 1666 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1667 GFP_KERNEL); 1668 if (!rx_q->buf_pool) 1669 goto err_dma; 1670 1671 if (priv->extend_desc) { 1672 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1673 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1674 &rx_q->dma_rx_phy, 1675 GFP_KERNEL); 1676 if (!rx_q->dma_erx) 1677 goto err_dma; 1678 1679 } else { 1680 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1681 DMA_RX_SIZE * sizeof(struct dma_desc), 1682 &rx_q->dma_rx_phy, 1683 GFP_KERNEL); 1684 if (!rx_q->dma_rx) 1685 goto err_dma; 1686 } 1687 } 1688 1689 return 0; 1690 1691 err_dma: 1692 free_dma_rx_desc_resources(priv); 1693 1694 return ret; 1695 } 1696 1697 /** 1698 * alloc_dma_tx_desc_resources - alloc TX resources. 1699 * @priv: private structure 1700 * Description: according to which descriptor can be used (extend or basic) 1701 * this function allocates the resources for TX and RX paths. In case of 1702 * reception, for example, it pre-allocated the RX socket buffer in order to 1703 * allow zero-copy mechanism. 1704 */ 1705 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1706 { 1707 u32 tx_count = priv->plat->tx_queues_to_use; 1708 int ret = -ENOMEM; 1709 u32 queue; 1710 1711 /* TX queues buffers and DMA */ 1712 for (queue = 0; queue < tx_count; queue++) { 1713 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1714 size_t size; 1715 void *addr; 1716 1717 tx_q->queue_index = queue; 1718 tx_q->priv_data = priv; 1719 1720 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1721 sizeof(*tx_q->tx_skbuff_dma), 1722 GFP_KERNEL); 1723 if (!tx_q->tx_skbuff_dma) 1724 goto err_dma; 1725 1726 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1727 sizeof(struct sk_buff *), 1728 GFP_KERNEL); 1729 if (!tx_q->tx_skbuff) 1730 goto err_dma; 1731 1732 if (priv->extend_desc) 1733 size = sizeof(struct dma_extended_desc); 1734 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1735 size = sizeof(struct dma_edesc); 1736 else 1737 size = sizeof(struct dma_desc); 1738 1739 size *= DMA_TX_SIZE; 1740 1741 addr = dma_alloc_coherent(priv->device, size, 1742 &tx_q->dma_tx_phy, GFP_KERNEL); 1743 if (!addr) 1744 goto err_dma; 1745 1746 if (priv->extend_desc) 1747 tx_q->dma_etx = addr; 1748 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1749 tx_q->dma_entx = addr; 1750 else 1751 tx_q->dma_tx = addr; 1752 } 1753 1754 return 0; 1755 1756 err_dma: 1757 free_dma_tx_desc_resources(priv); 1758 return ret; 1759 } 1760 1761 /** 1762 * alloc_dma_desc_resources - alloc TX/RX resources. 1763 * @priv: private structure 1764 * Description: according to which descriptor can be used (extend or basic) 1765 * this function allocates the resources for TX and RX paths. In case of 1766 * reception, for example, it pre-allocated the RX socket buffer in order to 1767 * allow zero-copy mechanism. 1768 */ 1769 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1770 { 1771 /* RX Allocation */ 1772 int ret = alloc_dma_rx_desc_resources(priv); 1773 1774 if (ret) 1775 return ret; 1776 1777 ret = alloc_dma_tx_desc_resources(priv); 1778 1779 return ret; 1780 } 1781 1782 /** 1783 * free_dma_desc_resources - free dma desc resources 1784 * @priv: private structure 1785 */ 1786 static void free_dma_desc_resources(struct stmmac_priv *priv) 1787 { 1788 /* Release the DMA RX socket buffers */ 1789 free_dma_rx_desc_resources(priv); 1790 1791 /* Release the DMA TX socket buffers */ 1792 free_dma_tx_desc_resources(priv); 1793 } 1794 1795 /** 1796 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1797 * @priv: driver private structure 1798 * Description: It is used for enabling the rx queues in the MAC 1799 */ 1800 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1801 { 1802 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1803 int queue; 1804 u8 mode; 1805 1806 for (queue = 0; queue < rx_queues_count; queue++) { 1807 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1808 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1809 } 1810 } 1811 1812 /** 1813 * stmmac_start_rx_dma - start RX DMA channel 1814 * @priv: driver private structure 1815 * @chan: RX channel index 1816 * Description: 1817 * This starts a RX DMA channel 1818 */ 1819 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1820 { 1821 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1822 stmmac_start_rx(priv, priv->ioaddr, chan); 1823 } 1824 1825 /** 1826 * stmmac_start_tx_dma - start TX DMA channel 1827 * @priv: driver private structure 1828 * @chan: TX channel index 1829 * Description: 1830 * This starts a TX DMA channel 1831 */ 1832 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1833 { 1834 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1835 stmmac_start_tx(priv, priv->ioaddr, chan); 1836 } 1837 1838 /** 1839 * stmmac_stop_rx_dma - stop RX DMA channel 1840 * @priv: driver private structure 1841 * @chan: RX channel index 1842 * Description: 1843 * This stops a RX DMA channel 1844 */ 1845 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1846 { 1847 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1848 stmmac_stop_rx(priv, priv->ioaddr, chan); 1849 } 1850 1851 /** 1852 * stmmac_stop_tx_dma - stop TX DMA channel 1853 * @priv: driver private structure 1854 * @chan: TX channel index 1855 * Description: 1856 * This stops a TX DMA channel 1857 */ 1858 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1859 { 1860 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1861 stmmac_stop_tx(priv, priv->ioaddr, chan); 1862 } 1863 1864 /** 1865 * stmmac_start_all_dma - start all RX and TX DMA channels 1866 * @priv: driver private structure 1867 * Description: 1868 * This starts all the RX and TX DMA channels 1869 */ 1870 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1871 { 1872 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1873 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1874 u32 chan = 0; 1875 1876 for (chan = 0; chan < rx_channels_count; chan++) 1877 stmmac_start_rx_dma(priv, chan); 1878 1879 for (chan = 0; chan < tx_channels_count; chan++) 1880 stmmac_start_tx_dma(priv, chan); 1881 } 1882 1883 /** 1884 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1885 * @priv: driver private structure 1886 * Description: 1887 * This stops the RX and TX DMA channels 1888 */ 1889 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1890 { 1891 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1892 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1893 u32 chan = 0; 1894 1895 for (chan = 0; chan < rx_channels_count; chan++) 1896 stmmac_stop_rx_dma(priv, chan); 1897 1898 for (chan = 0; chan < tx_channels_count; chan++) 1899 stmmac_stop_tx_dma(priv, chan); 1900 } 1901 1902 /** 1903 * stmmac_dma_operation_mode - HW DMA operation mode 1904 * @priv: driver private structure 1905 * Description: it is used for configuring the DMA operation mode register in 1906 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1907 */ 1908 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1909 { 1910 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1911 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1912 int rxfifosz = priv->plat->rx_fifo_size; 1913 int txfifosz = priv->plat->tx_fifo_size; 1914 u32 txmode = 0; 1915 u32 rxmode = 0; 1916 u32 chan = 0; 1917 u8 qmode = 0; 1918 1919 if (rxfifosz == 0) 1920 rxfifosz = priv->dma_cap.rx_fifo_size; 1921 if (txfifosz == 0) 1922 txfifosz = priv->dma_cap.tx_fifo_size; 1923 1924 /* Adjust for real per queue fifo size */ 1925 rxfifosz /= rx_channels_count; 1926 txfifosz /= tx_channels_count; 1927 1928 if (priv->plat->force_thresh_dma_mode) { 1929 txmode = tc; 1930 rxmode = tc; 1931 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1932 /* 1933 * In case of GMAC, SF mode can be enabled 1934 * to perform the TX COE in HW. This depends on: 1935 * 1) TX COE if actually supported 1936 * 2) There is no bugged Jumbo frame support 1937 * that needs to not insert csum in the TDES. 1938 */ 1939 txmode = SF_DMA_MODE; 1940 rxmode = SF_DMA_MODE; 1941 priv->xstats.threshold = SF_DMA_MODE; 1942 } else { 1943 txmode = tc; 1944 rxmode = SF_DMA_MODE; 1945 } 1946 1947 /* configure all channels */ 1948 for (chan = 0; chan < rx_channels_count; chan++) { 1949 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1950 1951 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1952 rxfifosz, qmode); 1953 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1954 chan); 1955 } 1956 1957 for (chan = 0; chan < tx_channels_count; chan++) { 1958 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1959 1960 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1961 txfifosz, qmode); 1962 } 1963 } 1964 1965 /** 1966 * stmmac_tx_clean - to manage the transmission completion 1967 * @priv: driver private structure 1968 * @queue: TX queue index 1969 * Description: it reclaims the transmit resources after transmission completes. 1970 */ 1971 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1972 { 1973 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1974 unsigned int bytes_compl = 0, pkts_compl = 0; 1975 unsigned int entry, count = 0; 1976 1977 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1978 1979 priv->xstats.tx_clean++; 1980 1981 entry = tx_q->dirty_tx; 1982 while ((entry != tx_q->cur_tx) && (count < budget)) { 1983 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1984 struct dma_desc *p; 1985 int status; 1986 1987 if (priv->extend_desc) 1988 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1989 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1990 p = &tx_q->dma_entx[entry].basic; 1991 else 1992 p = tx_q->dma_tx + entry; 1993 1994 status = stmmac_tx_status(priv, &priv->dev->stats, 1995 &priv->xstats, p, priv->ioaddr); 1996 /* Check if the descriptor is owned by the DMA */ 1997 if (unlikely(status & tx_dma_own)) 1998 break; 1999 2000 count++; 2001 2002 /* Make sure descriptor fields are read after reading 2003 * the own bit. 2004 */ 2005 dma_rmb(); 2006 2007 /* Just consider the last segment and ...*/ 2008 if (likely(!(status & tx_not_ls))) { 2009 /* ... verify the status error condition */ 2010 if (unlikely(status & tx_err)) { 2011 priv->dev->stats.tx_errors++; 2012 } else { 2013 priv->dev->stats.tx_packets++; 2014 priv->xstats.tx_pkt_n++; 2015 } 2016 stmmac_get_tx_hwtstamp(priv, p, skb); 2017 } 2018 2019 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2020 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2021 dma_unmap_page(priv->device, 2022 tx_q->tx_skbuff_dma[entry].buf, 2023 tx_q->tx_skbuff_dma[entry].len, 2024 DMA_TO_DEVICE); 2025 else 2026 dma_unmap_single(priv->device, 2027 tx_q->tx_skbuff_dma[entry].buf, 2028 tx_q->tx_skbuff_dma[entry].len, 2029 DMA_TO_DEVICE); 2030 tx_q->tx_skbuff_dma[entry].buf = 0; 2031 tx_q->tx_skbuff_dma[entry].len = 0; 2032 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2033 } 2034 2035 stmmac_clean_desc3(priv, tx_q, p); 2036 2037 tx_q->tx_skbuff_dma[entry].last_segment = false; 2038 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2039 2040 if (likely(skb != NULL)) { 2041 pkts_compl++; 2042 bytes_compl += skb->len; 2043 dev_consume_skb_any(skb); 2044 tx_q->tx_skbuff[entry] = NULL; 2045 } 2046 2047 stmmac_release_tx_desc(priv, p, priv->mode); 2048 2049 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2050 } 2051 tx_q->dirty_tx = entry; 2052 2053 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2054 pkts_compl, bytes_compl); 2055 2056 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2057 queue))) && 2058 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 2059 2060 netif_dbg(priv, tx_done, priv->dev, 2061 "%s: restart transmit\n", __func__); 2062 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2063 } 2064 2065 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 2066 stmmac_enable_eee_mode(priv); 2067 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2068 } 2069 2070 /* We still have pending packets, let's call for a new scheduling */ 2071 if (tx_q->dirty_tx != tx_q->cur_tx) 2072 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2073 2074 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2075 2076 return count; 2077 } 2078 2079 /** 2080 * stmmac_tx_err - to manage the tx error 2081 * @priv: driver private structure 2082 * @chan: channel index 2083 * Description: it cleans the descriptors and restarts the transmission 2084 * in case of transmission errors. 2085 */ 2086 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2087 { 2088 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2089 2090 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2091 2092 stmmac_stop_tx_dma(priv, chan); 2093 dma_free_tx_skbufs(priv, chan); 2094 stmmac_clear_tx_descriptors(priv, chan); 2095 tx_q->dirty_tx = 0; 2096 tx_q->cur_tx = 0; 2097 tx_q->mss = 0; 2098 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2099 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2100 tx_q->dma_tx_phy, chan); 2101 stmmac_start_tx_dma(priv, chan); 2102 2103 priv->dev->stats.tx_errors++; 2104 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2105 } 2106 2107 /** 2108 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2109 * @priv: driver private structure 2110 * @txmode: TX operating mode 2111 * @rxmode: RX operating mode 2112 * @chan: channel index 2113 * Description: it is used for configuring of the DMA operation mode in 2114 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2115 * mode. 2116 */ 2117 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2118 u32 rxmode, u32 chan) 2119 { 2120 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2121 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2122 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2123 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2124 int rxfifosz = priv->plat->rx_fifo_size; 2125 int txfifosz = priv->plat->tx_fifo_size; 2126 2127 if (rxfifosz == 0) 2128 rxfifosz = priv->dma_cap.rx_fifo_size; 2129 if (txfifosz == 0) 2130 txfifosz = priv->dma_cap.tx_fifo_size; 2131 2132 /* Adjust for real per queue fifo size */ 2133 rxfifosz /= rx_channels_count; 2134 txfifosz /= tx_channels_count; 2135 2136 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2137 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2138 } 2139 2140 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2141 { 2142 int ret; 2143 2144 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2145 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2146 if (ret && (ret != -EINVAL)) { 2147 stmmac_global_err(priv); 2148 return true; 2149 } 2150 2151 return false; 2152 } 2153 2154 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2155 { 2156 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2157 &priv->xstats, chan); 2158 struct stmmac_channel *ch = &priv->channel[chan]; 2159 unsigned long flags; 2160 2161 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2162 if (napi_schedule_prep(&ch->rx_napi)) { 2163 spin_lock_irqsave(&ch->lock, flags); 2164 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2165 spin_unlock_irqrestore(&ch->lock, flags); 2166 __napi_schedule_irqoff(&ch->rx_napi); 2167 } 2168 } 2169 2170 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2171 if (napi_schedule_prep(&ch->tx_napi)) { 2172 spin_lock_irqsave(&ch->lock, flags); 2173 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2174 spin_unlock_irqrestore(&ch->lock, flags); 2175 __napi_schedule_irqoff(&ch->tx_napi); 2176 } 2177 } 2178 2179 return status; 2180 } 2181 2182 /** 2183 * stmmac_dma_interrupt - DMA ISR 2184 * @priv: driver private structure 2185 * Description: this is the DMA ISR. It is called by the main ISR. 2186 * It calls the dwmac dma routine and schedule poll method in case of some 2187 * work can be done. 2188 */ 2189 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2190 { 2191 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2192 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2193 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2194 tx_channel_count : rx_channel_count; 2195 u32 chan; 2196 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2197 2198 /* Make sure we never check beyond our status buffer. */ 2199 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2200 channels_to_check = ARRAY_SIZE(status); 2201 2202 for (chan = 0; chan < channels_to_check; chan++) 2203 status[chan] = stmmac_napi_check(priv, chan); 2204 2205 for (chan = 0; chan < tx_channel_count; chan++) { 2206 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2207 /* Try to bump up the dma threshold on this failure */ 2208 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2209 (tc <= 256)) { 2210 tc += 64; 2211 if (priv->plat->force_thresh_dma_mode) 2212 stmmac_set_dma_operation_mode(priv, 2213 tc, 2214 tc, 2215 chan); 2216 else 2217 stmmac_set_dma_operation_mode(priv, 2218 tc, 2219 SF_DMA_MODE, 2220 chan); 2221 priv->xstats.threshold = tc; 2222 } 2223 } else if (unlikely(status[chan] == tx_hard_error)) { 2224 stmmac_tx_err(priv, chan); 2225 } 2226 } 2227 } 2228 2229 /** 2230 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2231 * @priv: driver private structure 2232 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2233 */ 2234 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2235 { 2236 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2237 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2238 2239 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2240 2241 if (priv->dma_cap.rmon) { 2242 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2243 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2244 } else 2245 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2246 } 2247 2248 /** 2249 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2250 * @priv: driver private structure 2251 * Description: 2252 * new GMAC chip generations have a new register to indicate the 2253 * presence of the optional feature/functions. 2254 * This can be also used to override the value passed through the 2255 * platform and necessary for old MAC10/100 and GMAC chips. 2256 */ 2257 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2258 { 2259 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2260 } 2261 2262 /** 2263 * stmmac_check_ether_addr - check if the MAC addr is valid 2264 * @priv: driver private structure 2265 * Description: 2266 * it is to verify if the MAC address is valid, in case of failures it 2267 * generates a random MAC address 2268 */ 2269 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2270 { 2271 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2272 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2273 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2274 eth_hw_addr_random(priv->dev); 2275 dev_info(priv->device, "device MAC address %pM\n", 2276 priv->dev->dev_addr); 2277 } 2278 } 2279 2280 /** 2281 * stmmac_init_dma_engine - DMA init. 2282 * @priv: driver private structure 2283 * Description: 2284 * It inits the DMA invoking the specific MAC/GMAC callback. 2285 * Some DMA parameters can be passed from the platform; 2286 * in case of these are not passed a default is kept for the MAC or GMAC. 2287 */ 2288 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2289 { 2290 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2291 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2292 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2293 struct stmmac_rx_queue *rx_q; 2294 struct stmmac_tx_queue *tx_q; 2295 u32 chan = 0; 2296 int atds = 0; 2297 int ret = 0; 2298 2299 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2300 dev_err(priv->device, "Invalid DMA configuration\n"); 2301 return -EINVAL; 2302 } 2303 2304 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2305 atds = 1; 2306 2307 ret = stmmac_reset(priv, priv->ioaddr); 2308 if (ret) { 2309 dev_err(priv->device, "Failed to reset the dma\n"); 2310 return ret; 2311 } 2312 2313 /* DMA Configuration */ 2314 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2315 2316 if (priv->plat->axi) 2317 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2318 2319 /* DMA CSR Channel configuration */ 2320 for (chan = 0; chan < dma_csr_ch; chan++) 2321 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2322 2323 /* DMA RX Channel Configuration */ 2324 for (chan = 0; chan < rx_channels_count; chan++) { 2325 rx_q = &priv->rx_queue[chan]; 2326 2327 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2328 rx_q->dma_rx_phy, chan); 2329 2330 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2331 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2332 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2333 rx_q->rx_tail_addr, chan); 2334 } 2335 2336 /* DMA TX Channel Configuration */ 2337 for (chan = 0; chan < tx_channels_count; chan++) { 2338 tx_q = &priv->tx_queue[chan]; 2339 2340 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2341 tx_q->dma_tx_phy, chan); 2342 2343 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2344 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2345 tx_q->tx_tail_addr, chan); 2346 } 2347 2348 return ret; 2349 } 2350 2351 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2352 { 2353 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2354 2355 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2356 } 2357 2358 /** 2359 * stmmac_tx_timer - mitigation sw timer for tx. 2360 * @data: data pointer 2361 * Description: 2362 * This is the timer handler to directly invoke the stmmac_tx_clean. 2363 */ 2364 static void stmmac_tx_timer(struct timer_list *t) 2365 { 2366 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2367 struct stmmac_priv *priv = tx_q->priv_data; 2368 struct stmmac_channel *ch; 2369 2370 ch = &priv->channel[tx_q->queue_index]; 2371 2372 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2373 unsigned long flags; 2374 2375 spin_lock_irqsave(&ch->lock, flags); 2376 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2377 spin_unlock_irqrestore(&ch->lock, flags); 2378 __napi_schedule(&ch->tx_napi); 2379 } 2380 } 2381 2382 /** 2383 * stmmac_init_coalesce - init mitigation options. 2384 * @priv: driver private structure 2385 * Description: 2386 * This inits the coalesce parameters: i.e. timer rate, 2387 * timer handler and default threshold used for enabling the 2388 * interrupt on completion bit. 2389 */ 2390 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2391 { 2392 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2393 u32 chan; 2394 2395 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2396 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2397 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2398 2399 for (chan = 0; chan < tx_channel_count; chan++) { 2400 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2401 2402 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2403 } 2404 } 2405 2406 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2407 { 2408 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2409 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2410 u32 chan; 2411 2412 /* set TX ring length */ 2413 for (chan = 0; chan < tx_channels_count; chan++) 2414 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2415 (DMA_TX_SIZE - 1), chan); 2416 2417 /* set RX ring length */ 2418 for (chan = 0; chan < rx_channels_count; chan++) 2419 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2420 (DMA_RX_SIZE - 1), chan); 2421 } 2422 2423 /** 2424 * stmmac_set_tx_queue_weight - Set TX queue weight 2425 * @priv: driver private structure 2426 * Description: It is used for setting TX queues weight 2427 */ 2428 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2429 { 2430 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2431 u32 weight; 2432 u32 queue; 2433 2434 for (queue = 0; queue < tx_queues_count; queue++) { 2435 weight = priv->plat->tx_queues_cfg[queue].weight; 2436 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2437 } 2438 } 2439 2440 /** 2441 * stmmac_configure_cbs - Configure CBS in TX queue 2442 * @priv: driver private structure 2443 * Description: It is used for configuring CBS in AVB TX queues 2444 */ 2445 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2446 { 2447 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2448 u32 mode_to_use; 2449 u32 queue; 2450 2451 /* queue 0 is reserved for legacy traffic */ 2452 for (queue = 1; queue < tx_queues_count; queue++) { 2453 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2454 if (mode_to_use == MTL_QUEUE_DCB) 2455 continue; 2456 2457 stmmac_config_cbs(priv, priv->hw, 2458 priv->plat->tx_queues_cfg[queue].send_slope, 2459 priv->plat->tx_queues_cfg[queue].idle_slope, 2460 priv->plat->tx_queues_cfg[queue].high_credit, 2461 priv->plat->tx_queues_cfg[queue].low_credit, 2462 queue); 2463 } 2464 } 2465 2466 /** 2467 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2468 * @priv: driver private structure 2469 * Description: It is used for mapping RX queues to RX dma channels 2470 */ 2471 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2472 { 2473 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2474 u32 queue; 2475 u32 chan; 2476 2477 for (queue = 0; queue < rx_queues_count; queue++) { 2478 chan = priv->plat->rx_queues_cfg[queue].chan; 2479 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2480 } 2481 } 2482 2483 /** 2484 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2485 * @priv: driver private structure 2486 * Description: It is used for configuring the RX Queue Priority 2487 */ 2488 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2489 { 2490 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2491 u32 queue; 2492 u32 prio; 2493 2494 for (queue = 0; queue < rx_queues_count; queue++) { 2495 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2496 continue; 2497 2498 prio = priv->plat->rx_queues_cfg[queue].prio; 2499 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2500 } 2501 } 2502 2503 /** 2504 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2505 * @priv: driver private structure 2506 * Description: It is used for configuring the TX Queue Priority 2507 */ 2508 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2509 { 2510 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2511 u32 queue; 2512 u32 prio; 2513 2514 for (queue = 0; queue < tx_queues_count; queue++) { 2515 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2516 continue; 2517 2518 prio = priv->plat->tx_queues_cfg[queue].prio; 2519 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2520 } 2521 } 2522 2523 /** 2524 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2525 * @priv: driver private structure 2526 * Description: It is used for configuring the RX queue routing 2527 */ 2528 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2529 { 2530 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2531 u32 queue; 2532 u8 packet; 2533 2534 for (queue = 0; queue < rx_queues_count; queue++) { 2535 /* no specific packet type routing specified for the queue */ 2536 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2537 continue; 2538 2539 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2540 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2541 } 2542 } 2543 2544 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2545 { 2546 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2547 priv->rss.enable = false; 2548 return; 2549 } 2550 2551 if (priv->dev->features & NETIF_F_RXHASH) 2552 priv->rss.enable = true; 2553 else 2554 priv->rss.enable = false; 2555 2556 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2557 priv->plat->rx_queues_to_use); 2558 } 2559 2560 /** 2561 * stmmac_mtl_configuration - Configure MTL 2562 * @priv: driver private structure 2563 * Description: It is used for configurring MTL 2564 */ 2565 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2566 { 2567 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2568 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2569 2570 if (tx_queues_count > 1) 2571 stmmac_set_tx_queue_weight(priv); 2572 2573 /* Configure MTL RX algorithms */ 2574 if (rx_queues_count > 1) 2575 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2576 priv->plat->rx_sched_algorithm); 2577 2578 /* Configure MTL TX algorithms */ 2579 if (tx_queues_count > 1) 2580 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2581 priv->plat->tx_sched_algorithm); 2582 2583 /* Configure CBS in AVB TX queues */ 2584 if (tx_queues_count > 1) 2585 stmmac_configure_cbs(priv); 2586 2587 /* Map RX MTL to DMA channels */ 2588 stmmac_rx_queue_dma_chan_map(priv); 2589 2590 /* Enable MAC RX Queues */ 2591 stmmac_mac_enable_rx_queues(priv); 2592 2593 /* Set RX priorities */ 2594 if (rx_queues_count > 1) 2595 stmmac_mac_config_rx_queues_prio(priv); 2596 2597 /* Set TX priorities */ 2598 if (tx_queues_count > 1) 2599 stmmac_mac_config_tx_queues_prio(priv); 2600 2601 /* Set RX routing */ 2602 if (rx_queues_count > 1) 2603 stmmac_mac_config_rx_queues_routing(priv); 2604 2605 /* Receive Side Scaling */ 2606 if (rx_queues_count > 1) 2607 stmmac_mac_config_rss(priv); 2608 } 2609 2610 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2611 { 2612 if (priv->dma_cap.asp) { 2613 netdev_info(priv->dev, "Enabling Safety Features\n"); 2614 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2615 } else { 2616 netdev_info(priv->dev, "No Safety Features support found\n"); 2617 } 2618 } 2619 2620 /** 2621 * stmmac_hw_setup - setup mac in a usable state. 2622 * @dev : pointer to the device structure. 2623 * Description: 2624 * this is the main function to setup the HW in a usable state because the 2625 * dma engine is reset, the core registers are configured (e.g. AXI, 2626 * Checksum features, timers). The DMA is ready to start receiving and 2627 * transmitting. 2628 * Return value: 2629 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2630 * file on failure. 2631 */ 2632 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2633 { 2634 struct stmmac_priv *priv = netdev_priv(dev); 2635 u32 rx_cnt = priv->plat->rx_queues_to_use; 2636 u32 tx_cnt = priv->plat->tx_queues_to_use; 2637 u32 chan; 2638 int ret; 2639 2640 /* DMA initialization and SW reset */ 2641 ret = stmmac_init_dma_engine(priv); 2642 if (ret < 0) { 2643 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2644 __func__); 2645 return ret; 2646 } 2647 2648 /* Copy the MAC addr into the HW */ 2649 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2650 2651 /* PS and related bits will be programmed according to the speed */ 2652 if (priv->hw->pcs) { 2653 int speed = priv->plat->mac_port_sel_speed; 2654 2655 if ((speed == SPEED_10) || (speed == SPEED_100) || 2656 (speed == SPEED_1000)) { 2657 priv->hw->ps = speed; 2658 } else { 2659 dev_warn(priv->device, "invalid port speed\n"); 2660 priv->hw->ps = 0; 2661 } 2662 } 2663 2664 /* Initialize the MAC Core */ 2665 stmmac_core_init(priv, priv->hw, dev); 2666 2667 /* Initialize MTL*/ 2668 stmmac_mtl_configuration(priv); 2669 2670 /* Initialize Safety Features */ 2671 stmmac_safety_feat_configuration(priv); 2672 2673 ret = stmmac_rx_ipc(priv, priv->hw); 2674 if (!ret) { 2675 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2676 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2677 priv->hw->rx_csum = 0; 2678 } 2679 2680 /* Enable the MAC Rx/Tx */ 2681 stmmac_mac_set(priv, priv->ioaddr, true); 2682 2683 /* Set the HW DMA mode and the COE */ 2684 stmmac_dma_operation_mode(priv); 2685 2686 stmmac_mmc_setup(priv); 2687 2688 if (init_ptp) { 2689 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2690 if (ret < 0) 2691 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2692 2693 ret = stmmac_init_ptp(priv); 2694 if (ret == -EOPNOTSUPP) 2695 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2696 else if (ret) 2697 netdev_warn(priv->dev, "PTP init failed\n"); 2698 } 2699 2700 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 2701 2702 /* Convert the timer from msec to usec */ 2703 if (!priv->tx_lpi_timer) 2704 priv->tx_lpi_timer = eee_timer * 1000; 2705 2706 if (priv->use_riwt) { 2707 if (!priv->rx_riwt) 2708 priv->rx_riwt = DEF_DMA_RIWT; 2709 2710 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2711 } 2712 2713 if (priv->hw->pcs) 2714 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2715 2716 /* set TX and RX rings length */ 2717 stmmac_set_rings_length(priv); 2718 2719 /* Enable TSO */ 2720 if (priv->tso) { 2721 for (chan = 0; chan < tx_cnt; chan++) 2722 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2723 } 2724 2725 /* Enable Split Header */ 2726 if (priv->sph && priv->hw->rx_csum) { 2727 for (chan = 0; chan < rx_cnt; chan++) 2728 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2729 } 2730 2731 /* VLAN Tag Insertion */ 2732 if (priv->dma_cap.vlins) 2733 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2734 2735 /* TBS */ 2736 for (chan = 0; chan < tx_cnt; chan++) { 2737 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2738 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2739 2740 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2741 } 2742 2743 /* Start the ball rolling... */ 2744 stmmac_start_all_dma(priv); 2745 2746 return 0; 2747 } 2748 2749 static void stmmac_hw_teardown(struct net_device *dev) 2750 { 2751 struct stmmac_priv *priv = netdev_priv(dev); 2752 2753 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2754 } 2755 2756 /** 2757 * stmmac_open - open entry point of the driver 2758 * @dev : pointer to the device structure. 2759 * Description: 2760 * This function is the open entry point of the driver. 2761 * Return value: 2762 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2763 * file on failure. 2764 */ 2765 static int stmmac_open(struct net_device *dev) 2766 { 2767 struct stmmac_priv *priv = netdev_priv(dev); 2768 int bfsize = 0; 2769 u32 chan; 2770 int ret; 2771 2772 if (priv->hw->pcs != STMMAC_PCS_TBI && 2773 priv->hw->pcs != STMMAC_PCS_RTBI && 2774 priv->hw->xpcs == NULL) { 2775 ret = stmmac_init_phy(dev); 2776 if (ret) { 2777 netdev_err(priv->dev, 2778 "%s: Cannot attach to PHY (error: %d)\n", 2779 __func__, ret); 2780 return ret; 2781 } 2782 } 2783 2784 /* Extra statistics */ 2785 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2786 priv->xstats.threshold = tc; 2787 2788 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2789 if (bfsize < 0) 2790 bfsize = 0; 2791 2792 if (bfsize < BUF_SIZE_16KiB) 2793 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2794 2795 priv->dma_buf_sz = bfsize; 2796 buf_sz = bfsize; 2797 2798 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2799 2800 /* Earlier check for TBS */ 2801 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2802 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2803 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2804 2805 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2806 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2807 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2808 } 2809 2810 ret = alloc_dma_desc_resources(priv); 2811 if (ret < 0) { 2812 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2813 __func__); 2814 goto dma_desc_error; 2815 } 2816 2817 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2818 if (ret < 0) { 2819 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2820 __func__); 2821 goto init_error; 2822 } 2823 2824 ret = stmmac_hw_setup(dev, true); 2825 if (ret < 0) { 2826 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2827 goto init_error; 2828 } 2829 2830 stmmac_init_coalesce(priv); 2831 2832 phylink_start(priv->phylink); 2833 /* We may have called phylink_speed_down before */ 2834 phylink_speed_up(priv->phylink); 2835 2836 /* Request the IRQ lines */ 2837 ret = request_irq(dev->irq, stmmac_interrupt, 2838 IRQF_SHARED, dev->name, dev); 2839 if (unlikely(ret < 0)) { 2840 netdev_err(priv->dev, 2841 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2842 __func__, dev->irq, ret); 2843 goto irq_error; 2844 } 2845 2846 /* Request the Wake IRQ in case of another line is used for WoL */ 2847 if (priv->wol_irq != dev->irq) { 2848 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2849 IRQF_SHARED, dev->name, dev); 2850 if (unlikely(ret < 0)) { 2851 netdev_err(priv->dev, 2852 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2853 __func__, priv->wol_irq, ret); 2854 goto wolirq_error; 2855 } 2856 } 2857 2858 /* Request the IRQ lines */ 2859 if (priv->lpi_irq > 0) { 2860 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2861 dev->name, dev); 2862 if (unlikely(ret < 0)) { 2863 netdev_err(priv->dev, 2864 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2865 __func__, priv->lpi_irq, ret); 2866 goto lpiirq_error; 2867 } 2868 } 2869 2870 stmmac_enable_all_queues(priv); 2871 stmmac_start_all_queues(priv); 2872 2873 return 0; 2874 2875 lpiirq_error: 2876 if (priv->wol_irq != dev->irq) 2877 free_irq(priv->wol_irq, dev); 2878 wolirq_error: 2879 free_irq(dev->irq, dev); 2880 irq_error: 2881 phylink_stop(priv->phylink); 2882 2883 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2884 del_timer_sync(&priv->tx_queue[chan].txtimer); 2885 2886 stmmac_hw_teardown(dev); 2887 init_error: 2888 free_dma_desc_resources(priv); 2889 dma_desc_error: 2890 phylink_disconnect_phy(priv->phylink); 2891 return ret; 2892 } 2893 2894 /** 2895 * stmmac_release - close entry point of the driver 2896 * @dev : device pointer. 2897 * Description: 2898 * This is the stop entry point of the driver. 2899 */ 2900 static int stmmac_release(struct net_device *dev) 2901 { 2902 struct stmmac_priv *priv = netdev_priv(dev); 2903 u32 chan; 2904 2905 if (priv->eee_enabled) 2906 del_timer_sync(&priv->eee_ctrl_timer); 2907 2908 if (device_may_wakeup(priv->device)) 2909 phylink_speed_down(priv->phylink, false); 2910 /* Stop and disconnect the PHY */ 2911 phylink_stop(priv->phylink); 2912 phylink_disconnect_phy(priv->phylink); 2913 2914 stmmac_stop_all_queues(priv); 2915 2916 stmmac_disable_all_queues(priv); 2917 2918 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2919 del_timer_sync(&priv->tx_queue[chan].txtimer); 2920 2921 /* Free the IRQ lines */ 2922 free_irq(dev->irq, dev); 2923 if (priv->wol_irq != dev->irq) 2924 free_irq(priv->wol_irq, dev); 2925 if (priv->lpi_irq > 0) 2926 free_irq(priv->lpi_irq, dev); 2927 2928 /* Stop TX/RX DMA and clear the descriptors */ 2929 stmmac_stop_all_dma(priv); 2930 2931 /* Release and free the Rx/Tx resources */ 2932 free_dma_desc_resources(priv); 2933 2934 /* Disable the MAC Rx/Tx */ 2935 stmmac_mac_set(priv, priv->ioaddr, false); 2936 2937 netif_carrier_off(dev); 2938 2939 stmmac_release_ptp(priv); 2940 2941 return 0; 2942 } 2943 2944 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2945 struct stmmac_tx_queue *tx_q) 2946 { 2947 u16 tag = 0x0, inner_tag = 0x0; 2948 u32 inner_type = 0x0; 2949 struct dma_desc *p; 2950 2951 if (!priv->dma_cap.vlins) 2952 return false; 2953 if (!skb_vlan_tag_present(skb)) 2954 return false; 2955 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2956 inner_tag = skb_vlan_tag_get(skb); 2957 inner_type = STMMAC_VLAN_INSERT; 2958 } 2959 2960 tag = skb_vlan_tag_get(skb); 2961 2962 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2963 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2964 else 2965 p = &tx_q->dma_tx[tx_q->cur_tx]; 2966 2967 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2968 return false; 2969 2970 stmmac_set_tx_owner(priv, p); 2971 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2972 return true; 2973 } 2974 2975 /** 2976 * stmmac_tso_allocator - close entry point of the driver 2977 * @priv: driver private structure 2978 * @des: buffer start address 2979 * @total_len: total length to fill in descriptors 2980 * @last_segmant: condition for the last descriptor 2981 * @queue: TX queue index 2982 * Description: 2983 * This function fills descriptor and request new descriptors according to 2984 * buffer length to fill 2985 */ 2986 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2987 int total_len, bool last_segment, u32 queue) 2988 { 2989 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2990 struct dma_desc *desc; 2991 u32 buff_size; 2992 int tmp_len; 2993 2994 tmp_len = total_len; 2995 2996 while (tmp_len > 0) { 2997 dma_addr_t curr_addr; 2998 2999 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3000 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3001 3002 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3003 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3004 else 3005 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3006 3007 curr_addr = des + (total_len - tmp_len); 3008 if (priv->dma_cap.addr64 <= 32) 3009 desc->des0 = cpu_to_le32(curr_addr); 3010 else 3011 stmmac_set_desc_addr(priv, desc, curr_addr); 3012 3013 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3014 TSO_MAX_BUFF_SIZE : tmp_len; 3015 3016 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3017 0, 1, 3018 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3019 0, 0); 3020 3021 tmp_len -= TSO_MAX_BUFF_SIZE; 3022 } 3023 } 3024 3025 /** 3026 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3027 * @skb : the socket buffer 3028 * @dev : device pointer 3029 * Description: this is the transmit function that is called on TSO frames 3030 * (support available on GMAC4 and newer chips). 3031 * Diagram below show the ring programming in case of TSO frames: 3032 * 3033 * First Descriptor 3034 * -------- 3035 * | DES0 |---> buffer1 = L2/L3/L4 header 3036 * | DES1 |---> TCP Payload (can continue on next descr...) 3037 * | DES2 |---> buffer 1 and 2 len 3038 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3039 * -------- 3040 * | 3041 * ... 3042 * | 3043 * -------- 3044 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3045 * | DES1 | --| 3046 * | DES2 | --> buffer 1 and 2 len 3047 * | DES3 | 3048 * -------- 3049 * 3050 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3051 */ 3052 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3053 { 3054 struct dma_desc *desc, *first, *mss_desc = NULL; 3055 struct stmmac_priv *priv = netdev_priv(dev); 3056 int desc_size, tmp_pay_len = 0, first_tx; 3057 int nfrags = skb_shinfo(skb)->nr_frags; 3058 u32 queue = skb_get_queue_mapping(skb); 3059 unsigned int first_entry, tx_packets; 3060 struct stmmac_tx_queue *tx_q; 3061 bool has_vlan, set_ic; 3062 u8 proto_hdr_len, hdr; 3063 u32 pay_len, mss; 3064 dma_addr_t des; 3065 int i; 3066 3067 tx_q = &priv->tx_queue[queue]; 3068 first_tx = tx_q->cur_tx; 3069 3070 /* Compute header lengths */ 3071 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3072 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3073 hdr = sizeof(struct udphdr); 3074 } else { 3075 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3076 hdr = tcp_hdrlen(skb); 3077 } 3078 3079 /* Desc availability based on threshold should be enough safe */ 3080 if (unlikely(stmmac_tx_avail(priv, queue) < 3081 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3082 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3083 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3084 queue)); 3085 /* This is a hard error, log it. */ 3086 netdev_err(priv->dev, 3087 "%s: Tx Ring full when queue awake\n", 3088 __func__); 3089 } 3090 return NETDEV_TX_BUSY; 3091 } 3092 3093 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3094 3095 mss = skb_shinfo(skb)->gso_size; 3096 3097 /* set new MSS value if needed */ 3098 if (mss != tx_q->mss) { 3099 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3100 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3101 else 3102 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3103 3104 stmmac_set_mss(priv, mss_desc, mss); 3105 tx_q->mss = mss; 3106 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3107 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3108 } 3109 3110 if (netif_msg_tx_queued(priv)) { 3111 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3112 __func__, hdr, proto_hdr_len, pay_len, mss); 3113 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3114 skb->data_len); 3115 } 3116 3117 /* Check if VLAN can be inserted by HW */ 3118 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3119 3120 first_entry = tx_q->cur_tx; 3121 WARN_ON(tx_q->tx_skbuff[first_entry]); 3122 3123 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3124 desc = &tx_q->dma_entx[first_entry].basic; 3125 else 3126 desc = &tx_q->dma_tx[first_entry]; 3127 first = desc; 3128 3129 if (has_vlan) 3130 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3131 3132 /* first descriptor: fill Headers on Buf1 */ 3133 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3134 DMA_TO_DEVICE); 3135 if (dma_mapping_error(priv->device, des)) 3136 goto dma_map_err; 3137 3138 tx_q->tx_skbuff_dma[first_entry].buf = des; 3139 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3140 3141 if (priv->dma_cap.addr64 <= 32) { 3142 first->des0 = cpu_to_le32(des); 3143 3144 /* Fill start of payload in buff2 of first descriptor */ 3145 if (pay_len) 3146 first->des1 = cpu_to_le32(des + proto_hdr_len); 3147 3148 /* If needed take extra descriptors to fill the remaining payload */ 3149 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3150 } else { 3151 stmmac_set_desc_addr(priv, first, des); 3152 tmp_pay_len = pay_len; 3153 des += proto_hdr_len; 3154 pay_len = 0; 3155 } 3156 3157 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3158 3159 /* Prepare fragments */ 3160 for (i = 0; i < nfrags; i++) { 3161 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3162 3163 des = skb_frag_dma_map(priv->device, frag, 0, 3164 skb_frag_size(frag), 3165 DMA_TO_DEVICE); 3166 if (dma_mapping_error(priv->device, des)) 3167 goto dma_map_err; 3168 3169 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3170 (i == nfrags - 1), queue); 3171 3172 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3173 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3174 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3175 } 3176 3177 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3178 3179 /* Only the last descriptor gets to point to the skb. */ 3180 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3181 3182 /* Manage tx mitigation */ 3183 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3184 tx_q->tx_count_frames += tx_packets; 3185 3186 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3187 set_ic = true; 3188 else if (!priv->tx_coal_frames) 3189 set_ic = false; 3190 else if (tx_packets > priv->tx_coal_frames) 3191 set_ic = true; 3192 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3193 set_ic = true; 3194 else 3195 set_ic = false; 3196 3197 if (set_ic) { 3198 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3199 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3200 else 3201 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3202 3203 tx_q->tx_count_frames = 0; 3204 stmmac_set_tx_ic(priv, desc); 3205 priv->xstats.tx_set_ic_bit++; 3206 } 3207 3208 /* We've used all descriptors we need for this skb, however, 3209 * advance cur_tx so that it references a fresh descriptor. 3210 * ndo_start_xmit will fill this descriptor the next time it's 3211 * called and stmmac_tx_clean may clean up to this descriptor. 3212 */ 3213 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3214 3215 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3216 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3217 __func__); 3218 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3219 } 3220 3221 dev->stats.tx_bytes += skb->len; 3222 priv->xstats.tx_tso_frames++; 3223 priv->xstats.tx_tso_nfrags += nfrags; 3224 3225 if (priv->sarc_type) 3226 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3227 3228 skb_tx_timestamp(skb); 3229 3230 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3231 priv->hwts_tx_en)) { 3232 /* declare that device is doing timestamping */ 3233 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3234 stmmac_enable_tx_timestamp(priv, first); 3235 } 3236 3237 /* Complete the first descriptor before granting the DMA */ 3238 stmmac_prepare_tso_tx_desc(priv, first, 1, 3239 proto_hdr_len, 3240 pay_len, 3241 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3242 hdr / 4, (skb->len - proto_hdr_len)); 3243 3244 /* If context desc is used to change MSS */ 3245 if (mss_desc) { 3246 /* Make sure that first descriptor has been completely 3247 * written, including its own bit. This is because MSS is 3248 * actually before first descriptor, so we need to make 3249 * sure that MSS's own bit is the last thing written. 3250 */ 3251 dma_wmb(); 3252 stmmac_set_tx_owner(priv, mss_desc); 3253 } 3254 3255 /* The own bit must be the latest setting done when prepare the 3256 * descriptor and then barrier is needed to make sure that 3257 * all is coherent before granting the DMA engine. 3258 */ 3259 wmb(); 3260 3261 if (netif_msg_pktdata(priv)) { 3262 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3263 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3264 tx_q->cur_tx, first, nfrags); 3265 pr_info(">>> frame to be transmitted: "); 3266 print_pkt(skb->data, skb_headlen(skb)); 3267 } 3268 3269 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3270 3271 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3272 desc_size = sizeof(struct dma_edesc); 3273 else 3274 desc_size = sizeof(struct dma_desc); 3275 3276 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3277 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3278 stmmac_tx_timer_arm(priv, queue); 3279 3280 return NETDEV_TX_OK; 3281 3282 dma_map_err: 3283 dev_err(priv->device, "Tx dma map failed\n"); 3284 dev_kfree_skb(skb); 3285 priv->dev->stats.tx_dropped++; 3286 return NETDEV_TX_OK; 3287 } 3288 3289 /** 3290 * stmmac_xmit - Tx entry point of the driver 3291 * @skb : the socket buffer 3292 * @dev : device pointer 3293 * Description : this is the tx entry point of the driver. 3294 * It programs the chain or the ring and supports oversized frames 3295 * and SG feature. 3296 */ 3297 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3298 { 3299 unsigned int first_entry, tx_packets, enh_desc; 3300 struct stmmac_priv *priv = netdev_priv(dev); 3301 unsigned int nopaged_len = skb_headlen(skb); 3302 int i, csum_insertion = 0, is_jumbo = 0; 3303 u32 queue = skb_get_queue_mapping(skb); 3304 int nfrags = skb_shinfo(skb)->nr_frags; 3305 int gso = skb_shinfo(skb)->gso_type; 3306 struct dma_edesc *tbs_desc = NULL; 3307 int entry, desc_size, first_tx; 3308 struct dma_desc *desc, *first; 3309 struct stmmac_tx_queue *tx_q; 3310 bool has_vlan, set_ic; 3311 dma_addr_t des; 3312 3313 tx_q = &priv->tx_queue[queue]; 3314 first_tx = tx_q->cur_tx; 3315 3316 if (priv->tx_path_in_lpi_mode) 3317 stmmac_disable_eee_mode(priv); 3318 3319 /* Manage oversized TCP frames for GMAC4 device */ 3320 if (skb_is_gso(skb) && priv->tso) { 3321 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3322 return stmmac_tso_xmit(skb, dev); 3323 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3324 return stmmac_tso_xmit(skb, dev); 3325 } 3326 3327 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3328 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3329 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3330 queue)); 3331 /* This is a hard error, log it. */ 3332 netdev_err(priv->dev, 3333 "%s: Tx Ring full when queue awake\n", 3334 __func__); 3335 } 3336 return NETDEV_TX_BUSY; 3337 } 3338 3339 /* Check if VLAN can be inserted by HW */ 3340 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3341 3342 entry = tx_q->cur_tx; 3343 first_entry = entry; 3344 WARN_ON(tx_q->tx_skbuff[first_entry]); 3345 3346 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3347 3348 if (likely(priv->extend_desc)) 3349 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3350 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3351 desc = &tx_q->dma_entx[entry].basic; 3352 else 3353 desc = tx_q->dma_tx + entry; 3354 3355 first = desc; 3356 3357 if (has_vlan) 3358 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3359 3360 enh_desc = priv->plat->enh_desc; 3361 /* To program the descriptors according to the size of the frame */ 3362 if (enh_desc) 3363 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3364 3365 if (unlikely(is_jumbo)) { 3366 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3367 if (unlikely(entry < 0) && (entry != -EINVAL)) 3368 goto dma_map_err; 3369 } 3370 3371 for (i = 0; i < nfrags; i++) { 3372 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3373 int len = skb_frag_size(frag); 3374 bool last_segment = (i == (nfrags - 1)); 3375 3376 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3377 WARN_ON(tx_q->tx_skbuff[entry]); 3378 3379 if (likely(priv->extend_desc)) 3380 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3381 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3382 desc = &tx_q->dma_entx[entry].basic; 3383 else 3384 desc = tx_q->dma_tx + entry; 3385 3386 des = skb_frag_dma_map(priv->device, frag, 0, len, 3387 DMA_TO_DEVICE); 3388 if (dma_mapping_error(priv->device, des)) 3389 goto dma_map_err; /* should reuse desc w/o issues */ 3390 3391 tx_q->tx_skbuff_dma[entry].buf = des; 3392 3393 stmmac_set_desc_addr(priv, desc, des); 3394 3395 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3396 tx_q->tx_skbuff_dma[entry].len = len; 3397 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3398 3399 /* Prepare the descriptor and set the own bit too */ 3400 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3401 priv->mode, 1, last_segment, skb->len); 3402 } 3403 3404 /* Only the last descriptor gets to point to the skb. */ 3405 tx_q->tx_skbuff[entry] = skb; 3406 3407 /* According to the coalesce parameter the IC bit for the latest 3408 * segment is reset and the timer re-started to clean the tx status. 3409 * This approach takes care about the fragments: desc is the first 3410 * element in case of no SG. 3411 */ 3412 tx_packets = (entry + 1) - first_tx; 3413 tx_q->tx_count_frames += tx_packets; 3414 3415 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3416 set_ic = true; 3417 else if (!priv->tx_coal_frames) 3418 set_ic = false; 3419 else if (tx_packets > priv->tx_coal_frames) 3420 set_ic = true; 3421 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3422 set_ic = true; 3423 else 3424 set_ic = false; 3425 3426 if (set_ic) { 3427 if (likely(priv->extend_desc)) 3428 desc = &tx_q->dma_etx[entry].basic; 3429 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3430 desc = &tx_q->dma_entx[entry].basic; 3431 else 3432 desc = &tx_q->dma_tx[entry]; 3433 3434 tx_q->tx_count_frames = 0; 3435 stmmac_set_tx_ic(priv, desc); 3436 priv->xstats.tx_set_ic_bit++; 3437 } 3438 3439 /* We've used all descriptors we need for this skb, however, 3440 * advance cur_tx so that it references a fresh descriptor. 3441 * ndo_start_xmit will fill this descriptor the next time it's 3442 * called and stmmac_tx_clean may clean up to this descriptor. 3443 */ 3444 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3445 tx_q->cur_tx = entry; 3446 3447 if (netif_msg_pktdata(priv)) { 3448 netdev_dbg(priv->dev, 3449 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3450 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3451 entry, first, nfrags); 3452 3453 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3454 print_pkt(skb->data, skb->len); 3455 } 3456 3457 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3458 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3459 __func__); 3460 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3461 } 3462 3463 dev->stats.tx_bytes += skb->len; 3464 3465 if (priv->sarc_type) 3466 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3467 3468 skb_tx_timestamp(skb); 3469 3470 /* Ready to fill the first descriptor and set the OWN bit w/o any 3471 * problems because all the descriptors are actually ready to be 3472 * passed to the DMA engine. 3473 */ 3474 if (likely(!is_jumbo)) { 3475 bool last_segment = (nfrags == 0); 3476 3477 des = dma_map_single(priv->device, skb->data, 3478 nopaged_len, DMA_TO_DEVICE); 3479 if (dma_mapping_error(priv->device, des)) 3480 goto dma_map_err; 3481 3482 tx_q->tx_skbuff_dma[first_entry].buf = des; 3483 3484 stmmac_set_desc_addr(priv, first, des); 3485 3486 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3487 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3488 3489 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3490 priv->hwts_tx_en)) { 3491 /* declare that device is doing timestamping */ 3492 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3493 stmmac_enable_tx_timestamp(priv, first); 3494 } 3495 3496 /* Prepare the first descriptor setting the OWN bit too */ 3497 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3498 csum_insertion, priv->mode, 0, last_segment, 3499 skb->len); 3500 } 3501 3502 if (tx_q->tbs & STMMAC_TBS_EN) { 3503 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3504 3505 tbs_desc = &tx_q->dma_entx[first_entry]; 3506 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3507 } 3508 3509 stmmac_set_tx_owner(priv, first); 3510 3511 /* The own bit must be the latest setting done when prepare the 3512 * descriptor and then barrier is needed to make sure that 3513 * all is coherent before granting the DMA engine. 3514 */ 3515 wmb(); 3516 3517 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3518 3519 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3520 3521 if (likely(priv->extend_desc)) 3522 desc_size = sizeof(struct dma_extended_desc); 3523 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3524 desc_size = sizeof(struct dma_edesc); 3525 else 3526 desc_size = sizeof(struct dma_desc); 3527 3528 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3529 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3530 stmmac_tx_timer_arm(priv, queue); 3531 3532 return NETDEV_TX_OK; 3533 3534 dma_map_err: 3535 netdev_err(priv->dev, "Tx DMA map failed\n"); 3536 dev_kfree_skb(skb); 3537 priv->dev->stats.tx_dropped++; 3538 return NETDEV_TX_OK; 3539 } 3540 3541 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3542 { 3543 struct vlan_ethhdr *veth; 3544 __be16 vlan_proto; 3545 u16 vlanid; 3546 3547 veth = (struct vlan_ethhdr *)skb->data; 3548 vlan_proto = veth->h_vlan_proto; 3549 3550 if ((vlan_proto == htons(ETH_P_8021Q) && 3551 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3552 (vlan_proto == htons(ETH_P_8021AD) && 3553 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3554 /* pop the vlan tag */ 3555 vlanid = ntohs(veth->h_vlan_TCI); 3556 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3557 skb_pull(skb, VLAN_HLEN); 3558 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3559 } 3560 } 3561 3562 /** 3563 * stmmac_rx_refill - refill used skb preallocated buffers 3564 * @priv: driver private structure 3565 * @queue: RX queue index 3566 * Description : this is to reallocate the skb for the reception process 3567 * that is based on zero-copy. 3568 */ 3569 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3570 { 3571 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3572 int len, dirty = stmmac_rx_dirty(priv, queue); 3573 unsigned int entry = rx_q->dirty_rx; 3574 3575 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3576 3577 while (dirty-- > 0) { 3578 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3579 struct dma_desc *p; 3580 bool use_rx_wd; 3581 3582 if (priv->extend_desc) 3583 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3584 else 3585 p = rx_q->dma_rx + entry; 3586 3587 if (!buf->page) { 3588 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3589 if (!buf->page) 3590 break; 3591 } 3592 3593 if (priv->sph && !buf->sec_page) { 3594 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3595 if (!buf->sec_page) 3596 break; 3597 3598 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3599 3600 dma_sync_single_for_device(priv->device, buf->sec_addr, 3601 len, DMA_FROM_DEVICE); 3602 } 3603 3604 buf->addr = page_pool_get_dma_addr(buf->page); 3605 3606 /* Sync whole allocation to device. This will invalidate old 3607 * data. 3608 */ 3609 dma_sync_single_for_device(priv->device, buf->addr, len, 3610 DMA_FROM_DEVICE); 3611 3612 stmmac_set_desc_addr(priv, p, buf->addr); 3613 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3614 stmmac_refill_desc3(priv, rx_q, p); 3615 3616 rx_q->rx_count_frames++; 3617 rx_q->rx_count_frames += priv->rx_coal_frames; 3618 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3619 rx_q->rx_count_frames = 0; 3620 3621 use_rx_wd = !priv->rx_coal_frames; 3622 use_rx_wd |= rx_q->rx_count_frames > 0; 3623 if (!priv->use_riwt) 3624 use_rx_wd = false; 3625 3626 dma_wmb(); 3627 stmmac_set_rx_owner(priv, p, use_rx_wd); 3628 3629 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3630 } 3631 rx_q->dirty_rx = entry; 3632 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3633 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3634 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3635 } 3636 3637 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3638 struct dma_desc *p, 3639 int status, unsigned int len) 3640 { 3641 int ret, coe = priv->hw->rx_csum; 3642 unsigned int plen = 0, hlen = 0; 3643 3644 /* Not first descriptor, buffer is always zero */ 3645 if (priv->sph && len) 3646 return 0; 3647 3648 /* First descriptor, get split header length */ 3649 ret = stmmac_get_rx_header_len(priv, p, &hlen); 3650 if (priv->sph && hlen) { 3651 priv->xstats.rx_split_hdr_pkt_n++; 3652 return hlen; 3653 } 3654 3655 /* First descriptor, not last descriptor and not split header */ 3656 if (status & rx_not_ls) 3657 return priv->dma_buf_sz; 3658 3659 plen = stmmac_get_rx_frame_len(priv, p, coe); 3660 3661 /* First descriptor and last descriptor and not split header */ 3662 return min_t(unsigned int, priv->dma_buf_sz, plen); 3663 } 3664 3665 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3666 struct dma_desc *p, 3667 int status, unsigned int len) 3668 { 3669 int coe = priv->hw->rx_csum; 3670 unsigned int plen = 0; 3671 3672 /* Not split header, buffer is not available */ 3673 if (!priv->sph) 3674 return 0; 3675 3676 /* Not last descriptor */ 3677 if (status & rx_not_ls) 3678 return priv->dma_buf_sz; 3679 3680 plen = stmmac_get_rx_frame_len(priv, p, coe); 3681 3682 /* Last descriptor */ 3683 return plen - len; 3684 } 3685 3686 /** 3687 * stmmac_rx - manage the receive process 3688 * @priv: driver private structure 3689 * @limit: napi bugget 3690 * @queue: RX queue index. 3691 * Description : this the function called by the napi poll method. 3692 * It gets all the frames inside the ring. 3693 */ 3694 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3695 { 3696 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3697 struct stmmac_channel *ch = &priv->channel[queue]; 3698 unsigned int count = 0, error = 0, len = 0; 3699 int status = 0, coe = priv->hw->rx_csum; 3700 unsigned int next_entry = rx_q->cur_rx; 3701 struct sk_buff *skb = NULL; 3702 3703 if (netif_msg_rx_status(priv)) { 3704 void *rx_head; 3705 3706 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3707 if (priv->extend_desc) 3708 rx_head = (void *)rx_q->dma_erx; 3709 else 3710 rx_head = (void *)rx_q->dma_rx; 3711 3712 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3713 } 3714 while (count < limit) { 3715 unsigned int buf1_len = 0, buf2_len = 0; 3716 enum pkt_hash_types hash_type; 3717 struct stmmac_rx_buffer *buf; 3718 struct dma_desc *np, *p; 3719 int entry; 3720 u32 hash; 3721 3722 if (!count && rx_q->state_saved) { 3723 skb = rx_q->state.skb; 3724 error = rx_q->state.error; 3725 len = rx_q->state.len; 3726 } else { 3727 rx_q->state_saved = false; 3728 skb = NULL; 3729 error = 0; 3730 len = 0; 3731 } 3732 3733 if (count >= limit) 3734 break; 3735 3736 read_again: 3737 buf1_len = 0; 3738 buf2_len = 0; 3739 entry = next_entry; 3740 buf = &rx_q->buf_pool[entry]; 3741 3742 if (priv->extend_desc) 3743 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3744 else 3745 p = rx_q->dma_rx + entry; 3746 3747 /* read the status of the incoming frame */ 3748 status = stmmac_rx_status(priv, &priv->dev->stats, 3749 &priv->xstats, p); 3750 /* check if managed by the DMA otherwise go ahead */ 3751 if (unlikely(status & dma_own)) 3752 break; 3753 3754 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3755 next_entry = rx_q->cur_rx; 3756 3757 if (priv->extend_desc) 3758 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3759 else 3760 np = rx_q->dma_rx + next_entry; 3761 3762 prefetch(np); 3763 3764 if (priv->extend_desc) 3765 stmmac_rx_extended_status(priv, &priv->dev->stats, 3766 &priv->xstats, rx_q->dma_erx + entry); 3767 if (unlikely(status == discard_frame)) { 3768 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3769 buf->page = NULL; 3770 error = 1; 3771 if (!priv->hwts_rx_en) 3772 priv->dev->stats.rx_errors++; 3773 } 3774 3775 if (unlikely(error && (status & rx_not_ls))) 3776 goto read_again; 3777 if (unlikely(error)) { 3778 dev_kfree_skb(skb); 3779 skb = NULL; 3780 count++; 3781 continue; 3782 } 3783 3784 /* Buffer is good. Go on. */ 3785 3786 prefetch(page_address(buf->page)); 3787 if (buf->sec_page) 3788 prefetch(page_address(buf->sec_page)); 3789 3790 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3791 len += buf1_len; 3792 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3793 len += buf2_len; 3794 3795 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3796 * Type frames (LLC/LLC-SNAP) 3797 * 3798 * llc_snap is never checked in GMAC >= 4, so this ACS 3799 * feature is always disabled and packets need to be 3800 * stripped manually. 3801 */ 3802 if (likely(!(status & rx_not_ls)) && 3803 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3804 unlikely(status != llc_snap))) { 3805 if (buf2_len) 3806 buf2_len -= ETH_FCS_LEN; 3807 else 3808 buf1_len -= ETH_FCS_LEN; 3809 3810 len -= ETH_FCS_LEN; 3811 } 3812 3813 if (!skb) { 3814 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3815 if (!skb) { 3816 priv->dev->stats.rx_dropped++; 3817 count++; 3818 goto drain_data; 3819 } 3820 3821 dma_sync_single_for_cpu(priv->device, buf->addr, 3822 buf1_len, DMA_FROM_DEVICE); 3823 skb_copy_to_linear_data(skb, page_address(buf->page), 3824 buf1_len); 3825 skb_put(skb, buf1_len); 3826 3827 /* Data payload copied into SKB, page ready for recycle */ 3828 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3829 buf->page = NULL; 3830 } else if (buf1_len) { 3831 dma_sync_single_for_cpu(priv->device, buf->addr, 3832 buf1_len, DMA_FROM_DEVICE); 3833 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3834 buf->page, 0, buf1_len, 3835 priv->dma_buf_sz); 3836 3837 /* Data payload appended into SKB */ 3838 page_pool_release_page(rx_q->page_pool, buf->page); 3839 buf->page = NULL; 3840 } 3841 3842 if (buf2_len) { 3843 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3844 buf2_len, DMA_FROM_DEVICE); 3845 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3846 buf->sec_page, 0, buf2_len, 3847 priv->dma_buf_sz); 3848 3849 /* Data payload appended into SKB */ 3850 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3851 buf->sec_page = NULL; 3852 } 3853 3854 drain_data: 3855 if (likely(status & rx_not_ls)) 3856 goto read_again; 3857 if (!skb) 3858 continue; 3859 3860 /* Got entire packet into SKB. Finish it. */ 3861 3862 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3863 stmmac_rx_vlan(priv->dev, skb); 3864 skb->protocol = eth_type_trans(skb, priv->dev); 3865 3866 if (unlikely(!coe)) 3867 skb_checksum_none_assert(skb); 3868 else 3869 skb->ip_summed = CHECKSUM_UNNECESSARY; 3870 3871 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3872 skb_set_hash(skb, hash, hash_type); 3873 3874 skb_record_rx_queue(skb, queue); 3875 napi_gro_receive(&ch->rx_napi, skb); 3876 skb = NULL; 3877 3878 priv->dev->stats.rx_packets++; 3879 priv->dev->stats.rx_bytes += len; 3880 count++; 3881 } 3882 3883 if (status & rx_not_ls || skb) { 3884 rx_q->state_saved = true; 3885 rx_q->state.skb = skb; 3886 rx_q->state.error = error; 3887 rx_q->state.len = len; 3888 } 3889 3890 stmmac_rx_refill(priv, queue); 3891 3892 priv->xstats.rx_pkt_n += count; 3893 3894 return count; 3895 } 3896 3897 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3898 { 3899 struct stmmac_channel *ch = 3900 container_of(napi, struct stmmac_channel, rx_napi); 3901 struct stmmac_priv *priv = ch->priv_data; 3902 u32 chan = ch->index; 3903 int work_done; 3904 3905 priv->xstats.napi_poll++; 3906 3907 work_done = stmmac_rx(priv, budget, chan); 3908 if (work_done < budget && napi_complete_done(napi, work_done)) { 3909 unsigned long flags; 3910 3911 spin_lock_irqsave(&ch->lock, flags); 3912 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3913 spin_unlock_irqrestore(&ch->lock, flags); 3914 } 3915 3916 return work_done; 3917 } 3918 3919 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3920 { 3921 struct stmmac_channel *ch = 3922 container_of(napi, struct stmmac_channel, tx_napi); 3923 struct stmmac_priv *priv = ch->priv_data; 3924 u32 chan = ch->index; 3925 int work_done; 3926 3927 priv->xstats.napi_poll++; 3928 3929 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3930 work_done = min(work_done, budget); 3931 3932 if (work_done < budget && napi_complete_done(napi, work_done)) { 3933 unsigned long flags; 3934 3935 spin_lock_irqsave(&ch->lock, flags); 3936 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3937 spin_unlock_irqrestore(&ch->lock, flags); 3938 } 3939 3940 return work_done; 3941 } 3942 3943 /** 3944 * stmmac_tx_timeout 3945 * @dev : Pointer to net device structure 3946 * Description: this function is called when a packet transmission fails to 3947 * complete within a reasonable time. The driver will mark the error in the 3948 * netdev structure and arrange for the device to be reset to a sane state 3949 * in order to transmit a new packet. 3950 */ 3951 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3952 { 3953 struct stmmac_priv *priv = netdev_priv(dev); 3954 3955 stmmac_global_err(priv); 3956 } 3957 3958 /** 3959 * stmmac_set_rx_mode - entry point for multicast addressing 3960 * @dev : pointer to the device structure 3961 * Description: 3962 * This function is a driver entry point which gets called by the kernel 3963 * whenever multicast addresses must be enabled/disabled. 3964 * Return value: 3965 * void. 3966 */ 3967 static void stmmac_set_rx_mode(struct net_device *dev) 3968 { 3969 struct stmmac_priv *priv = netdev_priv(dev); 3970 3971 stmmac_set_filter(priv, priv->hw, dev); 3972 } 3973 3974 /** 3975 * stmmac_change_mtu - entry point to change MTU size for the device. 3976 * @dev : device pointer. 3977 * @new_mtu : the new MTU size for the device. 3978 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3979 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3980 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3981 * Return value: 3982 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3983 * file on failure. 3984 */ 3985 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3986 { 3987 struct stmmac_priv *priv = netdev_priv(dev); 3988 int txfifosz = priv->plat->tx_fifo_size; 3989 3990 if (txfifosz == 0) 3991 txfifosz = priv->dma_cap.tx_fifo_size; 3992 3993 txfifosz /= priv->plat->tx_queues_to_use; 3994 3995 if (netif_running(dev)) { 3996 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3997 return -EBUSY; 3998 } 3999 4000 new_mtu = STMMAC_ALIGN(new_mtu); 4001 4002 /* If condition true, FIFO is too small or MTU too large */ 4003 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 4004 return -EINVAL; 4005 4006 dev->mtu = new_mtu; 4007 4008 netdev_update_features(dev); 4009 4010 return 0; 4011 } 4012 4013 static netdev_features_t stmmac_fix_features(struct net_device *dev, 4014 netdev_features_t features) 4015 { 4016 struct stmmac_priv *priv = netdev_priv(dev); 4017 4018 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4019 features &= ~NETIF_F_RXCSUM; 4020 4021 if (!priv->plat->tx_coe) 4022 features &= ~NETIF_F_CSUM_MASK; 4023 4024 /* Some GMAC devices have a bugged Jumbo frame support that 4025 * needs to have the Tx COE disabled for oversized frames 4026 * (due to limited buffer sizes). In this case we disable 4027 * the TX csum insertion in the TDES and not use SF. 4028 */ 4029 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4030 features &= ~NETIF_F_CSUM_MASK; 4031 4032 /* Disable tso if asked by ethtool */ 4033 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4034 if (features & NETIF_F_TSO) 4035 priv->tso = true; 4036 else 4037 priv->tso = false; 4038 } 4039 4040 return features; 4041 } 4042 4043 static int stmmac_set_features(struct net_device *netdev, 4044 netdev_features_t features) 4045 { 4046 struct stmmac_priv *priv = netdev_priv(netdev); 4047 bool sph_en; 4048 u32 chan; 4049 4050 /* Keep the COE Type in case of csum is supporting */ 4051 if (features & NETIF_F_RXCSUM) 4052 priv->hw->rx_csum = priv->plat->rx_coe; 4053 else 4054 priv->hw->rx_csum = 0; 4055 /* No check needed because rx_coe has been set before and it will be 4056 * fixed in case of issue. 4057 */ 4058 stmmac_rx_ipc(priv, priv->hw); 4059 4060 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4061 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4062 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4063 4064 return 0; 4065 } 4066 4067 /** 4068 * stmmac_interrupt - main ISR 4069 * @irq: interrupt number. 4070 * @dev_id: to pass the net device pointer (must be valid). 4071 * Description: this is the main driver interrupt service routine. 4072 * It can call: 4073 * o DMA service routine (to manage incoming frame reception and transmission 4074 * status) 4075 * o Core interrupts to manage: remote wake-up, management counter, LPI 4076 * interrupts. 4077 */ 4078 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4079 { 4080 struct net_device *dev = (struct net_device *)dev_id; 4081 struct stmmac_priv *priv = netdev_priv(dev); 4082 u32 rx_cnt = priv->plat->rx_queues_to_use; 4083 u32 tx_cnt = priv->plat->tx_queues_to_use; 4084 u32 queues_count; 4085 u32 queue; 4086 bool xmac; 4087 4088 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4089 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4090 4091 if (priv->irq_wake) 4092 pm_wakeup_event(priv->device, 0); 4093 4094 /* Check if adapter is up */ 4095 if (test_bit(STMMAC_DOWN, &priv->state)) 4096 return IRQ_HANDLED; 4097 /* Check if a fatal error happened */ 4098 if (stmmac_safety_feat_interrupt(priv)) 4099 return IRQ_HANDLED; 4100 4101 /* To handle GMAC own interrupts */ 4102 if ((priv->plat->has_gmac) || xmac) { 4103 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4104 int mtl_status; 4105 4106 if (unlikely(status)) { 4107 /* For LPI we need to save the tx status */ 4108 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4109 priv->tx_path_in_lpi_mode = true; 4110 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4111 priv->tx_path_in_lpi_mode = false; 4112 } 4113 4114 for (queue = 0; queue < queues_count; queue++) { 4115 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4116 4117 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4118 queue); 4119 if (mtl_status != -EINVAL) 4120 status |= mtl_status; 4121 4122 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4123 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4124 rx_q->rx_tail_addr, 4125 queue); 4126 } 4127 4128 /* PCS link status */ 4129 if (priv->hw->pcs) { 4130 if (priv->xstats.pcs_link) 4131 netif_carrier_on(dev); 4132 else 4133 netif_carrier_off(dev); 4134 } 4135 } 4136 4137 /* To handle DMA interrupts */ 4138 stmmac_dma_interrupt(priv); 4139 4140 return IRQ_HANDLED; 4141 } 4142 4143 #ifdef CONFIG_NET_POLL_CONTROLLER 4144 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4145 * to allow network I/O with interrupts disabled. 4146 */ 4147 static void stmmac_poll_controller(struct net_device *dev) 4148 { 4149 disable_irq(dev->irq); 4150 stmmac_interrupt(dev->irq, dev); 4151 enable_irq(dev->irq); 4152 } 4153 #endif 4154 4155 /** 4156 * stmmac_ioctl - Entry point for the Ioctl 4157 * @dev: Device pointer. 4158 * @rq: An IOCTL specefic structure, that can contain a pointer to 4159 * a proprietary structure used to pass information to the driver. 4160 * @cmd: IOCTL command 4161 * Description: 4162 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4163 */ 4164 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4165 { 4166 struct stmmac_priv *priv = netdev_priv (dev); 4167 int ret = -EOPNOTSUPP; 4168 4169 if (!netif_running(dev)) 4170 return -EINVAL; 4171 4172 switch (cmd) { 4173 case SIOCGMIIPHY: 4174 case SIOCGMIIREG: 4175 case SIOCSMIIREG: 4176 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4177 break; 4178 case SIOCSHWTSTAMP: 4179 ret = stmmac_hwtstamp_set(dev, rq); 4180 break; 4181 case SIOCGHWTSTAMP: 4182 ret = stmmac_hwtstamp_get(dev, rq); 4183 break; 4184 default: 4185 break; 4186 } 4187 4188 return ret; 4189 } 4190 4191 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4192 void *cb_priv) 4193 { 4194 struct stmmac_priv *priv = cb_priv; 4195 int ret = -EOPNOTSUPP; 4196 4197 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4198 return ret; 4199 4200 stmmac_disable_all_queues(priv); 4201 4202 switch (type) { 4203 case TC_SETUP_CLSU32: 4204 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4205 break; 4206 case TC_SETUP_CLSFLOWER: 4207 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4208 break; 4209 default: 4210 break; 4211 } 4212 4213 stmmac_enable_all_queues(priv); 4214 return ret; 4215 } 4216 4217 static LIST_HEAD(stmmac_block_cb_list); 4218 4219 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4220 void *type_data) 4221 { 4222 struct stmmac_priv *priv = netdev_priv(ndev); 4223 4224 switch (type) { 4225 case TC_SETUP_BLOCK: 4226 return flow_block_cb_setup_simple(type_data, 4227 &stmmac_block_cb_list, 4228 stmmac_setup_tc_block_cb, 4229 priv, priv, true); 4230 case TC_SETUP_QDISC_CBS: 4231 return stmmac_tc_setup_cbs(priv, priv, type_data); 4232 case TC_SETUP_QDISC_TAPRIO: 4233 return stmmac_tc_setup_taprio(priv, priv, type_data); 4234 case TC_SETUP_QDISC_ETF: 4235 return stmmac_tc_setup_etf(priv, priv, type_data); 4236 default: 4237 return -EOPNOTSUPP; 4238 } 4239 } 4240 4241 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4242 struct net_device *sb_dev) 4243 { 4244 int gso = skb_shinfo(skb)->gso_type; 4245 4246 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4247 /* 4248 * There is no way to determine the number of TSO/USO 4249 * capable Queues. Let's use always the Queue 0 4250 * because if TSO/USO is supported then at least this 4251 * one will be capable. 4252 */ 4253 return 0; 4254 } 4255 4256 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4257 } 4258 4259 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4260 { 4261 struct stmmac_priv *priv = netdev_priv(ndev); 4262 int ret = 0; 4263 4264 ret = eth_mac_addr(ndev, addr); 4265 if (ret) 4266 return ret; 4267 4268 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4269 4270 return ret; 4271 } 4272 4273 #ifdef CONFIG_DEBUG_FS 4274 static struct dentry *stmmac_fs_dir; 4275 4276 static void sysfs_display_ring(void *head, int size, int extend_desc, 4277 struct seq_file *seq) 4278 { 4279 int i; 4280 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4281 struct dma_desc *p = (struct dma_desc *)head; 4282 4283 for (i = 0; i < size; i++) { 4284 if (extend_desc) { 4285 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4286 i, (unsigned int)virt_to_phys(ep), 4287 le32_to_cpu(ep->basic.des0), 4288 le32_to_cpu(ep->basic.des1), 4289 le32_to_cpu(ep->basic.des2), 4290 le32_to_cpu(ep->basic.des3)); 4291 ep++; 4292 } else { 4293 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4294 i, (unsigned int)virt_to_phys(p), 4295 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4296 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4297 p++; 4298 } 4299 seq_printf(seq, "\n"); 4300 } 4301 } 4302 4303 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4304 { 4305 struct net_device *dev = seq->private; 4306 struct stmmac_priv *priv = netdev_priv(dev); 4307 u32 rx_count = priv->plat->rx_queues_to_use; 4308 u32 tx_count = priv->plat->tx_queues_to_use; 4309 u32 queue; 4310 4311 if ((dev->flags & IFF_UP) == 0) 4312 return 0; 4313 4314 for (queue = 0; queue < rx_count; queue++) { 4315 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4316 4317 seq_printf(seq, "RX Queue %d:\n", queue); 4318 4319 if (priv->extend_desc) { 4320 seq_printf(seq, "Extended descriptor ring:\n"); 4321 sysfs_display_ring((void *)rx_q->dma_erx, 4322 DMA_RX_SIZE, 1, seq); 4323 } else { 4324 seq_printf(seq, "Descriptor ring:\n"); 4325 sysfs_display_ring((void *)rx_q->dma_rx, 4326 DMA_RX_SIZE, 0, seq); 4327 } 4328 } 4329 4330 for (queue = 0; queue < tx_count; queue++) { 4331 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4332 4333 seq_printf(seq, "TX Queue %d:\n", queue); 4334 4335 if (priv->extend_desc) { 4336 seq_printf(seq, "Extended descriptor ring:\n"); 4337 sysfs_display_ring((void *)tx_q->dma_etx, 4338 DMA_TX_SIZE, 1, seq); 4339 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4340 seq_printf(seq, "Descriptor ring:\n"); 4341 sysfs_display_ring((void *)tx_q->dma_tx, 4342 DMA_TX_SIZE, 0, seq); 4343 } 4344 } 4345 4346 return 0; 4347 } 4348 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4349 4350 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4351 { 4352 struct net_device *dev = seq->private; 4353 struct stmmac_priv *priv = netdev_priv(dev); 4354 4355 if (!priv->hw_cap_support) { 4356 seq_printf(seq, "DMA HW features not supported\n"); 4357 return 0; 4358 } 4359 4360 seq_printf(seq, "==============================\n"); 4361 seq_printf(seq, "\tDMA HW features\n"); 4362 seq_printf(seq, "==============================\n"); 4363 4364 seq_printf(seq, "\t10/100 Mbps: %s\n", 4365 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4366 seq_printf(seq, "\t1000 Mbps: %s\n", 4367 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4368 seq_printf(seq, "\tHalf duplex: %s\n", 4369 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4370 seq_printf(seq, "\tHash Filter: %s\n", 4371 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4372 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4373 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4374 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4375 (priv->dma_cap.pcs) ? "Y" : "N"); 4376 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4377 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4378 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4379 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4380 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4381 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4382 seq_printf(seq, "\tRMON module: %s\n", 4383 (priv->dma_cap.rmon) ? "Y" : "N"); 4384 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4385 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4386 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4387 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4388 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4389 (priv->dma_cap.eee) ? "Y" : "N"); 4390 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4391 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4392 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4393 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4394 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4395 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4396 } else { 4397 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4398 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4399 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4400 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4401 } 4402 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4403 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4404 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4405 priv->dma_cap.number_rx_channel); 4406 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4407 priv->dma_cap.number_tx_channel); 4408 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4409 priv->dma_cap.number_rx_queues); 4410 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4411 priv->dma_cap.number_tx_queues); 4412 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4413 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4414 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4415 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4416 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4417 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4418 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4419 priv->dma_cap.pps_out_num); 4420 seq_printf(seq, "\tSafety Features: %s\n", 4421 priv->dma_cap.asp ? "Y" : "N"); 4422 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4423 priv->dma_cap.frpsel ? "Y" : "N"); 4424 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4425 priv->dma_cap.addr64); 4426 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4427 priv->dma_cap.rssen ? "Y" : "N"); 4428 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4429 priv->dma_cap.vlhash ? "Y" : "N"); 4430 seq_printf(seq, "\tSplit Header: %s\n", 4431 priv->dma_cap.sphen ? "Y" : "N"); 4432 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4433 priv->dma_cap.vlins ? "Y" : "N"); 4434 seq_printf(seq, "\tDouble VLAN: %s\n", 4435 priv->dma_cap.dvlan ? "Y" : "N"); 4436 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4437 priv->dma_cap.l3l4fnum); 4438 seq_printf(seq, "\tARP Offloading: %s\n", 4439 priv->dma_cap.arpoffsel ? "Y" : "N"); 4440 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4441 priv->dma_cap.estsel ? "Y" : "N"); 4442 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4443 priv->dma_cap.fpesel ? "Y" : "N"); 4444 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4445 priv->dma_cap.tbssel ? "Y" : "N"); 4446 return 0; 4447 } 4448 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4449 4450 /* Use network device events to rename debugfs file entries. 4451 */ 4452 static int stmmac_device_event(struct notifier_block *unused, 4453 unsigned long event, void *ptr) 4454 { 4455 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4456 struct stmmac_priv *priv = netdev_priv(dev); 4457 4458 if (dev->netdev_ops != &stmmac_netdev_ops) 4459 goto done; 4460 4461 switch (event) { 4462 case NETDEV_CHANGENAME: 4463 if (priv->dbgfs_dir) 4464 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4465 priv->dbgfs_dir, 4466 stmmac_fs_dir, 4467 dev->name); 4468 break; 4469 } 4470 done: 4471 return NOTIFY_DONE; 4472 } 4473 4474 static struct notifier_block stmmac_notifier = { 4475 .notifier_call = stmmac_device_event, 4476 }; 4477 4478 static void stmmac_init_fs(struct net_device *dev) 4479 { 4480 struct stmmac_priv *priv = netdev_priv(dev); 4481 4482 rtnl_lock(); 4483 4484 /* Create per netdev entries */ 4485 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4486 4487 /* Entry to report DMA RX/TX rings */ 4488 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4489 &stmmac_rings_status_fops); 4490 4491 /* Entry to report the DMA HW features */ 4492 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4493 &stmmac_dma_cap_fops); 4494 4495 rtnl_unlock(); 4496 } 4497 4498 static void stmmac_exit_fs(struct net_device *dev) 4499 { 4500 struct stmmac_priv *priv = netdev_priv(dev); 4501 4502 debugfs_remove_recursive(priv->dbgfs_dir); 4503 } 4504 #endif /* CONFIG_DEBUG_FS */ 4505 4506 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4507 { 4508 unsigned char *data = (unsigned char *)&vid_le; 4509 unsigned char data_byte = 0; 4510 u32 crc = ~0x0; 4511 u32 temp = 0; 4512 int i, bits; 4513 4514 bits = get_bitmask_order(VLAN_VID_MASK); 4515 for (i = 0; i < bits; i++) { 4516 if ((i % 8) == 0) 4517 data_byte = data[i / 8]; 4518 4519 temp = ((crc & 1) ^ data_byte) & 1; 4520 crc >>= 1; 4521 data_byte >>= 1; 4522 4523 if (temp) 4524 crc ^= 0xedb88320; 4525 } 4526 4527 return crc; 4528 } 4529 4530 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4531 { 4532 u32 crc, hash = 0; 4533 __le16 pmatch = 0; 4534 int count = 0; 4535 u16 vid = 0; 4536 4537 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4538 __le16 vid_le = cpu_to_le16(vid); 4539 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4540 hash |= (1 << crc); 4541 count++; 4542 } 4543 4544 if (!priv->dma_cap.vlhash) { 4545 if (count > 2) /* VID = 0 always passes filter */ 4546 return -EOPNOTSUPP; 4547 4548 pmatch = cpu_to_le16(vid); 4549 hash = 0; 4550 } 4551 4552 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4553 } 4554 4555 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4556 { 4557 struct stmmac_priv *priv = netdev_priv(ndev); 4558 bool is_double = false; 4559 int ret; 4560 4561 if (be16_to_cpu(proto) == ETH_P_8021AD) 4562 is_double = true; 4563 4564 set_bit(vid, priv->active_vlans); 4565 ret = stmmac_vlan_update(priv, is_double); 4566 if (ret) { 4567 clear_bit(vid, priv->active_vlans); 4568 return ret; 4569 } 4570 4571 if (priv->hw->num_vlan) { 4572 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4573 if (ret) 4574 return ret; 4575 } 4576 4577 return 0; 4578 } 4579 4580 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4581 { 4582 struct stmmac_priv *priv = netdev_priv(ndev); 4583 bool is_double = false; 4584 int ret; 4585 4586 if (be16_to_cpu(proto) == ETH_P_8021AD) 4587 is_double = true; 4588 4589 clear_bit(vid, priv->active_vlans); 4590 4591 if (priv->hw->num_vlan) { 4592 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4593 if (ret) 4594 return ret; 4595 } 4596 4597 return stmmac_vlan_update(priv, is_double); 4598 } 4599 4600 static const struct net_device_ops stmmac_netdev_ops = { 4601 .ndo_open = stmmac_open, 4602 .ndo_start_xmit = stmmac_xmit, 4603 .ndo_stop = stmmac_release, 4604 .ndo_change_mtu = stmmac_change_mtu, 4605 .ndo_fix_features = stmmac_fix_features, 4606 .ndo_set_features = stmmac_set_features, 4607 .ndo_set_rx_mode = stmmac_set_rx_mode, 4608 .ndo_tx_timeout = stmmac_tx_timeout, 4609 .ndo_do_ioctl = stmmac_ioctl, 4610 .ndo_setup_tc = stmmac_setup_tc, 4611 .ndo_select_queue = stmmac_select_queue, 4612 #ifdef CONFIG_NET_POLL_CONTROLLER 4613 .ndo_poll_controller = stmmac_poll_controller, 4614 #endif 4615 .ndo_set_mac_address = stmmac_set_mac_address, 4616 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4617 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4618 }; 4619 4620 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4621 { 4622 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4623 return; 4624 if (test_bit(STMMAC_DOWN, &priv->state)) 4625 return; 4626 4627 netdev_err(priv->dev, "Reset adapter.\n"); 4628 4629 rtnl_lock(); 4630 netif_trans_update(priv->dev); 4631 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4632 usleep_range(1000, 2000); 4633 4634 set_bit(STMMAC_DOWN, &priv->state); 4635 dev_close(priv->dev); 4636 dev_open(priv->dev, NULL); 4637 clear_bit(STMMAC_DOWN, &priv->state); 4638 clear_bit(STMMAC_RESETING, &priv->state); 4639 rtnl_unlock(); 4640 } 4641 4642 static void stmmac_service_task(struct work_struct *work) 4643 { 4644 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4645 service_task); 4646 4647 stmmac_reset_subtask(priv); 4648 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4649 } 4650 4651 /** 4652 * stmmac_hw_init - Init the MAC device 4653 * @priv: driver private structure 4654 * Description: this function is to configure the MAC device according to 4655 * some platform parameters or the HW capability register. It prepares the 4656 * driver to use either ring or chain modes and to setup either enhanced or 4657 * normal descriptors. 4658 */ 4659 static int stmmac_hw_init(struct stmmac_priv *priv) 4660 { 4661 int ret; 4662 4663 /* dwmac-sun8i only work in chain mode */ 4664 if (priv->plat->has_sun8i) 4665 chain_mode = 1; 4666 priv->chain_mode = chain_mode; 4667 4668 /* Initialize HW Interface */ 4669 ret = stmmac_hwif_init(priv); 4670 if (ret) 4671 return ret; 4672 4673 /* Get the HW capability (new GMAC newer than 3.50a) */ 4674 priv->hw_cap_support = stmmac_get_hw_features(priv); 4675 if (priv->hw_cap_support) { 4676 dev_info(priv->device, "DMA HW capability register supported\n"); 4677 4678 /* We can override some gmac/dma configuration fields: e.g. 4679 * enh_desc, tx_coe (e.g. that are passed through the 4680 * platform) with the values from the HW capability 4681 * register (if supported). 4682 */ 4683 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4684 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4685 priv->hw->pmt = priv->plat->pmt; 4686 if (priv->dma_cap.hash_tb_sz) { 4687 priv->hw->multicast_filter_bins = 4688 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4689 priv->hw->mcast_bits_log2 = 4690 ilog2(priv->hw->multicast_filter_bins); 4691 } 4692 4693 /* TXCOE doesn't work in thresh DMA mode */ 4694 if (priv->plat->force_thresh_dma_mode) 4695 priv->plat->tx_coe = 0; 4696 else 4697 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4698 4699 /* In case of GMAC4 rx_coe is from HW cap register. */ 4700 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4701 4702 if (priv->dma_cap.rx_coe_type2) 4703 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4704 else if (priv->dma_cap.rx_coe_type1) 4705 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4706 4707 } else { 4708 dev_info(priv->device, "No HW DMA feature register supported\n"); 4709 } 4710 4711 if (priv->plat->rx_coe) { 4712 priv->hw->rx_csum = priv->plat->rx_coe; 4713 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4714 if (priv->synopsys_id < DWMAC_CORE_4_00) 4715 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4716 } 4717 if (priv->plat->tx_coe) 4718 dev_info(priv->device, "TX Checksum insertion supported\n"); 4719 4720 if (priv->plat->pmt) { 4721 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4722 device_set_wakeup_capable(priv->device, 1); 4723 } 4724 4725 if (priv->dma_cap.tsoen) 4726 dev_info(priv->device, "TSO supported\n"); 4727 4728 /* Run HW quirks, if any */ 4729 if (priv->hwif_quirks) { 4730 ret = priv->hwif_quirks(priv); 4731 if (ret) 4732 return ret; 4733 } 4734 4735 /* Rx Watchdog is available in the COREs newer than the 3.40. 4736 * In some case, for example on bugged HW this feature 4737 * has to be disable and this can be done by passing the 4738 * riwt_off field from the platform. 4739 */ 4740 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4741 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4742 priv->use_riwt = 1; 4743 dev_info(priv->device, 4744 "Enable RX Mitigation via HW Watchdog Timer\n"); 4745 } 4746 4747 return 0; 4748 } 4749 4750 /** 4751 * stmmac_dvr_probe 4752 * @device: device pointer 4753 * @plat_dat: platform data pointer 4754 * @res: stmmac resource pointer 4755 * Description: this is the main probe function used to 4756 * call the alloc_etherdev, allocate the priv structure. 4757 * Return: 4758 * returns 0 on success, otherwise errno. 4759 */ 4760 int stmmac_dvr_probe(struct device *device, 4761 struct plat_stmmacenet_data *plat_dat, 4762 struct stmmac_resources *res) 4763 { 4764 struct net_device *ndev = NULL; 4765 struct stmmac_priv *priv; 4766 u32 queue, rxq, maxq; 4767 int i, ret = 0; 4768 4769 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4770 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4771 if (!ndev) 4772 return -ENOMEM; 4773 4774 SET_NETDEV_DEV(ndev, device); 4775 4776 priv = netdev_priv(ndev); 4777 priv->device = device; 4778 priv->dev = ndev; 4779 4780 stmmac_set_ethtool_ops(ndev); 4781 priv->pause = pause; 4782 priv->plat = plat_dat; 4783 priv->ioaddr = res->addr; 4784 priv->dev->base_addr = (unsigned long)res->addr; 4785 4786 priv->dev->irq = res->irq; 4787 priv->wol_irq = res->wol_irq; 4788 priv->lpi_irq = res->lpi_irq; 4789 4790 if (!IS_ERR_OR_NULL(res->mac)) 4791 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4792 4793 dev_set_drvdata(device, priv->dev); 4794 4795 /* Verify driver arguments */ 4796 stmmac_verify_args(); 4797 4798 /* Allocate workqueue */ 4799 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4800 if (!priv->wq) { 4801 dev_err(priv->device, "failed to create workqueue\n"); 4802 return -ENOMEM; 4803 } 4804 4805 INIT_WORK(&priv->service_task, stmmac_service_task); 4806 4807 /* Override with kernel parameters if supplied XXX CRS XXX 4808 * this needs to have multiple instances 4809 */ 4810 if ((phyaddr >= 0) && (phyaddr <= 31)) 4811 priv->plat->phy_addr = phyaddr; 4812 4813 if (priv->plat->stmmac_rst) { 4814 ret = reset_control_assert(priv->plat->stmmac_rst); 4815 reset_control_deassert(priv->plat->stmmac_rst); 4816 /* Some reset controllers have only reset callback instead of 4817 * assert + deassert callbacks pair. 4818 */ 4819 if (ret == -ENOTSUPP) 4820 reset_control_reset(priv->plat->stmmac_rst); 4821 } 4822 4823 /* Init MAC and get the capabilities */ 4824 ret = stmmac_hw_init(priv); 4825 if (ret) 4826 goto error_hw_init; 4827 4828 stmmac_check_ether_addr(priv); 4829 4830 /* Configure real RX and TX queues */ 4831 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4832 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4833 4834 ndev->netdev_ops = &stmmac_netdev_ops; 4835 4836 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4837 NETIF_F_RXCSUM; 4838 4839 ret = stmmac_tc_init(priv, priv); 4840 if (!ret) { 4841 ndev->hw_features |= NETIF_F_HW_TC; 4842 } 4843 4844 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4845 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4846 if (priv->plat->has_gmac4) 4847 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4848 priv->tso = true; 4849 dev_info(priv->device, "TSO feature enabled\n"); 4850 } 4851 4852 if (priv->dma_cap.sphen) { 4853 ndev->hw_features |= NETIF_F_GRO; 4854 priv->sph = true; 4855 dev_info(priv->device, "SPH feature enabled\n"); 4856 } 4857 4858 if (priv->dma_cap.addr64) { 4859 ret = dma_set_mask_and_coherent(device, 4860 DMA_BIT_MASK(priv->dma_cap.addr64)); 4861 if (!ret) { 4862 dev_info(priv->device, "Using %d bits DMA width\n", 4863 priv->dma_cap.addr64); 4864 4865 /* 4866 * If more than 32 bits can be addressed, make sure to 4867 * enable enhanced addressing mode. 4868 */ 4869 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4870 priv->plat->dma_cfg->eame = true; 4871 } else { 4872 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4873 if (ret) { 4874 dev_err(priv->device, "Failed to set DMA Mask\n"); 4875 goto error_hw_init; 4876 } 4877 4878 priv->dma_cap.addr64 = 32; 4879 } 4880 } 4881 4882 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4883 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4884 #ifdef STMMAC_VLAN_TAG_USED 4885 /* Both mac100 and gmac support receive VLAN tag detection */ 4886 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4887 if (priv->dma_cap.vlhash) { 4888 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4889 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4890 } 4891 if (priv->dma_cap.vlins) { 4892 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4893 if (priv->dma_cap.dvlan) 4894 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4895 } 4896 #endif 4897 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4898 4899 /* Initialize RSS */ 4900 rxq = priv->plat->rx_queues_to_use; 4901 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4902 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4903 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4904 4905 if (priv->dma_cap.rssen && priv->plat->rss_en) 4906 ndev->features |= NETIF_F_RXHASH; 4907 4908 /* MTU range: 46 - hw-specific max */ 4909 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4910 if (priv->plat->has_xgmac) 4911 ndev->max_mtu = XGMAC_JUMBO_LEN; 4912 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4913 ndev->max_mtu = JUMBO_LEN; 4914 else 4915 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4916 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4917 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4918 */ 4919 if ((priv->plat->maxmtu < ndev->max_mtu) && 4920 (priv->plat->maxmtu >= ndev->min_mtu)) 4921 ndev->max_mtu = priv->plat->maxmtu; 4922 else if (priv->plat->maxmtu < ndev->min_mtu) 4923 dev_warn(priv->device, 4924 "%s: warning: maxmtu having invalid value (%d)\n", 4925 __func__, priv->plat->maxmtu); 4926 4927 if (flow_ctrl) 4928 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4929 4930 /* Setup channels NAPI */ 4931 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4932 4933 for (queue = 0; queue < maxq; queue++) { 4934 struct stmmac_channel *ch = &priv->channel[queue]; 4935 4936 spin_lock_init(&ch->lock); 4937 ch->priv_data = priv; 4938 ch->index = queue; 4939 4940 if (queue < priv->plat->rx_queues_to_use) { 4941 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4942 NAPI_POLL_WEIGHT); 4943 } 4944 if (queue < priv->plat->tx_queues_to_use) { 4945 netif_tx_napi_add(ndev, &ch->tx_napi, 4946 stmmac_napi_poll_tx, 4947 NAPI_POLL_WEIGHT); 4948 } 4949 } 4950 4951 mutex_init(&priv->lock); 4952 4953 /* If a specific clk_csr value is passed from the platform 4954 * this means that the CSR Clock Range selection cannot be 4955 * changed at run-time and it is fixed. Viceversa the driver'll try to 4956 * set the MDC clock dynamically according to the csr actual 4957 * clock input. 4958 */ 4959 if (priv->plat->clk_csr >= 0) 4960 priv->clk_csr = priv->plat->clk_csr; 4961 else 4962 stmmac_clk_csr_set(priv); 4963 4964 stmmac_check_pcs_mode(priv); 4965 4966 if (priv->hw->pcs != STMMAC_PCS_TBI && 4967 priv->hw->pcs != STMMAC_PCS_RTBI) { 4968 /* MDIO bus Registration */ 4969 ret = stmmac_mdio_register(ndev); 4970 if (ret < 0) { 4971 dev_err(priv->device, 4972 "%s: MDIO bus (id: %d) registration failed", 4973 __func__, priv->plat->bus_id); 4974 goto error_mdio_register; 4975 } 4976 } 4977 4978 ret = stmmac_phy_setup(priv); 4979 if (ret) { 4980 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4981 goto error_phy_setup; 4982 } 4983 4984 ret = register_netdev(ndev); 4985 if (ret) { 4986 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4987 __func__, ret); 4988 goto error_netdev_register; 4989 } 4990 4991 if (priv->plat->serdes_powerup) { 4992 ret = priv->plat->serdes_powerup(ndev, 4993 priv->plat->bsp_priv); 4994 4995 if (ret < 0) 4996 goto error_serdes_powerup; 4997 } 4998 4999 #ifdef CONFIG_DEBUG_FS 5000 stmmac_init_fs(ndev); 5001 #endif 5002 5003 return ret; 5004 5005 error_serdes_powerup: 5006 unregister_netdev(ndev); 5007 error_netdev_register: 5008 phylink_destroy(priv->phylink); 5009 error_phy_setup: 5010 if (priv->hw->pcs != STMMAC_PCS_TBI && 5011 priv->hw->pcs != STMMAC_PCS_RTBI) 5012 stmmac_mdio_unregister(ndev); 5013 error_mdio_register: 5014 for (queue = 0; queue < maxq; queue++) { 5015 struct stmmac_channel *ch = &priv->channel[queue]; 5016 5017 if (queue < priv->plat->rx_queues_to_use) 5018 netif_napi_del(&ch->rx_napi); 5019 if (queue < priv->plat->tx_queues_to_use) 5020 netif_napi_del(&ch->tx_napi); 5021 } 5022 error_hw_init: 5023 destroy_workqueue(priv->wq); 5024 5025 return ret; 5026 } 5027 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5028 5029 /** 5030 * stmmac_dvr_remove 5031 * @dev: device pointer 5032 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5033 * changes the link status, releases the DMA descriptor rings. 5034 */ 5035 int stmmac_dvr_remove(struct device *dev) 5036 { 5037 struct net_device *ndev = dev_get_drvdata(dev); 5038 struct stmmac_priv *priv = netdev_priv(ndev); 5039 5040 netdev_info(priv->dev, "%s: removing driver", __func__); 5041 5042 stmmac_stop_all_dma(priv); 5043 5044 if (priv->plat->serdes_powerdown) 5045 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5046 5047 stmmac_mac_set(priv, priv->ioaddr, false); 5048 netif_carrier_off(ndev); 5049 unregister_netdev(ndev); 5050 #ifdef CONFIG_DEBUG_FS 5051 stmmac_exit_fs(ndev); 5052 #endif 5053 phylink_destroy(priv->phylink); 5054 if (priv->plat->stmmac_rst) 5055 reset_control_assert(priv->plat->stmmac_rst); 5056 clk_disable_unprepare(priv->plat->pclk); 5057 clk_disable_unprepare(priv->plat->stmmac_clk); 5058 if (priv->hw->pcs != STMMAC_PCS_TBI && 5059 priv->hw->pcs != STMMAC_PCS_RTBI) 5060 stmmac_mdio_unregister(ndev); 5061 destroy_workqueue(priv->wq); 5062 mutex_destroy(&priv->lock); 5063 5064 return 0; 5065 } 5066 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5067 5068 /** 5069 * stmmac_suspend - suspend callback 5070 * @dev: device pointer 5071 * Description: this is the function to suspend the device and it is called 5072 * by the platform driver to stop the network queue, release the resources, 5073 * program the PMT register (for WoL), clean and release driver resources. 5074 */ 5075 int stmmac_suspend(struct device *dev) 5076 { 5077 struct net_device *ndev = dev_get_drvdata(dev); 5078 struct stmmac_priv *priv = netdev_priv(ndev); 5079 u32 chan; 5080 5081 if (!ndev || !netif_running(ndev)) 5082 return 0; 5083 5084 phylink_mac_change(priv->phylink, false); 5085 5086 mutex_lock(&priv->lock); 5087 5088 netif_device_detach(ndev); 5089 stmmac_stop_all_queues(priv); 5090 5091 stmmac_disable_all_queues(priv); 5092 5093 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5094 del_timer_sync(&priv->tx_queue[chan].txtimer); 5095 5096 /* Stop TX/RX DMA */ 5097 stmmac_stop_all_dma(priv); 5098 5099 if (priv->plat->serdes_powerdown) 5100 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5101 5102 /* Enable Power down mode by programming the PMT regs */ 5103 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5104 stmmac_pmt(priv, priv->hw, priv->wolopts); 5105 priv->irq_wake = 1; 5106 } else { 5107 mutex_unlock(&priv->lock); 5108 rtnl_lock(); 5109 if (device_may_wakeup(priv->device)) 5110 phylink_speed_down(priv->phylink, false); 5111 phylink_stop(priv->phylink); 5112 rtnl_unlock(); 5113 mutex_lock(&priv->lock); 5114 5115 stmmac_mac_set(priv, priv->ioaddr, false); 5116 pinctrl_pm_select_sleep_state(priv->device); 5117 /* Disable clock in case of PWM is off */ 5118 if (priv->plat->clk_ptp_ref) 5119 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5120 clk_disable_unprepare(priv->plat->pclk); 5121 clk_disable_unprepare(priv->plat->stmmac_clk); 5122 } 5123 mutex_unlock(&priv->lock); 5124 5125 priv->speed = SPEED_UNKNOWN; 5126 return 0; 5127 } 5128 EXPORT_SYMBOL_GPL(stmmac_suspend); 5129 5130 /** 5131 * stmmac_reset_queues_param - reset queue parameters 5132 * @dev: device pointer 5133 */ 5134 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5135 { 5136 u32 rx_cnt = priv->plat->rx_queues_to_use; 5137 u32 tx_cnt = priv->plat->tx_queues_to_use; 5138 u32 queue; 5139 5140 for (queue = 0; queue < rx_cnt; queue++) { 5141 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5142 5143 rx_q->cur_rx = 0; 5144 rx_q->dirty_rx = 0; 5145 } 5146 5147 for (queue = 0; queue < tx_cnt; queue++) { 5148 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5149 5150 tx_q->cur_tx = 0; 5151 tx_q->dirty_tx = 0; 5152 tx_q->mss = 0; 5153 } 5154 } 5155 5156 /** 5157 * stmmac_resume - resume callback 5158 * @dev: device pointer 5159 * Description: when resume this function is invoked to setup the DMA and CORE 5160 * in a usable state. 5161 */ 5162 int stmmac_resume(struct device *dev) 5163 { 5164 struct net_device *ndev = dev_get_drvdata(dev); 5165 struct stmmac_priv *priv = netdev_priv(ndev); 5166 int ret; 5167 5168 if (!netif_running(ndev)) 5169 return 0; 5170 5171 /* Power Down bit, into the PM register, is cleared 5172 * automatically as soon as a magic packet or a Wake-up frame 5173 * is received. Anyway, it's better to manually clear 5174 * this bit because it can generate problems while resuming 5175 * from another devices (e.g. serial console). 5176 */ 5177 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5178 mutex_lock(&priv->lock); 5179 stmmac_pmt(priv, priv->hw, 0); 5180 mutex_unlock(&priv->lock); 5181 priv->irq_wake = 0; 5182 } else { 5183 pinctrl_pm_select_default_state(priv->device); 5184 /* enable the clk previously disabled */ 5185 clk_prepare_enable(priv->plat->stmmac_clk); 5186 clk_prepare_enable(priv->plat->pclk); 5187 if (priv->plat->clk_ptp_ref) 5188 clk_prepare_enable(priv->plat->clk_ptp_ref); 5189 /* reset the phy so that it's ready */ 5190 if (priv->mii) 5191 stmmac_mdio_reset(priv->mii); 5192 } 5193 5194 if (priv->plat->serdes_powerup) { 5195 ret = priv->plat->serdes_powerup(ndev, 5196 priv->plat->bsp_priv); 5197 5198 if (ret < 0) 5199 return ret; 5200 } 5201 5202 mutex_lock(&priv->lock); 5203 5204 stmmac_reset_queues_param(priv); 5205 5206 stmmac_clear_descriptors(priv); 5207 5208 stmmac_hw_setup(ndev, false); 5209 stmmac_init_coalesce(priv); 5210 stmmac_set_rx_mode(ndev); 5211 5212 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5213 5214 stmmac_enable_all_queues(priv); 5215 5216 stmmac_start_all_queues(priv); 5217 5218 mutex_unlock(&priv->lock); 5219 5220 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 5221 rtnl_lock(); 5222 phylink_start(priv->phylink); 5223 /* We may have called phylink_speed_down before */ 5224 phylink_speed_up(priv->phylink); 5225 rtnl_unlock(); 5226 } 5227 5228 phylink_mac_change(priv->phylink, true); 5229 5230 netif_device_attach(ndev); 5231 5232 return 0; 5233 } 5234 EXPORT_SYMBOL_GPL(stmmac_resume); 5235 5236 #ifndef MODULE 5237 static int __init stmmac_cmdline_opt(char *str) 5238 { 5239 char *opt; 5240 5241 if (!str || !*str) 5242 return -EINVAL; 5243 while ((opt = strsep(&str, ",")) != NULL) { 5244 if (!strncmp(opt, "debug:", 6)) { 5245 if (kstrtoint(opt + 6, 0, &debug)) 5246 goto err; 5247 } else if (!strncmp(opt, "phyaddr:", 8)) { 5248 if (kstrtoint(opt + 8, 0, &phyaddr)) 5249 goto err; 5250 } else if (!strncmp(opt, "buf_sz:", 7)) { 5251 if (kstrtoint(opt + 7, 0, &buf_sz)) 5252 goto err; 5253 } else if (!strncmp(opt, "tc:", 3)) { 5254 if (kstrtoint(opt + 3, 0, &tc)) 5255 goto err; 5256 } else if (!strncmp(opt, "watchdog:", 9)) { 5257 if (kstrtoint(opt + 9, 0, &watchdog)) 5258 goto err; 5259 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5260 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5261 goto err; 5262 } else if (!strncmp(opt, "pause:", 6)) { 5263 if (kstrtoint(opt + 6, 0, &pause)) 5264 goto err; 5265 } else if (!strncmp(opt, "eee_timer:", 10)) { 5266 if (kstrtoint(opt + 10, 0, &eee_timer)) 5267 goto err; 5268 } else if (!strncmp(opt, "chain_mode:", 11)) { 5269 if (kstrtoint(opt + 11, 0, &chain_mode)) 5270 goto err; 5271 } 5272 } 5273 return 0; 5274 5275 err: 5276 pr_err("%s: ERROR broken module parameter conversion", __func__); 5277 return -EINVAL; 5278 } 5279 5280 __setup("stmmaceth=", stmmac_cmdline_opt); 5281 #endif /* MODULE */ 5282 5283 static int __init stmmac_init(void) 5284 { 5285 #ifdef CONFIG_DEBUG_FS 5286 /* Create debugfs main directory if it doesn't exist yet */ 5287 if (!stmmac_fs_dir) 5288 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5289 register_netdevice_notifier(&stmmac_notifier); 5290 #endif 5291 5292 return 0; 5293 } 5294 5295 static void __exit stmmac_exit(void) 5296 { 5297 #ifdef CONFIG_DEBUG_FS 5298 unregister_netdevice_notifier(&stmmac_notifier); 5299 debugfs_remove_recursive(stmmac_fs_dir); 5300 #endif 5301 } 5302 5303 module_init(stmmac_init) 5304 module_exit(stmmac_exit) 5305 5306 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5307 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5308 MODULE_LICENSE("GPL"); 5309