1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 #include <linux/of_mdio.h> 56 #include "dwmac1000.h" 57 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 60 61 /* Module parameters */ 62 #define TX_TIMEO 5000 63 static int watchdog = TX_TIMEO; 64 module_param(watchdog, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 66 67 static int debug = -1; 68 module_param(debug, int, S_IRUGO | S_IWUSR); 69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 70 71 static int phyaddr = -1; 72 module_param(phyaddr, int, S_IRUGO); 73 MODULE_PARM_DESC(phyaddr, "Physical device address"); 74 75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 77 78 static int flow_ctrl = FLOW_OFF; 79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 81 82 static int pause = PAUSE_TIME; 83 module_param(pause, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 85 86 #define TC_DEFAULT 64 87 static int tc = TC_DEFAULT; 88 module_param(tc, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(tc, "DMA threshold control value"); 90 91 #define DEFAULT_BUFSIZE 1536 92 static int buf_sz = DEFAULT_BUFSIZE; 93 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 94 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 95 96 #define STMMAC_RX_COPYBREAK 256 97 98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 99 NETIF_MSG_LINK | NETIF_MSG_IFUP | 100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 101 102 #define STMMAC_DEFAULT_LPI_TIMER 1000 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 107 108 /* By default the driver will use the ring mode to manage tx and rx descriptors, 109 * but allow user to force to use the chain instead of the ring 110 */ 111 static unsigned int chain_mode; 112 module_param(chain_mode, int, S_IRUGO); 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 114 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 116 117 #ifdef CONFIG_DEBUG_FS 118 static int stmmac_init_fs(struct net_device *dev); 119 static void stmmac_exit_fs(struct net_device *dev); 120 #endif 121 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 123 124 /** 125 * stmmac_verify_args - verify the driver parameters. 126 * Description: it checks the driver parameters and set a default in case of 127 * errors. 128 */ 129 static void stmmac_verify_args(void) 130 { 131 if (unlikely(watchdog < 0)) 132 watchdog = TX_TIMEO; 133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 134 buf_sz = DEFAULT_BUFSIZE; 135 if (unlikely(flow_ctrl > 1)) 136 flow_ctrl = FLOW_AUTO; 137 else if (likely(flow_ctrl < 0)) 138 flow_ctrl = FLOW_OFF; 139 if (unlikely((pause < 0) || (pause > 0xffff))) 140 pause = PAUSE_TIME; 141 if (eee_timer < 0) 142 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 143 } 144 145 /** 146 * stmmac_clk_csr_set - dynamically set the MDC clock 147 * @priv: driver private structure 148 * Description: this is to dynamically set the MDC clock according to the csr 149 * clock input. 150 * Note: 151 * If a specific clk_csr value is passed from the platform 152 * this means that the CSR Clock Range selection cannot be 153 * changed at run-time and it is fixed (as reported in the driver 154 * documentation). Viceversa the driver will try to set the MDC 155 * clock dynamically according to the actual clock input. 156 */ 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 158 { 159 u32 clk_rate; 160 161 clk_rate = clk_get_rate(priv->stmmac_clk); 162 163 /* Platform provided default clk_csr would be assumed valid 164 * for all other cases except for the below mentioned ones. 165 * For values higher than the IEEE 802.3 specified frequency 166 * we can not estimate the proper divider as it is not known 167 * the frequency of clk_csr_i. So we do not change the default 168 * divider. 169 */ 170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 171 if (clk_rate < CSR_F_35M) 172 priv->clk_csr = STMMAC_CSR_20_35M; 173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 174 priv->clk_csr = STMMAC_CSR_35_60M; 175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 176 priv->clk_csr = STMMAC_CSR_60_100M; 177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 178 priv->clk_csr = STMMAC_CSR_100_150M; 179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 180 priv->clk_csr = STMMAC_CSR_150_250M; 181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 182 priv->clk_csr = STMMAC_CSR_250_300M; 183 } 184 } 185 186 static void print_pkt(unsigned char *buf, int len) 187 { 188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 190 } 191 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 193 { 194 unsigned avail; 195 196 if (priv->dirty_tx > priv->cur_tx) 197 avail = priv->dirty_tx - priv->cur_tx - 1; 198 else 199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; 200 201 return avail; 202 } 203 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) 205 { 206 unsigned dirty; 207 208 if (priv->dirty_rx <= priv->cur_rx) 209 dirty = priv->cur_rx - priv->dirty_rx; 210 else 211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; 212 213 return dirty; 214 } 215 216 /** 217 * stmmac_hw_fix_mac_speed - callback for speed selection 218 * @priv: driver private structure 219 * Description: on some platforms (e.g. ST), some HW system configuraton 220 * registers have to be set according to the link speed negotiated. 221 */ 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 223 { 224 struct net_device *ndev = priv->dev; 225 struct phy_device *phydev = ndev->phydev; 226 227 if (likely(priv->plat->fix_mac_speed)) 228 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 229 } 230 231 /** 232 * stmmac_enable_eee_mode - check and enter in LPI mode 233 * @priv: driver private structure 234 * Description: this function is to verify and enter in LPI mode in case of 235 * EEE. 236 */ 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 238 { 239 /* Check and enter in LPI mode */ 240 if ((priv->dirty_tx == priv->cur_tx) && 241 (priv->tx_path_in_lpi_mode == false)) 242 priv->hw->mac->set_eee_mode(priv->hw); 243 } 244 245 /** 246 * stmmac_disable_eee_mode - disable and exit from LPI mode 247 * @priv: driver private structure 248 * Description: this function is to exit and disable EEE in case of 249 * LPI state is true. This is called by the xmit. 250 */ 251 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 252 { 253 priv->hw->mac->reset_eee_mode(priv->hw); 254 del_timer_sync(&priv->eee_ctrl_timer); 255 priv->tx_path_in_lpi_mode = false; 256 } 257 258 /** 259 * stmmac_eee_ctrl_timer - EEE TX SW timer. 260 * @arg : data hook 261 * Description: 262 * if there is no data transfer and if we are not in LPI state, 263 * then MAC Transmitter can be moved to LPI state. 264 */ 265 static void stmmac_eee_ctrl_timer(unsigned long arg) 266 { 267 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 268 269 stmmac_enable_eee_mode(priv); 270 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 271 } 272 273 /** 274 * stmmac_eee_init - init EEE 275 * @priv: driver private structure 276 * Description: 277 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 278 * can also manage EEE, this function enable the LPI state and start related 279 * timer. 280 */ 281 bool stmmac_eee_init(struct stmmac_priv *priv) 282 { 283 struct net_device *ndev = priv->dev; 284 unsigned long flags; 285 bool ret = false; 286 287 /* Using PCS we cannot dial with the phy registers at this stage 288 * so we do not support extra feature like EEE. 289 */ 290 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 291 (priv->hw->pcs == STMMAC_PCS_TBI) || 292 (priv->hw->pcs == STMMAC_PCS_RTBI)) 293 goto out; 294 295 /* MAC core supports the EEE feature. */ 296 if (priv->dma_cap.eee) { 297 int tx_lpi_timer = priv->tx_lpi_timer; 298 299 /* Check if the PHY supports EEE */ 300 if (phy_init_eee(ndev->phydev, 1)) { 301 /* To manage at run-time if the EEE cannot be supported 302 * anymore (for example because the lp caps have been 303 * changed). 304 * In that case the driver disable own timers. 305 */ 306 spin_lock_irqsave(&priv->lock, flags); 307 if (priv->eee_active) { 308 netdev_dbg(priv->dev, "disable EEE\n"); 309 del_timer_sync(&priv->eee_ctrl_timer); 310 priv->hw->mac->set_eee_timer(priv->hw, 0, 311 tx_lpi_timer); 312 } 313 priv->eee_active = 0; 314 spin_unlock_irqrestore(&priv->lock, flags); 315 goto out; 316 } 317 /* Activate the EEE and start timers */ 318 spin_lock_irqsave(&priv->lock, flags); 319 if (!priv->eee_active) { 320 priv->eee_active = 1; 321 setup_timer(&priv->eee_ctrl_timer, 322 stmmac_eee_ctrl_timer, 323 (unsigned long)priv); 324 mod_timer(&priv->eee_ctrl_timer, 325 STMMAC_LPI_T(eee_timer)); 326 327 priv->hw->mac->set_eee_timer(priv->hw, 328 STMMAC_DEFAULT_LIT_LS, 329 tx_lpi_timer); 330 } 331 /* Set HW EEE according to the speed */ 332 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); 333 334 ret = true; 335 spin_unlock_irqrestore(&priv->lock, flags); 336 337 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 338 } 339 out: 340 return ret; 341 } 342 343 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 344 * @priv: driver private structure 345 * @p : descriptor pointer 346 * @skb : the socket buffer 347 * Description : 348 * This function will read timestamp from the descriptor & pass it to stack. 349 * and also perform some sanity checks. 350 */ 351 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 352 struct dma_desc *p, struct sk_buff *skb) 353 { 354 struct skb_shared_hwtstamps shhwtstamp; 355 u64 ns; 356 357 if (!priv->hwts_tx_en) 358 return; 359 360 /* exit if skb doesn't support hw tstamp */ 361 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 362 return; 363 364 /* check tx tstamp status */ 365 if (!priv->hw->desc->get_tx_timestamp_status(p)) { 366 /* get the valid tstamp */ 367 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); 368 369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 370 shhwtstamp.hwtstamp = ns_to_ktime(ns); 371 372 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); 373 /* pass tstamp to stack */ 374 skb_tstamp_tx(skb, &shhwtstamp); 375 } 376 377 return; 378 } 379 380 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 381 * @priv: driver private structure 382 * @p : descriptor pointer 383 * @np : next descriptor pointer 384 * @skb : the socket buffer 385 * Description : 386 * This function will read received packet's timestamp from the descriptor 387 * and pass it to stack. It also perform some sanity checks. 388 */ 389 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 390 struct dma_desc *np, struct sk_buff *skb) 391 { 392 struct skb_shared_hwtstamps *shhwtstamp = NULL; 393 u64 ns; 394 395 if (!priv->hwts_rx_en) 396 return; 397 398 /* Check if timestamp is available */ 399 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { 400 /* For GMAC4, the valid timestamp is from CTX next desc. */ 401 if (priv->plat->has_gmac4) 402 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); 403 else 404 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); 405 406 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); 407 shhwtstamp = skb_hwtstamps(skb); 408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 409 shhwtstamp->hwtstamp = ns_to_ktime(ns); 410 } else { 411 netdev_err(priv->dev, "cannot get RX hw timestamp\n"); 412 } 413 } 414 415 /** 416 * stmmac_hwtstamp_ioctl - control hardware timestamping. 417 * @dev: device pointer. 418 * @ifr: An IOCTL specefic structure, that can contain a pointer to 419 * a proprietary structure used to pass information to the driver. 420 * Description: 421 * This function configures the MAC to enable/disable both outgoing(TX) 422 * and incoming(RX) packets time stamping based on user input. 423 * Return Value: 424 * 0 on success and an appropriate -ve integer on failure. 425 */ 426 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 427 { 428 struct stmmac_priv *priv = netdev_priv(dev); 429 struct hwtstamp_config config; 430 struct timespec64 now; 431 u64 temp = 0; 432 u32 ptp_v2 = 0; 433 u32 tstamp_all = 0; 434 u32 ptp_over_ipv4_udp = 0; 435 u32 ptp_over_ipv6_udp = 0; 436 u32 ptp_over_ethernet = 0; 437 u32 snap_type_sel = 0; 438 u32 ts_master_en = 0; 439 u32 ts_event_en = 0; 440 u32 value = 0; 441 u32 sec_inc; 442 443 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 444 netdev_alert(priv->dev, "No support for HW time stamping\n"); 445 priv->hwts_tx_en = 0; 446 priv->hwts_rx_en = 0; 447 448 return -EOPNOTSUPP; 449 } 450 451 if (copy_from_user(&config, ifr->ifr_data, 452 sizeof(struct hwtstamp_config))) 453 return -EFAULT; 454 455 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 456 __func__, config.flags, config.tx_type, config.rx_filter); 457 458 /* reserved for future extensions */ 459 if (config.flags) 460 return -EINVAL; 461 462 if (config.tx_type != HWTSTAMP_TX_OFF && 463 config.tx_type != HWTSTAMP_TX_ON) 464 return -ERANGE; 465 466 if (priv->adv_ts) { 467 switch (config.rx_filter) { 468 case HWTSTAMP_FILTER_NONE: 469 /* time stamp no incoming packet at all */ 470 config.rx_filter = HWTSTAMP_FILTER_NONE; 471 break; 472 473 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 474 /* PTP v1, UDP, any kind of event packet */ 475 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 476 /* take time stamp for all event messages */ 477 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 478 479 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 480 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 481 break; 482 483 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 484 /* PTP v1, UDP, Sync packet */ 485 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 486 /* take time stamp for SYNC messages only */ 487 ts_event_en = PTP_TCR_TSEVNTENA; 488 489 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 490 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 491 break; 492 493 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 494 /* PTP v1, UDP, Delay_req packet */ 495 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 496 /* take time stamp for Delay_Req messages only */ 497 ts_master_en = PTP_TCR_TSMSTRENA; 498 ts_event_en = PTP_TCR_TSEVNTENA; 499 500 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 501 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 502 break; 503 504 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 505 /* PTP v2, UDP, any kind of event packet */ 506 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 507 ptp_v2 = PTP_TCR_TSVER2ENA; 508 /* take time stamp for all event messages */ 509 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 510 511 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 512 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 513 break; 514 515 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 516 /* PTP v2, UDP, Sync packet */ 517 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 518 ptp_v2 = PTP_TCR_TSVER2ENA; 519 /* take time stamp for SYNC messages only */ 520 ts_event_en = PTP_TCR_TSEVNTENA; 521 522 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 523 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 524 break; 525 526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 527 /* PTP v2, UDP, Delay_req packet */ 528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 529 ptp_v2 = PTP_TCR_TSVER2ENA; 530 /* take time stamp for Delay_Req messages only */ 531 ts_master_en = PTP_TCR_TSMSTRENA; 532 ts_event_en = PTP_TCR_TSEVNTENA; 533 534 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 535 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 536 break; 537 538 case HWTSTAMP_FILTER_PTP_V2_EVENT: 539 /* PTP v2/802.AS1 any layer, any kind of event packet */ 540 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 541 ptp_v2 = PTP_TCR_TSVER2ENA; 542 /* take time stamp for all event messages */ 543 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 544 545 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 546 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 547 ptp_over_ethernet = PTP_TCR_TSIPENA; 548 break; 549 550 case HWTSTAMP_FILTER_PTP_V2_SYNC: 551 /* PTP v2/802.AS1, any layer, Sync packet */ 552 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 553 ptp_v2 = PTP_TCR_TSVER2ENA; 554 /* take time stamp for SYNC messages only */ 555 ts_event_en = PTP_TCR_TSEVNTENA; 556 557 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 558 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 559 ptp_over_ethernet = PTP_TCR_TSIPENA; 560 break; 561 562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 563 /* PTP v2/802.AS1, any layer, Delay_req packet */ 564 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 565 ptp_v2 = PTP_TCR_TSVER2ENA; 566 /* take time stamp for Delay_Req messages only */ 567 ts_master_en = PTP_TCR_TSMSTRENA; 568 ts_event_en = PTP_TCR_TSEVNTENA; 569 570 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 571 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 572 ptp_over_ethernet = PTP_TCR_TSIPENA; 573 break; 574 575 case HWTSTAMP_FILTER_ALL: 576 /* time stamp any incoming packet */ 577 config.rx_filter = HWTSTAMP_FILTER_ALL; 578 tstamp_all = PTP_TCR_TSENALL; 579 break; 580 581 default: 582 return -ERANGE; 583 } 584 } else { 585 switch (config.rx_filter) { 586 case HWTSTAMP_FILTER_NONE: 587 config.rx_filter = HWTSTAMP_FILTER_NONE; 588 break; 589 default: 590 /* PTP v1, UDP, any kind of event packet */ 591 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 592 break; 593 } 594 } 595 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 596 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 597 598 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 599 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); 600 else { 601 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 602 tstamp_all | ptp_v2 | ptp_over_ethernet | 603 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 604 ts_master_en | snap_type_sel); 605 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); 606 607 /* program Sub Second Increment reg */ 608 sec_inc = priv->hw->ptp->config_sub_second_increment( 609 priv->ptpaddr, priv->clk_ptp_rate, 610 priv->plat->has_gmac4); 611 temp = div_u64(1000000000ULL, sec_inc); 612 613 /* calculate default added value: 614 * formula is : 615 * addend = (2^32)/freq_div_ratio; 616 * where, freq_div_ratio = 1e9ns/sec_inc 617 */ 618 temp = (u64)(temp << 32); 619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 620 priv->hw->ptp->config_addend(priv->ptpaddr, 621 priv->default_addend); 622 623 /* initialize system time */ 624 ktime_get_real_ts64(&now); 625 626 /* lower 32 bits of tv_sec are safe until y2106 */ 627 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, 628 now.tv_nsec); 629 } 630 631 return copy_to_user(ifr->ifr_data, &config, 632 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 633 } 634 635 /** 636 * stmmac_init_ptp - init PTP 637 * @priv: driver private structure 638 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 639 * This is done by looking at the HW cap. register. 640 * This function also registers the ptp driver. 641 */ 642 static int stmmac_init_ptp(struct stmmac_priv *priv) 643 { 644 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 645 return -EOPNOTSUPP; 646 647 /* Fall-back to main clock in case of no PTP ref is passed */ 648 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 649 if (IS_ERR(priv->clk_ptp_ref)) { 650 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 651 priv->clk_ptp_ref = NULL; 652 netdev_dbg(priv->dev, "PTP uses main clock\n"); 653 } else { 654 clk_prepare_enable(priv->clk_ptp_ref); 655 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 656 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); 657 } 658 659 priv->adv_ts = 0; 660 /* Check if adv_ts can be enabled for dwmac 4.x core */ 661 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) 662 priv->adv_ts = 1; 663 /* Dwmac 3.x core with extend_desc can support adv_ts */ 664 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 665 priv->adv_ts = 1; 666 667 if (priv->dma_cap.time_stamp) 668 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 669 670 if (priv->adv_ts) 671 netdev_info(priv->dev, 672 "IEEE 1588-2008 Advanced Timestamp supported\n"); 673 674 priv->hw->ptp = &stmmac_ptp; 675 priv->hwts_tx_en = 0; 676 priv->hwts_rx_en = 0; 677 678 stmmac_ptp_register(priv); 679 680 return 0; 681 } 682 683 static void stmmac_release_ptp(struct stmmac_priv *priv) 684 { 685 if (priv->clk_ptp_ref) 686 clk_disable_unprepare(priv->clk_ptp_ref); 687 stmmac_ptp_unregister(priv); 688 } 689 690 /** 691 * stmmac_adjust_link - adjusts the link parameters 692 * @dev: net device structure 693 * Description: this is the helper called by the physical abstraction layer 694 * drivers to communicate the phy link status. According the speed and duplex 695 * this driver can invoke registered glue-logic as well. 696 * It also invoke the eee initialization because it could happen when switch 697 * on different networks (that are eee capable). 698 */ 699 static void stmmac_adjust_link(struct net_device *dev) 700 { 701 struct stmmac_priv *priv = netdev_priv(dev); 702 struct phy_device *phydev = dev->phydev; 703 unsigned long flags; 704 int new_state = 0; 705 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 706 707 if (phydev == NULL) 708 return; 709 710 spin_lock_irqsave(&priv->lock, flags); 711 712 if (phydev->link) { 713 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 714 715 /* Now we make sure that we can be in full duplex mode. 716 * If not, we operate in half-duplex mode. */ 717 if (phydev->duplex != priv->oldduplex) { 718 new_state = 1; 719 if (!(phydev->duplex)) 720 ctrl &= ~priv->hw->link.duplex; 721 else 722 ctrl |= priv->hw->link.duplex; 723 priv->oldduplex = phydev->duplex; 724 } 725 /* Flow Control operation */ 726 if (phydev->pause) 727 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 728 fc, pause_time); 729 730 if (phydev->speed != priv->speed) { 731 new_state = 1; 732 switch (phydev->speed) { 733 case 1000: 734 if (likely((priv->plat->has_gmac) || 735 (priv->plat->has_gmac4))) 736 ctrl &= ~priv->hw->link.port; 737 stmmac_hw_fix_mac_speed(priv); 738 break; 739 case 100: 740 case 10: 741 if (likely((priv->plat->has_gmac) || 742 (priv->plat->has_gmac4))) { 743 ctrl |= priv->hw->link.port; 744 if (phydev->speed == SPEED_100) { 745 ctrl |= priv->hw->link.speed; 746 } else { 747 ctrl &= ~(priv->hw->link.speed); 748 } 749 } else { 750 ctrl &= ~priv->hw->link.port; 751 } 752 stmmac_hw_fix_mac_speed(priv); 753 break; 754 default: 755 netif_warn(priv, link, priv->dev, 756 "Speed (%d) not 10/100\n", 757 phydev->speed); 758 break; 759 } 760 761 priv->speed = phydev->speed; 762 } 763 764 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 765 766 if (!priv->oldlink) { 767 new_state = 1; 768 priv->oldlink = 1; 769 } 770 } else if (priv->oldlink) { 771 new_state = 1; 772 priv->oldlink = 0; 773 priv->speed = 0; 774 priv->oldduplex = -1; 775 } 776 777 if (new_state && netif_msg_link(priv)) 778 phy_print_status(phydev); 779 780 spin_unlock_irqrestore(&priv->lock, flags); 781 782 if (phydev->is_pseudo_fixed_link) 783 /* Stop PHY layer to call the hook to adjust the link in case 784 * of a switch is attached to the stmmac driver. 785 */ 786 phydev->irq = PHY_IGNORE_INTERRUPT; 787 else 788 /* At this stage, init the EEE if supported. 789 * Never called in case of fixed_link. 790 */ 791 priv->eee_enabled = stmmac_eee_init(priv); 792 } 793 794 /** 795 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 796 * @priv: driver private structure 797 * Description: this is to verify if the HW supports the PCS. 798 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 799 * configured for the TBI, RTBI, or SGMII PHY interface. 800 */ 801 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 802 { 803 int interface = priv->plat->interface; 804 805 if (priv->dma_cap.pcs) { 806 if ((interface == PHY_INTERFACE_MODE_RGMII) || 807 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 808 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 809 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 810 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 811 priv->hw->pcs = STMMAC_PCS_RGMII; 812 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 813 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 814 priv->hw->pcs = STMMAC_PCS_SGMII; 815 } 816 } 817 } 818 819 /** 820 * stmmac_init_phy - PHY initialization 821 * @dev: net device structure 822 * Description: it initializes the driver's PHY state, and attaches the PHY 823 * to the mac driver. 824 * Return value: 825 * 0 on success 826 */ 827 static int stmmac_init_phy(struct net_device *dev) 828 { 829 struct stmmac_priv *priv = netdev_priv(dev); 830 struct phy_device *phydev; 831 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 832 char bus_id[MII_BUS_ID_SIZE]; 833 int interface = priv->plat->interface; 834 int max_speed = priv->plat->max_speed; 835 priv->oldlink = 0; 836 priv->speed = 0; 837 priv->oldduplex = -1; 838 839 if (priv->plat->phy_node) { 840 phydev = of_phy_connect(dev, priv->plat->phy_node, 841 &stmmac_adjust_link, 0, interface); 842 } else { 843 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 844 priv->plat->bus_id); 845 846 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 847 priv->plat->phy_addr); 848 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, 849 phy_id_fmt); 850 851 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 852 interface); 853 } 854 855 if (IS_ERR_OR_NULL(phydev)) { 856 netdev_err(priv->dev, "Could not attach to PHY\n"); 857 if (!phydev) 858 return -ENODEV; 859 860 return PTR_ERR(phydev); 861 } 862 863 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 864 if ((interface == PHY_INTERFACE_MODE_MII) || 865 (interface == PHY_INTERFACE_MODE_RMII) || 866 (max_speed < 1000 && max_speed > 0)) 867 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 868 SUPPORTED_1000baseT_Full); 869 870 /* 871 * Broken HW is sometimes missing the pull-up resistor on the 872 * MDIO line, which results in reads to non-existent devices returning 873 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 874 * device as well. 875 * Note: phydev->phy_id is the result of reading the UID PHY registers. 876 */ 877 if (!priv->plat->phy_node && phydev->phy_id == 0) { 878 phy_disconnect(phydev); 879 return -ENODEV; 880 } 881 882 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid 883 * subsequent PHY polling, make sure we force a link transition if 884 * we have a UP/DOWN/UP transition 885 */ 886 if (phydev->is_pseudo_fixed_link) 887 phydev->irq = PHY_POLL; 888 889 netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n", 890 __func__, phydev->phy_id, phydev->link); 891 892 return 0; 893 } 894 895 static void stmmac_display_rings(struct stmmac_priv *priv) 896 { 897 void *head_rx, *head_tx; 898 899 if (priv->extend_desc) { 900 head_rx = (void *)priv->dma_erx; 901 head_tx = (void *)priv->dma_etx; 902 } else { 903 head_rx = (void *)priv->dma_rx; 904 head_tx = (void *)priv->dma_tx; 905 } 906 907 /* Display Rx ring */ 908 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); 909 /* Display Tx ring */ 910 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); 911 } 912 913 static int stmmac_set_bfsize(int mtu, int bufsize) 914 { 915 int ret = bufsize; 916 917 if (mtu >= BUF_SIZE_4KiB) 918 ret = BUF_SIZE_8KiB; 919 else if (mtu >= BUF_SIZE_2KiB) 920 ret = BUF_SIZE_4KiB; 921 else if (mtu > DEFAULT_BUFSIZE) 922 ret = BUF_SIZE_2KiB; 923 else 924 ret = DEFAULT_BUFSIZE; 925 926 return ret; 927 } 928 929 /** 930 * stmmac_clear_descriptors - clear descriptors 931 * @priv: driver private structure 932 * Description: this function is called to clear the tx and rx descriptors 933 * in case of both basic and extended descriptors are used. 934 */ 935 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 936 { 937 int i; 938 939 /* Clear the Rx/Tx descriptors */ 940 for (i = 0; i < DMA_RX_SIZE; i++) 941 if (priv->extend_desc) 942 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 943 priv->use_riwt, priv->mode, 944 (i == DMA_RX_SIZE - 1)); 945 else 946 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 947 priv->use_riwt, priv->mode, 948 (i == DMA_RX_SIZE - 1)); 949 for (i = 0; i < DMA_TX_SIZE; i++) 950 if (priv->extend_desc) 951 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 952 priv->mode, 953 (i == DMA_TX_SIZE - 1)); 954 else 955 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 956 priv->mode, 957 (i == DMA_TX_SIZE - 1)); 958 } 959 960 /** 961 * stmmac_init_rx_buffers - init the RX descriptor buffer. 962 * @priv: driver private structure 963 * @p: descriptor pointer 964 * @i: descriptor index 965 * @flags: gfp flag. 966 * Description: this function is called to allocate a receive buffer, perform 967 * the DMA mapping and init the descriptor. 968 */ 969 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 970 int i, gfp_t flags) 971 { 972 struct sk_buff *skb; 973 974 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 975 if (!skb) { 976 netdev_err(priv->dev, 977 "%s: Rx init fails; skb is NULL\n", __func__); 978 return -ENOMEM; 979 } 980 priv->rx_skbuff[i] = skb; 981 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 982 priv->dma_buf_sz, 983 DMA_FROM_DEVICE); 984 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 985 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 986 dev_kfree_skb_any(skb); 987 return -EINVAL; 988 } 989 990 if (priv->synopsys_id >= DWMAC_CORE_4_00) 991 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]); 992 else 993 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]); 994 995 if ((priv->hw->mode->init_desc3) && 996 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 997 priv->hw->mode->init_desc3(p); 998 999 return 0; 1000 } 1001 1002 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 1003 { 1004 if (priv->rx_skbuff[i]) { 1005 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1006 priv->dma_buf_sz, DMA_FROM_DEVICE); 1007 dev_kfree_skb_any(priv->rx_skbuff[i]); 1008 } 1009 priv->rx_skbuff[i] = NULL; 1010 } 1011 1012 /** 1013 * init_dma_desc_rings - init the RX/TX descriptor rings 1014 * @dev: net device structure 1015 * @flags: gfp flag. 1016 * Description: this function initializes the DMA RX/TX descriptors 1017 * and allocates the socket buffers. It suppors the chained and ring 1018 * modes. 1019 */ 1020 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1021 { 1022 int i; 1023 struct stmmac_priv *priv = netdev_priv(dev); 1024 unsigned int bfsize = 0; 1025 int ret = -ENOMEM; 1026 1027 if (priv->hw->mode->set_16kib_bfsize) 1028 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1029 1030 if (bfsize < BUF_SIZE_16KiB) 1031 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1032 1033 priv->dma_buf_sz = bfsize; 1034 1035 netif_dbg(priv, probe, priv->dev, 1036 "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", 1037 __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy); 1038 1039 /* RX INITIALIZATION */ 1040 netif_dbg(priv, probe, priv->dev, 1041 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1042 1043 for (i = 0; i < DMA_RX_SIZE; i++) { 1044 struct dma_desc *p; 1045 if (priv->extend_desc) 1046 p = &((priv->dma_erx + i)->basic); 1047 else 1048 p = priv->dma_rx + i; 1049 1050 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1051 if (ret) 1052 goto err_init_rx_buffers; 1053 1054 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", 1055 priv->rx_skbuff[i], priv->rx_skbuff[i]->data, 1056 (unsigned int)priv->rx_skbuff_dma[i]); 1057 } 1058 priv->cur_rx = 0; 1059 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1060 buf_sz = bfsize; 1061 1062 /* Setup the chained descriptor addresses */ 1063 if (priv->mode == STMMAC_CHAIN_MODE) { 1064 if (priv->extend_desc) { 1065 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1066 DMA_RX_SIZE, 1); 1067 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1068 DMA_TX_SIZE, 1); 1069 } else { 1070 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1071 DMA_RX_SIZE, 0); 1072 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1073 DMA_TX_SIZE, 0); 1074 } 1075 } 1076 1077 /* TX INITIALIZATION */ 1078 for (i = 0; i < DMA_TX_SIZE; i++) { 1079 struct dma_desc *p; 1080 if (priv->extend_desc) 1081 p = &((priv->dma_etx + i)->basic); 1082 else 1083 p = priv->dma_tx + i; 1084 1085 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1086 p->des0 = 0; 1087 p->des1 = 0; 1088 p->des2 = 0; 1089 p->des3 = 0; 1090 } else { 1091 p->des2 = 0; 1092 } 1093 1094 priv->tx_skbuff_dma[i].buf = 0; 1095 priv->tx_skbuff_dma[i].map_as_page = false; 1096 priv->tx_skbuff_dma[i].len = 0; 1097 priv->tx_skbuff_dma[i].last_segment = false; 1098 priv->tx_skbuff[i] = NULL; 1099 } 1100 1101 priv->dirty_tx = 0; 1102 priv->cur_tx = 0; 1103 netdev_reset_queue(priv->dev); 1104 1105 stmmac_clear_descriptors(priv); 1106 1107 if (netif_msg_hw(priv)) 1108 stmmac_display_rings(priv); 1109 1110 return 0; 1111 err_init_rx_buffers: 1112 while (--i >= 0) 1113 stmmac_free_rx_buffers(priv, i); 1114 return ret; 1115 } 1116 1117 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1118 { 1119 int i; 1120 1121 for (i = 0; i < DMA_RX_SIZE; i++) 1122 stmmac_free_rx_buffers(priv, i); 1123 } 1124 1125 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1126 { 1127 int i; 1128 1129 for (i = 0; i < DMA_TX_SIZE; i++) { 1130 struct dma_desc *p; 1131 1132 if (priv->extend_desc) 1133 p = &((priv->dma_etx + i)->basic); 1134 else 1135 p = priv->dma_tx + i; 1136 1137 if (priv->tx_skbuff_dma[i].buf) { 1138 if (priv->tx_skbuff_dma[i].map_as_page) 1139 dma_unmap_page(priv->device, 1140 priv->tx_skbuff_dma[i].buf, 1141 priv->tx_skbuff_dma[i].len, 1142 DMA_TO_DEVICE); 1143 else 1144 dma_unmap_single(priv->device, 1145 priv->tx_skbuff_dma[i].buf, 1146 priv->tx_skbuff_dma[i].len, 1147 DMA_TO_DEVICE); 1148 } 1149 1150 if (priv->tx_skbuff[i] != NULL) { 1151 dev_kfree_skb_any(priv->tx_skbuff[i]); 1152 priv->tx_skbuff[i] = NULL; 1153 priv->tx_skbuff_dma[i].buf = 0; 1154 priv->tx_skbuff_dma[i].map_as_page = false; 1155 } 1156 } 1157 } 1158 1159 /** 1160 * alloc_dma_desc_resources - alloc TX/RX resources. 1161 * @priv: private structure 1162 * Description: according to which descriptor can be used (extend or basic) 1163 * this function allocates the resources for TX and RX paths. In case of 1164 * reception, for example, it pre-allocated the RX socket buffer in order to 1165 * allow zero-copy mechanism. 1166 */ 1167 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1168 { 1169 int ret = -ENOMEM; 1170 1171 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), 1172 GFP_KERNEL); 1173 if (!priv->rx_skbuff_dma) 1174 return -ENOMEM; 1175 1176 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), 1177 GFP_KERNEL); 1178 if (!priv->rx_skbuff) 1179 goto err_rx_skbuff; 1180 1181 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1182 sizeof(*priv->tx_skbuff_dma), 1183 GFP_KERNEL); 1184 if (!priv->tx_skbuff_dma) 1185 goto err_tx_skbuff_dma; 1186 1187 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), 1188 GFP_KERNEL); 1189 if (!priv->tx_skbuff) 1190 goto err_tx_skbuff; 1191 1192 if (priv->extend_desc) { 1193 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1194 sizeof(struct 1195 dma_extended_desc), 1196 &priv->dma_rx_phy, 1197 GFP_KERNEL); 1198 if (!priv->dma_erx) 1199 goto err_dma; 1200 1201 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1202 sizeof(struct 1203 dma_extended_desc), 1204 &priv->dma_tx_phy, 1205 GFP_KERNEL); 1206 if (!priv->dma_etx) { 1207 dma_free_coherent(priv->device, DMA_RX_SIZE * 1208 sizeof(struct dma_extended_desc), 1209 priv->dma_erx, priv->dma_rx_phy); 1210 goto err_dma; 1211 } 1212 } else { 1213 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1214 sizeof(struct dma_desc), 1215 &priv->dma_rx_phy, 1216 GFP_KERNEL); 1217 if (!priv->dma_rx) 1218 goto err_dma; 1219 1220 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1221 sizeof(struct dma_desc), 1222 &priv->dma_tx_phy, 1223 GFP_KERNEL); 1224 if (!priv->dma_tx) { 1225 dma_free_coherent(priv->device, DMA_RX_SIZE * 1226 sizeof(struct dma_desc), 1227 priv->dma_rx, priv->dma_rx_phy); 1228 goto err_dma; 1229 } 1230 } 1231 1232 return 0; 1233 1234 err_dma: 1235 kfree(priv->tx_skbuff); 1236 err_tx_skbuff: 1237 kfree(priv->tx_skbuff_dma); 1238 err_tx_skbuff_dma: 1239 kfree(priv->rx_skbuff); 1240 err_rx_skbuff: 1241 kfree(priv->rx_skbuff_dma); 1242 return ret; 1243 } 1244 1245 static void free_dma_desc_resources(struct stmmac_priv *priv) 1246 { 1247 /* Release the DMA TX/RX socket buffers */ 1248 dma_free_rx_skbufs(priv); 1249 dma_free_tx_skbufs(priv); 1250 1251 /* Free DMA regions of consistent memory previously allocated */ 1252 if (!priv->extend_desc) { 1253 dma_free_coherent(priv->device, 1254 DMA_TX_SIZE * sizeof(struct dma_desc), 1255 priv->dma_tx, priv->dma_tx_phy); 1256 dma_free_coherent(priv->device, 1257 DMA_RX_SIZE * sizeof(struct dma_desc), 1258 priv->dma_rx, priv->dma_rx_phy); 1259 } else { 1260 dma_free_coherent(priv->device, DMA_TX_SIZE * 1261 sizeof(struct dma_extended_desc), 1262 priv->dma_etx, priv->dma_tx_phy); 1263 dma_free_coherent(priv->device, DMA_RX_SIZE * 1264 sizeof(struct dma_extended_desc), 1265 priv->dma_erx, priv->dma_rx_phy); 1266 } 1267 kfree(priv->rx_skbuff_dma); 1268 kfree(priv->rx_skbuff); 1269 kfree(priv->tx_skbuff_dma); 1270 kfree(priv->tx_skbuff); 1271 } 1272 1273 /** 1274 * stmmac_dma_operation_mode - HW DMA operation mode 1275 * @priv: driver private structure 1276 * Description: it is used for configuring the DMA operation mode register in 1277 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1278 */ 1279 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1280 { 1281 int rxfifosz = priv->plat->rx_fifo_size; 1282 1283 if (priv->plat->force_thresh_dma_mode) 1284 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); 1285 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1286 /* 1287 * In case of GMAC, SF mode can be enabled 1288 * to perform the TX COE in HW. This depends on: 1289 * 1) TX COE if actually supported 1290 * 2) There is no bugged Jumbo frame support 1291 * that needs to not insert csum in the TDES. 1292 */ 1293 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, 1294 rxfifosz); 1295 priv->xstats.threshold = SF_DMA_MODE; 1296 } else 1297 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, 1298 rxfifosz); 1299 } 1300 1301 /** 1302 * stmmac_tx_clean - to manage the transmission completion 1303 * @priv: driver private structure 1304 * Description: it reclaims the transmit resources after transmission completes. 1305 */ 1306 static void stmmac_tx_clean(struct stmmac_priv *priv) 1307 { 1308 unsigned int bytes_compl = 0, pkts_compl = 0; 1309 unsigned int entry = priv->dirty_tx; 1310 1311 spin_lock(&priv->tx_lock); 1312 1313 priv->xstats.tx_clean++; 1314 1315 while (entry != priv->cur_tx) { 1316 struct sk_buff *skb = priv->tx_skbuff[entry]; 1317 struct dma_desc *p; 1318 int status; 1319 1320 if (priv->extend_desc) 1321 p = (struct dma_desc *)(priv->dma_etx + entry); 1322 else 1323 p = priv->dma_tx + entry; 1324 1325 status = priv->hw->desc->tx_status(&priv->dev->stats, 1326 &priv->xstats, p, 1327 priv->ioaddr); 1328 /* Check if the descriptor is owned by the DMA */ 1329 if (unlikely(status & tx_dma_own)) 1330 break; 1331 1332 /* Just consider the last segment and ...*/ 1333 if (likely(!(status & tx_not_ls))) { 1334 /* ... verify the status error condition */ 1335 if (unlikely(status & tx_err)) { 1336 priv->dev->stats.tx_errors++; 1337 } else { 1338 priv->dev->stats.tx_packets++; 1339 priv->xstats.tx_pkt_n++; 1340 } 1341 stmmac_get_tx_hwtstamp(priv, p, skb); 1342 } 1343 1344 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1345 if (priv->tx_skbuff_dma[entry].map_as_page) 1346 dma_unmap_page(priv->device, 1347 priv->tx_skbuff_dma[entry].buf, 1348 priv->tx_skbuff_dma[entry].len, 1349 DMA_TO_DEVICE); 1350 else 1351 dma_unmap_single(priv->device, 1352 priv->tx_skbuff_dma[entry].buf, 1353 priv->tx_skbuff_dma[entry].len, 1354 DMA_TO_DEVICE); 1355 priv->tx_skbuff_dma[entry].buf = 0; 1356 priv->tx_skbuff_dma[entry].len = 0; 1357 priv->tx_skbuff_dma[entry].map_as_page = false; 1358 } 1359 1360 if (priv->hw->mode->clean_desc3) 1361 priv->hw->mode->clean_desc3(priv, p); 1362 1363 priv->tx_skbuff_dma[entry].last_segment = false; 1364 priv->tx_skbuff_dma[entry].is_jumbo = false; 1365 1366 if (likely(skb != NULL)) { 1367 pkts_compl++; 1368 bytes_compl += skb->len; 1369 dev_consume_skb_any(skb); 1370 priv->tx_skbuff[entry] = NULL; 1371 } 1372 1373 priv->hw->desc->release_tx_desc(p, priv->mode); 1374 1375 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1376 } 1377 priv->dirty_tx = entry; 1378 1379 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1380 1381 if (unlikely(netif_queue_stopped(priv->dev) && 1382 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { 1383 netif_tx_lock(priv->dev); 1384 if (netif_queue_stopped(priv->dev) && 1385 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) { 1386 netif_dbg(priv, tx_done, priv->dev, 1387 "%s: restart transmit\n", __func__); 1388 netif_wake_queue(priv->dev); 1389 } 1390 netif_tx_unlock(priv->dev); 1391 } 1392 1393 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1394 stmmac_enable_eee_mode(priv); 1395 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1396 } 1397 spin_unlock(&priv->tx_lock); 1398 } 1399 1400 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1401 { 1402 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1403 } 1404 1405 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1406 { 1407 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1408 } 1409 1410 /** 1411 * stmmac_tx_err - to manage the tx error 1412 * @priv: driver private structure 1413 * Description: it cleans the descriptors and restarts the transmission 1414 * in case of transmission errors. 1415 */ 1416 static void stmmac_tx_err(struct stmmac_priv *priv) 1417 { 1418 int i; 1419 netif_stop_queue(priv->dev); 1420 1421 priv->hw->dma->stop_tx(priv->ioaddr); 1422 dma_free_tx_skbufs(priv); 1423 for (i = 0; i < DMA_TX_SIZE; i++) 1424 if (priv->extend_desc) 1425 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1426 priv->mode, 1427 (i == DMA_TX_SIZE - 1)); 1428 else 1429 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1430 priv->mode, 1431 (i == DMA_TX_SIZE - 1)); 1432 priv->dirty_tx = 0; 1433 priv->cur_tx = 0; 1434 netdev_reset_queue(priv->dev); 1435 priv->hw->dma->start_tx(priv->ioaddr); 1436 1437 priv->dev->stats.tx_errors++; 1438 netif_wake_queue(priv->dev); 1439 } 1440 1441 /** 1442 * stmmac_dma_interrupt - DMA ISR 1443 * @priv: driver private structure 1444 * Description: this is the DMA ISR. It is called by the main ISR. 1445 * It calls the dwmac dma routine and schedule poll method in case of some 1446 * work can be done. 1447 */ 1448 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1449 { 1450 int status; 1451 int rxfifosz = priv->plat->rx_fifo_size; 1452 1453 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1454 if (likely((status & handle_rx)) || (status & handle_tx)) { 1455 if (likely(napi_schedule_prep(&priv->napi))) { 1456 stmmac_disable_dma_irq(priv); 1457 __napi_schedule(&priv->napi); 1458 } 1459 } 1460 if (unlikely(status & tx_hard_error_bump_tc)) { 1461 /* Try to bump up the dma threshold on this failure */ 1462 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1463 (tc <= 256)) { 1464 tc += 64; 1465 if (priv->plat->force_thresh_dma_mode) 1466 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, 1467 rxfifosz); 1468 else 1469 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1470 SF_DMA_MODE, rxfifosz); 1471 priv->xstats.threshold = tc; 1472 } 1473 } else if (unlikely(status == tx_hard_error)) 1474 stmmac_tx_err(priv); 1475 } 1476 1477 /** 1478 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1479 * @priv: driver private structure 1480 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1481 */ 1482 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1483 { 1484 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1485 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1486 1487 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1488 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; 1489 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; 1490 } else { 1491 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; 1492 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; 1493 } 1494 1495 dwmac_mmc_intr_all_mask(priv->mmcaddr); 1496 1497 if (priv->dma_cap.rmon) { 1498 dwmac_mmc_ctrl(priv->mmcaddr, mode); 1499 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1500 } else 1501 netdev_info(priv->dev, "No MAC Management Counters available\n"); 1502 } 1503 1504 /** 1505 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1506 * @priv: driver private structure 1507 * Description: select the Enhanced/Alternate or Normal descriptors. 1508 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1509 * supported by the HW capability register. 1510 */ 1511 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1512 { 1513 if (priv->plat->enh_desc) { 1514 dev_info(priv->device, "Enhanced/Alternate descriptors\n"); 1515 1516 /* GMAC older than 3.50 has no extended descriptors */ 1517 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1518 dev_info(priv->device, "Enabled extended descriptors\n"); 1519 priv->extend_desc = 1; 1520 } else 1521 dev_warn(priv->device, "Extended descriptors not supported\n"); 1522 1523 priv->hw->desc = &enh_desc_ops; 1524 } else { 1525 dev_info(priv->device, "Normal descriptors\n"); 1526 priv->hw->desc = &ndesc_ops; 1527 } 1528 } 1529 1530 /** 1531 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1532 * @priv: driver private structure 1533 * Description: 1534 * new GMAC chip generations have a new register to indicate the 1535 * presence of the optional feature/functions. 1536 * This can be also used to override the value passed through the 1537 * platform and necessary for old MAC10/100 and GMAC chips. 1538 */ 1539 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1540 { 1541 u32 ret = 0; 1542 1543 if (priv->hw->dma->get_hw_feature) { 1544 priv->hw->dma->get_hw_feature(priv->ioaddr, 1545 &priv->dma_cap); 1546 ret = 1; 1547 } 1548 1549 return ret; 1550 } 1551 1552 /** 1553 * stmmac_check_ether_addr - check if the MAC addr is valid 1554 * @priv: driver private structure 1555 * Description: 1556 * it is to verify if the MAC address is valid, in case of failures it 1557 * generates a random MAC address 1558 */ 1559 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1560 { 1561 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1562 priv->hw->mac->get_umac_addr(priv->hw, 1563 priv->dev->dev_addr, 0); 1564 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1565 eth_hw_addr_random(priv->dev); 1566 netdev_info(priv->dev, "device MAC address %pM\n", 1567 priv->dev->dev_addr); 1568 } 1569 } 1570 1571 /** 1572 * stmmac_init_dma_engine - DMA init. 1573 * @priv: driver private structure 1574 * Description: 1575 * It inits the DMA invoking the specific MAC/GMAC callback. 1576 * Some DMA parameters can be passed from the platform; 1577 * in case of these are not passed a default is kept for the MAC or GMAC. 1578 */ 1579 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1580 { 1581 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0; 1582 int mixed_burst = 0; 1583 int atds = 0; 1584 int ret = 0; 1585 1586 if (priv->plat->dma_cfg) { 1587 pbl = priv->plat->dma_cfg->pbl; 1588 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1589 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1590 aal = priv->plat->dma_cfg->aal; 1591 } 1592 1593 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1594 atds = 1; 1595 1596 ret = priv->hw->dma->reset(priv->ioaddr); 1597 if (ret) { 1598 dev_err(priv->device, "Failed to reset the dma\n"); 1599 return ret; 1600 } 1601 1602 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1603 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds); 1604 1605 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1606 priv->rx_tail_addr = priv->dma_rx_phy + 1607 (DMA_RX_SIZE * sizeof(struct dma_desc)); 1608 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, 1609 STMMAC_CHAN0); 1610 1611 priv->tx_tail_addr = priv->dma_tx_phy + 1612 (DMA_TX_SIZE * sizeof(struct dma_desc)); 1613 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 1614 STMMAC_CHAN0); 1615 } 1616 1617 if (priv->plat->axi && priv->hw->dma->axi) 1618 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); 1619 1620 return ret; 1621 } 1622 1623 /** 1624 * stmmac_tx_timer - mitigation sw timer for tx. 1625 * @data: data pointer 1626 * Description: 1627 * This is the timer handler to directly invoke the stmmac_tx_clean. 1628 */ 1629 static void stmmac_tx_timer(unsigned long data) 1630 { 1631 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1632 1633 stmmac_tx_clean(priv); 1634 } 1635 1636 /** 1637 * stmmac_init_tx_coalesce - init tx mitigation options. 1638 * @priv: driver private structure 1639 * Description: 1640 * This inits the transmit coalesce parameters: i.e. timer rate, 1641 * timer handler and default threshold used for enabling the 1642 * interrupt on completion bit. 1643 */ 1644 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1645 { 1646 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1647 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1648 init_timer(&priv->txtimer); 1649 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1650 priv->txtimer.data = (unsigned long)priv; 1651 priv->txtimer.function = stmmac_tx_timer; 1652 add_timer(&priv->txtimer); 1653 } 1654 1655 /** 1656 * stmmac_hw_setup - setup mac in a usable state. 1657 * @dev : pointer to the device structure. 1658 * Description: 1659 * this is the main function to setup the HW in a usable state because the 1660 * dma engine is reset, the core registers are configured (e.g. AXI, 1661 * Checksum features, timers). The DMA is ready to start receiving and 1662 * transmitting. 1663 * Return value: 1664 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1665 * file on failure. 1666 */ 1667 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1668 { 1669 struct stmmac_priv *priv = netdev_priv(dev); 1670 int ret; 1671 1672 /* DMA initialization and SW reset */ 1673 ret = stmmac_init_dma_engine(priv); 1674 if (ret < 0) { 1675 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 1676 __func__); 1677 return ret; 1678 } 1679 1680 /* Copy the MAC addr into the HW */ 1681 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1682 1683 /* If required, perform hw setup of the bus. */ 1684 if (priv->plat->bus_setup) 1685 priv->plat->bus_setup(priv->ioaddr); 1686 1687 /* PS and related bits will be programmed according to the speed */ 1688 if (priv->hw->pcs) { 1689 int speed = priv->plat->mac_port_sel_speed; 1690 1691 if ((speed == SPEED_10) || (speed == SPEED_100) || 1692 (speed == SPEED_1000)) { 1693 priv->hw->ps = speed; 1694 } else { 1695 dev_warn(priv->device, "invalid port speed\n"); 1696 priv->hw->ps = 0; 1697 } 1698 } 1699 1700 /* Initialize the MAC Core */ 1701 priv->hw->mac->core_init(priv->hw, dev->mtu); 1702 1703 ret = priv->hw->mac->rx_ipc(priv->hw); 1704 if (!ret) { 1705 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 1706 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1707 priv->hw->rx_csum = 0; 1708 } 1709 1710 /* Enable the MAC Rx/Tx */ 1711 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1712 stmmac_dwmac4_set_mac(priv->ioaddr, true); 1713 else 1714 stmmac_set_mac(priv->ioaddr, true); 1715 1716 /* Set the HW DMA mode and the COE */ 1717 stmmac_dma_operation_mode(priv); 1718 1719 stmmac_mmc_setup(priv); 1720 1721 if (init_ptp) { 1722 ret = stmmac_init_ptp(priv); 1723 if (ret) 1724 netdev_warn(priv->dev, "fail to init PTP.\n"); 1725 } 1726 1727 #ifdef CONFIG_DEBUG_FS 1728 ret = stmmac_init_fs(dev); 1729 if (ret < 0) 1730 netdev_warn(priv->dev, "%s: failed debugFS registration\n", 1731 __func__); 1732 #endif 1733 /* Start the ball rolling... */ 1734 netdev_dbg(priv->dev, "DMA RX/TX processes started...\n"); 1735 priv->hw->dma->start_tx(priv->ioaddr); 1736 priv->hw->dma->start_rx(priv->ioaddr); 1737 1738 /* Dump DMA/MAC registers */ 1739 if (netif_msg_hw(priv)) { 1740 priv->hw->mac->dump_regs(priv->hw); 1741 priv->hw->dma->dump_regs(priv->ioaddr); 1742 } 1743 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1744 1745 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1746 priv->rx_riwt = MAX_DMA_RIWT; 1747 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1748 } 1749 1750 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) 1751 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); 1752 1753 /* set TX ring length */ 1754 if (priv->hw->dma->set_tx_ring_len) 1755 priv->hw->dma->set_tx_ring_len(priv->ioaddr, 1756 (DMA_TX_SIZE - 1)); 1757 /* set RX ring length */ 1758 if (priv->hw->dma->set_rx_ring_len) 1759 priv->hw->dma->set_rx_ring_len(priv->ioaddr, 1760 (DMA_RX_SIZE - 1)); 1761 /* Enable TSO */ 1762 if (priv->tso) 1763 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); 1764 1765 return 0; 1766 } 1767 1768 /** 1769 * stmmac_open - open entry point of the driver 1770 * @dev : pointer to the device structure. 1771 * Description: 1772 * This function is the open entry point of the driver. 1773 * Return value: 1774 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1775 * file on failure. 1776 */ 1777 static int stmmac_open(struct net_device *dev) 1778 { 1779 struct stmmac_priv *priv = netdev_priv(dev); 1780 int ret; 1781 1782 stmmac_check_ether_addr(priv); 1783 1784 if (priv->hw->pcs != STMMAC_PCS_RGMII && 1785 priv->hw->pcs != STMMAC_PCS_TBI && 1786 priv->hw->pcs != STMMAC_PCS_RTBI) { 1787 ret = stmmac_init_phy(dev); 1788 if (ret) { 1789 netdev_err(priv->dev, 1790 "%s: Cannot attach to PHY (error: %d)\n", 1791 __func__, ret); 1792 return ret; 1793 } 1794 } 1795 1796 /* Extra statistics */ 1797 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1798 priv->xstats.threshold = tc; 1799 1800 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1801 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 1802 1803 ret = alloc_dma_desc_resources(priv); 1804 if (ret < 0) { 1805 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 1806 __func__); 1807 goto dma_desc_error; 1808 } 1809 1810 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1811 if (ret < 0) { 1812 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 1813 __func__); 1814 goto init_error; 1815 } 1816 1817 ret = stmmac_hw_setup(dev, true); 1818 if (ret < 0) { 1819 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 1820 goto init_error; 1821 } 1822 1823 stmmac_init_tx_coalesce(priv); 1824 1825 if (dev->phydev) 1826 phy_start(dev->phydev); 1827 1828 /* Request the IRQ lines */ 1829 ret = request_irq(dev->irq, stmmac_interrupt, 1830 IRQF_SHARED, dev->name, dev); 1831 if (unlikely(ret < 0)) { 1832 netdev_err(priv->dev, 1833 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 1834 __func__, dev->irq, ret); 1835 goto init_error; 1836 } 1837 1838 /* Request the Wake IRQ in case of another line is used for WoL */ 1839 if (priv->wol_irq != dev->irq) { 1840 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1841 IRQF_SHARED, dev->name, dev); 1842 if (unlikely(ret < 0)) { 1843 netdev_err(priv->dev, 1844 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1845 __func__, priv->wol_irq, ret); 1846 goto wolirq_error; 1847 } 1848 } 1849 1850 /* Request the IRQ lines */ 1851 if (priv->lpi_irq > 0) { 1852 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1853 dev->name, dev); 1854 if (unlikely(ret < 0)) { 1855 netdev_err(priv->dev, 1856 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1857 __func__, priv->lpi_irq, ret); 1858 goto lpiirq_error; 1859 } 1860 } 1861 1862 napi_enable(&priv->napi); 1863 netif_start_queue(dev); 1864 1865 return 0; 1866 1867 lpiirq_error: 1868 if (priv->wol_irq != dev->irq) 1869 free_irq(priv->wol_irq, dev); 1870 wolirq_error: 1871 free_irq(dev->irq, dev); 1872 1873 init_error: 1874 free_dma_desc_resources(priv); 1875 dma_desc_error: 1876 if (dev->phydev) 1877 phy_disconnect(dev->phydev); 1878 1879 return ret; 1880 } 1881 1882 /** 1883 * stmmac_release - close entry point of the driver 1884 * @dev : device pointer. 1885 * Description: 1886 * This is the stop entry point of the driver. 1887 */ 1888 static int stmmac_release(struct net_device *dev) 1889 { 1890 struct stmmac_priv *priv = netdev_priv(dev); 1891 1892 if (priv->eee_enabled) 1893 del_timer_sync(&priv->eee_ctrl_timer); 1894 1895 /* Stop and disconnect the PHY */ 1896 if (dev->phydev) { 1897 phy_stop(dev->phydev); 1898 phy_disconnect(dev->phydev); 1899 } 1900 1901 netif_stop_queue(dev); 1902 1903 napi_disable(&priv->napi); 1904 1905 del_timer_sync(&priv->txtimer); 1906 1907 /* Free the IRQ lines */ 1908 free_irq(dev->irq, dev); 1909 if (priv->wol_irq != dev->irq) 1910 free_irq(priv->wol_irq, dev); 1911 if (priv->lpi_irq > 0) 1912 free_irq(priv->lpi_irq, dev); 1913 1914 /* Stop TX/RX DMA and clear the descriptors */ 1915 priv->hw->dma->stop_tx(priv->ioaddr); 1916 priv->hw->dma->stop_rx(priv->ioaddr); 1917 1918 /* Release and free the Rx/Tx resources */ 1919 free_dma_desc_resources(priv); 1920 1921 /* Disable the MAC Rx/Tx */ 1922 stmmac_set_mac(priv->ioaddr, false); 1923 1924 netif_carrier_off(dev); 1925 1926 #ifdef CONFIG_DEBUG_FS 1927 stmmac_exit_fs(dev); 1928 #endif 1929 1930 stmmac_release_ptp(priv); 1931 1932 return 0; 1933 } 1934 1935 /** 1936 * stmmac_tso_allocator - close entry point of the driver 1937 * @priv: driver private structure 1938 * @des: buffer start address 1939 * @total_len: total length to fill in descriptors 1940 * @last_segmant: condition for the last descriptor 1941 * Description: 1942 * This function fills descriptor and request new descriptors according to 1943 * buffer length to fill 1944 */ 1945 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, 1946 int total_len, bool last_segment) 1947 { 1948 struct dma_desc *desc; 1949 int tmp_len; 1950 u32 buff_size; 1951 1952 tmp_len = total_len; 1953 1954 while (tmp_len > 0) { 1955 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 1956 desc = priv->dma_tx + priv->cur_tx; 1957 1958 desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); 1959 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 1960 TSO_MAX_BUFF_SIZE : tmp_len; 1961 1962 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, 1963 0, 1, 1964 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), 1965 0, 0); 1966 1967 tmp_len -= TSO_MAX_BUFF_SIZE; 1968 } 1969 } 1970 1971 /** 1972 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 1973 * @skb : the socket buffer 1974 * @dev : device pointer 1975 * Description: this is the transmit function that is called on TSO frames 1976 * (support available on GMAC4 and newer chips). 1977 * Diagram below show the ring programming in case of TSO frames: 1978 * 1979 * First Descriptor 1980 * -------- 1981 * | DES0 |---> buffer1 = L2/L3/L4 header 1982 * | DES1 |---> TCP Payload (can continue on next descr...) 1983 * | DES2 |---> buffer 1 and 2 len 1984 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 1985 * -------- 1986 * | 1987 * ... 1988 * | 1989 * -------- 1990 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 1991 * | DES1 | --| 1992 * | DES2 | --> buffer 1 and 2 len 1993 * | DES3 | 1994 * -------- 1995 * 1996 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 1997 */ 1998 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 1999 { 2000 u32 pay_len, mss; 2001 int tmp_pay_len = 0; 2002 struct stmmac_priv *priv = netdev_priv(dev); 2003 int nfrags = skb_shinfo(skb)->nr_frags; 2004 unsigned int first_entry, des; 2005 struct dma_desc *desc, *first, *mss_desc = NULL; 2006 u8 proto_hdr_len; 2007 int i; 2008 2009 spin_lock(&priv->tx_lock); 2010 2011 /* Compute header lengths */ 2012 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2013 2014 /* Desc availability based on threshold should be enough safe */ 2015 if (unlikely(stmmac_tx_avail(priv) < 2016 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2017 if (!netif_queue_stopped(dev)) { 2018 netif_stop_queue(dev); 2019 /* This is a hard error, log it. */ 2020 netdev_err(priv->dev, 2021 "%s: Tx Ring full when queue awake\n", 2022 __func__); 2023 } 2024 spin_unlock(&priv->tx_lock); 2025 return NETDEV_TX_BUSY; 2026 } 2027 2028 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2029 2030 mss = skb_shinfo(skb)->gso_size; 2031 2032 /* set new MSS value if needed */ 2033 if (mss != priv->mss) { 2034 mss_desc = priv->dma_tx + priv->cur_tx; 2035 priv->hw->desc->set_mss(mss_desc, mss); 2036 priv->mss = mss; 2037 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2038 } 2039 2040 if (netif_msg_tx_queued(priv)) { 2041 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2042 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2043 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2044 skb->data_len); 2045 } 2046 2047 first_entry = priv->cur_tx; 2048 2049 desc = priv->dma_tx + first_entry; 2050 first = desc; 2051 2052 /* first descriptor: fill Headers on Buf1 */ 2053 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2054 DMA_TO_DEVICE); 2055 if (dma_mapping_error(priv->device, des)) 2056 goto dma_map_err; 2057 2058 priv->tx_skbuff_dma[first_entry].buf = des; 2059 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2060 priv->tx_skbuff[first_entry] = skb; 2061 2062 first->des0 = cpu_to_le32(des); 2063 2064 /* Fill start of payload in buff2 of first descriptor */ 2065 if (pay_len) 2066 first->des1 = cpu_to_le32(des + proto_hdr_len); 2067 2068 /* If needed take extra descriptors to fill the remaining payload */ 2069 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2070 2071 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); 2072 2073 /* Prepare fragments */ 2074 for (i = 0; i < nfrags; i++) { 2075 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2076 2077 des = skb_frag_dma_map(priv->device, frag, 0, 2078 skb_frag_size(frag), 2079 DMA_TO_DEVICE); 2080 2081 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2082 (i == nfrags - 1)); 2083 2084 priv->tx_skbuff_dma[priv->cur_tx].buf = des; 2085 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); 2086 priv->tx_skbuff[priv->cur_tx] = NULL; 2087 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; 2088 } 2089 2090 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; 2091 2092 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2093 2094 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2095 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2096 __func__); 2097 netif_stop_queue(dev); 2098 } 2099 2100 dev->stats.tx_bytes += skb->len; 2101 priv->xstats.tx_tso_frames++; 2102 priv->xstats.tx_tso_nfrags += nfrags; 2103 2104 /* Manage tx mitigation */ 2105 priv->tx_count_frames += nfrags + 1; 2106 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2107 mod_timer(&priv->txtimer, 2108 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2109 } else { 2110 priv->tx_count_frames = 0; 2111 priv->hw->desc->set_tx_ic(desc); 2112 priv->xstats.tx_set_ic_bit++; 2113 } 2114 2115 if (!priv->hwts_tx_en) 2116 skb_tx_timestamp(skb); 2117 2118 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2119 priv->hwts_tx_en)) { 2120 /* declare that device is doing timestamping */ 2121 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2122 priv->hw->desc->enable_tx_timestamp(first); 2123 } 2124 2125 /* Complete the first descriptor before granting the DMA */ 2126 priv->hw->desc->prepare_tso_tx_desc(first, 1, 2127 proto_hdr_len, 2128 pay_len, 2129 1, priv->tx_skbuff_dma[first_entry].last_segment, 2130 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2131 2132 /* If context desc is used to change MSS */ 2133 if (mss_desc) 2134 priv->hw->desc->set_tx_owner(mss_desc); 2135 2136 /* The own bit must be the latest setting done when prepare the 2137 * descriptor and then barrier is needed to make sure that 2138 * all is coherent before granting the DMA engine. 2139 */ 2140 smp_wmb(); 2141 2142 if (netif_msg_pktdata(priv)) { 2143 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 2144 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2145 priv->cur_tx, first, nfrags); 2146 2147 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 2148 0); 2149 2150 pr_info(">>> frame to be transmitted: "); 2151 print_pkt(skb->data, skb_headlen(skb)); 2152 } 2153 2154 netdev_sent_queue(dev, skb->len); 2155 2156 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2157 STMMAC_CHAN0); 2158 2159 spin_unlock(&priv->tx_lock); 2160 return NETDEV_TX_OK; 2161 2162 dma_map_err: 2163 spin_unlock(&priv->tx_lock); 2164 dev_err(priv->device, "Tx dma map failed\n"); 2165 dev_kfree_skb(skb); 2166 priv->dev->stats.tx_dropped++; 2167 return NETDEV_TX_OK; 2168 } 2169 2170 /** 2171 * stmmac_xmit - Tx entry point of the driver 2172 * @skb : the socket buffer 2173 * @dev : device pointer 2174 * Description : this is the tx entry point of the driver. 2175 * It programs the chain or the ring and supports oversized frames 2176 * and SG feature. 2177 */ 2178 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 2179 { 2180 struct stmmac_priv *priv = netdev_priv(dev); 2181 unsigned int nopaged_len = skb_headlen(skb); 2182 int i, csum_insertion = 0, is_jumbo = 0; 2183 int nfrags = skb_shinfo(skb)->nr_frags; 2184 unsigned int entry, first_entry; 2185 struct dma_desc *desc, *first; 2186 unsigned int enh_desc; 2187 unsigned int des; 2188 2189 /* Manage oversized TCP frames for GMAC4 device */ 2190 if (skb_is_gso(skb) && priv->tso) { 2191 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 2192 return stmmac_tso_xmit(skb, dev); 2193 } 2194 2195 spin_lock(&priv->tx_lock); 2196 2197 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 2198 spin_unlock(&priv->tx_lock); 2199 if (!netif_queue_stopped(dev)) { 2200 netif_stop_queue(dev); 2201 /* This is a hard error, log it. */ 2202 netdev_err(priv->dev, 2203 "%s: Tx Ring full when queue awake\n", 2204 __func__); 2205 } 2206 return NETDEV_TX_BUSY; 2207 } 2208 2209 if (priv->tx_path_in_lpi_mode) 2210 stmmac_disable_eee_mode(priv); 2211 2212 entry = priv->cur_tx; 2213 first_entry = entry; 2214 2215 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 2216 2217 if (likely(priv->extend_desc)) 2218 desc = (struct dma_desc *)(priv->dma_etx + entry); 2219 else 2220 desc = priv->dma_tx + entry; 2221 2222 first = desc; 2223 2224 priv->tx_skbuff[first_entry] = skb; 2225 2226 enh_desc = priv->plat->enh_desc; 2227 /* To program the descriptors according to the size of the frame */ 2228 if (enh_desc) 2229 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 2230 2231 if (unlikely(is_jumbo) && likely(priv->synopsys_id < 2232 DWMAC_CORE_4_00)) { 2233 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 2234 if (unlikely(entry < 0)) 2235 goto dma_map_err; 2236 } 2237 2238 for (i = 0; i < nfrags; i++) { 2239 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2240 int len = skb_frag_size(frag); 2241 bool last_segment = (i == (nfrags - 1)); 2242 2243 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2244 2245 if (likely(priv->extend_desc)) 2246 desc = (struct dma_desc *)(priv->dma_etx + entry); 2247 else 2248 desc = priv->dma_tx + entry; 2249 2250 des = skb_frag_dma_map(priv->device, frag, 0, len, 2251 DMA_TO_DEVICE); 2252 if (dma_mapping_error(priv->device, des)) 2253 goto dma_map_err; /* should reuse desc w/o issues */ 2254 2255 priv->tx_skbuff[entry] = NULL; 2256 2257 priv->tx_skbuff_dma[entry].buf = des; 2258 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2259 desc->des0 = cpu_to_le32(des); 2260 else 2261 desc->des2 = cpu_to_le32(des); 2262 2263 priv->tx_skbuff_dma[entry].map_as_page = true; 2264 priv->tx_skbuff_dma[entry].len = len; 2265 priv->tx_skbuff_dma[entry].last_segment = last_segment; 2266 2267 /* Prepare the descriptor and set the own bit too */ 2268 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2269 priv->mode, 1, last_segment); 2270 } 2271 2272 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2273 2274 priv->cur_tx = entry; 2275 2276 if (netif_msg_pktdata(priv)) { 2277 void *tx_head; 2278 2279 netdev_dbg(priv->dev, 2280 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 2281 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2282 entry, first, nfrags); 2283 2284 if (priv->extend_desc) 2285 tx_head = (void *)priv->dma_etx; 2286 else 2287 tx_head = (void *)priv->dma_tx; 2288 2289 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); 2290 2291 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 2292 print_pkt(skb->data, skb->len); 2293 } 2294 2295 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2296 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2297 __func__); 2298 netif_stop_queue(dev); 2299 } 2300 2301 dev->stats.tx_bytes += skb->len; 2302 2303 /* According to the coalesce parameter the IC bit for the latest 2304 * segment is reset and the timer re-started to clean the tx status. 2305 * This approach takes care about the fragments: desc is the first 2306 * element in case of no SG. 2307 */ 2308 priv->tx_count_frames += nfrags + 1; 2309 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2310 mod_timer(&priv->txtimer, 2311 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2312 } else { 2313 priv->tx_count_frames = 0; 2314 priv->hw->desc->set_tx_ic(desc); 2315 priv->xstats.tx_set_ic_bit++; 2316 } 2317 2318 if (!priv->hwts_tx_en) 2319 skb_tx_timestamp(skb); 2320 2321 /* Ready to fill the first descriptor and set the OWN bit w/o any 2322 * problems because all the descriptors are actually ready to be 2323 * passed to the DMA engine. 2324 */ 2325 if (likely(!is_jumbo)) { 2326 bool last_segment = (nfrags == 0); 2327 2328 des = dma_map_single(priv->device, skb->data, 2329 nopaged_len, DMA_TO_DEVICE); 2330 if (dma_mapping_error(priv->device, des)) 2331 goto dma_map_err; 2332 2333 priv->tx_skbuff_dma[first_entry].buf = des; 2334 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2335 first->des0 = cpu_to_le32(des); 2336 else 2337 first->des2 = cpu_to_le32(des); 2338 2339 priv->tx_skbuff_dma[first_entry].len = nopaged_len; 2340 priv->tx_skbuff_dma[first_entry].last_segment = last_segment; 2341 2342 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2343 priv->hwts_tx_en)) { 2344 /* declare that device is doing timestamping */ 2345 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2346 priv->hw->desc->enable_tx_timestamp(first); 2347 } 2348 2349 /* Prepare the first descriptor setting the OWN bit too */ 2350 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, 2351 csum_insertion, priv->mode, 1, 2352 last_segment); 2353 2354 /* The own bit must be the latest setting done when prepare the 2355 * descriptor and then barrier is needed to make sure that 2356 * all is coherent before granting the DMA engine. 2357 */ 2358 smp_wmb(); 2359 } 2360 2361 netdev_sent_queue(dev, skb->len); 2362 2363 if (priv->synopsys_id < DWMAC_CORE_4_00) 2364 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2365 else 2366 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2367 STMMAC_CHAN0); 2368 2369 spin_unlock(&priv->tx_lock); 2370 return NETDEV_TX_OK; 2371 2372 dma_map_err: 2373 spin_unlock(&priv->tx_lock); 2374 netdev_err(priv->dev, "Tx DMA map failed\n"); 2375 dev_kfree_skb(skb); 2376 priv->dev->stats.tx_dropped++; 2377 return NETDEV_TX_OK; 2378 } 2379 2380 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2381 { 2382 struct ethhdr *ehdr; 2383 u16 vlanid; 2384 2385 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2386 NETIF_F_HW_VLAN_CTAG_RX && 2387 !__vlan_get_tag(skb, &vlanid)) { 2388 /* pop the vlan tag */ 2389 ehdr = (struct ethhdr *)skb->data; 2390 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2391 skb_pull(skb, VLAN_HLEN); 2392 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2393 } 2394 } 2395 2396 2397 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) 2398 { 2399 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) 2400 return 0; 2401 2402 return 1; 2403 } 2404 2405 /** 2406 * stmmac_rx_refill - refill used skb preallocated buffers 2407 * @priv: driver private structure 2408 * Description : this is to reallocate the skb for the reception process 2409 * that is based on zero-copy. 2410 */ 2411 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2412 { 2413 int bfsize = priv->dma_buf_sz; 2414 unsigned int entry = priv->dirty_rx; 2415 int dirty = stmmac_rx_dirty(priv); 2416 2417 while (dirty-- > 0) { 2418 struct dma_desc *p; 2419 2420 if (priv->extend_desc) 2421 p = (struct dma_desc *)(priv->dma_erx + entry); 2422 else 2423 p = priv->dma_rx + entry; 2424 2425 if (likely(priv->rx_skbuff[entry] == NULL)) { 2426 struct sk_buff *skb; 2427 2428 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2429 if (unlikely(!skb)) { 2430 /* so for a while no zero-copy! */ 2431 priv->rx_zeroc_thresh = STMMAC_RX_THRESH; 2432 if (unlikely(net_ratelimit())) 2433 dev_err(priv->device, 2434 "fail to alloc skb entry %d\n", 2435 entry); 2436 break; 2437 } 2438 2439 priv->rx_skbuff[entry] = skb; 2440 priv->rx_skbuff_dma[entry] = 2441 dma_map_single(priv->device, skb->data, bfsize, 2442 DMA_FROM_DEVICE); 2443 if (dma_mapping_error(priv->device, 2444 priv->rx_skbuff_dma[entry])) { 2445 netdev_err(priv->dev, "Rx DMA map failed\n"); 2446 dev_kfree_skb(skb); 2447 break; 2448 } 2449 2450 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2451 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]); 2452 p->des1 = 0; 2453 } else { 2454 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]); 2455 } 2456 if (priv->hw->mode->refill_desc3) 2457 priv->hw->mode->refill_desc3(priv, p); 2458 2459 if (priv->rx_zeroc_thresh > 0) 2460 priv->rx_zeroc_thresh--; 2461 2462 netif_dbg(priv, rx_status, priv->dev, 2463 "refill entry #%d\n", entry); 2464 } 2465 wmb(); 2466 2467 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2468 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); 2469 else 2470 priv->hw->desc->set_rx_owner(p); 2471 2472 wmb(); 2473 2474 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 2475 } 2476 priv->dirty_rx = entry; 2477 } 2478 2479 /** 2480 * stmmac_rx - manage the receive process 2481 * @priv: driver private structure 2482 * @limit: napi bugget. 2483 * Description : this the function called by the napi poll method. 2484 * It gets all the frames inside the ring. 2485 */ 2486 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2487 { 2488 unsigned int entry = priv->cur_rx; 2489 unsigned int next_entry; 2490 unsigned int count = 0; 2491 int coe = priv->hw->rx_csum; 2492 2493 if (netif_msg_rx_status(priv)) { 2494 void *rx_head; 2495 2496 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 2497 if (priv->extend_desc) 2498 rx_head = (void *)priv->dma_erx; 2499 else 2500 rx_head = (void *)priv->dma_rx; 2501 2502 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); 2503 } 2504 while (count < limit) { 2505 int status; 2506 struct dma_desc *p; 2507 struct dma_desc *np; 2508 2509 if (priv->extend_desc) 2510 p = (struct dma_desc *)(priv->dma_erx + entry); 2511 else 2512 p = priv->dma_rx + entry; 2513 2514 /* read the status of the incoming frame */ 2515 status = priv->hw->desc->rx_status(&priv->dev->stats, 2516 &priv->xstats, p); 2517 /* check if managed by the DMA otherwise go ahead */ 2518 if (unlikely(status & dma_own)) 2519 break; 2520 2521 count++; 2522 2523 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); 2524 next_entry = priv->cur_rx; 2525 2526 if (priv->extend_desc) 2527 np = (struct dma_desc *)(priv->dma_erx + next_entry); 2528 else 2529 np = priv->dma_rx + next_entry; 2530 2531 prefetch(np); 2532 2533 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2534 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2535 &priv->xstats, 2536 priv->dma_erx + 2537 entry); 2538 if (unlikely(status == discard_frame)) { 2539 priv->dev->stats.rx_errors++; 2540 if (priv->hwts_rx_en && !priv->extend_desc) { 2541 /* DESC2 & DESC3 will be overwitten by device 2542 * with timestamp value, hence reinitialize 2543 * them in stmmac_rx_refill() function so that 2544 * device can reuse it. 2545 */ 2546 priv->rx_skbuff[entry] = NULL; 2547 dma_unmap_single(priv->device, 2548 priv->rx_skbuff_dma[entry], 2549 priv->dma_buf_sz, 2550 DMA_FROM_DEVICE); 2551 } 2552 } else { 2553 struct sk_buff *skb; 2554 int frame_len; 2555 unsigned int des; 2556 2557 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2558 des = le32_to_cpu(p->des0); 2559 else 2560 des = le32_to_cpu(p->des2); 2561 2562 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2563 2564 /* If frame length is greather than skb buffer size 2565 * (preallocated during init) then the packet is 2566 * ignored 2567 */ 2568 if (frame_len > priv->dma_buf_sz) { 2569 netdev_err(priv->dev, 2570 "len %d larger than size (%d)\n", 2571 frame_len, priv->dma_buf_sz); 2572 priv->dev->stats.rx_length_errors++; 2573 break; 2574 } 2575 2576 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2577 * Type frames (LLC/LLC-SNAP) 2578 */ 2579 if (unlikely(status != llc_snap)) 2580 frame_len -= ETH_FCS_LEN; 2581 2582 if (netif_msg_rx_status(priv)) { 2583 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", 2584 p, entry, des); 2585 if (frame_len > ETH_FRAME_LEN) 2586 netdev_dbg(priv->dev, "frame size %d, COE: %d\n", 2587 frame_len, status); 2588 } 2589 2590 /* The zero-copy is always used for all the sizes 2591 * in case of GMAC4 because it needs 2592 * to refill the used descriptors, always. 2593 */ 2594 if (unlikely(!priv->plat->has_gmac4 && 2595 ((frame_len < priv->rx_copybreak) || 2596 stmmac_rx_threshold_count(priv)))) { 2597 skb = netdev_alloc_skb_ip_align(priv->dev, 2598 frame_len); 2599 if (unlikely(!skb)) { 2600 if (net_ratelimit()) 2601 dev_warn(priv->device, 2602 "packet dropped\n"); 2603 priv->dev->stats.rx_dropped++; 2604 break; 2605 } 2606 2607 dma_sync_single_for_cpu(priv->device, 2608 priv->rx_skbuff_dma 2609 [entry], frame_len, 2610 DMA_FROM_DEVICE); 2611 skb_copy_to_linear_data(skb, 2612 priv-> 2613 rx_skbuff[entry]->data, 2614 frame_len); 2615 2616 skb_put(skb, frame_len); 2617 dma_sync_single_for_device(priv->device, 2618 priv->rx_skbuff_dma 2619 [entry], frame_len, 2620 DMA_FROM_DEVICE); 2621 } else { 2622 skb = priv->rx_skbuff[entry]; 2623 if (unlikely(!skb)) { 2624 netdev_err(priv->dev, 2625 "%s: Inconsistent Rx chain\n", 2626 priv->dev->name); 2627 priv->dev->stats.rx_dropped++; 2628 break; 2629 } 2630 prefetch(skb->data - NET_IP_ALIGN); 2631 priv->rx_skbuff[entry] = NULL; 2632 priv->rx_zeroc_thresh++; 2633 2634 skb_put(skb, frame_len); 2635 dma_unmap_single(priv->device, 2636 priv->rx_skbuff_dma[entry], 2637 priv->dma_buf_sz, 2638 DMA_FROM_DEVICE); 2639 } 2640 2641 if (netif_msg_pktdata(priv)) { 2642 netdev_dbg(priv->dev, "frame received (%dbytes)", 2643 frame_len); 2644 print_pkt(skb->data, frame_len); 2645 } 2646 2647 stmmac_get_rx_hwtstamp(priv, p, np, skb); 2648 2649 stmmac_rx_vlan(priv->dev, skb); 2650 2651 skb->protocol = eth_type_trans(skb, priv->dev); 2652 2653 if (unlikely(!coe)) 2654 skb_checksum_none_assert(skb); 2655 else 2656 skb->ip_summed = CHECKSUM_UNNECESSARY; 2657 2658 napi_gro_receive(&priv->napi, skb); 2659 2660 priv->dev->stats.rx_packets++; 2661 priv->dev->stats.rx_bytes += frame_len; 2662 } 2663 entry = next_entry; 2664 } 2665 2666 stmmac_rx_refill(priv); 2667 2668 priv->xstats.rx_pkt_n += count; 2669 2670 return count; 2671 } 2672 2673 /** 2674 * stmmac_poll - stmmac poll method (NAPI) 2675 * @napi : pointer to the napi structure. 2676 * @budget : maximum number of packets that the current CPU can receive from 2677 * all interfaces. 2678 * Description : 2679 * To look at the incoming frames and clear the tx resources. 2680 */ 2681 static int stmmac_poll(struct napi_struct *napi, int budget) 2682 { 2683 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2684 int work_done = 0; 2685 2686 priv->xstats.napi_poll++; 2687 stmmac_tx_clean(priv); 2688 2689 work_done = stmmac_rx(priv, budget); 2690 if (work_done < budget) { 2691 napi_complete(napi); 2692 stmmac_enable_dma_irq(priv); 2693 } 2694 return work_done; 2695 } 2696 2697 /** 2698 * stmmac_tx_timeout 2699 * @dev : Pointer to net device structure 2700 * Description: this function is called when a packet transmission fails to 2701 * complete within a reasonable time. The driver will mark the error in the 2702 * netdev structure and arrange for the device to be reset to a sane state 2703 * in order to transmit a new packet. 2704 */ 2705 static void stmmac_tx_timeout(struct net_device *dev) 2706 { 2707 struct stmmac_priv *priv = netdev_priv(dev); 2708 2709 /* Clear Tx resources and restart transmitting again */ 2710 stmmac_tx_err(priv); 2711 } 2712 2713 /** 2714 * stmmac_set_rx_mode - entry point for multicast addressing 2715 * @dev : pointer to the device structure 2716 * Description: 2717 * This function is a driver entry point which gets called by the kernel 2718 * whenever multicast addresses must be enabled/disabled. 2719 * Return value: 2720 * void. 2721 */ 2722 static void stmmac_set_rx_mode(struct net_device *dev) 2723 { 2724 struct stmmac_priv *priv = netdev_priv(dev); 2725 2726 priv->hw->mac->set_filter(priv->hw, dev); 2727 } 2728 2729 /** 2730 * stmmac_change_mtu - entry point to change MTU size for the device. 2731 * @dev : device pointer. 2732 * @new_mtu : the new MTU size for the device. 2733 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2734 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2735 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2736 * Return value: 2737 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2738 * file on failure. 2739 */ 2740 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2741 { 2742 struct stmmac_priv *priv = netdev_priv(dev); 2743 2744 if (netif_running(dev)) { 2745 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 2746 return -EBUSY; 2747 } 2748 2749 dev->mtu = new_mtu; 2750 2751 netdev_update_features(dev); 2752 2753 return 0; 2754 } 2755 2756 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2757 netdev_features_t features) 2758 { 2759 struct stmmac_priv *priv = netdev_priv(dev); 2760 2761 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2762 features &= ~NETIF_F_RXCSUM; 2763 2764 if (!priv->plat->tx_coe) 2765 features &= ~NETIF_F_CSUM_MASK; 2766 2767 /* Some GMAC devices have a bugged Jumbo frame support that 2768 * needs to have the Tx COE disabled for oversized frames 2769 * (due to limited buffer sizes). In this case we disable 2770 * the TX csum insertionin the TDES and not use SF. 2771 */ 2772 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2773 features &= ~NETIF_F_CSUM_MASK; 2774 2775 /* Disable tso if asked by ethtool */ 2776 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 2777 if (features & NETIF_F_TSO) 2778 priv->tso = true; 2779 else 2780 priv->tso = false; 2781 } 2782 2783 return features; 2784 } 2785 2786 static int stmmac_set_features(struct net_device *netdev, 2787 netdev_features_t features) 2788 { 2789 struct stmmac_priv *priv = netdev_priv(netdev); 2790 2791 /* Keep the COE Type in case of csum is supporting */ 2792 if (features & NETIF_F_RXCSUM) 2793 priv->hw->rx_csum = priv->plat->rx_coe; 2794 else 2795 priv->hw->rx_csum = 0; 2796 /* No check needed because rx_coe has been set before and it will be 2797 * fixed in case of issue. 2798 */ 2799 priv->hw->mac->rx_ipc(priv->hw); 2800 2801 return 0; 2802 } 2803 2804 /** 2805 * stmmac_interrupt - main ISR 2806 * @irq: interrupt number. 2807 * @dev_id: to pass the net device pointer. 2808 * Description: this is the main driver interrupt service routine. 2809 * It can call: 2810 * o DMA service routine (to manage incoming frame reception and transmission 2811 * status) 2812 * o Core interrupts to manage: remote wake-up, management counter, LPI 2813 * interrupts. 2814 */ 2815 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2816 { 2817 struct net_device *dev = (struct net_device *)dev_id; 2818 struct stmmac_priv *priv = netdev_priv(dev); 2819 2820 if (priv->irq_wake) 2821 pm_wakeup_event(priv->device, 0); 2822 2823 if (unlikely(!dev)) { 2824 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 2825 return IRQ_NONE; 2826 } 2827 2828 /* To handle GMAC own interrupts */ 2829 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { 2830 int status = priv->hw->mac->host_irq_status(priv->hw, 2831 &priv->xstats); 2832 if (unlikely(status)) { 2833 /* For LPI we need to save the tx status */ 2834 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2835 priv->tx_path_in_lpi_mode = true; 2836 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2837 priv->tx_path_in_lpi_mode = false; 2838 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) 2839 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, 2840 priv->rx_tail_addr, 2841 STMMAC_CHAN0); 2842 } 2843 2844 /* PCS link status */ 2845 if (priv->hw->pcs) { 2846 if (priv->xstats.pcs_link) 2847 netif_carrier_on(dev); 2848 else 2849 netif_carrier_off(dev); 2850 } 2851 } 2852 2853 /* To handle DMA interrupts */ 2854 stmmac_dma_interrupt(priv); 2855 2856 return IRQ_HANDLED; 2857 } 2858 2859 #ifdef CONFIG_NET_POLL_CONTROLLER 2860 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2861 * to allow network I/O with interrupts disabled. 2862 */ 2863 static void stmmac_poll_controller(struct net_device *dev) 2864 { 2865 disable_irq(dev->irq); 2866 stmmac_interrupt(dev->irq, dev); 2867 enable_irq(dev->irq); 2868 } 2869 #endif 2870 2871 /** 2872 * stmmac_ioctl - Entry point for the Ioctl 2873 * @dev: Device pointer. 2874 * @rq: An IOCTL specefic structure, that can contain a pointer to 2875 * a proprietary structure used to pass information to the driver. 2876 * @cmd: IOCTL command 2877 * Description: 2878 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2879 */ 2880 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2881 { 2882 int ret = -EOPNOTSUPP; 2883 2884 if (!netif_running(dev)) 2885 return -EINVAL; 2886 2887 switch (cmd) { 2888 case SIOCGMIIPHY: 2889 case SIOCGMIIREG: 2890 case SIOCSMIIREG: 2891 if (!dev->phydev) 2892 return -EINVAL; 2893 ret = phy_mii_ioctl(dev->phydev, rq, cmd); 2894 break; 2895 case SIOCSHWTSTAMP: 2896 ret = stmmac_hwtstamp_ioctl(dev, rq); 2897 break; 2898 default: 2899 break; 2900 } 2901 2902 return ret; 2903 } 2904 2905 #ifdef CONFIG_DEBUG_FS 2906 static struct dentry *stmmac_fs_dir; 2907 2908 static void sysfs_display_ring(void *head, int size, int extend_desc, 2909 struct seq_file *seq) 2910 { 2911 int i; 2912 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2913 struct dma_desc *p = (struct dma_desc *)head; 2914 2915 for (i = 0; i < size; i++) { 2916 u64 x; 2917 if (extend_desc) { 2918 x = *(u64 *) ep; 2919 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2920 i, (unsigned int)virt_to_phys(ep), 2921 le32_to_cpu(ep->basic.des0), 2922 le32_to_cpu(ep->basic.des1), 2923 le32_to_cpu(ep->basic.des2), 2924 le32_to_cpu(ep->basic.des3)); 2925 ep++; 2926 } else { 2927 x = *(u64 *) p; 2928 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2929 i, (unsigned int)virt_to_phys(ep), 2930 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 2931 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 2932 p++; 2933 } 2934 seq_printf(seq, "\n"); 2935 } 2936 } 2937 2938 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2939 { 2940 struct net_device *dev = seq->private; 2941 struct stmmac_priv *priv = netdev_priv(dev); 2942 2943 if (priv->extend_desc) { 2944 seq_printf(seq, "Extended RX descriptor ring:\n"); 2945 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); 2946 seq_printf(seq, "Extended TX descriptor ring:\n"); 2947 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); 2948 } else { 2949 seq_printf(seq, "RX descriptor ring:\n"); 2950 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); 2951 seq_printf(seq, "TX descriptor ring:\n"); 2952 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); 2953 } 2954 2955 return 0; 2956 } 2957 2958 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2959 { 2960 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2961 } 2962 2963 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */ 2964 2965 static const struct file_operations stmmac_rings_status_fops = { 2966 .owner = THIS_MODULE, 2967 .open = stmmac_sysfs_ring_open, 2968 .read = seq_read, 2969 .llseek = seq_lseek, 2970 .release = single_release, 2971 }; 2972 2973 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2974 { 2975 struct net_device *dev = seq->private; 2976 struct stmmac_priv *priv = netdev_priv(dev); 2977 2978 if (!priv->hw_cap_support) { 2979 seq_printf(seq, "DMA HW features not supported\n"); 2980 return 0; 2981 } 2982 2983 seq_printf(seq, "==============================\n"); 2984 seq_printf(seq, "\tDMA HW features\n"); 2985 seq_printf(seq, "==============================\n"); 2986 2987 seq_printf(seq, "\t10/100 Mbps: %s\n", 2988 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2989 seq_printf(seq, "\t1000 Mbps: %s\n", 2990 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2991 seq_printf(seq, "\tHalf duplex: %s\n", 2992 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2993 seq_printf(seq, "\tHash Filter: %s\n", 2994 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2995 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2996 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2997 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2998 (priv->dma_cap.pcs) ? "Y" : "N"); 2999 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 3000 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 3001 seq_printf(seq, "\tPMT Remote wake up: %s\n", 3002 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 3003 seq_printf(seq, "\tPMT Magic Frame: %s\n", 3004 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 3005 seq_printf(seq, "\tRMON module: %s\n", 3006 (priv->dma_cap.rmon) ? "Y" : "N"); 3007 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 3008 (priv->dma_cap.time_stamp) ? "Y" : "N"); 3009 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 3010 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 3011 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 3012 (priv->dma_cap.eee) ? "Y" : "N"); 3013 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 3014 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3015 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3016 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3017 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3018 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3019 } else { 3020 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3021 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3022 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3023 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3024 } 3025 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3026 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3027 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3028 priv->dma_cap.number_rx_channel); 3029 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3030 priv->dma_cap.number_tx_channel); 3031 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3032 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3033 3034 return 0; 3035 } 3036 3037 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 3038 { 3039 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 3040 } 3041 3042 static const struct file_operations stmmac_dma_cap_fops = { 3043 .owner = THIS_MODULE, 3044 .open = stmmac_sysfs_dma_cap_open, 3045 .read = seq_read, 3046 .llseek = seq_lseek, 3047 .release = single_release, 3048 }; 3049 3050 static int stmmac_init_fs(struct net_device *dev) 3051 { 3052 struct stmmac_priv *priv = netdev_priv(dev); 3053 3054 /* Create per netdev entries */ 3055 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3056 3057 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3058 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); 3059 3060 return -ENOMEM; 3061 } 3062 3063 /* Entry to report DMA RX/TX rings */ 3064 priv->dbgfs_rings_status = 3065 debugfs_create_file("descriptors_status", S_IRUGO, 3066 priv->dbgfs_dir, dev, 3067 &stmmac_rings_status_fops); 3068 3069 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3070 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); 3071 debugfs_remove_recursive(priv->dbgfs_dir); 3072 3073 return -ENOMEM; 3074 } 3075 3076 /* Entry to report the DMA HW features */ 3077 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, 3078 priv->dbgfs_dir, 3079 dev, &stmmac_dma_cap_fops); 3080 3081 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3082 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); 3083 debugfs_remove_recursive(priv->dbgfs_dir); 3084 3085 return -ENOMEM; 3086 } 3087 3088 return 0; 3089 } 3090 3091 static void stmmac_exit_fs(struct net_device *dev) 3092 { 3093 struct stmmac_priv *priv = netdev_priv(dev); 3094 3095 debugfs_remove_recursive(priv->dbgfs_dir); 3096 } 3097 #endif /* CONFIG_DEBUG_FS */ 3098 3099 static const struct net_device_ops stmmac_netdev_ops = { 3100 .ndo_open = stmmac_open, 3101 .ndo_start_xmit = stmmac_xmit, 3102 .ndo_stop = stmmac_release, 3103 .ndo_change_mtu = stmmac_change_mtu, 3104 .ndo_fix_features = stmmac_fix_features, 3105 .ndo_set_features = stmmac_set_features, 3106 .ndo_set_rx_mode = stmmac_set_rx_mode, 3107 .ndo_tx_timeout = stmmac_tx_timeout, 3108 .ndo_do_ioctl = stmmac_ioctl, 3109 #ifdef CONFIG_NET_POLL_CONTROLLER 3110 .ndo_poll_controller = stmmac_poll_controller, 3111 #endif 3112 .ndo_set_mac_address = eth_mac_addr, 3113 }; 3114 3115 /** 3116 * stmmac_hw_init - Init the MAC device 3117 * @priv: driver private structure 3118 * Description: this function is to configure the MAC device according to 3119 * some platform parameters or the HW capability register. It prepares the 3120 * driver to use either ring or chain modes and to setup either enhanced or 3121 * normal descriptors. 3122 */ 3123 static int stmmac_hw_init(struct stmmac_priv *priv) 3124 { 3125 struct mac_device_info *mac; 3126 3127 /* Identify the MAC HW device */ 3128 if (priv->plat->has_gmac) { 3129 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3130 mac = dwmac1000_setup(priv->ioaddr, 3131 priv->plat->multicast_filter_bins, 3132 priv->plat->unicast_filter_entries, 3133 &priv->synopsys_id); 3134 } else if (priv->plat->has_gmac4) { 3135 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3136 mac = dwmac4_setup(priv->ioaddr, 3137 priv->plat->multicast_filter_bins, 3138 priv->plat->unicast_filter_entries, 3139 &priv->synopsys_id); 3140 } else { 3141 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); 3142 } 3143 if (!mac) 3144 return -ENOMEM; 3145 3146 priv->hw = mac; 3147 3148 /* To use the chained or ring mode */ 3149 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3150 priv->hw->mode = &dwmac4_ring_mode_ops; 3151 } else { 3152 if (chain_mode) { 3153 priv->hw->mode = &chain_mode_ops; 3154 dev_info(priv->device, "Chain mode enabled\n"); 3155 priv->mode = STMMAC_CHAIN_MODE; 3156 } else { 3157 priv->hw->mode = &ring_mode_ops; 3158 dev_info(priv->device, "Ring mode enabled\n"); 3159 priv->mode = STMMAC_RING_MODE; 3160 } 3161 } 3162 3163 /* Get the HW capability (new GMAC newer than 3.50a) */ 3164 priv->hw_cap_support = stmmac_get_hw_features(priv); 3165 if (priv->hw_cap_support) { 3166 dev_info(priv->device, "DMA HW capability register supported\n"); 3167 3168 /* We can override some gmac/dma configuration fields: e.g. 3169 * enh_desc, tx_coe (e.g. that are passed through the 3170 * platform) with the values from the HW capability 3171 * register (if supported). 3172 */ 3173 priv->plat->enh_desc = priv->dma_cap.enh_desc; 3174 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 3175 priv->hw->pmt = priv->plat->pmt; 3176 3177 /* TXCOE doesn't work in thresh DMA mode */ 3178 if (priv->plat->force_thresh_dma_mode) 3179 priv->plat->tx_coe = 0; 3180 else 3181 priv->plat->tx_coe = priv->dma_cap.tx_coe; 3182 3183 /* In case of GMAC4 rx_coe is from HW cap register. */ 3184 priv->plat->rx_coe = priv->dma_cap.rx_coe; 3185 3186 if (priv->dma_cap.rx_coe_type2) 3187 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 3188 else if (priv->dma_cap.rx_coe_type1) 3189 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 3190 3191 } else { 3192 dev_info(priv->device, "No HW DMA feature register supported\n"); 3193 } 3194 3195 /* To use alternate (extended), normal or GMAC4 descriptor structures */ 3196 if (priv->synopsys_id >= DWMAC_CORE_4_00) 3197 priv->hw->desc = &dwmac4_desc_ops; 3198 else 3199 stmmac_selec_desc_mode(priv); 3200 3201 if (priv->plat->rx_coe) { 3202 priv->hw->rx_csum = priv->plat->rx_coe; 3203 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 3204 if (priv->synopsys_id < DWMAC_CORE_4_00) 3205 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 3206 } 3207 if (priv->plat->tx_coe) 3208 dev_info(priv->device, "TX Checksum insertion supported\n"); 3209 3210 if (priv->plat->pmt) { 3211 dev_info(priv->device, "Wake-Up On Lan supported\n"); 3212 device_set_wakeup_capable(priv->device, 1); 3213 } 3214 3215 if (priv->dma_cap.tsoen) 3216 dev_info(priv->device, "TSO supported\n"); 3217 3218 return 0; 3219 } 3220 3221 /** 3222 * stmmac_dvr_probe 3223 * @device: device pointer 3224 * @plat_dat: platform data pointer 3225 * @res: stmmac resource pointer 3226 * Description: this is the main probe function used to 3227 * call the alloc_etherdev, allocate the priv structure. 3228 * Return: 3229 * returns 0 on success, otherwise errno. 3230 */ 3231 int stmmac_dvr_probe(struct device *device, 3232 struct plat_stmmacenet_data *plat_dat, 3233 struct stmmac_resources *res) 3234 { 3235 int ret = 0; 3236 struct net_device *ndev = NULL; 3237 struct stmmac_priv *priv; 3238 3239 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 3240 if (!ndev) 3241 return -ENOMEM; 3242 3243 SET_NETDEV_DEV(ndev, device); 3244 3245 priv = netdev_priv(ndev); 3246 priv->device = device; 3247 priv->dev = ndev; 3248 3249 stmmac_set_ethtool_ops(ndev); 3250 priv->pause = pause; 3251 priv->plat = plat_dat; 3252 priv->ioaddr = res->addr; 3253 priv->dev->base_addr = (unsigned long)res->addr; 3254 3255 priv->dev->irq = res->irq; 3256 priv->wol_irq = res->wol_irq; 3257 priv->lpi_irq = res->lpi_irq; 3258 3259 if (res->mac) 3260 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 3261 3262 dev_set_drvdata(device, priv->dev); 3263 3264 /* Verify driver arguments */ 3265 stmmac_verify_args(); 3266 3267 /* Override with kernel parameters if supplied XXX CRS XXX 3268 * this needs to have multiple instances 3269 */ 3270 if ((phyaddr >= 0) && (phyaddr <= 31)) 3271 priv->plat->phy_addr = phyaddr; 3272 3273 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 3274 if (IS_ERR(priv->stmmac_clk)) { 3275 netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n", 3276 __func__); 3277 /* If failed to obtain stmmac_clk and specific clk_csr value 3278 * is NOT passed from the platform, probe fail. 3279 */ 3280 if (!priv->plat->clk_csr) { 3281 ret = PTR_ERR(priv->stmmac_clk); 3282 goto error_clk_get; 3283 } else { 3284 priv->stmmac_clk = NULL; 3285 } 3286 } 3287 clk_prepare_enable(priv->stmmac_clk); 3288 3289 priv->pclk = devm_clk_get(priv->device, "pclk"); 3290 if (IS_ERR(priv->pclk)) { 3291 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { 3292 ret = -EPROBE_DEFER; 3293 goto error_pclk_get; 3294 } 3295 priv->pclk = NULL; 3296 } 3297 clk_prepare_enable(priv->pclk); 3298 3299 priv->stmmac_rst = devm_reset_control_get(priv->device, 3300 STMMAC_RESOURCE_NAME); 3301 if (IS_ERR(priv->stmmac_rst)) { 3302 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 3303 ret = -EPROBE_DEFER; 3304 goto error_hw_init; 3305 } 3306 dev_info(priv->device, "no reset control found\n"); 3307 priv->stmmac_rst = NULL; 3308 } 3309 if (priv->stmmac_rst) 3310 reset_control_deassert(priv->stmmac_rst); 3311 3312 /* Init MAC and get the capabilities */ 3313 ret = stmmac_hw_init(priv); 3314 if (ret) 3315 goto error_hw_init; 3316 3317 ndev->netdev_ops = &stmmac_netdev_ops; 3318 3319 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3320 NETIF_F_RXCSUM; 3321 3322 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3323 ndev->hw_features |= NETIF_F_TSO; 3324 priv->tso = true; 3325 dev_info(priv->device, "TSO feature enabled\n"); 3326 } 3327 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 3328 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 3329 #ifdef STMMAC_VLAN_TAG_USED 3330 /* Both mac100 and gmac support receive VLAN tag detection */ 3331 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3332 #endif 3333 priv->msg_enable = netif_msg_init(debug, default_msg_level); 3334 3335 /* MTU range: 46 - hw-specific max */ 3336 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 3337 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 3338 ndev->max_mtu = JUMBO_LEN; 3339 else 3340 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 3341 if (priv->plat->maxmtu < ndev->max_mtu) 3342 ndev->max_mtu = priv->plat->maxmtu; 3343 3344 if (flow_ctrl) 3345 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 3346 3347 /* Rx Watchdog is available in the COREs newer than the 3.40. 3348 * In some case, for example on bugged HW this feature 3349 * has to be disable and this can be done by passing the 3350 * riwt_off field from the platform. 3351 */ 3352 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 3353 priv->use_riwt = 1; 3354 netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n"); 3355 } 3356 3357 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 3358 3359 spin_lock_init(&priv->lock); 3360 spin_lock_init(&priv->tx_lock); 3361 3362 ret = register_netdev(ndev); 3363 if (ret) { 3364 netdev_err(priv->dev, "%s: ERROR %i registering the device\n", 3365 __func__, ret); 3366 goto error_netdev_register; 3367 } 3368 3369 /* If a specific clk_csr value is passed from the platform 3370 * this means that the CSR Clock Range selection cannot be 3371 * changed at run-time and it is fixed. Viceversa the driver'll try to 3372 * set the MDC clock dynamically according to the csr actual 3373 * clock input. 3374 */ 3375 if (!priv->plat->clk_csr) 3376 stmmac_clk_csr_set(priv); 3377 else 3378 priv->clk_csr = priv->plat->clk_csr; 3379 3380 stmmac_check_pcs_mode(priv); 3381 3382 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3383 priv->hw->pcs != STMMAC_PCS_TBI && 3384 priv->hw->pcs != STMMAC_PCS_RTBI) { 3385 /* MDIO bus Registration */ 3386 ret = stmmac_mdio_register(ndev); 3387 if (ret < 0) { 3388 netdev_err(priv->dev, 3389 "%s: MDIO bus (id: %d) registration failed", 3390 __func__, priv->plat->bus_id); 3391 goto error_mdio_register; 3392 } 3393 } 3394 3395 return 0; 3396 3397 error_mdio_register: 3398 unregister_netdev(ndev); 3399 error_netdev_register: 3400 netif_napi_del(&priv->napi); 3401 error_hw_init: 3402 clk_disable_unprepare(priv->pclk); 3403 error_pclk_get: 3404 clk_disable_unprepare(priv->stmmac_clk); 3405 error_clk_get: 3406 free_netdev(ndev); 3407 3408 return ret; 3409 } 3410 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 3411 3412 /** 3413 * stmmac_dvr_remove 3414 * @dev: device pointer 3415 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 3416 * changes the link status, releases the DMA descriptor rings. 3417 */ 3418 int stmmac_dvr_remove(struct device *dev) 3419 { 3420 struct net_device *ndev = dev_get_drvdata(dev); 3421 struct stmmac_priv *priv = netdev_priv(ndev); 3422 3423 netdev_info(priv->dev, "%s: removing driver", __func__); 3424 3425 priv->hw->dma->stop_rx(priv->ioaddr); 3426 priv->hw->dma->stop_tx(priv->ioaddr); 3427 3428 stmmac_set_mac(priv->ioaddr, false); 3429 netif_carrier_off(ndev); 3430 unregister_netdev(ndev); 3431 if (priv->stmmac_rst) 3432 reset_control_assert(priv->stmmac_rst); 3433 clk_disable_unprepare(priv->pclk); 3434 clk_disable_unprepare(priv->stmmac_clk); 3435 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3436 priv->hw->pcs != STMMAC_PCS_TBI && 3437 priv->hw->pcs != STMMAC_PCS_RTBI) 3438 stmmac_mdio_unregister(ndev); 3439 free_netdev(ndev); 3440 3441 return 0; 3442 } 3443 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 3444 3445 /** 3446 * stmmac_suspend - suspend callback 3447 * @dev: device pointer 3448 * Description: this is the function to suspend the device and it is called 3449 * by the platform driver to stop the network queue, release the resources, 3450 * program the PMT register (for WoL), clean and release driver resources. 3451 */ 3452 int stmmac_suspend(struct device *dev) 3453 { 3454 struct net_device *ndev = dev_get_drvdata(dev); 3455 struct stmmac_priv *priv = netdev_priv(ndev); 3456 unsigned long flags; 3457 3458 if (!ndev || !netif_running(ndev)) 3459 return 0; 3460 3461 if (ndev->phydev) 3462 phy_stop(ndev->phydev); 3463 3464 spin_lock_irqsave(&priv->lock, flags); 3465 3466 netif_device_detach(ndev); 3467 netif_stop_queue(ndev); 3468 3469 napi_disable(&priv->napi); 3470 3471 /* Stop TX/RX DMA */ 3472 priv->hw->dma->stop_tx(priv->ioaddr); 3473 priv->hw->dma->stop_rx(priv->ioaddr); 3474 3475 /* Enable Power down mode by programming the PMT regs */ 3476 if (device_may_wakeup(priv->device)) { 3477 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3478 priv->irq_wake = 1; 3479 } else { 3480 stmmac_set_mac(priv->ioaddr, false); 3481 pinctrl_pm_select_sleep_state(priv->device); 3482 /* Disable clock in case of PWM is off */ 3483 clk_disable(priv->pclk); 3484 clk_disable(priv->stmmac_clk); 3485 } 3486 spin_unlock_irqrestore(&priv->lock, flags); 3487 3488 priv->oldlink = 0; 3489 priv->speed = 0; 3490 priv->oldduplex = -1; 3491 return 0; 3492 } 3493 EXPORT_SYMBOL_GPL(stmmac_suspend); 3494 3495 /** 3496 * stmmac_resume - resume callback 3497 * @dev: device pointer 3498 * Description: when resume this function is invoked to setup the DMA and CORE 3499 * in a usable state. 3500 */ 3501 int stmmac_resume(struct device *dev) 3502 { 3503 struct net_device *ndev = dev_get_drvdata(dev); 3504 struct stmmac_priv *priv = netdev_priv(ndev); 3505 unsigned long flags; 3506 3507 if (!netif_running(ndev)) 3508 return 0; 3509 3510 /* Power Down bit, into the PM register, is cleared 3511 * automatically as soon as a magic packet or a Wake-up frame 3512 * is received. Anyway, it's better to manually clear 3513 * this bit because it can generate problems while resuming 3514 * from another devices (e.g. serial console). 3515 */ 3516 if (device_may_wakeup(priv->device)) { 3517 spin_lock_irqsave(&priv->lock, flags); 3518 priv->hw->mac->pmt(priv->hw, 0); 3519 spin_unlock_irqrestore(&priv->lock, flags); 3520 priv->irq_wake = 0; 3521 } else { 3522 pinctrl_pm_select_default_state(priv->device); 3523 /* enable the clk prevously disabled */ 3524 clk_enable(priv->stmmac_clk); 3525 clk_enable(priv->pclk); 3526 /* reset the phy so that it's ready */ 3527 if (priv->mii) 3528 stmmac_mdio_reset(priv->mii); 3529 } 3530 3531 netif_device_attach(ndev); 3532 3533 spin_lock_irqsave(&priv->lock, flags); 3534 3535 priv->cur_rx = 0; 3536 priv->dirty_rx = 0; 3537 priv->dirty_tx = 0; 3538 priv->cur_tx = 0; 3539 /* reset private mss value to force mss context settings at 3540 * next tso xmit (only used for gmac4). 3541 */ 3542 priv->mss = 0; 3543 3544 stmmac_clear_descriptors(priv); 3545 3546 stmmac_hw_setup(ndev, false); 3547 stmmac_init_tx_coalesce(priv); 3548 stmmac_set_rx_mode(ndev); 3549 3550 napi_enable(&priv->napi); 3551 3552 netif_start_queue(ndev); 3553 3554 spin_unlock_irqrestore(&priv->lock, flags); 3555 3556 if (ndev->phydev) 3557 phy_start(ndev->phydev); 3558 3559 return 0; 3560 } 3561 EXPORT_SYMBOL_GPL(stmmac_resume); 3562 3563 #ifndef MODULE 3564 static int __init stmmac_cmdline_opt(char *str) 3565 { 3566 char *opt; 3567 3568 if (!str || !*str) 3569 return -EINVAL; 3570 while ((opt = strsep(&str, ",")) != NULL) { 3571 if (!strncmp(opt, "debug:", 6)) { 3572 if (kstrtoint(opt + 6, 0, &debug)) 3573 goto err; 3574 } else if (!strncmp(opt, "phyaddr:", 8)) { 3575 if (kstrtoint(opt + 8, 0, &phyaddr)) 3576 goto err; 3577 } else if (!strncmp(opt, "buf_sz:", 7)) { 3578 if (kstrtoint(opt + 7, 0, &buf_sz)) 3579 goto err; 3580 } else if (!strncmp(opt, "tc:", 3)) { 3581 if (kstrtoint(opt + 3, 0, &tc)) 3582 goto err; 3583 } else if (!strncmp(opt, "watchdog:", 9)) { 3584 if (kstrtoint(opt + 9, 0, &watchdog)) 3585 goto err; 3586 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3587 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3588 goto err; 3589 } else if (!strncmp(opt, "pause:", 6)) { 3590 if (kstrtoint(opt + 6, 0, &pause)) 3591 goto err; 3592 } else if (!strncmp(opt, "eee_timer:", 10)) { 3593 if (kstrtoint(opt + 10, 0, &eee_timer)) 3594 goto err; 3595 } else if (!strncmp(opt, "chain_mode:", 11)) { 3596 if (kstrtoint(opt + 11, 0, &chain_mode)) 3597 goto err; 3598 } 3599 } 3600 return 0; 3601 3602 err: 3603 pr_err("%s: ERROR broken module parameter conversion", __func__); 3604 return -EINVAL; 3605 } 3606 3607 __setup("stmmaceth=", stmmac_cmdline_opt); 3608 #endif /* MODULE */ 3609 3610 static int __init stmmac_init(void) 3611 { 3612 #ifdef CONFIG_DEBUG_FS 3613 /* Create debugfs main directory if it doesn't exist yet */ 3614 if (!stmmac_fs_dir) { 3615 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 3616 3617 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 3618 pr_err("ERROR %s, debugfs create directory failed\n", 3619 STMMAC_RESOURCE_NAME); 3620 3621 return -ENOMEM; 3622 } 3623 } 3624 #endif 3625 3626 return 0; 3627 } 3628 3629 static void __exit stmmac_exit(void) 3630 { 3631 #ifdef CONFIG_DEBUG_FS 3632 debugfs_remove_recursive(stmmac_fs_dir); 3633 #endif 3634 } 3635 3636 module_init(stmmac_init) 3637 module_exit(stmmac_exit) 3638 3639 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3640 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3641 MODULE_LICENSE("GPL"); 3642