1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 if (priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) 992 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 993 994 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 995 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 996 997 if (interface == PHY_INTERFACE_MODE_USXGMII) { 998 switch (speed) { 999 case SPEED_10000: 1000 ctrl |= priv->hw->link.xgmii.speed10000; 1001 break; 1002 case SPEED_5000: 1003 ctrl |= priv->hw->link.xgmii.speed5000; 1004 break; 1005 case SPEED_2500: 1006 ctrl |= priv->hw->link.xgmii.speed2500; 1007 break; 1008 default: 1009 return; 1010 } 1011 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1012 switch (speed) { 1013 case SPEED_100000: 1014 ctrl |= priv->hw->link.xlgmii.speed100000; 1015 break; 1016 case SPEED_50000: 1017 ctrl |= priv->hw->link.xlgmii.speed50000; 1018 break; 1019 case SPEED_40000: 1020 ctrl |= priv->hw->link.xlgmii.speed40000; 1021 break; 1022 case SPEED_25000: 1023 ctrl |= priv->hw->link.xlgmii.speed25000; 1024 break; 1025 case SPEED_10000: 1026 ctrl |= priv->hw->link.xgmii.speed10000; 1027 break; 1028 case SPEED_2500: 1029 ctrl |= priv->hw->link.speed2500; 1030 break; 1031 case SPEED_1000: 1032 ctrl |= priv->hw->link.speed1000; 1033 break; 1034 default: 1035 return; 1036 } 1037 } else { 1038 switch (speed) { 1039 case SPEED_2500: 1040 ctrl |= priv->hw->link.speed2500; 1041 break; 1042 case SPEED_1000: 1043 ctrl |= priv->hw->link.speed1000; 1044 break; 1045 case SPEED_100: 1046 ctrl |= priv->hw->link.speed100; 1047 break; 1048 case SPEED_10: 1049 ctrl |= priv->hw->link.speed10; 1050 break; 1051 default: 1052 return; 1053 } 1054 } 1055 1056 priv->speed = speed; 1057 1058 if (priv->plat->fix_mac_speed) 1059 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1060 1061 if (!duplex) 1062 ctrl &= ~priv->hw->link.duplex; 1063 else 1064 ctrl |= priv->hw->link.duplex; 1065 1066 /* Flow Control operation */ 1067 if (rx_pause && tx_pause) 1068 priv->flow_ctrl = FLOW_AUTO; 1069 else if (rx_pause && !tx_pause) 1070 priv->flow_ctrl = FLOW_RX; 1071 else if (!rx_pause && tx_pause) 1072 priv->flow_ctrl = FLOW_TX; 1073 else 1074 priv->flow_ctrl = FLOW_OFF; 1075 1076 stmmac_mac_flow_ctrl(priv, duplex); 1077 1078 if (ctrl != old_ctrl) 1079 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1080 1081 stmmac_mac_set(priv, priv->ioaddr, true); 1082 if (phy && priv->dma_cap.eee) { 1083 priv->eee_active = 1084 phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0; 1085 priv->eee_enabled = stmmac_eee_init(priv); 1086 priv->tx_lpi_enabled = priv->eee_enabled; 1087 stmmac_set_eee_pls(priv, priv->hw, true); 1088 } 1089 1090 if (priv->dma_cap.fpesel) 1091 stmmac_fpe_link_state_handle(priv, true); 1092 } 1093 1094 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1095 .mac_select_pcs = stmmac_mac_select_pcs, 1096 .mac_config = stmmac_mac_config, 1097 .mac_link_down = stmmac_mac_link_down, 1098 .mac_link_up = stmmac_mac_link_up, 1099 }; 1100 1101 /** 1102 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1103 * @priv: driver private structure 1104 * Description: this is to verify if the HW supports the PCS. 1105 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1106 * configured for the TBI, RTBI, or SGMII PHY interface. 1107 */ 1108 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1109 { 1110 int interface = priv->plat->interface; 1111 1112 if (priv->dma_cap.pcs) { 1113 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1114 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1115 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1116 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1117 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1118 priv->hw->pcs = STMMAC_PCS_RGMII; 1119 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1120 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1121 priv->hw->pcs = STMMAC_PCS_SGMII; 1122 } 1123 } 1124 } 1125 1126 /** 1127 * stmmac_init_phy - PHY initialization 1128 * @dev: net device structure 1129 * Description: it initializes the driver's PHY state, and attaches the PHY 1130 * to the mac driver. 1131 * Return value: 1132 * 0 on success 1133 */ 1134 static int stmmac_init_phy(struct net_device *dev) 1135 { 1136 struct stmmac_priv *priv = netdev_priv(dev); 1137 struct fwnode_handle *fwnode; 1138 int ret; 1139 1140 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1141 if (!fwnode) 1142 fwnode = dev_fwnode(priv->device); 1143 1144 if (fwnode) 1145 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1146 1147 /* Some DT bindings do not set-up the PHY handle. Let's try to 1148 * manually parse it 1149 */ 1150 if (!fwnode || ret) { 1151 int addr = priv->plat->phy_addr; 1152 struct phy_device *phydev; 1153 1154 if (addr < 0) { 1155 netdev_err(priv->dev, "no phy found\n"); 1156 return -ENODEV; 1157 } 1158 1159 phydev = mdiobus_get_phy(priv->mii, addr); 1160 if (!phydev) { 1161 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1162 return -ENODEV; 1163 } 1164 1165 ret = phylink_connect_phy(priv->phylink, phydev); 1166 } 1167 1168 if (!priv->plat->pmt) { 1169 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1170 1171 phylink_ethtool_get_wol(priv->phylink, &wol); 1172 device_set_wakeup_capable(priv->device, !!wol.supported); 1173 } 1174 1175 return ret; 1176 } 1177 1178 static int stmmac_phy_setup(struct stmmac_priv *priv) 1179 { 1180 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1181 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1182 int max_speed = priv->plat->max_speed; 1183 int mode = priv->plat->phy_interface; 1184 struct phylink *phylink; 1185 1186 priv->phylink_config.dev = &priv->dev->dev; 1187 priv->phylink_config.type = PHYLINK_NETDEV; 1188 if (priv->plat->mdio_bus_data) 1189 priv->phylink_config.ovr_an_inband = 1190 mdio_bus_data->xpcs_an_inband; 1191 1192 if (!fwnode) 1193 fwnode = dev_fwnode(priv->device); 1194 1195 /* Set the platform/firmware specified interface mode */ 1196 __set_bit(mode, priv->phylink_config.supported_interfaces); 1197 1198 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1199 if (priv->hw->xpcs) 1200 xpcs_get_interfaces(priv->hw->xpcs, 1201 priv->phylink_config.supported_interfaces); 1202 1203 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1204 MAC_10 | MAC_100; 1205 1206 if (!max_speed || max_speed >= 1000) 1207 priv->phylink_config.mac_capabilities |= MAC_1000; 1208 1209 if (priv->plat->has_gmac4) { 1210 if (!max_speed || max_speed >= 2500) 1211 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1212 } else if (priv->plat->has_xgmac) { 1213 if (!max_speed || max_speed >= 2500) 1214 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1215 if (!max_speed || max_speed >= 5000) 1216 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1217 if (!max_speed || max_speed >= 10000) 1218 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1219 if (!max_speed || max_speed >= 25000) 1220 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1221 if (!max_speed || max_speed >= 40000) 1222 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1223 if (!max_speed || max_speed >= 50000) 1224 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1225 if (!max_speed || max_speed >= 100000) 1226 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1227 } 1228 1229 /* Half-Duplex can only work with single queue */ 1230 if (priv->plat->tx_queues_to_use > 1) 1231 priv->phylink_config.mac_capabilities &= 1232 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1233 priv->phylink_config.mac_managed_pm = true; 1234 1235 phylink = phylink_create(&priv->phylink_config, fwnode, 1236 mode, &stmmac_phylink_mac_ops); 1237 if (IS_ERR(phylink)) 1238 return PTR_ERR(phylink); 1239 1240 priv->phylink = phylink; 1241 return 0; 1242 } 1243 1244 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1245 struct stmmac_dma_conf *dma_conf) 1246 { 1247 u32 rx_cnt = priv->plat->rx_queues_to_use; 1248 unsigned int desc_size; 1249 void *head_rx; 1250 u32 queue; 1251 1252 /* Display RX rings */ 1253 for (queue = 0; queue < rx_cnt; queue++) { 1254 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1255 1256 pr_info("\tRX Queue %u rings\n", queue); 1257 1258 if (priv->extend_desc) { 1259 head_rx = (void *)rx_q->dma_erx; 1260 desc_size = sizeof(struct dma_extended_desc); 1261 } else { 1262 head_rx = (void *)rx_q->dma_rx; 1263 desc_size = sizeof(struct dma_desc); 1264 } 1265 1266 /* Display RX ring */ 1267 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1268 rx_q->dma_rx_phy, desc_size); 1269 } 1270 } 1271 1272 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1273 struct stmmac_dma_conf *dma_conf) 1274 { 1275 u32 tx_cnt = priv->plat->tx_queues_to_use; 1276 unsigned int desc_size; 1277 void *head_tx; 1278 u32 queue; 1279 1280 /* Display TX rings */ 1281 for (queue = 0; queue < tx_cnt; queue++) { 1282 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1283 1284 pr_info("\tTX Queue %d rings\n", queue); 1285 1286 if (priv->extend_desc) { 1287 head_tx = (void *)tx_q->dma_etx; 1288 desc_size = sizeof(struct dma_extended_desc); 1289 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1290 head_tx = (void *)tx_q->dma_entx; 1291 desc_size = sizeof(struct dma_edesc); 1292 } else { 1293 head_tx = (void *)tx_q->dma_tx; 1294 desc_size = sizeof(struct dma_desc); 1295 } 1296 1297 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1298 tx_q->dma_tx_phy, desc_size); 1299 } 1300 } 1301 1302 static void stmmac_display_rings(struct stmmac_priv *priv, 1303 struct stmmac_dma_conf *dma_conf) 1304 { 1305 /* Display RX ring */ 1306 stmmac_display_rx_rings(priv, dma_conf); 1307 1308 /* Display TX ring */ 1309 stmmac_display_tx_rings(priv, dma_conf); 1310 } 1311 1312 static int stmmac_set_bfsize(int mtu, int bufsize) 1313 { 1314 int ret = bufsize; 1315 1316 if (mtu >= BUF_SIZE_8KiB) 1317 ret = BUF_SIZE_16KiB; 1318 else if (mtu >= BUF_SIZE_4KiB) 1319 ret = BUF_SIZE_8KiB; 1320 else if (mtu >= BUF_SIZE_2KiB) 1321 ret = BUF_SIZE_4KiB; 1322 else if (mtu > DEFAULT_BUFSIZE) 1323 ret = BUF_SIZE_2KiB; 1324 else 1325 ret = DEFAULT_BUFSIZE; 1326 1327 return ret; 1328 } 1329 1330 /** 1331 * stmmac_clear_rx_descriptors - clear RX descriptors 1332 * @priv: driver private structure 1333 * @dma_conf: structure to take the dma data 1334 * @queue: RX queue index 1335 * Description: this function is called to clear the RX descriptors 1336 * in case of both basic and extended descriptors are used. 1337 */ 1338 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1339 struct stmmac_dma_conf *dma_conf, 1340 u32 queue) 1341 { 1342 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1343 int i; 1344 1345 /* Clear the RX descriptors */ 1346 for (i = 0; i < dma_conf->dma_rx_size; i++) 1347 if (priv->extend_desc) 1348 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1349 priv->use_riwt, priv->mode, 1350 (i == dma_conf->dma_rx_size - 1), 1351 dma_conf->dma_buf_sz); 1352 else 1353 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1354 priv->use_riwt, priv->mode, 1355 (i == dma_conf->dma_rx_size - 1), 1356 dma_conf->dma_buf_sz); 1357 } 1358 1359 /** 1360 * stmmac_clear_tx_descriptors - clear tx descriptors 1361 * @priv: driver private structure 1362 * @dma_conf: structure to take the dma data 1363 * @queue: TX queue index. 1364 * Description: this function is called to clear the TX descriptors 1365 * in case of both basic and extended descriptors are used. 1366 */ 1367 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1368 struct stmmac_dma_conf *dma_conf, 1369 u32 queue) 1370 { 1371 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1372 int i; 1373 1374 /* Clear the TX descriptors */ 1375 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1376 int last = (i == (dma_conf->dma_tx_size - 1)); 1377 struct dma_desc *p; 1378 1379 if (priv->extend_desc) 1380 p = &tx_q->dma_etx[i].basic; 1381 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1382 p = &tx_q->dma_entx[i].basic; 1383 else 1384 p = &tx_q->dma_tx[i]; 1385 1386 stmmac_init_tx_desc(priv, p, priv->mode, last); 1387 } 1388 } 1389 1390 /** 1391 * stmmac_clear_descriptors - clear descriptors 1392 * @priv: driver private structure 1393 * @dma_conf: structure to take the dma data 1394 * Description: this function is called to clear the TX and RX descriptors 1395 * in case of both basic and extended descriptors are used. 1396 */ 1397 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1398 struct stmmac_dma_conf *dma_conf) 1399 { 1400 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1401 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1402 u32 queue; 1403 1404 /* Clear the RX descriptors */ 1405 for (queue = 0; queue < rx_queue_cnt; queue++) 1406 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1407 1408 /* Clear the TX descriptors */ 1409 for (queue = 0; queue < tx_queue_cnt; queue++) 1410 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1411 } 1412 1413 /** 1414 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1415 * @priv: driver private structure 1416 * @dma_conf: structure to take the dma data 1417 * @p: descriptor pointer 1418 * @i: descriptor index 1419 * @flags: gfp flag 1420 * @queue: RX queue index 1421 * Description: this function is called to allocate a receive buffer, perform 1422 * the DMA mapping and init the descriptor. 1423 */ 1424 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1425 struct stmmac_dma_conf *dma_conf, 1426 struct dma_desc *p, 1427 int i, gfp_t flags, u32 queue) 1428 { 1429 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1430 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1431 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1432 1433 if (priv->dma_cap.addr64 <= 32) 1434 gfp |= GFP_DMA32; 1435 1436 if (!buf->page) { 1437 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1438 if (!buf->page) 1439 return -ENOMEM; 1440 buf->page_offset = stmmac_rx_offset(priv); 1441 } 1442 1443 if (priv->sph && !buf->sec_page) { 1444 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1445 if (!buf->sec_page) 1446 return -ENOMEM; 1447 1448 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1449 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1450 } else { 1451 buf->sec_page = NULL; 1452 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1453 } 1454 1455 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1456 1457 stmmac_set_desc_addr(priv, p, buf->addr); 1458 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1459 stmmac_init_desc3(priv, p); 1460 1461 return 0; 1462 } 1463 1464 /** 1465 * stmmac_free_rx_buffer - free RX dma buffers 1466 * @priv: private structure 1467 * @rx_q: RX queue 1468 * @i: buffer index. 1469 */ 1470 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1471 struct stmmac_rx_queue *rx_q, 1472 int i) 1473 { 1474 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1475 1476 if (buf->page) 1477 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1478 buf->page = NULL; 1479 1480 if (buf->sec_page) 1481 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1482 buf->sec_page = NULL; 1483 } 1484 1485 /** 1486 * stmmac_free_tx_buffer - free RX dma buffers 1487 * @priv: private structure 1488 * @dma_conf: structure to take the dma data 1489 * @queue: RX queue index 1490 * @i: buffer index. 1491 */ 1492 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1493 struct stmmac_dma_conf *dma_conf, 1494 u32 queue, int i) 1495 { 1496 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1497 1498 if (tx_q->tx_skbuff_dma[i].buf && 1499 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1500 if (tx_q->tx_skbuff_dma[i].map_as_page) 1501 dma_unmap_page(priv->device, 1502 tx_q->tx_skbuff_dma[i].buf, 1503 tx_q->tx_skbuff_dma[i].len, 1504 DMA_TO_DEVICE); 1505 else 1506 dma_unmap_single(priv->device, 1507 tx_q->tx_skbuff_dma[i].buf, 1508 tx_q->tx_skbuff_dma[i].len, 1509 DMA_TO_DEVICE); 1510 } 1511 1512 if (tx_q->xdpf[i] && 1513 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1514 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1515 xdp_return_frame(tx_q->xdpf[i]); 1516 tx_q->xdpf[i] = NULL; 1517 } 1518 1519 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1520 tx_q->xsk_frames_done++; 1521 1522 if (tx_q->tx_skbuff[i] && 1523 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1524 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1525 tx_q->tx_skbuff[i] = NULL; 1526 } 1527 1528 tx_q->tx_skbuff_dma[i].buf = 0; 1529 tx_q->tx_skbuff_dma[i].map_as_page = false; 1530 } 1531 1532 /** 1533 * dma_free_rx_skbufs - free RX dma buffers 1534 * @priv: private structure 1535 * @dma_conf: structure to take the dma data 1536 * @queue: RX queue index 1537 */ 1538 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1539 struct stmmac_dma_conf *dma_conf, 1540 u32 queue) 1541 { 1542 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1543 int i; 1544 1545 for (i = 0; i < dma_conf->dma_rx_size; i++) 1546 stmmac_free_rx_buffer(priv, rx_q, i); 1547 } 1548 1549 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1550 struct stmmac_dma_conf *dma_conf, 1551 u32 queue, gfp_t flags) 1552 { 1553 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1554 int i; 1555 1556 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1557 struct dma_desc *p; 1558 int ret; 1559 1560 if (priv->extend_desc) 1561 p = &((rx_q->dma_erx + i)->basic); 1562 else 1563 p = rx_q->dma_rx + i; 1564 1565 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1566 queue); 1567 if (ret) 1568 return ret; 1569 1570 rx_q->buf_alloc_num++; 1571 } 1572 1573 return 0; 1574 } 1575 1576 /** 1577 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1578 * @priv: private structure 1579 * @dma_conf: structure to take the dma data 1580 * @queue: RX queue index 1581 */ 1582 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1583 struct stmmac_dma_conf *dma_conf, 1584 u32 queue) 1585 { 1586 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1587 int i; 1588 1589 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1590 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1591 1592 if (!buf->xdp) 1593 continue; 1594 1595 xsk_buff_free(buf->xdp); 1596 buf->xdp = NULL; 1597 } 1598 } 1599 1600 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1601 struct stmmac_dma_conf *dma_conf, 1602 u32 queue) 1603 { 1604 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1605 int i; 1606 1607 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1608 struct stmmac_rx_buffer *buf; 1609 dma_addr_t dma_addr; 1610 struct dma_desc *p; 1611 1612 if (priv->extend_desc) 1613 p = (struct dma_desc *)(rx_q->dma_erx + i); 1614 else 1615 p = rx_q->dma_rx + i; 1616 1617 buf = &rx_q->buf_pool[i]; 1618 1619 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1620 if (!buf->xdp) 1621 return -ENOMEM; 1622 1623 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1624 stmmac_set_desc_addr(priv, p, dma_addr); 1625 rx_q->buf_alloc_num++; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1632 { 1633 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1634 return NULL; 1635 1636 return xsk_get_pool_from_qid(priv->dev, queue); 1637 } 1638 1639 /** 1640 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1641 * @priv: driver private structure 1642 * @dma_conf: structure to take the dma data 1643 * @queue: RX queue index 1644 * @flags: gfp flag. 1645 * Description: this function initializes the DMA RX descriptors 1646 * and allocates the socket buffers. It supports the chained and ring 1647 * modes. 1648 */ 1649 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1650 struct stmmac_dma_conf *dma_conf, 1651 u32 queue, gfp_t flags) 1652 { 1653 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1654 int ret; 1655 1656 netif_dbg(priv, probe, priv->dev, 1657 "(%s) dma_rx_phy=0x%08x\n", __func__, 1658 (u32)rx_q->dma_rx_phy); 1659 1660 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1661 1662 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1663 1664 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1665 1666 if (rx_q->xsk_pool) { 1667 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1668 MEM_TYPE_XSK_BUFF_POOL, 1669 NULL)); 1670 netdev_info(priv->dev, 1671 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1672 rx_q->queue_index); 1673 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1674 } else { 1675 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1676 MEM_TYPE_PAGE_POOL, 1677 rx_q->page_pool)); 1678 netdev_info(priv->dev, 1679 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1680 rx_q->queue_index); 1681 } 1682 1683 if (rx_q->xsk_pool) { 1684 /* RX XDP ZC buffer pool may not be populated, e.g. 1685 * xdpsock TX-only. 1686 */ 1687 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1688 } else { 1689 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1690 if (ret < 0) 1691 return -ENOMEM; 1692 } 1693 1694 /* Setup the chained descriptor addresses */ 1695 if (priv->mode == STMMAC_CHAIN_MODE) { 1696 if (priv->extend_desc) 1697 stmmac_mode_init(priv, rx_q->dma_erx, 1698 rx_q->dma_rx_phy, 1699 dma_conf->dma_rx_size, 1); 1700 else 1701 stmmac_mode_init(priv, rx_q->dma_rx, 1702 rx_q->dma_rx_phy, 1703 dma_conf->dma_rx_size, 0); 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int init_dma_rx_desc_rings(struct net_device *dev, 1710 struct stmmac_dma_conf *dma_conf, 1711 gfp_t flags) 1712 { 1713 struct stmmac_priv *priv = netdev_priv(dev); 1714 u32 rx_count = priv->plat->rx_queues_to_use; 1715 int queue; 1716 int ret; 1717 1718 /* RX INITIALIZATION */ 1719 netif_dbg(priv, probe, priv->dev, 1720 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1721 1722 for (queue = 0; queue < rx_count; queue++) { 1723 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1724 if (ret) 1725 goto err_init_rx_buffers; 1726 } 1727 1728 return 0; 1729 1730 err_init_rx_buffers: 1731 while (queue >= 0) { 1732 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1733 1734 if (rx_q->xsk_pool) 1735 dma_free_rx_xskbufs(priv, dma_conf, queue); 1736 else 1737 dma_free_rx_skbufs(priv, dma_conf, queue); 1738 1739 rx_q->buf_alloc_num = 0; 1740 rx_q->xsk_pool = NULL; 1741 1742 queue--; 1743 } 1744 1745 return ret; 1746 } 1747 1748 /** 1749 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1750 * @priv: driver private structure 1751 * @dma_conf: structure to take the dma data 1752 * @queue: TX queue index 1753 * Description: this function initializes the DMA TX descriptors 1754 * and allocates the socket buffers. It supports the chained and ring 1755 * modes. 1756 */ 1757 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1758 struct stmmac_dma_conf *dma_conf, 1759 u32 queue) 1760 { 1761 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1762 int i; 1763 1764 netif_dbg(priv, probe, priv->dev, 1765 "(%s) dma_tx_phy=0x%08x\n", __func__, 1766 (u32)tx_q->dma_tx_phy); 1767 1768 /* Setup the chained descriptor addresses */ 1769 if (priv->mode == STMMAC_CHAIN_MODE) { 1770 if (priv->extend_desc) 1771 stmmac_mode_init(priv, tx_q->dma_etx, 1772 tx_q->dma_tx_phy, 1773 dma_conf->dma_tx_size, 1); 1774 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1775 stmmac_mode_init(priv, tx_q->dma_tx, 1776 tx_q->dma_tx_phy, 1777 dma_conf->dma_tx_size, 0); 1778 } 1779 1780 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1781 1782 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1783 struct dma_desc *p; 1784 1785 if (priv->extend_desc) 1786 p = &((tx_q->dma_etx + i)->basic); 1787 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1788 p = &((tx_q->dma_entx + i)->basic); 1789 else 1790 p = tx_q->dma_tx + i; 1791 1792 stmmac_clear_desc(priv, p); 1793 1794 tx_q->tx_skbuff_dma[i].buf = 0; 1795 tx_q->tx_skbuff_dma[i].map_as_page = false; 1796 tx_q->tx_skbuff_dma[i].len = 0; 1797 tx_q->tx_skbuff_dma[i].last_segment = false; 1798 tx_q->tx_skbuff[i] = NULL; 1799 } 1800 1801 return 0; 1802 } 1803 1804 static int init_dma_tx_desc_rings(struct net_device *dev, 1805 struct stmmac_dma_conf *dma_conf) 1806 { 1807 struct stmmac_priv *priv = netdev_priv(dev); 1808 u32 tx_queue_cnt; 1809 u32 queue; 1810 1811 tx_queue_cnt = priv->plat->tx_queues_to_use; 1812 1813 for (queue = 0; queue < tx_queue_cnt; queue++) 1814 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1815 1816 return 0; 1817 } 1818 1819 /** 1820 * init_dma_desc_rings - init the RX/TX descriptor rings 1821 * @dev: net device structure 1822 * @dma_conf: structure to take the dma data 1823 * @flags: gfp flag. 1824 * Description: this function initializes the DMA RX/TX descriptors 1825 * and allocates the socket buffers. It supports the chained and ring 1826 * modes. 1827 */ 1828 static int init_dma_desc_rings(struct net_device *dev, 1829 struct stmmac_dma_conf *dma_conf, 1830 gfp_t flags) 1831 { 1832 struct stmmac_priv *priv = netdev_priv(dev); 1833 int ret; 1834 1835 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1836 if (ret) 1837 return ret; 1838 1839 ret = init_dma_tx_desc_rings(dev, dma_conf); 1840 1841 stmmac_clear_descriptors(priv, dma_conf); 1842 1843 if (netif_msg_hw(priv)) 1844 stmmac_display_rings(priv, dma_conf); 1845 1846 return ret; 1847 } 1848 1849 /** 1850 * dma_free_tx_skbufs - free TX dma buffers 1851 * @priv: private structure 1852 * @dma_conf: structure to take the dma data 1853 * @queue: TX queue index 1854 */ 1855 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1856 struct stmmac_dma_conf *dma_conf, 1857 u32 queue) 1858 { 1859 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1860 int i; 1861 1862 tx_q->xsk_frames_done = 0; 1863 1864 for (i = 0; i < dma_conf->dma_tx_size; i++) 1865 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1866 1867 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1868 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1869 tx_q->xsk_frames_done = 0; 1870 tx_q->xsk_pool = NULL; 1871 } 1872 } 1873 1874 /** 1875 * stmmac_free_tx_skbufs - free TX skb buffers 1876 * @priv: private structure 1877 */ 1878 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1879 { 1880 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1881 u32 queue; 1882 1883 for (queue = 0; queue < tx_queue_cnt; queue++) 1884 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1885 } 1886 1887 /** 1888 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1889 * @priv: private structure 1890 * @dma_conf: structure to take the dma data 1891 * @queue: RX queue index 1892 */ 1893 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1894 struct stmmac_dma_conf *dma_conf, 1895 u32 queue) 1896 { 1897 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1898 1899 /* Release the DMA RX socket buffers */ 1900 if (rx_q->xsk_pool) 1901 dma_free_rx_xskbufs(priv, dma_conf, queue); 1902 else 1903 dma_free_rx_skbufs(priv, dma_conf, queue); 1904 1905 rx_q->buf_alloc_num = 0; 1906 rx_q->xsk_pool = NULL; 1907 1908 /* Free DMA regions of consistent memory previously allocated */ 1909 if (!priv->extend_desc) 1910 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1911 sizeof(struct dma_desc), 1912 rx_q->dma_rx, rx_q->dma_rx_phy); 1913 else 1914 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1915 sizeof(struct dma_extended_desc), 1916 rx_q->dma_erx, rx_q->dma_rx_phy); 1917 1918 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1919 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1920 1921 kfree(rx_q->buf_pool); 1922 if (rx_q->page_pool) 1923 page_pool_destroy(rx_q->page_pool); 1924 } 1925 1926 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1927 struct stmmac_dma_conf *dma_conf) 1928 { 1929 u32 rx_count = priv->plat->rx_queues_to_use; 1930 u32 queue; 1931 1932 /* Free RX queue resources */ 1933 for (queue = 0; queue < rx_count; queue++) 1934 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1935 } 1936 1937 /** 1938 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1939 * @priv: private structure 1940 * @dma_conf: structure to take the dma data 1941 * @queue: TX queue index 1942 */ 1943 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1944 struct stmmac_dma_conf *dma_conf, 1945 u32 queue) 1946 { 1947 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1948 size_t size; 1949 void *addr; 1950 1951 /* Release the DMA TX socket buffers */ 1952 dma_free_tx_skbufs(priv, dma_conf, queue); 1953 1954 if (priv->extend_desc) { 1955 size = sizeof(struct dma_extended_desc); 1956 addr = tx_q->dma_etx; 1957 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1958 size = sizeof(struct dma_edesc); 1959 addr = tx_q->dma_entx; 1960 } else { 1961 size = sizeof(struct dma_desc); 1962 addr = tx_q->dma_tx; 1963 } 1964 1965 size *= dma_conf->dma_tx_size; 1966 1967 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1968 1969 kfree(tx_q->tx_skbuff_dma); 1970 kfree(tx_q->tx_skbuff); 1971 } 1972 1973 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1974 struct stmmac_dma_conf *dma_conf) 1975 { 1976 u32 tx_count = priv->plat->tx_queues_to_use; 1977 u32 queue; 1978 1979 /* Free TX queue resources */ 1980 for (queue = 0; queue < tx_count; queue++) 1981 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1982 } 1983 1984 /** 1985 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1986 * @priv: private structure 1987 * @dma_conf: structure to take the dma data 1988 * @queue: RX queue index 1989 * Description: according to which descriptor can be used (extend or basic) 1990 * this function allocates the resources for TX and RX paths. In case of 1991 * reception, for example, it pre-allocated the RX socket buffer in order to 1992 * allow zero-copy mechanism. 1993 */ 1994 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1995 struct stmmac_dma_conf *dma_conf, 1996 u32 queue) 1997 { 1998 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1999 struct stmmac_channel *ch = &priv->channel[queue]; 2000 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2001 struct page_pool_params pp_params = { 0 }; 2002 unsigned int num_pages; 2003 unsigned int napi_id; 2004 int ret; 2005 2006 rx_q->queue_index = queue; 2007 rx_q->priv_data = priv; 2008 2009 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2010 pp_params.pool_size = dma_conf->dma_rx_size; 2011 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2012 pp_params.order = ilog2(num_pages); 2013 pp_params.nid = dev_to_node(priv->device); 2014 pp_params.dev = priv->device; 2015 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2016 pp_params.offset = stmmac_rx_offset(priv); 2017 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2018 2019 rx_q->page_pool = page_pool_create(&pp_params); 2020 if (IS_ERR(rx_q->page_pool)) { 2021 ret = PTR_ERR(rx_q->page_pool); 2022 rx_q->page_pool = NULL; 2023 return ret; 2024 } 2025 2026 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2027 sizeof(*rx_q->buf_pool), 2028 GFP_KERNEL); 2029 if (!rx_q->buf_pool) 2030 return -ENOMEM; 2031 2032 if (priv->extend_desc) { 2033 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2034 dma_conf->dma_rx_size * 2035 sizeof(struct dma_extended_desc), 2036 &rx_q->dma_rx_phy, 2037 GFP_KERNEL); 2038 if (!rx_q->dma_erx) 2039 return -ENOMEM; 2040 2041 } else { 2042 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2043 dma_conf->dma_rx_size * 2044 sizeof(struct dma_desc), 2045 &rx_q->dma_rx_phy, 2046 GFP_KERNEL); 2047 if (!rx_q->dma_rx) 2048 return -ENOMEM; 2049 } 2050 2051 if (stmmac_xdp_is_enabled(priv) && 2052 test_bit(queue, priv->af_xdp_zc_qps)) 2053 napi_id = ch->rxtx_napi.napi_id; 2054 else 2055 napi_id = ch->rx_napi.napi_id; 2056 2057 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2058 rx_q->queue_index, 2059 napi_id); 2060 if (ret) { 2061 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2062 return -EINVAL; 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2069 struct stmmac_dma_conf *dma_conf) 2070 { 2071 u32 rx_count = priv->plat->rx_queues_to_use; 2072 u32 queue; 2073 int ret; 2074 2075 /* RX queues buffers and DMA */ 2076 for (queue = 0; queue < rx_count; queue++) { 2077 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2078 if (ret) 2079 goto err_dma; 2080 } 2081 2082 return 0; 2083 2084 err_dma: 2085 free_dma_rx_desc_resources(priv, dma_conf); 2086 2087 return ret; 2088 } 2089 2090 /** 2091 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2092 * @priv: private structure 2093 * @dma_conf: structure to take the dma data 2094 * @queue: TX queue index 2095 * Description: according to which descriptor can be used (extend or basic) 2096 * this function allocates the resources for TX and RX paths. In case of 2097 * reception, for example, it pre-allocated the RX socket buffer in order to 2098 * allow zero-copy mechanism. 2099 */ 2100 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2101 struct stmmac_dma_conf *dma_conf, 2102 u32 queue) 2103 { 2104 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2105 size_t size; 2106 void *addr; 2107 2108 tx_q->queue_index = queue; 2109 tx_q->priv_data = priv; 2110 2111 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2112 sizeof(*tx_q->tx_skbuff_dma), 2113 GFP_KERNEL); 2114 if (!tx_q->tx_skbuff_dma) 2115 return -ENOMEM; 2116 2117 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2118 sizeof(struct sk_buff *), 2119 GFP_KERNEL); 2120 if (!tx_q->tx_skbuff) 2121 return -ENOMEM; 2122 2123 if (priv->extend_desc) 2124 size = sizeof(struct dma_extended_desc); 2125 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2126 size = sizeof(struct dma_edesc); 2127 else 2128 size = sizeof(struct dma_desc); 2129 2130 size *= dma_conf->dma_tx_size; 2131 2132 addr = dma_alloc_coherent(priv->device, size, 2133 &tx_q->dma_tx_phy, GFP_KERNEL); 2134 if (!addr) 2135 return -ENOMEM; 2136 2137 if (priv->extend_desc) 2138 tx_q->dma_etx = addr; 2139 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2140 tx_q->dma_entx = addr; 2141 else 2142 tx_q->dma_tx = addr; 2143 2144 return 0; 2145 } 2146 2147 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2148 struct stmmac_dma_conf *dma_conf) 2149 { 2150 u32 tx_count = priv->plat->tx_queues_to_use; 2151 u32 queue; 2152 int ret; 2153 2154 /* TX queues buffers and DMA */ 2155 for (queue = 0; queue < tx_count; queue++) { 2156 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2157 if (ret) 2158 goto err_dma; 2159 } 2160 2161 return 0; 2162 2163 err_dma: 2164 free_dma_tx_desc_resources(priv, dma_conf); 2165 return ret; 2166 } 2167 2168 /** 2169 * alloc_dma_desc_resources - alloc TX/RX resources. 2170 * @priv: private structure 2171 * @dma_conf: structure to take the dma data 2172 * Description: according to which descriptor can be used (extend or basic) 2173 * this function allocates the resources for TX and RX paths. In case of 2174 * reception, for example, it pre-allocated the RX socket buffer in order to 2175 * allow zero-copy mechanism. 2176 */ 2177 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2178 struct stmmac_dma_conf *dma_conf) 2179 { 2180 /* RX Allocation */ 2181 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2182 2183 if (ret) 2184 return ret; 2185 2186 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2187 2188 return ret; 2189 } 2190 2191 /** 2192 * free_dma_desc_resources - free dma desc resources 2193 * @priv: private structure 2194 * @dma_conf: structure to take the dma data 2195 */ 2196 static void free_dma_desc_resources(struct stmmac_priv *priv, 2197 struct stmmac_dma_conf *dma_conf) 2198 { 2199 /* Release the DMA TX socket buffers */ 2200 free_dma_tx_desc_resources(priv, dma_conf); 2201 2202 /* Release the DMA RX socket buffers later 2203 * to ensure all pending XDP_TX buffers are returned. 2204 */ 2205 free_dma_rx_desc_resources(priv, dma_conf); 2206 } 2207 2208 /** 2209 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2210 * @priv: driver private structure 2211 * Description: It is used for enabling the rx queues in the MAC 2212 */ 2213 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2214 { 2215 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2216 int queue; 2217 u8 mode; 2218 2219 for (queue = 0; queue < rx_queues_count; queue++) { 2220 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2221 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2222 } 2223 } 2224 2225 /** 2226 * stmmac_start_rx_dma - start RX DMA channel 2227 * @priv: driver private structure 2228 * @chan: RX channel index 2229 * Description: 2230 * This starts a RX DMA channel 2231 */ 2232 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2233 { 2234 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2235 stmmac_start_rx(priv, priv->ioaddr, chan); 2236 } 2237 2238 /** 2239 * stmmac_start_tx_dma - start TX DMA channel 2240 * @priv: driver private structure 2241 * @chan: TX channel index 2242 * Description: 2243 * This starts a TX DMA channel 2244 */ 2245 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2246 { 2247 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2248 stmmac_start_tx(priv, priv->ioaddr, chan); 2249 } 2250 2251 /** 2252 * stmmac_stop_rx_dma - stop RX DMA channel 2253 * @priv: driver private structure 2254 * @chan: RX channel index 2255 * Description: 2256 * This stops a RX DMA channel 2257 */ 2258 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2259 { 2260 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2261 stmmac_stop_rx(priv, priv->ioaddr, chan); 2262 } 2263 2264 /** 2265 * stmmac_stop_tx_dma - stop TX DMA channel 2266 * @priv: driver private structure 2267 * @chan: TX channel index 2268 * Description: 2269 * This stops a TX DMA channel 2270 */ 2271 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2272 { 2273 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2274 stmmac_stop_tx(priv, priv->ioaddr, chan); 2275 } 2276 2277 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2278 { 2279 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2280 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2281 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2282 u32 chan; 2283 2284 for (chan = 0; chan < dma_csr_ch; chan++) { 2285 struct stmmac_channel *ch = &priv->channel[chan]; 2286 unsigned long flags; 2287 2288 spin_lock_irqsave(&ch->lock, flags); 2289 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2290 spin_unlock_irqrestore(&ch->lock, flags); 2291 } 2292 } 2293 2294 /** 2295 * stmmac_start_all_dma - start all RX and TX DMA channels 2296 * @priv: driver private structure 2297 * Description: 2298 * This starts all the RX and TX DMA channels 2299 */ 2300 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2301 { 2302 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2303 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2304 u32 chan = 0; 2305 2306 for (chan = 0; chan < rx_channels_count; chan++) 2307 stmmac_start_rx_dma(priv, chan); 2308 2309 for (chan = 0; chan < tx_channels_count; chan++) 2310 stmmac_start_tx_dma(priv, chan); 2311 } 2312 2313 /** 2314 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2315 * @priv: driver private structure 2316 * Description: 2317 * This stops the RX and TX DMA channels 2318 */ 2319 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2320 { 2321 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2322 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2323 u32 chan = 0; 2324 2325 for (chan = 0; chan < rx_channels_count; chan++) 2326 stmmac_stop_rx_dma(priv, chan); 2327 2328 for (chan = 0; chan < tx_channels_count; chan++) 2329 stmmac_stop_tx_dma(priv, chan); 2330 } 2331 2332 /** 2333 * stmmac_dma_operation_mode - HW DMA operation mode 2334 * @priv: driver private structure 2335 * Description: it is used for configuring the DMA operation mode register in 2336 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2337 */ 2338 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2339 { 2340 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2341 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2342 int rxfifosz = priv->plat->rx_fifo_size; 2343 int txfifosz = priv->plat->tx_fifo_size; 2344 u32 txmode = 0; 2345 u32 rxmode = 0; 2346 u32 chan = 0; 2347 u8 qmode = 0; 2348 2349 if (rxfifosz == 0) 2350 rxfifosz = priv->dma_cap.rx_fifo_size; 2351 if (txfifosz == 0) 2352 txfifosz = priv->dma_cap.tx_fifo_size; 2353 2354 /* Adjust for real per queue fifo size */ 2355 rxfifosz /= rx_channels_count; 2356 txfifosz /= tx_channels_count; 2357 2358 if (priv->plat->force_thresh_dma_mode) { 2359 txmode = tc; 2360 rxmode = tc; 2361 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2362 /* 2363 * In case of GMAC, SF mode can be enabled 2364 * to perform the TX COE in HW. This depends on: 2365 * 1) TX COE if actually supported 2366 * 2) There is no bugged Jumbo frame support 2367 * that needs to not insert csum in the TDES. 2368 */ 2369 txmode = SF_DMA_MODE; 2370 rxmode = SF_DMA_MODE; 2371 priv->xstats.threshold = SF_DMA_MODE; 2372 } else { 2373 txmode = tc; 2374 rxmode = SF_DMA_MODE; 2375 } 2376 2377 /* configure all channels */ 2378 for (chan = 0; chan < rx_channels_count; chan++) { 2379 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2380 u32 buf_size; 2381 2382 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2383 2384 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2385 rxfifosz, qmode); 2386 2387 if (rx_q->xsk_pool) { 2388 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2389 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2390 buf_size, 2391 chan); 2392 } else { 2393 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2394 priv->dma_conf.dma_buf_sz, 2395 chan); 2396 } 2397 } 2398 2399 for (chan = 0; chan < tx_channels_count; chan++) { 2400 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2401 2402 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2403 txfifosz, qmode); 2404 } 2405 } 2406 2407 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2408 { 2409 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2410 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2411 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2412 unsigned int entry = tx_q->cur_tx; 2413 struct dma_desc *tx_desc = NULL; 2414 struct xdp_desc xdp_desc; 2415 bool work_done = true; 2416 2417 /* Avoids TX time-out as we are sharing with slow path */ 2418 txq_trans_cond_update(nq); 2419 2420 budget = min(budget, stmmac_tx_avail(priv, queue)); 2421 2422 while (budget-- > 0) { 2423 dma_addr_t dma_addr; 2424 bool set_ic; 2425 2426 /* We are sharing with slow path and stop XSK TX desc submission when 2427 * available TX ring is less than threshold. 2428 */ 2429 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2430 !netif_carrier_ok(priv->dev)) { 2431 work_done = false; 2432 break; 2433 } 2434 2435 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2436 break; 2437 2438 if (likely(priv->extend_desc)) 2439 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2440 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2441 tx_desc = &tx_q->dma_entx[entry].basic; 2442 else 2443 tx_desc = tx_q->dma_tx + entry; 2444 2445 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2446 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2447 2448 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2449 2450 /* To return XDP buffer to XSK pool, we simple call 2451 * xsk_tx_completed(), so we don't need to fill up 2452 * 'buf' and 'xdpf'. 2453 */ 2454 tx_q->tx_skbuff_dma[entry].buf = 0; 2455 tx_q->xdpf[entry] = NULL; 2456 2457 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2458 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2459 tx_q->tx_skbuff_dma[entry].last_segment = true; 2460 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2461 2462 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2463 2464 tx_q->tx_count_frames++; 2465 2466 if (!priv->tx_coal_frames[queue]) 2467 set_ic = false; 2468 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2469 set_ic = true; 2470 else 2471 set_ic = false; 2472 2473 if (set_ic) { 2474 tx_q->tx_count_frames = 0; 2475 stmmac_set_tx_ic(priv, tx_desc); 2476 priv->xstats.tx_set_ic_bit++; 2477 } 2478 2479 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2480 true, priv->mode, true, true, 2481 xdp_desc.len); 2482 2483 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2484 2485 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2486 entry = tx_q->cur_tx; 2487 } 2488 2489 if (tx_desc) { 2490 stmmac_flush_tx_descriptors(priv, queue); 2491 xsk_tx_release(pool); 2492 } 2493 2494 /* Return true if all of the 3 conditions are met 2495 * a) TX Budget is still available 2496 * b) work_done = true when XSK TX desc peek is empty (no more 2497 * pending XSK TX for transmission) 2498 */ 2499 return !!budget && work_done; 2500 } 2501 2502 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2503 { 2504 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2505 tc += 64; 2506 2507 if (priv->plat->force_thresh_dma_mode) 2508 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2509 else 2510 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2511 chan); 2512 2513 priv->xstats.threshold = tc; 2514 } 2515 } 2516 2517 /** 2518 * stmmac_tx_clean - to manage the transmission completion 2519 * @priv: driver private structure 2520 * @budget: napi budget limiting this functions packet handling 2521 * @queue: TX queue index 2522 * Description: it reclaims the transmit resources after transmission completes. 2523 */ 2524 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2525 { 2526 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2527 unsigned int bytes_compl = 0, pkts_compl = 0; 2528 unsigned int entry, xmits = 0, count = 0; 2529 2530 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2531 2532 priv->xstats.tx_clean++; 2533 2534 tx_q->xsk_frames_done = 0; 2535 2536 entry = tx_q->dirty_tx; 2537 2538 /* Try to clean all TX complete frame in 1 shot */ 2539 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2540 struct xdp_frame *xdpf; 2541 struct sk_buff *skb; 2542 struct dma_desc *p; 2543 int status; 2544 2545 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2546 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2547 xdpf = tx_q->xdpf[entry]; 2548 skb = NULL; 2549 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2550 xdpf = NULL; 2551 skb = tx_q->tx_skbuff[entry]; 2552 } else { 2553 xdpf = NULL; 2554 skb = NULL; 2555 } 2556 2557 if (priv->extend_desc) 2558 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2559 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2560 p = &tx_q->dma_entx[entry].basic; 2561 else 2562 p = tx_q->dma_tx + entry; 2563 2564 status = stmmac_tx_status(priv, &priv->dev->stats, 2565 &priv->xstats, p, priv->ioaddr); 2566 /* Check if the descriptor is owned by the DMA */ 2567 if (unlikely(status & tx_dma_own)) 2568 break; 2569 2570 count++; 2571 2572 /* Make sure descriptor fields are read after reading 2573 * the own bit. 2574 */ 2575 dma_rmb(); 2576 2577 /* Just consider the last segment and ...*/ 2578 if (likely(!(status & tx_not_ls))) { 2579 /* ... verify the status error condition */ 2580 if (unlikely(status & tx_err)) { 2581 priv->dev->stats.tx_errors++; 2582 if (unlikely(status & tx_err_bump_tc)) 2583 stmmac_bump_dma_threshold(priv, queue); 2584 } else { 2585 priv->dev->stats.tx_packets++; 2586 priv->xstats.tx_pkt_n++; 2587 priv->xstats.txq_stats[queue].tx_pkt_n++; 2588 } 2589 if (skb) 2590 stmmac_get_tx_hwtstamp(priv, p, skb); 2591 } 2592 2593 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2594 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2595 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2596 dma_unmap_page(priv->device, 2597 tx_q->tx_skbuff_dma[entry].buf, 2598 tx_q->tx_skbuff_dma[entry].len, 2599 DMA_TO_DEVICE); 2600 else 2601 dma_unmap_single(priv->device, 2602 tx_q->tx_skbuff_dma[entry].buf, 2603 tx_q->tx_skbuff_dma[entry].len, 2604 DMA_TO_DEVICE); 2605 tx_q->tx_skbuff_dma[entry].buf = 0; 2606 tx_q->tx_skbuff_dma[entry].len = 0; 2607 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2608 } 2609 2610 stmmac_clean_desc3(priv, tx_q, p); 2611 2612 tx_q->tx_skbuff_dma[entry].last_segment = false; 2613 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2614 2615 if (xdpf && 2616 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2617 xdp_return_frame_rx_napi(xdpf); 2618 tx_q->xdpf[entry] = NULL; 2619 } 2620 2621 if (xdpf && 2622 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2623 xdp_return_frame(xdpf); 2624 tx_q->xdpf[entry] = NULL; 2625 } 2626 2627 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2628 tx_q->xsk_frames_done++; 2629 2630 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2631 if (likely(skb)) { 2632 pkts_compl++; 2633 bytes_compl += skb->len; 2634 dev_consume_skb_any(skb); 2635 tx_q->tx_skbuff[entry] = NULL; 2636 } 2637 } 2638 2639 stmmac_release_tx_desc(priv, p, priv->mode); 2640 2641 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2642 } 2643 tx_q->dirty_tx = entry; 2644 2645 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2646 pkts_compl, bytes_compl); 2647 2648 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2649 queue))) && 2650 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2651 2652 netif_dbg(priv, tx_done, priv->dev, 2653 "%s: restart transmit\n", __func__); 2654 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2655 } 2656 2657 if (tx_q->xsk_pool) { 2658 bool work_done; 2659 2660 if (tx_q->xsk_frames_done) 2661 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2662 2663 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2664 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2665 2666 /* For XSK TX, we try to send as many as possible. 2667 * If XSK work done (XSK TX desc empty and budget still 2668 * available), return "budget - 1" to reenable TX IRQ. 2669 * Else, return "budget" to make NAPI continue polling. 2670 */ 2671 work_done = stmmac_xdp_xmit_zc(priv, queue, 2672 STMMAC_XSK_TX_BUDGET_MAX); 2673 if (work_done) 2674 xmits = budget - 1; 2675 else 2676 xmits = budget; 2677 } 2678 2679 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2680 priv->eee_sw_timer_en) { 2681 if (stmmac_enable_eee_mode(priv)) 2682 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2683 } 2684 2685 /* We still have pending packets, let's call for a new scheduling */ 2686 if (tx_q->dirty_tx != tx_q->cur_tx) 2687 hrtimer_start(&tx_q->txtimer, 2688 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2689 HRTIMER_MODE_REL); 2690 2691 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2692 2693 /* Combine decisions from TX clean and XSK TX */ 2694 return max(count, xmits); 2695 } 2696 2697 /** 2698 * stmmac_tx_err - to manage the tx error 2699 * @priv: driver private structure 2700 * @chan: channel index 2701 * Description: it cleans the descriptors and restarts the transmission 2702 * in case of transmission errors. 2703 */ 2704 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2705 { 2706 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2707 2708 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2709 2710 stmmac_stop_tx_dma(priv, chan); 2711 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2712 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2713 stmmac_reset_tx_queue(priv, chan); 2714 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2715 tx_q->dma_tx_phy, chan); 2716 stmmac_start_tx_dma(priv, chan); 2717 2718 priv->dev->stats.tx_errors++; 2719 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2720 } 2721 2722 /** 2723 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2724 * @priv: driver private structure 2725 * @txmode: TX operating mode 2726 * @rxmode: RX operating mode 2727 * @chan: channel index 2728 * Description: it is used for configuring of the DMA operation mode in 2729 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2730 * mode. 2731 */ 2732 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2733 u32 rxmode, u32 chan) 2734 { 2735 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2736 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2737 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2738 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2739 int rxfifosz = priv->plat->rx_fifo_size; 2740 int txfifosz = priv->plat->tx_fifo_size; 2741 2742 if (rxfifosz == 0) 2743 rxfifosz = priv->dma_cap.rx_fifo_size; 2744 if (txfifosz == 0) 2745 txfifosz = priv->dma_cap.tx_fifo_size; 2746 2747 /* Adjust for real per queue fifo size */ 2748 rxfifosz /= rx_channels_count; 2749 txfifosz /= tx_channels_count; 2750 2751 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2752 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2753 } 2754 2755 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2756 { 2757 int ret; 2758 2759 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2760 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2761 if (ret && (ret != -EINVAL)) { 2762 stmmac_global_err(priv); 2763 return true; 2764 } 2765 2766 return false; 2767 } 2768 2769 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2770 { 2771 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2772 &priv->xstats, chan, dir); 2773 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2774 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2775 struct stmmac_channel *ch = &priv->channel[chan]; 2776 struct napi_struct *rx_napi; 2777 struct napi_struct *tx_napi; 2778 unsigned long flags; 2779 2780 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2781 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2782 2783 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2784 if (napi_schedule_prep(rx_napi)) { 2785 spin_lock_irqsave(&ch->lock, flags); 2786 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2787 spin_unlock_irqrestore(&ch->lock, flags); 2788 __napi_schedule(rx_napi); 2789 } 2790 } 2791 2792 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2793 if (napi_schedule_prep(tx_napi)) { 2794 spin_lock_irqsave(&ch->lock, flags); 2795 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2796 spin_unlock_irqrestore(&ch->lock, flags); 2797 __napi_schedule(tx_napi); 2798 } 2799 } 2800 2801 return status; 2802 } 2803 2804 /** 2805 * stmmac_dma_interrupt - DMA ISR 2806 * @priv: driver private structure 2807 * Description: this is the DMA ISR. It is called by the main ISR. 2808 * It calls the dwmac dma routine and schedule poll method in case of some 2809 * work can be done. 2810 */ 2811 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2812 { 2813 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2814 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2815 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2816 tx_channel_count : rx_channel_count; 2817 u32 chan; 2818 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2819 2820 /* Make sure we never check beyond our status buffer. */ 2821 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2822 channels_to_check = ARRAY_SIZE(status); 2823 2824 for (chan = 0; chan < channels_to_check; chan++) 2825 status[chan] = stmmac_napi_check(priv, chan, 2826 DMA_DIR_RXTX); 2827 2828 for (chan = 0; chan < tx_channel_count; chan++) { 2829 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2830 /* Try to bump up the dma threshold on this failure */ 2831 stmmac_bump_dma_threshold(priv, chan); 2832 } else if (unlikely(status[chan] == tx_hard_error)) { 2833 stmmac_tx_err(priv, chan); 2834 } 2835 } 2836 } 2837 2838 /** 2839 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2840 * @priv: driver private structure 2841 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2842 */ 2843 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2844 { 2845 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2846 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2847 2848 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2849 2850 if (priv->dma_cap.rmon) { 2851 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2852 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2853 } else 2854 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2855 } 2856 2857 /** 2858 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2859 * @priv: driver private structure 2860 * Description: 2861 * new GMAC chip generations have a new register to indicate the 2862 * presence of the optional feature/functions. 2863 * This can be also used to override the value passed through the 2864 * platform and necessary for old MAC10/100 and GMAC chips. 2865 */ 2866 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2867 { 2868 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2869 } 2870 2871 /** 2872 * stmmac_check_ether_addr - check if the MAC addr is valid 2873 * @priv: driver private structure 2874 * Description: 2875 * it is to verify if the MAC address is valid, in case of failures it 2876 * generates a random MAC address 2877 */ 2878 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2879 { 2880 u8 addr[ETH_ALEN]; 2881 2882 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2883 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2884 if (is_valid_ether_addr(addr)) 2885 eth_hw_addr_set(priv->dev, addr); 2886 else 2887 eth_hw_addr_random(priv->dev); 2888 dev_info(priv->device, "device MAC address %pM\n", 2889 priv->dev->dev_addr); 2890 } 2891 } 2892 2893 /** 2894 * stmmac_init_dma_engine - DMA init. 2895 * @priv: driver private structure 2896 * Description: 2897 * It inits the DMA invoking the specific MAC/GMAC callback. 2898 * Some DMA parameters can be passed from the platform; 2899 * in case of these are not passed a default is kept for the MAC or GMAC. 2900 */ 2901 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2902 { 2903 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2904 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2905 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2906 struct stmmac_rx_queue *rx_q; 2907 struct stmmac_tx_queue *tx_q; 2908 u32 chan = 0; 2909 int atds = 0; 2910 int ret = 0; 2911 2912 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2913 dev_err(priv->device, "Invalid DMA configuration\n"); 2914 return -EINVAL; 2915 } 2916 2917 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2918 atds = 1; 2919 2920 ret = stmmac_reset(priv, priv->ioaddr); 2921 if (ret) { 2922 dev_err(priv->device, "Failed to reset the dma\n"); 2923 return ret; 2924 } 2925 2926 /* DMA Configuration */ 2927 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2928 2929 if (priv->plat->axi) 2930 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2931 2932 /* DMA CSR Channel configuration */ 2933 for (chan = 0; chan < dma_csr_ch; chan++) { 2934 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2935 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2936 } 2937 2938 /* DMA RX Channel Configuration */ 2939 for (chan = 0; chan < rx_channels_count; chan++) { 2940 rx_q = &priv->dma_conf.rx_queue[chan]; 2941 2942 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2943 rx_q->dma_rx_phy, chan); 2944 2945 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2946 (rx_q->buf_alloc_num * 2947 sizeof(struct dma_desc)); 2948 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2949 rx_q->rx_tail_addr, chan); 2950 } 2951 2952 /* DMA TX Channel Configuration */ 2953 for (chan = 0; chan < tx_channels_count; chan++) { 2954 tx_q = &priv->dma_conf.tx_queue[chan]; 2955 2956 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2957 tx_q->dma_tx_phy, chan); 2958 2959 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2960 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2961 tx_q->tx_tail_addr, chan); 2962 } 2963 2964 return ret; 2965 } 2966 2967 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2968 { 2969 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2970 2971 hrtimer_start(&tx_q->txtimer, 2972 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2973 HRTIMER_MODE_REL); 2974 } 2975 2976 /** 2977 * stmmac_tx_timer - mitigation sw timer for tx. 2978 * @t: data pointer 2979 * Description: 2980 * This is the timer handler to directly invoke the stmmac_tx_clean. 2981 */ 2982 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2983 { 2984 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2985 struct stmmac_priv *priv = tx_q->priv_data; 2986 struct stmmac_channel *ch; 2987 struct napi_struct *napi; 2988 2989 ch = &priv->channel[tx_q->queue_index]; 2990 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2991 2992 if (likely(napi_schedule_prep(napi))) { 2993 unsigned long flags; 2994 2995 spin_lock_irqsave(&ch->lock, flags); 2996 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2997 spin_unlock_irqrestore(&ch->lock, flags); 2998 __napi_schedule(napi); 2999 } 3000 3001 return HRTIMER_NORESTART; 3002 } 3003 3004 /** 3005 * stmmac_init_coalesce - init mitigation options. 3006 * @priv: driver private structure 3007 * Description: 3008 * This inits the coalesce parameters: i.e. timer rate, 3009 * timer handler and default threshold used for enabling the 3010 * interrupt on completion bit. 3011 */ 3012 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3013 { 3014 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3015 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3016 u32 chan; 3017 3018 for (chan = 0; chan < tx_channel_count; chan++) { 3019 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3020 3021 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3022 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3023 3024 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3025 tx_q->txtimer.function = stmmac_tx_timer; 3026 } 3027 3028 for (chan = 0; chan < rx_channel_count; chan++) 3029 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3030 } 3031 3032 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3033 { 3034 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3035 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3036 u32 chan; 3037 3038 /* set TX ring length */ 3039 for (chan = 0; chan < tx_channels_count; chan++) 3040 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3041 (priv->dma_conf.dma_tx_size - 1), chan); 3042 3043 /* set RX ring length */ 3044 for (chan = 0; chan < rx_channels_count; chan++) 3045 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3046 (priv->dma_conf.dma_rx_size - 1), chan); 3047 } 3048 3049 /** 3050 * stmmac_set_tx_queue_weight - Set TX queue weight 3051 * @priv: driver private structure 3052 * Description: It is used for setting TX queues weight 3053 */ 3054 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3055 { 3056 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3057 u32 weight; 3058 u32 queue; 3059 3060 for (queue = 0; queue < tx_queues_count; queue++) { 3061 weight = priv->plat->tx_queues_cfg[queue].weight; 3062 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3063 } 3064 } 3065 3066 /** 3067 * stmmac_configure_cbs - Configure CBS in TX queue 3068 * @priv: driver private structure 3069 * Description: It is used for configuring CBS in AVB TX queues 3070 */ 3071 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3072 { 3073 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3074 u32 mode_to_use; 3075 u32 queue; 3076 3077 /* queue 0 is reserved for legacy traffic */ 3078 for (queue = 1; queue < tx_queues_count; queue++) { 3079 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3080 if (mode_to_use == MTL_QUEUE_DCB) 3081 continue; 3082 3083 stmmac_config_cbs(priv, priv->hw, 3084 priv->plat->tx_queues_cfg[queue].send_slope, 3085 priv->plat->tx_queues_cfg[queue].idle_slope, 3086 priv->plat->tx_queues_cfg[queue].high_credit, 3087 priv->plat->tx_queues_cfg[queue].low_credit, 3088 queue); 3089 } 3090 } 3091 3092 /** 3093 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3094 * @priv: driver private structure 3095 * Description: It is used for mapping RX queues to RX dma channels 3096 */ 3097 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3098 { 3099 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3100 u32 queue; 3101 u32 chan; 3102 3103 for (queue = 0; queue < rx_queues_count; queue++) { 3104 chan = priv->plat->rx_queues_cfg[queue].chan; 3105 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3106 } 3107 } 3108 3109 /** 3110 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3111 * @priv: driver private structure 3112 * Description: It is used for configuring the RX Queue Priority 3113 */ 3114 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3115 { 3116 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3117 u32 queue; 3118 u32 prio; 3119 3120 for (queue = 0; queue < rx_queues_count; queue++) { 3121 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3122 continue; 3123 3124 prio = priv->plat->rx_queues_cfg[queue].prio; 3125 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3126 } 3127 } 3128 3129 /** 3130 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3131 * @priv: driver private structure 3132 * Description: It is used for configuring the TX Queue Priority 3133 */ 3134 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3135 { 3136 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3137 u32 queue; 3138 u32 prio; 3139 3140 for (queue = 0; queue < tx_queues_count; queue++) { 3141 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3142 continue; 3143 3144 prio = priv->plat->tx_queues_cfg[queue].prio; 3145 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3146 } 3147 } 3148 3149 /** 3150 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3151 * @priv: driver private structure 3152 * Description: It is used for configuring the RX queue routing 3153 */ 3154 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3155 { 3156 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3157 u32 queue; 3158 u8 packet; 3159 3160 for (queue = 0; queue < rx_queues_count; queue++) { 3161 /* no specific packet type routing specified for the queue */ 3162 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3163 continue; 3164 3165 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3166 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3167 } 3168 } 3169 3170 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3171 { 3172 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3173 priv->rss.enable = false; 3174 return; 3175 } 3176 3177 if (priv->dev->features & NETIF_F_RXHASH) 3178 priv->rss.enable = true; 3179 else 3180 priv->rss.enable = false; 3181 3182 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3183 priv->plat->rx_queues_to_use); 3184 } 3185 3186 /** 3187 * stmmac_mtl_configuration - Configure MTL 3188 * @priv: driver private structure 3189 * Description: It is used for configurring MTL 3190 */ 3191 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3192 { 3193 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3194 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3195 3196 if (tx_queues_count > 1) 3197 stmmac_set_tx_queue_weight(priv); 3198 3199 /* Configure MTL RX algorithms */ 3200 if (rx_queues_count > 1) 3201 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3202 priv->plat->rx_sched_algorithm); 3203 3204 /* Configure MTL TX algorithms */ 3205 if (tx_queues_count > 1) 3206 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3207 priv->plat->tx_sched_algorithm); 3208 3209 /* Configure CBS in AVB TX queues */ 3210 if (tx_queues_count > 1) 3211 stmmac_configure_cbs(priv); 3212 3213 /* Map RX MTL to DMA channels */ 3214 stmmac_rx_queue_dma_chan_map(priv); 3215 3216 /* Enable MAC RX Queues */ 3217 stmmac_mac_enable_rx_queues(priv); 3218 3219 /* Set RX priorities */ 3220 if (rx_queues_count > 1) 3221 stmmac_mac_config_rx_queues_prio(priv); 3222 3223 /* Set TX priorities */ 3224 if (tx_queues_count > 1) 3225 stmmac_mac_config_tx_queues_prio(priv); 3226 3227 /* Set RX routing */ 3228 if (rx_queues_count > 1) 3229 stmmac_mac_config_rx_queues_routing(priv); 3230 3231 /* Receive Side Scaling */ 3232 if (rx_queues_count > 1) 3233 stmmac_mac_config_rss(priv); 3234 } 3235 3236 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3237 { 3238 if (priv->dma_cap.asp) { 3239 netdev_info(priv->dev, "Enabling Safety Features\n"); 3240 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3241 priv->plat->safety_feat_cfg); 3242 } else { 3243 netdev_info(priv->dev, "No Safety Features support found\n"); 3244 } 3245 } 3246 3247 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3248 { 3249 char *name; 3250 3251 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3252 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3253 3254 name = priv->wq_name; 3255 sprintf(name, "%s-fpe", priv->dev->name); 3256 3257 priv->fpe_wq = create_singlethread_workqueue(name); 3258 if (!priv->fpe_wq) { 3259 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3260 3261 return -ENOMEM; 3262 } 3263 netdev_info(priv->dev, "FPE workqueue start"); 3264 3265 return 0; 3266 } 3267 3268 /** 3269 * stmmac_hw_setup - setup mac in a usable state. 3270 * @dev : pointer to the device structure. 3271 * @ptp_register: register PTP if set 3272 * Description: 3273 * this is the main function to setup the HW in a usable state because the 3274 * dma engine is reset, the core registers are configured (e.g. AXI, 3275 * Checksum features, timers). The DMA is ready to start receiving and 3276 * transmitting. 3277 * Return value: 3278 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3279 * file on failure. 3280 */ 3281 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3282 { 3283 struct stmmac_priv *priv = netdev_priv(dev); 3284 u32 rx_cnt = priv->plat->rx_queues_to_use; 3285 u32 tx_cnt = priv->plat->tx_queues_to_use; 3286 bool sph_en; 3287 u32 chan; 3288 int ret; 3289 3290 /* DMA initialization and SW reset */ 3291 ret = stmmac_init_dma_engine(priv); 3292 if (ret < 0) { 3293 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3294 __func__); 3295 return ret; 3296 } 3297 3298 /* Copy the MAC addr into the HW */ 3299 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3300 3301 /* PS and related bits will be programmed according to the speed */ 3302 if (priv->hw->pcs) { 3303 int speed = priv->plat->mac_port_sel_speed; 3304 3305 if ((speed == SPEED_10) || (speed == SPEED_100) || 3306 (speed == SPEED_1000)) { 3307 priv->hw->ps = speed; 3308 } else { 3309 dev_warn(priv->device, "invalid port speed\n"); 3310 priv->hw->ps = 0; 3311 } 3312 } 3313 3314 /* Initialize the MAC Core */ 3315 stmmac_core_init(priv, priv->hw, dev); 3316 3317 /* Initialize MTL*/ 3318 stmmac_mtl_configuration(priv); 3319 3320 /* Initialize Safety Features */ 3321 stmmac_safety_feat_configuration(priv); 3322 3323 ret = stmmac_rx_ipc(priv, priv->hw); 3324 if (!ret) { 3325 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3326 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3327 priv->hw->rx_csum = 0; 3328 } 3329 3330 /* Enable the MAC Rx/Tx */ 3331 stmmac_mac_set(priv, priv->ioaddr, true); 3332 3333 /* Set the HW DMA mode and the COE */ 3334 stmmac_dma_operation_mode(priv); 3335 3336 stmmac_mmc_setup(priv); 3337 3338 if (ptp_register) { 3339 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3340 if (ret < 0) 3341 netdev_warn(priv->dev, 3342 "failed to enable PTP reference clock: %pe\n", 3343 ERR_PTR(ret)); 3344 } 3345 3346 ret = stmmac_init_ptp(priv); 3347 if (ret == -EOPNOTSUPP) 3348 netdev_info(priv->dev, "PTP not supported by HW\n"); 3349 else if (ret) 3350 netdev_warn(priv->dev, "PTP init failed\n"); 3351 else if (ptp_register) 3352 stmmac_ptp_register(priv); 3353 3354 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3355 3356 /* Convert the timer from msec to usec */ 3357 if (!priv->tx_lpi_timer) 3358 priv->tx_lpi_timer = eee_timer * 1000; 3359 3360 if (priv->use_riwt) { 3361 u32 queue; 3362 3363 for (queue = 0; queue < rx_cnt; queue++) { 3364 if (!priv->rx_riwt[queue]) 3365 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3366 3367 stmmac_rx_watchdog(priv, priv->ioaddr, 3368 priv->rx_riwt[queue], queue); 3369 } 3370 } 3371 3372 if (priv->hw->pcs) 3373 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3374 3375 /* set TX and RX rings length */ 3376 stmmac_set_rings_length(priv); 3377 3378 /* Enable TSO */ 3379 if (priv->tso) { 3380 for (chan = 0; chan < tx_cnt; chan++) { 3381 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3382 3383 /* TSO and TBS cannot co-exist */ 3384 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3385 continue; 3386 3387 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3388 } 3389 } 3390 3391 /* Enable Split Header */ 3392 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3393 for (chan = 0; chan < rx_cnt; chan++) 3394 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3395 3396 3397 /* VLAN Tag Insertion */ 3398 if (priv->dma_cap.vlins) 3399 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3400 3401 /* TBS */ 3402 for (chan = 0; chan < tx_cnt; chan++) { 3403 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3404 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3405 3406 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3407 } 3408 3409 /* Configure real RX and TX queues */ 3410 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3411 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3412 3413 /* Start the ball rolling... */ 3414 stmmac_start_all_dma(priv); 3415 3416 if (priv->dma_cap.fpesel) { 3417 stmmac_fpe_start_wq(priv); 3418 3419 if (priv->plat->fpe_cfg->enable) 3420 stmmac_fpe_handshake(priv, true); 3421 } 3422 3423 return 0; 3424 } 3425 3426 static void stmmac_hw_teardown(struct net_device *dev) 3427 { 3428 struct stmmac_priv *priv = netdev_priv(dev); 3429 3430 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3431 } 3432 3433 static void stmmac_free_irq(struct net_device *dev, 3434 enum request_irq_err irq_err, int irq_idx) 3435 { 3436 struct stmmac_priv *priv = netdev_priv(dev); 3437 int j; 3438 3439 switch (irq_err) { 3440 case REQ_IRQ_ERR_ALL: 3441 irq_idx = priv->plat->tx_queues_to_use; 3442 fallthrough; 3443 case REQ_IRQ_ERR_TX: 3444 for (j = irq_idx - 1; j >= 0; j--) { 3445 if (priv->tx_irq[j] > 0) { 3446 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3447 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3448 } 3449 } 3450 irq_idx = priv->plat->rx_queues_to_use; 3451 fallthrough; 3452 case REQ_IRQ_ERR_RX: 3453 for (j = irq_idx - 1; j >= 0; j--) { 3454 if (priv->rx_irq[j] > 0) { 3455 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3456 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3457 } 3458 } 3459 3460 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3461 free_irq(priv->sfty_ue_irq, dev); 3462 fallthrough; 3463 case REQ_IRQ_ERR_SFTY_UE: 3464 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3465 free_irq(priv->sfty_ce_irq, dev); 3466 fallthrough; 3467 case REQ_IRQ_ERR_SFTY_CE: 3468 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3469 free_irq(priv->lpi_irq, dev); 3470 fallthrough; 3471 case REQ_IRQ_ERR_LPI: 3472 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3473 free_irq(priv->wol_irq, dev); 3474 fallthrough; 3475 case REQ_IRQ_ERR_WOL: 3476 free_irq(dev->irq, dev); 3477 fallthrough; 3478 case REQ_IRQ_ERR_MAC: 3479 case REQ_IRQ_ERR_NO: 3480 /* If MAC IRQ request error, no more IRQ to free */ 3481 break; 3482 } 3483 } 3484 3485 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3486 { 3487 struct stmmac_priv *priv = netdev_priv(dev); 3488 enum request_irq_err irq_err; 3489 cpumask_t cpu_mask; 3490 int irq_idx = 0; 3491 char *int_name; 3492 int ret; 3493 int i; 3494 3495 /* For common interrupt */ 3496 int_name = priv->int_name_mac; 3497 sprintf(int_name, "%s:%s", dev->name, "mac"); 3498 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3499 0, int_name, dev); 3500 if (unlikely(ret < 0)) { 3501 netdev_err(priv->dev, 3502 "%s: alloc mac MSI %d (error: %d)\n", 3503 __func__, dev->irq, ret); 3504 irq_err = REQ_IRQ_ERR_MAC; 3505 goto irq_error; 3506 } 3507 3508 /* Request the Wake IRQ in case of another line 3509 * is used for WoL 3510 */ 3511 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3512 int_name = priv->int_name_wol; 3513 sprintf(int_name, "%s:%s", dev->name, "wol"); 3514 ret = request_irq(priv->wol_irq, 3515 stmmac_mac_interrupt, 3516 0, int_name, dev); 3517 if (unlikely(ret < 0)) { 3518 netdev_err(priv->dev, 3519 "%s: alloc wol MSI %d (error: %d)\n", 3520 __func__, priv->wol_irq, ret); 3521 irq_err = REQ_IRQ_ERR_WOL; 3522 goto irq_error; 3523 } 3524 } 3525 3526 /* Request the LPI IRQ in case of another line 3527 * is used for LPI 3528 */ 3529 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3530 int_name = priv->int_name_lpi; 3531 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3532 ret = request_irq(priv->lpi_irq, 3533 stmmac_mac_interrupt, 3534 0, int_name, dev); 3535 if (unlikely(ret < 0)) { 3536 netdev_err(priv->dev, 3537 "%s: alloc lpi MSI %d (error: %d)\n", 3538 __func__, priv->lpi_irq, ret); 3539 irq_err = REQ_IRQ_ERR_LPI; 3540 goto irq_error; 3541 } 3542 } 3543 3544 /* Request the Safety Feature Correctible Error line in 3545 * case of another line is used 3546 */ 3547 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3548 int_name = priv->int_name_sfty_ce; 3549 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3550 ret = request_irq(priv->sfty_ce_irq, 3551 stmmac_safety_interrupt, 3552 0, int_name, dev); 3553 if (unlikely(ret < 0)) { 3554 netdev_err(priv->dev, 3555 "%s: alloc sfty ce MSI %d (error: %d)\n", 3556 __func__, priv->sfty_ce_irq, ret); 3557 irq_err = REQ_IRQ_ERR_SFTY_CE; 3558 goto irq_error; 3559 } 3560 } 3561 3562 /* Request the Safety Feature Uncorrectible Error line in 3563 * case of another line is used 3564 */ 3565 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3566 int_name = priv->int_name_sfty_ue; 3567 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3568 ret = request_irq(priv->sfty_ue_irq, 3569 stmmac_safety_interrupt, 3570 0, int_name, dev); 3571 if (unlikely(ret < 0)) { 3572 netdev_err(priv->dev, 3573 "%s: alloc sfty ue MSI %d (error: %d)\n", 3574 __func__, priv->sfty_ue_irq, ret); 3575 irq_err = REQ_IRQ_ERR_SFTY_UE; 3576 goto irq_error; 3577 } 3578 } 3579 3580 /* Request Rx MSI irq */ 3581 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3582 if (i >= MTL_MAX_RX_QUEUES) 3583 break; 3584 if (priv->rx_irq[i] == 0) 3585 continue; 3586 3587 int_name = priv->int_name_rx_irq[i]; 3588 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3589 ret = request_irq(priv->rx_irq[i], 3590 stmmac_msi_intr_rx, 3591 0, int_name, &priv->dma_conf.rx_queue[i]); 3592 if (unlikely(ret < 0)) { 3593 netdev_err(priv->dev, 3594 "%s: alloc rx-%d MSI %d (error: %d)\n", 3595 __func__, i, priv->rx_irq[i], ret); 3596 irq_err = REQ_IRQ_ERR_RX; 3597 irq_idx = i; 3598 goto irq_error; 3599 } 3600 cpumask_clear(&cpu_mask); 3601 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3602 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3603 } 3604 3605 /* Request Tx MSI irq */ 3606 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3607 if (i >= MTL_MAX_TX_QUEUES) 3608 break; 3609 if (priv->tx_irq[i] == 0) 3610 continue; 3611 3612 int_name = priv->int_name_tx_irq[i]; 3613 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3614 ret = request_irq(priv->tx_irq[i], 3615 stmmac_msi_intr_tx, 3616 0, int_name, &priv->dma_conf.tx_queue[i]); 3617 if (unlikely(ret < 0)) { 3618 netdev_err(priv->dev, 3619 "%s: alloc tx-%d MSI %d (error: %d)\n", 3620 __func__, i, priv->tx_irq[i], ret); 3621 irq_err = REQ_IRQ_ERR_TX; 3622 irq_idx = i; 3623 goto irq_error; 3624 } 3625 cpumask_clear(&cpu_mask); 3626 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3627 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3628 } 3629 3630 return 0; 3631 3632 irq_error: 3633 stmmac_free_irq(dev, irq_err, irq_idx); 3634 return ret; 3635 } 3636 3637 static int stmmac_request_irq_single(struct net_device *dev) 3638 { 3639 struct stmmac_priv *priv = netdev_priv(dev); 3640 enum request_irq_err irq_err; 3641 int ret; 3642 3643 ret = request_irq(dev->irq, stmmac_interrupt, 3644 IRQF_SHARED, dev->name, dev); 3645 if (unlikely(ret < 0)) { 3646 netdev_err(priv->dev, 3647 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3648 __func__, dev->irq, ret); 3649 irq_err = REQ_IRQ_ERR_MAC; 3650 goto irq_error; 3651 } 3652 3653 /* Request the Wake IRQ in case of another line 3654 * is used for WoL 3655 */ 3656 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3657 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3658 IRQF_SHARED, dev->name, dev); 3659 if (unlikely(ret < 0)) { 3660 netdev_err(priv->dev, 3661 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3662 __func__, priv->wol_irq, ret); 3663 irq_err = REQ_IRQ_ERR_WOL; 3664 goto irq_error; 3665 } 3666 } 3667 3668 /* Request the IRQ lines */ 3669 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3670 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3671 IRQF_SHARED, dev->name, dev); 3672 if (unlikely(ret < 0)) { 3673 netdev_err(priv->dev, 3674 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3675 __func__, priv->lpi_irq, ret); 3676 irq_err = REQ_IRQ_ERR_LPI; 3677 goto irq_error; 3678 } 3679 } 3680 3681 return 0; 3682 3683 irq_error: 3684 stmmac_free_irq(dev, irq_err, 0); 3685 return ret; 3686 } 3687 3688 static int stmmac_request_irq(struct net_device *dev) 3689 { 3690 struct stmmac_priv *priv = netdev_priv(dev); 3691 int ret; 3692 3693 /* Request the IRQ lines */ 3694 if (priv->plat->multi_msi_en) 3695 ret = stmmac_request_irq_multi_msi(dev); 3696 else 3697 ret = stmmac_request_irq_single(dev); 3698 3699 return ret; 3700 } 3701 3702 /** 3703 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3704 * @priv: driver private structure 3705 * @mtu: MTU to setup the dma queue and buf with 3706 * Description: Allocate and generate a dma_conf based on the provided MTU. 3707 * Allocate the Tx/Rx DMA queue and init them. 3708 * Return value: 3709 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3710 */ 3711 static struct stmmac_dma_conf * 3712 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3713 { 3714 struct stmmac_dma_conf *dma_conf; 3715 int chan, bfsize, ret; 3716 3717 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3718 if (!dma_conf) { 3719 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3720 __func__); 3721 return ERR_PTR(-ENOMEM); 3722 } 3723 3724 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3725 if (bfsize < 0) 3726 bfsize = 0; 3727 3728 if (bfsize < BUF_SIZE_16KiB) 3729 bfsize = stmmac_set_bfsize(mtu, 0); 3730 3731 dma_conf->dma_buf_sz = bfsize; 3732 /* Chose the tx/rx size from the already defined one in the 3733 * priv struct. (if defined) 3734 */ 3735 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3736 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3737 3738 if (!dma_conf->dma_tx_size) 3739 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3740 if (!dma_conf->dma_rx_size) 3741 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3742 3743 /* Earlier check for TBS */ 3744 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3745 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3746 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3747 3748 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3749 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3750 } 3751 3752 ret = alloc_dma_desc_resources(priv, dma_conf); 3753 if (ret < 0) { 3754 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3755 __func__); 3756 goto alloc_error; 3757 } 3758 3759 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3760 if (ret < 0) { 3761 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3762 __func__); 3763 goto init_error; 3764 } 3765 3766 return dma_conf; 3767 3768 init_error: 3769 free_dma_desc_resources(priv, dma_conf); 3770 alloc_error: 3771 kfree(dma_conf); 3772 return ERR_PTR(ret); 3773 } 3774 3775 /** 3776 * __stmmac_open - open entry point of the driver 3777 * @dev : pointer to the device structure. 3778 * @dma_conf : structure to take the dma data 3779 * Description: 3780 * This function is the open entry point of the driver. 3781 * Return value: 3782 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3783 * file on failure. 3784 */ 3785 static int __stmmac_open(struct net_device *dev, 3786 struct stmmac_dma_conf *dma_conf) 3787 { 3788 struct stmmac_priv *priv = netdev_priv(dev); 3789 int mode = priv->plat->phy_interface; 3790 u32 chan; 3791 int ret; 3792 3793 ret = pm_runtime_resume_and_get(priv->device); 3794 if (ret < 0) 3795 return ret; 3796 3797 if (priv->hw->pcs != STMMAC_PCS_TBI && 3798 priv->hw->pcs != STMMAC_PCS_RTBI && 3799 (!priv->hw->xpcs || 3800 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3801 ret = stmmac_init_phy(dev); 3802 if (ret) { 3803 netdev_err(priv->dev, 3804 "%s: Cannot attach to PHY (error: %d)\n", 3805 __func__, ret); 3806 goto init_phy_error; 3807 } 3808 } 3809 3810 /* Extra statistics */ 3811 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3812 priv->xstats.threshold = tc; 3813 3814 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3815 3816 buf_sz = dma_conf->dma_buf_sz; 3817 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3818 3819 stmmac_reset_queues_param(priv); 3820 3821 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 3822 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3823 if (ret < 0) { 3824 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3825 __func__); 3826 goto init_error; 3827 } 3828 } 3829 3830 ret = stmmac_hw_setup(dev, true); 3831 if (ret < 0) { 3832 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3833 goto init_error; 3834 } 3835 3836 stmmac_init_coalesce(priv); 3837 3838 phylink_start(priv->phylink); 3839 /* We may have called phylink_speed_down before */ 3840 phylink_speed_up(priv->phylink); 3841 3842 ret = stmmac_request_irq(dev); 3843 if (ret) 3844 goto irq_error; 3845 3846 stmmac_enable_all_queues(priv); 3847 netif_tx_start_all_queues(priv->dev); 3848 stmmac_enable_all_dma_irq(priv); 3849 3850 return 0; 3851 3852 irq_error: 3853 phylink_stop(priv->phylink); 3854 3855 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3856 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3857 3858 stmmac_hw_teardown(dev); 3859 init_error: 3860 free_dma_desc_resources(priv, &priv->dma_conf); 3861 phylink_disconnect_phy(priv->phylink); 3862 init_phy_error: 3863 pm_runtime_put(priv->device); 3864 return ret; 3865 } 3866 3867 static int stmmac_open(struct net_device *dev) 3868 { 3869 struct stmmac_priv *priv = netdev_priv(dev); 3870 struct stmmac_dma_conf *dma_conf; 3871 int ret; 3872 3873 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3874 if (IS_ERR(dma_conf)) 3875 return PTR_ERR(dma_conf); 3876 3877 ret = __stmmac_open(dev, dma_conf); 3878 kfree(dma_conf); 3879 return ret; 3880 } 3881 3882 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3883 { 3884 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3885 3886 if (priv->fpe_wq) 3887 destroy_workqueue(priv->fpe_wq); 3888 3889 netdev_info(priv->dev, "FPE workqueue stop"); 3890 } 3891 3892 /** 3893 * stmmac_release - close entry point of the driver 3894 * @dev : device pointer. 3895 * Description: 3896 * This is the stop entry point of the driver. 3897 */ 3898 static int stmmac_release(struct net_device *dev) 3899 { 3900 struct stmmac_priv *priv = netdev_priv(dev); 3901 u32 chan; 3902 3903 if (device_may_wakeup(priv->device)) 3904 phylink_speed_down(priv->phylink, false); 3905 /* Stop and disconnect the PHY */ 3906 phylink_stop(priv->phylink); 3907 phylink_disconnect_phy(priv->phylink); 3908 3909 stmmac_disable_all_queues(priv); 3910 3911 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3912 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3913 3914 netif_tx_disable(dev); 3915 3916 /* Free the IRQ lines */ 3917 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3918 3919 if (priv->eee_enabled) { 3920 priv->tx_path_in_lpi_mode = false; 3921 del_timer_sync(&priv->eee_ctrl_timer); 3922 } 3923 3924 /* Stop TX/RX DMA and clear the descriptors */ 3925 stmmac_stop_all_dma(priv); 3926 3927 /* Release and free the Rx/Tx resources */ 3928 free_dma_desc_resources(priv, &priv->dma_conf); 3929 3930 /* Disable the MAC Rx/Tx */ 3931 stmmac_mac_set(priv, priv->ioaddr, false); 3932 3933 /* Powerdown Serdes if there is */ 3934 if (priv->plat->serdes_powerdown) 3935 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3936 3937 netif_carrier_off(dev); 3938 3939 stmmac_release_ptp(priv); 3940 3941 pm_runtime_put(priv->device); 3942 3943 if (priv->dma_cap.fpesel) 3944 stmmac_fpe_stop_wq(priv); 3945 3946 return 0; 3947 } 3948 3949 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3950 struct stmmac_tx_queue *tx_q) 3951 { 3952 u16 tag = 0x0, inner_tag = 0x0; 3953 u32 inner_type = 0x0; 3954 struct dma_desc *p; 3955 3956 if (!priv->dma_cap.vlins) 3957 return false; 3958 if (!skb_vlan_tag_present(skb)) 3959 return false; 3960 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3961 inner_tag = skb_vlan_tag_get(skb); 3962 inner_type = STMMAC_VLAN_INSERT; 3963 } 3964 3965 tag = skb_vlan_tag_get(skb); 3966 3967 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3968 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3969 else 3970 p = &tx_q->dma_tx[tx_q->cur_tx]; 3971 3972 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3973 return false; 3974 3975 stmmac_set_tx_owner(priv, p); 3976 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3977 return true; 3978 } 3979 3980 /** 3981 * stmmac_tso_allocator - close entry point of the driver 3982 * @priv: driver private structure 3983 * @des: buffer start address 3984 * @total_len: total length to fill in descriptors 3985 * @last_segment: condition for the last descriptor 3986 * @queue: TX queue index 3987 * Description: 3988 * This function fills descriptor and request new descriptors according to 3989 * buffer length to fill 3990 */ 3991 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3992 int total_len, bool last_segment, u32 queue) 3993 { 3994 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3995 struct dma_desc *desc; 3996 u32 buff_size; 3997 int tmp_len; 3998 3999 tmp_len = total_len; 4000 4001 while (tmp_len > 0) { 4002 dma_addr_t curr_addr; 4003 4004 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4005 priv->dma_conf.dma_tx_size); 4006 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4007 4008 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4009 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4010 else 4011 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4012 4013 curr_addr = des + (total_len - tmp_len); 4014 if (priv->dma_cap.addr64 <= 32) 4015 desc->des0 = cpu_to_le32(curr_addr); 4016 else 4017 stmmac_set_desc_addr(priv, desc, curr_addr); 4018 4019 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4020 TSO_MAX_BUFF_SIZE : tmp_len; 4021 4022 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4023 0, 1, 4024 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4025 0, 0); 4026 4027 tmp_len -= TSO_MAX_BUFF_SIZE; 4028 } 4029 } 4030 4031 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4032 { 4033 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4034 int desc_size; 4035 4036 if (likely(priv->extend_desc)) 4037 desc_size = sizeof(struct dma_extended_desc); 4038 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4039 desc_size = sizeof(struct dma_edesc); 4040 else 4041 desc_size = sizeof(struct dma_desc); 4042 4043 /* The own bit must be the latest setting done when prepare the 4044 * descriptor and then barrier is needed to make sure that 4045 * all is coherent before granting the DMA engine. 4046 */ 4047 wmb(); 4048 4049 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4050 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4051 } 4052 4053 /** 4054 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4055 * @skb : the socket buffer 4056 * @dev : device pointer 4057 * Description: this is the transmit function that is called on TSO frames 4058 * (support available on GMAC4 and newer chips). 4059 * Diagram below show the ring programming in case of TSO frames: 4060 * 4061 * First Descriptor 4062 * -------- 4063 * | DES0 |---> buffer1 = L2/L3/L4 header 4064 * | DES1 |---> TCP Payload (can continue on next descr...) 4065 * | DES2 |---> buffer 1 and 2 len 4066 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4067 * -------- 4068 * | 4069 * ... 4070 * | 4071 * -------- 4072 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4073 * | DES1 | --| 4074 * | DES2 | --> buffer 1 and 2 len 4075 * | DES3 | 4076 * -------- 4077 * 4078 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4079 */ 4080 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4081 { 4082 struct dma_desc *desc, *first, *mss_desc = NULL; 4083 struct stmmac_priv *priv = netdev_priv(dev); 4084 int nfrags = skb_shinfo(skb)->nr_frags; 4085 u32 queue = skb_get_queue_mapping(skb); 4086 unsigned int first_entry, tx_packets; 4087 int tmp_pay_len = 0, first_tx; 4088 struct stmmac_tx_queue *tx_q; 4089 bool has_vlan, set_ic; 4090 u8 proto_hdr_len, hdr; 4091 u32 pay_len, mss; 4092 dma_addr_t des; 4093 int i; 4094 4095 tx_q = &priv->dma_conf.tx_queue[queue]; 4096 first_tx = tx_q->cur_tx; 4097 4098 /* Compute header lengths */ 4099 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4100 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4101 hdr = sizeof(struct udphdr); 4102 } else { 4103 proto_hdr_len = skb_tcp_all_headers(skb); 4104 hdr = tcp_hdrlen(skb); 4105 } 4106 4107 /* Desc availability based on threshold should be enough safe */ 4108 if (unlikely(stmmac_tx_avail(priv, queue) < 4109 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4110 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4111 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4112 queue)); 4113 /* This is a hard error, log it. */ 4114 netdev_err(priv->dev, 4115 "%s: Tx Ring full when queue awake\n", 4116 __func__); 4117 } 4118 return NETDEV_TX_BUSY; 4119 } 4120 4121 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4122 4123 mss = skb_shinfo(skb)->gso_size; 4124 4125 /* set new MSS value if needed */ 4126 if (mss != tx_q->mss) { 4127 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4128 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4129 else 4130 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4131 4132 stmmac_set_mss(priv, mss_desc, mss); 4133 tx_q->mss = mss; 4134 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4135 priv->dma_conf.dma_tx_size); 4136 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4137 } 4138 4139 if (netif_msg_tx_queued(priv)) { 4140 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4141 __func__, hdr, proto_hdr_len, pay_len, mss); 4142 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4143 skb->data_len); 4144 } 4145 4146 /* Check if VLAN can be inserted by HW */ 4147 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4148 4149 first_entry = tx_q->cur_tx; 4150 WARN_ON(tx_q->tx_skbuff[first_entry]); 4151 4152 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4153 desc = &tx_q->dma_entx[first_entry].basic; 4154 else 4155 desc = &tx_q->dma_tx[first_entry]; 4156 first = desc; 4157 4158 if (has_vlan) 4159 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4160 4161 /* first descriptor: fill Headers on Buf1 */ 4162 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4163 DMA_TO_DEVICE); 4164 if (dma_mapping_error(priv->device, des)) 4165 goto dma_map_err; 4166 4167 tx_q->tx_skbuff_dma[first_entry].buf = des; 4168 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4169 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4170 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4171 4172 if (priv->dma_cap.addr64 <= 32) { 4173 first->des0 = cpu_to_le32(des); 4174 4175 /* Fill start of payload in buff2 of first descriptor */ 4176 if (pay_len) 4177 first->des1 = cpu_to_le32(des + proto_hdr_len); 4178 4179 /* If needed take extra descriptors to fill the remaining payload */ 4180 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4181 } else { 4182 stmmac_set_desc_addr(priv, first, des); 4183 tmp_pay_len = pay_len; 4184 des += proto_hdr_len; 4185 pay_len = 0; 4186 } 4187 4188 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4189 4190 /* Prepare fragments */ 4191 for (i = 0; i < nfrags; i++) { 4192 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4193 4194 des = skb_frag_dma_map(priv->device, frag, 0, 4195 skb_frag_size(frag), 4196 DMA_TO_DEVICE); 4197 if (dma_mapping_error(priv->device, des)) 4198 goto dma_map_err; 4199 4200 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4201 (i == nfrags - 1), queue); 4202 4203 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4204 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4205 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4206 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4207 } 4208 4209 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4210 4211 /* Only the last descriptor gets to point to the skb. */ 4212 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4213 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4214 4215 /* Manage tx mitigation */ 4216 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4217 tx_q->tx_count_frames += tx_packets; 4218 4219 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4220 set_ic = true; 4221 else if (!priv->tx_coal_frames[queue]) 4222 set_ic = false; 4223 else if (tx_packets > priv->tx_coal_frames[queue]) 4224 set_ic = true; 4225 else if ((tx_q->tx_count_frames % 4226 priv->tx_coal_frames[queue]) < tx_packets) 4227 set_ic = true; 4228 else 4229 set_ic = false; 4230 4231 if (set_ic) { 4232 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4233 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4234 else 4235 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4236 4237 tx_q->tx_count_frames = 0; 4238 stmmac_set_tx_ic(priv, desc); 4239 priv->xstats.tx_set_ic_bit++; 4240 } 4241 4242 /* We've used all descriptors we need for this skb, however, 4243 * advance cur_tx so that it references a fresh descriptor. 4244 * ndo_start_xmit will fill this descriptor the next time it's 4245 * called and stmmac_tx_clean may clean up to this descriptor. 4246 */ 4247 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4248 4249 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4250 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4251 __func__); 4252 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4253 } 4254 4255 dev->stats.tx_bytes += skb->len; 4256 priv->xstats.tx_tso_frames++; 4257 priv->xstats.tx_tso_nfrags += nfrags; 4258 4259 if (priv->sarc_type) 4260 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4261 4262 skb_tx_timestamp(skb); 4263 4264 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4265 priv->hwts_tx_en)) { 4266 /* declare that device is doing timestamping */ 4267 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4268 stmmac_enable_tx_timestamp(priv, first); 4269 } 4270 4271 /* Complete the first descriptor before granting the DMA */ 4272 stmmac_prepare_tso_tx_desc(priv, first, 1, 4273 proto_hdr_len, 4274 pay_len, 4275 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4276 hdr / 4, (skb->len - proto_hdr_len)); 4277 4278 /* If context desc is used to change MSS */ 4279 if (mss_desc) { 4280 /* Make sure that first descriptor has been completely 4281 * written, including its own bit. This is because MSS is 4282 * actually before first descriptor, so we need to make 4283 * sure that MSS's own bit is the last thing written. 4284 */ 4285 dma_wmb(); 4286 stmmac_set_tx_owner(priv, mss_desc); 4287 } 4288 4289 if (netif_msg_pktdata(priv)) { 4290 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4291 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4292 tx_q->cur_tx, first, nfrags); 4293 pr_info(">>> frame to be transmitted: "); 4294 print_pkt(skb->data, skb_headlen(skb)); 4295 } 4296 4297 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4298 4299 stmmac_flush_tx_descriptors(priv, queue); 4300 stmmac_tx_timer_arm(priv, queue); 4301 4302 return NETDEV_TX_OK; 4303 4304 dma_map_err: 4305 dev_err(priv->device, "Tx dma map failed\n"); 4306 dev_kfree_skb(skb); 4307 priv->dev->stats.tx_dropped++; 4308 return NETDEV_TX_OK; 4309 } 4310 4311 /** 4312 * stmmac_xmit - Tx entry point of the driver 4313 * @skb : the socket buffer 4314 * @dev : device pointer 4315 * Description : this is the tx entry point of the driver. 4316 * It programs the chain or the ring and supports oversized frames 4317 * and SG feature. 4318 */ 4319 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4320 { 4321 unsigned int first_entry, tx_packets, enh_desc; 4322 struct stmmac_priv *priv = netdev_priv(dev); 4323 unsigned int nopaged_len = skb_headlen(skb); 4324 int i, csum_insertion = 0, is_jumbo = 0; 4325 u32 queue = skb_get_queue_mapping(skb); 4326 int nfrags = skb_shinfo(skb)->nr_frags; 4327 int gso = skb_shinfo(skb)->gso_type; 4328 struct dma_edesc *tbs_desc = NULL; 4329 struct dma_desc *desc, *first; 4330 struct stmmac_tx_queue *tx_q; 4331 bool has_vlan, set_ic; 4332 int entry, first_tx; 4333 dma_addr_t des; 4334 4335 tx_q = &priv->dma_conf.tx_queue[queue]; 4336 first_tx = tx_q->cur_tx; 4337 4338 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4339 stmmac_disable_eee_mode(priv); 4340 4341 /* Manage oversized TCP frames for GMAC4 device */ 4342 if (skb_is_gso(skb) && priv->tso) { 4343 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4344 return stmmac_tso_xmit(skb, dev); 4345 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4346 return stmmac_tso_xmit(skb, dev); 4347 } 4348 4349 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4350 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4351 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4352 queue)); 4353 /* This is a hard error, log it. */ 4354 netdev_err(priv->dev, 4355 "%s: Tx Ring full when queue awake\n", 4356 __func__); 4357 } 4358 return NETDEV_TX_BUSY; 4359 } 4360 4361 /* Check if VLAN can be inserted by HW */ 4362 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4363 4364 entry = tx_q->cur_tx; 4365 first_entry = entry; 4366 WARN_ON(tx_q->tx_skbuff[first_entry]); 4367 4368 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4369 4370 if (likely(priv->extend_desc)) 4371 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4372 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4373 desc = &tx_q->dma_entx[entry].basic; 4374 else 4375 desc = tx_q->dma_tx + entry; 4376 4377 first = desc; 4378 4379 if (has_vlan) 4380 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4381 4382 enh_desc = priv->plat->enh_desc; 4383 /* To program the descriptors according to the size of the frame */ 4384 if (enh_desc) 4385 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4386 4387 if (unlikely(is_jumbo)) { 4388 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4389 if (unlikely(entry < 0) && (entry != -EINVAL)) 4390 goto dma_map_err; 4391 } 4392 4393 for (i = 0; i < nfrags; i++) { 4394 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4395 int len = skb_frag_size(frag); 4396 bool last_segment = (i == (nfrags - 1)); 4397 4398 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4399 WARN_ON(tx_q->tx_skbuff[entry]); 4400 4401 if (likely(priv->extend_desc)) 4402 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4403 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4404 desc = &tx_q->dma_entx[entry].basic; 4405 else 4406 desc = tx_q->dma_tx + entry; 4407 4408 des = skb_frag_dma_map(priv->device, frag, 0, len, 4409 DMA_TO_DEVICE); 4410 if (dma_mapping_error(priv->device, des)) 4411 goto dma_map_err; /* should reuse desc w/o issues */ 4412 4413 tx_q->tx_skbuff_dma[entry].buf = des; 4414 4415 stmmac_set_desc_addr(priv, desc, des); 4416 4417 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4418 tx_q->tx_skbuff_dma[entry].len = len; 4419 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4420 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4421 4422 /* Prepare the descriptor and set the own bit too */ 4423 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4424 priv->mode, 1, last_segment, skb->len); 4425 } 4426 4427 /* Only the last descriptor gets to point to the skb. */ 4428 tx_q->tx_skbuff[entry] = skb; 4429 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4430 4431 /* According to the coalesce parameter the IC bit for the latest 4432 * segment is reset and the timer re-started to clean the tx status. 4433 * This approach takes care about the fragments: desc is the first 4434 * element in case of no SG. 4435 */ 4436 tx_packets = (entry + 1) - first_tx; 4437 tx_q->tx_count_frames += tx_packets; 4438 4439 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4440 set_ic = true; 4441 else if (!priv->tx_coal_frames[queue]) 4442 set_ic = false; 4443 else if (tx_packets > priv->tx_coal_frames[queue]) 4444 set_ic = true; 4445 else if ((tx_q->tx_count_frames % 4446 priv->tx_coal_frames[queue]) < tx_packets) 4447 set_ic = true; 4448 else 4449 set_ic = false; 4450 4451 if (set_ic) { 4452 if (likely(priv->extend_desc)) 4453 desc = &tx_q->dma_etx[entry].basic; 4454 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4455 desc = &tx_q->dma_entx[entry].basic; 4456 else 4457 desc = &tx_q->dma_tx[entry]; 4458 4459 tx_q->tx_count_frames = 0; 4460 stmmac_set_tx_ic(priv, desc); 4461 priv->xstats.tx_set_ic_bit++; 4462 } 4463 4464 /* We've used all descriptors we need for this skb, however, 4465 * advance cur_tx so that it references a fresh descriptor. 4466 * ndo_start_xmit will fill this descriptor the next time it's 4467 * called and stmmac_tx_clean may clean up to this descriptor. 4468 */ 4469 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4470 tx_q->cur_tx = entry; 4471 4472 if (netif_msg_pktdata(priv)) { 4473 netdev_dbg(priv->dev, 4474 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4475 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4476 entry, first, nfrags); 4477 4478 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4479 print_pkt(skb->data, skb->len); 4480 } 4481 4482 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4483 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4484 __func__); 4485 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4486 } 4487 4488 dev->stats.tx_bytes += skb->len; 4489 4490 if (priv->sarc_type) 4491 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4492 4493 skb_tx_timestamp(skb); 4494 4495 /* Ready to fill the first descriptor and set the OWN bit w/o any 4496 * problems because all the descriptors are actually ready to be 4497 * passed to the DMA engine. 4498 */ 4499 if (likely(!is_jumbo)) { 4500 bool last_segment = (nfrags == 0); 4501 4502 des = dma_map_single(priv->device, skb->data, 4503 nopaged_len, DMA_TO_DEVICE); 4504 if (dma_mapping_error(priv->device, des)) 4505 goto dma_map_err; 4506 4507 tx_q->tx_skbuff_dma[first_entry].buf = des; 4508 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4509 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4510 4511 stmmac_set_desc_addr(priv, first, des); 4512 4513 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4514 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4515 4516 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4517 priv->hwts_tx_en)) { 4518 /* declare that device is doing timestamping */ 4519 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4520 stmmac_enable_tx_timestamp(priv, first); 4521 } 4522 4523 /* Prepare the first descriptor setting the OWN bit too */ 4524 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4525 csum_insertion, priv->mode, 0, last_segment, 4526 skb->len); 4527 } 4528 4529 if (tx_q->tbs & STMMAC_TBS_EN) { 4530 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4531 4532 tbs_desc = &tx_q->dma_entx[first_entry]; 4533 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4534 } 4535 4536 stmmac_set_tx_owner(priv, first); 4537 4538 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4539 4540 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4541 4542 stmmac_flush_tx_descriptors(priv, queue); 4543 stmmac_tx_timer_arm(priv, queue); 4544 4545 return NETDEV_TX_OK; 4546 4547 dma_map_err: 4548 netdev_err(priv->dev, "Tx DMA map failed\n"); 4549 dev_kfree_skb(skb); 4550 priv->dev->stats.tx_dropped++; 4551 return NETDEV_TX_OK; 4552 } 4553 4554 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4555 { 4556 struct vlan_ethhdr *veth; 4557 __be16 vlan_proto; 4558 u16 vlanid; 4559 4560 veth = (struct vlan_ethhdr *)skb->data; 4561 vlan_proto = veth->h_vlan_proto; 4562 4563 if ((vlan_proto == htons(ETH_P_8021Q) && 4564 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4565 (vlan_proto == htons(ETH_P_8021AD) && 4566 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4567 /* pop the vlan tag */ 4568 vlanid = ntohs(veth->h_vlan_TCI); 4569 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4570 skb_pull(skb, VLAN_HLEN); 4571 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4572 } 4573 } 4574 4575 /** 4576 * stmmac_rx_refill - refill used skb preallocated buffers 4577 * @priv: driver private structure 4578 * @queue: RX queue index 4579 * Description : this is to reallocate the skb for the reception process 4580 * that is based on zero-copy. 4581 */ 4582 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4583 { 4584 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4585 int dirty = stmmac_rx_dirty(priv, queue); 4586 unsigned int entry = rx_q->dirty_rx; 4587 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4588 4589 if (priv->dma_cap.addr64 <= 32) 4590 gfp |= GFP_DMA32; 4591 4592 while (dirty-- > 0) { 4593 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4594 struct dma_desc *p; 4595 bool use_rx_wd; 4596 4597 if (priv->extend_desc) 4598 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4599 else 4600 p = rx_q->dma_rx + entry; 4601 4602 if (!buf->page) { 4603 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4604 if (!buf->page) 4605 break; 4606 } 4607 4608 if (priv->sph && !buf->sec_page) { 4609 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4610 if (!buf->sec_page) 4611 break; 4612 4613 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4614 } 4615 4616 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4617 4618 stmmac_set_desc_addr(priv, p, buf->addr); 4619 if (priv->sph) 4620 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4621 else 4622 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4623 stmmac_refill_desc3(priv, rx_q, p); 4624 4625 rx_q->rx_count_frames++; 4626 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4627 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4628 rx_q->rx_count_frames = 0; 4629 4630 use_rx_wd = !priv->rx_coal_frames[queue]; 4631 use_rx_wd |= rx_q->rx_count_frames > 0; 4632 if (!priv->use_riwt) 4633 use_rx_wd = false; 4634 4635 dma_wmb(); 4636 stmmac_set_rx_owner(priv, p, use_rx_wd); 4637 4638 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4639 } 4640 rx_q->dirty_rx = entry; 4641 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4642 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4643 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4644 } 4645 4646 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4647 struct dma_desc *p, 4648 int status, unsigned int len) 4649 { 4650 unsigned int plen = 0, hlen = 0; 4651 int coe = priv->hw->rx_csum; 4652 4653 /* Not first descriptor, buffer is always zero */ 4654 if (priv->sph && len) 4655 return 0; 4656 4657 /* First descriptor, get split header length */ 4658 stmmac_get_rx_header_len(priv, p, &hlen); 4659 if (priv->sph && hlen) { 4660 priv->xstats.rx_split_hdr_pkt_n++; 4661 return hlen; 4662 } 4663 4664 /* First descriptor, not last descriptor and not split header */ 4665 if (status & rx_not_ls) 4666 return priv->dma_conf.dma_buf_sz; 4667 4668 plen = stmmac_get_rx_frame_len(priv, p, coe); 4669 4670 /* First descriptor and last descriptor and not split header */ 4671 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4672 } 4673 4674 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4675 struct dma_desc *p, 4676 int status, unsigned int len) 4677 { 4678 int coe = priv->hw->rx_csum; 4679 unsigned int plen = 0; 4680 4681 /* Not split header, buffer is not available */ 4682 if (!priv->sph) 4683 return 0; 4684 4685 /* Not last descriptor */ 4686 if (status & rx_not_ls) 4687 return priv->dma_conf.dma_buf_sz; 4688 4689 plen = stmmac_get_rx_frame_len(priv, p, coe); 4690 4691 /* Last descriptor */ 4692 return plen - len; 4693 } 4694 4695 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4696 struct xdp_frame *xdpf, bool dma_map) 4697 { 4698 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4699 unsigned int entry = tx_q->cur_tx; 4700 struct dma_desc *tx_desc; 4701 dma_addr_t dma_addr; 4702 bool set_ic; 4703 4704 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4705 return STMMAC_XDP_CONSUMED; 4706 4707 if (likely(priv->extend_desc)) 4708 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4709 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4710 tx_desc = &tx_q->dma_entx[entry].basic; 4711 else 4712 tx_desc = tx_q->dma_tx + entry; 4713 4714 if (dma_map) { 4715 dma_addr = dma_map_single(priv->device, xdpf->data, 4716 xdpf->len, DMA_TO_DEVICE); 4717 if (dma_mapping_error(priv->device, dma_addr)) 4718 return STMMAC_XDP_CONSUMED; 4719 4720 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4721 } else { 4722 struct page *page = virt_to_page(xdpf->data); 4723 4724 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4725 xdpf->headroom; 4726 dma_sync_single_for_device(priv->device, dma_addr, 4727 xdpf->len, DMA_BIDIRECTIONAL); 4728 4729 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4730 } 4731 4732 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4733 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4734 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4735 tx_q->tx_skbuff_dma[entry].last_segment = true; 4736 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4737 4738 tx_q->xdpf[entry] = xdpf; 4739 4740 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4741 4742 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4743 true, priv->mode, true, true, 4744 xdpf->len); 4745 4746 tx_q->tx_count_frames++; 4747 4748 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4749 set_ic = true; 4750 else 4751 set_ic = false; 4752 4753 if (set_ic) { 4754 tx_q->tx_count_frames = 0; 4755 stmmac_set_tx_ic(priv, tx_desc); 4756 priv->xstats.tx_set_ic_bit++; 4757 } 4758 4759 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4760 4761 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4762 tx_q->cur_tx = entry; 4763 4764 return STMMAC_XDP_TX; 4765 } 4766 4767 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4768 int cpu) 4769 { 4770 int index = cpu; 4771 4772 if (unlikely(index < 0)) 4773 index = 0; 4774 4775 while (index >= priv->plat->tx_queues_to_use) 4776 index -= priv->plat->tx_queues_to_use; 4777 4778 return index; 4779 } 4780 4781 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4782 struct xdp_buff *xdp) 4783 { 4784 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4785 int cpu = smp_processor_id(); 4786 struct netdev_queue *nq; 4787 int queue; 4788 int res; 4789 4790 if (unlikely(!xdpf)) 4791 return STMMAC_XDP_CONSUMED; 4792 4793 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4794 nq = netdev_get_tx_queue(priv->dev, queue); 4795 4796 __netif_tx_lock(nq, cpu); 4797 /* Avoids TX time-out as we are sharing with slow path */ 4798 txq_trans_cond_update(nq); 4799 4800 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4801 if (res == STMMAC_XDP_TX) 4802 stmmac_flush_tx_descriptors(priv, queue); 4803 4804 __netif_tx_unlock(nq); 4805 4806 return res; 4807 } 4808 4809 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4810 struct bpf_prog *prog, 4811 struct xdp_buff *xdp) 4812 { 4813 u32 act; 4814 int res; 4815 4816 act = bpf_prog_run_xdp(prog, xdp); 4817 switch (act) { 4818 case XDP_PASS: 4819 res = STMMAC_XDP_PASS; 4820 break; 4821 case XDP_TX: 4822 res = stmmac_xdp_xmit_back(priv, xdp); 4823 break; 4824 case XDP_REDIRECT: 4825 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4826 res = STMMAC_XDP_CONSUMED; 4827 else 4828 res = STMMAC_XDP_REDIRECT; 4829 break; 4830 default: 4831 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4832 fallthrough; 4833 case XDP_ABORTED: 4834 trace_xdp_exception(priv->dev, prog, act); 4835 fallthrough; 4836 case XDP_DROP: 4837 res = STMMAC_XDP_CONSUMED; 4838 break; 4839 } 4840 4841 return res; 4842 } 4843 4844 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4845 struct xdp_buff *xdp) 4846 { 4847 struct bpf_prog *prog; 4848 int res; 4849 4850 prog = READ_ONCE(priv->xdp_prog); 4851 if (!prog) { 4852 res = STMMAC_XDP_PASS; 4853 goto out; 4854 } 4855 4856 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4857 out: 4858 return ERR_PTR(-res); 4859 } 4860 4861 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4862 int xdp_status) 4863 { 4864 int cpu = smp_processor_id(); 4865 int queue; 4866 4867 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4868 4869 if (xdp_status & STMMAC_XDP_TX) 4870 stmmac_tx_timer_arm(priv, queue); 4871 4872 if (xdp_status & STMMAC_XDP_REDIRECT) 4873 xdp_do_flush(); 4874 } 4875 4876 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4877 struct xdp_buff *xdp) 4878 { 4879 unsigned int metasize = xdp->data - xdp->data_meta; 4880 unsigned int datasize = xdp->data_end - xdp->data; 4881 struct sk_buff *skb; 4882 4883 skb = __napi_alloc_skb(&ch->rxtx_napi, 4884 xdp->data_end - xdp->data_hard_start, 4885 GFP_ATOMIC | __GFP_NOWARN); 4886 if (unlikely(!skb)) 4887 return NULL; 4888 4889 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4890 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4891 if (metasize) 4892 skb_metadata_set(skb, metasize); 4893 4894 return skb; 4895 } 4896 4897 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4898 struct dma_desc *p, struct dma_desc *np, 4899 struct xdp_buff *xdp) 4900 { 4901 struct stmmac_channel *ch = &priv->channel[queue]; 4902 unsigned int len = xdp->data_end - xdp->data; 4903 enum pkt_hash_types hash_type; 4904 int coe = priv->hw->rx_csum; 4905 struct sk_buff *skb; 4906 u32 hash; 4907 4908 skb = stmmac_construct_skb_zc(ch, xdp); 4909 if (!skb) { 4910 priv->dev->stats.rx_dropped++; 4911 return; 4912 } 4913 4914 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4915 stmmac_rx_vlan(priv->dev, skb); 4916 skb->protocol = eth_type_trans(skb, priv->dev); 4917 4918 if (unlikely(!coe)) 4919 skb_checksum_none_assert(skb); 4920 else 4921 skb->ip_summed = CHECKSUM_UNNECESSARY; 4922 4923 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4924 skb_set_hash(skb, hash, hash_type); 4925 4926 skb_record_rx_queue(skb, queue); 4927 napi_gro_receive(&ch->rxtx_napi, skb); 4928 4929 priv->dev->stats.rx_packets++; 4930 priv->dev->stats.rx_bytes += len; 4931 } 4932 4933 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4934 { 4935 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4936 unsigned int entry = rx_q->dirty_rx; 4937 struct dma_desc *rx_desc = NULL; 4938 bool ret = true; 4939 4940 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4941 4942 while (budget-- > 0 && entry != rx_q->cur_rx) { 4943 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4944 dma_addr_t dma_addr; 4945 bool use_rx_wd; 4946 4947 if (!buf->xdp) { 4948 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4949 if (!buf->xdp) { 4950 ret = false; 4951 break; 4952 } 4953 } 4954 4955 if (priv->extend_desc) 4956 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4957 else 4958 rx_desc = rx_q->dma_rx + entry; 4959 4960 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4961 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4962 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4963 stmmac_refill_desc3(priv, rx_q, rx_desc); 4964 4965 rx_q->rx_count_frames++; 4966 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4967 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4968 rx_q->rx_count_frames = 0; 4969 4970 use_rx_wd = !priv->rx_coal_frames[queue]; 4971 use_rx_wd |= rx_q->rx_count_frames > 0; 4972 if (!priv->use_riwt) 4973 use_rx_wd = false; 4974 4975 dma_wmb(); 4976 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4977 4978 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4979 } 4980 4981 if (rx_desc) { 4982 rx_q->dirty_rx = entry; 4983 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4984 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4985 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4986 } 4987 4988 return ret; 4989 } 4990 4991 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4992 { 4993 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4994 unsigned int count = 0, error = 0, len = 0; 4995 int dirty = stmmac_rx_dirty(priv, queue); 4996 unsigned int next_entry = rx_q->cur_rx; 4997 unsigned int desc_size; 4998 struct bpf_prog *prog; 4999 bool failure = false; 5000 int xdp_status = 0; 5001 int status = 0; 5002 5003 if (netif_msg_rx_status(priv)) { 5004 void *rx_head; 5005 5006 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5007 if (priv->extend_desc) { 5008 rx_head = (void *)rx_q->dma_erx; 5009 desc_size = sizeof(struct dma_extended_desc); 5010 } else { 5011 rx_head = (void *)rx_q->dma_rx; 5012 desc_size = sizeof(struct dma_desc); 5013 } 5014 5015 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5016 rx_q->dma_rx_phy, desc_size); 5017 } 5018 while (count < limit) { 5019 struct stmmac_rx_buffer *buf; 5020 unsigned int buf1_len = 0; 5021 struct dma_desc *np, *p; 5022 int entry; 5023 int res; 5024 5025 if (!count && rx_q->state_saved) { 5026 error = rx_q->state.error; 5027 len = rx_q->state.len; 5028 } else { 5029 rx_q->state_saved = false; 5030 error = 0; 5031 len = 0; 5032 } 5033 5034 if (count >= limit) 5035 break; 5036 5037 read_again: 5038 buf1_len = 0; 5039 entry = next_entry; 5040 buf = &rx_q->buf_pool[entry]; 5041 5042 if (dirty >= STMMAC_RX_FILL_BATCH) { 5043 failure = failure || 5044 !stmmac_rx_refill_zc(priv, queue, dirty); 5045 dirty = 0; 5046 } 5047 5048 if (priv->extend_desc) 5049 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5050 else 5051 p = rx_q->dma_rx + entry; 5052 5053 /* read the status of the incoming frame */ 5054 status = stmmac_rx_status(priv, &priv->dev->stats, 5055 &priv->xstats, p); 5056 /* check if managed by the DMA otherwise go ahead */ 5057 if (unlikely(status & dma_own)) 5058 break; 5059 5060 /* Prefetch the next RX descriptor */ 5061 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5062 priv->dma_conf.dma_rx_size); 5063 next_entry = rx_q->cur_rx; 5064 5065 if (priv->extend_desc) 5066 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5067 else 5068 np = rx_q->dma_rx + next_entry; 5069 5070 prefetch(np); 5071 5072 /* Ensure a valid XSK buffer before proceed */ 5073 if (!buf->xdp) 5074 break; 5075 5076 if (priv->extend_desc) 5077 stmmac_rx_extended_status(priv, &priv->dev->stats, 5078 &priv->xstats, 5079 rx_q->dma_erx + entry); 5080 if (unlikely(status == discard_frame)) { 5081 xsk_buff_free(buf->xdp); 5082 buf->xdp = NULL; 5083 dirty++; 5084 error = 1; 5085 if (!priv->hwts_rx_en) 5086 priv->dev->stats.rx_errors++; 5087 } 5088 5089 if (unlikely(error && (status & rx_not_ls))) 5090 goto read_again; 5091 if (unlikely(error)) { 5092 count++; 5093 continue; 5094 } 5095 5096 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5097 if (likely(status & rx_not_ls)) { 5098 xsk_buff_free(buf->xdp); 5099 buf->xdp = NULL; 5100 dirty++; 5101 count++; 5102 goto read_again; 5103 } 5104 5105 /* XDP ZC Frame only support primary buffers for now */ 5106 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5107 len += buf1_len; 5108 5109 /* ACS is disabled; strip manually. */ 5110 if (likely(!(status & rx_not_ls))) { 5111 buf1_len -= ETH_FCS_LEN; 5112 len -= ETH_FCS_LEN; 5113 } 5114 5115 /* RX buffer is good and fit into a XSK pool buffer */ 5116 buf->xdp->data_end = buf->xdp->data + buf1_len; 5117 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5118 5119 prog = READ_ONCE(priv->xdp_prog); 5120 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5121 5122 switch (res) { 5123 case STMMAC_XDP_PASS: 5124 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5125 xsk_buff_free(buf->xdp); 5126 break; 5127 case STMMAC_XDP_CONSUMED: 5128 xsk_buff_free(buf->xdp); 5129 priv->dev->stats.rx_dropped++; 5130 break; 5131 case STMMAC_XDP_TX: 5132 case STMMAC_XDP_REDIRECT: 5133 xdp_status |= res; 5134 break; 5135 } 5136 5137 buf->xdp = NULL; 5138 dirty++; 5139 count++; 5140 } 5141 5142 if (status & rx_not_ls) { 5143 rx_q->state_saved = true; 5144 rx_q->state.error = error; 5145 rx_q->state.len = len; 5146 } 5147 5148 stmmac_finalize_xdp_rx(priv, xdp_status); 5149 5150 priv->xstats.rx_pkt_n += count; 5151 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5152 5153 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5154 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5155 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5156 else 5157 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5158 5159 return (int)count; 5160 } 5161 5162 return failure ? limit : (int)count; 5163 } 5164 5165 /** 5166 * stmmac_rx - manage the receive process 5167 * @priv: driver private structure 5168 * @limit: napi bugget 5169 * @queue: RX queue index. 5170 * Description : this the function called by the napi poll method. 5171 * It gets all the frames inside the ring. 5172 */ 5173 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5174 { 5175 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5176 struct stmmac_channel *ch = &priv->channel[queue]; 5177 unsigned int count = 0, error = 0, len = 0; 5178 int status = 0, coe = priv->hw->rx_csum; 5179 unsigned int next_entry = rx_q->cur_rx; 5180 enum dma_data_direction dma_dir; 5181 unsigned int desc_size; 5182 struct sk_buff *skb = NULL; 5183 struct xdp_buff xdp; 5184 int xdp_status = 0; 5185 int buf_sz; 5186 5187 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5188 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5189 5190 if (netif_msg_rx_status(priv)) { 5191 void *rx_head; 5192 5193 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5194 if (priv->extend_desc) { 5195 rx_head = (void *)rx_q->dma_erx; 5196 desc_size = sizeof(struct dma_extended_desc); 5197 } else { 5198 rx_head = (void *)rx_q->dma_rx; 5199 desc_size = sizeof(struct dma_desc); 5200 } 5201 5202 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5203 rx_q->dma_rx_phy, desc_size); 5204 } 5205 while (count < limit) { 5206 unsigned int buf1_len = 0, buf2_len = 0; 5207 enum pkt_hash_types hash_type; 5208 struct stmmac_rx_buffer *buf; 5209 struct dma_desc *np, *p; 5210 int entry; 5211 u32 hash; 5212 5213 if (!count && rx_q->state_saved) { 5214 skb = rx_q->state.skb; 5215 error = rx_q->state.error; 5216 len = rx_q->state.len; 5217 } else { 5218 rx_q->state_saved = false; 5219 skb = NULL; 5220 error = 0; 5221 len = 0; 5222 } 5223 5224 if (count >= limit) 5225 break; 5226 5227 read_again: 5228 buf1_len = 0; 5229 buf2_len = 0; 5230 entry = next_entry; 5231 buf = &rx_q->buf_pool[entry]; 5232 5233 if (priv->extend_desc) 5234 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5235 else 5236 p = rx_q->dma_rx + entry; 5237 5238 /* read the status of the incoming frame */ 5239 status = stmmac_rx_status(priv, &priv->dev->stats, 5240 &priv->xstats, p); 5241 /* check if managed by the DMA otherwise go ahead */ 5242 if (unlikely(status & dma_own)) 5243 break; 5244 5245 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5246 priv->dma_conf.dma_rx_size); 5247 next_entry = rx_q->cur_rx; 5248 5249 if (priv->extend_desc) 5250 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5251 else 5252 np = rx_q->dma_rx + next_entry; 5253 5254 prefetch(np); 5255 5256 if (priv->extend_desc) 5257 stmmac_rx_extended_status(priv, &priv->dev->stats, 5258 &priv->xstats, rx_q->dma_erx + entry); 5259 if (unlikely(status == discard_frame)) { 5260 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5261 buf->page = NULL; 5262 error = 1; 5263 if (!priv->hwts_rx_en) 5264 priv->dev->stats.rx_errors++; 5265 } 5266 5267 if (unlikely(error && (status & rx_not_ls))) 5268 goto read_again; 5269 if (unlikely(error)) { 5270 dev_kfree_skb(skb); 5271 skb = NULL; 5272 count++; 5273 continue; 5274 } 5275 5276 /* Buffer is good. Go on. */ 5277 5278 prefetch(page_address(buf->page) + buf->page_offset); 5279 if (buf->sec_page) 5280 prefetch(page_address(buf->sec_page)); 5281 5282 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5283 len += buf1_len; 5284 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5285 len += buf2_len; 5286 5287 /* ACS is disabled; strip manually. */ 5288 if (likely(!(status & rx_not_ls))) { 5289 if (buf2_len) { 5290 buf2_len -= ETH_FCS_LEN; 5291 len -= ETH_FCS_LEN; 5292 } else if (buf1_len) { 5293 buf1_len -= ETH_FCS_LEN; 5294 len -= ETH_FCS_LEN; 5295 } 5296 } 5297 5298 if (!skb) { 5299 unsigned int pre_len, sync_len; 5300 5301 dma_sync_single_for_cpu(priv->device, buf->addr, 5302 buf1_len, dma_dir); 5303 5304 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5305 xdp_prepare_buff(&xdp, page_address(buf->page), 5306 buf->page_offset, buf1_len, false); 5307 5308 pre_len = xdp.data_end - xdp.data_hard_start - 5309 buf->page_offset; 5310 skb = stmmac_xdp_run_prog(priv, &xdp); 5311 /* Due xdp_adjust_tail: DMA sync for_device 5312 * cover max len CPU touch 5313 */ 5314 sync_len = xdp.data_end - xdp.data_hard_start - 5315 buf->page_offset; 5316 sync_len = max(sync_len, pre_len); 5317 5318 /* For Not XDP_PASS verdict */ 5319 if (IS_ERR(skb)) { 5320 unsigned int xdp_res = -PTR_ERR(skb); 5321 5322 if (xdp_res & STMMAC_XDP_CONSUMED) { 5323 page_pool_put_page(rx_q->page_pool, 5324 virt_to_head_page(xdp.data), 5325 sync_len, true); 5326 buf->page = NULL; 5327 priv->dev->stats.rx_dropped++; 5328 5329 /* Clear skb as it was set as 5330 * status by XDP program. 5331 */ 5332 skb = NULL; 5333 5334 if (unlikely((status & rx_not_ls))) 5335 goto read_again; 5336 5337 count++; 5338 continue; 5339 } else if (xdp_res & (STMMAC_XDP_TX | 5340 STMMAC_XDP_REDIRECT)) { 5341 xdp_status |= xdp_res; 5342 buf->page = NULL; 5343 skb = NULL; 5344 count++; 5345 continue; 5346 } 5347 } 5348 } 5349 5350 if (!skb) { 5351 /* XDP program may expand or reduce tail */ 5352 buf1_len = xdp.data_end - xdp.data; 5353 5354 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5355 if (!skb) { 5356 priv->dev->stats.rx_dropped++; 5357 count++; 5358 goto drain_data; 5359 } 5360 5361 /* XDP program may adjust header */ 5362 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5363 skb_put(skb, buf1_len); 5364 5365 /* Data payload copied into SKB, page ready for recycle */ 5366 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5367 buf->page = NULL; 5368 } else if (buf1_len) { 5369 dma_sync_single_for_cpu(priv->device, buf->addr, 5370 buf1_len, dma_dir); 5371 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5372 buf->page, buf->page_offset, buf1_len, 5373 priv->dma_conf.dma_buf_sz); 5374 5375 /* Data payload appended into SKB */ 5376 page_pool_release_page(rx_q->page_pool, buf->page); 5377 buf->page = NULL; 5378 } 5379 5380 if (buf2_len) { 5381 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5382 buf2_len, dma_dir); 5383 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5384 buf->sec_page, 0, buf2_len, 5385 priv->dma_conf.dma_buf_sz); 5386 5387 /* Data payload appended into SKB */ 5388 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5389 buf->sec_page = NULL; 5390 } 5391 5392 drain_data: 5393 if (likely(status & rx_not_ls)) 5394 goto read_again; 5395 if (!skb) 5396 continue; 5397 5398 /* Got entire packet into SKB. Finish it. */ 5399 5400 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5401 stmmac_rx_vlan(priv->dev, skb); 5402 skb->protocol = eth_type_trans(skb, priv->dev); 5403 5404 if (unlikely(!coe)) 5405 skb_checksum_none_assert(skb); 5406 else 5407 skb->ip_summed = CHECKSUM_UNNECESSARY; 5408 5409 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5410 skb_set_hash(skb, hash, hash_type); 5411 5412 skb_record_rx_queue(skb, queue); 5413 napi_gro_receive(&ch->rx_napi, skb); 5414 skb = NULL; 5415 5416 priv->dev->stats.rx_packets++; 5417 priv->dev->stats.rx_bytes += len; 5418 count++; 5419 } 5420 5421 if (status & rx_not_ls || skb) { 5422 rx_q->state_saved = true; 5423 rx_q->state.skb = skb; 5424 rx_q->state.error = error; 5425 rx_q->state.len = len; 5426 } 5427 5428 stmmac_finalize_xdp_rx(priv, xdp_status); 5429 5430 stmmac_rx_refill(priv, queue); 5431 5432 priv->xstats.rx_pkt_n += count; 5433 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5434 5435 return count; 5436 } 5437 5438 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5439 { 5440 struct stmmac_channel *ch = 5441 container_of(napi, struct stmmac_channel, rx_napi); 5442 struct stmmac_priv *priv = ch->priv_data; 5443 u32 chan = ch->index; 5444 int work_done; 5445 5446 priv->xstats.napi_poll++; 5447 5448 work_done = stmmac_rx(priv, budget, chan); 5449 if (work_done < budget && napi_complete_done(napi, work_done)) { 5450 unsigned long flags; 5451 5452 spin_lock_irqsave(&ch->lock, flags); 5453 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5454 spin_unlock_irqrestore(&ch->lock, flags); 5455 } 5456 5457 return work_done; 5458 } 5459 5460 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5461 { 5462 struct stmmac_channel *ch = 5463 container_of(napi, struct stmmac_channel, tx_napi); 5464 struct stmmac_priv *priv = ch->priv_data; 5465 u32 chan = ch->index; 5466 int work_done; 5467 5468 priv->xstats.napi_poll++; 5469 5470 work_done = stmmac_tx_clean(priv, budget, chan); 5471 work_done = min(work_done, budget); 5472 5473 if (work_done < budget && napi_complete_done(napi, work_done)) { 5474 unsigned long flags; 5475 5476 spin_lock_irqsave(&ch->lock, flags); 5477 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5478 spin_unlock_irqrestore(&ch->lock, flags); 5479 } 5480 5481 return work_done; 5482 } 5483 5484 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5485 { 5486 struct stmmac_channel *ch = 5487 container_of(napi, struct stmmac_channel, rxtx_napi); 5488 struct stmmac_priv *priv = ch->priv_data; 5489 int rx_done, tx_done, rxtx_done; 5490 u32 chan = ch->index; 5491 5492 priv->xstats.napi_poll++; 5493 5494 tx_done = stmmac_tx_clean(priv, budget, chan); 5495 tx_done = min(tx_done, budget); 5496 5497 rx_done = stmmac_rx_zc(priv, budget, chan); 5498 5499 rxtx_done = max(tx_done, rx_done); 5500 5501 /* If either TX or RX work is not complete, return budget 5502 * and keep pooling 5503 */ 5504 if (rxtx_done >= budget) 5505 return budget; 5506 5507 /* all work done, exit the polling mode */ 5508 if (napi_complete_done(napi, rxtx_done)) { 5509 unsigned long flags; 5510 5511 spin_lock_irqsave(&ch->lock, flags); 5512 /* Both RX and TX work done are compelte, 5513 * so enable both RX & TX IRQs. 5514 */ 5515 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5516 spin_unlock_irqrestore(&ch->lock, flags); 5517 } 5518 5519 return min(rxtx_done, budget - 1); 5520 } 5521 5522 /** 5523 * stmmac_tx_timeout 5524 * @dev : Pointer to net device structure 5525 * @txqueue: the index of the hanging transmit queue 5526 * Description: this function is called when a packet transmission fails to 5527 * complete within a reasonable time. The driver will mark the error in the 5528 * netdev structure and arrange for the device to be reset to a sane state 5529 * in order to transmit a new packet. 5530 */ 5531 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5532 { 5533 struct stmmac_priv *priv = netdev_priv(dev); 5534 5535 stmmac_global_err(priv); 5536 } 5537 5538 /** 5539 * stmmac_set_rx_mode - entry point for multicast addressing 5540 * @dev : pointer to the device structure 5541 * Description: 5542 * This function is a driver entry point which gets called by the kernel 5543 * whenever multicast addresses must be enabled/disabled. 5544 * Return value: 5545 * void. 5546 */ 5547 static void stmmac_set_rx_mode(struct net_device *dev) 5548 { 5549 struct stmmac_priv *priv = netdev_priv(dev); 5550 5551 stmmac_set_filter(priv, priv->hw, dev); 5552 } 5553 5554 /** 5555 * stmmac_change_mtu - entry point to change MTU size for the device. 5556 * @dev : device pointer. 5557 * @new_mtu : the new MTU size for the device. 5558 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5559 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5560 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5561 * Return value: 5562 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5563 * file on failure. 5564 */ 5565 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5566 { 5567 struct stmmac_priv *priv = netdev_priv(dev); 5568 int txfifosz = priv->plat->tx_fifo_size; 5569 struct stmmac_dma_conf *dma_conf; 5570 const int mtu = new_mtu; 5571 int ret; 5572 5573 if (txfifosz == 0) 5574 txfifosz = priv->dma_cap.tx_fifo_size; 5575 5576 txfifosz /= priv->plat->tx_queues_to_use; 5577 5578 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5579 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5580 return -EINVAL; 5581 } 5582 5583 new_mtu = STMMAC_ALIGN(new_mtu); 5584 5585 /* If condition true, FIFO is too small or MTU too large */ 5586 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5587 return -EINVAL; 5588 5589 if (netif_running(dev)) { 5590 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5591 /* Try to allocate the new DMA conf with the new mtu */ 5592 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5593 if (IS_ERR(dma_conf)) { 5594 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5595 mtu); 5596 return PTR_ERR(dma_conf); 5597 } 5598 5599 stmmac_release(dev); 5600 5601 ret = __stmmac_open(dev, dma_conf); 5602 kfree(dma_conf); 5603 if (ret) { 5604 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5605 return ret; 5606 } 5607 5608 stmmac_set_rx_mode(dev); 5609 } 5610 5611 dev->mtu = mtu; 5612 netdev_update_features(dev); 5613 5614 return 0; 5615 } 5616 5617 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5618 netdev_features_t features) 5619 { 5620 struct stmmac_priv *priv = netdev_priv(dev); 5621 5622 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5623 features &= ~NETIF_F_RXCSUM; 5624 5625 if (!priv->plat->tx_coe) 5626 features &= ~NETIF_F_CSUM_MASK; 5627 5628 /* Some GMAC devices have a bugged Jumbo frame support that 5629 * needs to have the Tx COE disabled for oversized frames 5630 * (due to limited buffer sizes). In this case we disable 5631 * the TX csum insertion in the TDES and not use SF. 5632 */ 5633 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5634 features &= ~NETIF_F_CSUM_MASK; 5635 5636 /* Disable tso if asked by ethtool */ 5637 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5638 if (features & NETIF_F_TSO) 5639 priv->tso = true; 5640 else 5641 priv->tso = false; 5642 } 5643 5644 return features; 5645 } 5646 5647 static int stmmac_set_features(struct net_device *netdev, 5648 netdev_features_t features) 5649 { 5650 struct stmmac_priv *priv = netdev_priv(netdev); 5651 5652 /* Keep the COE Type in case of csum is supporting */ 5653 if (features & NETIF_F_RXCSUM) 5654 priv->hw->rx_csum = priv->plat->rx_coe; 5655 else 5656 priv->hw->rx_csum = 0; 5657 /* No check needed because rx_coe has been set before and it will be 5658 * fixed in case of issue. 5659 */ 5660 stmmac_rx_ipc(priv, priv->hw); 5661 5662 if (priv->sph_cap) { 5663 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5664 u32 chan; 5665 5666 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5667 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5668 } 5669 5670 return 0; 5671 } 5672 5673 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5674 { 5675 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5676 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5677 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5678 bool *hs_enable = &fpe_cfg->hs_enable; 5679 5680 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5681 return; 5682 5683 /* If LP has sent verify mPacket, LP is FPE capable */ 5684 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5685 if (*lp_state < FPE_STATE_CAPABLE) 5686 *lp_state = FPE_STATE_CAPABLE; 5687 5688 /* If user has requested FPE enable, quickly response */ 5689 if (*hs_enable) 5690 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5691 MPACKET_RESPONSE); 5692 } 5693 5694 /* If Local has sent verify mPacket, Local is FPE capable */ 5695 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5696 if (*lo_state < FPE_STATE_CAPABLE) 5697 *lo_state = FPE_STATE_CAPABLE; 5698 } 5699 5700 /* If LP has sent response mPacket, LP is entering FPE ON */ 5701 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5702 *lp_state = FPE_STATE_ENTERING_ON; 5703 5704 /* If Local has sent response mPacket, Local is entering FPE ON */ 5705 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5706 *lo_state = FPE_STATE_ENTERING_ON; 5707 5708 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5709 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5710 priv->fpe_wq) { 5711 queue_work(priv->fpe_wq, &priv->fpe_task); 5712 } 5713 } 5714 5715 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5716 { 5717 u32 rx_cnt = priv->plat->rx_queues_to_use; 5718 u32 tx_cnt = priv->plat->tx_queues_to_use; 5719 u32 queues_count; 5720 u32 queue; 5721 bool xmac; 5722 5723 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5724 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5725 5726 if (priv->irq_wake) 5727 pm_wakeup_event(priv->device, 0); 5728 5729 if (priv->dma_cap.estsel) 5730 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5731 &priv->xstats, tx_cnt); 5732 5733 if (priv->dma_cap.fpesel) { 5734 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5735 priv->dev); 5736 5737 stmmac_fpe_event_status(priv, status); 5738 } 5739 5740 /* To handle GMAC own interrupts */ 5741 if ((priv->plat->has_gmac) || xmac) { 5742 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5743 5744 if (unlikely(status)) { 5745 /* For LPI we need to save the tx status */ 5746 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5747 priv->tx_path_in_lpi_mode = true; 5748 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5749 priv->tx_path_in_lpi_mode = false; 5750 } 5751 5752 for (queue = 0; queue < queues_count; queue++) { 5753 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5754 queue); 5755 } 5756 5757 /* PCS link status */ 5758 if (priv->hw->pcs) { 5759 if (priv->xstats.pcs_link) 5760 netif_carrier_on(priv->dev); 5761 else 5762 netif_carrier_off(priv->dev); 5763 } 5764 5765 stmmac_timestamp_interrupt(priv, priv); 5766 } 5767 } 5768 5769 /** 5770 * stmmac_interrupt - main ISR 5771 * @irq: interrupt number. 5772 * @dev_id: to pass the net device pointer. 5773 * Description: this is the main driver interrupt service routine. 5774 * It can call: 5775 * o DMA service routine (to manage incoming frame reception and transmission 5776 * status) 5777 * o Core interrupts to manage: remote wake-up, management counter, LPI 5778 * interrupts. 5779 */ 5780 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5781 { 5782 struct net_device *dev = (struct net_device *)dev_id; 5783 struct stmmac_priv *priv = netdev_priv(dev); 5784 5785 /* Check if adapter is up */ 5786 if (test_bit(STMMAC_DOWN, &priv->state)) 5787 return IRQ_HANDLED; 5788 5789 /* Check if a fatal error happened */ 5790 if (stmmac_safety_feat_interrupt(priv)) 5791 return IRQ_HANDLED; 5792 5793 /* To handle Common interrupts */ 5794 stmmac_common_interrupt(priv); 5795 5796 /* To handle DMA interrupts */ 5797 stmmac_dma_interrupt(priv); 5798 5799 return IRQ_HANDLED; 5800 } 5801 5802 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5803 { 5804 struct net_device *dev = (struct net_device *)dev_id; 5805 struct stmmac_priv *priv = netdev_priv(dev); 5806 5807 if (unlikely(!dev)) { 5808 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5809 return IRQ_NONE; 5810 } 5811 5812 /* Check if adapter is up */ 5813 if (test_bit(STMMAC_DOWN, &priv->state)) 5814 return IRQ_HANDLED; 5815 5816 /* To handle Common interrupts */ 5817 stmmac_common_interrupt(priv); 5818 5819 return IRQ_HANDLED; 5820 } 5821 5822 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5823 { 5824 struct net_device *dev = (struct net_device *)dev_id; 5825 struct stmmac_priv *priv = netdev_priv(dev); 5826 5827 if (unlikely(!dev)) { 5828 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5829 return IRQ_NONE; 5830 } 5831 5832 /* Check if adapter is up */ 5833 if (test_bit(STMMAC_DOWN, &priv->state)) 5834 return IRQ_HANDLED; 5835 5836 /* Check if a fatal error happened */ 5837 stmmac_safety_feat_interrupt(priv); 5838 5839 return IRQ_HANDLED; 5840 } 5841 5842 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5843 { 5844 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5845 struct stmmac_dma_conf *dma_conf; 5846 int chan = tx_q->queue_index; 5847 struct stmmac_priv *priv; 5848 int status; 5849 5850 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5851 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5852 5853 if (unlikely(!data)) { 5854 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5855 return IRQ_NONE; 5856 } 5857 5858 /* Check if adapter is up */ 5859 if (test_bit(STMMAC_DOWN, &priv->state)) 5860 return IRQ_HANDLED; 5861 5862 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5863 5864 if (unlikely(status & tx_hard_error_bump_tc)) { 5865 /* Try to bump up the dma threshold on this failure */ 5866 stmmac_bump_dma_threshold(priv, chan); 5867 } else if (unlikely(status == tx_hard_error)) { 5868 stmmac_tx_err(priv, chan); 5869 } 5870 5871 return IRQ_HANDLED; 5872 } 5873 5874 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5875 { 5876 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5877 struct stmmac_dma_conf *dma_conf; 5878 int chan = rx_q->queue_index; 5879 struct stmmac_priv *priv; 5880 5881 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5882 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5883 5884 if (unlikely(!data)) { 5885 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5886 return IRQ_NONE; 5887 } 5888 5889 /* Check if adapter is up */ 5890 if (test_bit(STMMAC_DOWN, &priv->state)) 5891 return IRQ_HANDLED; 5892 5893 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5894 5895 return IRQ_HANDLED; 5896 } 5897 5898 #ifdef CONFIG_NET_POLL_CONTROLLER 5899 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5900 * to allow network I/O with interrupts disabled. 5901 */ 5902 static void stmmac_poll_controller(struct net_device *dev) 5903 { 5904 struct stmmac_priv *priv = netdev_priv(dev); 5905 int i; 5906 5907 /* If adapter is down, do nothing */ 5908 if (test_bit(STMMAC_DOWN, &priv->state)) 5909 return; 5910 5911 if (priv->plat->multi_msi_en) { 5912 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5913 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5914 5915 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5916 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5917 } else { 5918 disable_irq(dev->irq); 5919 stmmac_interrupt(dev->irq, dev); 5920 enable_irq(dev->irq); 5921 } 5922 } 5923 #endif 5924 5925 /** 5926 * stmmac_ioctl - Entry point for the Ioctl 5927 * @dev: Device pointer. 5928 * @rq: An IOCTL specefic structure, that can contain a pointer to 5929 * a proprietary structure used to pass information to the driver. 5930 * @cmd: IOCTL command 5931 * Description: 5932 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5933 */ 5934 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5935 { 5936 struct stmmac_priv *priv = netdev_priv (dev); 5937 int ret = -EOPNOTSUPP; 5938 5939 if (!netif_running(dev)) 5940 return -EINVAL; 5941 5942 switch (cmd) { 5943 case SIOCGMIIPHY: 5944 case SIOCGMIIREG: 5945 case SIOCSMIIREG: 5946 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5947 break; 5948 case SIOCSHWTSTAMP: 5949 ret = stmmac_hwtstamp_set(dev, rq); 5950 break; 5951 case SIOCGHWTSTAMP: 5952 ret = stmmac_hwtstamp_get(dev, rq); 5953 break; 5954 default: 5955 break; 5956 } 5957 5958 return ret; 5959 } 5960 5961 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5962 void *cb_priv) 5963 { 5964 struct stmmac_priv *priv = cb_priv; 5965 int ret = -EOPNOTSUPP; 5966 5967 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5968 return ret; 5969 5970 __stmmac_disable_all_queues(priv); 5971 5972 switch (type) { 5973 case TC_SETUP_CLSU32: 5974 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5975 break; 5976 case TC_SETUP_CLSFLOWER: 5977 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5978 break; 5979 default: 5980 break; 5981 } 5982 5983 stmmac_enable_all_queues(priv); 5984 return ret; 5985 } 5986 5987 static LIST_HEAD(stmmac_block_cb_list); 5988 5989 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5990 void *type_data) 5991 { 5992 struct stmmac_priv *priv = netdev_priv(ndev); 5993 5994 switch (type) { 5995 case TC_QUERY_CAPS: 5996 return stmmac_tc_query_caps(priv, priv, type_data); 5997 case TC_SETUP_BLOCK: 5998 return flow_block_cb_setup_simple(type_data, 5999 &stmmac_block_cb_list, 6000 stmmac_setup_tc_block_cb, 6001 priv, priv, true); 6002 case TC_SETUP_QDISC_CBS: 6003 return stmmac_tc_setup_cbs(priv, priv, type_data); 6004 case TC_SETUP_QDISC_TAPRIO: 6005 return stmmac_tc_setup_taprio(priv, priv, type_data); 6006 case TC_SETUP_QDISC_ETF: 6007 return stmmac_tc_setup_etf(priv, priv, type_data); 6008 default: 6009 return -EOPNOTSUPP; 6010 } 6011 } 6012 6013 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6014 struct net_device *sb_dev) 6015 { 6016 int gso = skb_shinfo(skb)->gso_type; 6017 6018 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6019 /* 6020 * There is no way to determine the number of TSO/USO 6021 * capable Queues. Let's use always the Queue 0 6022 * because if TSO/USO is supported then at least this 6023 * one will be capable. 6024 */ 6025 return 0; 6026 } 6027 6028 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6029 } 6030 6031 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6032 { 6033 struct stmmac_priv *priv = netdev_priv(ndev); 6034 int ret = 0; 6035 6036 ret = pm_runtime_resume_and_get(priv->device); 6037 if (ret < 0) 6038 return ret; 6039 6040 ret = eth_mac_addr(ndev, addr); 6041 if (ret) 6042 goto set_mac_error; 6043 6044 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6045 6046 set_mac_error: 6047 pm_runtime_put(priv->device); 6048 6049 return ret; 6050 } 6051 6052 #ifdef CONFIG_DEBUG_FS 6053 static struct dentry *stmmac_fs_dir; 6054 6055 static void sysfs_display_ring(void *head, int size, int extend_desc, 6056 struct seq_file *seq, dma_addr_t dma_phy_addr) 6057 { 6058 int i; 6059 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6060 struct dma_desc *p = (struct dma_desc *)head; 6061 dma_addr_t dma_addr; 6062 6063 for (i = 0; i < size; i++) { 6064 if (extend_desc) { 6065 dma_addr = dma_phy_addr + i * sizeof(*ep); 6066 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6067 i, &dma_addr, 6068 le32_to_cpu(ep->basic.des0), 6069 le32_to_cpu(ep->basic.des1), 6070 le32_to_cpu(ep->basic.des2), 6071 le32_to_cpu(ep->basic.des3)); 6072 ep++; 6073 } else { 6074 dma_addr = dma_phy_addr + i * sizeof(*p); 6075 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6076 i, &dma_addr, 6077 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6078 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6079 p++; 6080 } 6081 seq_printf(seq, "\n"); 6082 } 6083 } 6084 6085 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6086 { 6087 struct net_device *dev = seq->private; 6088 struct stmmac_priv *priv = netdev_priv(dev); 6089 u32 rx_count = priv->plat->rx_queues_to_use; 6090 u32 tx_count = priv->plat->tx_queues_to_use; 6091 u32 queue; 6092 6093 if ((dev->flags & IFF_UP) == 0) 6094 return 0; 6095 6096 for (queue = 0; queue < rx_count; queue++) { 6097 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6098 6099 seq_printf(seq, "RX Queue %d:\n", queue); 6100 6101 if (priv->extend_desc) { 6102 seq_printf(seq, "Extended descriptor ring:\n"); 6103 sysfs_display_ring((void *)rx_q->dma_erx, 6104 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6105 } else { 6106 seq_printf(seq, "Descriptor ring:\n"); 6107 sysfs_display_ring((void *)rx_q->dma_rx, 6108 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6109 } 6110 } 6111 6112 for (queue = 0; queue < tx_count; queue++) { 6113 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6114 6115 seq_printf(seq, "TX Queue %d:\n", queue); 6116 6117 if (priv->extend_desc) { 6118 seq_printf(seq, "Extended descriptor ring:\n"); 6119 sysfs_display_ring((void *)tx_q->dma_etx, 6120 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6121 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6122 seq_printf(seq, "Descriptor ring:\n"); 6123 sysfs_display_ring((void *)tx_q->dma_tx, 6124 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6125 } 6126 } 6127 6128 return 0; 6129 } 6130 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6131 6132 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6133 { 6134 struct net_device *dev = seq->private; 6135 struct stmmac_priv *priv = netdev_priv(dev); 6136 6137 if (!priv->hw_cap_support) { 6138 seq_printf(seq, "DMA HW features not supported\n"); 6139 return 0; 6140 } 6141 6142 seq_printf(seq, "==============================\n"); 6143 seq_printf(seq, "\tDMA HW features\n"); 6144 seq_printf(seq, "==============================\n"); 6145 6146 seq_printf(seq, "\t10/100 Mbps: %s\n", 6147 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6148 seq_printf(seq, "\t1000 Mbps: %s\n", 6149 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6150 seq_printf(seq, "\tHalf duplex: %s\n", 6151 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6152 seq_printf(seq, "\tHash Filter: %s\n", 6153 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6154 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6155 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6156 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6157 (priv->dma_cap.pcs) ? "Y" : "N"); 6158 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6159 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6160 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6161 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6162 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6163 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6164 seq_printf(seq, "\tRMON module: %s\n", 6165 (priv->dma_cap.rmon) ? "Y" : "N"); 6166 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6167 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6168 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6169 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6170 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6171 (priv->dma_cap.eee) ? "Y" : "N"); 6172 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6173 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6174 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6175 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6176 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6177 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6178 } else { 6179 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6180 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6181 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6182 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6183 } 6184 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6185 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6186 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6187 priv->dma_cap.number_rx_channel); 6188 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6189 priv->dma_cap.number_tx_channel); 6190 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6191 priv->dma_cap.number_rx_queues); 6192 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6193 priv->dma_cap.number_tx_queues); 6194 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6195 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6196 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6197 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6198 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6199 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6200 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6201 priv->dma_cap.pps_out_num); 6202 seq_printf(seq, "\tSafety Features: %s\n", 6203 priv->dma_cap.asp ? "Y" : "N"); 6204 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6205 priv->dma_cap.frpsel ? "Y" : "N"); 6206 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6207 priv->dma_cap.addr64); 6208 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6209 priv->dma_cap.rssen ? "Y" : "N"); 6210 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6211 priv->dma_cap.vlhash ? "Y" : "N"); 6212 seq_printf(seq, "\tSplit Header: %s\n", 6213 priv->dma_cap.sphen ? "Y" : "N"); 6214 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6215 priv->dma_cap.vlins ? "Y" : "N"); 6216 seq_printf(seq, "\tDouble VLAN: %s\n", 6217 priv->dma_cap.dvlan ? "Y" : "N"); 6218 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6219 priv->dma_cap.l3l4fnum); 6220 seq_printf(seq, "\tARP Offloading: %s\n", 6221 priv->dma_cap.arpoffsel ? "Y" : "N"); 6222 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6223 priv->dma_cap.estsel ? "Y" : "N"); 6224 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6225 priv->dma_cap.fpesel ? "Y" : "N"); 6226 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6227 priv->dma_cap.tbssel ? "Y" : "N"); 6228 return 0; 6229 } 6230 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6231 6232 /* Use network device events to rename debugfs file entries. 6233 */ 6234 static int stmmac_device_event(struct notifier_block *unused, 6235 unsigned long event, void *ptr) 6236 { 6237 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6238 struct stmmac_priv *priv = netdev_priv(dev); 6239 6240 if (dev->netdev_ops != &stmmac_netdev_ops) 6241 goto done; 6242 6243 switch (event) { 6244 case NETDEV_CHANGENAME: 6245 if (priv->dbgfs_dir) 6246 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6247 priv->dbgfs_dir, 6248 stmmac_fs_dir, 6249 dev->name); 6250 break; 6251 } 6252 done: 6253 return NOTIFY_DONE; 6254 } 6255 6256 static struct notifier_block stmmac_notifier = { 6257 .notifier_call = stmmac_device_event, 6258 }; 6259 6260 static void stmmac_init_fs(struct net_device *dev) 6261 { 6262 struct stmmac_priv *priv = netdev_priv(dev); 6263 6264 rtnl_lock(); 6265 6266 /* Create per netdev entries */ 6267 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6268 6269 /* Entry to report DMA RX/TX rings */ 6270 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6271 &stmmac_rings_status_fops); 6272 6273 /* Entry to report the DMA HW features */ 6274 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6275 &stmmac_dma_cap_fops); 6276 6277 rtnl_unlock(); 6278 } 6279 6280 static void stmmac_exit_fs(struct net_device *dev) 6281 { 6282 struct stmmac_priv *priv = netdev_priv(dev); 6283 6284 debugfs_remove_recursive(priv->dbgfs_dir); 6285 } 6286 #endif /* CONFIG_DEBUG_FS */ 6287 6288 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6289 { 6290 unsigned char *data = (unsigned char *)&vid_le; 6291 unsigned char data_byte = 0; 6292 u32 crc = ~0x0; 6293 u32 temp = 0; 6294 int i, bits; 6295 6296 bits = get_bitmask_order(VLAN_VID_MASK); 6297 for (i = 0; i < bits; i++) { 6298 if ((i % 8) == 0) 6299 data_byte = data[i / 8]; 6300 6301 temp = ((crc & 1) ^ data_byte) & 1; 6302 crc >>= 1; 6303 data_byte >>= 1; 6304 6305 if (temp) 6306 crc ^= 0xedb88320; 6307 } 6308 6309 return crc; 6310 } 6311 6312 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6313 { 6314 u32 crc, hash = 0; 6315 __le16 pmatch = 0; 6316 int count = 0; 6317 u16 vid = 0; 6318 6319 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6320 __le16 vid_le = cpu_to_le16(vid); 6321 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6322 hash |= (1 << crc); 6323 count++; 6324 } 6325 6326 if (!priv->dma_cap.vlhash) { 6327 if (count > 2) /* VID = 0 always passes filter */ 6328 return -EOPNOTSUPP; 6329 6330 pmatch = cpu_to_le16(vid); 6331 hash = 0; 6332 } 6333 6334 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6335 } 6336 6337 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6338 { 6339 struct stmmac_priv *priv = netdev_priv(ndev); 6340 bool is_double = false; 6341 int ret; 6342 6343 if (be16_to_cpu(proto) == ETH_P_8021AD) 6344 is_double = true; 6345 6346 set_bit(vid, priv->active_vlans); 6347 ret = stmmac_vlan_update(priv, is_double); 6348 if (ret) { 6349 clear_bit(vid, priv->active_vlans); 6350 return ret; 6351 } 6352 6353 if (priv->hw->num_vlan) { 6354 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6355 if (ret) 6356 return ret; 6357 } 6358 6359 return 0; 6360 } 6361 6362 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6363 { 6364 struct stmmac_priv *priv = netdev_priv(ndev); 6365 bool is_double = false; 6366 int ret; 6367 6368 ret = pm_runtime_resume_and_get(priv->device); 6369 if (ret < 0) 6370 return ret; 6371 6372 if (be16_to_cpu(proto) == ETH_P_8021AD) 6373 is_double = true; 6374 6375 clear_bit(vid, priv->active_vlans); 6376 6377 if (priv->hw->num_vlan) { 6378 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6379 if (ret) 6380 goto del_vlan_error; 6381 } 6382 6383 ret = stmmac_vlan_update(priv, is_double); 6384 6385 del_vlan_error: 6386 pm_runtime_put(priv->device); 6387 6388 return ret; 6389 } 6390 6391 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6392 { 6393 struct stmmac_priv *priv = netdev_priv(dev); 6394 6395 switch (bpf->command) { 6396 case XDP_SETUP_PROG: 6397 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6398 case XDP_SETUP_XSK_POOL: 6399 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6400 bpf->xsk.queue_id); 6401 default: 6402 return -EOPNOTSUPP; 6403 } 6404 } 6405 6406 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6407 struct xdp_frame **frames, u32 flags) 6408 { 6409 struct stmmac_priv *priv = netdev_priv(dev); 6410 int cpu = smp_processor_id(); 6411 struct netdev_queue *nq; 6412 int i, nxmit = 0; 6413 int queue; 6414 6415 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6416 return -ENETDOWN; 6417 6418 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6419 return -EINVAL; 6420 6421 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6422 nq = netdev_get_tx_queue(priv->dev, queue); 6423 6424 __netif_tx_lock(nq, cpu); 6425 /* Avoids TX time-out as we are sharing with slow path */ 6426 txq_trans_cond_update(nq); 6427 6428 for (i = 0; i < num_frames; i++) { 6429 int res; 6430 6431 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6432 if (res == STMMAC_XDP_CONSUMED) 6433 break; 6434 6435 nxmit++; 6436 } 6437 6438 if (flags & XDP_XMIT_FLUSH) { 6439 stmmac_flush_tx_descriptors(priv, queue); 6440 stmmac_tx_timer_arm(priv, queue); 6441 } 6442 6443 __netif_tx_unlock(nq); 6444 6445 return nxmit; 6446 } 6447 6448 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6449 { 6450 struct stmmac_channel *ch = &priv->channel[queue]; 6451 unsigned long flags; 6452 6453 spin_lock_irqsave(&ch->lock, flags); 6454 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6455 spin_unlock_irqrestore(&ch->lock, flags); 6456 6457 stmmac_stop_rx_dma(priv, queue); 6458 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6459 } 6460 6461 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6462 { 6463 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6464 struct stmmac_channel *ch = &priv->channel[queue]; 6465 unsigned long flags; 6466 u32 buf_size; 6467 int ret; 6468 6469 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6470 if (ret) { 6471 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6472 return; 6473 } 6474 6475 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6476 if (ret) { 6477 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6478 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6479 return; 6480 } 6481 6482 stmmac_reset_rx_queue(priv, queue); 6483 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6484 6485 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6486 rx_q->dma_rx_phy, rx_q->queue_index); 6487 6488 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6489 sizeof(struct dma_desc)); 6490 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6491 rx_q->rx_tail_addr, rx_q->queue_index); 6492 6493 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6494 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6495 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6496 buf_size, 6497 rx_q->queue_index); 6498 } else { 6499 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6500 priv->dma_conf.dma_buf_sz, 6501 rx_q->queue_index); 6502 } 6503 6504 stmmac_start_rx_dma(priv, queue); 6505 6506 spin_lock_irqsave(&ch->lock, flags); 6507 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6508 spin_unlock_irqrestore(&ch->lock, flags); 6509 } 6510 6511 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6512 { 6513 struct stmmac_channel *ch = &priv->channel[queue]; 6514 unsigned long flags; 6515 6516 spin_lock_irqsave(&ch->lock, flags); 6517 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6518 spin_unlock_irqrestore(&ch->lock, flags); 6519 6520 stmmac_stop_tx_dma(priv, queue); 6521 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6522 } 6523 6524 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6525 { 6526 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6527 struct stmmac_channel *ch = &priv->channel[queue]; 6528 unsigned long flags; 6529 int ret; 6530 6531 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6532 if (ret) { 6533 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6534 return; 6535 } 6536 6537 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6538 if (ret) { 6539 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6540 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6541 return; 6542 } 6543 6544 stmmac_reset_tx_queue(priv, queue); 6545 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6546 6547 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6548 tx_q->dma_tx_phy, tx_q->queue_index); 6549 6550 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6551 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6552 6553 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6554 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6555 tx_q->tx_tail_addr, tx_q->queue_index); 6556 6557 stmmac_start_tx_dma(priv, queue); 6558 6559 spin_lock_irqsave(&ch->lock, flags); 6560 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6561 spin_unlock_irqrestore(&ch->lock, flags); 6562 } 6563 6564 void stmmac_xdp_release(struct net_device *dev) 6565 { 6566 struct stmmac_priv *priv = netdev_priv(dev); 6567 u32 chan; 6568 6569 /* Ensure tx function is not running */ 6570 netif_tx_disable(dev); 6571 6572 /* Disable NAPI process */ 6573 stmmac_disable_all_queues(priv); 6574 6575 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6576 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6577 6578 /* Free the IRQ lines */ 6579 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6580 6581 /* Stop TX/RX DMA channels */ 6582 stmmac_stop_all_dma(priv); 6583 6584 /* Release and free the Rx/Tx resources */ 6585 free_dma_desc_resources(priv, &priv->dma_conf); 6586 6587 /* Disable the MAC Rx/Tx */ 6588 stmmac_mac_set(priv, priv->ioaddr, false); 6589 6590 /* set trans_start so we don't get spurious 6591 * watchdogs during reset 6592 */ 6593 netif_trans_update(dev); 6594 netif_carrier_off(dev); 6595 } 6596 6597 int stmmac_xdp_open(struct net_device *dev) 6598 { 6599 struct stmmac_priv *priv = netdev_priv(dev); 6600 u32 rx_cnt = priv->plat->rx_queues_to_use; 6601 u32 tx_cnt = priv->plat->tx_queues_to_use; 6602 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6603 struct stmmac_rx_queue *rx_q; 6604 struct stmmac_tx_queue *tx_q; 6605 u32 buf_size; 6606 bool sph_en; 6607 u32 chan; 6608 int ret; 6609 6610 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6611 if (ret < 0) { 6612 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6613 __func__); 6614 goto dma_desc_error; 6615 } 6616 6617 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6618 if (ret < 0) { 6619 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6620 __func__); 6621 goto init_error; 6622 } 6623 6624 /* DMA CSR Channel configuration */ 6625 for (chan = 0; chan < dma_csr_ch; chan++) { 6626 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6627 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6628 } 6629 6630 /* Adjust Split header */ 6631 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6632 6633 /* DMA RX Channel Configuration */ 6634 for (chan = 0; chan < rx_cnt; chan++) { 6635 rx_q = &priv->dma_conf.rx_queue[chan]; 6636 6637 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6638 rx_q->dma_rx_phy, chan); 6639 6640 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6641 (rx_q->buf_alloc_num * 6642 sizeof(struct dma_desc)); 6643 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6644 rx_q->rx_tail_addr, chan); 6645 6646 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6647 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6648 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6649 buf_size, 6650 rx_q->queue_index); 6651 } else { 6652 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6653 priv->dma_conf.dma_buf_sz, 6654 rx_q->queue_index); 6655 } 6656 6657 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6658 } 6659 6660 /* DMA TX Channel Configuration */ 6661 for (chan = 0; chan < tx_cnt; chan++) { 6662 tx_q = &priv->dma_conf.tx_queue[chan]; 6663 6664 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6665 tx_q->dma_tx_phy, chan); 6666 6667 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6668 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6669 tx_q->tx_tail_addr, chan); 6670 6671 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6672 tx_q->txtimer.function = stmmac_tx_timer; 6673 } 6674 6675 /* Enable the MAC Rx/Tx */ 6676 stmmac_mac_set(priv, priv->ioaddr, true); 6677 6678 /* Start Rx & Tx DMA Channels */ 6679 stmmac_start_all_dma(priv); 6680 6681 ret = stmmac_request_irq(dev); 6682 if (ret) 6683 goto irq_error; 6684 6685 /* Enable NAPI process*/ 6686 stmmac_enable_all_queues(priv); 6687 netif_carrier_on(dev); 6688 netif_tx_start_all_queues(dev); 6689 stmmac_enable_all_dma_irq(priv); 6690 6691 return 0; 6692 6693 irq_error: 6694 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6695 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6696 6697 stmmac_hw_teardown(dev); 6698 init_error: 6699 free_dma_desc_resources(priv, &priv->dma_conf); 6700 dma_desc_error: 6701 return ret; 6702 } 6703 6704 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6705 { 6706 struct stmmac_priv *priv = netdev_priv(dev); 6707 struct stmmac_rx_queue *rx_q; 6708 struct stmmac_tx_queue *tx_q; 6709 struct stmmac_channel *ch; 6710 6711 if (test_bit(STMMAC_DOWN, &priv->state) || 6712 !netif_carrier_ok(priv->dev)) 6713 return -ENETDOWN; 6714 6715 if (!stmmac_xdp_is_enabled(priv)) 6716 return -EINVAL; 6717 6718 if (queue >= priv->plat->rx_queues_to_use || 6719 queue >= priv->plat->tx_queues_to_use) 6720 return -EINVAL; 6721 6722 rx_q = &priv->dma_conf.rx_queue[queue]; 6723 tx_q = &priv->dma_conf.tx_queue[queue]; 6724 ch = &priv->channel[queue]; 6725 6726 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6727 return -EINVAL; 6728 6729 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6730 /* EQoS does not have per-DMA channel SW interrupt, 6731 * so we schedule RX Napi straight-away. 6732 */ 6733 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6734 __napi_schedule(&ch->rxtx_napi); 6735 } 6736 6737 return 0; 6738 } 6739 6740 static const struct net_device_ops stmmac_netdev_ops = { 6741 .ndo_open = stmmac_open, 6742 .ndo_start_xmit = stmmac_xmit, 6743 .ndo_stop = stmmac_release, 6744 .ndo_change_mtu = stmmac_change_mtu, 6745 .ndo_fix_features = stmmac_fix_features, 6746 .ndo_set_features = stmmac_set_features, 6747 .ndo_set_rx_mode = stmmac_set_rx_mode, 6748 .ndo_tx_timeout = stmmac_tx_timeout, 6749 .ndo_eth_ioctl = stmmac_ioctl, 6750 .ndo_setup_tc = stmmac_setup_tc, 6751 .ndo_select_queue = stmmac_select_queue, 6752 #ifdef CONFIG_NET_POLL_CONTROLLER 6753 .ndo_poll_controller = stmmac_poll_controller, 6754 #endif 6755 .ndo_set_mac_address = stmmac_set_mac_address, 6756 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6757 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6758 .ndo_bpf = stmmac_bpf, 6759 .ndo_xdp_xmit = stmmac_xdp_xmit, 6760 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6761 }; 6762 6763 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6764 { 6765 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6766 return; 6767 if (test_bit(STMMAC_DOWN, &priv->state)) 6768 return; 6769 6770 netdev_err(priv->dev, "Reset adapter.\n"); 6771 6772 rtnl_lock(); 6773 netif_trans_update(priv->dev); 6774 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6775 usleep_range(1000, 2000); 6776 6777 set_bit(STMMAC_DOWN, &priv->state); 6778 dev_close(priv->dev); 6779 dev_open(priv->dev, NULL); 6780 clear_bit(STMMAC_DOWN, &priv->state); 6781 clear_bit(STMMAC_RESETING, &priv->state); 6782 rtnl_unlock(); 6783 } 6784 6785 static void stmmac_service_task(struct work_struct *work) 6786 { 6787 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6788 service_task); 6789 6790 stmmac_reset_subtask(priv); 6791 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6792 } 6793 6794 /** 6795 * stmmac_hw_init - Init the MAC device 6796 * @priv: driver private structure 6797 * Description: this function is to configure the MAC device according to 6798 * some platform parameters or the HW capability register. It prepares the 6799 * driver to use either ring or chain modes and to setup either enhanced or 6800 * normal descriptors. 6801 */ 6802 static int stmmac_hw_init(struct stmmac_priv *priv) 6803 { 6804 int ret; 6805 6806 /* dwmac-sun8i only work in chain mode */ 6807 if (priv->plat->has_sun8i) 6808 chain_mode = 1; 6809 priv->chain_mode = chain_mode; 6810 6811 /* Initialize HW Interface */ 6812 ret = stmmac_hwif_init(priv); 6813 if (ret) 6814 return ret; 6815 6816 /* Get the HW capability (new GMAC newer than 3.50a) */ 6817 priv->hw_cap_support = stmmac_get_hw_features(priv); 6818 if (priv->hw_cap_support) { 6819 dev_info(priv->device, "DMA HW capability register supported\n"); 6820 6821 /* We can override some gmac/dma configuration fields: e.g. 6822 * enh_desc, tx_coe (e.g. that are passed through the 6823 * platform) with the values from the HW capability 6824 * register (if supported). 6825 */ 6826 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6827 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6828 !priv->plat->use_phy_wol; 6829 priv->hw->pmt = priv->plat->pmt; 6830 if (priv->dma_cap.hash_tb_sz) { 6831 priv->hw->multicast_filter_bins = 6832 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6833 priv->hw->mcast_bits_log2 = 6834 ilog2(priv->hw->multicast_filter_bins); 6835 } 6836 6837 /* TXCOE doesn't work in thresh DMA mode */ 6838 if (priv->plat->force_thresh_dma_mode) 6839 priv->plat->tx_coe = 0; 6840 else 6841 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6842 6843 /* In case of GMAC4 rx_coe is from HW cap register. */ 6844 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6845 6846 if (priv->dma_cap.rx_coe_type2) 6847 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6848 else if (priv->dma_cap.rx_coe_type1) 6849 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6850 6851 } else { 6852 dev_info(priv->device, "No HW DMA feature register supported\n"); 6853 } 6854 6855 if (priv->plat->rx_coe) { 6856 priv->hw->rx_csum = priv->plat->rx_coe; 6857 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6858 if (priv->synopsys_id < DWMAC_CORE_4_00) 6859 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6860 } 6861 if (priv->plat->tx_coe) 6862 dev_info(priv->device, "TX Checksum insertion supported\n"); 6863 6864 if (priv->plat->pmt) { 6865 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6866 device_set_wakeup_capable(priv->device, 1); 6867 } 6868 6869 if (priv->dma_cap.tsoen) 6870 dev_info(priv->device, "TSO supported\n"); 6871 6872 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6873 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6874 6875 /* Run HW quirks, if any */ 6876 if (priv->hwif_quirks) { 6877 ret = priv->hwif_quirks(priv); 6878 if (ret) 6879 return ret; 6880 } 6881 6882 /* Rx Watchdog is available in the COREs newer than the 3.40. 6883 * In some case, for example on bugged HW this feature 6884 * has to be disable and this can be done by passing the 6885 * riwt_off field from the platform. 6886 */ 6887 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6888 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6889 priv->use_riwt = 1; 6890 dev_info(priv->device, 6891 "Enable RX Mitigation via HW Watchdog Timer\n"); 6892 } 6893 6894 return 0; 6895 } 6896 6897 static void stmmac_napi_add(struct net_device *dev) 6898 { 6899 struct stmmac_priv *priv = netdev_priv(dev); 6900 u32 queue, maxq; 6901 6902 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6903 6904 for (queue = 0; queue < maxq; queue++) { 6905 struct stmmac_channel *ch = &priv->channel[queue]; 6906 6907 ch->priv_data = priv; 6908 ch->index = queue; 6909 spin_lock_init(&ch->lock); 6910 6911 if (queue < priv->plat->rx_queues_to_use) { 6912 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6913 } 6914 if (queue < priv->plat->tx_queues_to_use) { 6915 netif_napi_add_tx(dev, &ch->tx_napi, 6916 stmmac_napi_poll_tx); 6917 } 6918 if (queue < priv->plat->rx_queues_to_use && 6919 queue < priv->plat->tx_queues_to_use) { 6920 netif_napi_add(dev, &ch->rxtx_napi, 6921 stmmac_napi_poll_rxtx); 6922 } 6923 } 6924 } 6925 6926 static void stmmac_napi_del(struct net_device *dev) 6927 { 6928 struct stmmac_priv *priv = netdev_priv(dev); 6929 u32 queue, maxq; 6930 6931 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6932 6933 for (queue = 0; queue < maxq; queue++) { 6934 struct stmmac_channel *ch = &priv->channel[queue]; 6935 6936 if (queue < priv->plat->rx_queues_to_use) 6937 netif_napi_del(&ch->rx_napi); 6938 if (queue < priv->plat->tx_queues_to_use) 6939 netif_napi_del(&ch->tx_napi); 6940 if (queue < priv->plat->rx_queues_to_use && 6941 queue < priv->plat->tx_queues_to_use) { 6942 netif_napi_del(&ch->rxtx_napi); 6943 } 6944 } 6945 } 6946 6947 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6948 { 6949 struct stmmac_priv *priv = netdev_priv(dev); 6950 int ret = 0; 6951 6952 if (netif_running(dev)) 6953 stmmac_release(dev); 6954 6955 stmmac_napi_del(dev); 6956 6957 priv->plat->rx_queues_to_use = rx_cnt; 6958 priv->plat->tx_queues_to_use = tx_cnt; 6959 6960 stmmac_napi_add(dev); 6961 6962 if (netif_running(dev)) 6963 ret = stmmac_open(dev); 6964 6965 return ret; 6966 } 6967 6968 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6969 { 6970 struct stmmac_priv *priv = netdev_priv(dev); 6971 int ret = 0; 6972 6973 if (netif_running(dev)) 6974 stmmac_release(dev); 6975 6976 priv->dma_conf.dma_rx_size = rx_size; 6977 priv->dma_conf.dma_tx_size = tx_size; 6978 6979 if (netif_running(dev)) 6980 ret = stmmac_open(dev); 6981 6982 return ret; 6983 } 6984 6985 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6986 static void stmmac_fpe_lp_task(struct work_struct *work) 6987 { 6988 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6989 fpe_task); 6990 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6991 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6992 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6993 bool *hs_enable = &fpe_cfg->hs_enable; 6994 bool *enable = &fpe_cfg->enable; 6995 int retries = 20; 6996 6997 while (retries-- > 0) { 6998 /* Bail out immediately if FPE handshake is OFF */ 6999 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 7000 break; 7001 7002 if (*lo_state == FPE_STATE_ENTERING_ON && 7003 *lp_state == FPE_STATE_ENTERING_ON) { 7004 stmmac_fpe_configure(priv, priv->ioaddr, 7005 priv->plat->tx_queues_to_use, 7006 priv->plat->rx_queues_to_use, 7007 *enable); 7008 7009 netdev_info(priv->dev, "configured FPE\n"); 7010 7011 *lo_state = FPE_STATE_ON; 7012 *lp_state = FPE_STATE_ON; 7013 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7014 break; 7015 } 7016 7017 if ((*lo_state == FPE_STATE_CAPABLE || 7018 *lo_state == FPE_STATE_ENTERING_ON) && 7019 *lp_state != FPE_STATE_ON) { 7020 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7021 *lo_state, *lp_state); 7022 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7023 MPACKET_VERIFY); 7024 } 7025 /* Sleep then retry */ 7026 msleep(500); 7027 } 7028 7029 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7030 } 7031 7032 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7033 { 7034 if (priv->plat->fpe_cfg->hs_enable != enable) { 7035 if (enable) { 7036 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7037 MPACKET_VERIFY); 7038 } else { 7039 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7040 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7041 } 7042 7043 priv->plat->fpe_cfg->hs_enable = enable; 7044 } 7045 } 7046 7047 /** 7048 * stmmac_dvr_probe 7049 * @device: device pointer 7050 * @plat_dat: platform data pointer 7051 * @res: stmmac resource pointer 7052 * Description: this is the main probe function used to 7053 * call the alloc_etherdev, allocate the priv structure. 7054 * Return: 7055 * returns 0 on success, otherwise errno. 7056 */ 7057 int stmmac_dvr_probe(struct device *device, 7058 struct plat_stmmacenet_data *plat_dat, 7059 struct stmmac_resources *res) 7060 { 7061 struct net_device *ndev = NULL; 7062 struct stmmac_priv *priv; 7063 u32 rxq; 7064 int i, ret = 0; 7065 7066 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7067 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7068 if (!ndev) 7069 return -ENOMEM; 7070 7071 SET_NETDEV_DEV(ndev, device); 7072 7073 priv = netdev_priv(ndev); 7074 priv->device = device; 7075 priv->dev = ndev; 7076 7077 stmmac_set_ethtool_ops(ndev); 7078 priv->pause = pause; 7079 priv->plat = plat_dat; 7080 priv->ioaddr = res->addr; 7081 priv->dev->base_addr = (unsigned long)res->addr; 7082 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7083 7084 priv->dev->irq = res->irq; 7085 priv->wol_irq = res->wol_irq; 7086 priv->lpi_irq = res->lpi_irq; 7087 priv->sfty_ce_irq = res->sfty_ce_irq; 7088 priv->sfty_ue_irq = res->sfty_ue_irq; 7089 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7090 priv->rx_irq[i] = res->rx_irq[i]; 7091 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7092 priv->tx_irq[i] = res->tx_irq[i]; 7093 7094 if (!is_zero_ether_addr(res->mac)) 7095 eth_hw_addr_set(priv->dev, res->mac); 7096 7097 dev_set_drvdata(device, priv->dev); 7098 7099 /* Verify driver arguments */ 7100 stmmac_verify_args(); 7101 7102 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7103 if (!priv->af_xdp_zc_qps) 7104 return -ENOMEM; 7105 7106 /* Allocate workqueue */ 7107 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7108 if (!priv->wq) { 7109 dev_err(priv->device, "failed to create workqueue\n"); 7110 ret = -ENOMEM; 7111 goto error_wq_init; 7112 } 7113 7114 INIT_WORK(&priv->service_task, stmmac_service_task); 7115 7116 /* Initialize Link Partner FPE workqueue */ 7117 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7118 7119 /* Override with kernel parameters if supplied XXX CRS XXX 7120 * this needs to have multiple instances 7121 */ 7122 if ((phyaddr >= 0) && (phyaddr <= 31)) 7123 priv->plat->phy_addr = phyaddr; 7124 7125 if (priv->plat->stmmac_rst) { 7126 ret = reset_control_assert(priv->plat->stmmac_rst); 7127 reset_control_deassert(priv->plat->stmmac_rst); 7128 /* Some reset controllers have only reset callback instead of 7129 * assert + deassert callbacks pair. 7130 */ 7131 if (ret == -ENOTSUPP) 7132 reset_control_reset(priv->plat->stmmac_rst); 7133 } 7134 7135 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7136 if (ret == -ENOTSUPP) 7137 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7138 ERR_PTR(ret)); 7139 7140 /* Init MAC and get the capabilities */ 7141 ret = stmmac_hw_init(priv); 7142 if (ret) 7143 goto error_hw_init; 7144 7145 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7146 */ 7147 if (priv->synopsys_id < DWMAC_CORE_5_20) 7148 priv->plat->dma_cfg->dche = false; 7149 7150 stmmac_check_ether_addr(priv); 7151 7152 ndev->netdev_ops = &stmmac_netdev_ops; 7153 7154 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7155 NETIF_F_RXCSUM; 7156 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7157 NETDEV_XDP_ACT_XSK_ZEROCOPY | 7158 NETDEV_XDP_ACT_NDO_XMIT; 7159 7160 ret = stmmac_tc_init(priv, priv); 7161 if (!ret) { 7162 ndev->hw_features |= NETIF_F_HW_TC; 7163 } 7164 7165 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7166 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7167 if (priv->plat->has_gmac4) 7168 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7169 priv->tso = true; 7170 dev_info(priv->device, "TSO feature enabled\n"); 7171 } 7172 7173 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7174 ndev->hw_features |= NETIF_F_GRO; 7175 priv->sph_cap = true; 7176 priv->sph = priv->sph_cap; 7177 dev_info(priv->device, "SPH feature enabled\n"); 7178 } 7179 7180 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7181 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7182 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7183 * So overwrite dma_cap.addr64 according to HW real design. 7184 */ 7185 if (priv->plat->addr64) 7186 priv->dma_cap.addr64 = priv->plat->addr64; 7187 7188 if (priv->dma_cap.addr64) { 7189 ret = dma_set_mask_and_coherent(device, 7190 DMA_BIT_MASK(priv->dma_cap.addr64)); 7191 if (!ret) { 7192 dev_info(priv->device, "Using %d bits DMA width\n", 7193 priv->dma_cap.addr64); 7194 7195 /* 7196 * If more than 32 bits can be addressed, make sure to 7197 * enable enhanced addressing mode. 7198 */ 7199 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7200 priv->plat->dma_cfg->eame = true; 7201 } else { 7202 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7203 if (ret) { 7204 dev_err(priv->device, "Failed to set DMA Mask\n"); 7205 goto error_hw_init; 7206 } 7207 7208 priv->dma_cap.addr64 = 32; 7209 } 7210 } 7211 7212 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7213 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7214 #ifdef STMMAC_VLAN_TAG_USED 7215 /* Both mac100 and gmac support receive VLAN tag detection */ 7216 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7217 if (priv->dma_cap.vlhash) { 7218 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7219 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7220 } 7221 if (priv->dma_cap.vlins) { 7222 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7223 if (priv->dma_cap.dvlan) 7224 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7225 } 7226 #endif 7227 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7228 7229 /* Initialize RSS */ 7230 rxq = priv->plat->rx_queues_to_use; 7231 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7232 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7233 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7234 7235 if (priv->dma_cap.rssen && priv->plat->rss_en) 7236 ndev->features |= NETIF_F_RXHASH; 7237 7238 /* MTU range: 46 - hw-specific max */ 7239 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7240 if (priv->plat->has_xgmac) 7241 ndev->max_mtu = XGMAC_JUMBO_LEN; 7242 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7243 ndev->max_mtu = JUMBO_LEN; 7244 else 7245 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7246 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7247 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7248 */ 7249 if ((priv->plat->maxmtu < ndev->max_mtu) && 7250 (priv->plat->maxmtu >= ndev->min_mtu)) 7251 ndev->max_mtu = priv->plat->maxmtu; 7252 else if (priv->plat->maxmtu < ndev->min_mtu) 7253 dev_warn(priv->device, 7254 "%s: warning: maxmtu having invalid value (%d)\n", 7255 __func__, priv->plat->maxmtu); 7256 7257 if (flow_ctrl) 7258 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7259 7260 /* Setup channels NAPI */ 7261 stmmac_napi_add(ndev); 7262 7263 mutex_init(&priv->lock); 7264 7265 /* If a specific clk_csr value is passed from the platform 7266 * this means that the CSR Clock Range selection cannot be 7267 * changed at run-time and it is fixed. Viceversa the driver'll try to 7268 * set the MDC clock dynamically according to the csr actual 7269 * clock input. 7270 */ 7271 if (priv->plat->clk_csr >= 0) 7272 priv->clk_csr = priv->plat->clk_csr; 7273 else 7274 stmmac_clk_csr_set(priv); 7275 7276 stmmac_check_pcs_mode(priv); 7277 7278 pm_runtime_get_noresume(device); 7279 pm_runtime_set_active(device); 7280 if (!pm_runtime_enabled(device)) 7281 pm_runtime_enable(device); 7282 7283 if (priv->hw->pcs != STMMAC_PCS_TBI && 7284 priv->hw->pcs != STMMAC_PCS_RTBI) { 7285 /* MDIO bus Registration */ 7286 ret = stmmac_mdio_register(ndev); 7287 if (ret < 0) { 7288 dev_err_probe(priv->device, ret, 7289 "%s: MDIO bus (id: %d) registration failed\n", 7290 __func__, priv->plat->bus_id); 7291 goto error_mdio_register; 7292 } 7293 } 7294 7295 if (priv->plat->speed_mode_2500) 7296 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7297 7298 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7299 ret = stmmac_xpcs_setup(priv->mii); 7300 if (ret) 7301 goto error_xpcs_setup; 7302 } 7303 7304 ret = stmmac_phy_setup(priv); 7305 if (ret) { 7306 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7307 goto error_phy_setup; 7308 } 7309 7310 ret = register_netdev(ndev); 7311 if (ret) { 7312 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7313 __func__, ret); 7314 goto error_netdev_register; 7315 } 7316 7317 #ifdef CONFIG_DEBUG_FS 7318 stmmac_init_fs(ndev); 7319 #endif 7320 7321 if (priv->plat->dump_debug_regs) 7322 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7323 7324 /* Let pm_runtime_put() disable the clocks. 7325 * If CONFIG_PM is not enabled, the clocks will stay powered. 7326 */ 7327 pm_runtime_put(device); 7328 7329 return ret; 7330 7331 error_netdev_register: 7332 phylink_destroy(priv->phylink); 7333 error_xpcs_setup: 7334 error_phy_setup: 7335 if (priv->hw->pcs != STMMAC_PCS_TBI && 7336 priv->hw->pcs != STMMAC_PCS_RTBI) 7337 stmmac_mdio_unregister(ndev); 7338 error_mdio_register: 7339 stmmac_napi_del(ndev); 7340 error_hw_init: 7341 destroy_workqueue(priv->wq); 7342 error_wq_init: 7343 bitmap_free(priv->af_xdp_zc_qps); 7344 7345 return ret; 7346 } 7347 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7348 7349 /** 7350 * stmmac_dvr_remove 7351 * @dev: device pointer 7352 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7353 * changes the link status, releases the DMA descriptor rings. 7354 */ 7355 void stmmac_dvr_remove(struct device *dev) 7356 { 7357 struct net_device *ndev = dev_get_drvdata(dev); 7358 struct stmmac_priv *priv = netdev_priv(ndev); 7359 7360 netdev_info(priv->dev, "%s: removing driver", __func__); 7361 7362 pm_runtime_get_sync(dev); 7363 7364 stmmac_stop_all_dma(priv); 7365 stmmac_mac_set(priv, priv->ioaddr, false); 7366 netif_carrier_off(ndev); 7367 unregister_netdev(ndev); 7368 7369 /* Serdes power down needs to happen after VLAN filter 7370 * is deleted that is triggered by unregister_netdev(). 7371 */ 7372 if (priv->plat->serdes_powerdown) 7373 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7374 7375 #ifdef CONFIG_DEBUG_FS 7376 stmmac_exit_fs(ndev); 7377 #endif 7378 phylink_destroy(priv->phylink); 7379 if (priv->plat->stmmac_rst) 7380 reset_control_assert(priv->plat->stmmac_rst); 7381 reset_control_assert(priv->plat->stmmac_ahb_rst); 7382 if (priv->hw->pcs != STMMAC_PCS_TBI && 7383 priv->hw->pcs != STMMAC_PCS_RTBI) 7384 stmmac_mdio_unregister(ndev); 7385 destroy_workqueue(priv->wq); 7386 mutex_destroy(&priv->lock); 7387 bitmap_free(priv->af_xdp_zc_qps); 7388 7389 pm_runtime_disable(dev); 7390 pm_runtime_put_noidle(dev); 7391 } 7392 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7393 7394 /** 7395 * stmmac_suspend - suspend callback 7396 * @dev: device pointer 7397 * Description: this is the function to suspend the device and it is called 7398 * by the platform driver to stop the network queue, release the resources, 7399 * program the PMT register (for WoL), clean and release driver resources. 7400 */ 7401 int stmmac_suspend(struct device *dev) 7402 { 7403 struct net_device *ndev = dev_get_drvdata(dev); 7404 struct stmmac_priv *priv = netdev_priv(ndev); 7405 u32 chan; 7406 7407 if (!ndev || !netif_running(ndev)) 7408 return 0; 7409 7410 mutex_lock(&priv->lock); 7411 7412 netif_device_detach(ndev); 7413 7414 stmmac_disable_all_queues(priv); 7415 7416 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7417 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7418 7419 if (priv->eee_enabled) { 7420 priv->tx_path_in_lpi_mode = false; 7421 del_timer_sync(&priv->eee_ctrl_timer); 7422 } 7423 7424 /* Stop TX/RX DMA */ 7425 stmmac_stop_all_dma(priv); 7426 7427 if (priv->plat->serdes_powerdown) 7428 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7429 7430 /* Enable Power down mode by programming the PMT regs */ 7431 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7432 stmmac_pmt(priv, priv->hw, priv->wolopts); 7433 priv->irq_wake = 1; 7434 } else { 7435 stmmac_mac_set(priv, priv->ioaddr, false); 7436 pinctrl_pm_select_sleep_state(priv->device); 7437 } 7438 7439 mutex_unlock(&priv->lock); 7440 7441 rtnl_lock(); 7442 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7443 phylink_suspend(priv->phylink, true); 7444 } else { 7445 if (device_may_wakeup(priv->device)) 7446 phylink_speed_down(priv->phylink, false); 7447 phylink_suspend(priv->phylink, false); 7448 } 7449 rtnl_unlock(); 7450 7451 if (priv->dma_cap.fpesel) { 7452 /* Disable FPE */ 7453 stmmac_fpe_configure(priv, priv->ioaddr, 7454 priv->plat->tx_queues_to_use, 7455 priv->plat->rx_queues_to_use, false); 7456 7457 stmmac_fpe_handshake(priv, false); 7458 stmmac_fpe_stop_wq(priv); 7459 } 7460 7461 priv->speed = SPEED_UNKNOWN; 7462 return 0; 7463 } 7464 EXPORT_SYMBOL_GPL(stmmac_suspend); 7465 7466 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7467 { 7468 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7469 7470 rx_q->cur_rx = 0; 7471 rx_q->dirty_rx = 0; 7472 } 7473 7474 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7475 { 7476 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7477 7478 tx_q->cur_tx = 0; 7479 tx_q->dirty_tx = 0; 7480 tx_q->mss = 0; 7481 7482 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7483 } 7484 7485 /** 7486 * stmmac_reset_queues_param - reset queue parameters 7487 * @priv: device pointer 7488 */ 7489 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7490 { 7491 u32 rx_cnt = priv->plat->rx_queues_to_use; 7492 u32 tx_cnt = priv->plat->tx_queues_to_use; 7493 u32 queue; 7494 7495 for (queue = 0; queue < rx_cnt; queue++) 7496 stmmac_reset_rx_queue(priv, queue); 7497 7498 for (queue = 0; queue < tx_cnt; queue++) 7499 stmmac_reset_tx_queue(priv, queue); 7500 } 7501 7502 /** 7503 * stmmac_resume - resume callback 7504 * @dev: device pointer 7505 * Description: when resume this function is invoked to setup the DMA and CORE 7506 * in a usable state. 7507 */ 7508 int stmmac_resume(struct device *dev) 7509 { 7510 struct net_device *ndev = dev_get_drvdata(dev); 7511 struct stmmac_priv *priv = netdev_priv(ndev); 7512 int ret; 7513 7514 if (!netif_running(ndev)) 7515 return 0; 7516 7517 /* Power Down bit, into the PM register, is cleared 7518 * automatically as soon as a magic packet or a Wake-up frame 7519 * is received. Anyway, it's better to manually clear 7520 * this bit because it can generate problems while resuming 7521 * from another devices (e.g. serial console). 7522 */ 7523 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7524 mutex_lock(&priv->lock); 7525 stmmac_pmt(priv, priv->hw, 0); 7526 mutex_unlock(&priv->lock); 7527 priv->irq_wake = 0; 7528 } else { 7529 pinctrl_pm_select_default_state(priv->device); 7530 /* reset the phy so that it's ready */ 7531 if (priv->mii) 7532 stmmac_mdio_reset(priv->mii); 7533 } 7534 7535 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 7536 ret = priv->plat->serdes_powerup(ndev, 7537 priv->plat->bsp_priv); 7538 7539 if (ret < 0) 7540 return ret; 7541 } 7542 7543 rtnl_lock(); 7544 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7545 phylink_resume(priv->phylink); 7546 } else { 7547 phylink_resume(priv->phylink); 7548 if (device_may_wakeup(priv->device)) 7549 phylink_speed_up(priv->phylink); 7550 } 7551 rtnl_unlock(); 7552 7553 rtnl_lock(); 7554 mutex_lock(&priv->lock); 7555 7556 stmmac_reset_queues_param(priv); 7557 7558 stmmac_free_tx_skbufs(priv); 7559 stmmac_clear_descriptors(priv, &priv->dma_conf); 7560 7561 stmmac_hw_setup(ndev, false); 7562 stmmac_init_coalesce(priv); 7563 stmmac_set_rx_mode(ndev); 7564 7565 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7566 7567 stmmac_enable_all_queues(priv); 7568 stmmac_enable_all_dma_irq(priv); 7569 7570 mutex_unlock(&priv->lock); 7571 rtnl_unlock(); 7572 7573 netif_device_attach(ndev); 7574 7575 return 0; 7576 } 7577 EXPORT_SYMBOL_GPL(stmmac_resume); 7578 7579 #ifndef MODULE 7580 static int __init stmmac_cmdline_opt(char *str) 7581 { 7582 char *opt; 7583 7584 if (!str || !*str) 7585 return 1; 7586 while ((opt = strsep(&str, ",")) != NULL) { 7587 if (!strncmp(opt, "debug:", 6)) { 7588 if (kstrtoint(opt + 6, 0, &debug)) 7589 goto err; 7590 } else if (!strncmp(opt, "phyaddr:", 8)) { 7591 if (kstrtoint(opt + 8, 0, &phyaddr)) 7592 goto err; 7593 } else if (!strncmp(opt, "buf_sz:", 7)) { 7594 if (kstrtoint(opt + 7, 0, &buf_sz)) 7595 goto err; 7596 } else if (!strncmp(opt, "tc:", 3)) { 7597 if (kstrtoint(opt + 3, 0, &tc)) 7598 goto err; 7599 } else if (!strncmp(opt, "watchdog:", 9)) { 7600 if (kstrtoint(opt + 9, 0, &watchdog)) 7601 goto err; 7602 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7603 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7604 goto err; 7605 } else if (!strncmp(opt, "pause:", 6)) { 7606 if (kstrtoint(opt + 6, 0, &pause)) 7607 goto err; 7608 } else if (!strncmp(opt, "eee_timer:", 10)) { 7609 if (kstrtoint(opt + 10, 0, &eee_timer)) 7610 goto err; 7611 } else if (!strncmp(opt, "chain_mode:", 11)) { 7612 if (kstrtoint(opt + 11, 0, &chain_mode)) 7613 goto err; 7614 } 7615 } 7616 return 1; 7617 7618 err: 7619 pr_err("%s: ERROR broken module parameter conversion", __func__); 7620 return 1; 7621 } 7622 7623 __setup("stmmaceth=", stmmac_cmdline_opt); 7624 #endif /* MODULE */ 7625 7626 static int __init stmmac_init(void) 7627 { 7628 #ifdef CONFIG_DEBUG_FS 7629 /* Create debugfs main directory if it doesn't exist yet */ 7630 if (!stmmac_fs_dir) 7631 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7632 register_netdevice_notifier(&stmmac_notifier); 7633 #endif 7634 7635 return 0; 7636 } 7637 7638 static void __exit stmmac_exit(void) 7639 { 7640 #ifdef CONFIG_DEBUG_FS 7641 unregister_netdevice_notifier(&stmmac_notifier); 7642 debugfs_remove_recursive(stmmac_fs_dir); 7643 #endif 7644 } 7645 7646 module_init(stmmac_init) 7647 module_exit(stmmac_exit) 7648 7649 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7650 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7651 MODULE_LICENSE("GPL"); 7652