1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 if (priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) 992 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 993 994 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 995 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 996 997 if (interface == PHY_INTERFACE_MODE_USXGMII) { 998 switch (speed) { 999 case SPEED_10000: 1000 ctrl |= priv->hw->link.xgmii.speed10000; 1001 break; 1002 case SPEED_5000: 1003 ctrl |= priv->hw->link.xgmii.speed5000; 1004 break; 1005 case SPEED_2500: 1006 ctrl |= priv->hw->link.xgmii.speed2500; 1007 break; 1008 default: 1009 return; 1010 } 1011 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1012 switch (speed) { 1013 case SPEED_100000: 1014 ctrl |= priv->hw->link.xlgmii.speed100000; 1015 break; 1016 case SPEED_50000: 1017 ctrl |= priv->hw->link.xlgmii.speed50000; 1018 break; 1019 case SPEED_40000: 1020 ctrl |= priv->hw->link.xlgmii.speed40000; 1021 break; 1022 case SPEED_25000: 1023 ctrl |= priv->hw->link.xlgmii.speed25000; 1024 break; 1025 case SPEED_10000: 1026 ctrl |= priv->hw->link.xgmii.speed10000; 1027 break; 1028 case SPEED_2500: 1029 ctrl |= priv->hw->link.speed2500; 1030 break; 1031 case SPEED_1000: 1032 ctrl |= priv->hw->link.speed1000; 1033 break; 1034 default: 1035 return; 1036 } 1037 } else { 1038 switch (speed) { 1039 case SPEED_2500: 1040 ctrl |= priv->hw->link.speed2500; 1041 break; 1042 case SPEED_1000: 1043 ctrl |= priv->hw->link.speed1000; 1044 break; 1045 case SPEED_100: 1046 ctrl |= priv->hw->link.speed100; 1047 break; 1048 case SPEED_10: 1049 ctrl |= priv->hw->link.speed10; 1050 break; 1051 default: 1052 return; 1053 } 1054 } 1055 1056 priv->speed = speed; 1057 1058 if (priv->plat->fix_mac_speed) 1059 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1060 1061 if (!duplex) 1062 ctrl &= ~priv->hw->link.duplex; 1063 else 1064 ctrl |= priv->hw->link.duplex; 1065 1066 /* Flow Control operation */ 1067 if (rx_pause && tx_pause) 1068 priv->flow_ctrl = FLOW_AUTO; 1069 else if (rx_pause && !tx_pause) 1070 priv->flow_ctrl = FLOW_RX; 1071 else if (!rx_pause && tx_pause) 1072 priv->flow_ctrl = FLOW_TX; 1073 else 1074 priv->flow_ctrl = FLOW_OFF; 1075 1076 stmmac_mac_flow_ctrl(priv, duplex); 1077 1078 if (ctrl != old_ctrl) 1079 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1080 1081 stmmac_mac_set(priv, priv->ioaddr, true); 1082 if (phy && priv->dma_cap.eee) { 1083 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1084 priv->eee_enabled = stmmac_eee_init(priv); 1085 priv->tx_lpi_enabled = priv->eee_enabled; 1086 stmmac_set_eee_pls(priv, priv->hw, true); 1087 } 1088 1089 if (priv->dma_cap.fpesel) 1090 stmmac_fpe_link_state_handle(priv, true); 1091 } 1092 1093 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1094 .mac_select_pcs = stmmac_mac_select_pcs, 1095 .mac_config = stmmac_mac_config, 1096 .mac_link_down = stmmac_mac_link_down, 1097 .mac_link_up = stmmac_mac_link_up, 1098 }; 1099 1100 /** 1101 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1102 * @priv: driver private structure 1103 * Description: this is to verify if the HW supports the PCS. 1104 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1105 * configured for the TBI, RTBI, or SGMII PHY interface. 1106 */ 1107 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1108 { 1109 int interface = priv->plat->interface; 1110 1111 if (priv->dma_cap.pcs) { 1112 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1113 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1114 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1115 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1116 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1117 priv->hw->pcs = STMMAC_PCS_RGMII; 1118 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1119 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1120 priv->hw->pcs = STMMAC_PCS_SGMII; 1121 } 1122 } 1123 } 1124 1125 /** 1126 * stmmac_init_phy - PHY initialization 1127 * @dev: net device structure 1128 * Description: it initializes the driver's PHY state, and attaches the PHY 1129 * to the mac driver. 1130 * Return value: 1131 * 0 on success 1132 */ 1133 static int stmmac_init_phy(struct net_device *dev) 1134 { 1135 struct stmmac_priv *priv = netdev_priv(dev); 1136 struct fwnode_handle *fwnode; 1137 int ret; 1138 1139 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1140 if (!fwnode) 1141 fwnode = dev_fwnode(priv->device); 1142 1143 if (fwnode) 1144 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1145 1146 /* Some DT bindings do not set-up the PHY handle. Let's try to 1147 * manually parse it 1148 */ 1149 if (!fwnode || ret) { 1150 int addr = priv->plat->phy_addr; 1151 struct phy_device *phydev; 1152 1153 if (addr < 0) { 1154 netdev_err(priv->dev, "no phy found\n"); 1155 return -ENODEV; 1156 } 1157 1158 phydev = mdiobus_get_phy(priv->mii, addr); 1159 if (!phydev) { 1160 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1161 return -ENODEV; 1162 } 1163 1164 ret = phylink_connect_phy(priv->phylink, phydev); 1165 } 1166 1167 if (!priv->plat->pmt) { 1168 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1169 1170 phylink_ethtool_get_wol(priv->phylink, &wol); 1171 device_set_wakeup_capable(priv->device, !!wol.supported); 1172 } 1173 1174 return ret; 1175 } 1176 1177 static int stmmac_phy_setup(struct stmmac_priv *priv) 1178 { 1179 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1180 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1181 int max_speed = priv->plat->max_speed; 1182 int mode = priv->plat->phy_interface; 1183 struct phylink *phylink; 1184 1185 priv->phylink_config.dev = &priv->dev->dev; 1186 priv->phylink_config.type = PHYLINK_NETDEV; 1187 if (priv->plat->mdio_bus_data) 1188 priv->phylink_config.ovr_an_inband = 1189 mdio_bus_data->xpcs_an_inband; 1190 1191 if (!fwnode) 1192 fwnode = dev_fwnode(priv->device); 1193 1194 /* Set the platform/firmware specified interface mode */ 1195 __set_bit(mode, priv->phylink_config.supported_interfaces); 1196 1197 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1198 if (priv->hw->xpcs) 1199 xpcs_get_interfaces(priv->hw->xpcs, 1200 priv->phylink_config.supported_interfaces); 1201 1202 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1203 MAC_10 | MAC_100; 1204 1205 if (!max_speed || max_speed >= 1000) 1206 priv->phylink_config.mac_capabilities |= MAC_1000; 1207 1208 if (priv->plat->has_gmac4) { 1209 if (!max_speed || max_speed >= 2500) 1210 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1211 } else if (priv->plat->has_xgmac) { 1212 if (!max_speed || max_speed >= 2500) 1213 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1214 if (!max_speed || max_speed >= 5000) 1215 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1216 if (!max_speed || max_speed >= 10000) 1217 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1218 if (!max_speed || max_speed >= 25000) 1219 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1220 if (!max_speed || max_speed >= 40000) 1221 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1222 if (!max_speed || max_speed >= 50000) 1223 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1224 if (!max_speed || max_speed >= 100000) 1225 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1226 } 1227 1228 /* Half-Duplex can only work with single queue */ 1229 if (priv->plat->tx_queues_to_use > 1) 1230 priv->phylink_config.mac_capabilities &= 1231 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1232 priv->phylink_config.mac_managed_pm = true; 1233 1234 phylink = phylink_create(&priv->phylink_config, fwnode, 1235 mode, &stmmac_phylink_mac_ops); 1236 if (IS_ERR(phylink)) 1237 return PTR_ERR(phylink); 1238 1239 priv->phylink = phylink; 1240 return 0; 1241 } 1242 1243 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1244 struct stmmac_dma_conf *dma_conf) 1245 { 1246 u32 rx_cnt = priv->plat->rx_queues_to_use; 1247 unsigned int desc_size; 1248 void *head_rx; 1249 u32 queue; 1250 1251 /* Display RX rings */ 1252 for (queue = 0; queue < rx_cnt; queue++) { 1253 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1254 1255 pr_info("\tRX Queue %u rings\n", queue); 1256 1257 if (priv->extend_desc) { 1258 head_rx = (void *)rx_q->dma_erx; 1259 desc_size = sizeof(struct dma_extended_desc); 1260 } else { 1261 head_rx = (void *)rx_q->dma_rx; 1262 desc_size = sizeof(struct dma_desc); 1263 } 1264 1265 /* Display RX ring */ 1266 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1267 rx_q->dma_rx_phy, desc_size); 1268 } 1269 } 1270 1271 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1272 struct stmmac_dma_conf *dma_conf) 1273 { 1274 u32 tx_cnt = priv->plat->tx_queues_to_use; 1275 unsigned int desc_size; 1276 void *head_tx; 1277 u32 queue; 1278 1279 /* Display TX rings */ 1280 for (queue = 0; queue < tx_cnt; queue++) { 1281 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1282 1283 pr_info("\tTX Queue %d rings\n", queue); 1284 1285 if (priv->extend_desc) { 1286 head_tx = (void *)tx_q->dma_etx; 1287 desc_size = sizeof(struct dma_extended_desc); 1288 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1289 head_tx = (void *)tx_q->dma_entx; 1290 desc_size = sizeof(struct dma_edesc); 1291 } else { 1292 head_tx = (void *)tx_q->dma_tx; 1293 desc_size = sizeof(struct dma_desc); 1294 } 1295 1296 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1297 tx_q->dma_tx_phy, desc_size); 1298 } 1299 } 1300 1301 static void stmmac_display_rings(struct stmmac_priv *priv, 1302 struct stmmac_dma_conf *dma_conf) 1303 { 1304 /* Display RX ring */ 1305 stmmac_display_rx_rings(priv, dma_conf); 1306 1307 /* Display TX ring */ 1308 stmmac_display_tx_rings(priv, dma_conf); 1309 } 1310 1311 static int stmmac_set_bfsize(int mtu, int bufsize) 1312 { 1313 int ret = bufsize; 1314 1315 if (mtu >= BUF_SIZE_8KiB) 1316 ret = BUF_SIZE_16KiB; 1317 else if (mtu >= BUF_SIZE_4KiB) 1318 ret = BUF_SIZE_8KiB; 1319 else if (mtu >= BUF_SIZE_2KiB) 1320 ret = BUF_SIZE_4KiB; 1321 else if (mtu > DEFAULT_BUFSIZE) 1322 ret = BUF_SIZE_2KiB; 1323 else 1324 ret = DEFAULT_BUFSIZE; 1325 1326 return ret; 1327 } 1328 1329 /** 1330 * stmmac_clear_rx_descriptors - clear RX descriptors 1331 * @priv: driver private structure 1332 * @dma_conf: structure to take the dma data 1333 * @queue: RX queue index 1334 * Description: this function is called to clear the RX descriptors 1335 * in case of both basic and extended descriptors are used. 1336 */ 1337 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1338 struct stmmac_dma_conf *dma_conf, 1339 u32 queue) 1340 { 1341 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1342 int i; 1343 1344 /* Clear the RX descriptors */ 1345 for (i = 0; i < dma_conf->dma_rx_size; i++) 1346 if (priv->extend_desc) 1347 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1348 priv->use_riwt, priv->mode, 1349 (i == dma_conf->dma_rx_size - 1), 1350 dma_conf->dma_buf_sz); 1351 else 1352 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1353 priv->use_riwt, priv->mode, 1354 (i == dma_conf->dma_rx_size - 1), 1355 dma_conf->dma_buf_sz); 1356 } 1357 1358 /** 1359 * stmmac_clear_tx_descriptors - clear tx descriptors 1360 * @priv: driver private structure 1361 * @dma_conf: structure to take the dma data 1362 * @queue: TX queue index. 1363 * Description: this function is called to clear the TX descriptors 1364 * in case of both basic and extended descriptors are used. 1365 */ 1366 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1367 struct stmmac_dma_conf *dma_conf, 1368 u32 queue) 1369 { 1370 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1371 int i; 1372 1373 /* Clear the TX descriptors */ 1374 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1375 int last = (i == (dma_conf->dma_tx_size - 1)); 1376 struct dma_desc *p; 1377 1378 if (priv->extend_desc) 1379 p = &tx_q->dma_etx[i].basic; 1380 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1381 p = &tx_q->dma_entx[i].basic; 1382 else 1383 p = &tx_q->dma_tx[i]; 1384 1385 stmmac_init_tx_desc(priv, p, priv->mode, last); 1386 } 1387 } 1388 1389 /** 1390 * stmmac_clear_descriptors - clear descriptors 1391 * @priv: driver private structure 1392 * @dma_conf: structure to take the dma data 1393 * Description: this function is called to clear the TX and RX descriptors 1394 * in case of both basic and extended descriptors are used. 1395 */ 1396 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1397 struct stmmac_dma_conf *dma_conf) 1398 { 1399 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1400 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1401 u32 queue; 1402 1403 /* Clear the RX descriptors */ 1404 for (queue = 0; queue < rx_queue_cnt; queue++) 1405 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1406 1407 /* Clear the TX descriptors */ 1408 for (queue = 0; queue < tx_queue_cnt; queue++) 1409 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1410 } 1411 1412 /** 1413 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1414 * @priv: driver private structure 1415 * @dma_conf: structure to take the dma data 1416 * @p: descriptor pointer 1417 * @i: descriptor index 1418 * @flags: gfp flag 1419 * @queue: RX queue index 1420 * Description: this function is called to allocate a receive buffer, perform 1421 * the DMA mapping and init the descriptor. 1422 */ 1423 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1424 struct stmmac_dma_conf *dma_conf, 1425 struct dma_desc *p, 1426 int i, gfp_t flags, u32 queue) 1427 { 1428 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1429 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1430 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1431 1432 if (priv->dma_cap.addr64 <= 32) 1433 gfp |= GFP_DMA32; 1434 1435 if (!buf->page) { 1436 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1437 if (!buf->page) 1438 return -ENOMEM; 1439 buf->page_offset = stmmac_rx_offset(priv); 1440 } 1441 1442 if (priv->sph && !buf->sec_page) { 1443 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1444 if (!buf->sec_page) 1445 return -ENOMEM; 1446 1447 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1448 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1449 } else { 1450 buf->sec_page = NULL; 1451 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1452 } 1453 1454 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1455 1456 stmmac_set_desc_addr(priv, p, buf->addr); 1457 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1458 stmmac_init_desc3(priv, p); 1459 1460 return 0; 1461 } 1462 1463 /** 1464 * stmmac_free_rx_buffer - free RX dma buffers 1465 * @priv: private structure 1466 * @rx_q: RX queue 1467 * @i: buffer index. 1468 */ 1469 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1470 struct stmmac_rx_queue *rx_q, 1471 int i) 1472 { 1473 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1474 1475 if (buf->page) 1476 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1477 buf->page = NULL; 1478 1479 if (buf->sec_page) 1480 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1481 buf->sec_page = NULL; 1482 } 1483 1484 /** 1485 * stmmac_free_tx_buffer - free RX dma buffers 1486 * @priv: private structure 1487 * @dma_conf: structure to take the dma data 1488 * @queue: RX queue index 1489 * @i: buffer index. 1490 */ 1491 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1492 struct stmmac_dma_conf *dma_conf, 1493 u32 queue, int i) 1494 { 1495 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1496 1497 if (tx_q->tx_skbuff_dma[i].buf && 1498 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1499 if (tx_q->tx_skbuff_dma[i].map_as_page) 1500 dma_unmap_page(priv->device, 1501 tx_q->tx_skbuff_dma[i].buf, 1502 tx_q->tx_skbuff_dma[i].len, 1503 DMA_TO_DEVICE); 1504 else 1505 dma_unmap_single(priv->device, 1506 tx_q->tx_skbuff_dma[i].buf, 1507 tx_q->tx_skbuff_dma[i].len, 1508 DMA_TO_DEVICE); 1509 } 1510 1511 if (tx_q->xdpf[i] && 1512 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1513 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1514 xdp_return_frame(tx_q->xdpf[i]); 1515 tx_q->xdpf[i] = NULL; 1516 } 1517 1518 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1519 tx_q->xsk_frames_done++; 1520 1521 if (tx_q->tx_skbuff[i] && 1522 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1523 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1524 tx_q->tx_skbuff[i] = NULL; 1525 } 1526 1527 tx_q->tx_skbuff_dma[i].buf = 0; 1528 tx_q->tx_skbuff_dma[i].map_as_page = false; 1529 } 1530 1531 /** 1532 * dma_free_rx_skbufs - free RX dma buffers 1533 * @priv: private structure 1534 * @dma_conf: structure to take the dma data 1535 * @queue: RX queue index 1536 */ 1537 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1538 struct stmmac_dma_conf *dma_conf, 1539 u32 queue) 1540 { 1541 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1542 int i; 1543 1544 for (i = 0; i < dma_conf->dma_rx_size; i++) 1545 stmmac_free_rx_buffer(priv, rx_q, i); 1546 } 1547 1548 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1549 struct stmmac_dma_conf *dma_conf, 1550 u32 queue, gfp_t flags) 1551 { 1552 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1553 int i; 1554 1555 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1556 struct dma_desc *p; 1557 int ret; 1558 1559 if (priv->extend_desc) 1560 p = &((rx_q->dma_erx + i)->basic); 1561 else 1562 p = rx_q->dma_rx + i; 1563 1564 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1565 queue); 1566 if (ret) 1567 return ret; 1568 1569 rx_q->buf_alloc_num++; 1570 } 1571 1572 return 0; 1573 } 1574 1575 /** 1576 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1577 * @priv: private structure 1578 * @dma_conf: structure to take the dma data 1579 * @queue: RX queue index 1580 */ 1581 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1582 struct stmmac_dma_conf *dma_conf, 1583 u32 queue) 1584 { 1585 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1586 int i; 1587 1588 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1589 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1590 1591 if (!buf->xdp) 1592 continue; 1593 1594 xsk_buff_free(buf->xdp); 1595 buf->xdp = NULL; 1596 } 1597 } 1598 1599 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1600 struct stmmac_dma_conf *dma_conf, 1601 u32 queue) 1602 { 1603 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1604 int i; 1605 1606 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1607 struct stmmac_rx_buffer *buf; 1608 dma_addr_t dma_addr; 1609 struct dma_desc *p; 1610 1611 if (priv->extend_desc) 1612 p = (struct dma_desc *)(rx_q->dma_erx + i); 1613 else 1614 p = rx_q->dma_rx + i; 1615 1616 buf = &rx_q->buf_pool[i]; 1617 1618 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1619 if (!buf->xdp) 1620 return -ENOMEM; 1621 1622 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1623 stmmac_set_desc_addr(priv, p, dma_addr); 1624 rx_q->buf_alloc_num++; 1625 } 1626 1627 return 0; 1628 } 1629 1630 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1631 { 1632 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1633 return NULL; 1634 1635 return xsk_get_pool_from_qid(priv->dev, queue); 1636 } 1637 1638 /** 1639 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1640 * @priv: driver private structure 1641 * @dma_conf: structure to take the dma data 1642 * @queue: RX queue index 1643 * @flags: gfp flag. 1644 * Description: this function initializes the DMA RX descriptors 1645 * and allocates the socket buffers. It supports the chained and ring 1646 * modes. 1647 */ 1648 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1649 struct stmmac_dma_conf *dma_conf, 1650 u32 queue, gfp_t flags) 1651 { 1652 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1653 int ret; 1654 1655 netif_dbg(priv, probe, priv->dev, 1656 "(%s) dma_rx_phy=0x%08x\n", __func__, 1657 (u32)rx_q->dma_rx_phy); 1658 1659 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1660 1661 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1662 1663 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1664 1665 if (rx_q->xsk_pool) { 1666 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1667 MEM_TYPE_XSK_BUFF_POOL, 1668 NULL)); 1669 netdev_info(priv->dev, 1670 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1671 rx_q->queue_index); 1672 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1673 } else { 1674 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1675 MEM_TYPE_PAGE_POOL, 1676 rx_q->page_pool)); 1677 netdev_info(priv->dev, 1678 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1679 rx_q->queue_index); 1680 } 1681 1682 if (rx_q->xsk_pool) { 1683 /* RX XDP ZC buffer pool may not be populated, e.g. 1684 * xdpsock TX-only. 1685 */ 1686 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1687 } else { 1688 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1689 if (ret < 0) 1690 return -ENOMEM; 1691 } 1692 1693 /* Setup the chained descriptor addresses */ 1694 if (priv->mode == STMMAC_CHAIN_MODE) { 1695 if (priv->extend_desc) 1696 stmmac_mode_init(priv, rx_q->dma_erx, 1697 rx_q->dma_rx_phy, 1698 dma_conf->dma_rx_size, 1); 1699 else 1700 stmmac_mode_init(priv, rx_q->dma_rx, 1701 rx_q->dma_rx_phy, 1702 dma_conf->dma_rx_size, 0); 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int init_dma_rx_desc_rings(struct net_device *dev, 1709 struct stmmac_dma_conf *dma_conf, 1710 gfp_t flags) 1711 { 1712 struct stmmac_priv *priv = netdev_priv(dev); 1713 u32 rx_count = priv->plat->rx_queues_to_use; 1714 int queue; 1715 int ret; 1716 1717 /* RX INITIALIZATION */ 1718 netif_dbg(priv, probe, priv->dev, 1719 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1720 1721 for (queue = 0; queue < rx_count; queue++) { 1722 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1723 if (ret) 1724 goto err_init_rx_buffers; 1725 } 1726 1727 return 0; 1728 1729 err_init_rx_buffers: 1730 while (queue >= 0) { 1731 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1732 1733 if (rx_q->xsk_pool) 1734 dma_free_rx_xskbufs(priv, dma_conf, queue); 1735 else 1736 dma_free_rx_skbufs(priv, dma_conf, queue); 1737 1738 rx_q->buf_alloc_num = 0; 1739 rx_q->xsk_pool = NULL; 1740 1741 queue--; 1742 } 1743 1744 return ret; 1745 } 1746 1747 /** 1748 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1749 * @priv: driver private structure 1750 * @dma_conf: structure to take the dma data 1751 * @queue: TX queue index 1752 * Description: this function initializes the DMA TX descriptors 1753 * and allocates the socket buffers. It supports the chained and ring 1754 * modes. 1755 */ 1756 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1757 struct stmmac_dma_conf *dma_conf, 1758 u32 queue) 1759 { 1760 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1761 int i; 1762 1763 netif_dbg(priv, probe, priv->dev, 1764 "(%s) dma_tx_phy=0x%08x\n", __func__, 1765 (u32)tx_q->dma_tx_phy); 1766 1767 /* Setup the chained descriptor addresses */ 1768 if (priv->mode == STMMAC_CHAIN_MODE) { 1769 if (priv->extend_desc) 1770 stmmac_mode_init(priv, tx_q->dma_etx, 1771 tx_q->dma_tx_phy, 1772 dma_conf->dma_tx_size, 1); 1773 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1774 stmmac_mode_init(priv, tx_q->dma_tx, 1775 tx_q->dma_tx_phy, 1776 dma_conf->dma_tx_size, 0); 1777 } 1778 1779 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1780 1781 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1782 struct dma_desc *p; 1783 1784 if (priv->extend_desc) 1785 p = &((tx_q->dma_etx + i)->basic); 1786 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1787 p = &((tx_q->dma_entx + i)->basic); 1788 else 1789 p = tx_q->dma_tx + i; 1790 1791 stmmac_clear_desc(priv, p); 1792 1793 tx_q->tx_skbuff_dma[i].buf = 0; 1794 tx_q->tx_skbuff_dma[i].map_as_page = false; 1795 tx_q->tx_skbuff_dma[i].len = 0; 1796 tx_q->tx_skbuff_dma[i].last_segment = false; 1797 tx_q->tx_skbuff[i] = NULL; 1798 } 1799 1800 return 0; 1801 } 1802 1803 static int init_dma_tx_desc_rings(struct net_device *dev, 1804 struct stmmac_dma_conf *dma_conf) 1805 { 1806 struct stmmac_priv *priv = netdev_priv(dev); 1807 u32 tx_queue_cnt; 1808 u32 queue; 1809 1810 tx_queue_cnt = priv->plat->tx_queues_to_use; 1811 1812 for (queue = 0; queue < tx_queue_cnt; queue++) 1813 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1814 1815 return 0; 1816 } 1817 1818 /** 1819 * init_dma_desc_rings - init the RX/TX descriptor rings 1820 * @dev: net device structure 1821 * @dma_conf: structure to take the dma data 1822 * @flags: gfp flag. 1823 * Description: this function initializes the DMA RX/TX descriptors 1824 * and allocates the socket buffers. It supports the chained and ring 1825 * modes. 1826 */ 1827 static int init_dma_desc_rings(struct net_device *dev, 1828 struct stmmac_dma_conf *dma_conf, 1829 gfp_t flags) 1830 { 1831 struct stmmac_priv *priv = netdev_priv(dev); 1832 int ret; 1833 1834 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1835 if (ret) 1836 return ret; 1837 1838 ret = init_dma_tx_desc_rings(dev, dma_conf); 1839 1840 stmmac_clear_descriptors(priv, dma_conf); 1841 1842 if (netif_msg_hw(priv)) 1843 stmmac_display_rings(priv, dma_conf); 1844 1845 return ret; 1846 } 1847 1848 /** 1849 * dma_free_tx_skbufs - free TX dma buffers 1850 * @priv: private structure 1851 * @dma_conf: structure to take the dma data 1852 * @queue: TX queue index 1853 */ 1854 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1855 struct stmmac_dma_conf *dma_conf, 1856 u32 queue) 1857 { 1858 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1859 int i; 1860 1861 tx_q->xsk_frames_done = 0; 1862 1863 for (i = 0; i < dma_conf->dma_tx_size; i++) 1864 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1865 1866 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1867 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1868 tx_q->xsk_frames_done = 0; 1869 tx_q->xsk_pool = NULL; 1870 } 1871 } 1872 1873 /** 1874 * stmmac_free_tx_skbufs - free TX skb buffers 1875 * @priv: private structure 1876 */ 1877 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1878 { 1879 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1880 u32 queue; 1881 1882 for (queue = 0; queue < tx_queue_cnt; queue++) 1883 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1884 } 1885 1886 /** 1887 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1888 * @priv: private structure 1889 * @dma_conf: structure to take the dma data 1890 * @queue: RX queue index 1891 */ 1892 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1893 struct stmmac_dma_conf *dma_conf, 1894 u32 queue) 1895 { 1896 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1897 1898 /* Release the DMA RX socket buffers */ 1899 if (rx_q->xsk_pool) 1900 dma_free_rx_xskbufs(priv, dma_conf, queue); 1901 else 1902 dma_free_rx_skbufs(priv, dma_conf, queue); 1903 1904 rx_q->buf_alloc_num = 0; 1905 rx_q->xsk_pool = NULL; 1906 1907 /* Free DMA regions of consistent memory previously allocated */ 1908 if (!priv->extend_desc) 1909 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1910 sizeof(struct dma_desc), 1911 rx_q->dma_rx, rx_q->dma_rx_phy); 1912 else 1913 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1914 sizeof(struct dma_extended_desc), 1915 rx_q->dma_erx, rx_q->dma_rx_phy); 1916 1917 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1918 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1919 1920 kfree(rx_q->buf_pool); 1921 if (rx_q->page_pool) 1922 page_pool_destroy(rx_q->page_pool); 1923 } 1924 1925 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1926 struct stmmac_dma_conf *dma_conf) 1927 { 1928 u32 rx_count = priv->plat->rx_queues_to_use; 1929 u32 queue; 1930 1931 /* Free RX queue resources */ 1932 for (queue = 0; queue < rx_count; queue++) 1933 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1934 } 1935 1936 /** 1937 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1938 * @priv: private structure 1939 * @dma_conf: structure to take the dma data 1940 * @queue: TX queue index 1941 */ 1942 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1943 struct stmmac_dma_conf *dma_conf, 1944 u32 queue) 1945 { 1946 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1947 size_t size; 1948 void *addr; 1949 1950 /* Release the DMA TX socket buffers */ 1951 dma_free_tx_skbufs(priv, dma_conf, queue); 1952 1953 if (priv->extend_desc) { 1954 size = sizeof(struct dma_extended_desc); 1955 addr = tx_q->dma_etx; 1956 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1957 size = sizeof(struct dma_edesc); 1958 addr = tx_q->dma_entx; 1959 } else { 1960 size = sizeof(struct dma_desc); 1961 addr = tx_q->dma_tx; 1962 } 1963 1964 size *= dma_conf->dma_tx_size; 1965 1966 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1967 1968 kfree(tx_q->tx_skbuff_dma); 1969 kfree(tx_q->tx_skbuff); 1970 } 1971 1972 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1973 struct stmmac_dma_conf *dma_conf) 1974 { 1975 u32 tx_count = priv->plat->tx_queues_to_use; 1976 u32 queue; 1977 1978 /* Free TX queue resources */ 1979 for (queue = 0; queue < tx_count; queue++) 1980 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1981 } 1982 1983 /** 1984 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1985 * @priv: private structure 1986 * @dma_conf: structure to take the dma data 1987 * @queue: RX queue index 1988 * Description: according to which descriptor can be used (extend or basic) 1989 * this function allocates the resources for TX and RX paths. In case of 1990 * reception, for example, it pre-allocated the RX socket buffer in order to 1991 * allow zero-copy mechanism. 1992 */ 1993 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1994 struct stmmac_dma_conf *dma_conf, 1995 u32 queue) 1996 { 1997 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1998 struct stmmac_channel *ch = &priv->channel[queue]; 1999 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2000 struct page_pool_params pp_params = { 0 }; 2001 unsigned int num_pages; 2002 unsigned int napi_id; 2003 int ret; 2004 2005 rx_q->queue_index = queue; 2006 rx_q->priv_data = priv; 2007 2008 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2009 pp_params.pool_size = dma_conf->dma_rx_size; 2010 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2011 pp_params.order = ilog2(num_pages); 2012 pp_params.nid = dev_to_node(priv->device); 2013 pp_params.dev = priv->device; 2014 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2015 pp_params.offset = stmmac_rx_offset(priv); 2016 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2017 2018 rx_q->page_pool = page_pool_create(&pp_params); 2019 if (IS_ERR(rx_q->page_pool)) { 2020 ret = PTR_ERR(rx_q->page_pool); 2021 rx_q->page_pool = NULL; 2022 return ret; 2023 } 2024 2025 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2026 sizeof(*rx_q->buf_pool), 2027 GFP_KERNEL); 2028 if (!rx_q->buf_pool) 2029 return -ENOMEM; 2030 2031 if (priv->extend_desc) { 2032 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2033 dma_conf->dma_rx_size * 2034 sizeof(struct dma_extended_desc), 2035 &rx_q->dma_rx_phy, 2036 GFP_KERNEL); 2037 if (!rx_q->dma_erx) 2038 return -ENOMEM; 2039 2040 } else { 2041 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2042 dma_conf->dma_rx_size * 2043 sizeof(struct dma_desc), 2044 &rx_q->dma_rx_phy, 2045 GFP_KERNEL); 2046 if (!rx_q->dma_rx) 2047 return -ENOMEM; 2048 } 2049 2050 if (stmmac_xdp_is_enabled(priv) && 2051 test_bit(queue, priv->af_xdp_zc_qps)) 2052 napi_id = ch->rxtx_napi.napi_id; 2053 else 2054 napi_id = ch->rx_napi.napi_id; 2055 2056 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2057 rx_q->queue_index, 2058 napi_id); 2059 if (ret) { 2060 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2061 return -EINVAL; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2068 struct stmmac_dma_conf *dma_conf) 2069 { 2070 u32 rx_count = priv->plat->rx_queues_to_use; 2071 u32 queue; 2072 int ret; 2073 2074 /* RX queues buffers and DMA */ 2075 for (queue = 0; queue < rx_count; queue++) { 2076 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2077 if (ret) 2078 goto err_dma; 2079 } 2080 2081 return 0; 2082 2083 err_dma: 2084 free_dma_rx_desc_resources(priv, dma_conf); 2085 2086 return ret; 2087 } 2088 2089 /** 2090 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2091 * @priv: private structure 2092 * @dma_conf: structure to take the dma data 2093 * @queue: TX queue index 2094 * Description: according to which descriptor can be used (extend or basic) 2095 * this function allocates the resources for TX and RX paths. In case of 2096 * reception, for example, it pre-allocated the RX socket buffer in order to 2097 * allow zero-copy mechanism. 2098 */ 2099 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2100 struct stmmac_dma_conf *dma_conf, 2101 u32 queue) 2102 { 2103 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2104 size_t size; 2105 void *addr; 2106 2107 tx_q->queue_index = queue; 2108 tx_q->priv_data = priv; 2109 2110 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2111 sizeof(*tx_q->tx_skbuff_dma), 2112 GFP_KERNEL); 2113 if (!tx_q->tx_skbuff_dma) 2114 return -ENOMEM; 2115 2116 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2117 sizeof(struct sk_buff *), 2118 GFP_KERNEL); 2119 if (!tx_q->tx_skbuff) 2120 return -ENOMEM; 2121 2122 if (priv->extend_desc) 2123 size = sizeof(struct dma_extended_desc); 2124 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2125 size = sizeof(struct dma_edesc); 2126 else 2127 size = sizeof(struct dma_desc); 2128 2129 size *= dma_conf->dma_tx_size; 2130 2131 addr = dma_alloc_coherent(priv->device, size, 2132 &tx_q->dma_tx_phy, GFP_KERNEL); 2133 if (!addr) 2134 return -ENOMEM; 2135 2136 if (priv->extend_desc) 2137 tx_q->dma_etx = addr; 2138 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2139 tx_q->dma_entx = addr; 2140 else 2141 tx_q->dma_tx = addr; 2142 2143 return 0; 2144 } 2145 2146 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2147 struct stmmac_dma_conf *dma_conf) 2148 { 2149 u32 tx_count = priv->plat->tx_queues_to_use; 2150 u32 queue; 2151 int ret; 2152 2153 /* TX queues buffers and DMA */ 2154 for (queue = 0; queue < tx_count; queue++) { 2155 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2156 if (ret) 2157 goto err_dma; 2158 } 2159 2160 return 0; 2161 2162 err_dma: 2163 free_dma_tx_desc_resources(priv, dma_conf); 2164 return ret; 2165 } 2166 2167 /** 2168 * alloc_dma_desc_resources - alloc TX/RX resources. 2169 * @priv: private structure 2170 * @dma_conf: structure to take the dma data 2171 * Description: according to which descriptor can be used (extend or basic) 2172 * this function allocates the resources for TX and RX paths. In case of 2173 * reception, for example, it pre-allocated the RX socket buffer in order to 2174 * allow zero-copy mechanism. 2175 */ 2176 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2177 struct stmmac_dma_conf *dma_conf) 2178 { 2179 /* RX Allocation */ 2180 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2181 2182 if (ret) 2183 return ret; 2184 2185 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2186 2187 return ret; 2188 } 2189 2190 /** 2191 * free_dma_desc_resources - free dma desc resources 2192 * @priv: private structure 2193 * @dma_conf: structure to take the dma data 2194 */ 2195 static void free_dma_desc_resources(struct stmmac_priv *priv, 2196 struct stmmac_dma_conf *dma_conf) 2197 { 2198 /* Release the DMA TX socket buffers */ 2199 free_dma_tx_desc_resources(priv, dma_conf); 2200 2201 /* Release the DMA RX socket buffers later 2202 * to ensure all pending XDP_TX buffers are returned. 2203 */ 2204 free_dma_rx_desc_resources(priv, dma_conf); 2205 } 2206 2207 /** 2208 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2209 * @priv: driver private structure 2210 * Description: It is used for enabling the rx queues in the MAC 2211 */ 2212 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2213 { 2214 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2215 int queue; 2216 u8 mode; 2217 2218 for (queue = 0; queue < rx_queues_count; queue++) { 2219 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2220 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2221 } 2222 } 2223 2224 /** 2225 * stmmac_start_rx_dma - start RX DMA channel 2226 * @priv: driver private structure 2227 * @chan: RX channel index 2228 * Description: 2229 * This starts a RX DMA channel 2230 */ 2231 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2232 { 2233 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2234 stmmac_start_rx(priv, priv->ioaddr, chan); 2235 } 2236 2237 /** 2238 * stmmac_start_tx_dma - start TX DMA channel 2239 * @priv: driver private structure 2240 * @chan: TX channel index 2241 * Description: 2242 * This starts a TX DMA channel 2243 */ 2244 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2245 { 2246 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2247 stmmac_start_tx(priv, priv->ioaddr, chan); 2248 } 2249 2250 /** 2251 * stmmac_stop_rx_dma - stop RX DMA channel 2252 * @priv: driver private structure 2253 * @chan: RX channel index 2254 * Description: 2255 * This stops a RX DMA channel 2256 */ 2257 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2258 { 2259 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2260 stmmac_stop_rx(priv, priv->ioaddr, chan); 2261 } 2262 2263 /** 2264 * stmmac_stop_tx_dma - stop TX DMA channel 2265 * @priv: driver private structure 2266 * @chan: TX channel index 2267 * Description: 2268 * This stops a TX DMA channel 2269 */ 2270 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2271 { 2272 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2273 stmmac_stop_tx(priv, priv->ioaddr, chan); 2274 } 2275 2276 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2277 { 2278 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2279 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2280 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2281 u32 chan; 2282 2283 for (chan = 0; chan < dma_csr_ch; chan++) { 2284 struct stmmac_channel *ch = &priv->channel[chan]; 2285 unsigned long flags; 2286 2287 spin_lock_irqsave(&ch->lock, flags); 2288 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2289 spin_unlock_irqrestore(&ch->lock, flags); 2290 } 2291 } 2292 2293 /** 2294 * stmmac_start_all_dma - start all RX and TX DMA channels 2295 * @priv: driver private structure 2296 * Description: 2297 * This starts all the RX and TX DMA channels 2298 */ 2299 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2300 { 2301 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2302 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2303 u32 chan = 0; 2304 2305 for (chan = 0; chan < rx_channels_count; chan++) 2306 stmmac_start_rx_dma(priv, chan); 2307 2308 for (chan = 0; chan < tx_channels_count; chan++) 2309 stmmac_start_tx_dma(priv, chan); 2310 } 2311 2312 /** 2313 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2314 * @priv: driver private structure 2315 * Description: 2316 * This stops the RX and TX DMA channels 2317 */ 2318 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2319 { 2320 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2321 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2322 u32 chan = 0; 2323 2324 for (chan = 0; chan < rx_channels_count; chan++) 2325 stmmac_stop_rx_dma(priv, chan); 2326 2327 for (chan = 0; chan < tx_channels_count; chan++) 2328 stmmac_stop_tx_dma(priv, chan); 2329 } 2330 2331 /** 2332 * stmmac_dma_operation_mode - HW DMA operation mode 2333 * @priv: driver private structure 2334 * Description: it is used for configuring the DMA operation mode register in 2335 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2336 */ 2337 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2338 { 2339 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2340 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2341 int rxfifosz = priv->plat->rx_fifo_size; 2342 int txfifosz = priv->plat->tx_fifo_size; 2343 u32 txmode = 0; 2344 u32 rxmode = 0; 2345 u32 chan = 0; 2346 u8 qmode = 0; 2347 2348 if (rxfifosz == 0) 2349 rxfifosz = priv->dma_cap.rx_fifo_size; 2350 if (txfifosz == 0) 2351 txfifosz = priv->dma_cap.tx_fifo_size; 2352 2353 /* Adjust for real per queue fifo size */ 2354 rxfifosz /= rx_channels_count; 2355 txfifosz /= tx_channels_count; 2356 2357 if (priv->plat->force_thresh_dma_mode) { 2358 txmode = tc; 2359 rxmode = tc; 2360 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2361 /* 2362 * In case of GMAC, SF mode can be enabled 2363 * to perform the TX COE in HW. This depends on: 2364 * 1) TX COE if actually supported 2365 * 2) There is no bugged Jumbo frame support 2366 * that needs to not insert csum in the TDES. 2367 */ 2368 txmode = SF_DMA_MODE; 2369 rxmode = SF_DMA_MODE; 2370 priv->xstats.threshold = SF_DMA_MODE; 2371 } else { 2372 txmode = tc; 2373 rxmode = SF_DMA_MODE; 2374 } 2375 2376 /* configure all channels */ 2377 for (chan = 0; chan < rx_channels_count; chan++) { 2378 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2379 u32 buf_size; 2380 2381 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2382 2383 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2384 rxfifosz, qmode); 2385 2386 if (rx_q->xsk_pool) { 2387 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2388 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2389 buf_size, 2390 chan); 2391 } else { 2392 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2393 priv->dma_conf.dma_buf_sz, 2394 chan); 2395 } 2396 } 2397 2398 for (chan = 0; chan < tx_channels_count; chan++) { 2399 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2400 2401 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2402 txfifosz, qmode); 2403 } 2404 } 2405 2406 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2407 { 2408 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2409 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2410 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2411 unsigned int entry = tx_q->cur_tx; 2412 struct dma_desc *tx_desc = NULL; 2413 struct xdp_desc xdp_desc; 2414 bool work_done = true; 2415 2416 /* Avoids TX time-out as we are sharing with slow path */ 2417 txq_trans_cond_update(nq); 2418 2419 budget = min(budget, stmmac_tx_avail(priv, queue)); 2420 2421 while (budget-- > 0) { 2422 dma_addr_t dma_addr; 2423 bool set_ic; 2424 2425 /* We are sharing with slow path and stop XSK TX desc submission when 2426 * available TX ring is less than threshold. 2427 */ 2428 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2429 !netif_carrier_ok(priv->dev)) { 2430 work_done = false; 2431 break; 2432 } 2433 2434 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2435 break; 2436 2437 if (likely(priv->extend_desc)) 2438 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2439 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2440 tx_desc = &tx_q->dma_entx[entry].basic; 2441 else 2442 tx_desc = tx_q->dma_tx + entry; 2443 2444 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2445 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2446 2447 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2448 2449 /* To return XDP buffer to XSK pool, we simple call 2450 * xsk_tx_completed(), so we don't need to fill up 2451 * 'buf' and 'xdpf'. 2452 */ 2453 tx_q->tx_skbuff_dma[entry].buf = 0; 2454 tx_q->xdpf[entry] = NULL; 2455 2456 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2457 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2458 tx_q->tx_skbuff_dma[entry].last_segment = true; 2459 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2460 2461 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2462 2463 tx_q->tx_count_frames++; 2464 2465 if (!priv->tx_coal_frames[queue]) 2466 set_ic = false; 2467 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2468 set_ic = true; 2469 else 2470 set_ic = false; 2471 2472 if (set_ic) { 2473 tx_q->tx_count_frames = 0; 2474 stmmac_set_tx_ic(priv, tx_desc); 2475 priv->xstats.tx_set_ic_bit++; 2476 } 2477 2478 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2479 true, priv->mode, true, true, 2480 xdp_desc.len); 2481 2482 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2483 2484 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2485 entry = tx_q->cur_tx; 2486 } 2487 2488 if (tx_desc) { 2489 stmmac_flush_tx_descriptors(priv, queue); 2490 xsk_tx_release(pool); 2491 } 2492 2493 /* Return true if all of the 3 conditions are met 2494 * a) TX Budget is still available 2495 * b) work_done = true when XSK TX desc peek is empty (no more 2496 * pending XSK TX for transmission) 2497 */ 2498 return !!budget && work_done; 2499 } 2500 2501 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2502 { 2503 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2504 tc += 64; 2505 2506 if (priv->plat->force_thresh_dma_mode) 2507 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2508 else 2509 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2510 chan); 2511 2512 priv->xstats.threshold = tc; 2513 } 2514 } 2515 2516 /** 2517 * stmmac_tx_clean - to manage the transmission completion 2518 * @priv: driver private structure 2519 * @budget: napi budget limiting this functions packet handling 2520 * @queue: TX queue index 2521 * Description: it reclaims the transmit resources after transmission completes. 2522 */ 2523 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2524 { 2525 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2526 unsigned int bytes_compl = 0, pkts_compl = 0; 2527 unsigned int entry, xmits = 0, count = 0; 2528 2529 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2530 2531 priv->xstats.tx_clean++; 2532 2533 tx_q->xsk_frames_done = 0; 2534 2535 entry = tx_q->dirty_tx; 2536 2537 /* Try to clean all TX complete frame in 1 shot */ 2538 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2539 struct xdp_frame *xdpf; 2540 struct sk_buff *skb; 2541 struct dma_desc *p; 2542 int status; 2543 2544 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2545 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2546 xdpf = tx_q->xdpf[entry]; 2547 skb = NULL; 2548 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2549 xdpf = NULL; 2550 skb = tx_q->tx_skbuff[entry]; 2551 } else { 2552 xdpf = NULL; 2553 skb = NULL; 2554 } 2555 2556 if (priv->extend_desc) 2557 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2558 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2559 p = &tx_q->dma_entx[entry].basic; 2560 else 2561 p = tx_q->dma_tx + entry; 2562 2563 status = stmmac_tx_status(priv, &priv->dev->stats, 2564 &priv->xstats, p, priv->ioaddr); 2565 /* Check if the descriptor is owned by the DMA */ 2566 if (unlikely(status & tx_dma_own)) 2567 break; 2568 2569 count++; 2570 2571 /* Make sure descriptor fields are read after reading 2572 * the own bit. 2573 */ 2574 dma_rmb(); 2575 2576 /* Just consider the last segment and ...*/ 2577 if (likely(!(status & tx_not_ls))) { 2578 /* ... verify the status error condition */ 2579 if (unlikely(status & tx_err)) { 2580 priv->dev->stats.tx_errors++; 2581 if (unlikely(status & tx_err_bump_tc)) 2582 stmmac_bump_dma_threshold(priv, queue); 2583 } else { 2584 priv->dev->stats.tx_packets++; 2585 priv->xstats.tx_pkt_n++; 2586 priv->xstats.txq_stats[queue].tx_pkt_n++; 2587 } 2588 if (skb) 2589 stmmac_get_tx_hwtstamp(priv, p, skb); 2590 } 2591 2592 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2593 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2594 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2595 dma_unmap_page(priv->device, 2596 tx_q->tx_skbuff_dma[entry].buf, 2597 tx_q->tx_skbuff_dma[entry].len, 2598 DMA_TO_DEVICE); 2599 else 2600 dma_unmap_single(priv->device, 2601 tx_q->tx_skbuff_dma[entry].buf, 2602 tx_q->tx_skbuff_dma[entry].len, 2603 DMA_TO_DEVICE); 2604 tx_q->tx_skbuff_dma[entry].buf = 0; 2605 tx_q->tx_skbuff_dma[entry].len = 0; 2606 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2607 } 2608 2609 stmmac_clean_desc3(priv, tx_q, p); 2610 2611 tx_q->tx_skbuff_dma[entry].last_segment = false; 2612 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2613 2614 if (xdpf && 2615 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2616 xdp_return_frame_rx_napi(xdpf); 2617 tx_q->xdpf[entry] = NULL; 2618 } 2619 2620 if (xdpf && 2621 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2622 xdp_return_frame(xdpf); 2623 tx_q->xdpf[entry] = NULL; 2624 } 2625 2626 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2627 tx_q->xsk_frames_done++; 2628 2629 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2630 if (likely(skb)) { 2631 pkts_compl++; 2632 bytes_compl += skb->len; 2633 dev_consume_skb_any(skb); 2634 tx_q->tx_skbuff[entry] = NULL; 2635 } 2636 } 2637 2638 stmmac_release_tx_desc(priv, p, priv->mode); 2639 2640 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2641 } 2642 tx_q->dirty_tx = entry; 2643 2644 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2645 pkts_compl, bytes_compl); 2646 2647 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2648 queue))) && 2649 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2650 2651 netif_dbg(priv, tx_done, priv->dev, 2652 "%s: restart transmit\n", __func__); 2653 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2654 } 2655 2656 if (tx_q->xsk_pool) { 2657 bool work_done; 2658 2659 if (tx_q->xsk_frames_done) 2660 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2661 2662 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2663 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2664 2665 /* For XSK TX, we try to send as many as possible. 2666 * If XSK work done (XSK TX desc empty and budget still 2667 * available), return "budget - 1" to reenable TX IRQ. 2668 * Else, return "budget" to make NAPI continue polling. 2669 */ 2670 work_done = stmmac_xdp_xmit_zc(priv, queue, 2671 STMMAC_XSK_TX_BUDGET_MAX); 2672 if (work_done) 2673 xmits = budget - 1; 2674 else 2675 xmits = budget; 2676 } 2677 2678 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2679 priv->eee_sw_timer_en) { 2680 if (stmmac_enable_eee_mode(priv)) 2681 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2682 } 2683 2684 /* We still have pending packets, let's call for a new scheduling */ 2685 if (tx_q->dirty_tx != tx_q->cur_tx) 2686 hrtimer_start(&tx_q->txtimer, 2687 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2688 HRTIMER_MODE_REL); 2689 2690 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2691 2692 /* Combine decisions from TX clean and XSK TX */ 2693 return max(count, xmits); 2694 } 2695 2696 /** 2697 * stmmac_tx_err - to manage the tx error 2698 * @priv: driver private structure 2699 * @chan: channel index 2700 * Description: it cleans the descriptors and restarts the transmission 2701 * in case of transmission errors. 2702 */ 2703 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2704 { 2705 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2706 2707 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2708 2709 stmmac_stop_tx_dma(priv, chan); 2710 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2711 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2712 stmmac_reset_tx_queue(priv, chan); 2713 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2714 tx_q->dma_tx_phy, chan); 2715 stmmac_start_tx_dma(priv, chan); 2716 2717 priv->dev->stats.tx_errors++; 2718 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2719 } 2720 2721 /** 2722 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2723 * @priv: driver private structure 2724 * @txmode: TX operating mode 2725 * @rxmode: RX operating mode 2726 * @chan: channel index 2727 * Description: it is used for configuring of the DMA operation mode in 2728 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2729 * mode. 2730 */ 2731 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2732 u32 rxmode, u32 chan) 2733 { 2734 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2735 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2736 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2737 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2738 int rxfifosz = priv->plat->rx_fifo_size; 2739 int txfifosz = priv->plat->tx_fifo_size; 2740 2741 if (rxfifosz == 0) 2742 rxfifosz = priv->dma_cap.rx_fifo_size; 2743 if (txfifosz == 0) 2744 txfifosz = priv->dma_cap.tx_fifo_size; 2745 2746 /* Adjust for real per queue fifo size */ 2747 rxfifosz /= rx_channels_count; 2748 txfifosz /= tx_channels_count; 2749 2750 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2751 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2752 } 2753 2754 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2755 { 2756 int ret; 2757 2758 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2759 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2760 if (ret && (ret != -EINVAL)) { 2761 stmmac_global_err(priv); 2762 return true; 2763 } 2764 2765 return false; 2766 } 2767 2768 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2769 { 2770 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2771 &priv->xstats, chan, dir); 2772 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2773 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2774 struct stmmac_channel *ch = &priv->channel[chan]; 2775 struct napi_struct *rx_napi; 2776 struct napi_struct *tx_napi; 2777 unsigned long flags; 2778 2779 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2780 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2781 2782 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2783 if (napi_schedule_prep(rx_napi)) { 2784 spin_lock_irqsave(&ch->lock, flags); 2785 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2786 spin_unlock_irqrestore(&ch->lock, flags); 2787 __napi_schedule(rx_napi); 2788 } 2789 } 2790 2791 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2792 if (napi_schedule_prep(tx_napi)) { 2793 spin_lock_irqsave(&ch->lock, flags); 2794 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2795 spin_unlock_irqrestore(&ch->lock, flags); 2796 __napi_schedule(tx_napi); 2797 } 2798 } 2799 2800 return status; 2801 } 2802 2803 /** 2804 * stmmac_dma_interrupt - DMA ISR 2805 * @priv: driver private structure 2806 * Description: this is the DMA ISR. It is called by the main ISR. 2807 * It calls the dwmac dma routine and schedule poll method in case of some 2808 * work can be done. 2809 */ 2810 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2811 { 2812 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2813 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2814 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2815 tx_channel_count : rx_channel_count; 2816 u32 chan; 2817 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2818 2819 /* Make sure we never check beyond our status buffer. */ 2820 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2821 channels_to_check = ARRAY_SIZE(status); 2822 2823 for (chan = 0; chan < channels_to_check; chan++) 2824 status[chan] = stmmac_napi_check(priv, chan, 2825 DMA_DIR_RXTX); 2826 2827 for (chan = 0; chan < tx_channel_count; chan++) { 2828 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2829 /* Try to bump up the dma threshold on this failure */ 2830 stmmac_bump_dma_threshold(priv, chan); 2831 } else if (unlikely(status[chan] == tx_hard_error)) { 2832 stmmac_tx_err(priv, chan); 2833 } 2834 } 2835 } 2836 2837 /** 2838 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2839 * @priv: driver private structure 2840 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2841 */ 2842 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2843 { 2844 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2845 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2846 2847 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2848 2849 if (priv->dma_cap.rmon) { 2850 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2851 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2852 } else 2853 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2854 } 2855 2856 /** 2857 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2858 * @priv: driver private structure 2859 * Description: 2860 * new GMAC chip generations have a new register to indicate the 2861 * presence of the optional feature/functions. 2862 * This can be also used to override the value passed through the 2863 * platform and necessary for old MAC10/100 and GMAC chips. 2864 */ 2865 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2866 { 2867 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2868 } 2869 2870 /** 2871 * stmmac_check_ether_addr - check if the MAC addr is valid 2872 * @priv: driver private structure 2873 * Description: 2874 * it is to verify if the MAC address is valid, in case of failures it 2875 * generates a random MAC address 2876 */ 2877 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2878 { 2879 u8 addr[ETH_ALEN]; 2880 2881 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2882 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2883 if (is_valid_ether_addr(addr)) 2884 eth_hw_addr_set(priv->dev, addr); 2885 else 2886 eth_hw_addr_random(priv->dev); 2887 dev_info(priv->device, "device MAC address %pM\n", 2888 priv->dev->dev_addr); 2889 } 2890 } 2891 2892 /** 2893 * stmmac_init_dma_engine - DMA init. 2894 * @priv: driver private structure 2895 * Description: 2896 * It inits the DMA invoking the specific MAC/GMAC callback. 2897 * Some DMA parameters can be passed from the platform; 2898 * in case of these are not passed a default is kept for the MAC or GMAC. 2899 */ 2900 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2901 { 2902 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2903 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2904 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2905 struct stmmac_rx_queue *rx_q; 2906 struct stmmac_tx_queue *tx_q; 2907 u32 chan = 0; 2908 int atds = 0; 2909 int ret = 0; 2910 2911 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2912 dev_err(priv->device, "Invalid DMA configuration\n"); 2913 return -EINVAL; 2914 } 2915 2916 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2917 atds = 1; 2918 2919 ret = stmmac_reset(priv, priv->ioaddr); 2920 if (ret) { 2921 dev_err(priv->device, "Failed to reset the dma\n"); 2922 return ret; 2923 } 2924 2925 /* DMA Configuration */ 2926 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2927 2928 if (priv->plat->axi) 2929 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2930 2931 /* DMA CSR Channel configuration */ 2932 for (chan = 0; chan < dma_csr_ch; chan++) { 2933 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2934 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2935 } 2936 2937 /* DMA RX Channel Configuration */ 2938 for (chan = 0; chan < rx_channels_count; chan++) { 2939 rx_q = &priv->dma_conf.rx_queue[chan]; 2940 2941 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2942 rx_q->dma_rx_phy, chan); 2943 2944 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2945 (rx_q->buf_alloc_num * 2946 sizeof(struct dma_desc)); 2947 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2948 rx_q->rx_tail_addr, chan); 2949 } 2950 2951 /* DMA TX Channel Configuration */ 2952 for (chan = 0; chan < tx_channels_count; chan++) { 2953 tx_q = &priv->dma_conf.tx_queue[chan]; 2954 2955 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2956 tx_q->dma_tx_phy, chan); 2957 2958 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2959 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2960 tx_q->tx_tail_addr, chan); 2961 } 2962 2963 return ret; 2964 } 2965 2966 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2967 { 2968 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2969 2970 hrtimer_start(&tx_q->txtimer, 2971 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2972 HRTIMER_MODE_REL); 2973 } 2974 2975 /** 2976 * stmmac_tx_timer - mitigation sw timer for tx. 2977 * @t: data pointer 2978 * Description: 2979 * This is the timer handler to directly invoke the stmmac_tx_clean. 2980 */ 2981 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2982 { 2983 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2984 struct stmmac_priv *priv = tx_q->priv_data; 2985 struct stmmac_channel *ch; 2986 struct napi_struct *napi; 2987 2988 ch = &priv->channel[tx_q->queue_index]; 2989 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2990 2991 if (likely(napi_schedule_prep(napi))) { 2992 unsigned long flags; 2993 2994 spin_lock_irqsave(&ch->lock, flags); 2995 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2996 spin_unlock_irqrestore(&ch->lock, flags); 2997 __napi_schedule(napi); 2998 } 2999 3000 return HRTIMER_NORESTART; 3001 } 3002 3003 /** 3004 * stmmac_init_coalesce - init mitigation options. 3005 * @priv: driver private structure 3006 * Description: 3007 * This inits the coalesce parameters: i.e. timer rate, 3008 * timer handler and default threshold used for enabling the 3009 * interrupt on completion bit. 3010 */ 3011 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3012 { 3013 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3014 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3015 u32 chan; 3016 3017 for (chan = 0; chan < tx_channel_count; chan++) { 3018 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3019 3020 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3021 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3022 3023 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3024 tx_q->txtimer.function = stmmac_tx_timer; 3025 } 3026 3027 for (chan = 0; chan < rx_channel_count; chan++) 3028 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3029 } 3030 3031 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3032 { 3033 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3034 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3035 u32 chan; 3036 3037 /* set TX ring length */ 3038 for (chan = 0; chan < tx_channels_count; chan++) 3039 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3040 (priv->dma_conf.dma_tx_size - 1), chan); 3041 3042 /* set RX ring length */ 3043 for (chan = 0; chan < rx_channels_count; chan++) 3044 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3045 (priv->dma_conf.dma_rx_size - 1), chan); 3046 } 3047 3048 /** 3049 * stmmac_set_tx_queue_weight - Set TX queue weight 3050 * @priv: driver private structure 3051 * Description: It is used for setting TX queues weight 3052 */ 3053 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3054 { 3055 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3056 u32 weight; 3057 u32 queue; 3058 3059 for (queue = 0; queue < tx_queues_count; queue++) { 3060 weight = priv->plat->tx_queues_cfg[queue].weight; 3061 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3062 } 3063 } 3064 3065 /** 3066 * stmmac_configure_cbs - Configure CBS in TX queue 3067 * @priv: driver private structure 3068 * Description: It is used for configuring CBS in AVB TX queues 3069 */ 3070 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3071 { 3072 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3073 u32 mode_to_use; 3074 u32 queue; 3075 3076 /* queue 0 is reserved for legacy traffic */ 3077 for (queue = 1; queue < tx_queues_count; queue++) { 3078 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3079 if (mode_to_use == MTL_QUEUE_DCB) 3080 continue; 3081 3082 stmmac_config_cbs(priv, priv->hw, 3083 priv->plat->tx_queues_cfg[queue].send_slope, 3084 priv->plat->tx_queues_cfg[queue].idle_slope, 3085 priv->plat->tx_queues_cfg[queue].high_credit, 3086 priv->plat->tx_queues_cfg[queue].low_credit, 3087 queue); 3088 } 3089 } 3090 3091 /** 3092 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3093 * @priv: driver private structure 3094 * Description: It is used for mapping RX queues to RX dma channels 3095 */ 3096 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3097 { 3098 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3099 u32 queue; 3100 u32 chan; 3101 3102 for (queue = 0; queue < rx_queues_count; queue++) { 3103 chan = priv->plat->rx_queues_cfg[queue].chan; 3104 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3105 } 3106 } 3107 3108 /** 3109 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3110 * @priv: driver private structure 3111 * Description: It is used for configuring the RX Queue Priority 3112 */ 3113 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3114 { 3115 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3116 u32 queue; 3117 u32 prio; 3118 3119 for (queue = 0; queue < rx_queues_count; queue++) { 3120 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3121 continue; 3122 3123 prio = priv->plat->rx_queues_cfg[queue].prio; 3124 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3125 } 3126 } 3127 3128 /** 3129 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3130 * @priv: driver private structure 3131 * Description: It is used for configuring the TX Queue Priority 3132 */ 3133 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3134 { 3135 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3136 u32 queue; 3137 u32 prio; 3138 3139 for (queue = 0; queue < tx_queues_count; queue++) { 3140 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3141 continue; 3142 3143 prio = priv->plat->tx_queues_cfg[queue].prio; 3144 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3145 } 3146 } 3147 3148 /** 3149 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3150 * @priv: driver private structure 3151 * Description: It is used for configuring the RX queue routing 3152 */ 3153 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3154 { 3155 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3156 u32 queue; 3157 u8 packet; 3158 3159 for (queue = 0; queue < rx_queues_count; queue++) { 3160 /* no specific packet type routing specified for the queue */ 3161 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3162 continue; 3163 3164 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3165 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3166 } 3167 } 3168 3169 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3170 { 3171 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3172 priv->rss.enable = false; 3173 return; 3174 } 3175 3176 if (priv->dev->features & NETIF_F_RXHASH) 3177 priv->rss.enable = true; 3178 else 3179 priv->rss.enable = false; 3180 3181 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3182 priv->plat->rx_queues_to_use); 3183 } 3184 3185 /** 3186 * stmmac_mtl_configuration - Configure MTL 3187 * @priv: driver private structure 3188 * Description: It is used for configurring MTL 3189 */ 3190 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3191 { 3192 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3193 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3194 3195 if (tx_queues_count > 1) 3196 stmmac_set_tx_queue_weight(priv); 3197 3198 /* Configure MTL RX algorithms */ 3199 if (rx_queues_count > 1) 3200 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3201 priv->plat->rx_sched_algorithm); 3202 3203 /* Configure MTL TX algorithms */ 3204 if (tx_queues_count > 1) 3205 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3206 priv->plat->tx_sched_algorithm); 3207 3208 /* Configure CBS in AVB TX queues */ 3209 if (tx_queues_count > 1) 3210 stmmac_configure_cbs(priv); 3211 3212 /* Map RX MTL to DMA channels */ 3213 stmmac_rx_queue_dma_chan_map(priv); 3214 3215 /* Enable MAC RX Queues */ 3216 stmmac_mac_enable_rx_queues(priv); 3217 3218 /* Set RX priorities */ 3219 if (rx_queues_count > 1) 3220 stmmac_mac_config_rx_queues_prio(priv); 3221 3222 /* Set TX priorities */ 3223 if (tx_queues_count > 1) 3224 stmmac_mac_config_tx_queues_prio(priv); 3225 3226 /* Set RX routing */ 3227 if (rx_queues_count > 1) 3228 stmmac_mac_config_rx_queues_routing(priv); 3229 3230 /* Receive Side Scaling */ 3231 if (rx_queues_count > 1) 3232 stmmac_mac_config_rss(priv); 3233 } 3234 3235 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3236 { 3237 if (priv->dma_cap.asp) { 3238 netdev_info(priv->dev, "Enabling Safety Features\n"); 3239 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3240 priv->plat->safety_feat_cfg); 3241 } else { 3242 netdev_info(priv->dev, "No Safety Features support found\n"); 3243 } 3244 } 3245 3246 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3247 { 3248 char *name; 3249 3250 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3251 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3252 3253 name = priv->wq_name; 3254 sprintf(name, "%s-fpe", priv->dev->name); 3255 3256 priv->fpe_wq = create_singlethread_workqueue(name); 3257 if (!priv->fpe_wq) { 3258 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3259 3260 return -ENOMEM; 3261 } 3262 netdev_info(priv->dev, "FPE workqueue start"); 3263 3264 return 0; 3265 } 3266 3267 /** 3268 * stmmac_hw_setup - setup mac in a usable state. 3269 * @dev : pointer to the device structure. 3270 * @ptp_register: register PTP if set 3271 * Description: 3272 * this is the main function to setup the HW in a usable state because the 3273 * dma engine is reset, the core registers are configured (e.g. AXI, 3274 * Checksum features, timers). The DMA is ready to start receiving and 3275 * transmitting. 3276 * Return value: 3277 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3278 * file on failure. 3279 */ 3280 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3281 { 3282 struct stmmac_priv *priv = netdev_priv(dev); 3283 u32 rx_cnt = priv->plat->rx_queues_to_use; 3284 u32 tx_cnt = priv->plat->tx_queues_to_use; 3285 bool sph_en; 3286 u32 chan; 3287 int ret; 3288 3289 /* DMA initialization and SW reset */ 3290 ret = stmmac_init_dma_engine(priv); 3291 if (ret < 0) { 3292 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3293 __func__); 3294 return ret; 3295 } 3296 3297 /* Copy the MAC addr into the HW */ 3298 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3299 3300 /* PS and related bits will be programmed according to the speed */ 3301 if (priv->hw->pcs) { 3302 int speed = priv->plat->mac_port_sel_speed; 3303 3304 if ((speed == SPEED_10) || (speed == SPEED_100) || 3305 (speed == SPEED_1000)) { 3306 priv->hw->ps = speed; 3307 } else { 3308 dev_warn(priv->device, "invalid port speed\n"); 3309 priv->hw->ps = 0; 3310 } 3311 } 3312 3313 /* Initialize the MAC Core */ 3314 stmmac_core_init(priv, priv->hw, dev); 3315 3316 /* Initialize MTL*/ 3317 stmmac_mtl_configuration(priv); 3318 3319 /* Initialize Safety Features */ 3320 stmmac_safety_feat_configuration(priv); 3321 3322 ret = stmmac_rx_ipc(priv, priv->hw); 3323 if (!ret) { 3324 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3325 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3326 priv->hw->rx_csum = 0; 3327 } 3328 3329 /* Enable the MAC Rx/Tx */ 3330 stmmac_mac_set(priv, priv->ioaddr, true); 3331 3332 /* Set the HW DMA mode and the COE */ 3333 stmmac_dma_operation_mode(priv); 3334 3335 stmmac_mmc_setup(priv); 3336 3337 if (ptp_register) { 3338 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3339 if (ret < 0) 3340 netdev_warn(priv->dev, 3341 "failed to enable PTP reference clock: %pe\n", 3342 ERR_PTR(ret)); 3343 } 3344 3345 ret = stmmac_init_ptp(priv); 3346 if (ret == -EOPNOTSUPP) 3347 netdev_info(priv->dev, "PTP not supported by HW\n"); 3348 else if (ret) 3349 netdev_warn(priv->dev, "PTP init failed\n"); 3350 else if (ptp_register) 3351 stmmac_ptp_register(priv); 3352 3353 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3354 3355 /* Convert the timer from msec to usec */ 3356 if (!priv->tx_lpi_timer) 3357 priv->tx_lpi_timer = eee_timer * 1000; 3358 3359 if (priv->use_riwt) { 3360 u32 queue; 3361 3362 for (queue = 0; queue < rx_cnt; queue++) { 3363 if (!priv->rx_riwt[queue]) 3364 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3365 3366 stmmac_rx_watchdog(priv, priv->ioaddr, 3367 priv->rx_riwt[queue], queue); 3368 } 3369 } 3370 3371 if (priv->hw->pcs) 3372 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3373 3374 /* set TX and RX rings length */ 3375 stmmac_set_rings_length(priv); 3376 3377 /* Enable TSO */ 3378 if (priv->tso) { 3379 for (chan = 0; chan < tx_cnt; chan++) { 3380 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3381 3382 /* TSO and TBS cannot co-exist */ 3383 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3384 continue; 3385 3386 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3387 } 3388 } 3389 3390 /* Enable Split Header */ 3391 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3392 for (chan = 0; chan < rx_cnt; chan++) 3393 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3394 3395 3396 /* VLAN Tag Insertion */ 3397 if (priv->dma_cap.vlins) 3398 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3399 3400 /* TBS */ 3401 for (chan = 0; chan < tx_cnt; chan++) { 3402 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3403 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3404 3405 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3406 } 3407 3408 /* Configure real RX and TX queues */ 3409 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3410 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3411 3412 /* Start the ball rolling... */ 3413 stmmac_start_all_dma(priv); 3414 3415 if (priv->dma_cap.fpesel) { 3416 stmmac_fpe_start_wq(priv); 3417 3418 if (priv->plat->fpe_cfg->enable) 3419 stmmac_fpe_handshake(priv, true); 3420 } 3421 3422 return 0; 3423 } 3424 3425 static void stmmac_hw_teardown(struct net_device *dev) 3426 { 3427 struct stmmac_priv *priv = netdev_priv(dev); 3428 3429 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3430 } 3431 3432 static void stmmac_free_irq(struct net_device *dev, 3433 enum request_irq_err irq_err, int irq_idx) 3434 { 3435 struct stmmac_priv *priv = netdev_priv(dev); 3436 int j; 3437 3438 switch (irq_err) { 3439 case REQ_IRQ_ERR_ALL: 3440 irq_idx = priv->plat->tx_queues_to_use; 3441 fallthrough; 3442 case REQ_IRQ_ERR_TX: 3443 for (j = irq_idx - 1; j >= 0; j--) { 3444 if (priv->tx_irq[j] > 0) { 3445 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3446 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3447 } 3448 } 3449 irq_idx = priv->plat->rx_queues_to_use; 3450 fallthrough; 3451 case REQ_IRQ_ERR_RX: 3452 for (j = irq_idx - 1; j >= 0; j--) { 3453 if (priv->rx_irq[j] > 0) { 3454 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3455 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3456 } 3457 } 3458 3459 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3460 free_irq(priv->sfty_ue_irq, dev); 3461 fallthrough; 3462 case REQ_IRQ_ERR_SFTY_UE: 3463 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3464 free_irq(priv->sfty_ce_irq, dev); 3465 fallthrough; 3466 case REQ_IRQ_ERR_SFTY_CE: 3467 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3468 free_irq(priv->lpi_irq, dev); 3469 fallthrough; 3470 case REQ_IRQ_ERR_LPI: 3471 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3472 free_irq(priv->wol_irq, dev); 3473 fallthrough; 3474 case REQ_IRQ_ERR_WOL: 3475 free_irq(dev->irq, dev); 3476 fallthrough; 3477 case REQ_IRQ_ERR_MAC: 3478 case REQ_IRQ_ERR_NO: 3479 /* If MAC IRQ request error, no more IRQ to free */ 3480 break; 3481 } 3482 } 3483 3484 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3485 { 3486 struct stmmac_priv *priv = netdev_priv(dev); 3487 enum request_irq_err irq_err; 3488 cpumask_t cpu_mask; 3489 int irq_idx = 0; 3490 char *int_name; 3491 int ret; 3492 int i; 3493 3494 /* For common interrupt */ 3495 int_name = priv->int_name_mac; 3496 sprintf(int_name, "%s:%s", dev->name, "mac"); 3497 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3498 0, int_name, dev); 3499 if (unlikely(ret < 0)) { 3500 netdev_err(priv->dev, 3501 "%s: alloc mac MSI %d (error: %d)\n", 3502 __func__, dev->irq, ret); 3503 irq_err = REQ_IRQ_ERR_MAC; 3504 goto irq_error; 3505 } 3506 3507 /* Request the Wake IRQ in case of another line 3508 * is used for WoL 3509 */ 3510 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3511 int_name = priv->int_name_wol; 3512 sprintf(int_name, "%s:%s", dev->name, "wol"); 3513 ret = request_irq(priv->wol_irq, 3514 stmmac_mac_interrupt, 3515 0, int_name, dev); 3516 if (unlikely(ret < 0)) { 3517 netdev_err(priv->dev, 3518 "%s: alloc wol MSI %d (error: %d)\n", 3519 __func__, priv->wol_irq, ret); 3520 irq_err = REQ_IRQ_ERR_WOL; 3521 goto irq_error; 3522 } 3523 } 3524 3525 /* Request the LPI IRQ in case of another line 3526 * is used for LPI 3527 */ 3528 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3529 int_name = priv->int_name_lpi; 3530 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3531 ret = request_irq(priv->lpi_irq, 3532 stmmac_mac_interrupt, 3533 0, int_name, dev); 3534 if (unlikely(ret < 0)) { 3535 netdev_err(priv->dev, 3536 "%s: alloc lpi MSI %d (error: %d)\n", 3537 __func__, priv->lpi_irq, ret); 3538 irq_err = REQ_IRQ_ERR_LPI; 3539 goto irq_error; 3540 } 3541 } 3542 3543 /* Request the Safety Feature Correctible Error line in 3544 * case of another line is used 3545 */ 3546 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3547 int_name = priv->int_name_sfty_ce; 3548 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3549 ret = request_irq(priv->sfty_ce_irq, 3550 stmmac_safety_interrupt, 3551 0, int_name, dev); 3552 if (unlikely(ret < 0)) { 3553 netdev_err(priv->dev, 3554 "%s: alloc sfty ce MSI %d (error: %d)\n", 3555 __func__, priv->sfty_ce_irq, ret); 3556 irq_err = REQ_IRQ_ERR_SFTY_CE; 3557 goto irq_error; 3558 } 3559 } 3560 3561 /* Request the Safety Feature Uncorrectible Error line in 3562 * case of another line is used 3563 */ 3564 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3565 int_name = priv->int_name_sfty_ue; 3566 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3567 ret = request_irq(priv->sfty_ue_irq, 3568 stmmac_safety_interrupt, 3569 0, int_name, dev); 3570 if (unlikely(ret < 0)) { 3571 netdev_err(priv->dev, 3572 "%s: alloc sfty ue MSI %d (error: %d)\n", 3573 __func__, priv->sfty_ue_irq, ret); 3574 irq_err = REQ_IRQ_ERR_SFTY_UE; 3575 goto irq_error; 3576 } 3577 } 3578 3579 /* Request Rx MSI irq */ 3580 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3581 if (i >= MTL_MAX_RX_QUEUES) 3582 break; 3583 if (priv->rx_irq[i] == 0) 3584 continue; 3585 3586 int_name = priv->int_name_rx_irq[i]; 3587 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3588 ret = request_irq(priv->rx_irq[i], 3589 stmmac_msi_intr_rx, 3590 0, int_name, &priv->dma_conf.rx_queue[i]); 3591 if (unlikely(ret < 0)) { 3592 netdev_err(priv->dev, 3593 "%s: alloc rx-%d MSI %d (error: %d)\n", 3594 __func__, i, priv->rx_irq[i], ret); 3595 irq_err = REQ_IRQ_ERR_RX; 3596 irq_idx = i; 3597 goto irq_error; 3598 } 3599 cpumask_clear(&cpu_mask); 3600 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3601 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3602 } 3603 3604 /* Request Tx MSI irq */ 3605 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3606 if (i >= MTL_MAX_TX_QUEUES) 3607 break; 3608 if (priv->tx_irq[i] == 0) 3609 continue; 3610 3611 int_name = priv->int_name_tx_irq[i]; 3612 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3613 ret = request_irq(priv->tx_irq[i], 3614 stmmac_msi_intr_tx, 3615 0, int_name, &priv->dma_conf.tx_queue[i]); 3616 if (unlikely(ret < 0)) { 3617 netdev_err(priv->dev, 3618 "%s: alloc tx-%d MSI %d (error: %d)\n", 3619 __func__, i, priv->tx_irq[i], ret); 3620 irq_err = REQ_IRQ_ERR_TX; 3621 irq_idx = i; 3622 goto irq_error; 3623 } 3624 cpumask_clear(&cpu_mask); 3625 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3626 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3627 } 3628 3629 return 0; 3630 3631 irq_error: 3632 stmmac_free_irq(dev, irq_err, irq_idx); 3633 return ret; 3634 } 3635 3636 static int stmmac_request_irq_single(struct net_device *dev) 3637 { 3638 struct stmmac_priv *priv = netdev_priv(dev); 3639 enum request_irq_err irq_err; 3640 int ret; 3641 3642 ret = request_irq(dev->irq, stmmac_interrupt, 3643 IRQF_SHARED, dev->name, dev); 3644 if (unlikely(ret < 0)) { 3645 netdev_err(priv->dev, 3646 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3647 __func__, dev->irq, ret); 3648 irq_err = REQ_IRQ_ERR_MAC; 3649 goto irq_error; 3650 } 3651 3652 /* Request the Wake IRQ in case of another line 3653 * is used for WoL 3654 */ 3655 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3656 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3657 IRQF_SHARED, dev->name, dev); 3658 if (unlikely(ret < 0)) { 3659 netdev_err(priv->dev, 3660 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3661 __func__, priv->wol_irq, ret); 3662 irq_err = REQ_IRQ_ERR_WOL; 3663 goto irq_error; 3664 } 3665 } 3666 3667 /* Request the IRQ lines */ 3668 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3669 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3670 IRQF_SHARED, dev->name, dev); 3671 if (unlikely(ret < 0)) { 3672 netdev_err(priv->dev, 3673 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3674 __func__, priv->lpi_irq, ret); 3675 irq_err = REQ_IRQ_ERR_LPI; 3676 goto irq_error; 3677 } 3678 } 3679 3680 return 0; 3681 3682 irq_error: 3683 stmmac_free_irq(dev, irq_err, 0); 3684 return ret; 3685 } 3686 3687 static int stmmac_request_irq(struct net_device *dev) 3688 { 3689 struct stmmac_priv *priv = netdev_priv(dev); 3690 int ret; 3691 3692 /* Request the IRQ lines */ 3693 if (priv->plat->multi_msi_en) 3694 ret = stmmac_request_irq_multi_msi(dev); 3695 else 3696 ret = stmmac_request_irq_single(dev); 3697 3698 return ret; 3699 } 3700 3701 /** 3702 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3703 * @priv: driver private structure 3704 * @mtu: MTU to setup the dma queue and buf with 3705 * Description: Allocate and generate a dma_conf based on the provided MTU. 3706 * Allocate the Tx/Rx DMA queue and init them. 3707 * Return value: 3708 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3709 */ 3710 static struct stmmac_dma_conf * 3711 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3712 { 3713 struct stmmac_dma_conf *dma_conf; 3714 int chan, bfsize, ret; 3715 3716 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3717 if (!dma_conf) { 3718 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3719 __func__); 3720 return ERR_PTR(-ENOMEM); 3721 } 3722 3723 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3724 if (bfsize < 0) 3725 bfsize = 0; 3726 3727 if (bfsize < BUF_SIZE_16KiB) 3728 bfsize = stmmac_set_bfsize(mtu, 0); 3729 3730 dma_conf->dma_buf_sz = bfsize; 3731 /* Chose the tx/rx size from the already defined one in the 3732 * priv struct. (if defined) 3733 */ 3734 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3735 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3736 3737 if (!dma_conf->dma_tx_size) 3738 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3739 if (!dma_conf->dma_rx_size) 3740 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3741 3742 /* Earlier check for TBS */ 3743 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3744 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3745 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3746 3747 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3748 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3749 } 3750 3751 ret = alloc_dma_desc_resources(priv, dma_conf); 3752 if (ret < 0) { 3753 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3754 __func__); 3755 goto alloc_error; 3756 } 3757 3758 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3759 if (ret < 0) { 3760 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3761 __func__); 3762 goto init_error; 3763 } 3764 3765 return dma_conf; 3766 3767 init_error: 3768 free_dma_desc_resources(priv, dma_conf); 3769 alloc_error: 3770 kfree(dma_conf); 3771 return ERR_PTR(ret); 3772 } 3773 3774 /** 3775 * __stmmac_open - open entry point of the driver 3776 * @dev : pointer to the device structure. 3777 * @dma_conf : structure to take the dma data 3778 * Description: 3779 * This function is the open entry point of the driver. 3780 * Return value: 3781 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3782 * file on failure. 3783 */ 3784 static int __stmmac_open(struct net_device *dev, 3785 struct stmmac_dma_conf *dma_conf) 3786 { 3787 struct stmmac_priv *priv = netdev_priv(dev); 3788 int mode = priv->plat->phy_interface; 3789 u32 chan; 3790 int ret; 3791 3792 ret = pm_runtime_resume_and_get(priv->device); 3793 if (ret < 0) 3794 return ret; 3795 3796 if (priv->hw->pcs != STMMAC_PCS_TBI && 3797 priv->hw->pcs != STMMAC_PCS_RTBI && 3798 (!priv->hw->xpcs || 3799 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3800 ret = stmmac_init_phy(dev); 3801 if (ret) { 3802 netdev_err(priv->dev, 3803 "%s: Cannot attach to PHY (error: %d)\n", 3804 __func__, ret); 3805 goto init_phy_error; 3806 } 3807 } 3808 3809 /* Extra statistics */ 3810 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3811 priv->xstats.threshold = tc; 3812 3813 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3814 3815 buf_sz = dma_conf->dma_buf_sz; 3816 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3817 3818 stmmac_reset_queues_param(priv); 3819 3820 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 3821 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3822 if (ret < 0) { 3823 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3824 __func__); 3825 goto init_error; 3826 } 3827 } 3828 3829 ret = stmmac_hw_setup(dev, true); 3830 if (ret < 0) { 3831 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3832 goto init_error; 3833 } 3834 3835 stmmac_init_coalesce(priv); 3836 3837 phylink_start(priv->phylink); 3838 /* We may have called phylink_speed_down before */ 3839 phylink_speed_up(priv->phylink); 3840 3841 ret = stmmac_request_irq(dev); 3842 if (ret) 3843 goto irq_error; 3844 3845 stmmac_enable_all_queues(priv); 3846 netif_tx_start_all_queues(priv->dev); 3847 stmmac_enable_all_dma_irq(priv); 3848 3849 return 0; 3850 3851 irq_error: 3852 phylink_stop(priv->phylink); 3853 3854 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3855 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3856 3857 stmmac_hw_teardown(dev); 3858 init_error: 3859 free_dma_desc_resources(priv, &priv->dma_conf); 3860 phylink_disconnect_phy(priv->phylink); 3861 init_phy_error: 3862 pm_runtime_put(priv->device); 3863 return ret; 3864 } 3865 3866 static int stmmac_open(struct net_device *dev) 3867 { 3868 struct stmmac_priv *priv = netdev_priv(dev); 3869 struct stmmac_dma_conf *dma_conf; 3870 int ret; 3871 3872 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3873 if (IS_ERR(dma_conf)) 3874 return PTR_ERR(dma_conf); 3875 3876 ret = __stmmac_open(dev, dma_conf); 3877 kfree(dma_conf); 3878 return ret; 3879 } 3880 3881 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3882 { 3883 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3884 3885 if (priv->fpe_wq) 3886 destroy_workqueue(priv->fpe_wq); 3887 3888 netdev_info(priv->dev, "FPE workqueue stop"); 3889 } 3890 3891 /** 3892 * stmmac_release - close entry point of the driver 3893 * @dev : device pointer. 3894 * Description: 3895 * This is the stop entry point of the driver. 3896 */ 3897 static int stmmac_release(struct net_device *dev) 3898 { 3899 struct stmmac_priv *priv = netdev_priv(dev); 3900 u32 chan; 3901 3902 if (device_may_wakeup(priv->device)) 3903 phylink_speed_down(priv->phylink, false); 3904 /* Stop and disconnect the PHY */ 3905 phylink_stop(priv->phylink); 3906 phylink_disconnect_phy(priv->phylink); 3907 3908 stmmac_disable_all_queues(priv); 3909 3910 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3911 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3912 3913 netif_tx_disable(dev); 3914 3915 /* Free the IRQ lines */ 3916 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3917 3918 if (priv->eee_enabled) { 3919 priv->tx_path_in_lpi_mode = false; 3920 del_timer_sync(&priv->eee_ctrl_timer); 3921 } 3922 3923 /* Stop TX/RX DMA and clear the descriptors */ 3924 stmmac_stop_all_dma(priv); 3925 3926 /* Release and free the Rx/Tx resources */ 3927 free_dma_desc_resources(priv, &priv->dma_conf); 3928 3929 /* Disable the MAC Rx/Tx */ 3930 stmmac_mac_set(priv, priv->ioaddr, false); 3931 3932 /* Powerdown Serdes if there is */ 3933 if (priv->plat->serdes_powerdown) 3934 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3935 3936 netif_carrier_off(dev); 3937 3938 stmmac_release_ptp(priv); 3939 3940 pm_runtime_put(priv->device); 3941 3942 if (priv->dma_cap.fpesel) 3943 stmmac_fpe_stop_wq(priv); 3944 3945 return 0; 3946 } 3947 3948 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3949 struct stmmac_tx_queue *tx_q) 3950 { 3951 u16 tag = 0x0, inner_tag = 0x0; 3952 u32 inner_type = 0x0; 3953 struct dma_desc *p; 3954 3955 if (!priv->dma_cap.vlins) 3956 return false; 3957 if (!skb_vlan_tag_present(skb)) 3958 return false; 3959 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3960 inner_tag = skb_vlan_tag_get(skb); 3961 inner_type = STMMAC_VLAN_INSERT; 3962 } 3963 3964 tag = skb_vlan_tag_get(skb); 3965 3966 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3967 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3968 else 3969 p = &tx_q->dma_tx[tx_q->cur_tx]; 3970 3971 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3972 return false; 3973 3974 stmmac_set_tx_owner(priv, p); 3975 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3976 return true; 3977 } 3978 3979 /** 3980 * stmmac_tso_allocator - close entry point of the driver 3981 * @priv: driver private structure 3982 * @des: buffer start address 3983 * @total_len: total length to fill in descriptors 3984 * @last_segment: condition for the last descriptor 3985 * @queue: TX queue index 3986 * Description: 3987 * This function fills descriptor and request new descriptors according to 3988 * buffer length to fill 3989 */ 3990 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3991 int total_len, bool last_segment, u32 queue) 3992 { 3993 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3994 struct dma_desc *desc; 3995 u32 buff_size; 3996 int tmp_len; 3997 3998 tmp_len = total_len; 3999 4000 while (tmp_len > 0) { 4001 dma_addr_t curr_addr; 4002 4003 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4004 priv->dma_conf.dma_tx_size); 4005 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4006 4007 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4008 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4009 else 4010 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4011 4012 curr_addr = des + (total_len - tmp_len); 4013 if (priv->dma_cap.addr64 <= 32) 4014 desc->des0 = cpu_to_le32(curr_addr); 4015 else 4016 stmmac_set_desc_addr(priv, desc, curr_addr); 4017 4018 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4019 TSO_MAX_BUFF_SIZE : tmp_len; 4020 4021 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4022 0, 1, 4023 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4024 0, 0); 4025 4026 tmp_len -= TSO_MAX_BUFF_SIZE; 4027 } 4028 } 4029 4030 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4031 { 4032 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4033 int desc_size; 4034 4035 if (likely(priv->extend_desc)) 4036 desc_size = sizeof(struct dma_extended_desc); 4037 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4038 desc_size = sizeof(struct dma_edesc); 4039 else 4040 desc_size = sizeof(struct dma_desc); 4041 4042 /* The own bit must be the latest setting done when prepare the 4043 * descriptor and then barrier is needed to make sure that 4044 * all is coherent before granting the DMA engine. 4045 */ 4046 wmb(); 4047 4048 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4049 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4050 } 4051 4052 /** 4053 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4054 * @skb : the socket buffer 4055 * @dev : device pointer 4056 * Description: this is the transmit function that is called on TSO frames 4057 * (support available on GMAC4 and newer chips). 4058 * Diagram below show the ring programming in case of TSO frames: 4059 * 4060 * First Descriptor 4061 * -------- 4062 * | DES0 |---> buffer1 = L2/L3/L4 header 4063 * | DES1 |---> TCP Payload (can continue on next descr...) 4064 * | DES2 |---> buffer 1 and 2 len 4065 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4066 * -------- 4067 * | 4068 * ... 4069 * | 4070 * -------- 4071 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4072 * | DES1 | --| 4073 * | DES2 | --> buffer 1 and 2 len 4074 * | DES3 | 4075 * -------- 4076 * 4077 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4078 */ 4079 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4080 { 4081 struct dma_desc *desc, *first, *mss_desc = NULL; 4082 struct stmmac_priv *priv = netdev_priv(dev); 4083 int nfrags = skb_shinfo(skb)->nr_frags; 4084 u32 queue = skb_get_queue_mapping(skb); 4085 unsigned int first_entry, tx_packets; 4086 int tmp_pay_len = 0, first_tx; 4087 struct stmmac_tx_queue *tx_q; 4088 bool has_vlan, set_ic; 4089 u8 proto_hdr_len, hdr; 4090 u32 pay_len, mss; 4091 dma_addr_t des; 4092 int i; 4093 4094 tx_q = &priv->dma_conf.tx_queue[queue]; 4095 first_tx = tx_q->cur_tx; 4096 4097 /* Compute header lengths */ 4098 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4099 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4100 hdr = sizeof(struct udphdr); 4101 } else { 4102 proto_hdr_len = skb_tcp_all_headers(skb); 4103 hdr = tcp_hdrlen(skb); 4104 } 4105 4106 /* Desc availability based on threshold should be enough safe */ 4107 if (unlikely(stmmac_tx_avail(priv, queue) < 4108 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4109 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4110 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4111 queue)); 4112 /* This is a hard error, log it. */ 4113 netdev_err(priv->dev, 4114 "%s: Tx Ring full when queue awake\n", 4115 __func__); 4116 } 4117 return NETDEV_TX_BUSY; 4118 } 4119 4120 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4121 4122 mss = skb_shinfo(skb)->gso_size; 4123 4124 /* set new MSS value if needed */ 4125 if (mss != tx_q->mss) { 4126 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4127 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4128 else 4129 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4130 4131 stmmac_set_mss(priv, mss_desc, mss); 4132 tx_q->mss = mss; 4133 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4134 priv->dma_conf.dma_tx_size); 4135 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4136 } 4137 4138 if (netif_msg_tx_queued(priv)) { 4139 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4140 __func__, hdr, proto_hdr_len, pay_len, mss); 4141 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4142 skb->data_len); 4143 } 4144 4145 /* Check if VLAN can be inserted by HW */ 4146 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4147 4148 first_entry = tx_q->cur_tx; 4149 WARN_ON(tx_q->tx_skbuff[first_entry]); 4150 4151 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4152 desc = &tx_q->dma_entx[first_entry].basic; 4153 else 4154 desc = &tx_q->dma_tx[first_entry]; 4155 first = desc; 4156 4157 if (has_vlan) 4158 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4159 4160 /* first descriptor: fill Headers on Buf1 */ 4161 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4162 DMA_TO_DEVICE); 4163 if (dma_mapping_error(priv->device, des)) 4164 goto dma_map_err; 4165 4166 tx_q->tx_skbuff_dma[first_entry].buf = des; 4167 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4168 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4169 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4170 4171 if (priv->dma_cap.addr64 <= 32) { 4172 first->des0 = cpu_to_le32(des); 4173 4174 /* Fill start of payload in buff2 of first descriptor */ 4175 if (pay_len) 4176 first->des1 = cpu_to_le32(des + proto_hdr_len); 4177 4178 /* If needed take extra descriptors to fill the remaining payload */ 4179 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4180 } else { 4181 stmmac_set_desc_addr(priv, first, des); 4182 tmp_pay_len = pay_len; 4183 des += proto_hdr_len; 4184 pay_len = 0; 4185 } 4186 4187 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4188 4189 /* Prepare fragments */ 4190 for (i = 0; i < nfrags; i++) { 4191 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4192 4193 des = skb_frag_dma_map(priv->device, frag, 0, 4194 skb_frag_size(frag), 4195 DMA_TO_DEVICE); 4196 if (dma_mapping_error(priv->device, des)) 4197 goto dma_map_err; 4198 4199 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4200 (i == nfrags - 1), queue); 4201 4202 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4203 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4204 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4205 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4206 } 4207 4208 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4209 4210 /* Only the last descriptor gets to point to the skb. */ 4211 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4212 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4213 4214 /* Manage tx mitigation */ 4215 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4216 tx_q->tx_count_frames += tx_packets; 4217 4218 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4219 set_ic = true; 4220 else if (!priv->tx_coal_frames[queue]) 4221 set_ic = false; 4222 else if (tx_packets > priv->tx_coal_frames[queue]) 4223 set_ic = true; 4224 else if ((tx_q->tx_count_frames % 4225 priv->tx_coal_frames[queue]) < tx_packets) 4226 set_ic = true; 4227 else 4228 set_ic = false; 4229 4230 if (set_ic) { 4231 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4232 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4233 else 4234 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4235 4236 tx_q->tx_count_frames = 0; 4237 stmmac_set_tx_ic(priv, desc); 4238 priv->xstats.tx_set_ic_bit++; 4239 } 4240 4241 /* We've used all descriptors we need for this skb, however, 4242 * advance cur_tx so that it references a fresh descriptor. 4243 * ndo_start_xmit will fill this descriptor the next time it's 4244 * called and stmmac_tx_clean may clean up to this descriptor. 4245 */ 4246 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4247 4248 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4249 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4250 __func__); 4251 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4252 } 4253 4254 dev->stats.tx_bytes += skb->len; 4255 priv->xstats.tx_tso_frames++; 4256 priv->xstats.tx_tso_nfrags += nfrags; 4257 4258 if (priv->sarc_type) 4259 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4260 4261 skb_tx_timestamp(skb); 4262 4263 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4264 priv->hwts_tx_en)) { 4265 /* declare that device is doing timestamping */ 4266 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4267 stmmac_enable_tx_timestamp(priv, first); 4268 } 4269 4270 /* Complete the first descriptor before granting the DMA */ 4271 stmmac_prepare_tso_tx_desc(priv, first, 1, 4272 proto_hdr_len, 4273 pay_len, 4274 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4275 hdr / 4, (skb->len - proto_hdr_len)); 4276 4277 /* If context desc is used to change MSS */ 4278 if (mss_desc) { 4279 /* Make sure that first descriptor has been completely 4280 * written, including its own bit. This is because MSS is 4281 * actually before first descriptor, so we need to make 4282 * sure that MSS's own bit is the last thing written. 4283 */ 4284 dma_wmb(); 4285 stmmac_set_tx_owner(priv, mss_desc); 4286 } 4287 4288 if (netif_msg_pktdata(priv)) { 4289 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4290 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4291 tx_q->cur_tx, first, nfrags); 4292 pr_info(">>> frame to be transmitted: "); 4293 print_pkt(skb->data, skb_headlen(skb)); 4294 } 4295 4296 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4297 4298 stmmac_flush_tx_descriptors(priv, queue); 4299 stmmac_tx_timer_arm(priv, queue); 4300 4301 return NETDEV_TX_OK; 4302 4303 dma_map_err: 4304 dev_err(priv->device, "Tx dma map failed\n"); 4305 dev_kfree_skb(skb); 4306 priv->dev->stats.tx_dropped++; 4307 return NETDEV_TX_OK; 4308 } 4309 4310 /** 4311 * stmmac_xmit - Tx entry point of the driver 4312 * @skb : the socket buffer 4313 * @dev : device pointer 4314 * Description : this is the tx entry point of the driver. 4315 * It programs the chain or the ring and supports oversized frames 4316 * and SG feature. 4317 */ 4318 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4319 { 4320 unsigned int first_entry, tx_packets, enh_desc; 4321 struct stmmac_priv *priv = netdev_priv(dev); 4322 unsigned int nopaged_len = skb_headlen(skb); 4323 int i, csum_insertion = 0, is_jumbo = 0; 4324 u32 queue = skb_get_queue_mapping(skb); 4325 int nfrags = skb_shinfo(skb)->nr_frags; 4326 int gso = skb_shinfo(skb)->gso_type; 4327 struct dma_edesc *tbs_desc = NULL; 4328 struct dma_desc *desc, *first; 4329 struct stmmac_tx_queue *tx_q; 4330 bool has_vlan, set_ic; 4331 int entry, first_tx; 4332 dma_addr_t des; 4333 4334 tx_q = &priv->dma_conf.tx_queue[queue]; 4335 first_tx = tx_q->cur_tx; 4336 4337 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4338 stmmac_disable_eee_mode(priv); 4339 4340 /* Manage oversized TCP frames for GMAC4 device */ 4341 if (skb_is_gso(skb) && priv->tso) { 4342 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4343 return stmmac_tso_xmit(skb, dev); 4344 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4345 return stmmac_tso_xmit(skb, dev); 4346 } 4347 4348 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4349 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4350 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4351 queue)); 4352 /* This is a hard error, log it. */ 4353 netdev_err(priv->dev, 4354 "%s: Tx Ring full when queue awake\n", 4355 __func__); 4356 } 4357 return NETDEV_TX_BUSY; 4358 } 4359 4360 /* Check if VLAN can be inserted by HW */ 4361 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4362 4363 entry = tx_q->cur_tx; 4364 first_entry = entry; 4365 WARN_ON(tx_q->tx_skbuff[first_entry]); 4366 4367 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4368 4369 if (likely(priv->extend_desc)) 4370 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4371 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4372 desc = &tx_q->dma_entx[entry].basic; 4373 else 4374 desc = tx_q->dma_tx + entry; 4375 4376 first = desc; 4377 4378 if (has_vlan) 4379 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4380 4381 enh_desc = priv->plat->enh_desc; 4382 /* To program the descriptors according to the size of the frame */ 4383 if (enh_desc) 4384 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4385 4386 if (unlikely(is_jumbo)) { 4387 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4388 if (unlikely(entry < 0) && (entry != -EINVAL)) 4389 goto dma_map_err; 4390 } 4391 4392 for (i = 0; i < nfrags; i++) { 4393 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4394 int len = skb_frag_size(frag); 4395 bool last_segment = (i == (nfrags - 1)); 4396 4397 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4398 WARN_ON(tx_q->tx_skbuff[entry]); 4399 4400 if (likely(priv->extend_desc)) 4401 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4402 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4403 desc = &tx_q->dma_entx[entry].basic; 4404 else 4405 desc = tx_q->dma_tx + entry; 4406 4407 des = skb_frag_dma_map(priv->device, frag, 0, len, 4408 DMA_TO_DEVICE); 4409 if (dma_mapping_error(priv->device, des)) 4410 goto dma_map_err; /* should reuse desc w/o issues */ 4411 4412 tx_q->tx_skbuff_dma[entry].buf = des; 4413 4414 stmmac_set_desc_addr(priv, desc, des); 4415 4416 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4417 tx_q->tx_skbuff_dma[entry].len = len; 4418 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4419 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4420 4421 /* Prepare the descriptor and set the own bit too */ 4422 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4423 priv->mode, 1, last_segment, skb->len); 4424 } 4425 4426 /* Only the last descriptor gets to point to the skb. */ 4427 tx_q->tx_skbuff[entry] = skb; 4428 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4429 4430 /* According to the coalesce parameter the IC bit for the latest 4431 * segment is reset and the timer re-started to clean the tx status. 4432 * This approach takes care about the fragments: desc is the first 4433 * element in case of no SG. 4434 */ 4435 tx_packets = (entry + 1) - first_tx; 4436 tx_q->tx_count_frames += tx_packets; 4437 4438 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4439 set_ic = true; 4440 else if (!priv->tx_coal_frames[queue]) 4441 set_ic = false; 4442 else if (tx_packets > priv->tx_coal_frames[queue]) 4443 set_ic = true; 4444 else if ((tx_q->tx_count_frames % 4445 priv->tx_coal_frames[queue]) < tx_packets) 4446 set_ic = true; 4447 else 4448 set_ic = false; 4449 4450 if (set_ic) { 4451 if (likely(priv->extend_desc)) 4452 desc = &tx_q->dma_etx[entry].basic; 4453 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4454 desc = &tx_q->dma_entx[entry].basic; 4455 else 4456 desc = &tx_q->dma_tx[entry]; 4457 4458 tx_q->tx_count_frames = 0; 4459 stmmac_set_tx_ic(priv, desc); 4460 priv->xstats.tx_set_ic_bit++; 4461 } 4462 4463 /* We've used all descriptors we need for this skb, however, 4464 * advance cur_tx so that it references a fresh descriptor. 4465 * ndo_start_xmit will fill this descriptor the next time it's 4466 * called and stmmac_tx_clean may clean up to this descriptor. 4467 */ 4468 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4469 tx_q->cur_tx = entry; 4470 4471 if (netif_msg_pktdata(priv)) { 4472 netdev_dbg(priv->dev, 4473 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4474 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4475 entry, first, nfrags); 4476 4477 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4478 print_pkt(skb->data, skb->len); 4479 } 4480 4481 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4482 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4483 __func__); 4484 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4485 } 4486 4487 dev->stats.tx_bytes += skb->len; 4488 4489 if (priv->sarc_type) 4490 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4491 4492 skb_tx_timestamp(skb); 4493 4494 /* Ready to fill the first descriptor and set the OWN bit w/o any 4495 * problems because all the descriptors are actually ready to be 4496 * passed to the DMA engine. 4497 */ 4498 if (likely(!is_jumbo)) { 4499 bool last_segment = (nfrags == 0); 4500 4501 des = dma_map_single(priv->device, skb->data, 4502 nopaged_len, DMA_TO_DEVICE); 4503 if (dma_mapping_error(priv->device, des)) 4504 goto dma_map_err; 4505 4506 tx_q->tx_skbuff_dma[first_entry].buf = des; 4507 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4508 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4509 4510 stmmac_set_desc_addr(priv, first, des); 4511 4512 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4513 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4514 4515 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4516 priv->hwts_tx_en)) { 4517 /* declare that device is doing timestamping */ 4518 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4519 stmmac_enable_tx_timestamp(priv, first); 4520 } 4521 4522 /* Prepare the first descriptor setting the OWN bit too */ 4523 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4524 csum_insertion, priv->mode, 0, last_segment, 4525 skb->len); 4526 } 4527 4528 if (tx_q->tbs & STMMAC_TBS_EN) { 4529 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4530 4531 tbs_desc = &tx_q->dma_entx[first_entry]; 4532 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4533 } 4534 4535 stmmac_set_tx_owner(priv, first); 4536 4537 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4538 4539 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4540 4541 stmmac_flush_tx_descriptors(priv, queue); 4542 stmmac_tx_timer_arm(priv, queue); 4543 4544 return NETDEV_TX_OK; 4545 4546 dma_map_err: 4547 netdev_err(priv->dev, "Tx DMA map failed\n"); 4548 dev_kfree_skb(skb); 4549 priv->dev->stats.tx_dropped++; 4550 return NETDEV_TX_OK; 4551 } 4552 4553 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4554 { 4555 struct vlan_ethhdr *veth; 4556 __be16 vlan_proto; 4557 u16 vlanid; 4558 4559 veth = (struct vlan_ethhdr *)skb->data; 4560 vlan_proto = veth->h_vlan_proto; 4561 4562 if ((vlan_proto == htons(ETH_P_8021Q) && 4563 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4564 (vlan_proto == htons(ETH_P_8021AD) && 4565 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4566 /* pop the vlan tag */ 4567 vlanid = ntohs(veth->h_vlan_TCI); 4568 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4569 skb_pull(skb, VLAN_HLEN); 4570 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4571 } 4572 } 4573 4574 /** 4575 * stmmac_rx_refill - refill used skb preallocated buffers 4576 * @priv: driver private structure 4577 * @queue: RX queue index 4578 * Description : this is to reallocate the skb for the reception process 4579 * that is based on zero-copy. 4580 */ 4581 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4582 { 4583 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4584 int dirty = stmmac_rx_dirty(priv, queue); 4585 unsigned int entry = rx_q->dirty_rx; 4586 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4587 4588 if (priv->dma_cap.addr64 <= 32) 4589 gfp |= GFP_DMA32; 4590 4591 while (dirty-- > 0) { 4592 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4593 struct dma_desc *p; 4594 bool use_rx_wd; 4595 4596 if (priv->extend_desc) 4597 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4598 else 4599 p = rx_q->dma_rx + entry; 4600 4601 if (!buf->page) { 4602 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4603 if (!buf->page) 4604 break; 4605 } 4606 4607 if (priv->sph && !buf->sec_page) { 4608 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4609 if (!buf->sec_page) 4610 break; 4611 4612 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4613 } 4614 4615 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4616 4617 stmmac_set_desc_addr(priv, p, buf->addr); 4618 if (priv->sph) 4619 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4620 else 4621 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4622 stmmac_refill_desc3(priv, rx_q, p); 4623 4624 rx_q->rx_count_frames++; 4625 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4626 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4627 rx_q->rx_count_frames = 0; 4628 4629 use_rx_wd = !priv->rx_coal_frames[queue]; 4630 use_rx_wd |= rx_q->rx_count_frames > 0; 4631 if (!priv->use_riwt) 4632 use_rx_wd = false; 4633 4634 dma_wmb(); 4635 stmmac_set_rx_owner(priv, p, use_rx_wd); 4636 4637 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4638 } 4639 rx_q->dirty_rx = entry; 4640 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4641 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4642 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4643 } 4644 4645 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4646 struct dma_desc *p, 4647 int status, unsigned int len) 4648 { 4649 unsigned int plen = 0, hlen = 0; 4650 int coe = priv->hw->rx_csum; 4651 4652 /* Not first descriptor, buffer is always zero */ 4653 if (priv->sph && len) 4654 return 0; 4655 4656 /* First descriptor, get split header length */ 4657 stmmac_get_rx_header_len(priv, p, &hlen); 4658 if (priv->sph && hlen) { 4659 priv->xstats.rx_split_hdr_pkt_n++; 4660 return hlen; 4661 } 4662 4663 /* First descriptor, not last descriptor and not split header */ 4664 if (status & rx_not_ls) 4665 return priv->dma_conf.dma_buf_sz; 4666 4667 plen = stmmac_get_rx_frame_len(priv, p, coe); 4668 4669 /* First descriptor and last descriptor and not split header */ 4670 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4671 } 4672 4673 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4674 struct dma_desc *p, 4675 int status, unsigned int len) 4676 { 4677 int coe = priv->hw->rx_csum; 4678 unsigned int plen = 0; 4679 4680 /* Not split header, buffer is not available */ 4681 if (!priv->sph) 4682 return 0; 4683 4684 /* Not last descriptor */ 4685 if (status & rx_not_ls) 4686 return priv->dma_conf.dma_buf_sz; 4687 4688 plen = stmmac_get_rx_frame_len(priv, p, coe); 4689 4690 /* Last descriptor */ 4691 return plen - len; 4692 } 4693 4694 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4695 struct xdp_frame *xdpf, bool dma_map) 4696 { 4697 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4698 unsigned int entry = tx_q->cur_tx; 4699 struct dma_desc *tx_desc; 4700 dma_addr_t dma_addr; 4701 bool set_ic; 4702 4703 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4704 return STMMAC_XDP_CONSUMED; 4705 4706 if (likely(priv->extend_desc)) 4707 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4708 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4709 tx_desc = &tx_q->dma_entx[entry].basic; 4710 else 4711 tx_desc = tx_q->dma_tx + entry; 4712 4713 if (dma_map) { 4714 dma_addr = dma_map_single(priv->device, xdpf->data, 4715 xdpf->len, DMA_TO_DEVICE); 4716 if (dma_mapping_error(priv->device, dma_addr)) 4717 return STMMAC_XDP_CONSUMED; 4718 4719 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4720 } else { 4721 struct page *page = virt_to_page(xdpf->data); 4722 4723 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4724 xdpf->headroom; 4725 dma_sync_single_for_device(priv->device, dma_addr, 4726 xdpf->len, DMA_BIDIRECTIONAL); 4727 4728 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4729 } 4730 4731 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4732 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4733 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4734 tx_q->tx_skbuff_dma[entry].last_segment = true; 4735 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4736 4737 tx_q->xdpf[entry] = xdpf; 4738 4739 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4740 4741 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4742 true, priv->mode, true, true, 4743 xdpf->len); 4744 4745 tx_q->tx_count_frames++; 4746 4747 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4748 set_ic = true; 4749 else 4750 set_ic = false; 4751 4752 if (set_ic) { 4753 tx_q->tx_count_frames = 0; 4754 stmmac_set_tx_ic(priv, tx_desc); 4755 priv->xstats.tx_set_ic_bit++; 4756 } 4757 4758 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4759 4760 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4761 tx_q->cur_tx = entry; 4762 4763 return STMMAC_XDP_TX; 4764 } 4765 4766 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4767 int cpu) 4768 { 4769 int index = cpu; 4770 4771 if (unlikely(index < 0)) 4772 index = 0; 4773 4774 while (index >= priv->plat->tx_queues_to_use) 4775 index -= priv->plat->tx_queues_to_use; 4776 4777 return index; 4778 } 4779 4780 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4781 struct xdp_buff *xdp) 4782 { 4783 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4784 int cpu = smp_processor_id(); 4785 struct netdev_queue *nq; 4786 int queue; 4787 int res; 4788 4789 if (unlikely(!xdpf)) 4790 return STMMAC_XDP_CONSUMED; 4791 4792 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4793 nq = netdev_get_tx_queue(priv->dev, queue); 4794 4795 __netif_tx_lock(nq, cpu); 4796 /* Avoids TX time-out as we are sharing with slow path */ 4797 txq_trans_cond_update(nq); 4798 4799 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4800 if (res == STMMAC_XDP_TX) 4801 stmmac_flush_tx_descriptors(priv, queue); 4802 4803 __netif_tx_unlock(nq); 4804 4805 return res; 4806 } 4807 4808 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4809 struct bpf_prog *prog, 4810 struct xdp_buff *xdp) 4811 { 4812 u32 act; 4813 int res; 4814 4815 act = bpf_prog_run_xdp(prog, xdp); 4816 switch (act) { 4817 case XDP_PASS: 4818 res = STMMAC_XDP_PASS; 4819 break; 4820 case XDP_TX: 4821 res = stmmac_xdp_xmit_back(priv, xdp); 4822 break; 4823 case XDP_REDIRECT: 4824 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4825 res = STMMAC_XDP_CONSUMED; 4826 else 4827 res = STMMAC_XDP_REDIRECT; 4828 break; 4829 default: 4830 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4831 fallthrough; 4832 case XDP_ABORTED: 4833 trace_xdp_exception(priv->dev, prog, act); 4834 fallthrough; 4835 case XDP_DROP: 4836 res = STMMAC_XDP_CONSUMED; 4837 break; 4838 } 4839 4840 return res; 4841 } 4842 4843 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4844 struct xdp_buff *xdp) 4845 { 4846 struct bpf_prog *prog; 4847 int res; 4848 4849 prog = READ_ONCE(priv->xdp_prog); 4850 if (!prog) { 4851 res = STMMAC_XDP_PASS; 4852 goto out; 4853 } 4854 4855 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4856 out: 4857 return ERR_PTR(-res); 4858 } 4859 4860 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4861 int xdp_status) 4862 { 4863 int cpu = smp_processor_id(); 4864 int queue; 4865 4866 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4867 4868 if (xdp_status & STMMAC_XDP_TX) 4869 stmmac_tx_timer_arm(priv, queue); 4870 4871 if (xdp_status & STMMAC_XDP_REDIRECT) 4872 xdp_do_flush(); 4873 } 4874 4875 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4876 struct xdp_buff *xdp) 4877 { 4878 unsigned int metasize = xdp->data - xdp->data_meta; 4879 unsigned int datasize = xdp->data_end - xdp->data; 4880 struct sk_buff *skb; 4881 4882 skb = __napi_alloc_skb(&ch->rxtx_napi, 4883 xdp->data_end - xdp->data_hard_start, 4884 GFP_ATOMIC | __GFP_NOWARN); 4885 if (unlikely(!skb)) 4886 return NULL; 4887 4888 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4889 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4890 if (metasize) 4891 skb_metadata_set(skb, metasize); 4892 4893 return skb; 4894 } 4895 4896 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4897 struct dma_desc *p, struct dma_desc *np, 4898 struct xdp_buff *xdp) 4899 { 4900 struct stmmac_channel *ch = &priv->channel[queue]; 4901 unsigned int len = xdp->data_end - xdp->data; 4902 enum pkt_hash_types hash_type; 4903 int coe = priv->hw->rx_csum; 4904 struct sk_buff *skb; 4905 u32 hash; 4906 4907 skb = stmmac_construct_skb_zc(ch, xdp); 4908 if (!skb) { 4909 priv->dev->stats.rx_dropped++; 4910 return; 4911 } 4912 4913 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4914 stmmac_rx_vlan(priv->dev, skb); 4915 skb->protocol = eth_type_trans(skb, priv->dev); 4916 4917 if (unlikely(!coe)) 4918 skb_checksum_none_assert(skb); 4919 else 4920 skb->ip_summed = CHECKSUM_UNNECESSARY; 4921 4922 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4923 skb_set_hash(skb, hash, hash_type); 4924 4925 skb_record_rx_queue(skb, queue); 4926 napi_gro_receive(&ch->rxtx_napi, skb); 4927 4928 priv->dev->stats.rx_packets++; 4929 priv->dev->stats.rx_bytes += len; 4930 } 4931 4932 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4933 { 4934 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4935 unsigned int entry = rx_q->dirty_rx; 4936 struct dma_desc *rx_desc = NULL; 4937 bool ret = true; 4938 4939 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4940 4941 while (budget-- > 0 && entry != rx_q->cur_rx) { 4942 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4943 dma_addr_t dma_addr; 4944 bool use_rx_wd; 4945 4946 if (!buf->xdp) { 4947 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4948 if (!buf->xdp) { 4949 ret = false; 4950 break; 4951 } 4952 } 4953 4954 if (priv->extend_desc) 4955 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4956 else 4957 rx_desc = rx_q->dma_rx + entry; 4958 4959 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4960 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4961 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4962 stmmac_refill_desc3(priv, rx_q, rx_desc); 4963 4964 rx_q->rx_count_frames++; 4965 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4966 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4967 rx_q->rx_count_frames = 0; 4968 4969 use_rx_wd = !priv->rx_coal_frames[queue]; 4970 use_rx_wd |= rx_q->rx_count_frames > 0; 4971 if (!priv->use_riwt) 4972 use_rx_wd = false; 4973 4974 dma_wmb(); 4975 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4976 4977 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4978 } 4979 4980 if (rx_desc) { 4981 rx_q->dirty_rx = entry; 4982 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4983 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4984 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4985 } 4986 4987 return ret; 4988 } 4989 4990 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4991 { 4992 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4993 unsigned int count = 0, error = 0, len = 0; 4994 int dirty = stmmac_rx_dirty(priv, queue); 4995 unsigned int next_entry = rx_q->cur_rx; 4996 unsigned int desc_size; 4997 struct bpf_prog *prog; 4998 bool failure = false; 4999 int xdp_status = 0; 5000 int status = 0; 5001 5002 if (netif_msg_rx_status(priv)) { 5003 void *rx_head; 5004 5005 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5006 if (priv->extend_desc) { 5007 rx_head = (void *)rx_q->dma_erx; 5008 desc_size = sizeof(struct dma_extended_desc); 5009 } else { 5010 rx_head = (void *)rx_q->dma_rx; 5011 desc_size = sizeof(struct dma_desc); 5012 } 5013 5014 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5015 rx_q->dma_rx_phy, desc_size); 5016 } 5017 while (count < limit) { 5018 struct stmmac_rx_buffer *buf; 5019 unsigned int buf1_len = 0; 5020 struct dma_desc *np, *p; 5021 int entry; 5022 int res; 5023 5024 if (!count && rx_q->state_saved) { 5025 error = rx_q->state.error; 5026 len = rx_q->state.len; 5027 } else { 5028 rx_q->state_saved = false; 5029 error = 0; 5030 len = 0; 5031 } 5032 5033 if (count >= limit) 5034 break; 5035 5036 read_again: 5037 buf1_len = 0; 5038 entry = next_entry; 5039 buf = &rx_q->buf_pool[entry]; 5040 5041 if (dirty >= STMMAC_RX_FILL_BATCH) { 5042 failure = failure || 5043 !stmmac_rx_refill_zc(priv, queue, dirty); 5044 dirty = 0; 5045 } 5046 5047 if (priv->extend_desc) 5048 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5049 else 5050 p = rx_q->dma_rx + entry; 5051 5052 /* read the status of the incoming frame */ 5053 status = stmmac_rx_status(priv, &priv->dev->stats, 5054 &priv->xstats, p); 5055 /* check if managed by the DMA otherwise go ahead */ 5056 if (unlikely(status & dma_own)) 5057 break; 5058 5059 /* Prefetch the next RX descriptor */ 5060 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5061 priv->dma_conf.dma_rx_size); 5062 next_entry = rx_q->cur_rx; 5063 5064 if (priv->extend_desc) 5065 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5066 else 5067 np = rx_q->dma_rx + next_entry; 5068 5069 prefetch(np); 5070 5071 /* Ensure a valid XSK buffer before proceed */ 5072 if (!buf->xdp) 5073 break; 5074 5075 if (priv->extend_desc) 5076 stmmac_rx_extended_status(priv, &priv->dev->stats, 5077 &priv->xstats, 5078 rx_q->dma_erx + entry); 5079 if (unlikely(status == discard_frame)) { 5080 xsk_buff_free(buf->xdp); 5081 buf->xdp = NULL; 5082 dirty++; 5083 error = 1; 5084 if (!priv->hwts_rx_en) 5085 priv->dev->stats.rx_errors++; 5086 } 5087 5088 if (unlikely(error && (status & rx_not_ls))) 5089 goto read_again; 5090 if (unlikely(error)) { 5091 count++; 5092 continue; 5093 } 5094 5095 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5096 if (likely(status & rx_not_ls)) { 5097 xsk_buff_free(buf->xdp); 5098 buf->xdp = NULL; 5099 dirty++; 5100 count++; 5101 goto read_again; 5102 } 5103 5104 /* XDP ZC Frame only support primary buffers for now */ 5105 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5106 len += buf1_len; 5107 5108 /* ACS is disabled; strip manually. */ 5109 if (likely(!(status & rx_not_ls))) { 5110 buf1_len -= ETH_FCS_LEN; 5111 len -= ETH_FCS_LEN; 5112 } 5113 5114 /* RX buffer is good and fit into a XSK pool buffer */ 5115 buf->xdp->data_end = buf->xdp->data + buf1_len; 5116 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5117 5118 prog = READ_ONCE(priv->xdp_prog); 5119 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5120 5121 switch (res) { 5122 case STMMAC_XDP_PASS: 5123 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5124 xsk_buff_free(buf->xdp); 5125 break; 5126 case STMMAC_XDP_CONSUMED: 5127 xsk_buff_free(buf->xdp); 5128 priv->dev->stats.rx_dropped++; 5129 break; 5130 case STMMAC_XDP_TX: 5131 case STMMAC_XDP_REDIRECT: 5132 xdp_status |= res; 5133 break; 5134 } 5135 5136 buf->xdp = NULL; 5137 dirty++; 5138 count++; 5139 } 5140 5141 if (status & rx_not_ls) { 5142 rx_q->state_saved = true; 5143 rx_q->state.error = error; 5144 rx_q->state.len = len; 5145 } 5146 5147 stmmac_finalize_xdp_rx(priv, xdp_status); 5148 5149 priv->xstats.rx_pkt_n += count; 5150 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5151 5152 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5153 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5154 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5155 else 5156 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5157 5158 return (int)count; 5159 } 5160 5161 return failure ? limit : (int)count; 5162 } 5163 5164 /** 5165 * stmmac_rx - manage the receive process 5166 * @priv: driver private structure 5167 * @limit: napi bugget 5168 * @queue: RX queue index. 5169 * Description : this the function called by the napi poll method. 5170 * It gets all the frames inside the ring. 5171 */ 5172 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5173 { 5174 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5175 struct stmmac_channel *ch = &priv->channel[queue]; 5176 unsigned int count = 0, error = 0, len = 0; 5177 int status = 0, coe = priv->hw->rx_csum; 5178 unsigned int next_entry = rx_q->cur_rx; 5179 enum dma_data_direction dma_dir; 5180 unsigned int desc_size; 5181 struct sk_buff *skb = NULL; 5182 struct xdp_buff xdp; 5183 int xdp_status = 0; 5184 int buf_sz; 5185 5186 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5187 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5188 5189 if (netif_msg_rx_status(priv)) { 5190 void *rx_head; 5191 5192 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5193 if (priv->extend_desc) { 5194 rx_head = (void *)rx_q->dma_erx; 5195 desc_size = sizeof(struct dma_extended_desc); 5196 } else { 5197 rx_head = (void *)rx_q->dma_rx; 5198 desc_size = sizeof(struct dma_desc); 5199 } 5200 5201 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5202 rx_q->dma_rx_phy, desc_size); 5203 } 5204 while (count < limit) { 5205 unsigned int buf1_len = 0, buf2_len = 0; 5206 enum pkt_hash_types hash_type; 5207 struct stmmac_rx_buffer *buf; 5208 struct dma_desc *np, *p; 5209 int entry; 5210 u32 hash; 5211 5212 if (!count && rx_q->state_saved) { 5213 skb = rx_q->state.skb; 5214 error = rx_q->state.error; 5215 len = rx_q->state.len; 5216 } else { 5217 rx_q->state_saved = false; 5218 skb = NULL; 5219 error = 0; 5220 len = 0; 5221 } 5222 5223 if (count >= limit) 5224 break; 5225 5226 read_again: 5227 buf1_len = 0; 5228 buf2_len = 0; 5229 entry = next_entry; 5230 buf = &rx_q->buf_pool[entry]; 5231 5232 if (priv->extend_desc) 5233 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5234 else 5235 p = rx_q->dma_rx + entry; 5236 5237 /* read the status of the incoming frame */ 5238 status = stmmac_rx_status(priv, &priv->dev->stats, 5239 &priv->xstats, p); 5240 /* check if managed by the DMA otherwise go ahead */ 5241 if (unlikely(status & dma_own)) 5242 break; 5243 5244 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5245 priv->dma_conf.dma_rx_size); 5246 next_entry = rx_q->cur_rx; 5247 5248 if (priv->extend_desc) 5249 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5250 else 5251 np = rx_q->dma_rx + next_entry; 5252 5253 prefetch(np); 5254 5255 if (priv->extend_desc) 5256 stmmac_rx_extended_status(priv, &priv->dev->stats, 5257 &priv->xstats, rx_q->dma_erx + entry); 5258 if (unlikely(status == discard_frame)) { 5259 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5260 buf->page = NULL; 5261 error = 1; 5262 if (!priv->hwts_rx_en) 5263 priv->dev->stats.rx_errors++; 5264 } 5265 5266 if (unlikely(error && (status & rx_not_ls))) 5267 goto read_again; 5268 if (unlikely(error)) { 5269 dev_kfree_skb(skb); 5270 skb = NULL; 5271 count++; 5272 continue; 5273 } 5274 5275 /* Buffer is good. Go on. */ 5276 5277 prefetch(page_address(buf->page) + buf->page_offset); 5278 if (buf->sec_page) 5279 prefetch(page_address(buf->sec_page)); 5280 5281 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5282 len += buf1_len; 5283 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5284 len += buf2_len; 5285 5286 /* ACS is disabled; strip manually. */ 5287 if (likely(!(status & rx_not_ls))) { 5288 if (buf2_len) { 5289 buf2_len -= ETH_FCS_LEN; 5290 len -= ETH_FCS_LEN; 5291 } else if (buf1_len) { 5292 buf1_len -= ETH_FCS_LEN; 5293 len -= ETH_FCS_LEN; 5294 } 5295 } 5296 5297 if (!skb) { 5298 unsigned int pre_len, sync_len; 5299 5300 dma_sync_single_for_cpu(priv->device, buf->addr, 5301 buf1_len, dma_dir); 5302 5303 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5304 xdp_prepare_buff(&xdp, page_address(buf->page), 5305 buf->page_offset, buf1_len, false); 5306 5307 pre_len = xdp.data_end - xdp.data_hard_start - 5308 buf->page_offset; 5309 skb = stmmac_xdp_run_prog(priv, &xdp); 5310 /* Due xdp_adjust_tail: DMA sync for_device 5311 * cover max len CPU touch 5312 */ 5313 sync_len = xdp.data_end - xdp.data_hard_start - 5314 buf->page_offset; 5315 sync_len = max(sync_len, pre_len); 5316 5317 /* For Not XDP_PASS verdict */ 5318 if (IS_ERR(skb)) { 5319 unsigned int xdp_res = -PTR_ERR(skb); 5320 5321 if (xdp_res & STMMAC_XDP_CONSUMED) { 5322 page_pool_put_page(rx_q->page_pool, 5323 virt_to_head_page(xdp.data), 5324 sync_len, true); 5325 buf->page = NULL; 5326 priv->dev->stats.rx_dropped++; 5327 5328 /* Clear skb as it was set as 5329 * status by XDP program. 5330 */ 5331 skb = NULL; 5332 5333 if (unlikely((status & rx_not_ls))) 5334 goto read_again; 5335 5336 count++; 5337 continue; 5338 } else if (xdp_res & (STMMAC_XDP_TX | 5339 STMMAC_XDP_REDIRECT)) { 5340 xdp_status |= xdp_res; 5341 buf->page = NULL; 5342 skb = NULL; 5343 count++; 5344 continue; 5345 } 5346 } 5347 } 5348 5349 if (!skb) { 5350 /* XDP program may expand or reduce tail */ 5351 buf1_len = xdp.data_end - xdp.data; 5352 5353 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5354 if (!skb) { 5355 priv->dev->stats.rx_dropped++; 5356 count++; 5357 goto drain_data; 5358 } 5359 5360 /* XDP program may adjust header */ 5361 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5362 skb_put(skb, buf1_len); 5363 5364 /* Data payload copied into SKB, page ready for recycle */ 5365 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5366 buf->page = NULL; 5367 } else if (buf1_len) { 5368 dma_sync_single_for_cpu(priv->device, buf->addr, 5369 buf1_len, dma_dir); 5370 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5371 buf->page, buf->page_offset, buf1_len, 5372 priv->dma_conf.dma_buf_sz); 5373 5374 /* Data payload appended into SKB */ 5375 page_pool_release_page(rx_q->page_pool, buf->page); 5376 buf->page = NULL; 5377 } 5378 5379 if (buf2_len) { 5380 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5381 buf2_len, dma_dir); 5382 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5383 buf->sec_page, 0, buf2_len, 5384 priv->dma_conf.dma_buf_sz); 5385 5386 /* Data payload appended into SKB */ 5387 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5388 buf->sec_page = NULL; 5389 } 5390 5391 drain_data: 5392 if (likely(status & rx_not_ls)) 5393 goto read_again; 5394 if (!skb) 5395 continue; 5396 5397 /* Got entire packet into SKB. Finish it. */ 5398 5399 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5400 stmmac_rx_vlan(priv->dev, skb); 5401 skb->protocol = eth_type_trans(skb, priv->dev); 5402 5403 if (unlikely(!coe)) 5404 skb_checksum_none_assert(skb); 5405 else 5406 skb->ip_summed = CHECKSUM_UNNECESSARY; 5407 5408 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5409 skb_set_hash(skb, hash, hash_type); 5410 5411 skb_record_rx_queue(skb, queue); 5412 napi_gro_receive(&ch->rx_napi, skb); 5413 skb = NULL; 5414 5415 priv->dev->stats.rx_packets++; 5416 priv->dev->stats.rx_bytes += len; 5417 count++; 5418 } 5419 5420 if (status & rx_not_ls || skb) { 5421 rx_q->state_saved = true; 5422 rx_q->state.skb = skb; 5423 rx_q->state.error = error; 5424 rx_q->state.len = len; 5425 } 5426 5427 stmmac_finalize_xdp_rx(priv, xdp_status); 5428 5429 stmmac_rx_refill(priv, queue); 5430 5431 priv->xstats.rx_pkt_n += count; 5432 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5433 5434 return count; 5435 } 5436 5437 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5438 { 5439 struct stmmac_channel *ch = 5440 container_of(napi, struct stmmac_channel, rx_napi); 5441 struct stmmac_priv *priv = ch->priv_data; 5442 u32 chan = ch->index; 5443 int work_done; 5444 5445 priv->xstats.napi_poll++; 5446 5447 work_done = stmmac_rx(priv, budget, chan); 5448 if (work_done < budget && napi_complete_done(napi, work_done)) { 5449 unsigned long flags; 5450 5451 spin_lock_irqsave(&ch->lock, flags); 5452 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5453 spin_unlock_irqrestore(&ch->lock, flags); 5454 } 5455 5456 return work_done; 5457 } 5458 5459 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5460 { 5461 struct stmmac_channel *ch = 5462 container_of(napi, struct stmmac_channel, tx_napi); 5463 struct stmmac_priv *priv = ch->priv_data; 5464 u32 chan = ch->index; 5465 int work_done; 5466 5467 priv->xstats.napi_poll++; 5468 5469 work_done = stmmac_tx_clean(priv, budget, chan); 5470 work_done = min(work_done, budget); 5471 5472 if (work_done < budget && napi_complete_done(napi, work_done)) { 5473 unsigned long flags; 5474 5475 spin_lock_irqsave(&ch->lock, flags); 5476 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5477 spin_unlock_irqrestore(&ch->lock, flags); 5478 } 5479 5480 return work_done; 5481 } 5482 5483 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5484 { 5485 struct stmmac_channel *ch = 5486 container_of(napi, struct stmmac_channel, rxtx_napi); 5487 struct stmmac_priv *priv = ch->priv_data; 5488 int rx_done, tx_done, rxtx_done; 5489 u32 chan = ch->index; 5490 5491 priv->xstats.napi_poll++; 5492 5493 tx_done = stmmac_tx_clean(priv, budget, chan); 5494 tx_done = min(tx_done, budget); 5495 5496 rx_done = stmmac_rx_zc(priv, budget, chan); 5497 5498 rxtx_done = max(tx_done, rx_done); 5499 5500 /* If either TX or RX work is not complete, return budget 5501 * and keep pooling 5502 */ 5503 if (rxtx_done >= budget) 5504 return budget; 5505 5506 /* all work done, exit the polling mode */ 5507 if (napi_complete_done(napi, rxtx_done)) { 5508 unsigned long flags; 5509 5510 spin_lock_irqsave(&ch->lock, flags); 5511 /* Both RX and TX work done are compelte, 5512 * so enable both RX & TX IRQs. 5513 */ 5514 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5515 spin_unlock_irqrestore(&ch->lock, flags); 5516 } 5517 5518 return min(rxtx_done, budget - 1); 5519 } 5520 5521 /** 5522 * stmmac_tx_timeout 5523 * @dev : Pointer to net device structure 5524 * @txqueue: the index of the hanging transmit queue 5525 * Description: this function is called when a packet transmission fails to 5526 * complete within a reasonable time. The driver will mark the error in the 5527 * netdev structure and arrange for the device to be reset to a sane state 5528 * in order to transmit a new packet. 5529 */ 5530 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5531 { 5532 struct stmmac_priv *priv = netdev_priv(dev); 5533 5534 stmmac_global_err(priv); 5535 } 5536 5537 /** 5538 * stmmac_set_rx_mode - entry point for multicast addressing 5539 * @dev : pointer to the device structure 5540 * Description: 5541 * This function is a driver entry point which gets called by the kernel 5542 * whenever multicast addresses must be enabled/disabled. 5543 * Return value: 5544 * void. 5545 */ 5546 static void stmmac_set_rx_mode(struct net_device *dev) 5547 { 5548 struct stmmac_priv *priv = netdev_priv(dev); 5549 5550 stmmac_set_filter(priv, priv->hw, dev); 5551 } 5552 5553 /** 5554 * stmmac_change_mtu - entry point to change MTU size for the device. 5555 * @dev : device pointer. 5556 * @new_mtu : the new MTU size for the device. 5557 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5558 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5559 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5560 * Return value: 5561 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5562 * file on failure. 5563 */ 5564 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5565 { 5566 struct stmmac_priv *priv = netdev_priv(dev); 5567 int txfifosz = priv->plat->tx_fifo_size; 5568 struct stmmac_dma_conf *dma_conf; 5569 const int mtu = new_mtu; 5570 int ret; 5571 5572 if (txfifosz == 0) 5573 txfifosz = priv->dma_cap.tx_fifo_size; 5574 5575 txfifosz /= priv->plat->tx_queues_to_use; 5576 5577 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5578 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5579 return -EINVAL; 5580 } 5581 5582 new_mtu = STMMAC_ALIGN(new_mtu); 5583 5584 /* If condition true, FIFO is too small or MTU too large */ 5585 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5586 return -EINVAL; 5587 5588 if (netif_running(dev)) { 5589 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5590 /* Try to allocate the new DMA conf with the new mtu */ 5591 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5592 if (IS_ERR(dma_conf)) { 5593 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5594 mtu); 5595 return PTR_ERR(dma_conf); 5596 } 5597 5598 stmmac_release(dev); 5599 5600 ret = __stmmac_open(dev, dma_conf); 5601 kfree(dma_conf); 5602 if (ret) { 5603 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5604 return ret; 5605 } 5606 5607 stmmac_set_rx_mode(dev); 5608 } 5609 5610 dev->mtu = mtu; 5611 netdev_update_features(dev); 5612 5613 return 0; 5614 } 5615 5616 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5617 netdev_features_t features) 5618 { 5619 struct stmmac_priv *priv = netdev_priv(dev); 5620 5621 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5622 features &= ~NETIF_F_RXCSUM; 5623 5624 if (!priv->plat->tx_coe) 5625 features &= ~NETIF_F_CSUM_MASK; 5626 5627 /* Some GMAC devices have a bugged Jumbo frame support that 5628 * needs to have the Tx COE disabled for oversized frames 5629 * (due to limited buffer sizes). In this case we disable 5630 * the TX csum insertion in the TDES and not use SF. 5631 */ 5632 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5633 features &= ~NETIF_F_CSUM_MASK; 5634 5635 /* Disable tso if asked by ethtool */ 5636 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5637 if (features & NETIF_F_TSO) 5638 priv->tso = true; 5639 else 5640 priv->tso = false; 5641 } 5642 5643 return features; 5644 } 5645 5646 static int stmmac_set_features(struct net_device *netdev, 5647 netdev_features_t features) 5648 { 5649 struct stmmac_priv *priv = netdev_priv(netdev); 5650 5651 /* Keep the COE Type in case of csum is supporting */ 5652 if (features & NETIF_F_RXCSUM) 5653 priv->hw->rx_csum = priv->plat->rx_coe; 5654 else 5655 priv->hw->rx_csum = 0; 5656 /* No check needed because rx_coe has been set before and it will be 5657 * fixed in case of issue. 5658 */ 5659 stmmac_rx_ipc(priv, priv->hw); 5660 5661 if (priv->sph_cap) { 5662 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5663 u32 chan; 5664 5665 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5666 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5667 } 5668 5669 return 0; 5670 } 5671 5672 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5673 { 5674 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5675 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5676 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5677 bool *hs_enable = &fpe_cfg->hs_enable; 5678 5679 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5680 return; 5681 5682 /* If LP has sent verify mPacket, LP is FPE capable */ 5683 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5684 if (*lp_state < FPE_STATE_CAPABLE) 5685 *lp_state = FPE_STATE_CAPABLE; 5686 5687 /* If user has requested FPE enable, quickly response */ 5688 if (*hs_enable) 5689 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5690 MPACKET_RESPONSE); 5691 } 5692 5693 /* If Local has sent verify mPacket, Local is FPE capable */ 5694 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5695 if (*lo_state < FPE_STATE_CAPABLE) 5696 *lo_state = FPE_STATE_CAPABLE; 5697 } 5698 5699 /* If LP has sent response mPacket, LP is entering FPE ON */ 5700 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5701 *lp_state = FPE_STATE_ENTERING_ON; 5702 5703 /* If Local has sent response mPacket, Local is entering FPE ON */ 5704 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5705 *lo_state = FPE_STATE_ENTERING_ON; 5706 5707 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5708 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5709 priv->fpe_wq) { 5710 queue_work(priv->fpe_wq, &priv->fpe_task); 5711 } 5712 } 5713 5714 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5715 { 5716 u32 rx_cnt = priv->plat->rx_queues_to_use; 5717 u32 tx_cnt = priv->plat->tx_queues_to_use; 5718 u32 queues_count; 5719 u32 queue; 5720 bool xmac; 5721 5722 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5723 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5724 5725 if (priv->irq_wake) 5726 pm_wakeup_event(priv->device, 0); 5727 5728 if (priv->dma_cap.estsel) 5729 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5730 &priv->xstats, tx_cnt); 5731 5732 if (priv->dma_cap.fpesel) { 5733 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5734 priv->dev); 5735 5736 stmmac_fpe_event_status(priv, status); 5737 } 5738 5739 /* To handle GMAC own interrupts */ 5740 if ((priv->plat->has_gmac) || xmac) { 5741 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5742 5743 if (unlikely(status)) { 5744 /* For LPI we need to save the tx status */ 5745 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5746 priv->tx_path_in_lpi_mode = true; 5747 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5748 priv->tx_path_in_lpi_mode = false; 5749 } 5750 5751 for (queue = 0; queue < queues_count; queue++) { 5752 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5753 queue); 5754 } 5755 5756 /* PCS link status */ 5757 if (priv->hw->pcs) { 5758 if (priv->xstats.pcs_link) 5759 netif_carrier_on(priv->dev); 5760 else 5761 netif_carrier_off(priv->dev); 5762 } 5763 5764 stmmac_timestamp_interrupt(priv, priv); 5765 } 5766 } 5767 5768 /** 5769 * stmmac_interrupt - main ISR 5770 * @irq: interrupt number. 5771 * @dev_id: to pass the net device pointer. 5772 * Description: this is the main driver interrupt service routine. 5773 * It can call: 5774 * o DMA service routine (to manage incoming frame reception and transmission 5775 * status) 5776 * o Core interrupts to manage: remote wake-up, management counter, LPI 5777 * interrupts. 5778 */ 5779 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5780 { 5781 struct net_device *dev = (struct net_device *)dev_id; 5782 struct stmmac_priv *priv = netdev_priv(dev); 5783 5784 /* Check if adapter is up */ 5785 if (test_bit(STMMAC_DOWN, &priv->state)) 5786 return IRQ_HANDLED; 5787 5788 /* Check if a fatal error happened */ 5789 if (stmmac_safety_feat_interrupt(priv)) 5790 return IRQ_HANDLED; 5791 5792 /* To handle Common interrupts */ 5793 stmmac_common_interrupt(priv); 5794 5795 /* To handle DMA interrupts */ 5796 stmmac_dma_interrupt(priv); 5797 5798 return IRQ_HANDLED; 5799 } 5800 5801 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5802 { 5803 struct net_device *dev = (struct net_device *)dev_id; 5804 struct stmmac_priv *priv = netdev_priv(dev); 5805 5806 if (unlikely(!dev)) { 5807 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5808 return IRQ_NONE; 5809 } 5810 5811 /* Check if adapter is up */ 5812 if (test_bit(STMMAC_DOWN, &priv->state)) 5813 return IRQ_HANDLED; 5814 5815 /* To handle Common interrupts */ 5816 stmmac_common_interrupt(priv); 5817 5818 return IRQ_HANDLED; 5819 } 5820 5821 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5822 { 5823 struct net_device *dev = (struct net_device *)dev_id; 5824 struct stmmac_priv *priv = netdev_priv(dev); 5825 5826 if (unlikely(!dev)) { 5827 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5828 return IRQ_NONE; 5829 } 5830 5831 /* Check if adapter is up */ 5832 if (test_bit(STMMAC_DOWN, &priv->state)) 5833 return IRQ_HANDLED; 5834 5835 /* Check if a fatal error happened */ 5836 stmmac_safety_feat_interrupt(priv); 5837 5838 return IRQ_HANDLED; 5839 } 5840 5841 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5842 { 5843 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5844 struct stmmac_dma_conf *dma_conf; 5845 int chan = tx_q->queue_index; 5846 struct stmmac_priv *priv; 5847 int status; 5848 5849 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5850 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5851 5852 if (unlikely(!data)) { 5853 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5854 return IRQ_NONE; 5855 } 5856 5857 /* Check if adapter is up */ 5858 if (test_bit(STMMAC_DOWN, &priv->state)) 5859 return IRQ_HANDLED; 5860 5861 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5862 5863 if (unlikely(status & tx_hard_error_bump_tc)) { 5864 /* Try to bump up the dma threshold on this failure */ 5865 stmmac_bump_dma_threshold(priv, chan); 5866 } else if (unlikely(status == tx_hard_error)) { 5867 stmmac_tx_err(priv, chan); 5868 } 5869 5870 return IRQ_HANDLED; 5871 } 5872 5873 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5874 { 5875 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5876 struct stmmac_dma_conf *dma_conf; 5877 int chan = rx_q->queue_index; 5878 struct stmmac_priv *priv; 5879 5880 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5881 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5882 5883 if (unlikely(!data)) { 5884 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5885 return IRQ_NONE; 5886 } 5887 5888 /* Check if adapter is up */ 5889 if (test_bit(STMMAC_DOWN, &priv->state)) 5890 return IRQ_HANDLED; 5891 5892 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5893 5894 return IRQ_HANDLED; 5895 } 5896 5897 #ifdef CONFIG_NET_POLL_CONTROLLER 5898 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5899 * to allow network I/O with interrupts disabled. 5900 */ 5901 static void stmmac_poll_controller(struct net_device *dev) 5902 { 5903 struct stmmac_priv *priv = netdev_priv(dev); 5904 int i; 5905 5906 /* If adapter is down, do nothing */ 5907 if (test_bit(STMMAC_DOWN, &priv->state)) 5908 return; 5909 5910 if (priv->plat->multi_msi_en) { 5911 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5912 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5913 5914 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5915 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5916 } else { 5917 disable_irq(dev->irq); 5918 stmmac_interrupt(dev->irq, dev); 5919 enable_irq(dev->irq); 5920 } 5921 } 5922 #endif 5923 5924 /** 5925 * stmmac_ioctl - Entry point for the Ioctl 5926 * @dev: Device pointer. 5927 * @rq: An IOCTL specefic structure, that can contain a pointer to 5928 * a proprietary structure used to pass information to the driver. 5929 * @cmd: IOCTL command 5930 * Description: 5931 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5932 */ 5933 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5934 { 5935 struct stmmac_priv *priv = netdev_priv (dev); 5936 int ret = -EOPNOTSUPP; 5937 5938 if (!netif_running(dev)) 5939 return -EINVAL; 5940 5941 switch (cmd) { 5942 case SIOCGMIIPHY: 5943 case SIOCGMIIREG: 5944 case SIOCSMIIREG: 5945 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5946 break; 5947 case SIOCSHWTSTAMP: 5948 ret = stmmac_hwtstamp_set(dev, rq); 5949 break; 5950 case SIOCGHWTSTAMP: 5951 ret = stmmac_hwtstamp_get(dev, rq); 5952 break; 5953 default: 5954 break; 5955 } 5956 5957 return ret; 5958 } 5959 5960 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5961 void *cb_priv) 5962 { 5963 struct stmmac_priv *priv = cb_priv; 5964 int ret = -EOPNOTSUPP; 5965 5966 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5967 return ret; 5968 5969 __stmmac_disable_all_queues(priv); 5970 5971 switch (type) { 5972 case TC_SETUP_CLSU32: 5973 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5974 break; 5975 case TC_SETUP_CLSFLOWER: 5976 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5977 break; 5978 default: 5979 break; 5980 } 5981 5982 stmmac_enable_all_queues(priv); 5983 return ret; 5984 } 5985 5986 static LIST_HEAD(stmmac_block_cb_list); 5987 5988 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5989 void *type_data) 5990 { 5991 struct stmmac_priv *priv = netdev_priv(ndev); 5992 5993 switch (type) { 5994 case TC_SETUP_BLOCK: 5995 return flow_block_cb_setup_simple(type_data, 5996 &stmmac_block_cb_list, 5997 stmmac_setup_tc_block_cb, 5998 priv, priv, true); 5999 case TC_SETUP_QDISC_CBS: 6000 return stmmac_tc_setup_cbs(priv, priv, type_data); 6001 case TC_SETUP_QDISC_TAPRIO: 6002 return stmmac_tc_setup_taprio(priv, priv, type_data); 6003 case TC_SETUP_QDISC_ETF: 6004 return stmmac_tc_setup_etf(priv, priv, type_data); 6005 default: 6006 return -EOPNOTSUPP; 6007 } 6008 } 6009 6010 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6011 struct net_device *sb_dev) 6012 { 6013 int gso = skb_shinfo(skb)->gso_type; 6014 6015 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6016 /* 6017 * There is no way to determine the number of TSO/USO 6018 * capable Queues. Let's use always the Queue 0 6019 * because if TSO/USO is supported then at least this 6020 * one will be capable. 6021 */ 6022 return 0; 6023 } 6024 6025 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6026 } 6027 6028 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6029 { 6030 struct stmmac_priv *priv = netdev_priv(ndev); 6031 int ret = 0; 6032 6033 ret = pm_runtime_resume_and_get(priv->device); 6034 if (ret < 0) 6035 return ret; 6036 6037 ret = eth_mac_addr(ndev, addr); 6038 if (ret) 6039 goto set_mac_error; 6040 6041 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6042 6043 set_mac_error: 6044 pm_runtime_put(priv->device); 6045 6046 return ret; 6047 } 6048 6049 #ifdef CONFIG_DEBUG_FS 6050 static struct dentry *stmmac_fs_dir; 6051 6052 static void sysfs_display_ring(void *head, int size, int extend_desc, 6053 struct seq_file *seq, dma_addr_t dma_phy_addr) 6054 { 6055 int i; 6056 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6057 struct dma_desc *p = (struct dma_desc *)head; 6058 dma_addr_t dma_addr; 6059 6060 for (i = 0; i < size; i++) { 6061 if (extend_desc) { 6062 dma_addr = dma_phy_addr + i * sizeof(*ep); 6063 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6064 i, &dma_addr, 6065 le32_to_cpu(ep->basic.des0), 6066 le32_to_cpu(ep->basic.des1), 6067 le32_to_cpu(ep->basic.des2), 6068 le32_to_cpu(ep->basic.des3)); 6069 ep++; 6070 } else { 6071 dma_addr = dma_phy_addr + i * sizeof(*p); 6072 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6073 i, &dma_addr, 6074 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6075 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6076 p++; 6077 } 6078 seq_printf(seq, "\n"); 6079 } 6080 } 6081 6082 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6083 { 6084 struct net_device *dev = seq->private; 6085 struct stmmac_priv *priv = netdev_priv(dev); 6086 u32 rx_count = priv->plat->rx_queues_to_use; 6087 u32 tx_count = priv->plat->tx_queues_to_use; 6088 u32 queue; 6089 6090 if ((dev->flags & IFF_UP) == 0) 6091 return 0; 6092 6093 for (queue = 0; queue < rx_count; queue++) { 6094 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6095 6096 seq_printf(seq, "RX Queue %d:\n", queue); 6097 6098 if (priv->extend_desc) { 6099 seq_printf(seq, "Extended descriptor ring:\n"); 6100 sysfs_display_ring((void *)rx_q->dma_erx, 6101 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6102 } else { 6103 seq_printf(seq, "Descriptor ring:\n"); 6104 sysfs_display_ring((void *)rx_q->dma_rx, 6105 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6106 } 6107 } 6108 6109 for (queue = 0; queue < tx_count; queue++) { 6110 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6111 6112 seq_printf(seq, "TX Queue %d:\n", queue); 6113 6114 if (priv->extend_desc) { 6115 seq_printf(seq, "Extended descriptor ring:\n"); 6116 sysfs_display_ring((void *)tx_q->dma_etx, 6117 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6118 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6119 seq_printf(seq, "Descriptor ring:\n"); 6120 sysfs_display_ring((void *)tx_q->dma_tx, 6121 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6122 } 6123 } 6124 6125 return 0; 6126 } 6127 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6128 6129 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6130 { 6131 struct net_device *dev = seq->private; 6132 struct stmmac_priv *priv = netdev_priv(dev); 6133 6134 if (!priv->hw_cap_support) { 6135 seq_printf(seq, "DMA HW features not supported\n"); 6136 return 0; 6137 } 6138 6139 seq_printf(seq, "==============================\n"); 6140 seq_printf(seq, "\tDMA HW features\n"); 6141 seq_printf(seq, "==============================\n"); 6142 6143 seq_printf(seq, "\t10/100 Mbps: %s\n", 6144 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6145 seq_printf(seq, "\t1000 Mbps: %s\n", 6146 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6147 seq_printf(seq, "\tHalf duplex: %s\n", 6148 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6149 seq_printf(seq, "\tHash Filter: %s\n", 6150 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6151 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6152 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6153 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6154 (priv->dma_cap.pcs) ? "Y" : "N"); 6155 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6156 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6157 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6158 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6159 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6160 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6161 seq_printf(seq, "\tRMON module: %s\n", 6162 (priv->dma_cap.rmon) ? "Y" : "N"); 6163 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6164 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6165 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6166 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6167 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6168 (priv->dma_cap.eee) ? "Y" : "N"); 6169 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6170 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6171 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6172 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6173 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6174 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6175 } else { 6176 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6177 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6178 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6179 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6180 } 6181 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6182 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6183 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6184 priv->dma_cap.number_rx_channel); 6185 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6186 priv->dma_cap.number_tx_channel); 6187 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6188 priv->dma_cap.number_rx_queues); 6189 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6190 priv->dma_cap.number_tx_queues); 6191 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6192 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6193 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6194 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6195 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6196 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6197 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6198 priv->dma_cap.pps_out_num); 6199 seq_printf(seq, "\tSafety Features: %s\n", 6200 priv->dma_cap.asp ? "Y" : "N"); 6201 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6202 priv->dma_cap.frpsel ? "Y" : "N"); 6203 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6204 priv->dma_cap.addr64); 6205 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6206 priv->dma_cap.rssen ? "Y" : "N"); 6207 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6208 priv->dma_cap.vlhash ? "Y" : "N"); 6209 seq_printf(seq, "\tSplit Header: %s\n", 6210 priv->dma_cap.sphen ? "Y" : "N"); 6211 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6212 priv->dma_cap.vlins ? "Y" : "N"); 6213 seq_printf(seq, "\tDouble VLAN: %s\n", 6214 priv->dma_cap.dvlan ? "Y" : "N"); 6215 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6216 priv->dma_cap.l3l4fnum); 6217 seq_printf(seq, "\tARP Offloading: %s\n", 6218 priv->dma_cap.arpoffsel ? "Y" : "N"); 6219 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6220 priv->dma_cap.estsel ? "Y" : "N"); 6221 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6222 priv->dma_cap.fpesel ? "Y" : "N"); 6223 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6224 priv->dma_cap.tbssel ? "Y" : "N"); 6225 return 0; 6226 } 6227 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6228 6229 /* Use network device events to rename debugfs file entries. 6230 */ 6231 static int stmmac_device_event(struct notifier_block *unused, 6232 unsigned long event, void *ptr) 6233 { 6234 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6235 struct stmmac_priv *priv = netdev_priv(dev); 6236 6237 if (dev->netdev_ops != &stmmac_netdev_ops) 6238 goto done; 6239 6240 switch (event) { 6241 case NETDEV_CHANGENAME: 6242 if (priv->dbgfs_dir) 6243 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6244 priv->dbgfs_dir, 6245 stmmac_fs_dir, 6246 dev->name); 6247 break; 6248 } 6249 done: 6250 return NOTIFY_DONE; 6251 } 6252 6253 static struct notifier_block stmmac_notifier = { 6254 .notifier_call = stmmac_device_event, 6255 }; 6256 6257 static void stmmac_init_fs(struct net_device *dev) 6258 { 6259 struct stmmac_priv *priv = netdev_priv(dev); 6260 6261 rtnl_lock(); 6262 6263 /* Create per netdev entries */ 6264 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6265 6266 /* Entry to report DMA RX/TX rings */ 6267 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6268 &stmmac_rings_status_fops); 6269 6270 /* Entry to report the DMA HW features */ 6271 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6272 &stmmac_dma_cap_fops); 6273 6274 rtnl_unlock(); 6275 } 6276 6277 static void stmmac_exit_fs(struct net_device *dev) 6278 { 6279 struct stmmac_priv *priv = netdev_priv(dev); 6280 6281 debugfs_remove_recursive(priv->dbgfs_dir); 6282 } 6283 #endif /* CONFIG_DEBUG_FS */ 6284 6285 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6286 { 6287 unsigned char *data = (unsigned char *)&vid_le; 6288 unsigned char data_byte = 0; 6289 u32 crc = ~0x0; 6290 u32 temp = 0; 6291 int i, bits; 6292 6293 bits = get_bitmask_order(VLAN_VID_MASK); 6294 for (i = 0; i < bits; i++) { 6295 if ((i % 8) == 0) 6296 data_byte = data[i / 8]; 6297 6298 temp = ((crc & 1) ^ data_byte) & 1; 6299 crc >>= 1; 6300 data_byte >>= 1; 6301 6302 if (temp) 6303 crc ^= 0xedb88320; 6304 } 6305 6306 return crc; 6307 } 6308 6309 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6310 { 6311 u32 crc, hash = 0; 6312 __le16 pmatch = 0; 6313 int count = 0; 6314 u16 vid = 0; 6315 6316 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6317 __le16 vid_le = cpu_to_le16(vid); 6318 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6319 hash |= (1 << crc); 6320 count++; 6321 } 6322 6323 if (!priv->dma_cap.vlhash) { 6324 if (count > 2) /* VID = 0 always passes filter */ 6325 return -EOPNOTSUPP; 6326 6327 pmatch = cpu_to_le16(vid); 6328 hash = 0; 6329 } 6330 6331 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6332 } 6333 6334 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6335 { 6336 struct stmmac_priv *priv = netdev_priv(ndev); 6337 bool is_double = false; 6338 int ret; 6339 6340 if (be16_to_cpu(proto) == ETH_P_8021AD) 6341 is_double = true; 6342 6343 set_bit(vid, priv->active_vlans); 6344 ret = stmmac_vlan_update(priv, is_double); 6345 if (ret) { 6346 clear_bit(vid, priv->active_vlans); 6347 return ret; 6348 } 6349 6350 if (priv->hw->num_vlan) { 6351 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6352 if (ret) 6353 return ret; 6354 } 6355 6356 return 0; 6357 } 6358 6359 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6360 { 6361 struct stmmac_priv *priv = netdev_priv(ndev); 6362 bool is_double = false; 6363 int ret; 6364 6365 ret = pm_runtime_resume_and_get(priv->device); 6366 if (ret < 0) 6367 return ret; 6368 6369 if (be16_to_cpu(proto) == ETH_P_8021AD) 6370 is_double = true; 6371 6372 clear_bit(vid, priv->active_vlans); 6373 6374 if (priv->hw->num_vlan) { 6375 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6376 if (ret) 6377 goto del_vlan_error; 6378 } 6379 6380 ret = stmmac_vlan_update(priv, is_double); 6381 6382 del_vlan_error: 6383 pm_runtime_put(priv->device); 6384 6385 return ret; 6386 } 6387 6388 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6389 { 6390 struct stmmac_priv *priv = netdev_priv(dev); 6391 6392 switch (bpf->command) { 6393 case XDP_SETUP_PROG: 6394 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6395 case XDP_SETUP_XSK_POOL: 6396 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6397 bpf->xsk.queue_id); 6398 default: 6399 return -EOPNOTSUPP; 6400 } 6401 } 6402 6403 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6404 struct xdp_frame **frames, u32 flags) 6405 { 6406 struct stmmac_priv *priv = netdev_priv(dev); 6407 int cpu = smp_processor_id(); 6408 struct netdev_queue *nq; 6409 int i, nxmit = 0; 6410 int queue; 6411 6412 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6413 return -ENETDOWN; 6414 6415 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6416 return -EINVAL; 6417 6418 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6419 nq = netdev_get_tx_queue(priv->dev, queue); 6420 6421 __netif_tx_lock(nq, cpu); 6422 /* Avoids TX time-out as we are sharing with slow path */ 6423 txq_trans_cond_update(nq); 6424 6425 for (i = 0; i < num_frames; i++) { 6426 int res; 6427 6428 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6429 if (res == STMMAC_XDP_CONSUMED) 6430 break; 6431 6432 nxmit++; 6433 } 6434 6435 if (flags & XDP_XMIT_FLUSH) { 6436 stmmac_flush_tx_descriptors(priv, queue); 6437 stmmac_tx_timer_arm(priv, queue); 6438 } 6439 6440 __netif_tx_unlock(nq); 6441 6442 return nxmit; 6443 } 6444 6445 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6446 { 6447 struct stmmac_channel *ch = &priv->channel[queue]; 6448 unsigned long flags; 6449 6450 spin_lock_irqsave(&ch->lock, flags); 6451 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6452 spin_unlock_irqrestore(&ch->lock, flags); 6453 6454 stmmac_stop_rx_dma(priv, queue); 6455 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6456 } 6457 6458 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6459 { 6460 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6461 struct stmmac_channel *ch = &priv->channel[queue]; 6462 unsigned long flags; 6463 u32 buf_size; 6464 int ret; 6465 6466 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6467 if (ret) { 6468 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6469 return; 6470 } 6471 6472 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6473 if (ret) { 6474 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6475 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6476 return; 6477 } 6478 6479 stmmac_reset_rx_queue(priv, queue); 6480 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6481 6482 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6483 rx_q->dma_rx_phy, rx_q->queue_index); 6484 6485 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6486 sizeof(struct dma_desc)); 6487 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6488 rx_q->rx_tail_addr, rx_q->queue_index); 6489 6490 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6491 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6492 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6493 buf_size, 6494 rx_q->queue_index); 6495 } else { 6496 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6497 priv->dma_conf.dma_buf_sz, 6498 rx_q->queue_index); 6499 } 6500 6501 stmmac_start_rx_dma(priv, queue); 6502 6503 spin_lock_irqsave(&ch->lock, flags); 6504 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6505 spin_unlock_irqrestore(&ch->lock, flags); 6506 } 6507 6508 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6509 { 6510 struct stmmac_channel *ch = &priv->channel[queue]; 6511 unsigned long flags; 6512 6513 spin_lock_irqsave(&ch->lock, flags); 6514 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6515 spin_unlock_irqrestore(&ch->lock, flags); 6516 6517 stmmac_stop_tx_dma(priv, queue); 6518 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6519 } 6520 6521 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6522 { 6523 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6524 struct stmmac_channel *ch = &priv->channel[queue]; 6525 unsigned long flags; 6526 int ret; 6527 6528 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6529 if (ret) { 6530 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6531 return; 6532 } 6533 6534 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6535 if (ret) { 6536 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6537 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6538 return; 6539 } 6540 6541 stmmac_reset_tx_queue(priv, queue); 6542 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6543 6544 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6545 tx_q->dma_tx_phy, tx_q->queue_index); 6546 6547 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6548 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6549 6550 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6551 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6552 tx_q->tx_tail_addr, tx_q->queue_index); 6553 6554 stmmac_start_tx_dma(priv, queue); 6555 6556 spin_lock_irqsave(&ch->lock, flags); 6557 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6558 spin_unlock_irqrestore(&ch->lock, flags); 6559 } 6560 6561 void stmmac_xdp_release(struct net_device *dev) 6562 { 6563 struct stmmac_priv *priv = netdev_priv(dev); 6564 u32 chan; 6565 6566 /* Ensure tx function is not running */ 6567 netif_tx_disable(dev); 6568 6569 /* Disable NAPI process */ 6570 stmmac_disable_all_queues(priv); 6571 6572 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6573 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6574 6575 /* Free the IRQ lines */ 6576 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6577 6578 /* Stop TX/RX DMA channels */ 6579 stmmac_stop_all_dma(priv); 6580 6581 /* Release and free the Rx/Tx resources */ 6582 free_dma_desc_resources(priv, &priv->dma_conf); 6583 6584 /* Disable the MAC Rx/Tx */ 6585 stmmac_mac_set(priv, priv->ioaddr, false); 6586 6587 /* set trans_start so we don't get spurious 6588 * watchdogs during reset 6589 */ 6590 netif_trans_update(dev); 6591 netif_carrier_off(dev); 6592 } 6593 6594 int stmmac_xdp_open(struct net_device *dev) 6595 { 6596 struct stmmac_priv *priv = netdev_priv(dev); 6597 u32 rx_cnt = priv->plat->rx_queues_to_use; 6598 u32 tx_cnt = priv->plat->tx_queues_to_use; 6599 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6600 struct stmmac_rx_queue *rx_q; 6601 struct stmmac_tx_queue *tx_q; 6602 u32 buf_size; 6603 bool sph_en; 6604 u32 chan; 6605 int ret; 6606 6607 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6608 if (ret < 0) { 6609 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6610 __func__); 6611 goto dma_desc_error; 6612 } 6613 6614 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6615 if (ret < 0) { 6616 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6617 __func__); 6618 goto init_error; 6619 } 6620 6621 /* DMA CSR Channel configuration */ 6622 for (chan = 0; chan < dma_csr_ch; chan++) { 6623 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6624 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6625 } 6626 6627 /* Adjust Split header */ 6628 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6629 6630 /* DMA RX Channel Configuration */ 6631 for (chan = 0; chan < rx_cnt; chan++) { 6632 rx_q = &priv->dma_conf.rx_queue[chan]; 6633 6634 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6635 rx_q->dma_rx_phy, chan); 6636 6637 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6638 (rx_q->buf_alloc_num * 6639 sizeof(struct dma_desc)); 6640 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6641 rx_q->rx_tail_addr, chan); 6642 6643 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6644 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6645 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6646 buf_size, 6647 rx_q->queue_index); 6648 } else { 6649 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6650 priv->dma_conf.dma_buf_sz, 6651 rx_q->queue_index); 6652 } 6653 6654 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6655 } 6656 6657 /* DMA TX Channel Configuration */ 6658 for (chan = 0; chan < tx_cnt; chan++) { 6659 tx_q = &priv->dma_conf.tx_queue[chan]; 6660 6661 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6662 tx_q->dma_tx_phy, chan); 6663 6664 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6665 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6666 tx_q->tx_tail_addr, chan); 6667 6668 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6669 tx_q->txtimer.function = stmmac_tx_timer; 6670 } 6671 6672 /* Enable the MAC Rx/Tx */ 6673 stmmac_mac_set(priv, priv->ioaddr, true); 6674 6675 /* Start Rx & Tx DMA Channels */ 6676 stmmac_start_all_dma(priv); 6677 6678 ret = stmmac_request_irq(dev); 6679 if (ret) 6680 goto irq_error; 6681 6682 /* Enable NAPI process*/ 6683 stmmac_enable_all_queues(priv); 6684 netif_carrier_on(dev); 6685 netif_tx_start_all_queues(dev); 6686 stmmac_enable_all_dma_irq(priv); 6687 6688 return 0; 6689 6690 irq_error: 6691 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6692 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6693 6694 stmmac_hw_teardown(dev); 6695 init_error: 6696 free_dma_desc_resources(priv, &priv->dma_conf); 6697 dma_desc_error: 6698 return ret; 6699 } 6700 6701 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6702 { 6703 struct stmmac_priv *priv = netdev_priv(dev); 6704 struct stmmac_rx_queue *rx_q; 6705 struct stmmac_tx_queue *tx_q; 6706 struct stmmac_channel *ch; 6707 6708 if (test_bit(STMMAC_DOWN, &priv->state) || 6709 !netif_carrier_ok(priv->dev)) 6710 return -ENETDOWN; 6711 6712 if (!stmmac_xdp_is_enabled(priv)) 6713 return -EINVAL; 6714 6715 if (queue >= priv->plat->rx_queues_to_use || 6716 queue >= priv->plat->tx_queues_to_use) 6717 return -EINVAL; 6718 6719 rx_q = &priv->dma_conf.rx_queue[queue]; 6720 tx_q = &priv->dma_conf.tx_queue[queue]; 6721 ch = &priv->channel[queue]; 6722 6723 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6724 return -EINVAL; 6725 6726 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6727 /* EQoS does not have per-DMA channel SW interrupt, 6728 * so we schedule RX Napi straight-away. 6729 */ 6730 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6731 __napi_schedule(&ch->rxtx_napi); 6732 } 6733 6734 return 0; 6735 } 6736 6737 static const struct net_device_ops stmmac_netdev_ops = { 6738 .ndo_open = stmmac_open, 6739 .ndo_start_xmit = stmmac_xmit, 6740 .ndo_stop = stmmac_release, 6741 .ndo_change_mtu = stmmac_change_mtu, 6742 .ndo_fix_features = stmmac_fix_features, 6743 .ndo_set_features = stmmac_set_features, 6744 .ndo_set_rx_mode = stmmac_set_rx_mode, 6745 .ndo_tx_timeout = stmmac_tx_timeout, 6746 .ndo_eth_ioctl = stmmac_ioctl, 6747 .ndo_setup_tc = stmmac_setup_tc, 6748 .ndo_select_queue = stmmac_select_queue, 6749 #ifdef CONFIG_NET_POLL_CONTROLLER 6750 .ndo_poll_controller = stmmac_poll_controller, 6751 #endif 6752 .ndo_set_mac_address = stmmac_set_mac_address, 6753 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6754 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6755 .ndo_bpf = stmmac_bpf, 6756 .ndo_xdp_xmit = stmmac_xdp_xmit, 6757 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6758 }; 6759 6760 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6761 { 6762 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6763 return; 6764 if (test_bit(STMMAC_DOWN, &priv->state)) 6765 return; 6766 6767 netdev_err(priv->dev, "Reset adapter.\n"); 6768 6769 rtnl_lock(); 6770 netif_trans_update(priv->dev); 6771 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6772 usleep_range(1000, 2000); 6773 6774 set_bit(STMMAC_DOWN, &priv->state); 6775 dev_close(priv->dev); 6776 dev_open(priv->dev, NULL); 6777 clear_bit(STMMAC_DOWN, &priv->state); 6778 clear_bit(STMMAC_RESETING, &priv->state); 6779 rtnl_unlock(); 6780 } 6781 6782 static void stmmac_service_task(struct work_struct *work) 6783 { 6784 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6785 service_task); 6786 6787 stmmac_reset_subtask(priv); 6788 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6789 } 6790 6791 /** 6792 * stmmac_hw_init - Init the MAC device 6793 * @priv: driver private structure 6794 * Description: this function is to configure the MAC device according to 6795 * some platform parameters or the HW capability register. It prepares the 6796 * driver to use either ring or chain modes and to setup either enhanced or 6797 * normal descriptors. 6798 */ 6799 static int stmmac_hw_init(struct stmmac_priv *priv) 6800 { 6801 int ret; 6802 6803 /* dwmac-sun8i only work in chain mode */ 6804 if (priv->plat->has_sun8i) 6805 chain_mode = 1; 6806 priv->chain_mode = chain_mode; 6807 6808 /* Initialize HW Interface */ 6809 ret = stmmac_hwif_init(priv); 6810 if (ret) 6811 return ret; 6812 6813 /* Get the HW capability (new GMAC newer than 3.50a) */ 6814 priv->hw_cap_support = stmmac_get_hw_features(priv); 6815 if (priv->hw_cap_support) { 6816 dev_info(priv->device, "DMA HW capability register supported\n"); 6817 6818 /* We can override some gmac/dma configuration fields: e.g. 6819 * enh_desc, tx_coe (e.g. that are passed through the 6820 * platform) with the values from the HW capability 6821 * register (if supported). 6822 */ 6823 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6824 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6825 !priv->plat->use_phy_wol; 6826 priv->hw->pmt = priv->plat->pmt; 6827 if (priv->dma_cap.hash_tb_sz) { 6828 priv->hw->multicast_filter_bins = 6829 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6830 priv->hw->mcast_bits_log2 = 6831 ilog2(priv->hw->multicast_filter_bins); 6832 } 6833 6834 /* TXCOE doesn't work in thresh DMA mode */ 6835 if (priv->plat->force_thresh_dma_mode) 6836 priv->plat->tx_coe = 0; 6837 else 6838 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6839 6840 /* In case of GMAC4 rx_coe is from HW cap register. */ 6841 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6842 6843 if (priv->dma_cap.rx_coe_type2) 6844 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6845 else if (priv->dma_cap.rx_coe_type1) 6846 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6847 6848 } else { 6849 dev_info(priv->device, "No HW DMA feature register supported\n"); 6850 } 6851 6852 if (priv->plat->rx_coe) { 6853 priv->hw->rx_csum = priv->plat->rx_coe; 6854 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6855 if (priv->synopsys_id < DWMAC_CORE_4_00) 6856 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6857 } 6858 if (priv->plat->tx_coe) 6859 dev_info(priv->device, "TX Checksum insertion supported\n"); 6860 6861 if (priv->plat->pmt) { 6862 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6863 device_set_wakeup_capable(priv->device, 1); 6864 } 6865 6866 if (priv->dma_cap.tsoen) 6867 dev_info(priv->device, "TSO supported\n"); 6868 6869 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6870 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6871 6872 /* Run HW quirks, if any */ 6873 if (priv->hwif_quirks) { 6874 ret = priv->hwif_quirks(priv); 6875 if (ret) 6876 return ret; 6877 } 6878 6879 /* Rx Watchdog is available in the COREs newer than the 3.40. 6880 * In some case, for example on bugged HW this feature 6881 * has to be disable and this can be done by passing the 6882 * riwt_off field from the platform. 6883 */ 6884 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6885 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6886 priv->use_riwt = 1; 6887 dev_info(priv->device, 6888 "Enable RX Mitigation via HW Watchdog Timer\n"); 6889 } 6890 6891 return 0; 6892 } 6893 6894 static void stmmac_napi_add(struct net_device *dev) 6895 { 6896 struct stmmac_priv *priv = netdev_priv(dev); 6897 u32 queue, maxq; 6898 6899 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6900 6901 for (queue = 0; queue < maxq; queue++) { 6902 struct stmmac_channel *ch = &priv->channel[queue]; 6903 6904 ch->priv_data = priv; 6905 ch->index = queue; 6906 spin_lock_init(&ch->lock); 6907 6908 if (queue < priv->plat->rx_queues_to_use) { 6909 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6910 } 6911 if (queue < priv->plat->tx_queues_to_use) { 6912 netif_napi_add_tx(dev, &ch->tx_napi, 6913 stmmac_napi_poll_tx); 6914 } 6915 if (queue < priv->plat->rx_queues_to_use && 6916 queue < priv->plat->tx_queues_to_use) { 6917 netif_napi_add(dev, &ch->rxtx_napi, 6918 stmmac_napi_poll_rxtx); 6919 } 6920 } 6921 } 6922 6923 static void stmmac_napi_del(struct net_device *dev) 6924 { 6925 struct stmmac_priv *priv = netdev_priv(dev); 6926 u32 queue, maxq; 6927 6928 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6929 6930 for (queue = 0; queue < maxq; queue++) { 6931 struct stmmac_channel *ch = &priv->channel[queue]; 6932 6933 if (queue < priv->plat->rx_queues_to_use) 6934 netif_napi_del(&ch->rx_napi); 6935 if (queue < priv->plat->tx_queues_to_use) 6936 netif_napi_del(&ch->tx_napi); 6937 if (queue < priv->plat->rx_queues_to_use && 6938 queue < priv->plat->tx_queues_to_use) { 6939 netif_napi_del(&ch->rxtx_napi); 6940 } 6941 } 6942 } 6943 6944 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6945 { 6946 struct stmmac_priv *priv = netdev_priv(dev); 6947 int ret = 0; 6948 6949 if (netif_running(dev)) 6950 stmmac_release(dev); 6951 6952 stmmac_napi_del(dev); 6953 6954 priv->plat->rx_queues_to_use = rx_cnt; 6955 priv->plat->tx_queues_to_use = tx_cnt; 6956 6957 stmmac_napi_add(dev); 6958 6959 if (netif_running(dev)) 6960 ret = stmmac_open(dev); 6961 6962 return ret; 6963 } 6964 6965 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6966 { 6967 struct stmmac_priv *priv = netdev_priv(dev); 6968 int ret = 0; 6969 6970 if (netif_running(dev)) 6971 stmmac_release(dev); 6972 6973 priv->dma_conf.dma_rx_size = rx_size; 6974 priv->dma_conf.dma_tx_size = tx_size; 6975 6976 if (netif_running(dev)) 6977 ret = stmmac_open(dev); 6978 6979 return ret; 6980 } 6981 6982 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6983 static void stmmac_fpe_lp_task(struct work_struct *work) 6984 { 6985 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6986 fpe_task); 6987 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6988 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6989 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6990 bool *hs_enable = &fpe_cfg->hs_enable; 6991 bool *enable = &fpe_cfg->enable; 6992 int retries = 20; 6993 6994 while (retries-- > 0) { 6995 /* Bail out immediately if FPE handshake is OFF */ 6996 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6997 break; 6998 6999 if (*lo_state == FPE_STATE_ENTERING_ON && 7000 *lp_state == FPE_STATE_ENTERING_ON) { 7001 stmmac_fpe_configure(priv, priv->ioaddr, 7002 priv->plat->tx_queues_to_use, 7003 priv->plat->rx_queues_to_use, 7004 *enable); 7005 7006 netdev_info(priv->dev, "configured FPE\n"); 7007 7008 *lo_state = FPE_STATE_ON; 7009 *lp_state = FPE_STATE_ON; 7010 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7011 break; 7012 } 7013 7014 if ((*lo_state == FPE_STATE_CAPABLE || 7015 *lo_state == FPE_STATE_ENTERING_ON) && 7016 *lp_state != FPE_STATE_ON) { 7017 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7018 *lo_state, *lp_state); 7019 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7020 MPACKET_VERIFY); 7021 } 7022 /* Sleep then retry */ 7023 msleep(500); 7024 } 7025 7026 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7027 } 7028 7029 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7030 { 7031 if (priv->plat->fpe_cfg->hs_enable != enable) { 7032 if (enable) { 7033 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7034 MPACKET_VERIFY); 7035 } else { 7036 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7037 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7038 } 7039 7040 priv->plat->fpe_cfg->hs_enable = enable; 7041 } 7042 } 7043 7044 /** 7045 * stmmac_dvr_probe 7046 * @device: device pointer 7047 * @plat_dat: platform data pointer 7048 * @res: stmmac resource pointer 7049 * Description: this is the main probe function used to 7050 * call the alloc_etherdev, allocate the priv structure. 7051 * Return: 7052 * returns 0 on success, otherwise errno. 7053 */ 7054 int stmmac_dvr_probe(struct device *device, 7055 struct plat_stmmacenet_data *plat_dat, 7056 struct stmmac_resources *res) 7057 { 7058 struct net_device *ndev = NULL; 7059 struct stmmac_priv *priv; 7060 u32 rxq; 7061 int i, ret = 0; 7062 7063 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7064 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7065 if (!ndev) 7066 return -ENOMEM; 7067 7068 SET_NETDEV_DEV(ndev, device); 7069 7070 priv = netdev_priv(ndev); 7071 priv->device = device; 7072 priv->dev = ndev; 7073 7074 stmmac_set_ethtool_ops(ndev); 7075 priv->pause = pause; 7076 priv->plat = plat_dat; 7077 priv->ioaddr = res->addr; 7078 priv->dev->base_addr = (unsigned long)res->addr; 7079 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7080 7081 priv->dev->irq = res->irq; 7082 priv->wol_irq = res->wol_irq; 7083 priv->lpi_irq = res->lpi_irq; 7084 priv->sfty_ce_irq = res->sfty_ce_irq; 7085 priv->sfty_ue_irq = res->sfty_ue_irq; 7086 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7087 priv->rx_irq[i] = res->rx_irq[i]; 7088 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7089 priv->tx_irq[i] = res->tx_irq[i]; 7090 7091 if (!is_zero_ether_addr(res->mac)) 7092 eth_hw_addr_set(priv->dev, res->mac); 7093 7094 dev_set_drvdata(device, priv->dev); 7095 7096 /* Verify driver arguments */ 7097 stmmac_verify_args(); 7098 7099 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7100 if (!priv->af_xdp_zc_qps) 7101 return -ENOMEM; 7102 7103 /* Allocate workqueue */ 7104 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7105 if (!priv->wq) { 7106 dev_err(priv->device, "failed to create workqueue\n"); 7107 ret = -ENOMEM; 7108 goto error_wq_init; 7109 } 7110 7111 INIT_WORK(&priv->service_task, stmmac_service_task); 7112 7113 /* Initialize Link Partner FPE workqueue */ 7114 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7115 7116 /* Override with kernel parameters if supplied XXX CRS XXX 7117 * this needs to have multiple instances 7118 */ 7119 if ((phyaddr >= 0) && (phyaddr <= 31)) 7120 priv->plat->phy_addr = phyaddr; 7121 7122 if (priv->plat->stmmac_rst) { 7123 ret = reset_control_assert(priv->plat->stmmac_rst); 7124 reset_control_deassert(priv->plat->stmmac_rst); 7125 /* Some reset controllers have only reset callback instead of 7126 * assert + deassert callbacks pair. 7127 */ 7128 if (ret == -ENOTSUPP) 7129 reset_control_reset(priv->plat->stmmac_rst); 7130 } 7131 7132 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7133 if (ret == -ENOTSUPP) 7134 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7135 ERR_PTR(ret)); 7136 7137 /* Init MAC and get the capabilities */ 7138 ret = stmmac_hw_init(priv); 7139 if (ret) 7140 goto error_hw_init; 7141 7142 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7143 */ 7144 if (priv->synopsys_id < DWMAC_CORE_5_20) 7145 priv->plat->dma_cfg->dche = false; 7146 7147 stmmac_check_ether_addr(priv); 7148 7149 ndev->netdev_ops = &stmmac_netdev_ops; 7150 7151 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7152 NETIF_F_RXCSUM; 7153 7154 ret = stmmac_tc_init(priv, priv); 7155 if (!ret) { 7156 ndev->hw_features |= NETIF_F_HW_TC; 7157 } 7158 7159 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7160 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7161 if (priv->plat->has_gmac4) 7162 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7163 priv->tso = true; 7164 dev_info(priv->device, "TSO feature enabled\n"); 7165 } 7166 7167 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7168 ndev->hw_features |= NETIF_F_GRO; 7169 priv->sph_cap = true; 7170 priv->sph = priv->sph_cap; 7171 dev_info(priv->device, "SPH feature enabled\n"); 7172 } 7173 7174 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7175 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7176 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7177 * So overwrite dma_cap.addr64 according to HW real design. 7178 */ 7179 if (priv->plat->addr64) 7180 priv->dma_cap.addr64 = priv->plat->addr64; 7181 7182 if (priv->dma_cap.addr64) { 7183 ret = dma_set_mask_and_coherent(device, 7184 DMA_BIT_MASK(priv->dma_cap.addr64)); 7185 if (!ret) { 7186 dev_info(priv->device, "Using %d bits DMA width\n", 7187 priv->dma_cap.addr64); 7188 7189 /* 7190 * If more than 32 bits can be addressed, make sure to 7191 * enable enhanced addressing mode. 7192 */ 7193 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7194 priv->plat->dma_cfg->eame = true; 7195 } else { 7196 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7197 if (ret) { 7198 dev_err(priv->device, "Failed to set DMA Mask\n"); 7199 goto error_hw_init; 7200 } 7201 7202 priv->dma_cap.addr64 = 32; 7203 } 7204 } 7205 7206 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7207 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7208 #ifdef STMMAC_VLAN_TAG_USED 7209 /* Both mac100 and gmac support receive VLAN tag detection */ 7210 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7211 if (priv->dma_cap.vlhash) { 7212 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7213 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7214 } 7215 if (priv->dma_cap.vlins) { 7216 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7217 if (priv->dma_cap.dvlan) 7218 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7219 } 7220 #endif 7221 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7222 7223 /* Initialize RSS */ 7224 rxq = priv->plat->rx_queues_to_use; 7225 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7226 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7227 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7228 7229 if (priv->dma_cap.rssen && priv->plat->rss_en) 7230 ndev->features |= NETIF_F_RXHASH; 7231 7232 /* MTU range: 46 - hw-specific max */ 7233 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7234 if (priv->plat->has_xgmac) 7235 ndev->max_mtu = XGMAC_JUMBO_LEN; 7236 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7237 ndev->max_mtu = JUMBO_LEN; 7238 else 7239 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7240 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7241 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7242 */ 7243 if ((priv->plat->maxmtu < ndev->max_mtu) && 7244 (priv->plat->maxmtu >= ndev->min_mtu)) 7245 ndev->max_mtu = priv->plat->maxmtu; 7246 else if (priv->plat->maxmtu < ndev->min_mtu) 7247 dev_warn(priv->device, 7248 "%s: warning: maxmtu having invalid value (%d)\n", 7249 __func__, priv->plat->maxmtu); 7250 7251 if (flow_ctrl) 7252 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7253 7254 /* Setup channels NAPI */ 7255 stmmac_napi_add(ndev); 7256 7257 mutex_init(&priv->lock); 7258 7259 /* If a specific clk_csr value is passed from the platform 7260 * this means that the CSR Clock Range selection cannot be 7261 * changed at run-time and it is fixed. Viceversa the driver'll try to 7262 * set the MDC clock dynamically according to the csr actual 7263 * clock input. 7264 */ 7265 if (priv->plat->clk_csr >= 0) 7266 priv->clk_csr = priv->plat->clk_csr; 7267 else 7268 stmmac_clk_csr_set(priv); 7269 7270 stmmac_check_pcs_mode(priv); 7271 7272 pm_runtime_get_noresume(device); 7273 pm_runtime_set_active(device); 7274 if (!pm_runtime_enabled(device)) 7275 pm_runtime_enable(device); 7276 7277 if (priv->hw->pcs != STMMAC_PCS_TBI && 7278 priv->hw->pcs != STMMAC_PCS_RTBI) { 7279 /* MDIO bus Registration */ 7280 ret = stmmac_mdio_register(ndev); 7281 if (ret < 0) { 7282 dev_err_probe(priv->device, ret, 7283 "%s: MDIO bus (id: %d) registration failed\n", 7284 __func__, priv->plat->bus_id); 7285 goto error_mdio_register; 7286 } 7287 } 7288 7289 if (priv->plat->speed_mode_2500) 7290 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7291 7292 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7293 ret = stmmac_xpcs_setup(priv->mii); 7294 if (ret) 7295 goto error_xpcs_setup; 7296 } 7297 7298 ret = stmmac_phy_setup(priv); 7299 if (ret) { 7300 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7301 goto error_phy_setup; 7302 } 7303 7304 ret = register_netdev(ndev); 7305 if (ret) { 7306 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7307 __func__, ret); 7308 goto error_netdev_register; 7309 } 7310 7311 #ifdef CONFIG_DEBUG_FS 7312 stmmac_init_fs(ndev); 7313 #endif 7314 7315 if (priv->plat->dump_debug_regs) 7316 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7317 7318 /* Let pm_runtime_put() disable the clocks. 7319 * If CONFIG_PM is not enabled, the clocks will stay powered. 7320 */ 7321 pm_runtime_put(device); 7322 7323 return ret; 7324 7325 error_netdev_register: 7326 phylink_destroy(priv->phylink); 7327 error_xpcs_setup: 7328 error_phy_setup: 7329 if (priv->hw->pcs != STMMAC_PCS_TBI && 7330 priv->hw->pcs != STMMAC_PCS_RTBI) 7331 stmmac_mdio_unregister(ndev); 7332 error_mdio_register: 7333 stmmac_napi_del(ndev); 7334 error_hw_init: 7335 destroy_workqueue(priv->wq); 7336 error_wq_init: 7337 bitmap_free(priv->af_xdp_zc_qps); 7338 7339 return ret; 7340 } 7341 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7342 7343 /** 7344 * stmmac_dvr_remove 7345 * @dev: device pointer 7346 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7347 * changes the link status, releases the DMA descriptor rings. 7348 */ 7349 int stmmac_dvr_remove(struct device *dev) 7350 { 7351 struct net_device *ndev = dev_get_drvdata(dev); 7352 struct stmmac_priv *priv = netdev_priv(ndev); 7353 7354 netdev_info(priv->dev, "%s: removing driver", __func__); 7355 7356 pm_runtime_get_sync(dev); 7357 7358 stmmac_stop_all_dma(priv); 7359 stmmac_mac_set(priv, priv->ioaddr, false); 7360 netif_carrier_off(ndev); 7361 unregister_netdev(ndev); 7362 7363 /* Serdes power down needs to happen after VLAN filter 7364 * is deleted that is triggered by unregister_netdev(). 7365 */ 7366 if (priv->plat->serdes_powerdown) 7367 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7368 7369 #ifdef CONFIG_DEBUG_FS 7370 stmmac_exit_fs(ndev); 7371 #endif 7372 phylink_destroy(priv->phylink); 7373 if (priv->plat->stmmac_rst) 7374 reset_control_assert(priv->plat->stmmac_rst); 7375 reset_control_assert(priv->plat->stmmac_ahb_rst); 7376 if (priv->hw->pcs != STMMAC_PCS_TBI && 7377 priv->hw->pcs != STMMAC_PCS_RTBI) 7378 stmmac_mdio_unregister(ndev); 7379 destroy_workqueue(priv->wq); 7380 mutex_destroy(&priv->lock); 7381 bitmap_free(priv->af_xdp_zc_qps); 7382 7383 pm_runtime_disable(dev); 7384 pm_runtime_put_noidle(dev); 7385 7386 return 0; 7387 } 7388 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7389 7390 /** 7391 * stmmac_suspend - suspend callback 7392 * @dev: device pointer 7393 * Description: this is the function to suspend the device and it is called 7394 * by the platform driver to stop the network queue, release the resources, 7395 * program the PMT register (for WoL), clean and release driver resources. 7396 */ 7397 int stmmac_suspend(struct device *dev) 7398 { 7399 struct net_device *ndev = dev_get_drvdata(dev); 7400 struct stmmac_priv *priv = netdev_priv(ndev); 7401 u32 chan; 7402 7403 if (!ndev || !netif_running(ndev)) 7404 return 0; 7405 7406 mutex_lock(&priv->lock); 7407 7408 netif_device_detach(ndev); 7409 7410 stmmac_disable_all_queues(priv); 7411 7412 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7413 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7414 7415 if (priv->eee_enabled) { 7416 priv->tx_path_in_lpi_mode = false; 7417 del_timer_sync(&priv->eee_ctrl_timer); 7418 } 7419 7420 /* Stop TX/RX DMA */ 7421 stmmac_stop_all_dma(priv); 7422 7423 if (priv->plat->serdes_powerdown) 7424 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7425 7426 /* Enable Power down mode by programming the PMT regs */ 7427 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7428 stmmac_pmt(priv, priv->hw, priv->wolopts); 7429 priv->irq_wake = 1; 7430 } else { 7431 stmmac_mac_set(priv, priv->ioaddr, false); 7432 pinctrl_pm_select_sleep_state(priv->device); 7433 } 7434 7435 mutex_unlock(&priv->lock); 7436 7437 rtnl_lock(); 7438 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7439 phylink_suspend(priv->phylink, true); 7440 } else { 7441 if (device_may_wakeup(priv->device)) 7442 phylink_speed_down(priv->phylink, false); 7443 phylink_suspend(priv->phylink, false); 7444 } 7445 rtnl_unlock(); 7446 7447 if (priv->dma_cap.fpesel) { 7448 /* Disable FPE */ 7449 stmmac_fpe_configure(priv, priv->ioaddr, 7450 priv->plat->tx_queues_to_use, 7451 priv->plat->rx_queues_to_use, false); 7452 7453 stmmac_fpe_handshake(priv, false); 7454 stmmac_fpe_stop_wq(priv); 7455 } 7456 7457 priv->speed = SPEED_UNKNOWN; 7458 return 0; 7459 } 7460 EXPORT_SYMBOL_GPL(stmmac_suspend); 7461 7462 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7463 { 7464 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7465 7466 rx_q->cur_rx = 0; 7467 rx_q->dirty_rx = 0; 7468 } 7469 7470 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7471 { 7472 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7473 7474 tx_q->cur_tx = 0; 7475 tx_q->dirty_tx = 0; 7476 tx_q->mss = 0; 7477 7478 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7479 } 7480 7481 /** 7482 * stmmac_reset_queues_param - reset queue parameters 7483 * @priv: device pointer 7484 */ 7485 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7486 { 7487 u32 rx_cnt = priv->plat->rx_queues_to_use; 7488 u32 tx_cnt = priv->plat->tx_queues_to_use; 7489 u32 queue; 7490 7491 for (queue = 0; queue < rx_cnt; queue++) 7492 stmmac_reset_rx_queue(priv, queue); 7493 7494 for (queue = 0; queue < tx_cnt; queue++) 7495 stmmac_reset_tx_queue(priv, queue); 7496 } 7497 7498 /** 7499 * stmmac_resume - resume callback 7500 * @dev: device pointer 7501 * Description: when resume this function is invoked to setup the DMA and CORE 7502 * in a usable state. 7503 */ 7504 int stmmac_resume(struct device *dev) 7505 { 7506 struct net_device *ndev = dev_get_drvdata(dev); 7507 struct stmmac_priv *priv = netdev_priv(ndev); 7508 int ret; 7509 7510 if (!netif_running(ndev)) 7511 return 0; 7512 7513 /* Power Down bit, into the PM register, is cleared 7514 * automatically as soon as a magic packet or a Wake-up frame 7515 * is received. Anyway, it's better to manually clear 7516 * this bit because it can generate problems while resuming 7517 * from another devices (e.g. serial console). 7518 */ 7519 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7520 mutex_lock(&priv->lock); 7521 stmmac_pmt(priv, priv->hw, 0); 7522 mutex_unlock(&priv->lock); 7523 priv->irq_wake = 0; 7524 } else { 7525 pinctrl_pm_select_default_state(priv->device); 7526 /* reset the phy so that it's ready */ 7527 if (priv->mii) 7528 stmmac_mdio_reset(priv->mii); 7529 } 7530 7531 if (!priv->plat->serdes_up_after_phy_linkup && priv->plat->serdes_powerup) { 7532 ret = priv->plat->serdes_powerup(ndev, 7533 priv->plat->bsp_priv); 7534 7535 if (ret < 0) 7536 return ret; 7537 } 7538 7539 rtnl_lock(); 7540 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7541 phylink_resume(priv->phylink); 7542 } else { 7543 phylink_resume(priv->phylink); 7544 if (device_may_wakeup(priv->device)) 7545 phylink_speed_up(priv->phylink); 7546 } 7547 rtnl_unlock(); 7548 7549 rtnl_lock(); 7550 mutex_lock(&priv->lock); 7551 7552 stmmac_reset_queues_param(priv); 7553 7554 stmmac_free_tx_skbufs(priv); 7555 stmmac_clear_descriptors(priv, &priv->dma_conf); 7556 7557 stmmac_hw_setup(ndev, false); 7558 stmmac_init_coalesce(priv); 7559 stmmac_set_rx_mode(ndev); 7560 7561 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7562 7563 stmmac_enable_all_queues(priv); 7564 stmmac_enable_all_dma_irq(priv); 7565 7566 mutex_unlock(&priv->lock); 7567 rtnl_unlock(); 7568 7569 netif_device_attach(ndev); 7570 7571 return 0; 7572 } 7573 EXPORT_SYMBOL_GPL(stmmac_resume); 7574 7575 #ifndef MODULE 7576 static int __init stmmac_cmdline_opt(char *str) 7577 { 7578 char *opt; 7579 7580 if (!str || !*str) 7581 return 1; 7582 while ((opt = strsep(&str, ",")) != NULL) { 7583 if (!strncmp(opt, "debug:", 6)) { 7584 if (kstrtoint(opt + 6, 0, &debug)) 7585 goto err; 7586 } else if (!strncmp(opt, "phyaddr:", 8)) { 7587 if (kstrtoint(opt + 8, 0, &phyaddr)) 7588 goto err; 7589 } else if (!strncmp(opt, "buf_sz:", 7)) { 7590 if (kstrtoint(opt + 7, 0, &buf_sz)) 7591 goto err; 7592 } else if (!strncmp(opt, "tc:", 3)) { 7593 if (kstrtoint(opt + 3, 0, &tc)) 7594 goto err; 7595 } else if (!strncmp(opt, "watchdog:", 9)) { 7596 if (kstrtoint(opt + 9, 0, &watchdog)) 7597 goto err; 7598 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7599 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7600 goto err; 7601 } else if (!strncmp(opt, "pause:", 6)) { 7602 if (kstrtoint(opt + 6, 0, &pause)) 7603 goto err; 7604 } else if (!strncmp(opt, "eee_timer:", 10)) { 7605 if (kstrtoint(opt + 10, 0, &eee_timer)) 7606 goto err; 7607 } else if (!strncmp(opt, "chain_mode:", 11)) { 7608 if (kstrtoint(opt + 11, 0, &chain_mode)) 7609 goto err; 7610 } 7611 } 7612 return 1; 7613 7614 err: 7615 pr_err("%s: ERROR broken module parameter conversion", __func__); 7616 return 1; 7617 } 7618 7619 __setup("stmmaceth=", stmmac_cmdline_opt); 7620 #endif /* MODULE */ 7621 7622 static int __init stmmac_init(void) 7623 { 7624 #ifdef CONFIG_DEBUG_FS 7625 /* Create debugfs main directory if it doesn't exist yet */ 7626 if (!stmmac_fs_dir) 7627 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7628 register_netdevice_notifier(&stmmac_notifier); 7629 #endif 7630 7631 return 0; 7632 } 7633 7634 static void __exit stmmac_exit(void) 7635 { 7636 #ifdef CONFIG_DEBUG_FS 7637 unregister_netdevice_notifier(&stmmac_notifier); 7638 debugfs_remove_recursive(stmmac_fs_dir); 7639 #endif 7640 } 7641 7642 module_init(stmmac_init) 7643 module_exit(stmmac_exit) 7644 7645 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7646 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7647 MODULE_LICENSE("GPL"); 7648