1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 #include <linux/of_mdio.h> 56 #include "dwmac1000.h" 57 58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 60 61 /* Module parameters */ 62 #define TX_TIMEO 5000 63 static int watchdog = TX_TIMEO; 64 module_param(watchdog, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 66 67 static int debug = -1; 68 module_param(debug, int, S_IRUGO | S_IWUSR); 69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 70 71 static int phyaddr = -1; 72 module_param(phyaddr, int, S_IRUGO); 73 MODULE_PARM_DESC(phyaddr, "Physical device address"); 74 75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 77 78 static int flow_ctrl = FLOW_OFF; 79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 81 82 static int pause = PAUSE_TIME; 83 module_param(pause, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 85 86 #define TC_DEFAULT 64 87 static int tc = TC_DEFAULT; 88 module_param(tc, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(tc, "DMA threshold control value"); 90 91 #define DEFAULT_BUFSIZE 1536 92 static int buf_sz = DEFAULT_BUFSIZE; 93 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 94 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 95 96 #define STMMAC_RX_COPYBREAK 256 97 98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 99 NETIF_MSG_LINK | NETIF_MSG_IFUP | 100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 101 102 #define STMMAC_DEFAULT_LPI_TIMER 1000 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 107 108 /* By default the driver will use the ring mode to manage tx and rx descriptors 109 * but passing this value so user can force to use the chain instead of the ring 110 */ 111 static unsigned int chain_mode; 112 module_param(chain_mode, int, S_IRUGO); 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 114 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 116 117 #ifdef CONFIG_DEBUG_FS 118 static int stmmac_init_fs(struct net_device *dev); 119 static void stmmac_exit_fs(struct net_device *dev); 120 #endif 121 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 123 124 /** 125 * stmmac_verify_args - verify the driver parameters. 126 * Description: it checks the driver parameters and set a default in case of 127 * errors. 128 */ 129 static void stmmac_verify_args(void) 130 { 131 if (unlikely(watchdog < 0)) 132 watchdog = TX_TIMEO; 133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 134 buf_sz = DEFAULT_BUFSIZE; 135 if (unlikely(flow_ctrl > 1)) 136 flow_ctrl = FLOW_AUTO; 137 else if (likely(flow_ctrl < 0)) 138 flow_ctrl = FLOW_OFF; 139 if (unlikely((pause < 0) || (pause > 0xffff))) 140 pause = PAUSE_TIME; 141 if (eee_timer < 0) 142 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 143 } 144 145 /** 146 * stmmac_clk_csr_set - dynamically set the MDC clock 147 * @priv: driver private structure 148 * Description: this is to dynamically set the MDC clock according to the csr 149 * clock input. 150 * Note: 151 * If a specific clk_csr value is passed from the platform 152 * this means that the CSR Clock Range selection cannot be 153 * changed at run-time and it is fixed (as reported in the driver 154 * documentation). Viceversa the driver will try to set the MDC 155 * clock dynamically according to the actual clock input. 156 */ 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 158 { 159 u32 clk_rate; 160 161 clk_rate = clk_get_rate(priv->stmmac_clk); 162 163 /* Platform provided default clk_csr would be assumed valid 164 * for all other cases except for the below mentioned ones. 165 * For values higher than the IEEE 802.3 specified frequency 166 * we can not estimate the proper divider as it is not known 167 * the frequency of clk_csr_i. So we do not change the default 168 * divider. 169 */ 170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 171 if (clk_rate < CSR_F_35M) 172 priv->clk_csr = STMMAC_CSR_20_35M; 173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 174 priv->clk_csr = STMMAC_CSR_35_60M; 175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 176 priv->clk_csr = STMMAC_CSR_60_100M; 177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 178 priv->clk_csr = STMMAC_CSR_100_150M; 179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 180 priv->clk_csr = STMMAC_CSR_150_250M; 181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 182 priv->clk_csr = STMMAC_CSR_250_300M; 183 } 184 } 185 186 static void print_pkt(unsigned char *buf, int len) 187 { 188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 190 } 191 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 193 { 194 unsigned avail; 195 196 if (priv->dirty_tx > priv->cur_tx) 197 avail = priv->dirty_tx - priv->cur_tx - 1; 198 else 199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; 200 201 return avail; 202 } 203 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) 205 { 206 unsigned dirty; 207 208 if (priv->dirty_rx <= priv->cur_rx) 209 dirty = priv->cur_rx - priv->dirty_rx; 210 else 211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; 212 213 return dirty; 214 } 215 216 /** 217 * stmmac_hw_fix_mac_speed - callback for speed selection 218 * @priv: driver private structure 219 * Description: on some platforms (e.g. ST), some HW system configuraton 220 * registers have to be set according to the link speed negotiated. 221 */ 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 223 { 224 struct phy_device *phydev = priv->phydev; 225 226 if (likely(priv->plat->fix_mac_speed)) 227 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 228 } 229 230 /** 231 * stmmac_enable_eee_mode - check and enter in LPI mode 232 * @priv: driver private structure 233 * Description: this function is to verify and enter in LPI mode in case of 234 * EEE. 235 */ 236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 237 { 238 /* Check and enter in LPI mode */ 239 if ((priv->dirty_tx == priv->cur_tx) && 240 (priv->tx_path_in_lpi_mode == false)) 241 priv->hw->mac->set_eee_mode(priv->hw); 242 } 243 244 /** 245 * stmmac_disable_eee_mode - disable and exit from LPI mode 246 * @priv: driver private structure 247 * Description: this function is to exit and disable EEE in case of 248 * LPI state is true. This is called by the xmit. 249 */ 250 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 251 { 252 priv->hw->mac->reset_eee_mode(priv->hw); 253 del_timer_sync(&priv->eee_ctrl_timer); 254 priv->tx_path_in_lpi_mode = false; 255 } 256 257 /** 258 * stmmac_eee_ctrl_timer - EEE TX SW timer. 259 * @arg : data hook 260 * Description: 261 * if there is no data transfer and if we are not in LPI state, 262 * then MAC Transmitter can be moved to LPI state. 263 */ 264 static void stmmac_eee_ctrl_timer(unsigned long arg) 265 { 266 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 267 268 stmmac_enable_eee_mode(priv); 269 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 270 } 271 272 /** 273 * stmmac_eee_init - init EEE 274 * @priv: driver private structure 275 * Description: 276 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 277 * can also manage EEE, this function enable the LPI state and start related 278 * timer. 279 */ 280 bool stmmac_eee_init(struct stmmac_priv *priv) 281 { 282 unsigned long flags; 283 bool ret = false; 284 285 /* Using PCS we cannot dial with the phy registers at this stage 286 * so we do not support extra feature like EEE. 287 */ 288 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 289 (priv->hw->pcs == STMMAC_PCS_TBI) || 290 (priv->hw->pcs == STMMAC_PCS_RTBI)) 291 goto out; 292 293 /* MAC core supports the EEE feature. */ 294 if (priv->dma_cap.eee) { 295 int tx_lpi_timer = priv->tx_lpi_timer; 296 297 /* Check if the PHY supports EEE */ 298 if (phy_init_eee(priv->phydev, 1)) { 299 /* To manage at run-time if the EEE cannot be supported 300 * anymore (for example because the lp caps have been 301 * changed). 302 * In that case the driver disable own timers. 303 */ 304 spin_lock_irqsave(&priv->lock, flags); 305 if (priv->eee_active) { 306 pr_debug("stmmac: disable EEE\n"); 307 del_timer_sync(&priv->eee_ctrl_timer); 308 priv->hw->mac->set_eee_timer(priv->hw, 0, 309 tx_lpi_timer); 310 } 311 priv->eee_active = 0; 312 spin_unlock_irqrestore(&priv->lock, flags); 313 goto out; 314 } 315 /* Activate the EEE and start timers */ 316 spin_lock_irqsave(&priv->lock, flags); 317 if (!priv->eee_active) { 318 priv->eee_active = 1; 319 setup_timer(&priv->eee_ctrl_timer, 320 stmmac_eee_ctrl_timer, 321 (unsigned long)priv); 322 mod_timer(&priv->eee_ctrl_timer, 323 STMMAC_LPI_T(eee_timer)); 324 325 priv->hw->mac->set_eee_timer(priv->hw, 326 STMMAC_DEFAULT_LIT_LS, 327 tx_lpi_timer); 328 } 329 /* Set HW EEE according to the speed */ 330 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); 331 332 ret = true; 333 spin_unlock_irqrestore(&priv->lock, flags); 334 335 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 336 } 337 out: 338 return ret; 339 } 340 341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 342 * @priv: driver private structure 343 * @entry : descriptor index to be used. 344 * @skb : the socket buffer 345 * Description : 346 * This function will read timestamp from the descriptor & pass it to stack. 347 * and also perform some sanity checks. 348 */ 349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 350 unsigned int entry, struct sk_buff *skb) 351 { 352 struct skb_shared_hwtstamps shhwtstamp; 353 u64 ns; 354 void *desc = NULL; 355 356 if (!priv->hwts_tx_en) 357 return; 358 359 /* exit if skb doesn't support hw tstamp */ 360 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 361 return; 362 363 if (priv->adv_ts) 364 desc = (priv->dma_etx + entry); 365 else 366 desc = (priv->dma_tx + entry); 367 368 /* check tx tstamp status */ 369 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 370 return; 371 372 /* get the valid tstamp */ 373 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 374 375 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 376 shhwtstamp.hwtstamp = ns_to_ktime(ns); 377 /* pass tstamp to stack */ 378 skb_tstamp_tx(skb, &shhwtstamp); 379 380 return; 381 } 382 383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 384 * @priv: driver private structure 385 * @entry : descriptor index to be used. 386 * @skb : the socket buffer 387 * Description : 388 * This function will read received packet's timestamp from the descriptor 389 * and pass it to stack. It also perform some sanity checks. 390 */ 391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 392 unsigned int entry, struct sk_buff *skb) 393 { 394 struct skb_shared_hwtstamps *shhwtstamp = NULL; 395 u64 ns; 396 void *desc = NULL; 397 398 if (!priv->hwts_rx_en) 399 return; 400 401 if (priv->adv_ts) 402 desc = (priv->dma_erx + entry); 403 else 404 desc = (priv->dma_rx + entry); 405 406 /* exit if rx tstamp is not valid */ 407 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 408 return; 409 410 /* get valid tstamp */ 411 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 412 shhwtstamp = skb_hwtstamps(skb); 413 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 414 shhwtstamp->hwtstamp = ns_to_ktime(ns); 415 } 416 417 /** 418 * stmmac_hwtstamp_ioctl - control hardware timestamping. 419 * @dev: device pointer. 420 * @ifr: An IOCTL specefic structure, that can contain a pointer to 421 * a proprietary structure used to pass information to the driver. 422 * Description: 423 * This function configures the MAC to enable/disable both outgoing(TX) 424 * and incoming(RX) packets time stamping based on user input. 425 * Return Value: 426 * 0 on success and an appropriate -ve integer on failure. 427 */ 428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 429 { 430 struct stmmac_priv *priv = netdev_priv(dev); 431 struct hwtstamp_config config; 432 struct timespec64 now; 433 u64 temp = 0; 434 u32 ptp_v2 = 0; 435 u32 tstamp_all = 0; 436 u32 ptp_over_ipv4_udp = 0; 437 u32 ptp_over_ipv6_udp = 0; 438 u32 ptp_over_ethernet = 0; 439 u32 snap_type_sel = 0; 440 u32 ts_master_en = 0; 441 u32 ts_event_en = 0; 442 u32 value = 0; 443 u32 sec_inc; 444 445 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 446 netdev_alert(priv->dev, "No support for HW time stamping\n"); 447 priv->hwts_tx_en = 0; 448 priv->hwts_rx_en = 0; 449 450 return -EOPNOTSUPP; 451 } 452 453 if (copy_from_user(&config, ifr->ifr_data, 454 sizeof(struct hwtstamp_config))) 455 return -EFAULT; 456 457 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 458 __func__, config.flags, config.tx_type, config.rx_filter); 459 460 /* reserved for future extensions */ 461 if (config.flags) 462 return -EINVAL; 463 464 if (config.tx_type != HWTSTAMP_TX_OFF && 465 config.tx_type != HWTSTAMP_TX_ON) 466 return -ERANGE; 467 468 if (priv->adv_ts) { 469 switch (config.rx_filter) { 470 case HWTSTAMP_FILTER_NONE: 471 /* time stamp no incoming packet at all */ 472 config.rx_filter = HWTSTAMP_FILTER_NONE; 473 break; 474 475 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 476 /* PTP v1, UDP, any kind of event packet */ 477 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 478 /* take time stamp for all event messages */ 479 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 480 481 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 482 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 483 break; 484 485 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 486 /* PTP v1, UDP, Sync packet */ 487 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 488 /* take time stamp for SYNC messages only */ 489 ts_event_en = PTP_TCR_TSEVNTENA; 490 491 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 492 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 493 break; 494 495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 496 /* PTP v1, UDP, Delay_req packet */ 497 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 498 /* take time stamp for Delay_Req messages only */ 499 ts_master_en = PTP_TCR_TSMSTRENA; 500 ts_event_en = PTP_TCR_TSEVNTENA; 501 502 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 503 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 504 break; 505 506 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 507 /* PTP v2, UDP, any kind of event packet */ 508 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 509 ptp_v2 = PTP_TCR_TSVER2ENA; 510 /* take time stamp for all event messages */ 511 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 512 513 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 514 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 515 break; 516 517 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 518 /* PTP v2, UDP, Sync packet */ 519 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 520 ptp_v2 = PTP_TCR_TSVER2ENA; 521 /* take time stamp for SYNC messages only */ 522 ts_event_en = PTP_TCR_TSEVNTENA; 523 524 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 525 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 526 break; 527 528 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 529 /* PTP v2, UDP, Delay_req packet */ 530 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 531 ptp_v2 = PTP_TCR_TSVER2ENA; 532 /* take time stamp for Delay_Req messages only */ 533 ts_master_en = PTP_TCR_TSMSTRENA; 534 ts_event_en = PTP_TCR_TSEVNTENA; 535 536 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 537 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 538 break; 539 540 case HWTSTAMP_FILTER_PTP_V2_EVENT: 541 /* PTP v2/802.AS1 any layer, any kind of event packet */ 542 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 543 ptp_v2 = PTP_TCR_TSVER2ENA; 544 /* take time stamp for all event messages */ 545 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 546 547 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 548 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 549 ptp_over_ethernet = PTP_TCR_TSIPENA; 550 break; 551 552 case HWTSTAMP_FILTER_PTP_V2_SYNC: 553 /* PTP v2/802.AS1, any layer, Sync packet */ 554 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 555 ptp_v2 = PTP_TCR_TSVER2ENA; 556 /* take time stamp for SYNC messages only */ 557 ts_event_en = PTP_TCR_TSEVNTENA; 558 559 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 560 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 561 ptp_over_ethernet = PTP_TCR_TSIPENA; 562 break; 563 564 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 565 /* PTP v2/802.AS1, any layer, Delay_req packet */ 566 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 567 ptp_v2 = PTP_TCR_TSVER2ENA; 568 /* take time stamp for Delay_Req messages only */ 569 ts_master_en = PTP_TCR_TSMSTRENA; 570 ts_event_en = PTP_TCR_TSEVNTENA; 571 572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 574 ptp_over_ethernet = PTP_TCR_TSIPENA; 575 break; 576 577 case HWTSTAMP_FILTER_ALL: 578 /* time stamp any incoming packet */ 579 config.rx_filter = HWTSTAMP_FILTER_ALL; 580 tstamp_all = PTP_TCR_TSENALL; 581 break; 582 583 default: 584 return -ERANGE; 585 } 586 } else { 587 switch (config.rx_filter) { 588 case HWTSTAMP_FILTER_NONE: 589 config.rx_filter = HWTSTAMP_FILTER_NONE; 590 break; 591 default: 592 /* PTP v1, UDP, any kind of event packet */ 593 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 594 break; 595 } 596 } 597 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 598 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 599 600 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 602 else { 603 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 604 tstamp_all | ptp_v2 | ptp_over_ethernet | 605 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 606 ts_master_en | snap_type_sel); 607 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 608 609 /* program Sub Second Increment reg */ 610 sec_inc = priv->hw->ptp->config_sub_second_increment( 611 priv->ioaddr, priv->clk_ptp_rate); 612 temp = div_u64(1000000000ULL, sec_inc); 613 614 /* calculate default added value: 615 * formula is : 616 * addend = (2^32)/freq_div_ratio; 617 * where, freq_div_ratio = 1e9ns/sec_inc 618 */ 619 temp = (u64)(temp << 32); 620 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 621 priv->hw->ptp->config_addend(priv->ioaddr, 622 priv->default_addend); 623 624 /* initialize system time */ 625 ktime_get_real_ts64(&now); 626 627 /* lower 32 bits of tv_sec are safe until y2106 */ 628 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec, 629 now.tv_nsec); 630 } 631 632 return copy_to_user(ifr->ifr_data, &config, 633 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 634 } 635 636 /** 637 * stmmac_init_ptp - init PTP 638 * @priv: driver private structure 639 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 640 * This is done by looking at the HW cap. register. 641 * This function also registers the ptp driver. 642 */ 643 static int stmmac_init_ptp(struct stmmac_priv *priv) 644 { 645 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 646 return -EOPNOTSUPP; 647 648 /* Fall-back to main clock in case of no PTP ref is passed */ 649 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 650 if (IS_ERR(priv->clk_ptp_ref)) { 651 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 652 priv->clk_ptp_ref = NULL; 653 netdev_dbg(priv->dev, "PTP uses main clock\n"); 654 } else { 655 clk_prepare_enable(priv->clk_ptp_ref); 656 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 657 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); 658 } 659 660 priv->adv_ts = 0; 661 /* Check if adv_ts can be enabled for dwmac 4.x core */ 662 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) 663 priv->adv_ts = 1; 664 /* Dwmac 3.x core with extend_desc can support adv_ts */ 665 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 666 priv->adv_ts = 1; 667 668 if (priv->dma_cap.time_stamp) 669 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 670 671 if (priv->adv_ts) 672 netdev_info(priv->dev, 673 "IEEE 1588-2008 Advanced Timestamp supported\n"); 674 675 priv->hw->ptp = &stmmac_ptp; 676 priv->hwts_tx_en = 0; 677 priv->hwts_rx_en = 0; 678 679 return stmmac_ptp_register(priv); 680 } 681 682 static void stmmac_release_ptp(struct stmmac_priv *priv) 683 { 684 if (priv->clk_ptp_ref) 685 clk_disable_unprepare(priv->clk_ptp_ref); 686 stmmac_ptp_unregister(priv); 687 } 688 689 /** 690 * stmmac_adjust_link - adjusts the link parameters 691 * @dev: net device structure 692 * Description: this is the helper called by the physical abstraction layer 693 * drivers to communicate the phy link status. According the speed and duplex 694 * this driver can invoke registered glue-logic as well. 695 * It also invoke the eee initialization because it could happen when switch 696 * on different networks (that are eee capable). 697 */ 698 static void stmmac_adjust_link(struct net_device *dev) 699 { 700 struct stmmac_priv *priv = netdev_priv(dev); 701 struct phy_device *phydev = priv->phydev; 702 unsigned long flags; 703 int new_state = 0; 704 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 705 706 if (phydev == NULL) 707 return; 708 709 spin_lock_irqsave(&priv->lock, flags); 710 711 if (phydev->link) { 712 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 713 714 /* Now we make sure that we can be in full duplex mode. 715 * If not, we operate in half-duplex mode. */ 716 if (phydev->duplex != priv->oldduplex) { 717 new_state = 1; 718 if (!(phydev->duplex)) 719 ctrl &= ~priv->hw->link.duplex; 720 else 721 ctrl |= priv->hw->link.duplex; 722 priv->oldduplex = phydev->duplex; 723 } 724 /* Flow Control operation */ 725 if (phydev->pause) 726 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 727 fc, pause_time); 728 729 if (phydev->speed != priv->speed) { 730 new_state = 1; 731 switch (phydev->speed) { 732 case 1000: 733 if (likely((priv->plat->has_gmac) || 734 (priv->plat->has_gmac4))) 735 ctrl &= ~priv->hw->link.port; 736 stmmac_hw_fix_mac_speed(priv); 737 break; 738 case 100: 739 case 10: 740 if (likely((priv->plat->has_gmac) || 741 (priv->plat->has_gmac4))) { 742 ctrl |= priv->hw->link.port; 743 if (phydev->speed == SPEED_100) { 744 ctrl |= priv->hw->link.speed; 745 } else { 746 ctrl &= ~(priv->hw->link.speed); 747 } 748 } else { 749 ctrl &= ~priv->hw->link.port; 750 } 751 stmmac_hw_fix_mac_speed(priv); 752 break; 753 default: 754 if (netif_msg_link(priv)) 755 pr_warn("%s: Speed (%d) not 10/100\n", 756 dev->name, phydev->speed); 757 break; 758 } 759 760 priv->speed = phydev->speed; 761 } 762 763 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 764 765 if (!priv->oldlink) { 766 new_state = 1; 767 priv->oldlink = 1; 768 } 769 } else if (priv->oldlink) { 770 new_state = 1; 771 priv->oldlink = 0; 772 priv->speed = 0; 773 priv->oldduplex = -1; 774 } 775 776 if (new_state && netif_msg_link(priv)) 777 phy_print_status(phydev); 778 779 spin_unlock_irqrestore(&priv->lock, flags); 780 781 if (phydev->is_pseudo_fixed_link) 782 /* Stop PHY layer to call the hook to adjust the link in case 783 * of a switch is attached to the stmmac driver. 784 */ 785 phydev->irq = PHY_IGNORE_INTERRUPT; 786 else 787 /* At this stage, init the EEE if supported. 788 * Never called in case of fixed_link. 789 */ 790 priv->eee_enabled = stmmac_eee_init(priv); 791 } 792 793 /** 794 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 795 * @priv: driver private structure 796 * Description: this is to verify if the HW supports the PCS. 797 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 798 * configured for the TBI, RTBI, or SGMII PHY interface. 799 */ 800 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 801 { 802 int interface = priv->plat->interface; 803 804 if (priv->dma_cap.pcs) { 805 if ((interface == PHY_INTERFACE_MODE_RGMII) || 806 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 807 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 808 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 809 pr_debug("STMMAC: PCS RGMII support enable\n"); 810 priv->hw->pcs = STMMAC_PCS_RGMII; 811 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 812 pr_debug("STMMAC: PCS SGMII support enable\n"); 813 priv->hw->pcs = STMMAC_PCS_SGMII; 814 } 815 } 816 } 817 818 /** 819 * stmmac_init_phy - PHY initialization 820 * @dev: net device structure 821 * Description: it initializes the driver's PHY state, and attaches the PHY 822 * to the mac driver. 823 * Return value: 824 * 0 on success 825 */ 826 static int stmmac_init_phy(struct net_device *dev) 827 { 828 struct stmmac_priv *priv = netdev_priv(dev); 829 struct phy_device *phydev; 830 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 831 char bus_id[MII_BUS_ID_SIZE]; 832 int interface = priv->plat->interface; 833 int max_speed = priv->plat->max_speed; 834 priv->oldlink = 0; 835 priv->speed = 0; 836 priv->oldduplex = -1; 837 838 if (priv->plat->phy_node) { 839 phydev = of_phy_connect(dev, priv->plat->phy_node, 840 &stmmac_adjust_link, 0, interface); 841 } else { 842 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 843 priv->plat->bus_id); 844 845 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 846 priv->plat->phy_addr); 847 pr_debug("stmmac_init_phy: trying to attach to %s\n", 848 phy_id_fmt); 849 850 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 851 interface); 852 } 853 854 if (IS_ERR_OR_NULL(phydev)) { 855 pr_err("%s: Could not attach to PHY\n", dev->name); 856 if (!phydev) 857 return -ENODEV; 858 859 return PTR_ERR(phydev); 860 } 861 862 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 863 if ((interface == PHY_INTERFACE_MODE_MII) || 864 (interface == PHY_INTERFACE_MODE_RMII) || 865 (max_speed < 1000 && max_speed > 0)) 866 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 867 SUPPORTED_1000baseT_Full); 868 869 /* 870 * Broken HW is sometimes missing the pull-up resistor on the 871 * MDIO line, which results in reads to non-existent devices returning 872 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 873 * device as well. 874 * Note: phydev->phy_id is the result of reading the UID PHY registers. 875 */ 876 if (!priv->plat->phy_node && phydev->phy_id == 0) { 877 phy_disconnect(phydev); 878 return -ENODEV; 879 } 880 881 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 882 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 883 884 priv->phydev = phydev; 885 886 return 0; 887 } 888 889 static void stmmac_display_rings(struct stmmac_priv *priv) 890 { 891 void *head_rx, *head_tx; 892 893 if (priv->extend_desc) { 894 head_rx = (void *)priv->dma_erx; 895 head_tx = (void *)priv->dma_etx; 896 } else { 897 head_rx = (void *)priv->dma_rx; 898 head_tx = (void *)priv->dma_tx; 899 } 900 901 /* Display Rx ring */ 902 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); 903 /* Display Tx ring */ 904 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); 905 } 906 907 static int stmmac_set_bfsize(int mtu, int bufsize) 908 { 909 int ret = bufsize; 910 911 if (mtu >= BUF_SIZE_4KiB) 912 ret = BUF_SIZE_8KiB; 913 else if (mtu >= BUF_SIZE_2KiB) 914 ret = BUF_SIZE_4KiB; 915 else if (mtu > DEFAULT_BUFSIZE) 916 ret = BUF_SIZE_2KiB; 917 else 918 ret = DEFAULT_BUFSIZE; 919 920 return ret; 921 } 922 923 /** 924 * stmmac_clear_descriptors - clear descriptors 925 * @priv: driver private structure 926 * Description: this function is called to clear the tx and rx descriptors 927 * in case of both basic and extended descriptors are used. 928 */ 929 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 930 { 931 int i; 932 933 /* Clear the Rx/Tx descriptors */ 934 for (i = 0; i < DMA_RX_SIZE; i++) 935 if (priv->extend_desc) 936 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 937 priv->use_riwt, priv->mode, 938 (i == DMA_RX_SIZE - 1)); 939 else 940 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 941 priv->use_riwt, priv->mode, 942 (i == DMA_RX_SIZE - 1)); 943 for (i = 0; i < DMA_TX_SIZE; i++) 944 if (priv->extend_desc) 945 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 946 priv->mode, 947 (i == DMA_TX_SIZE - 1)); 948 else 949 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 950 priv->mode, 951 (i == DMA_TX_SIZE - 1)); 952 } 953 954 /** 955 * stmmac_init_rx_buffers - init the RX descriptor buffer. 956 * @priv: driver private structure 957 * @p: descriptor pointer 958 * @i: descriptor index 959 * @flags: gfp flag. 960 * Description: this function is called to allocate a receive buffer, perform 961 * the DMA mapping and init the descriptor. 962 */ 963 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 964 int i, gfp_t flags) 965 { 966 struct sk_buff *skb; 967 968 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 969 if (!skb) { 970 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 971 return -ENOMEM; 972 } 973 priv->rx_skbuff[i] = skb; 974 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 975 priv->dma_buf_sz, 976 DMA_FROM_DEVICE); 977 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 978 pr_err("%s: DMA mapping error\n", __func__); 979 dev_kfree_skb_any(skb); 980 return -EINVAL; 981 } 982 983 if (priv->synopsys_id >= DWMAC_CORE_4_00) 984 p->des0 = priv->rx_skbuff_dma[i]; 985 else 986 p->des2 = priv->rx_skbuff_dma[i]; 987 988 if ((priv->hw->mode->init_desc3) && 989 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 990 priv->hw->mode->init_desc3(p); 991 992 return 0; 993 } 994 995 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 996 { 997 if (priv->rx_skbuff[i]) { 998 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 999 priv->dma_buf_sz, DMA_FROM_DEVICE); 1000 dev_kfree_skb_any(priv->rx_skbuff[i]); 1001 } 1002 priv->rx_skbuff[i] = NULL; 1003 } 1004 1005 /** 1006 * init_dma_desc_rings - init the RX/TX descriptor rings 1007 * @dev: net device structure 1008 * @flags: gfp flag. 1009 * Description: this function initializes the DMA RX/TX descriptors 1010 * and allocates the socket buffers. It suppors the chained and ring 1011 * modes. 1012 */ 1013 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1014 { 1015 int i; 1016 struct stmmac_priv *priv = netdev_priv(dev); 1017 unsigned int bfsize = 0; 1018 int ret = -ENOMEM; 1019 1020 if (priv->hw->mode->set_16kib_bfsize) 1021 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1022 1023 if (bfsize < BUF_SIZE_16KiB) 1024 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1025 1026 priv->dma_buf_sz = bfsize; 1027 1028 if (netif_msg_probe(priv)) { 1029 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1030 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1031 1032 /* RX INITIALIZATION */ 1033 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1034 } 1035 for (i = 0; i < DMA_RX_SIZE; i++) { 1036 struct dma_desc *p; 1037 if (priv->extend_desc) 1038 p = &((priv->dma_erx + i)->basic); 1039 else 1040 p = priv->dma_rx + i; 1041 1042 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1043 if (ret) 1044 goto err_init_rx_buffers; 1045 1046 if (netif_msg_probe(priv)) 1047 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1048 priv->rx_skbuff[i]->data, 1049 (unsigned int)priv->rx_skbuff_dma[i]); 1050 } 1051 priv->cur_rx = 0; 1052 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1053 buf_sz = bfsize; 1054 1055 /* Setup the chained descriptor addresses */ 1056 if (priv->mode == STMMAC_CHAIN_MODE) { 1057 if (priv->extend_desc) { 1058 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1059 DMA_RX_SIZE, 1); 1060 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1061 DMA_TX_SIZE, 1); 1062 } else { 1063 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1064 DMA_RX_SIZE, 0); 1065 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1066 DMA_TX_SIZE, 0); 1067 } 1068 } 1069 1070 /* TX INITIALIZATION */ 1071 for (i = 0; i < DMA_TX_SIZE; i++) { 1072 struct dma_desc *p; 1073 if (priv->extend_desc) 1074 p = &((priv->dma_etx + i)->basic); 1075 else 1076 p = priv->dma_tx + i; 1077 1078 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1079 p->des0 = 0; 1080 p->des1 = 0; 1081 p->des2 = 0; 1082 p->des3 = 0; 1083 } else { 1084 p->des2 = 0; 1085 } 1086 1087 priv->tx_skbuff_dma[i].buf = 0; 1088 priv->tx_skbuff_dma[i].map_as_page = false; 1089 priv->tx_skbuff_dma[i].len = 0; 1090 priv->tx_skbuff_dma[i].last_segment = false; 1091 priv->tx_skbuff[i] = NULL; 1092 } 1093 1094 priv->dirty_tx = 0; 1095 priv->cur_tx = 0; 1096 netdev_reset_queue(priv->dev); 1097 1098 stmmac_clear_descriptors(priv); 1099 1100 if (netif_msg_hw(priv)) 1101 stmmac_display_rings(priv); 1102 1103 return 0; 1104 err_init_rx_buffers: 1105 while (--i >= 0) 1106 stmmac_free_rx_buffers(priv, i); 1107 return ret; 1108 } 1109 1110 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1111 { 1112 int i; 1113 1114 for (i = 0; i < DMA_RX_SIZE; i++) 1115 stmmac_free_rx_buffers(priv, i); 1116 } 1117 1118 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1119 { 1120 int i; 1121 1122 for (i = 0; i < DMA_TX_SIZE; i++) { 1123 struct dma_desc *p; 1124 1125 if (priv->extend_desc) 1126 p = &((priv->dma_etx + i)->basic); 1127 else 1128 p = priv->dma_tx + i; 1129 1130 if (priv->tx_skbuff_dma[i].buf) { 1131 if (priv->tx_skbuff_dma[i].map_as_page) 1132 dma_unmap_page(priv->device, 1133 priv->tx_skbuff_dma[i].buf, 1134 priv->tx_skbuff_dma[i].len, 1135 DMA_TO_DEVICE); 1136 else 1137 dma_unmap_single(priv->device, 1138 priv->tx_skbuff_dma[i].buf, 1139 priv->tx_skbuff_dma[i].len, 1140 DMA_TO_DEVICE); 1141 } 1142 1143 if (priv->tx_skbuff[i] != NULL) { 1144 dev_kfree_skb_any(priv->tx_skbuff[i]); 1145 priv->tx_skbuff[i] = NULL; 1146 priv->tx_skbuff_dma[i].buf = 0; 1147 priv->tx_skbuff_dma[i].map_as_page = false; 1148 } 1149 } 1150 } 1151 1152 /** 1153 * alloc_dma_desc_resources - alloc TX/RX resources. 1154 * @priv: private structure 1155 * Description: according to which descriptor can be used (extend or basic) 1156 * this function allocates the resources for TX and RX paths. In case of 1157 * reception, for example, it pre-allocated the RX socket buffer in order to 1158 * allow zero-copy mechanism. 1159 */ 1160 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1161 { 1162 int ret = -ENOMEM; 1163 1164 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), 1165 GFP_KERNEL); 1166 if (!priv->rx_skbuff_dma) 1167 return -ENOMEM; 1168 1169 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), 1170 GFP_KERNEL); 1171 if (!priv->rx_skbuff) 1172 goto err_rx_skbuff; 1173 1174 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1175 sizeof(*priv->tx_skbuff_dma), 1176 GFP_KERNEL); 1177 if (!priv->tx_skbuff_dma) 1178 goto err_tx_skbuff_dma; 1179 1180 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), 1181 GFP_KERNEL); 1182 if (!priv->tx_skbuff) 1183 goto err_tx_skbuff; 1184 1185 if (priv->extend_desc) { 1186 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1187 sizeof(struct 1188 dma_extended_desc), 1189 &priv->dma_rx_phy, 1190 GFP_KERNEL); 1191 if (!priv->dma_erx) 1192 goto err_dma; 1193 1194 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1195 sizeof(struct 1196 dma_extended_desc), 1197 &priv->dma_tx_phy, 1198 GFP_KERNEL); 1199 if (!priv->dma_etx) { 1200 dma_free_coherent(priv->device, DMA_RX_SIZE * 1201 sizeof(struct dma_extended_desc), 1202 priv->dma_erx, priv->dma_rx_phy); 1203 goto err_dma; 1204 } 1205 } else { 1206 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * 1207 sizeof(struct dma_desc), 1208 &priv->dma_rx_phy, 1209 GFP_KERNEL); 1210 if (!priv->dma_rx) 1211 goto err_dma; 1212 1213 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * 1214 sizeof(struct dma_desc), 1215 &priv->dma_tx_phy, 1216 GFP_KERNEL); 1217 if (!priv->dma_tx) { 1218 dma_free_coherent(priv->device, DMA_RX_SIZE * 1219 sizeof(struct dma_desc), 1220 priv->dma_rx, priv->dma_rx_phy); 1221 goto err_dma; 1222 } 1223 } 1224 1225 return 0; 1226 1227 err_dma: 1228 kfree(priv->tx_skbuff); 1229 err_tx_skbuff: 1230 kfree(priv->tx_skbuff_dma); 1231 err_tx_skbuff_dma: 1232 kfree(priv->rx_skbuff); 1233 err_rx_skbuff: 1234 kfree(priv->rx_skbuff_dma); 1235 return ret; 1236 } 1237 1238 static void free_dma_desc_resources(struct stmmac_priv *priv) 1239 { 1240 /* Release the DMA TX/RX socket buffers */ 1241 dma_free_rx_skbufs(priv); 1242 dma_free_tx_skbufs(priv); 1243 1244 /* Free DMA regions of consistent memory previously allocated */ 1245 if (!priv->extend_desc) { 1246 dma_free_coherent(priv->device, 1247 DMA_TX_SIZE * sizeof(struct dma_desc), 1248 priv->dma_tx, priv->dma_tx_phy); 1249 dma_free_coherent(priv->device, 1250 DMA_RX_SIZE * sizeof(struct dma_desc), 1251 priv->dma_rx, priv->dma_rx_phy); 1252 } else { 1253 dma_free_coherent(priv->device, DMA_TX_SIZE * 1254 sizeof(struct dma_extended_desc), 1255 priv->dma_etx, priv->dma_tx_phy); 1256 dma_free_coherent(priv->device, DMA_RX_SIZE * 1257 sizeof(struct dma_extended_desc), 1258 priv->dma_erx, priv->dma_rx_phy); 1259 } 1260 kfree(priv->rx_skbuff_dma); 1261 kfree(priv->rx_skbuff); 1262 kfree(priv->tx_skbuff_dma); 1263 kfree(priv->tx_skbuff); 1264 } 1265 1266 /** 1267 * stmmac_dma_operation_mode - HW DMA operation mode 1268 * @priv: driver private structure 1269 * Description: it is used for configuring the DMA operation mode register in 1270 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1271 */ 1272 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1273 { 1274 int rxfifosz = priv->plat->rx_fifo_size; 1275 1276 if (priv->plat->force_thresh_dma_mode) 1277 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); 1278 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1279 /* 1280 * In case of GMAC, SF mode can be enabled 1281 * to perform the TX COE in HW. This depends on: 1282 * 1) TX COE if actually supported 1283 * 2) There is no bugged Jumbo frame support 1284 * that needs to not insert csum in the TDES. 1285 */ 1286 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, 1287 rxfifosz); 1288 priv->xstats.threshold = SF_DMA_MODE; 1289 } else 1290 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, 1291 rxfifosz); 1292 } 1293 1294 /** 1295 * stmmac_tx_clean - to manage the transmission completion 1296 * @priv: driver private structure 1297 * Description: it reclaims the transmit resources after transmission completes. 1298 */ 1299 static void stmmac_tx_clean(struct stmmac_priv *priv) 1300 { 1301 unsigned int bytes_compl = 0, pkts_compl = 0; 1302 unsigned int entry = priv->dirty_tx; 1303 1304 spin_lock(&priv->tx_lock); 1305 1306 priv->xstats.tx_clean++; 1307 1308 while (entry != priv->cur_tx) { 1309 struct sk_buff *skb = priv->tx_skbuff[entry]; 1310 struct dma_desc *p; 1311 int status; 1312 1313 if (priv->extend_desc) 1314 p = (struct dma_desc *)(priv->dma_etx + entry); 1315 else 1316 p = priv->dma_tx + entry; 1317 1318 status = priv->hw->desc->tx_status(&priv->dev->stats, 1319 &priv->xstats, p, 1320 priv->ioaddr); 1321 /* Check if the descriptor is owned by the DMA */ 1322 if (unlikely(status & tx_dma_own)) 1323 break; 1324 1325 /* Just consider the last segment and ...*/ 1326 if (likely(!(status & tx_not_ls))) { 1327 /* ... verify the status error condition */ 1328 if (unlikely(status & tx_err)) { 1329 priv->dev->stats.tx_errors++; 1330 } else { 1331 priv->dev->stats.tx_packets++; 1332 priv->xstats.tx_pkt_n++; 1333 } 1334 stmmac_get_tx_hwtstamp(priv, entry, skb); 1335 } 1336 1337 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1338 if (priv->tx_skbuff_dma[entry].map_as_page) 1339 dma_unmap_page(priv->device, 1340 priv->tx_skbuff_dma[entry].buf, 1341 priv->tx_skbuff_dma[entry].len, 1342 DMA_TO_DEVICE); 1343 else 1344 dma_unmap_single(priv->device, 1345 priv->tx_skbuff_dma[entry].buf, 1346 priv->tx_skbuff_dma[entry].len, 1347 DMA_TO_DEVICE); 1348 priv->tx_skbuff_dma[entry].buf = 0; 1349 priv->tx_skbuff_dma[entry].len = 0; 1350 priv->tx_skbuff_dma[entry].map_as_page = false; 1351 } 1352 1353 if (priv->hw->mode->clean_desc3) 1354 priv->hw->mode->clean_desc3(priv, p); 1355 1356 priv->tx_skbuff_dma[entry].last_segment = false; 1357 priv->tx_skbuff_dma[entry].is_jumbo = false; 1358 1359 if (likely(skb != NULL)) { 1360 pkts_compl++; 1361 bytes_compl += skb->len; 1362 dev_consume_skb_any(skb); 1363 priv->tx_skbuff[entry] = NULL; 1364 } 1365 1366 priv->hw->desc->release_tx_desc(p, priv->mode); 1367 1368 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1369 } 1370 priv->dirty_tx = entry; 1371 1372 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1373 1374 if (unlikely(netif_queue_stopped(priv->dev) && 1375 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { 1376 netif_tx_lock(priv->dev); 1377 if (netif_queue_stopped(priv->dev) && 1378 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) { 1379 if (netif_msg_tx_done(priv)) 1380 pr_debug("%s: restart transmit\n", __func__); 1381 netif_wake_queue(priv->dev); 1382 } 1383 netif_tx_unlock(priv->dev); 1384 } 1385 1386 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1387 stmmac_enable_eee_mode(priv); 1388 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1389 } 1390 spin_unlock(&priv->tx_lock); 1391 } 1392 1393 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1394 { 1395 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1396 } 1397 1398 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1399 { 1400 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1401 } 1402 1403 /** 1404 * stmmac_tx_err - to manage the tx error 1405 * @priv: driver private structure 1406 * Description: it cleans the descriptors and restarts the transmission 1407 * in case of transmission errors. 1408 */ 1409 static void stmmac_tx_err(struct stmmac_priv *priv) 1410 { 1411 int i; 1412 netif_stop_queue(priv->dev); 1413 1414 priv->hw->dma->stop_tx(priv->ioaddr); 1415 dma_free_tx_skbufs(priv); 1416 for (i = 0; i < DMA_TX_SIZE; i++) 1417 if (priv->extend_desc) 1418 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1419 priv->mode, 1420 (i == DMA_TX_SIZE - 1)); 1421 else 1422 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1423 priv->mode, 1424 (i == DMA_TX_SIZE - 1)); 1425 priv->dirty_tx = 0; 1426 priv->cur_tx = 0; 1427 netdev_reset_queue(priv->dev); 1428 priv->hw->dma->start_tx(priv->ioaddr); 1429 1430 priv->dev->stats.tx_errors++; 1431 netif_wake_queue(priv->dev); 1432 } 1433 1434 /** 1435 * stmmac_dma_interrupt - DMA ISR 1436 * @priv: driver private structure 1437 * Description: this is the DMA ISR. It is called by the main ISR. 1438 * It calls the dwmac dma routine and schedule poll method in case of some 1439 * work can be done. 1440 */ 1441 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1442 { 1443 int status; 1444 int rxfifosz = priv->plat->rx_fifo_size; 1445 1446 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1447 if (likely((status & handle_rx)) || (status & handle_tx)) { 1448 if (likely(napi_schedule_prep(&priv->napi))) { 1449 stmmac_disable_dma_irq(priv); 1450 __napi_schedule(&priv->napi); 1451 } 1452 } 1453 if (unlikely(status & tx_hard_error_bump_tc)) { 1454 /* Try to bump up the dma threshold on this failure */ 1455 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1456 (tc <= 256)) { 1457 tc += 64; 1458 if (priv->plat->force_thresh_dma_mode) 1459 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, 1460 rxfifosz); 1461 else 1462 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1463 SF_DMA_MODE, rxfifosz); 1464 priv->xstats.threshold = tc; 1465 } 1466 } else if (unlikely(status == tx_hard_error)) 1467 stmmac_tx_err(priv); 1468 } 1469 1470 /** 1471 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1472 * @priv: driver private structure 1473 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1474 */ 1475 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1476 { 1477 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1478 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1479 1480 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1481 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; 1482 else 1483 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; 1484 1485 dwmac_mmc_intr_all_mask(priv->mmcaddr); 1486 1487 if (priv->dma_cap.rmon) { 1488 dwmac_mmc_ctrl(priv->mmcaddr, mode); 1489 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1490 } else 1491 pr_info(" No MAC Management Counters available\n"); 1492 } 1493 1494 /** 1495 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1496 * @priv: driver private structure 1497 * Description: select the Enhanced/Alternate or Normal descriptors. 1498 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1499 * supported by the HW capability register. 1500 */ 1501 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1502 { 1503 if (priv->plat->enh_desc) { 1504 pr_info(" Enhanced/Alternate descriptors\n"); 1505 1506 /* GMAC older than 3.50 has no extended descriptors */ 1507 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1508 pr_info("\tEnabled extended descriptors\n"); 1509 priv->extend_desc = 1; 1510 } else 1511 pr_warn("Extended descriptors not supported\n"); 1512 1513 priv->hw->desc = &enh_desc_ops; 1514 } else { 1515 pr_info(" Normal descriptors\n"); 1516 priv->hw->desc = &ndesc_ops; 1517 } 1518 } 1519 1520 /** 1521 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1522 * @priv: driver private structure 1523 * Description: 1524 * new GMAC chip generations have a new register to indicate the 1525 * presence of the optional feature/functions. 1526 * This can be also used to override the value passed through the 1527 * platform and necessary for old MAC10/100 and GMAC chips. 1528 */ 1529 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1530 { 1531 u32 ret = 0; 1532 1533 if (priv->hw->dma->get_hw_feature) { 1534 priv->hw->dma->get_hw_feature(priv->ioaddr, 1535 &priv->dma_cap); 1536 ret = 1; 1537 } 1538 1539 return ret; 1540 } 1541 1542 /** 1543 * stmmac_check_ether_addr - check if the MAC addr is valid 1544 * @priv: driver private structure 1545 * Description: 1546 * it is to verify if the MAC address is valid, in case of failures it 1547 * generates a random MAC address 1548 */ 1549 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1550 { 1551 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1552 priv->hw->mac->get_umac_addr(priv->hw, 1553 priv->dev->dev_addr, 0); 1554 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1555 eth_hw_addr_random(priv->dev); 1556 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1557 priv->dev->dev_addr); 1558 } 1559 } 1560 1561 /** 1562 * stmmac_init_dma_engine - DMA init. 1563 * @priv: driver private structure 1564 * Description: 1565 * It inits the DMA invoking the specific MAC/GMAC callback. 1566 * Some DMA parameters can be passed from the platform; 1567 * in case of these are not passed a default is kept for the MAC or GMAC. 1568 */ 1569 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1570 { 1571 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0; 1572 int mixed_burst = 0; 1573 int atds = 0; 1574 int ret = 0; 1575 1576 if (priv->plat->dma_cfg) { 1577 pbl = priv->plat->dma_cfg->pbl; 1578 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1579 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1580 aal = priv->plat->dma_cfg->aal; 1581 } 1582 1583 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1584 atds = 1; 1585 1586 ret = priv->hw->dma->reset(priv->ioaddr); 1587 if (ret) { 1588 dev_err(priv->device, "Failed to reset the dma\n"); 1589 return ret; 1590 } 1591 1592 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1593 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds); 1594 1595 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 1596 priv->rx_tail_addr = priv->dma_rx_phy + 1597 (DMA_RX_SIZE * sizeof(struct dma_desc)); 1598 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, 1599 STMMAC_CHAN0); 1600 1601 priv->tx_tail_addr = priv->dma_tx_phy + 1602 (DMA_TX_SIZE * sizeof(struct dma_desc)); 1603 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 1604 STMMAC_CHAN0); 1605 } 1606 1607 if (priv->plat->axi && priv->hw->dma->axi) 1608 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); 1609 1610 return ret; 1611 } 1612 1613 /** 1614 * stmmac_tx_timer - mitigation sw timer for tx. 1615 * @data: data pointer 1616 * Description: 1617 * This is the timer handler to directly invoke the stmmac_tx_clean. 1618 */ 1619 static void stmmac_tx_timer(unsigned long data) 1620 { 1621 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1622 1623 stmmac_tx_clean(priv); 1624 } 1625 1626 /** 1627 * stmmac_init_tx_coalesce - init tx mitigation options. 1628 * @priv: driver private structure 1629 * Description: 1630 * This inits the transmit coalesce parameters: i.e. timer rate, 1631 * timer handler and default threshold used for enabling the 1632 * interrupt on completion bit. 1633 */ 1634 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1635 { 1636 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1637 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1638 init_timer(&priv->txtimer); 1639 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1640 priv->txtimer.data = (unsigned long)priv; 1641 priv->txtimer.function = stmmac_tx_timer; 1642 add_timer(&priv->txtimer); 1643 } 1644 1645 /** 1646 * stmmac_hw_setup - setup mac in a usable state. 1647 * @dev : pointer to the device structure. 1648 * Description: 1649 * this is the main function to setup the HW in a usable state because the 1650 * dma engine is reset, the core registers are configured (e.g. AXI, 1651 * Checksum features, timers). The DMA is ready to start receiving and 1652 * transmitting. 1653 * Return value: 1654 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1655 * file on failure. 1656 */ 1657 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1658 { 1659 struct stmmac_priv *priv = netdev_priv(dev); 1660 int ret; 1661 1662 /* DMA initialization and SW reset */ 1663 ret = stmmac_init_dma_engine(priv); 1664 if (ret < 0) { 1665 pr_err("%s: DMA engine initialization failed\n", __func__); 1666 return ret; 1667 } 1668 1669 /* Copy the MAC addr into the HW */ 1670 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1671 1672 /* If required, perform hw setup of the bus. */ 1673 if (priv->plat->bus_setup) 1674 priv->plat->bus_setup(priv->ioaddr); 1675 1676 /* PS and related bits will be programmed according to the speed */ 1677 if (priv->hw->pcs) { 1678 int speed = priv->plat->mac_port_sel_speed; 1679 1680 if ((speed == SPEED_10) || (speed == SPEED_100) || 1681 (speed == SPEED_1000)) { 1682 priv->hw->ps = speed; 1683 } else { 1684 dev_warn(priv->device, "invalid port speed\n"); 1685 priv->hw->ps = 0; 1686 } 1687 } 1688 1689 /* Initialize the MAC Core */ 1690 priv->hw->mac->core_init(priv->hw, dev->mtu); 1691 1692 ret = priv->hw->mac->rx_ipc(priv->hw); 1693 if (!ret) { 1694 pr_warn(" RX IPC Checksum Offload disabled\n"); 1695 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1696 priv->hw->rx_csum = 0; 1697 } 1698 1699 /* Enable the MAC Rx/Tx */ 1700 if (priv->synopsys_id >= DWMAC_CORE_4_00) 1701 stmmac_dwmac4_set_mac(priv->ioaddr, true); 1702 else 1703 stmmac_set_mac(priv->ioaddr, true); 1704 1705 /* Set the HW DMA mode and the COE */ 1706 stmmac_dma_operation_mode(priv); 1707 1708 stmmac_mmc_setup(priv); 1709 1710 if (init_ptp) { 1711 ret = stmmac_init_ptp(priv); 1712 if (ret) 1713 netdev_warn(priv->dev, "PTP support cannot init.\n"); 1714 } 1715 1716 #ifdef CONFIG_DEBUG_FS 1717 ret = stmmac_init_fs(dev); 1718 if (ret < 0) 1719 pr_warn("%s: failed debugFS registration\n", __func__); 1720 #endif 1721 /* Start the ball rolling... */ 1722 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1723 priv->hw->dma->start_tx(priv->ioaddr); 1724 priv->hw->dma->start_rx(priv->ioaddr); 1725 1726 /* Dump DMA/MAC registers */ 1727 if (netif_msg_hw(priv)) { 1728 priv->hw->mac->dump_regs(priv->hw); 1729 priv->hw->dma->dump_regs(priv->ioaddr); 1730 } 1731 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1732 1733 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1734 priv->rx_riwt = MAX_DMA_RIWT; 1735 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1736 } 1737 1738 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) 1739 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); 1740 1741 /* set TX ring length */ 1742 if (priv->hw->dma->set_tx_ring_len) 1743 priv->hw->dma->set_tx_ring_len(priv->ioaddr, 1744 (DMA_TX_SIZE - 1)); 1745 /* set RX ring length */ 1746 if (priv->hw->dma->set_rx_ring_len) 1747 priv->hw->dma->set_rx_ring_len(priv->ioaddr, 1748 (DMA_RX_SIZE - 1)); 1749 /* Enable TSO */ 1750 if (priv->tso) 1751 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); 1752 1753 return 0; 1754 } 1755 1756 /** 1757 * stmmac_open - open entry point of the driver 1758 * @dev : pointer to the device structure. 1759 * Description: 1760 * This function is the open entry point of the driver. 1761 * Return value: 1762 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1763 * file on failure. 1764 */ 1765 static int stmmac_open(struct net_device *dev) 1766 { 1767 struct stmmac_priv *priv = netdev_priv(dev); 1768 int ret; 1769 1770 stmmac_check_ether_addr(priv); 1771 1772 if (priv->hw->pcs != STMMAC_PCS_RGMII && 1773 priv->hw->pcs != STMMAC_PCS_TBI && 1774 priv->hw->pcs != STMMAC_PCS_RTBI) { 1775 ret = stmmac_init_phy(dev); 1776 if (ret) { 1777 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1778 __func__, ret); 1779 return ret; 1780 } 1781 } 1782 1783 /* Extra statistics */ 1784 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1785 priv->xstats.threshold = tc; 1786 1787 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1788 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 1789 1790 ret = alloc_dma_desc_resources(priv); 1791 if (ret < 0) { 1792 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1793 goto dma_desc_error; 1794 } 1795 1796 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1797 if (ret < 0) { 1798 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1799 goto init_error; 1800 } 1801 1802 ret = stmmac_hw_setup(dev, true); 1803 if (ret < 0) { 1804 pr_err("%s: Hw setup failed\n", __func__); 1805 goto init_error; 1806 } 1807 1808 stmmac_init_tx_coalesce(priv); 1809 1810 if (priv->phydev) 1811 phy_start(priv->phydev); 1812 1813 /* Request the IRQ lines */ 1814 ret = request_irq(dev->irq, stmmac_interrupt, 1815 IRQF_SHARED, dev->name, dev); 1816 if (unlikely(ret < 0)) { 1817 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1818 __func__, dev->irq, ret); 1819 goto init_error; 1820 } 1821 1822 /* Request the Wake IRQ in case of another line is used for WoL */ 1823 if (priv->wol_irq != dev->irq) { 1824 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1825 IRQF_SHARED, dev->name, dev); 1826 if (unlikely(ret < 0)) { 1827 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1828 __func__, priv->wol_irq, ret); 1829 goto wolirq_error; 1830 } 1831 } 1832 1833 /* Request the IRQ lines */ 1834 if (priv->lpi_irq > 0) { 1835 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1836 dev->name, dev); 1837 if (unlikely(ret < 0)) { 1838 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1839 __func__, priv->lpi_irq, ret); 1840 goto lpiirq_error; 1841 } 1842 } 1843 1844 napi_enable(&priv->napi); 1845 netif_start_queue(dev); 1846 1847 return 0; 1848 1849 lpiirq_error: 1850 if (priv->wol_irq != dev->irq) 1851 free_irq(priv->wol_irq, dev); 1852 wolirq_error: 1853 free_irq(dev->irq, dev); 1854 1855 init_error: 1856 free_dma_desc_resources(priv); 1857 dma_desc_error: 1858 if (priv->phydev) 1859 phy_disconnect(priv->phydev); 1860 1861 return ret; 1862 } 1863 1864 /** 1865 * stmmac_release - close entry point of the driver 1866 * @dev : device pointer. 1867 * Description: 1868 * This is the stop entry point of the driver. 1869 */ 1870 static int stmmac_release(struct net_device *dev) 1871 { 1872 struct stmmac_priv *priv = netdev_priv(dev); 1873 1874 if (priv->eee_enabled) 1875 del_timer_sync(&priv->eee_ctrl_timer); 1876 1877 /* Stop and disconnect the PHY */ 1878 if (priv->phydev) { 1879 phy_stop(priv->phydev); 1880 phy_disconnect(priv->phydev); 1881 priv->phydev = NULL; 1882 } 1883 1884 netif_stop_queue(dev); 1885 1886 napi_disable(&priv->napi); 1887 1888 del_timer_sync(&priv->txtimer); 1889 1890 /* Free the IRQ lines */ 1891 free_irq(dev->irq, dev); 1892 if (priv->wol_irq != dev->irq) 1893 free_irq(priv->wol_irq, dev); 1894 if (priv->lpi_irq > 0) 1895 free_irq(priv->lpi_irq, dev); 1896 1897 /* Stop TX/RX DMA and clear the descriptors */ 1898 priv->hw->dma->stop_tx(priv->ioaddr); 1899 priv->hw->dma->stop_rx(priv->ioaddr); 1900 1901 /* Release and free the Rx/Tx resources */ 1902 free_dma_desc_resources(priv); 1903 1904 /* Disable the MAC Rx/Tx */ 1905 stmmac_set_mac(priv->ioaddr, false); 1906 1907 netif_carrier_off(dev); 1908 1909 #ifdef CONFIG_DEBUG_FS 1910 stmmac_exit_fs(dev); 1911 #endif 1912 1913 stmmac_release_ptp(priv); 1914 1915 return 0; 1916 } 1917 1918 /** 1919 * stmmac_tso_allocator - close entry point of the driver 1920 * @priv: driver private structure 1921 * @des: buffer start address 1922 * @total_len: total length to fill in descriptors 1923 * @last_segmant: condition for the last descriptor 1924 * Description: 1925 * This function fills descriptor and request new descriptors according to 1926 * buffer length to fill 1927 */ 1928 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, 1929 int total_len, bool last_segment) 1930 { 1931 struct dma_desc *desc; 1932 int tmp_len; 1933 u32 buff_size; 1934 1935 tmp_len = total_len; 1936 1937 while (tmp_len > 0) { 1938 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 1939 desc = priv->dma_tx + priv->cur_tx; 1940 1941 desc->des0 = des + (total_len - tmp_len); 1942 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 1943 TSO_MAX_BUFF_SIZE : tmp_len; 1944 1945 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, 1946 0, 1, 1947 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), 1948 0, 0); 1949 1950 tmp_len -= TSO_MAX_BUFF_SIZE; 1951 } 1952 } 1953 1954 /** 1955 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 1956 * @skb : the socket buffer 1957 * @dev : device pointer 1958 * Description: this is the transmit function that is called on TSO frames 1959 * (support available on GMAC4 and newer chips). 1960 * Diagram below show the ring programming in case of TSO frames: 1961 * 1962 * First Descriptor 1963 * -------- 1964 * | DES0 |---> buffer1 = L2/L3/L4 header 1965 * | DES1 |---> TCP Payload (can continue on next descr...) 1966 * | DES2 |---> buffer 1 and 2 len 1967 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 1968 * -------- 1969 * | 1970 * ... 1971 * | 1972 * -------- 1973 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 1974 * | DES1 | --| 1975 * | DES2 | --> buffer 1 and 2 len 1976 * | DES3 | 1977 * -------- 1978 * 1979 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 1980 */ 1981 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 1982 { 1983 u32 pay_len, mss; 1984 int tmp_pay_len = 0; 1985 struct stmmac_priv *priv = netdev_priv(dev); 1986 int nfrags = skb_shinfo(skb)->nr_frags; 1987 unsigned int first_entry, des; 1988 struct dma_desc *desc, *first, *mss_desc = NULL; 1989 u8 proto_hdr_len; 1990 int i; 1991 1992 spin_lock(&priv->tx_lock); 1993 1994 /* Compute header lengths */ 1995 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1996 1997 /* Desc availability based on threshold should be enough safe */ 1998 if (unlikely(stmmac_tx_avail(priv) < 1999 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2000 if (!netif_queue_stopped(dev)) { 2001 netif_stop_queue(dev); 2002 /* This is a hard error, log it. */ 2003 pr_err("%s: Tx Ring full when queue awake\n", __func__); 2004 } 2005 spin_unlock(&priv->tx_lock); 2006 return NETDEV_TX_BUSY; 2007 } 2008 2009 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2010 2011 mss = skb_shinfo(skb)->gso_size; 2012 2013 /* set new MSS value if needed */ 2014 if (mss != priv->mss) { 2015 mss_desc = priv->dma_tx + priv->cur_tx; 2016 priv->hw->desc->set_mss(mss_desc, mss); 2017 priv->mss = mss; 2018 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2019 } 2020 2021 if (netif_msg_tx_queued(priv)) { 2022 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2023 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2024 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2025 skb->data_len); 2026 } 2027 2028 first_entry = priv->cur_tx; 2029 2030 desc = priv->dma_tx + first_entry; 2031 first = desc; 2032 2033 /* first descriptor: fill Headers on Buf1 */ 2034 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2035 DMA_TO_DEVICE); 2036 if (dma_mapping_error(priv->device, des)) 2037 goto dma_map_err; 2038 2039 priv->tx_skbuff_dma[first_entry].buf = des; 2040 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2041 priv->tx_skbuff[first_entry] = skb; 2042 2043 first->des0 = des; 2044 2045 /* Fill start of payload in buff2 of first descriptor */ 2046 if (pay_len) 2047 first->des1 = des + proto_hdr_len; 2048 2049 /* If needed take extra descriptors to fill the remaining payload */ 2050 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2051 2052 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); 2053 2054 /* Prepare fragments */ 2055 for (i = 0; i < nfrags; i++) { 2056 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2057 2058 des = skb_frag_dma_map(priv->device, frag, 0, 2059 skb_frag_size(frag), 2060 DMA_TO_DEVICE); 2061 2062 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2063 (i == nfrags - 1)); 2064 2065 priv->tx_skbuff_dma[priv->cur_tx].buf = des; 2066 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); 2067 priv->tx_skbuff[priv->cur_tx] = NULL; 2068 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; 2069 } 2070 2071 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; 2072 2073 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); 2074 2075 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2076 if (netif_msg_hw(priv)) 2077 pr_debug("%s: stop transmitted packets\n", __func__); 2078 netif_stop_queue(dev); 2079 } 2080 2081 dev->stats.tx_bytes += skb->len; 2082 priv->xstats.tx_tso_frames++; 2083 priv->xstats.tx_tso_nfrags += nfrags; 2084 2085 /* Manage tx mitigation */ 2086 priv->tx_count_frames += nfrags + 1; 2087 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2088 mod_timer(&priv->txtimer, 2089 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2090 } else { 2091 priv->tx_count_frames = 0; 2092 priv->hw->desc->set_tx_ic(desc); 2093 priv->xstats.tx_set_ic_bit++; 2094 } 2095 2096 if (!priv->hwts_tx_en) 2097 skb_tx_timestamp(skb); 2098 2099 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2100 priv->hwts_tx_en)) { 2101 /* declare that device is doing timestamping */ 2102 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2103 priv->hw->desc->enable_tx_timestamp(first); 2104 } 2105 2106 /* Complete the first descriptor before granting the DMA */ 2107 priv->hw->desc->prepare_tso_tx_desc(first, 1, 2108 proto_hdr_len, 2109 pay_len, 2110 1, priv->tx_skbuff_dma[first_entry].last_segment, 2111 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2112 2113 /* If context desc is used to change MSS */ 2114 if (mss_desc) 2115 priv->hw->desc->set_tx_owner(mss_desc); 2116 2117 /* The own bit must be the latest setting done when prepare the 2118 * descriptor and then barrier is needed to make sure that 2119 * all is coherent before granting the DMA engine. 2120 */ 2121 smp_wmb(); 2122 2123 if (netif_msg_pktdata(priv)) { 2124 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 2125 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2126 priv->cur_tx, first, nfrags); 2127 2128 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 2129 0); 2130 2131 pr_info(">>> frame to be transmitted: "); 2132 print_pkt(skb->data, skb_headlen(skb)); 2133 } 2134 2135 netdev_sent_queue(dev, skb->len); 2136 2137 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2138 STMMAC_CHAN0); 2139 2140 spin_unlock(&priv->tx_lock); 2141 return NETDEV_TX_OK; 2142 2143 dma_map_err: 2144 spin_unlock(&priv->tx_lock); 2145 dev_err(priv->device, "Tx dma map failed\n"); 2146 dev_kfree_skb(skb); 2147 priv->dev->stats.tx_dropped++; 2148 return NETDEV_TX_OK; 2149 } 2150 2151 /** 2152 * stmmac_xmit - Tx entry point of the driver 2153 * @skb : the socket buffer 2154 * @dev : device pointer 2155 * Description : this is the tx entry point of the driver. 2156 * It programs the chain or the ring and supports oversized frames 2157 * and SG feature. 2158 */ 2159 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 2160 { 2161 struct stmmac_priv *priv = netdev_priv(dev); 2162 unsigned int nopaged_len = skb_headlen(skb); 2163 int i, csum_insertion = 0, is_jumbo = 0; 2164 int nfrags = skb_shinfo(skb)->nr_frags; 2165 unsigned int entry, first_entry; 2166 struct dma_desc *desc, *first; 2167 unsigned int enh_desc; 2168 unsigned int des; 2169 2170 /* Manage oversized TCP frames for GMAC4 device */ 2171 if (skb_is_gso(skb) && priv->tso) { 2172 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 2173 return stmmac_tso_xmit(skb, dev); 2174 } 2175 2176 spin_lock(&priv->tx_lock); 2177 2178 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 2179 spin_unlock(&priv->tx_lock); 2180 if (!netif_queue_stopped(dev)) { 2181 netif_stop_queue(dev); 2182 /* This is a hard error, log it. */ 2183 pr_err("%s: Tx Ring full when queue awake\n", __func__); 2184 } 2185 return NETDEV_TX_BUSY; 2186 } 2187 2188 if (priv->tx_path_in_lpi_mode) 2189 stmmac_disable_eee_mode(priv); 2190 2191 entry = priv->cur_tx; 2192 first_entry = entry; 2193 2194 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 2195 2196 if (likely(priv->extend_desc)) 2197 desc = (struct dma_desc *)(priv->dma_etx + entry); 2198 else 2199 desc = priv->dma_tx + entry; 2200 2201 first = desc; 2202 2203 priv->tx_skbuff[first_entry] = skb; 2204 2205 enh_desc = priv->plat->enh_desc; 2206 /* To program the descriptors according to the size of the frame */ 2207 if (enh_desc) 2208 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 2209 2210 if (unlikely(is_jumbo) && likely(priv->synopsys_id < 2211 DWMAC_CORE_4_00)) { 2212 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 2213 if (unlikely(entry < 0)) 2214 goto dma_map_err; 2215 } 2216 2217 for (i = 0; i < nfrags; i++) { 2218 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2219 int len = skb_frag_size(frag); 2220 bool last_segment = (i == (nfrags - 1)); 2221 2222 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2223 2224 if (likely(priv->extend_desc)) 2225 desc = (struct dma_desc *)(priv->dma_etx + entry); 2226 else 2227 desc = priv->dma_tx + entry; 2228 2229 des = skb_frag_dma_map(priv->device, frag, 0, len, 2230 DMA_TO_DEVICE); 2231 if (dma_mapping_error(priv->device, des)) 2232 goto dma_map_err; /* should reuse desc w/o issues */ 2233 2234 priv->tx_skbuff[entry] = NULL; 2235 2236 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2237 desc->des0 = des; 2238 priv->tx_skbuff_dma[entry].buf = desc->des0; 2239 } else { 2240 desc->des2 = des; 2241 priv->tx_skbuff_dma[entry].buf = desc->des2; 2242 } 2243 2244 priv->tx_skbuff_dma[entry].map_as_page = true; 2245 priv->tx_skbuff_dma[entry].len = len; 2246 priv->tx_skbuff_dma[entry].last_segment = last_segment; 2247 2248 /* Prepare the descriptor and set the own bit too */ 2249 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2250 priv->mode, 1, last_segment); 2251 } 2252 2253 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2254 2255 priv->cur_tx = entry; 2256 2257 if (netif_msg_pktdata(priv)) { 2258 void *tx_head; 2259 2260 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 2261 __func__, priv->cur_tx, priv->dirty_tx, first_entry, 2262 entry, first, nfrags); 2263 2264 if (priv->extend_desc) 2265 tx_head = (void *)priv->dma_etx; 2266 else 2267 tx_head = (void *)priv->dma_tx; 2268 2269 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); 2270 2271 pr_debug(">>> frame to be transmitted: "); 2272 print_pkt(skb->data, skb->len); 2273 } 2274 2275 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2276 if (netif_msg_hw(priv)) 2277 pr_debug("%s: stop transmitted packets\n", __func__); 2278 netif_stop_queue(dev); 2279 } 2280 2281 dev->stats.tx_bytes += skb->len; 2282 2283 /* According to the coalesce parameter the IC bit for the latest 2284 * segment is reset and the timer re-started to clean the tx status. 2285 * This approach takes care about the fragments: desc is the first 2286 * element in case of no SG. 2287 */ 2288 priv->tx_count_frames += nfrags + 1; 2289 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { 2290 mod_timer(&priv->txtimer, 2291 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2292 } else { 2293 priv->tx_count_frames = 0; 2294 priv->hw->desc->set_tx_ic(desc); 2295 priv->xstats.tx_set_ic_bit++; 2296 } 2297 2298 if (!priv->hwts_tx_en) 2299 skb_tx_timestamp(skb); 2300 2301 /* Ready to fill the first descriptor and set the OWN bit w/o any 2302 * problems because all the descriptors are actually ready to be 2303 * passed to the DMA engine. 2304 */ 2305 if (likely(!is_jumbo)) { 2306 bool last_segment = (nfrags == 0); 2307 2308 des = dma_map_single(priv->device, skb->data, 2309 nopaged_len, DMA_TO_DEVICE); 2310 if (dma_mapping_error(priv->device, des)) 2311 goto dma_map_err; 2312 2313 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2314 first->des0 = des; 2315 priv->tx_skbuff_dma[first_entry].buf = first->des0; 2316 } else { 2317 first->des2 = des; 2318 priv->tx_skbuff_dma[first_entry].buf = first->des2; 2319 } 2320 2321 priv->tx_skbuff_dma[first_entry].len = nopaged_len; 2322 priv->tx_skbuff_dma[first_entry].last_segment = last_segment; 2323 2324 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2325 priv->hwts_tx_en)) { 2326 /* declare that device is doing timestamping */ 2327 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2328 priv->hw->desc->enable_tx_timestamp(first); 2329 } 2330 2331 /* Prepare the first descriptor setting the OWN bit too */ 2332 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, 2333 csum_insertion, priv->mode, 1, 2334 last_segment); 2335 2336 /* The own bit must be the latest setting done when prepare the 2337 * descriptor and then barrier is needed to make sure that 2338 * all is coherent before granting the DMA engine. 2339 */ 2340 smp_wmb(); 2341 } 2342 2343 netdev_sent_queue(dev, skb->len); 2344 2345 if (priv->synopsys_id < DWMAC_CORE_4_00) 2346 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2347 else 2348 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, 2349 STMMAC_CHAN0); 2350 2351 spin_unlock(&priv->tx_lock); 2352 return NETDEV_TX_OK; 2353 2354 dma_map_err: 2355 spin_unlock(&priv->tx_lock); 2356 dev_err(priv->device, "Tx dma map failed\n"); 2357 dev_kfree_skb(skb); 2358 priv->dev->stats.tx_dropped++; 2359 return NETDEV_TX_OK; 2360 } 2361 2362 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2363 { 2364 struct ethhdr *ehdr; 2365 u16 vlanid; 2366 2367 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2368 NETIF_F_HW_VLAN_CTAG_RX && 2369 !__vlan_get_tag(skb, &vlanid)) { 2370 /* pop the vlan tag */ 2371 ehdr = (struct ethhdr *)skb->data; 2372 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2373 skb_pull(skb, VLAN_HLEN); 2374 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2375 } 2376 } 2377 2378 2379 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) 2380 { 2381 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) 2382 return 0; 2383 2384 return 1; 2385 } 2386 2387 /** 2388 * stmmac_rx_refill - refill used skb preallocated buffers 2389 * @priv: driver private structure 2390 * Description : this is to reallocate the skb for the reception process 2391 * that is based on zero-copy. 2392 */ 2393 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2394 { 2395 int bfsize = priv->dma_buf_sz; 2396 unsigned int entry = priv->dirty_rx; 2397 int dirty = stmmac_rx_dirty(priv); 2398 2399 while (dirty-- > 0) { 2400 struct dma_desc *p; 2401 2402 if (priv->extend_desc) 2403 p = (struct dma_desc *)(priv->dma_erx + entry); 2404 else 2405 p = priv->dma_rx + entry; 2406 2407 if (likely(priv->rx_skbuff[entry] == NULL)) { 2408 struct sk_buff *skb; 2409 2410 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2411 if (unlikely(!skb)) { 2412 /* so for a while no zero-copy! */ 2413 priv->rx_zeroc_thresh = STMMAC_RX_THRESH; 2414 if (unlikely(net_ratelimit())) 2415 dev_err(priv->device, 2416 "fail to alloc skb entry %d\n", 2417 entry); 2418 break; 2419 } 2420 2421 priv->rx_skbuff[entry] = skb; 2422 priv->rx_skbuff_dma[entry] = 2423 dma_map_single(priv->device, skb->data, bfsize, 2424 DMA_FROM_DEVICE); 2425 if (dma_mapping_error(priv->device, 2426 priv->rx_skbuff_dma[entry])) { 2427 dev_err(priv->device, "Rx dma map failed\n"); 2428 dev_kfree_skb(skb); 2429 break; 2430 } 2431 2432 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { 2433 p->des0 = priv->rx_skbuff_dma[entry]; 2434 p->des1 = 0; 2435 } else { 2436 p->des2 = priv->rx_skbuff_dma[entry]; 2437 } 2438 if (priv->hw->mode->refill_desc3) 2439 priv->hw->mode->refill_desc3(priv, p); 2440 2441 if (priv->rx_zeroc_thresh > 0) 2442 priv->rx_zeroc_thresh--; 2443 2444 if (netif_msg_rx_status(priv)) 2445 pr_debug("\trefill entry #%d\n", entry); 2446 } 2447 wmb(); 2448 2449 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2450 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); 2451 else 2452 priv->hw->desc->set_rx_owner(p); 2453 2454 wmb(); 2455 2456 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 2457 } 2458 priv->dirty_rx = entry; 2459 } 2460 2461 /** 2462 * stmmac_rx - manage the receive process 2463 * @priv: driver private structure 2464 * @limit: napi bugget. 2465 * Description : this the function called by the napi poll method. 2466 * It gets all the frames inside the ring. 2467 */ 2468 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2469 { 2470 unsigned int entry = priv->cur_rx; 2471 unsigned int next_entry; 2472 unsigned int count = 0; 2473 int coe = priv->hw->rx_csum; 2474 2475 if (netif_msg_rx_status(priv)) { 2476 void *rx_head; 2477 2478 pr_debug("%s: descriptor ring:\n", __func__); 2479 if (priv->extend_desc) 2480 rx_head = (void *)priv->dma_erx; 2481 else 2482 rx_head = (void *)priv->dma_rx; 2483 2484 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); 2485 } 2486 while (count < limit) { 2487 int status; 2488 struct dma_desc *p; 2489 2490 if (priv->extend_desc) 2491 p = (struct dma_desc *)(priv->dma_erx + entry); 2492 else 2493 p = priv->dma_rx + entry; 2494 2495 /* read the status of the incoming frame */ 2496 status = priv->hw->desc->rx_status(&priv->dev->stats, 2497 &priv->xstats, p); 2498 /* check if managed by the DMA otherwise go ahead */ 2499 if (unlikely(status & dma_own)) 2500 break; 2501 2502 count++; 2503 2504 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); 2505 next_entry = priv->cur_rx; 2506 2507 if (priv->extend_desc) 2508 prefetch(priv->dma_erx + next_entry); 2509 else 2510 prefetch(priv->dma_rx + next_entry); 2511 2512 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2513 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2514 &priv->xstats, 2515 priv->dma_erx + 2516 entry); 2517 if (unlikely(status == discard_frame)) { 2518 priv->dev->stats.rx_errors++; 2519 if (priv->hwts_rx_en && !priv->extend_desc) { 2520 /* DESC2 & DESC3 will be overwitten by device 2521 * with timestamp value, hence reinitialize 2522 * them in stmmac_rx_refill() function so that 2523 * device can reuse it. 2524 */ 2525 priv->rx_skbuff[entry] = NULL; 2526 dma_unmap_single(priv->device, 2527 priv->rx_skbuff_dma[entry], 2528 priv->dma_buf_sz, 2529 DMA_FROM_DEVICE); 2530 } 2531 } else { 2532 struct sk_buff *skb; 2533 int frame_len; 2534 unsigned int des; 2535 2536 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) 2537 des = p->des0; 2538 else 2539 des = p->des2; 2540 2541 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2542 2543 /* If frame length is greather than skb buffer size 2544 * (preallocated during init) then the packet is 2545 * ignored 2546 */ 2547 if (frame_len > priv->dma_buf_sz) { 2548 pr_err("%s: len %d larger than size (%d)\n", 2549 priv->dev->name, frame_len, 2550 priv->dma_buf_sz); 2551 priv->dev->stats.rx_length_errors++; 2552 break; 2553 } 2554 2555 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2556 * Type frames (LLC/LLC-SNAP) 2557 */ 2558 if (unlikely(status != llc_snap)) 2559 frame_len -= ETH_FCS_LEN; 2560 2561 if (netif_msg_rx_status(priv)) { 2562 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2563 p, entry, des); 2564 if (frame_len > ETH_FRAME_LEN) 2565 pr_debug("\tframe size %d, COE: %d\n", 2566 frame_len, status); 2567 } 2568 2569 /* The zero-copy is always used for all the sizes 2570 * in case of GMAC4 because it needs 2571 * to refill the used descriptors, always. 2572 */ 2573 if (unlikely(!priv->plat->has_gmac4 && 2574 ((frame_len < priv->rx_copybreak) || 2575 stmmac_rx_threshold_count(priv)))) { 2576 skb = netdev_alloc_skb_ip_align(priv->dev, 2577 frame_len); 2578 if (unlikely(!skb)) { 2579 if (net_ratelimit()) 2580 dev_warn(priv->device, 2581 "packet dropped\n"); 2582 priv->dev->stats.rx_dropped++; 2583 break; 2584 } 2585 2586 dma_sync_single_for_cpu(priv->device, 2587 priv->rx_skbuff_dma 2588 [entry], frame_len, 2589 DMA_FROM_DEVICE); 2590 skb_copy_to_linear_data(skb, 2591 priv-> 2592 rx_skbuff[entry]->data, 2593 frame_len); 2594 2595 skb_put(skb, frame_len); 2596 dma_sync_single_for_device(priv->device, 2597 priv->rx_skbuff_dma 2598 [entry], frame_len, 2599 DMA_FROM_DEVICE); 2600 } else { 2601 skb = priv->rx_skbuff[entry]; 2602 if (unlikely(!skb)) { 2603 pr_err("%s: Inconsistent Rx chain\n", 2604 priv->dev->name); 2605 priv->dev->stats.rx_dropped++; 2606 break; 2607 } 2608 prefetch(skb->data - NET_IP_ALIGN); 2609 priv->rx_skbuff[entry] = NULL; 2610 priv->rx_zeroc_thresh++; 2611 2612 skb_put(skb, frame_len); 2613 dma_unmap_single(priv->device, 2614 priv->rx_skbuff_dma[entry], 2615 priv->dma_buf_sz, 2616 DMA_FROM_DEVICE); 2617 } 2618 2619 stmmac_get_rx_hwtstamp(priv, entry, skb); 2620 2621 if (netif_msg_pktdata(priv)) { 2622 pr_debug("frame received (%dbytes)", frame_len); 2623 print_pkt(skb->data, frame_len); 2624 } 2625 2626 stmmac_rx_vlan(priv->dev, skb); 2627 2628 skb->protocol = eth_type_trans(skb, priv->dev); 2629 2630 if (unlikely(!coe)) 2631 skb_checksum_none_assert(skb); 2632 else 2633 skb->ip_summed = CHECKSUM_UNNECESSARY; 2634 2635 napi_gro_receive(&priv->napi, skb); 2636 2637 priv->dev->stats.rx_packets++; 2638 priv->dev->stats.rx_bytes += frame_len; 2639 } 2640 entry = next_entry; 2641 } 2642 2643 stmmac_rx_refill(priv); 2644 2645 priv->xstats.rx_pkt_n += count; 2646 2647 return count; 2648 } 2649 2650 /** 2651 * stmmac_poll - stmmac poll method (NAPI) 2652 * @napi : pointer to the napi structure. 2653 * @budget : maximum number of packets that the current CPU can receive from 2654 * all interfaces. 2655 * Description : 2656 * To look at the incoming frames and clear the tx resources. 2657 */ 2658 static int stmmac_poll(struct napi_struct *napi, int budget) 2659 { 2660 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2661 int work_done = 0; 2662 2663 priv->xstats.napi_poll++; 2664 stmmac_tx_clean(priv); 2665 2666 work_done = stmmac_rx(priv, budget); 2667 if (work_done < budget) { 2668 napi_complete(napi); 2669 stmmac_enable_dma_irq(priv); 2670 } 2671 return work_done; 2672 } 2673 2674 /** 2675 * stmmac_tx_timeout 2676 * @dev : Pointer to net device structure 2677 * Description: this function is called when a packet transmission fails to 2678 * complete within a reasonable time. The driver will mark the error in the 2679 * netdev structure and arrange for the device to be reset to a sane state 2680 * in order to transmit a new packet. 2681 */ 2682 static void stmmac_tx_timeout(struct net_device *dev) 2683 { 2684 struct stmmac_priv *priv = netdev_priv(dev); 2685 2686 /* Clear Tx resources and restart transmitting again */ 2687 stmmac_tx_err(priv); 2688 } 2689 2690 /** 2691 * stmmac_set_rx_mode - entry point for multicast addressing 2692 * @dev : pointer to the device structure 2693 * Description: 2694 * This function is a driver entry point which gets called by the kernel 2695 * whenever multicast addresses must be enabled/disabled. 2696 * Return value: 2697 * void. 2698 */ 2699 static void stmmac_set_rx_mode(struct net_device *dev) 2700 { 2701 struct stmmac_priv *priv = netdev_priv(dev); 2702 2703 priv->hw->mac->set_filter(priv->hw, dev); 2704 } 2705 2706 /** 2707 * stmmac_change_mtu - entry point to change MTU size for the device. 2708 * @dev : device pointer. 2709 * @new_mtu : the new MTU size for the device. 2710 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2711 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2712 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2713 * Return value: 2714 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2715 * file on failure. 2716 */ 2717 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2718 { 2719 struct stmmac_priv *priv = netdev_priv(dev); 2720 int max_mtu; 2721 2722 if (netif_running(dev)) { 2723 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2724 return -EBUSY; 2725 } 2726 2727 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 2728 max_mtu = JUMBO_LEN; 2729 else 2730 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2731 2732 if (priv->plat->maxmtu < max_mtu) 2733 max_mtu = priv->plat->maxmtu; 2734 2735 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2736 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2737 return -EINVAL; 2738 } 2739 2740 dev->mtu = new_mtu; 2741 2742 netdev_update_features(dev); 2743 2744 return 0; 2745 } 2746 2747 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2748 netdev_features_t features) 2749 { 2750 struct stmmac_priv *priv = netdev_priv(dev); 2751 2752 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2753 features &= ~NETIF_F_RXCSUM; 2754 2755 if (!priv->plat->tx_coe) 2756 features &= ~NETIF_F_CSUM_MASK; 2757 2758 /* Some GMAC devices have a bugged Jumbo frame support that 2759 * needs to have the Tx COE disabled for oversized frames 2760 * (due to limited buffer sizes). In this case we disable 2761 * the TX csum insertionin the TDES and not use SF. 2762 */ 2763 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2764 features &= ~NETIF_F_CSUM_MASK; 2765 2766 /* Disable tso if asked by ethtool */ 2767 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 2768 if (features & NETIF_F_TSO) 2769 priv->tso = true; 2770 else 2771 priv->tso = false; 2772 } 2773 2774 return features; 2775 } 2776 2777 static int stmmac_set_features(struct net_device *netdev, 2778 netdev_features_t features) 2779 { 2780 struct stmmac_priv *priv = netdev_priv(netdev); 2781 2782 /* Keep the COE Type in case of csum is supporting */ 2783 if (features & NETIF_F_RXCSUM) 2784 priv->hw->rx_csum = priv->plat->rx_coe; 2785 else 2786 priv->hw->rx_csum = 0; 2787 /* No check needed because rx_coe has been set before and it will be 2788 * fixed in case of issue. 2789 */ 2790 priv->hw->mac->rx_ipc(priv->hw); 2791 2792 return 0; 2793 } 2794 2795 /** 2796 * stmmac_interrupt - main ISR 2797 * @irq: interrupt number. 2798 * @dev_id: to pass the net device pointer. 2799 * Description: this is the main driver interrupt service routine. 2800 * It can call: 2801 * o DMA service routine (to manage incoming frame reception and transmission 2802 * status) 2803 * o Core interrupts to manage: remote wake-up, management counter, LPI 2804 * interrupts. 2805 */ 2806 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2807 { 2808 struct net_device *dev = (struct net_device *)dev_id; 2809 struct stmmac_priv *priv = netdev_priv(dev); 2810 2811 if (priv->irq_wake) 2812 pm_wakeup_event(priv->device, 0); 2813 2814 if (unlikely(!dev)) { 2815 pr_err("%s: invalid dev pointer\n", __func__); 2816 return IRQ_NONE; 2817 } 2818 2819 /* To handle GMAC own interrupts */ 2820 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { 2821 int status = priv->hw->mac->host_irq_status(priv->hw, 2822 &priv->xstats); 2823 if (unlikely(status)) { 2824 /* For LPI we need to save the tx status */ 2825 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2826 priv->tx_path_in_lpi_mode = true; 2827 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2828 priv->tx_path_in_lpi_mode = false; 2829 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) 2830 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, 2831 priv->rx_tail_addr, 2832 STMMAC_CHAN0); 2833 } 2834 2835 /* PCS link status */ 2836 if (priv->hw->pcs) { 2837 if (priv->xstats.pcs_link) 2838 netif_carrier_on(dev); 2839 else 2840 netif_carrier_off(dev); 2841 } 2842 } 2843 2844 /* To handle DMA interrupts */ 2845 stmmac_dma_interrupt(priv); 2846 2847 return IRQ_HANDLED; 2848 } 2849 2850 #ifdef CONFIG_NET_POLL_CONTROLLER 2851 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2852 * to allow network I/O with interrupts disabled. 2853 */ 2854 static void stmmac_poll_controller(struct net_device *dev) 2855 { 2856 disable_irq(dev->irq); 2857 stmmac_interrupt(dev->irq, dev); 2858 enable_irq(dev->irq); 2859 } 2860 #endif 2861 2862 /** 2863 * stmmac_ioctl - Entry point for the Ioctl 2864 * @dev: Device pointer. 2865 * @rq: An IOCTL specefic structure, that can contain a pointer to 2866 * a proprietary structure used to pass information to the driver. 2867 * @cmd: IOCTL command 2868 * Description: 2869 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2870 */ 2871 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2872 { 2873 struct stmmac_priv *priv = netdev_priv(dev); 2874 int ret = -EOPNOTSUPP; 2875 2876 if (!netif_running(dev)) 2877 return -EINVAL; 2878 2879 switch (cmd) { 2880 case SIOCGMIIPHY: 2881 case SIOCGMIIREG: 2882 case SIOCSMIIREG: 2883 if (!priv->phydev) 2884 return -EINVAL; 2885 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2886 break; 2887 case SIOCSHWTSTAMP: 2888 ret = stmmac_hwtstamp_ioctl(dev, rq); 2889 break; 2890 default: 2891 break; 2892 } 2893 2894 return ret; 2895 } 2896 2897 #ifdef CONFIG_DEBUG_FS 2898 static struct dentry *stmmac_fs_dir; 2899 2900 static void sysfs_display_ring(void *head, int size, int extend_desc, 2901 struct seq_file *seq) 2902 { 2903 int i; 2904 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2905 struct dma_desc *p = (struct dma_desc *)head; 2906 2907 for (i = 0; i < size; i++) { 2908 u64 x; 2909 if (extend_desc) { 2910 x = *(u64 *) ep; 2911 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2912 i, (unsigned int)virt_to_phys(ep), 2913 ep->basic.des0, ep->basic.des1, 2914 ep->basic.des2, ep->basic.des3); 2915 ep++; 2916 } else { 2917 x = *(u64 *) p; 2918 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2919 i, (unsigned int)virt_to_phys(ep), 2920 p->des0, p->des1, p->des2, p->des3); 2921 p++; 2922 } 2923 seq_printf(seq, "\n"); 2924 } 2925 } 2926 2927 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2928 { 2929 struct net_device *dev = seq->private; 2930 struct stmmac_priv *priv = netdev_priv(dev); 2931 2932 if (priv->extend_desc) { 2933 seq_printf(seq, "Extended RX descriptor ring:\n"); 2934 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); 2935 seq_printf(seq, "Extended TX descriptor ring:\n"); 2936 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); 2937 } else { 2938 seq_printf(seq, "RX descriptor ring:\n"); 2939 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); 2940 seq_printf(seq, "TX descriptor ring:\n"); 2941 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); 2942 } 2943 2944 return 0; 2945 } 2946 2947 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2948 { 2949 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2950 } 2951 2952 static const struct file_operations stmmac_rings_status_fops = { 2953 .owner = THIS_MODULE, 2954 .open = stmmac_sysfs_ring_open, 2955 .read = seq_read, 2956 .llseek = seq_lseek, 2957 .release = single_release, 2958 }; 2959 2960 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2961 { 2962 struct net_device *dev = seq->private; 2963 struct stmmac_priv *priv = netdev_priv(dev); 2964 2965 if (!priv->hw_cap_support) { 2966 seq_printf(seq, "DMA HW features not supported\n"); 2967 return 0; 2968 } 2969 2970 seq_printf(seq, "==============================\n"); 2971 seq_printf(seq, "\tDMA HW features\n"); 2972 seq_printf(seq, "==============================\n"); 2973 2974 seq_printf(seq, "\t10/100 Mbps %s\n", 2975 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2976 seq_printf(seq, "\t1000 Mbps %s\n", 2977 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2978 seq_printf(seq, "\tHalf duple %s\n", 2979 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2980 seq_printf(seq, "\tHash Filter: %s\n", 2981 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2982 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2983 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2984 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2985 (priv->dma_cap.pcs) ? "Y" : "N"); 2986 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2987 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2988 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2989 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2990 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2991 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2992 seq_printf(seq, "\tRMON module: %s\n", 2993 (priv->dma_cap.rmon) ? "Y" : "N"); 2994 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2995 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2996 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2997 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2998 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2999 (priv->dma_cap.eee) ? "Y" : "N"); 3000 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 3001 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3002 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3003 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3004 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3005 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3006 } else { 3007 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3008 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3009 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3010 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3011 } 3012 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3013 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3014 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3015 priv->dma_cap.number_rx_channel); 3016 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3017 priv->dma_cap.number_tx_channel); 3018 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3019 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3020 3021 return 0; 3022 } 3023 3024 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 3025 { 3026 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 3027 } 3028 3029 static const struct file_operations stmmac_dma_cap_fops = { 3030 .owner = THIS_MODULE, 3031 .open = stmmac_sysfs_dma_cap_open, 3032 .read = seq_read, 3033 .llseek = seq_lseek, 3034 .release = single_release, 3035 }; 3036 3037 static int stmmac_init_fs(struct net_device *dev) 3038 { 3039 struct stmmac_priv *priv = netdev_priv(dev); 3040 3041 /* Create per netdev entries */ 3042 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3043 3044 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3045 pr_err("ERROR %s/%s, debugfs create directory failed\n", 3046 STMMAC_RESOURCE_NAME, dev->name); 3047 3048 return -ENOMEM; 3049 } 3050 3051 /* Entry to report DMA RX/TX rings */ 3052 priv->dbgfs_rings_status = 3053 debugfs_create_file("descriptors_status", S_IRUGO, 3054 priv->dbgfs_dir, dev, 3055 &stmmac_rings_status_fops); 3056 3057 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3058 pr_info("ERROR creating stmmac ring debugfs file\n"); 3059 debugfs_remove_recursive(priv->dbgfs_dir); 3060 3061 return -ENOMEM; 3062 } 3063 3064 /* Entry to report the DMA HW features */ 3065 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, 3066 priv->dbgfs_dir, 3067 dev, &stmmac_dma_cap_fops); 3068 3069 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3070 pr_info("ERROR creating stmmac MMC debugfs file\n"); 3071 debugfs_remove_recursive(priv->dbgfs_dir); 3072 3073 return -ENOMEM; 3074 } 3075 3076 return 0; 3077 } 3078 3079 static void stmmac_exit_fs(struct net_device *dev) 3080 { 3081 struct stmmac_priv *priv = netdev_priv(dev); 3082 3083 debugfs_remove_recursive(priv->dbgfs_dir); 3084 } 3085 #endif /* CONFIG_DEBUG_FS */ 3086 3087 static const struct net_device_ops stmmac_netdev_ops = { 3088 .ndo_open = stmmac_open, 3089 .ndo_start_xmit = stmmac_xmit, 3090 .ndo_stop = stmmac_release, 3091 .ndo_change_mtu = stmmac_change_mtu, 3092 .ndo_fix_features = stmmac_fix_features, 3093 .ndo_set_features = stmmac_set_features, 3094 .ndo_set_rx_mode = stmmac_set_rx_mode, 3095 .ndo_tx_timeout = stmmac_tx_timeout, 3096 .ndo_do_ioctl = stmmac_ioctl, 3097 #ifdef CONFIG_NET_POLL_CONTROLLER 3098 .ndo_poll_controller = stmmac_poll_controller, 3099 #endif 3100 .ndo_set_mac_address = eth_mac_addr, 3101 }; 3102 3103 /** 3104 * stmmac_hw_init - Init the MAC device 3105 * @priv: driver private structure 3106 * Description: this function is to configure the MAC device according to 3107 * some platform parameters or the HW capability register. It prepares the 3108 * driver to use either ring or chain modes and to setup either enhanced or 3109 * normal descriptors. 3110 */ 3111 static int stmmac_hw_init(struct stmmac_priv *priv) 3112 { 3113 struct mac_device_info *mac; 3114 3115 /* Identify the MAC HW device */ 3116 if (priv->plat->has_gmac) { 3117 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3118 mac = dwmac1000_setup(priv->ioaddr, 3119 priv->plat->multicast_filter_bins, 3120 priv->plat->unicast_filter_entries, 3121 &priv->synopsys_id); 3122 } else if (priv->plat->has_gmac4) { 3123 priv->dev->priv_flags |= IFF_UNICAST_FLT; 3124 mac = dwmac4_setup(priv->ioaddr, 3125 priv->plat->multicast_filter_bins, 3126 priv->plat->unicast_filter_entries, 3127 &priv->synopsys_id); 3128 } else { 3129 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); 3130 } 3131 if (!mac) 3132 return -ENOMEM; 3133 3134 priv->hw = mac; 3135 3136 /* To use the chained or ring mode */ 3137 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3138 priv->hw->mode = &dwmac4_ring_mode_ops; 3139 } else { 3140 if (chain_mode) { 3141 priv->hw->mode = &chain_mode_ops; 3142 pr_info(" Chain mode enabled\n"); 3143 priv->mode = STMMAC_CHAIN_MODE; 3144 } else { 3145 priv->hw->mode = &ring_mode_ops; 3146 pr_info(" Ring mode enabled\n"); 3147 priv->mode = STMMAC_RING_MODE; 3148 } 3149 } 3150 3151 /* Get the HW capability (new GMAC newer than 3.50a) */ 3152 priv->hw_cap_support = stmmac_get_hw_features(priv); 3153 if (priv->hw_cap_support) { 3154 pr_info(" DMA HW capability register supported"); 3155 3156 /* We can override some gmac/dma configuration fields: e.g. 3157 * enh_desc, tx_coe (e.g. that are passed through the 3158 * platform) with the values from the HW capability 3159 * register (if supported). 3160 */ 3161 priv->plat->enh_desc = priv->dma_cap.enh_desc; 3162 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 3163 priv->hw->pmt = priv->plat->pmt; 3164 3165 /* TXCOE doesn't work in thresh DMA mode */ 3166 if (priv->plat->force_thresh_dma_mode) 3167 priv->plat->tx_coe = 0; 3168 else 3169 priv->plat->tx_coe = priv->dma_cap.tx_coe; 3170 3171 /* In case of GMAC4 rx_coe is from HW cap register. */ 3172 priv->plat->rx_coe = priv->dma_cap.rx_coe; 3173 3174 if (priv->dma_cap.rx_coe_type2) 3175 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 3176 else if (priv->dma_cap.rx_coe_type1) 3177 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 3178 3179 } else 3180 pr_info(" No HW DMA feature register supported"); 3181 3182 /* To use alternate (extended), normal or GMAC4 descriptor structures */ 3183 if (priv->synopsys_id >= DWMAC_CORE_4_00) 3184 priv->hw->desc = &dwmac4_desc_ops; 3185 else 3186 stmmac_selec_desc_mode(priv); 3187 3188 if (priv->plat->rx_coe) { 3189 priv->hw->rx_csum = priv->plat->rx_coe; 3190 pr_info(" RX Checksum Offload Engine supported\n"); 3191 if (priv->synopsys_id < DWMAC_CORE_4_00) 3192 pr_info("\tCOE Type %d\n", priv->hw->rx_csum); 3193 } 3194 if (priv->plat->tx_coe) 3195 pr_info(" TX Checksum insertion supported\n"); 3196 3197 if (priv->plat->pmt) { 3198 pr_info(" Wake-Up On Lan supported\n"); 3199 device_set_wakeup_capable(priv->device, 1); 3200 } 3201 3202 if (priv->dma_cap.tsoen) 3203 pr_info(" TSO supported\n"); 3204 3205 return 0; 3206 } 3207 3208 /** 3209 * stmmac_dvr_probe 3210 * @device: device pointer 3211 * @plat_dat: platform data pointer 3212 * @res: stmmac resource pointer 3213 * Description: this is the main probe function used to 3214 * call the alloc_etherdev, allocate the priv structure. 3215 * Return: 3216 * returns 0 on success, otherwise errno. 3217 */ 3218 int stmmac_dvr_probe(struct device *device, 3219 struct plat_stmmacenet_data *plat_dat, 3220 struct stmmac_resources *res) 3221 { 3222 int ret = 0; 3223 struct net_device *ndev = NULL; 3224 struct stmmac_priv *priv; 3225 3226 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 3227 if (!ndev) 3228 return -ENOMEM; 3229 3230 SET_NETDEV_DEV(ndev, device); 3231 3232 priv = netdev_priv(ndev); 3233 priv->device = device; 3234 priv->dev = ndev; 3235 3236 stmmac_set_ethtool_ops(ndev); 3237 priv->pause = pause; 3238 priv->plat = plat_dat; 3239 priv->ioaddr = res->addr; 3240 priv->dev->base_addr = (unsigned long)res->addr; 3241 3242 priv->dev->irq = res->irq; 3243 priv->wol_irq = res->wol_irq; 3244 priv->lpi_irq = res->lpi_irq; 3245 3246 if (res->mac) 3247 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 3248 3249 dev_set_drvdata(device, priv->dev); 3250 3251 /* Verify driver arguments */ 3252 stmmac_verify_args(); 3253 3254 /* Override with kernel parameters if supplied XXX CRS XXX 3255 * this needs to have multiple instances 3256 */ 3257 if ((phyaddr >= 0) && (phyaddr <= 31)) 3258 priv->plat->phy_addr = phyaddr; 3259 3260 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 3261 if (IS_ERR(priv->stmmac_clk)) { 3262 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 3263 __func__); 3264 /* If failed to obtain stmmac_clk and specific clk_csr value 3265 * is NOT passed from the platform, probe fail. 3266 */ 3267 if (!priv->plat->clk_csr) { 3268 ret = PTR_ERR(priv->stmmac_clk); 3269 goto error_clk_get; 3270 } else { 3271 priv->stmmac_clk = NULL; 3272 } 3273 } 3274 clk_prepare_enable(priv->stmmac_clk); 3275 3276 priv->pclk = devm_clk_get(priv->device, "pclk"); 3277 if (IS_ERR(priv->pclk)) { 3278 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { 3279 ret = -EPROBE_DEFER; 3280 goto error_pclk_get; 3281 } 3282 priv->pclk = NULL; 3283 } 3284 clk_prepare_enable(priv->pclk); 3285 3286 priv->stmmac_rst = devm_reset_control_get(priv->device, 3287 STMMAC_RESOURCE_NAME); 3288 if (IS_ERR(priv->stmmac_rst)) { 3289 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 3290 ret = -EPROBE_DEFER; 3291 goto error_hw_init; 3292 } 3293 dev_info(priv->device, "no reset control found\n"); 3294 priv->stmmac_rst = NULL; 3295 } 3296 if (priv->stmmac_rst) 3297 reset_control_deassert(priv->stmmac_rst); 3298 3299 /* Init MAC and get the capabilities */ 3300 ret = stmmac_hw_init(priv); 3301 if (ret) 3302 goto error_hw_init; 3303 3304 ndev->netdev_ops = &stmmac_netdev_ops; 3305 3306 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3307 NETIF_F_RXCSUM; 3308 3309 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3310 ndev->hw_features |= NETIF_F_TSO; 3311 priv->tso = true; 3312 pr_info(" TSO feature enabled\n"); 3313 } 3314 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 3315 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 3316 #ifdef STMMAC_VLAN_TAG_USED 3317 /* Both mac100 and gmac support receive VLAN tag detection */ 3318 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3319 #endif 3320 priv->msg_enable = netif_msg_init(debug, default_msg_level); 3321 3322 if (flow_ctrl) 3323 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 3324 3325 /* Rx Watchdog is available in the COREs newer than the 3.40. 3326 * In some case, for example on bugged HW this feature 3327 * has to be disable and this can be done by passing the 3328 * riwt_off field from the platform. 3329 */ 3330 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 3331 priv->use_riwt = 1; 3332 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 3333 } 3334 3335 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 3336 3337 spin_lock_init(&priv->lock); 3338 spin_lock_init(&priv->tx_lock); 3339 3340 ret = register_netdev(ndev); 3341 if (ret) { 3342 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 3343 goto error_netdev_register; 3344 } 3345 3346 /* If a specific clk_csr value is passed from the platform 3347 * this means that the CSR Clock Range selection cannot be 3348 * changed at run-time and it is fixed. Viceversa the driver'll try to 3349 * set the MDC clock dynamically according to the csr actual 3350 * clock input. 3351 */ 3352 if (!priv->plat->clk_csr) 3353 stmmac_clk_csr_set(priv); 3354 else 3355 priv->clk_csr = priv->plat->clk_csr; 3356 3357 stmmac_check_pcs_mode(priv); 3358 3359 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3360 priv->hw->pcs != STMMAC_PCS_TBI && 3361 priv->hw->pcs != STMMAC_PCS_RTBI) { 3362 /* MDIO bus Registration */ 3363 ret = stmmac_mdio_register(ndev); 3364 if (ret < 0) { 3365 pr_debug("%s: MDIO bus (id: %d) registration failed", 3366 __func__, priv->plat->bus_id); 3367 goto error_mdio_register; 3368 } 3369 } 3370 3371 return 0; 3372 3373 error_mdio_register: 3374 unregister_netdev(ndev); 3375 error_netdev_register: 3376 netif_napi_del(&priv->napi); 3377 error_hw_init: 3378 clk_disable_unprepare(priv->pclk); 3379 error_pclk_get: 3380 clk_disable_unprepare(priv->stmmac_clk); 3381 error_clk_get: 3382 free_netdev(ndev); 3383 3384 return ret; 3385 } 3386 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 3387 3388 /** 3389 * stmmac_dvr_remove 3390 * @dev: device pointer 3391 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 3392 * changes the link status, releases the DMA descriptor rings. 3393 */ 3394 int stmmac_dvr_remove(struct device *dev) 3395 { 3396 struct net_device *ndev = dev_get_drvdata(dev); 3397 struct stmmac_priv *priv = netdev_priv(ndev); 3398 3399 pr_info("%s:\n\tremoving driver", __func__); 3400 3401 priv->hw->dma->stop_rx(priv->ioaddr); 3402 priv->hw->dma->stop_tx(priv->ioaddr); 3403 3404 stmmac_set_mac(priv->ioaddr, false); 3405 netif_carrier_off(ndev); 3406 unregister_netdev(ndev); 3407 of_node_put(priv->plat->phy_node); 3408 if (priv->stmmac_rst) 3409 reset_control_assert(priv->stmmac_rst); 3410 clk_disable_unprepare(priv->pclk); 3411 clk_disable_unprepare(priv->stmmac_clk); 3412 if (priv->hw->pcs != STMMAC_PCS_RGMII && 3413 priv->hw->pcs != STMMAC_PCS_TBI && 3414 priv->hw->pcs != STMMAC_PCS_RTBI) 3415 stmmac_mdio_unregister(ndev); 3416 free_netdev(ndev); 3417 3418 return 0; 3419 } 3420 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 3421 3422 /** 3423 * stmmac_suspend - suspend callback 3424 * @dev: device pointer 3425 * Description: this is the function to suspend the device and it is called 3426 * by the platform driver to stop the network queue, release the resources, 3427 * program the PMT register (for WoL), clean and release driver resources. 3428 */ 3429 int stmmac_suspend(struct device *dev) 3430 { 3431 struct net_device *ndev = dev_get_drvdata(dev); 3432 struct stmmac_priv *priv = netdev_priv(ndev); 3433 unsigned long flags; 3434 3435 if (!ndev || !netif_running(ndev)) 3436 return 0; 3437 3438 if (priv->phydev) 3439 phy_stop(priv->phydev); 3440 3441 spin_lock_irqsave(&priv->lock, flags); 3442 3443 netif_device_detach(ndev); 3444 netif_stop_queue(ndev); 3445 3446 napi_disable(&priv->napi); 3447 3448 /* Stop TX/RX DMA */ 3449 priv->hw->dma->stop_tx(priv->ioaddr); 3450 priv->hw->dma->stop_rx(priv->ioaddr); 3451 3452 /* Enable Power down mode by programming the PMT regs */ 3453 if (device_may_wakeup(priv->device)) { 3454 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3455 priv->irq_wake = 1; 3456 } else { 3457 stmmac_set_mac(priv->ioaddr, false); 3458 pinctrl_pm_select_sleep_state(priv->device); 3459 /* Disable clock in case of PWM is off */ 3460 clk_disable(priv->pclk); 3461 clk_disable(priv->stmmac_clk); 3462 } 3463 spin_unlock_irqrestore(&priv->lock, flags); 3464 3465 priv->oldlink = 0; 3466 priv->speed = 0; 3467 priv->oldduplex = -1; 3468 return 0; 3469 } 3470 EXPORT_SYMBOL_GPL(stmmac_suspend); 3471 3472 /** 3473 * stmmac_resume - resume callback 3474 * @dev: device pointer 3475 * Description: when resume this function is invoked to setup the DMA and CORE 3476 * in a usable state. 3477 */ 3478 int stmmac_resume(struct device *dev) 3479 { 3480 struct net_device *ndev = dev_get_drvdata(dev); 3481 struct stmmac_priv *priv = netdev_priv(ndev); 3482 unsigned long flags; 3483 3484 if (!netif_running(ndev)) 3485 return 0; 3486 3487 /* Power Down bit, into the PM register, is cleared 3488 * automatically as soon as a magic packet or a Wake-up frame 3489 * is received. Anyway, it's better to manually clear 3490 * this bit because it can generate problems while resuming 3491 * from another devices (e.g. serial console). 3492 */ 3493 if (device_may_wakeup(priv->device)) { 3494 spin_lock_irqsave(&priv->lock, flags); 3495 priv->hw->mac->pmt(priv->hw, 0); 3496 spin_unlock_irqrestore(&priv->lock, flags); 3497 priv->irq_wake = 0; 3498 } else { 3499 pinctrl_pm_select_default_state(priv->device); 3500 /* enable the clk prevously disabled */ 3501 clk_enable(priv->stmmac_clk); 3502 clk_enable(priv->pclk); 3503 /* reset the phy so that it's ready */ 3504 if (priv->mii) 3505 stmmac_mdio_reset(priv->mii); 3506 } 3507 3508 netif_device_attach(ndev); 3509 3510 spin_lock_irqsave(&priv->lock, flags); 3511 3512 priv->cur_rx = 0; 3513 priv->dirty_rx = 0; 3514 priv->dirty_tx = 0; 3515 priv->cur_tx = 0; 3516 /* reset private mss value to force mss context settings at 3517 * next tso xmit (only used for gmac4). 3518 */ 3519 priv->mss = 0; 3520 3521 stmmac_clear_descriptors(priv); 3522 3523 stmmac_hw_setup(ndev, false); 3524 stmmac_init_tx_coalesce(priv); 3525 stmmac_set_rx_mode(ndev); 3526 3527 napi_enable(&priv->napi); 3528 3529 netif_start_queue(ndev); 3530 3531 spin_unlock_irqrestore(&priv->lock, flags); 3532 3533 if (priv->phydev) 3534 phy_start(priv->phydev); 3535 3536 return 0; 3537 } 3538 EXPORT_SYMBOL_GPL(stmmac_resume); 3539 3540 #ifndef MODULE 3541 static int __init stmmac_cmdline_opt(char *str) 3542 { 3543 char *opt; 3544 3545 if (!str || !*str) 3546 return -EINVAL; 3547 while ((opt = strsep(&str, ",")) != NULL) { 3548 if (!strncmp(opt, "debug:", 6)) { 3549 if (kstrtoint(opt + 6, 0, &debug)) 3550 goto err; 3551 } else if (!strncmp(opt, "phyaddr:", 8)) { 3552 if (kstrtoint(opt + 8, 0, &phyaddr)) 3553 goto err; 3554 } else if (!strncmp(opt, "buf_sz:", 7)) { 3555 if (kstrtoint(opt + 7, 0, &buf_sz)) 3556 goto err; 3557 } else if (!strncmp(opt, "tc:", 3)) { 3558 if (kstrtoint(opt + 3, 0, &tc)) 3559 goto err; 3560 } else if (!strncmp(opt, "watchdog:", 9)) { 3561 if (kstrtoint(opt + 9, 0, &watchdog)) 3562 goto err; 3563 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3564 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3565 goto err; 3566 } else if (!strncmp(opt, "pause:", 6)) { 3567 if (kstrtoint(opt + 6, 0, &pause)) 3568 goto err; 3569 } else if (!strncmp(opt, "eee_timer:", 10)) { 3570 if (kstrtoint(opt + 10, 0, &eee_timer)) 3571 goto err; 3572 } else if (!strncmp(opt, "chain_mode:", 11)) { 3573 if (kstrtoint(opt + 11, 0, &chain_mode)) 3574 goto err; 3575 } 3576 } 3577 return 0; 3578 3579 err: 3580 pr_err("%s: ERROR broken module parameter conversion", __func__); 3581 return -EINVAL; 3582 } 3583 3584 __setup("stmmaceth=", stmmac_cmdline_opt); 3585 #endif /* MODULE */ 3586 3587 static int __init stmmac_init(void) 3588 { 3589 #ifdef CONFIG_DEBUG_FS 3590 /* Create debugfs main directory if it doesn't exist yet */ 3591 if (!stmmac_fs_dir) { 3592 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 3593 3594 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 3595 pr_err("ERROR %s, debugfs create directory failed\n", 3596 STMMAC_RESOURCE_NAME); 3597 3598 return -ENOMEM; 3599 } 3600 } 3601 #endif 3602 3603 return 0; 3604 } 3605 3606 static void __exit stmmac_exit(void) 3607 { 3608 #ifdef CONFIG_DEBUG_FS 3609 debugfs_remove_recursive(stmmac_fs_dir); 3610 #endif 3611 } 3612 3613 module_init(stmmac_init) 3614 module_exit(stmmac_exit) 3615 3616 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3617 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3618 MODULE_LICENSE("GPL"); 3619