1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <net/pkt_cls.h> 40 #include "stmmac_ptp.h" 41 #include "stmmac.h" 42 #include <linux/reset.h> 43 #include <linux/of_mdio.h> 44 #include "dwmac1000.h" 45 #include "dwxgmac2.h" 46 #include "hwif.h" 47 48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) 49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 50 51 /* Module parameters */ 52 #define TX_TIMEO 5000 53 static int watchdog = TX_TIMEO; 54 module_param(watchdog, int, 0644); 55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 56 57 static int debug = -1; 58 module_param(debug, int, 0644); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static int phyaddr = -1; 62 module_param(phyaddr, int, 0444); 63 MODULE_PARM_DESC(phyaddr, "Physical device address"); 64 65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 67 68 static int flow_ctrl = FLOW_AUTO; 69 module_param(flow_ctrl, int, 0644); 70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 71 72 static int pause = PAUSE_TIME; 73 module_param(pause, int, 0644); 74 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 75 76 #define TC_DEFAULT 64 77 static int tc = TC_DEFAULT; 78 module_param(tc, int, 0644); 79 MODULE_PARM_DESC(tc, "DMA threshold control value"); 80 81 #define DEFAULT_BUFSIZE 1536 82 static int buf_sz = DEFAULT_BUFSIZE; 83 module_param(buf_sz, int, 0644); 84 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 85 86 #define STMMAC_RX_COPYBREAK 256 87 88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | 90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 91 92 #define STMMAC_DEFAULT_LPI_TIMER 1000 93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 94 module_param(eee_timer, int, 0644); 95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 97 98 /* By default the driver will use the ring mode to manage tx and rx descriptors, 99 * but allow user to force to use the chain instead of the ring 100 */ 101 static unsigned int chain_mode; 102 module_param(chain_mode, int, 0444); 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 104 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 106 107 #ifdef CONFIG_DEBUG_FS 108 static void stmmac_init_fs(struct net_device *dev); 109 static void stmmac_exit_fs(struct net_device *dev); 110 #endif 111 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 113 114 /** 115 * stmmac_verify_args - verify the driver parameters. 116 * Description: it checks the driver parameters and set a default in case of 117 * errors. 118 */ 119 static void stmmac_verify_args(void) 120 { 121 if (unlikely(watchdog < 0)) 122 watchdog = TX_TIMEO; 123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 124 buf_sz = DEFAULT_BUFSIZE; 125 if (unlikely(flow_ctrl > 1)) 126 flow_ctrl = FLOW_AUTO; 127 else if (likely(flow_ctrl < 0)) 128 flow_ctrl = FLOW_OFF; 129 if (unlikely((pause < 0) || (pause > 0xffff))) 130 pause = PAUSE_TIME; 131 if (eee_timer < 0) 132 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 133 } 134 135 /** 136 * stmmac_disable_all_queues - Disable all queues 137 * @priv: driver private structure 138 */ 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 140 { 141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 144 u32 queue; 145 146 for (queue = 0; queue < maxq; queue++) { 147 struct stmmac_channel *ch = &priv->channel[queue]; 148 149 if (queue < rx_queues_cnt) 150 napi_disable(&ch->rx_napi); 151 if (queue < tx_queues_cnt) 152 napi_disable(&ch->tx_napi); 153 } 154 } 155 156 /** 157 * stmmac_enable_all_queues - Enable all queues 158 * @priv: driver private structure 159 */ 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 161 { 162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 165 u32 queue; 166 167 for (queue = 0; queue < maxq; queue++) { 168 struct stmmac_channel *ch = &priv->channel[queue]; 169 170 if (queue < rx_queues_cnt) 171 napi_enable(&ch->rx_napi); 172 if (queue < tx_queues_cnt) 173 napi_enable(&ch->tx_napi); 174 } 175 } 176 177 /** 178 * stmmac_stop_all_queues - Stop all queues 179 * @priv: driver private structure 180 */ 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 182 { 183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 184 u32 queue; 185 186 for (queue = 0; queue < tx_queues_cnt; queue++) 187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 188 } 189 190 /** 191 * stmmac_start_all_queues - Start all queues 192 * @priv: driver private structure 193 */ 194 static void stmmac_start_all_queues(struct stmmac_priv *priv) 195 { 196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 197 u32 queue; 198 199 for (queue = 0; queue < tx_queues_cnt; queue++) 200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 201 } 202 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 204 { 205 if (!test_bit(STMMAC_DOWN, &priv->state) && 206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 207 queue_work(priv->wq, &priv->service_task); 208 } 209 210 static void stmmac_global_err(struct stmmac_priv *priv) 211 { 212 netif_carrier_off(priv->dev); 213 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 214 stmmac_service_event_schedule(priv); 215 } 216 217 /** 218 * stmmac_clk_csr_set - dynamically set the MDC clock 219 * @priv: driver private structure 220 * Description: this is to dynamically set the MDC clock according to the csr 221 * clock input. 222 * Note: 223 * If a specific clk_csr value is passed from the platform 224 * this means that the CSR Clock Range selection cannot be 225 * changed at run-time and it is fixed (as reported in the driver 226 * documentation). Viceversa the driver will try to set the MDC 227 * clock dynamically according to the actual clock input. 228 */ 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 230 { 231 u32 clk_rate; 232 233 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 234 235 /* Platform provided default clk_csr would be assumed valid 236 * for all other cases except for the below mentioned ones. 237 * For values higher than the IEEE 802.3 specified frequency 238 * we can not estimate the proper divider as it is not known 239 * the frequency of clk_csr_i. So we do not change the default 240 * divider. 241 */ 242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 243 if (clk_rate < CSR_F_35M) 244 priv->clk_csr = STMMAC_CSR_20_35M; 245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 246 priv->clk_csr = STMMAC_CSR_35_60M; 247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 248 priv->clk_csr = STMMAC_CSR_60_100M; 249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 250 priv->clk_csr = STMMAC_CSR_100_150M; 251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 252 priv->clk_csr = STMMAC_CSR_150_250M; 253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 254 priv->clk_csr = STMMAC_CSR_250_300M; 255 } 256 257 if (priv->plat->has_sun8i) { 258 if (clk_rate > 160000000) 259 priv->clk_csr = 0x03; 260 else if (clk_rate > 80000000) 261 priv->clk_csr = 0x02; 262 else if (clk_rate > 40000000) 263 priv->clk_csr = 0x01; 264 else 265 priv->clk_csr = 0; 266 } 267 268 if (priv->plat->has_xgmac) { 269 if (clk_rate > 400000000) 270 priv->clk_csr = 0x5; 271 else if (clk_rate > 350000000) 272 priv->clk_csr = 0x4; 273 else if (clk_rate > 300000000) 274 priv->clk_csr = 0x3; 275 else if (clk_rate > 250000000) 276 priv->clk_csr = 0x2; 277 else if (clk_rate > 150000000) 278 priv->clk_csr = 0x1; 279 else 280 priv->clk_csr = 0x0; 281 } 282 } 283 284 static void print_pkt(unsigned char *buf, int len) 285 { 286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 288 } 289 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 291 { 292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 293 u32 avail; 294 295 if (tx_q->dirty_tx > tx_q->cur_tx) 296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 297 else 298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 299 300 return avail; 301 } 302 303 /** 304 * stmmac_rx_dirty - Get RX queue dirty 305 * @priv: driver private structure 306 * @queue: RX queue index 307 */ 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 309 { 310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 311 u32 dirty; 312 313 if (rx_q->dirty_rx <= rx_q->cur_rx) 314 dirty = rx_q->cur_rx - rx_q->dirty_rx; 315 else 316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 317 318 return dirty; 319 } 320 321 /** 322 * stmmac_enable_eee_mode - check and enter in LPI mode 323 * @priv: driver private structure 324 * Description: this function is to verify and enter in LPI mode in case of 325 * EEE. 326 */ 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 328 { 329 u32 tx_cnt = priv->plat->tx_queues_to_use; 330 u32 queue; 331 332 /* check if all TX queues have the work finished */ 333 for (queue = 0; queue < tx_cnt; queue++) { 334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 335 336 if (tx_q->dirty_tx != tx_q->cur_tx) 337 return; /* still unfinished work */ 338 } 339 340 /* Check and enter in LPI mode */ 341 if (!priv->tx_path_in_lpi_mode) 342 stmmac_set_eee_mode(priv, priv->hw, 343 priv->plat->en_tx_lpi_clockgating); 344 } 345 346 /** 347 * stmmac_disable_eee_mode - disable and exit from LPI mode 348 * @priv: driver private structure 349 * Description: this function is to exit and disable EEE in case of 350 * LPI state is true. This is called by the xmit. 351 */ 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 353 { 354 stmmac_reset_eee_mode(priv, priv->hw); 355 del_timer_sync(&priv->eee_ctrl_timer); 356 priv->tx_path_in_lpi_mode = false; 357 } 358 359 /** 360 * stmmac_eee_ctrl_timer - EEE TX SW timer. 361 * @arg : data hook 362 * Description: 363 * if there is no data transfer and if we are not in LPI state, 364 * then MAC Transmitter can be moved to LPI state. 365 */ 366 static void stmmac_eee_ctrl_timer(struct timer_list *t) 367 { 368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 369 370 stmmac_enable_eee_mode(priv); 371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 372 } 373 374 /** 375 * stmmac_eee_init - init EEE 376 * @priv: driver private structure 377 * Description: 378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 379 * can also manage EEE, this function enable the LPI state and start related 380 * timer. 381 */ 382 bool stmmac_eee_init(struct stmmac_priv *priv) 383 { 384 int tx_lpi_timer = priv->tx_lpi_timer; 385 386 /* Using PCS we cannot dial with the phy registers at this stage 387 * so we do not support extra feature like EEE. 388 */ 389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 390 (priv->hw->pcs == STMMAC_PCS_TBI) || 391 (priv->hw->pcs == STMMAC_PCS_RTBI)) 392 return false; 393 394 /* Check if MAC core supports the EEE feature. */ 395 if (!priv->dma_cap.eee) 396 return false; 397 398 mutex_lock(&priv->lock); 399 400 /* Check if it needs to be deactivated */ 401 if (!priv->eee_active) { 402 if (priv->eee_enabled) { 403 netdev_dbg(priv->dev, "disable EEE\n"); 404 del_timer_sync(&priv->eee_ctrl_timer); 405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 406 } 407 mutex_unlock(&priv->lock); 408 return false; 409 } 410 411 if (priv->eee_active && !priv->eee_enabled) { 412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 415 tx_lpi_timer); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 ts_event_en = PTP_TCR_TSEVNTENA; 633 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 634 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 635 ptp_over_ethernet = PTP_TCR_TSIPENA; 636 break; 637 638 case HWTSTAMP_FILTER_PTP_V2_SYNC: 639 /* PTP v2/802.AS1, any layer, Sync packet */ 640 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 641 ptp_v2 = PTP_TCR_TSVER2ENA; 642 /* take time stamp for SYNC messages only */ 643 ts_event_en = PTP_TCR_TSEVNTENA; 644 645 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 646 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 647 ptp_over_ethernet = PTP_TCR_TSIPENA; 648 break; 649 650 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 651 /* PTP v2/802.AS1, any layer, Delay_req packet */ 652 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 653 ptp_v2 = PTP_TCR_TSVER2ENA; 654 /* take time stamp for Delay_Req messages only */ 655 ts_master_en = PTP_TCR_TSMSTRENA; 656 ts_event_en = PTP_TCR_TSEVNTENA; 657 658 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 659 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 660 ptp_over_ethernet = PTP_TCR_TSIPENA; 661 break; 662 663 case HWTSTAMP_FILTER_NTP_ALL: 664 case HWTSTAMP_FILTER_ALL: 665 /* time stamp any incoming packet */ 666 config.rx_filter = HWTSTAMP_FILTER_ALL; 667 tstamp_all = PTP_TCR_TSENALL; 668 break; 669 670 default: 671 return -ERANGE; 672 } 673 } else { 674 switch (config.rx_filter) { 675 case HWTSTAMP_FILTER_NONE: 676 config.rx_filter = HWTSTAMP_FILTER_NONE; 677 break; 678 default: 679 /* PTP v1, UDP, any kind of event packet */ 680 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 681 break; 682 } 683 } 684 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 685 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 686 687 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 688 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 689 else { 690 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 691 tstamp_all | ptp_v2 | ptp_over_ethernet | 692 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 693 ts_master_en | snap_type_sel); 694 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 695 696 /* program Sub Second Increment reg */ 697 stmmac_config_sub_second_increment(priv, 698 priv->ptpaddr, priv->plat->clk_ptp_rate, 699 xmac, &sec_inc); 700 temp = div_u64(1000000000ULL, sec_inc); 701 702 /* Store sub second increment and flags for later use */ 703 priv->sub_second_inc = sec_inc; 704 priv->systime_flags = value; 705 706 /* calculate default added value: 707 * formula is : 708 * addend = (2^32)/freq_div_ratio; 709 * where, freq_div_ratio = 1e9ns/sec_inc 710 */ 711 temp = (u64)(temp << 32); 712 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 713 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 714 715 /* initialize system time */ 716 ktime_get_real_ts64(&now); 717 718 /* lower 32 bits of tv_sec are safe until y2106 */ 719 stmmac_init_systime(priv, priv->ptpaddr, 720 (u32)now.tv_sec, now.tv_nsec); 721 } 722 723 memcpy(&priv->tstamp_config, &config, sizeof(config)); 724 725 return copy_to_user(ifr->ifr_data, &config, 726 sizeof(config)) ? -EFAULT : 0; 727 } 728 729 /** 730 * stmmac_hwtstamp_get - read hardware timestamping. 731 * @dev: device pointer. 732 * @ifr: An IOCTL specific structure, that can contain a pointer to 733 * a proprietary structure used to pass information to the driver. 734 * Description: 735 * This function obtain the current hardware timestamping settings 736 as requested. 737 */ 738 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 739 { 740 struct stmmac_priv *priv = netdev_priv(dev); 741 struct hwtstamp_config *config = &priv->tstamp_config; 742 743 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 744 return -EOPNOTSUPP; 745 746 return copy_to_user(ifr->ifr_data, config, 747 sizeof(*config)) ? -EFAULT : 0; 748 } 749 750 /** 751 * stmmac_init_ptp - init PTP 752 * @priv: driver private structure 753 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 754 * This is done by looking at the HW cap. register. 755 * This function also registers the ptp driver. 756 */ 757 static int stmmac_init_ptp(struct stmmac_priv *priv) 758 { 759 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 760 761 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 762 return -EOPNOTSUPP; 763 764 priv->adv_ts = 0; 765 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 766 if (xmac && priv->dma_cap.atime_stamp) 767 priv->adv_ts = 1; 768 /* Dwmac 3.x core with extend_desc can support adv_ts */ 769 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 770 priv->adv_ts = 1; 771 772 if (priv->dma_cap.time_stamp) 773 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 774 775 if (priv->adv_ts) 776 netdev_info(priv->dev, 777 "IEEE 1588-2008 Advanced Timestamp supported\n"); 778 779 priv->hwts_tx_en = 0; 780 priv->hwts_rx_en = 0; 781 782 stmmac_ptp_register(priv); 783 784 return 0; 785 } 786 787 static void stmmac_release_ptp(struct stmmac_priv *priv) 788 { 789 if (priv->plat->clk_ptp_ref) 790 clk_disable_unprepare(priv->plat->clk_ptp_ref); 791 stmmac_ptp_unregister(priv); 792 } 793 794 /** 795 * stmmac_mac_flow_ctrl - Configure flow control in all queues 796 * @priv: driver private structure 797 * Description: It is used for configuring the flow control in all queues 798 */ 799 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 800 { 801 u32 tx_cnt = priv->plat->tx_queues_to_use; 802 803 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 804 priv->pause, tx_cnt); 805 } 806 807 static void stmmac_validate(struct phylink_config *config, 808 unsigned long *supported, 809 struct phylink_link_state *state) 810 { 811 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 812 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 814 int tx_cnt = priv->plat->tx_queues_to_use; 815 int max_speed = priv->plat->max_speed; 816 817 phylink_set(mac_supported, 10baseT_Half); 818 phylink_set(mac_supported, 10baseT_Full); 819 phylink_set(mac_supported, 100baseT_Half); 820 phylink_set(mac_supported, 100baseT_Full); 821 phylink_set(mac_supported, 1000baseT_Half); 822 phylink_set(mac_supported, 1000baseT_Full); 823 phylink_set(mac_supported, 1000baseKX_Full); 824 825 phylink_set(mac_supported, Autoneg); 826 phylink_set(mac_supported, Pause); 827 phylink_set(mac_supported, Asym_Pause); 828 phylink_set_port_modes(mac_supported); 829 830 /* Cut down 1G if asked to */ 831 if ((max_speed > 0) && (max_speed < 1000)) { 832 phylink_set(mask, 1000baseT_Full); 833 phylink_set(mask, 1000baseX_Full); 834 } else if (priv->plat->has_xgmac) { 835 if (!max_speed || (max_speed >= 2500)) { 836 phylink_set(mac_supported, 2500baseT_Full); 837 phylink_set(mac_supported, 2500baseX_Full); 838 } 839 if (!max_speed || (max_speed >= 5000)) { 840 phylink_set(mac_supported, 5000baseT_Full); 841 } 842 if (!max_speed || (max_speed >= 10000)) { 843 phylink_set(mac_supported, 10000baseSR_Full); 844 phylink_set(mac_supported, 10000baseLR_Full); 845 phylink_set(mac_supported, 10000baseER_Full); 846 phylink_set(mac_supported, 10000baseLRM_Full); 847 phylink_set(mac_supported, 10000baseT_Full); 848 phylink_set(mac_supported, 10000baseKX4_Full); 849 phylink_set(mac_supported, 10000baseKR_Full); 850 } 851 } 852 853 /* Half-Duplex can only work with single queue */ 854 if (tx_cnt > 1) { 855 phylink_set(mask, 10baseT_Half); 856 phylink_set(mask, 100baseT_Half); 857 phylink_set(mask, 1000baseT_Half); 858 } 859 860 bitmap_and(supported, supported, mac_supported, 861 __ETHTOOL_LINK_MODE_MASK_NBITS); 862 bitmap_andnot(supported, supported, mask, 863 __ETHTOOL_LINK_MODE_MASK_NBITS); 864 bitmap_and(state->advertising, state->advertising, mac_supported, 865 __ETHTOOL_LINK_MODE_MASK_NBITS); 866 bitmap_andnot(state->advertising, state->advertising, mask, 867 __ETHTOOL_LINK_MODE_MASK_NBITS); 868 } 869 870 static int stmmac_mac_link_state(struct phylink_config *config, 871 struct phylink_link_state *state) 872 { 873 return -EOPNOTSUPP; 874 } 875 876 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 877 const struct phylink_link_state *state) 878 { 879 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 880 u32 ctrl; 881 882 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 883 ctrl &= ~priv->hw->link.speed_mask; 884 885 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 886 switch (state->speed) { 887 case SPEED_10000: 888 ctrl |= priv->hw->link.xgmii.speed10000; 889 break; 890 case SPEED_5000: 891 ctrl |= priv->hw->link.xgmii.speed5000; 892 break; 893 case SPEED_2500: 894 ctrl |= priv->hw->link.xgmii.speed2500; 895 break; 896 default: 897 return; 898 } 899 } else { 900 switch (state->speed) { 901 case SPEED_2500: 902 ctrl |= priv->hw->link.speed2500; 903 break; 904 case SPEED_1000: 905 ctrl |= priv->hw->link.speed1000; 906 break; 907 case SPEED_100: 908 ctrl |= priv->hw->link.speed100; 909 break; 910 case SPEED_10: 911 ctrl |= priv->hw->link.speed10; 912 break; 913 default: 914 return; 915 } 916 } 917 918 priv->speed = state->speed; 919 920 if (priv->plat->fix_mac_speed) 921 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 922 923 if (!state->duplex) 924 ctrl &= ~priv->hw->link.duplex; 925 else 926 ctrl |= priv->hw->link.duplex; 927 928 /* Flow Control operation */ 929 if (state->pause) 930 stmmac_mac_flow_ctrl(priv, state->duplex); 931 932 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 933 } 934 935 static void stmmac_mac_an_restart(struct phylink_config *config) 936 { 937 /* Not Supported */ 938 } 939 940 static void stmmac_mac_link_down(struct phylink_config *config, 941 unsigned int mode, phy_interface_t interface) 942 { 943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 944 945 stmmac_mac_set(priv, priv->ioaddr, false); 946 priv->eee_active = false; 947 stmmac_eee_init(priv); 948 stmmac_set_eee_pls(priv, priv->hw, false); 949 } 950 951 static void stmmac_mac_link_up(struct phylink_config *config, 952 unsigned int mode, phy_interface_t interface, 953 struct phy_device *phy) 954 { 955 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 956 957 stmmac_mac_set(priv, priv->ioaddr, true); 958 if (phy && priv->dma_cap.eee) { 959 priv->eee_active = phy_init_eee(phy, 1) >= 0; 960 priv->eee_enabled = stmmac_eee_init(priv); 961 stmmac_set_eee_pls(priv, priv->hw, true); 962 } 963 } 964 965 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 966 .validate = stmmac_validate, 967 .mac_link_state = stmmac_mac_link_state, 968 .mac_config = stmmac_mac_config, 969 .mac_an_restart = stmmac_mac_an_restart, 970 .mac_link_down = stmmac_mac_link_down, 971 .mac_link_up = stmmac_mac_link_up, 972 }; 973 974 /** 975 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 976 * @priv: driver private structure 977 * Description: this is to verify if the HW supports the PCS. 978 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 979 * configured for the TBI, RTBI, or SGMII PHY interface. 980 */ 981 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 982 { 983 int interface = priv->plat->interface; 984 985 if (priv->dma_cap.pcs) { 986 if ((interface == PHY_INTERFACE_MODE_RGMII) || 987 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 988 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 989 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 990 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 991 priv->hw->pcs = STMMAC_PCS_RGMII; 992 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 993 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 994 priv->hw->pcs = STMMAC_PCS_SGMII; 995 } 996 } 997 } 998 999 /** 1000 * stmmac_init_phy - PHY initialization 1001 * @dev: net device structure 1002 * Description: it initializes the driver's PHY state, and attaches the PHY 1003 * to the mac driver. 1004 * Return value: 1005 * 0 on success 1006 */ 1007 static int stmmac_init_phy(struct net_device *dev) 1008 { 1009 struct stmmac_priv *priv = netdev_priv(dev); 1010 struct device_node *node; 1011 int ret; 1012 1013 node = priv->plat->phylink_node; 1014 1015 if (node) 1016 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1017 1018 /* Some DT bindings do not set-up the PHY handle. Let's try to 1019 * manually parse it 1020 */ 1021 if (!node || ret) { 1022 int addr = priv->plat->phy_addr; 1023 struct phy_device *phydev; 1024 1025 phydev = mdiobus_get_phy(priv->mii, addr); 1026 if (!phydev) { 1027 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1028 return -ENODEV; 1029 } 1030 1031 ret = phylink_connect_phy(priv->phylink, phydev); 1032 } 1033 1034 return ret; 1035 } 1036 1037 static int stmmac_phy_setup(struct stmmac_priv *priv) 1038 { 1039 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1040 int mode = priv->plat->phy_interface; 1041 struct phylink *phylink; 1042 1043 priv->phylink_config.dev = &priv->dev->dev; 1044 priv->phylink_config.type = PHYLINK_NETDEV; 1045 1046 phylink = phylink_create(&priv->phylink_config, fwnode, 1047 mode, &stmmac_phylink_mac_ops); 1048 if (IS_ERR(phylink)) 1049 return PTR_ERR(phylink); 1050 1051 priv->phylink = phylink; 1052 return 0; 1053 } 1054 1055 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1056 { 1057 u32 rx_cnt = priv->plat->rx_queues_to_use; 1058 void *head_rx; 1059 u32 queue; 1060 1061 /* Display RX rings */ 1062 for (queue = 0; queue < rx_cnt; queue++) { 1063 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1064 1065 pr_info("\tRX Queue %u rings\n", queue); 1066 1067 if (priv->extend_desc) 1068 head_rx = (void *)rx_q->dma_erx; 1069 else 1070 head_rx = (void *)rx_q->dma_rx; 1071 1072 /* Display RX ring */ 1073 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1074 } 1075 } 1076 1077 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1078 { 1079 u32 tx_cnt = priv->plat->tx_queues_to_use; 1080 void *head_tx; 1081 u32 queue; 1082 1083 /* Display TX rings */ 1084 for (queue = 0; queue < tx_cnt; queue++) { 1085 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1086 1087 pr_info("\tTX Queue %d rings\n", queue); 1088 1089 if (priv->extend_desc) 1090 head_tx = (void *)tx_q->dma_etx; 1091 else 1092 head_tx = (void *)tx_q->dma_tx; 1093 1094 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1095 } 1096 } 1097 1098 static void stmmac_display_rings(struct stmmac_priv *priv) 1099 { 1100 /* Display RX ring */ 1101 stmmac_display_rx_rings(priv); 1102 1103 /* Display TX ring */ 1104 stmmac_display_tx_rings(priv); 1105 } 1106 1107 static int stmmac_set_bfsize(int mtu, int bufsize) 1108 { 1109 int ret = bufsize; 1110 1111 if (mtu >= BUF_SIZE_4KiB) 1112 ret = BUF_SIZE_8KiB; 1113 else if (mtu >= BUF_SIZE_2KiB) 1114 ret = BUF_SIZE_4KiB; 1115 else if (mtu > DEFAULT_BUFSIZE) 1116 ret = BUF_SIZE_2KiB; 1117 else 1118 ret = DEFAULT_BUFSIZE; 1119 1120 return ret; 1121 } 1122 1123 /** 1124 * stmmac_clear_rx_descriptors - clear RX descriptors 1125 * @priv: driver private structure 1126 * @queue: RX queue index 1127 * Description: this function is called to clear the RX descriptors 1128 * in case of both basic and extended descriptors are used. 1129 */ 1130 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1131 { 1132 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1133 int i; 1134 1135 /* Clear the RX descriptors */ 1136 for (i = 0; i < DMA_RX_SIZE; i++) 1137 if (priv->extend_desc) 1138 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1139 priv->use_riwt, priv->mode, 1140 (i == DMA_RX_SIZE - 1), 1141 priv->dma_buf_sz); 1142 else 1143 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1144 priv->use_riwt, priv->mode, 1145 (i == DMA_RX_SIZE - 1), 1146 priv->dma_buf_sz); 1147 } 1148 1149 /** 1150 * stmmac_clear_tx_descriptors - clear tx descriptors 1151 * @priv: driver private structure 1152 * @queue: TX queue index. 1153 * Description: this function is called to clear the TX descriptors 1154 * in case of both basic and extended descriptors are used. 1155 */ 1156 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1157 { 1158 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1159 int i; 1160 1161 /* Clear the TX descriptors */ 1162 for (i = 0; i < DMA_TX_SIZE; i++) 1163 if (priv->extend_desc) 1164 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1165 priv->mode, (i == DMA_TX_SIZE - 1)); 1166 else 1167 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1168 priv->mode, (i == DMA_TX_SIZE - 1)); 1169 } 1170 1171 /** 1172 * stmmac_clear_descriptors - clear descriptors 1173 * @priv: driver private structure 1174 * Description: this function is called to clear the TX and RX descriptors 1175 * in case of both basic and extended descriptors are used. 1176 */ 1177 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1178 { 1179 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1180 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1181 u32 queue; 1182 1183 /* Clear the RX descriptors */ 1184 for (queue = 0; queue < rx_queue_cnt; queue++) 1185 stmmac_clear_rx_descriptors(priv, queue); 1186 1187 /* Clear the TX descriptors */ 1188 for (queue = 0; queue < tx_queue_cnt; queue++) 1189 stmmac_clear_tx_descriptors(priv, queue); 1190 } 1191 1192 /** 1193 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1194 * @priv: driver private structure 1195 * @p: descriptor pointer 1196 * @i: descriptor index 1197 * @flags: gfp flag 1198 * @queue: RX queue index 1199 * Description: this function is called to allocate a receive buffer, perform 1200 * the DMA mapping and init the descriptor. 1201 */ 1202 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1203 int i, gfp_t flags, u32 queue) 1204 { 1205 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1206 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1207 1208 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1209 if (!buf->page) 1210 return -ENOMEM; 1211 1212 if (priv->sph) { 1213 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1214 if (!buf->sec_page) 1215 return -ENOMEM; 1216 1217 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1218 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1219 } else { 1220 buf->sec_page = NULL; 1221 } 1222 1223 buf->addr = page_pool_get_dma_addr(buf->page); 1224 stmmac_set_desc_addr(priv, p, buf->addr); 1225 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1226 stmmac_init_desc3(priv, p); 1227 1228 return 0; 1229 } 1230 1231 /** 1232 * stmmac_free_rx_buffer - free RX dma buffers 1233 * @priv: private structure 1234 * @queue: RX queue index 1235 * @i: buffer index. 1236 */ 1237 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1238 { 1239 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1240 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1241 1242 if (buf->page) 1243 page_pool_put_page(rx_q->page_pool, buf->page, false); 1244 buf->page = NULL; 1245 1246 if (buf->sec_page) 1247 page_pool_put_page(rx_q->page_pool, buf->sec_page, false); 1248 buf->sec_page = NULL; 1249 } 1250 1251 /** 1252 * stmmac_free_tx_buffer - free RX dma buffers 1253 * @priv: private structure 1254 * @queue: RX queue index 1255 * @i: buffer index. 1256 */ 1257 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1258 { 1259 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1260 1261 if (tx_q->tx_skbuff_dma[i].buf) { 1262 if (tx_q->tx_skbuff_dma[i].map_as_page) 1263 dma_unmap_page(priv->device, 1264 tx_q->tx_skbuff_dma[i].buf, 1265 tx_q->tx_skbuff_dma[i].len, 1266 DMA_TO_DEVICE); 1267 else 1268 dma_unmap_single(priv->device, 1269 tx_q->tx_skbuff_dma[i].buf, 1270 tx_q->tx_skbuff_dma[i].len, 1271 DMA_TO_DEVICE); 1272 } 1273 1274 if (tx_q->tx_skbuff[i]) { 1275 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1276 tx_q->tx_skbuff[i] = NULL; 1277 tx_q->tx_skbuff_dma[i].buf = 0; 1278 tx_q->tx_skbuff_dma[i].map_as_page = false; 1279 } 1280 } 1281 1282 /** 1283 * init_dma_rx_desc_rings - init the RX descriptor rings 1284 * @dev: net device structure 1285 * @flags: gfp flag. 1286 * Description: this function initializes the DMA RX descriptors 1287 * and allocates the socket buffers. It supports the chained and ring 1288 * modes. 1289 */ 1290 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1291 { 1292 struct stmmac_priv *priv = netdev_priv(dev); 1293 u32 rx_count = priv->plat->rx_queues_to_use; 1294 int ret = -ENOMEM; 1295 int bfsize = 0; 1296 int queue; 1297 int i; 1298 1299 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 1300 if (bfsize < 0) 1301 bfsize = 0; 1302 1303 if (bfsize < BUF_SIZE_16KiB) 1304 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1305 1306 priv->dma_buf_sz = bfsize; 1307 1308 /* RX INITIALIZATION */ 1309 netif_dbg(priv, probe, priv->dev, 1310 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1311 1312 for (queue = 0; queue < rx_count; queue++) { 1313 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1314 1315 netif_dbg(priv, probe, priv->dev, 1316 "(%s) dma_rx_phy=0x%08x\n", __func__, 1317 (u32)rx_q->dma_rx_phy); 1318 1319 stmmac_clear_rx_descriptors(priv, queue); 1320 1321 for (i = 0; i < DMA_RX_SIZE; i++) { 1322 struct dma_desc *p; 1323 1324 if (priv->extend_desc) 1325 p = &((rx_q->dma_erx + i)->basic); 1326 else 1327 p = rx_q->dma_rx + i; 1328 1329 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1330 queue); 1331 if (ret) 1332 goto err_init_rx_buffers; 1333 } 1334 1335 rx_q->cur_rx = 0; 1336 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1337 1338 /* Setup the chained descriptor addresses */ 1339 if (priv->mode == STMMAC_CHAIN_MODE) { 1340 if (priv->extend_desc) 1341 stmmac_mode_init(priv, rx_q->dma_erx, 1342 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1343 else 1344 stmmac_mode_init(priv, rx_q->dma_rx, 1345 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1346 } 1347 } 1348 1349 buf_sz = bfsize; 1350 1351 return 0; 1352 1353 err_init_rx_buffers: 1354 while (queue >= 0) { 1355 while (--i >= 0) 1356 stmmac_free_rx_buffer(priv, queue, i); 1357 1358 if (queue == 0) 1359 break; 1360 1361 i = DMA_RX_SIZE; 1362 queue--; 1363 } 1364 1365 return ret; 1366 } 1367 1368 /** 1369 * init_dma_tx_desc_rings - init the TX descriptor rings 1370 * @dev: net device structure. 1371 * Description: this function initializes the DMA TX descriptors 1372 * and allocates the socket buffers. It supports the chained and ring 1373 * modes. 1374 */ 1375 static int init_dma_tx_desc_rings(struct net_device *dev) 1376 { 1377 struct stmmac_priv *priv = netdev_priv(dev); 1378 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1379 u32 queue; 1380 int i; 1381 1382 for (queue = 0; queue < tx_queue_cnt; queue++) { 1383 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1384 1385 netif_dbg(priv, probe, priv->dev, 1386 "(%s) dma_tx_phy=0x%08x\n", __func__, 1387 (u32)tx_q->dma_tx_phy); 1388 1389 /* Setup the chained descriptor addresses */ 1390 if (priv->mode == STMMAC_CHAIN_MODE) { 1391 if (priv->extend_desc) 1392 stmmac_mode_init(priv, tx_q->dma_etx, 1393 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1394 else 1395 stmmac_mode_init(priv, tx_q->dma_tx, 1396 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1397 } 1398 1399 for (i = 0; i < DMA_TX_SIZE; i++) { 1400 struct dma_desc *p; 1401 if (priv->extend_desc) 1402 p = &((tx_q->dma_etx + i)->basic); 1403 else 1404 p = tx_q->dma_tx + i; 1405 1406 stmmac_clear_desc(priv, p); 1407 1408 tx_q->tx_skbuff_dma[i].buf = 0; 1409 tx_q->tx_skbuff_dma[i].map_as_page = false; 1410 tx_q->tx_skbuff_dma[i].len = 0; 1411 tx_q->tx_skbuff_dma[i].last_segment = false; 1412 tx_q->tx_skbuff[i] = NULL; 1413 } 1414 1415 tx_q->dirty_tx = 0; 1416 tx_q->cur_tx = 0; 1417 tx_q->mss = 0; 1418 1419 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1420 } 1421 1422 return 0; 1423 } 1424 1425 /** 1426 * init_dma_desc_rings - init the RX/TX descriptor rings 1427 * @dev: net device structure 1428 * @flags: gfp flag. 1429 * Description: this function initializes the DMA RX/TX descriptors 1430 * and allocates the socket buffers. It supports the chained and ring 1431 * modes. 1432 */ 1433 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1434 { 1435 struct stmmac_priv *priv = netdev_priv(dev); 1436 int ret; 1437 1438 ret = init_dma_rx_desc_rings(dev, flags); 1439 if (ret) 1440 return ret; 1441 1442 ret = init_dma_tx_desc_rings(dev); 1443 1444 stmmac_clear_descriptors(priv); 1445 1446 if (netif_msg_hw(priv)) 1447 stmmac_display_rings(priv); 1448 1449 return ret; 1450 } 1451 1452 /** 1453 * dma_free_rx_skbufs - free RX dma buffers 1454 * @priv: private structure 1455 * @queue: RX queue index 1456 */ 1457 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1458 { 1459 int i; 1460 1461 for (i = 0; i < DMA_RX_SIZE; i++) 1462 stmmac_free_rx_buffer(priv, queue, i); 1463 } 1464 1465 /** 1466 * dma_free_tx_skbufs - free TX dma buffers 1467 * @priv: private structure 1468 * @queue: TX queue index 1469 */ 1470 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1471 { 1472 int i; 1473 1474 for (i = 0; i < DMA_TX_SIZE; i++) 1475 stmmac_free_tx_buffer(priv, queue, i); 1476 } 1477 1478 /** 1479 * free_dma_rx_desc_resources - free RX dma desc resources 1480 * @priv: private structure 1481 */ 1482 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1483 { 1484 u32 rx_count = priv->plat->rx_queues_to_use; 1485 u32 queue; 1486 1487 /* Free RX queue resources */ 1488 for (queue = 0; queue < rx_count; queue++) { 1489 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1490 1491 /* Release the DMA RX socket buffers */ 1492 dma_free_rx_skbufs(priv, queue); 1493 1494 /* Free DMA regions of consistent memory previously allocated */ 1495 if (!priv->extend_desc) 1496 dma_free_coherent(priv->device, 1497 DMA_RX_SIZE * sizeof(struct dma_desc), 1498 rx_q->dma_rx, rx_q->dma_rx_phy); 1499 else 1500 dma_free_coherent(priv->device, DMA_RX_SIZE * 1501 sizeof(struct dma_extended_desc), 1502 rx_q->dma_erx, rx_q->dma_rx_phy); 1503 1504 kfree(rx_q->buf_pool); 1505 if (rx_q->page_pool) { 1506 page_pool_request_shutdown(rx_q->page_pool); 1507 page_pool_destroy(rx_q->page_pool); 1508 } 1509 } 1510 } 1511 1512 /** 1513 * free_dma_tx_desc_resources - free TX dma desc resources 1514 * @priv: private structure 1515 */ 1516 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1517 { 1518 u32 tx_count = priv->plat->tx_queues_to_use; 1519 u32 queue; 1520 1521 /* Free TX queue resources */ 1522 for (queue = 0; queue < tx_count; queue++) { 1523 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1524 1525 /* Release the DMA TX socket buffers */ 1526 dma_free_tx_skbufs(priv, queue); 1527 1528 /* Free DMA regions of consistent memory previously allocated */ 1529 if (!priv->extend_desc) 1530 dma_free_coherent(priv->device, 1531 DMA_TX_SIZE * sizeof(struct dma_desc), 1532 tx_q->dma_tx, tx_q->dma_tx_phy); 1533 else 1534 dma_free_coherent(priv->device, DMA_TX_SIZE * 1535 sizeof(struct dma_extended_desc), 1536 tx_q->dma_etx, tx_q->dma_tx_phy); 1537 1538 kfree(tx_q->tx_skbuff_dma); 1539 kfree(tx_q->tx_skbuff); 1540 } 1541 } 1542 1543 /** 1544 * alloc_dma_rx_desc_resources - alloc RX resources. 1545 * @priv: private structure 1546 * Description: according to which descriptor can be used (extend or basic) 1547 * this function allocates the resources for TX and RX paths. In case of 1548 * reception, for example, it pre-allocated the RX socket buffer in order to 1549 * allow zero-copy mechanism. 1550 */ 1551 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1552 { 1553 u32 rx_count = priv->plat->rx_queues_to_use; 1554 int ret = -ENOMEM; 1555 u32 queue; 1556 1557 /* RX queues buffers and DMA */ 1558 for (queue = 0; queue < rx_count; queue++) { 1559 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1560 struct page_pool_params pp_params = { 0 }; 1561 unsigned int num_pages; 1562 1563 rx_q->queue_index = queue; 1564 rx_q->priv_data = priv; 1565 1566 pp_params.flags = PP_FLAG_DMA_MAP; 1567 pp_params.pool_size = DMA_RX_SIZE; 1568 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1569 pp_params.order = ilog2(num_pages); 1570 pp_params.nid = dev_to_node(priv->device); 1571 pp_params.dev = priv->device; 1572 pp_params.dma_dir = DMA_FROM_DEVICE; 1573 1574 rx_q->page_pool = page_pool_create(&pp_params); 1575 if (IS_ERR(rx_q->page_pool)) { 1576 ret = PTR_ERR(rx_q->page_pool); 1577 rx_q->page_pool = NULL; 1578 goto err_dma; 1579 } 1580 1581 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1582 GFP_KERNEL); 1583 if (!rx_q->buf_pool) 1584 goto err_dma; 1585 1586 if (priv->extend_desc) { 1587 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1588 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1589 &rx_q->dma_rx_phy, 1590 GFP_KERNEL); 1591 if (!rx_q->dma_erx) 1592 goto err_dma; 1593 1594 } else { 1595 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1596 DMA_RX_SIZE * sizeof(struct dma_desc), 1597 &rx_q->dma_rx_phy, 1598 GFP_KERNEL); 1599 if (!rx_q->dma_rx) 1600 goto err_dma; 1601 } 1602 } 1603 1604 return 0; 1605 1606 err_dma: 1607 free_dma_rx_desc_resources(priv); 1608 1609 return ret; 1610 } 1611 1612 /** 1613 * alloc_dma_tx_desc_resources - alloc TX resources. 1614 * @priv: private structure 1615 * Description: according to which descriptor can be used (extend or basic) 1616 * this function allocates the resources for TX and RX paths. In case of 1617 * reception, for example, it pre-allocated the RX socket buffer in order to 1618 * allow zero-copy mechanism. 1619 */ 1620 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1621 { 1622 u32 tx_count = priv->plat->tx_queues_to_use; 1623 int ret = -ENOMEM; 1624 u32 queue; 1625 1626 /* TX queues buffers and DMA */ 1627 for (queue = 0; queue < tx_count; queue++) { 1628 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1629 1630 tx_q->queue_index = queue; 1631 tx_q->priv_data = priv; 1632 1633 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1634 sizeof(*tx_q->tx_skbuff_dma), 1635 GFP_KERNEL); 1636 if (!tx_q->tx_skbuff_dma) 1637 goto err_dma; 1638 1639 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1640 sizeof(struct sk_buff *), 1641 GFP_KERNEL); 1642 if (!tx_q->tx_skbuff) 1643 goto err_dma; 1644 1645 if (priv->extend_desc) { 1646 tx_q->dma_etx = dma_alloc_coherent(priv->device, 1647 DMA_TX_SIZE * sizeof(struct dma_extended_desc), 1648 &tx_q->dma_tx_phy, 1649 GFP_KERNEL); 1650 if (!tx_q->dma_etx) 1651 goto err_dma; 1652 } else { 1653 tx_q->dma_tx = dma_alloc_coherent(priv->device, 1654 DMA_TX_SIZE * sizeof(struct dma_desc), 1655 &tx_q->dma_tx_phy, 1656 GFP_KERNEL); 1657 if (!tx_q->dma_tx) 1658 goto err_dma; 1659 } 1660 } 1661 1662 return 0; 1663 1664 err_dma: 1665 free_dma_tx_desc_resources(priv); 1666 1667 return ret; 1668 } 1669 1670 /** 1671 * alloc_dma_desc_resources - alloc TX/RX resources. 1672 * @priv: private structure 1673 * Description: according to which descriptor can be used (extend or basic) 1674 * this function allocates the resources for TX and RX paths. In case of 1675 * reception, for example, it pre-allocated the RX socket buffer in order to 1676 * allow zero-copy mechanism. 1677 */ 1678 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1679 { 1680 /* RX Allocation */ 1681 int ret = alloc_dma_rx_desc_resources(priv); 1682 1683 if (ret) 1684 return ret; 1685 1686 ret = alloc_dma_tx_desc_resources(priv); 1687 1688 return ret; 1689 } 1690 1691 /** 1692 * free_dma_desc_resources - free dma desc resources 1693 * @priv: private structure 1694 */ 1695 static void free_dma_desc_resources(struct stmmac_priv *priv) 1696 { 1697 /* Release the DMA RX socket buffers */ 1698 free_dma_rx_desc_resources(priv); 1699 1700 /* Release the DMA TX socket buffers */ 1701 free_dma_tx_desc_resources(priv); 1702 } 1703 1704 /** 1705 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1706 * @priv: driver private structure 1707 * Description: It is used for enabling the rx queues in the MAC 1708 */ 1709 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1710 { 1711 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1712 int queue; 1713 u8 mode; 1714 1715 for (queue = 0; queue < rx_queues_count; queue++) { 1716 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1717 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1718 } 1719 } 1720 1721 /** 1722 * stmmac_start_rx_dma - start RX DMA channel 1723 * @priv: driver private structure 1724 * @chan: RX channel index 1725 * Description: 1726 * This starts a RX DMA channel 1727 */ 1728 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1729 { 1730 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1731 stmmac_start_rx(priv, priv->ioaddr, chan); 1732 } 1733 1734 /** 1735 * stmmac_start_tx_dma - start TX DMA channel 1736 * @priv: driver private structure 1737 * @chan: TX channel index 1738 * Description: 1739 * This starts a TX DMA channel 1740 */ 1741 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1742 { 1743 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1744 stmmac_start_tx(priv, priv->ioaddr, chan); 1745 } 1746 1747 /** 1748 * stmmac_stop_rx_dma - stop RX DMA channel 1749 * @priv: driver private structure 1750 * @chan: RX channel index 1751 * Description: 1752 * This stops a RX DMA channel 1753 */ 1754 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1755 { 1756 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1757 stmmac_stop_rx(priv, priv->ioaddr, chan); 1758 } 1759 1760 /** 1761 * stmmac_stop_tx_dma - stop TX DMA channel 1762 * @priv: driver private structure 1763 * @chan: TX channel index 1764 * Description: 1765 * This stops a TX DMA channel 1766 */ 1767 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1768 { 1769 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1770 stmmac_stop_tx(priv, priv->ioaddr, chan); 1771 } 1772 1773 /** 1774 * stmmac_start_all_dma - start all RX and TX DMA channels 1775 * @priv: driver private structure 1776 * Description: 1777 * This starts all the RX and TX DMA channels 1778 */ 1779 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1780 { 1781 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1782 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1783 u32 chan = 0; 1784 1785 for (chan = 0; chan < rx_channels_count; chan++) 1786 stmmac_start_rx_dma(priv, chan); 1787 1788 for (chan = 0; chan < tx_channels_count; chan++) 1789 stmmac_start_tx_dma(priv, chan); 1790 } 1791 1792 /** 1793 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1794 * @priv: driver private structure 1795 * Description: 1796 * This stops the RX and TX DMA channels 1797 */ 1798 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1799 { 1800 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1801 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1802 u32 chan = 0; 1803 1804 for (chan = 0; chan < rx_channels_count; chan++) 1805 stmmac_stop_rx_dma(priv, chan); 1806 1807 for (chan = 0; chan < tx_channels_count; chan++) 1808 stmmac_stop_tx_dma(priv, chan); 1809 } 1810 1811 /** 1812 * stmmac_dma_operation_mode - HW DMA operation mode 1813 * @priv: driver private structure 1814 * Description: it is used for configuring the DMA operation mode register in 1815 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1816 */ 1817 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1818 { 1819 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1820 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1821 int rxfifosz = priv->plat->rx_fifo_size; 1822 int txfifosz = priv->plat->tx_fifo_size; 1823 u32 txmode = 0; 1824 u32 rxmode = 0; 1825 u32 chan = 0; 1826 u8 qmode = 0; 1827 1828 if (rxfifosz == 0) 1829 rxfifosz = priv->dma_cap.rx_fifo_size; 1830 if (txfifosz == 0) 1831 txfifosz = priv->dma_cap.tx_fifo_size; 1832 1833 /* Adjust for real per queue fifo size */ 1834 rxfifosz /= rx_channels_count; 1835 txfifosz /= tx_channels_count; 1836 1837 if (priv->plat->force_thresh_dma_mode) { 1838 txmode = tc; 1839 rxmode = tc; 1840 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1841 /* 1842 * In case of GMAC, SF mode can be enabled 1843 * to perform the TX COE in HW. This depends on: 1844 * 1) TX COE if actually supported 1845 * 2) There is no bugged Jumbo frame support 1846 * that needs to not insert csum in the TDES. 1847 */ 1848 txmode = SF_DMA_MODE; 1849 rxmode = SF_DMA_MODE; 1850 priv->xstats.threshold = SF_DMA_MODE; 1851 } else { 1852 txmode = tc; 1853 rxmode = SF_DMA_MODE; 1854 } 1855 1856 /* configure all channels */ 1857 for (chan = 0; chan < rx_channels_count; chan++) { 1858 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1859 1860 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1861 rxfifosz, qmode); 1862 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1863 chan); 1864 } 1865 1866 for (chan = 0; chan < tx_channels_count; chan++) { 1867 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1868 1869 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1870 txfifosz, qmode); 1871 } 1872 } 1873 1874 /** 1875 * stmmac_tx_clean - to manage the transmission completion 1876 * @priv: driver private structure 1877 * @queue: TX queue index 1878 * Description: it reclaims the transmit resources after transmission completes. 1879 */ 1880 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1881 { 1882 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1883 unsigned int bytes_compl = 0, pkts_compl = 0; 1884 unsigned int entry, count = 0; 1885 1886 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1887 1888 priv->xstats.tx_clean++; 1889 1890 entry = tx_q->dirty_tx; 1891 while ((entry != tx_q->cur_tx) && (count < budget)) { 1892 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1893 struct dma_desc *p; 1894 int status; 1895 1896 if (priv->extend_desc) 1897 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1898 else 1899 p = tx_q->dma_tx + entry; 1900 1901 status = stmmac_tx_status(priv, &priv->dev->stats, 1902 &priv->xstats, p, priv->ioaddr); 1903 /* Check if the descriptor is owned by the DMA */ 1904 if (unlikely(status & tx_dma_own)) 1905 break; 1906 1907 count++; 1908 1909 /* Make sure descriptor fields are read after reading 1910 * the own bit. 1911 */ 1912 dma_rmb(); 1913 1914 /* Just consider the last segment and ...*/ 1915 if (likely(!(status & tx_not_ls))) { 1916 /* ... verify the status error condition */ 1917 if (unlikely(status & tx_err)) { 1918 priv->dev->stats.tx_errors++; 1919 } else { 1920 priv->dev->stats.tx_packets++; 1921 priv->xstats.tx_pkt_n++; 1922 } 1923 stmmac_get_tx_hwtstamp(priv, p, skb); 1924 } 1925 1926 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1927 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1928 dma_unmap_page(priv->device, 1929 tx_q->tx_skbuff_dma[entry].buf, 1930 tx_q->tx_skbuff_dma[entry].len, 1931 DMA_TO_DEVICE); 1932 else 1933 dma_unmap_single(priv->device, 1934 tx_q->tx_skbuff_dma[entry].buf, 1935 tx_q->tx_skbuff_dma[entry].len, 1936 DMA_TO_DEVICE); 1937 tx_q->tx_skbuff_dma[entry].buf = 0; 1938 tx_q->tx_skbuff_dma[entry].len = 0; 1939 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1940 } 1941 1942 stmmac_clean_desc3(priv, tx_q, p); 1943 1944 tx_q->tx_skbuff_dma[entry].last_segment = false; 1945 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1946 1947 if (likely(skb != NULL)) { 1948 pkts_compl++; 1949 bytes_compl += skb->len; 1950 dev_consume_skb_any(skb); 1951 tx_q->tx_skbuff[entry] = NULL; 1952 } 1953 1954 stmmac_release_tx_desc(priv, p, priv->mode); 1955 1956 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1957 } 1958 tx_q->dirty_tx = entry; 1959 1960 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1961 pkts_compl, bytes_compl); 1962 1963 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1964 queue))) && 1965 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1966 1967 netif_dbg(priv, tx_done, priv->dev, 1968 "%s: restart transmit\n", __func__); 1969 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1970 } 1971 1972 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1973 stmmac_enable_eee_mode(priv); 1974 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1975 } 1976 1977 /* We still have pending packets, let's call for a new scheduling */ 1978 if (tx_q->dirty_tx != tx_q->cur_tx) 1979 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 1980 1981 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1982 1983 return count; 1984 } 1985 1986 /** 1987 * stmmac_tx_err - to manage the tx error 1988 * @priv: driver private structure 1989 * @chan: channel index 1990 * Description: it cleans the descriptors and restarts the transmission 1991 * in case of transmission errors. 1992 */ 1993 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 1994 { 1995 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 1996 int i; 1997 1998 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 1999 2000 stmmac_stop_tx_dma(priv, chan); 2001 dma_free_tx_skbufs(priv, chan); 2002 for (i = 0; i < DMA_TX_SIZE; i++) 2003 if (priv->extend_desc) 2004 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 2005 priv->mode, (i == DMA_TX_SIZE - 1)); 2006 else 2007 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 2008 priv->mode, (i == DMA_TX_SIZE - 1)); 2009 tx_q->dirty_tx = 0; 2010 tx_q->cur_tx = 0; 2011 tx_q->mss = 0; 2012 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2013 stmmac_start_tx_dma(priv, chan); 2014 2015 priv->dev->stats.tx_errors++; 2016 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2017 } 2018 2019 /** 2020 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2021 * @priv: driver private structure 2022 * @txmode: TX operating mode 2023 * @rxmode: RX operating mode 2024 * @chan: channel index 2025 * Description: it is used for configuring of the DMA operation mode in 2026 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2027 * mode. 2028 */ 2029 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2030 u32 rxmode, u32 chan) 2031 { 2032 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2033 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2034 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2035 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2036 int rxfifosz = priv->plat->rx_fifo_size; 2037 int txfifosz = priv->plat->tx_fifo_size; 2038 2039 if (rxfifosz == 0) 2040 rxfifosz = priv->dma_cap.rx_fifo_size; 2041 if (txfifosz == 0) 2042 txfifosz = priv->dma_cap.tx_fifo_size; 2043 2044 /* Adjust for real per queue fifo size */ 2045 rxfifosz /= rx_channels_count; 2046 txfifosz /= tx_channels_count; 2047 2048 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2049 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2050 } 2051 2052 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2053 { 2054 int ret; 2055 2056 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2057 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2058 if (ret && (ret != -EINVAL)) { 2059 stmmac_global_err(priv); 2060 return true; 2061 } 2062 2063 return false; 2064 } 2065 2066 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2067 { 2068 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2069 &priv->xstats, chan); 2070 struct stmmac_channel *ch = &priv->channel[chan]; 2071 2072 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2073 if (napi_schedule_prep(&ch->rx_napi)) { 2074 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2075 __napi_schedule_irqoff(&ch->rx_napi); 2076 status |= handle_tx; 2077 } 2078 } 2079 2080 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) 2081 napi_schedule_irqoff(&ch->tx_napi); 2082 2083 return status; 2084 } 2085 2086 /** 2087 * stmmac_dma_interrupt - DMA ISR 2088 * @priv: driver private structure 2089 * Description: this is the DMA ISR. It is called by the main ISR. 2090 * It calls the dwmac dma routine and schedule poll method in case of some 2091 * work can be done. 2092 */ 2093 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2094 { 2095 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2096 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2097 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2098 tx_channel_count : rx_channel_count; 2099 u32 chan; 2100 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2101 2102 /* Make sure we never check beyond our status buffer. */ 2103 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2104 channels_to_check = ARRAY_SIZE(status); 2105 2106 for (chan = 0; chan < channels_to_check; chan++) 2107 status[chan] = stmmac_napi_check(priv, chan); 2108 2109 for (chan = 0; chan < tx_channel_count; chan++) { 2110 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2111 /* Try to bump up the dma threshold on this failure */ 2112 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2113 (tc <= 256)) { 2114 tc += 64; 2115 if (priv->plat->force_thresh_dma_mode) 2116 stmmac_set_dma_operation_mode(priv, 2117 tc, 2118 tc, 2119 chan); 2120 else 2121 stmmac_set_dma_operation_mode(priv, 2122 tc, 2123 SF_DMA_MODE, 2124 chan); 2125 priv->xstats.threshold = tc; 2126 } 2127 } else if (unlikely(status[chan] == tx_hard_error)) { 2128 stmmac_tx_err(priv, chan); 2129 } 2130 } 2131 } 2132 2133 /** 2134 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2135 * @priv: driver private structure 2136 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2137 */ 2138 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2139 { 2140 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2141 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2142 2143 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2144 2145 if (priv->dma_cap.rmon) { 2146 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2147 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2148 } else 2149 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2150 } 2151 2152 /** 2153 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2154 * @priv: driver private structure 2155 * Description: 2156 * new GMAC chip generations have a new register to indicate the 2157 * presence of the optional feature/functions. 2158 * This can be also used to override the value passed through the 2159 * platform and necessary for old MAC10/100 and GMAC chips. 2160 */ 2161 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2162 { 2163 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2164 } 2165 2166 /** 2167 * stmmac_check_ether_addr - check if the MAC addr is valid 2168 * @priv: driver private structure 2169 * Description: 2170 * it is to verify if the MAC address is valid, in case of failures it 2171 * generates a random MAC address 2172 */ 2173 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2174 { 2175 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2176 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2177 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2178 eth_hw_addr_random(priv->dev); 2179 dev_info(priv->device, "device MAC address %pM\n", 2180 priv->dev->dev_addr); 2181 } 2182 } 2183 2184 /** 2185 * stmmac_init_dma_engine - DMA init. 2186 * @priv: driver private structure 2187 * Description: 2188 * It inits the DMA invoking the specific MAC/GMAC callback. 2189 * Some DMA parameters can be passed from the platform; 2190 * in case of these are not passed a default is kept for the MAC or GMAC. 2191 */ 2192 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2193 { 2194 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2195 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2196 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2197 struct stmmac_rx_queue *rx_q; 2198 struct stmmac_tx_queue *tx_q; 2199 u32 chan = 0; 2200 int atds = 0; 2201 int ret = 0; 2202 2203 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2204 dev_err(priv->device, "Invalid DMA configuration\n"); 2205 return -EINVAL; 2206 } 2207 2208 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2209 atds = 1; 2210 2211 ret = stmmac_reset(priv, priv->ioaddr); 2212 if (ret) { 2213 dev_err(priv->device, "Failed to reset the dma\n"); 2214 return ret; 2215 } 2216 2217 /* DMA Configuration */ 2218 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2219 2220 if (priv->plat->axi) 2221 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2222 2223 /* DMA CSR Channel configuration */ 2224 for (chan = 0; chan < dma_csr_ch; chan++) 2225 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2226 2227 /* DMA RX Channel Configuration */ 2228 for (chan = 0; chan < rx_channels_count; chan++) { 2229 rx_q = &priv->rx_queue[chan]; 2230 2231 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2232 rx_q->dma_rx_phy, chan); 2233 2234 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2235 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2236 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2237 rx_q->rx_tail_addr, chan); 2238 } 2239 2240 /* DMA TX Channel Configuration */ 2241 for (chan = 0; chan < tx_channels_count; chan++) { 2242 tx_q = &priv->tx_queue[chan]; 2243 2244 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2245 tx_q->dma_tx_phy, chan); 2246 2247 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2248 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2249 tx_q->tx_tail_addr, chan); 2250 } 2251 2252 return ret; 2253 } 2254 2255 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2256 { 2257 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2258 2259 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2260 } 2261 2262 /** 2263 * stmmac_tx_timer - mitigation sw timer for tx. 2264 * @data: data pointer 2265 * Description: 2266 * This is the timer handler to directly invoke the stmmac_tx_clean. 2267 */ 2268 static void stmmac_tx_timer(struct timer_list *t) 2269 { 2270 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2271 struct stmmac_priv *priv = tx_q->priv_data; 2272 struct stmmac_channel *ch; 2273 2274 ch = &priv->channel[tx_q->queue_index]; 2275 2276 /* 2277 * If NAPI is already running we can miss some events. Let's rearm 2278 * the timer and try again. 2279 */ 2280 if (likely(napi_schedule_prep(&ch->tx_napi))) 2281 __napi_schedule(&ch->tx_napi); 2282 else 2283 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 2284 } 2285 2286 /** 2287 * stmmac_init_coalesce - init mitigation options. 2288 * @priv: driver private structure 2289 * Description: 2290 * This inits the coalesce parameters: i.e. timer rate, 2291 * timer handler and default threshold used for enabling the 2292 * interrupt on completion bit. 2293 */ 2294 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2295 { 2296 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2297 u32 chan; 2298 2299 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2300 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2301 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2302 2303 for (chan = 0; chan < tx_channel_count; chan++) { 2304 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2305 2306 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2307 } 2308 } 2309 2310 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2311 { 2312 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2313 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2314 u32 chan; 2315 2316 /* set TX ring length */ 2317 for (chan = 0; chan < tx_channels_count; chan++) 2318 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2319 (DMA_TX_SIZE - 1), chan); 2320 2321 /* set RX ring length */ 2322 for (chan = 0; chan < rx_channels_count; chan++) 2323 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2324 (DMA_RX_SIZE - 1), chan); 2325 } 2326 2327 /** 2328 * stmmac_set_tx_queue_weight - Set TX queue weight 2329 * @priv: driver private structure 2330 * Description: It is used for setting TX queues weight 2331 */ 2332 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2333 { 2334 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2335 u32 weight; 2336 u32 queue; 2337 2338 for (queue = 0; queue < tx_queues_count; queue++) { 2339 weight = priv->plat->tx_queues_cfg[queue].weight; 2340 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2341 } 2342 } 2343 2344 /** 2345 * stmmac_configure_cbs - Configure CBS in TX queue 2346 * @priv: driver private structure 2347 * Description: It is used for configuring CBS in AVB TX queues 2348 */ 2349 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2350 { 2351 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2352 u32 mode_to_use; 2353 u32 queue; 2354 2355 /* queue 0 is reserved for legacy traffic */ 2356 for (queue = 1; queue < tx_queues_count; queue++) { 2357 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2358 if (mode_to_use == MTL_QUEUE_DCB) 2359 continue; 2360 2361 stmmac_config_cbs(priv, priv->hw, 2362 priv->plat->tx_queues_cfg[queue].send_slope, 2363 priv->plat->tx_queues_cfg[queue].idle_slope, 2364 priv->plat->tx_queues_cfg[queue].high_credit, 2365 priv->plat->tx_queues_cfg[queue].low_credit, 2366 queue); 2367 } 2368 } 2369 2370 /** 2371 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2372 * @priv: driver private structure 2373 * Description: It is used for mapping RX queues to RX dma channels 2374 */ 2375 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2376 { 2377 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2378 u32 queue; 2379 u32 chan; 2380 2381 for (queue = 0; queue < rx_queues_count; queue++) { 2382 chan = priv->plat->rx_queues_cfg[queue].chan; 2383 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2384 } 2385 } 2386 2387 /** 2388 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2389 * @priv: driver private structure 2390 * Description: It is used for configuring the RX Queue Priority 2391 */ 2392 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2393 { 2394 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2395 u32 queue; 2396 u32 prio; 2397 2398 for (queue = 0; queue < rx_queues_count; queue++) { 2399 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2400 continue; 2401 2402 prio = priv->plat->rx_queues_cfg[queue].prio; 2403 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2404 } 2405 } 2406 2407 /** 2408 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2409 * @priv: driver private structure 2410 * Description: It is used for configuring the TX Queue Priority 2411 */ 2412 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2413 { 2414 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2415 u32 queue; 2416 u32 prio; 2417 2418 for (queue = 0; queue < tx_queues_count; queue++) { 2419 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2420 continue; 2421 2422 prio = priv->plat->tx_queues_cfg[queue].prio; 2423 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2424 } 2425 } 2426 2427 /** 2428 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2429 * @priv: driver private structure 2430 * Description: It is used for configuring the RX queue routing 2431 */ 2432 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2433 { 2434 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2435 u32 queue; 2436 u8 packet; 2437 2438 for (queue = 0; queue < rx_queues_count; queue++) { 2439 /* no specific packet type routing specified for the queue */ 2440 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2441 continue; 2442 2443 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2444 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2445 } 2446 } 2447 2448 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2449 { 2450 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2451 priv->rss.enable = false; 2452 return; 2453 } 2454 2455 if (priv->dev->features & NETIF_F_RXHASH) 2456 priv->rss.enable = true; 2457 else 2458 priv->rss.enable = false; 2459 2460 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2461 priv->plat->rx_queues_to_use); 2462 } 2463 2464 /** 2465 * stmmac_mtl_configuration - Configure MTL 2466 * @priv: driver private structure 2467 * Description: It is used for configurring MTL 2468 */ 2469 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2470 { 2471 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2472 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2473 2474 if (tx_queues_count > 1) 2475 stmmac_set_tx_queue_weight(priv); 2476 2477 /* Configure MTL RX algorithms */ 2478 if (rx_queues_count > 1) 2479 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2480 priv->plat->rx_sched_algorithm); 2481 2482 /* Configure MTL TX algorithms */ 2483 if (tx_queues_count > 1) 2484 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2485 priv->plat->tx_sched_algorithm); 2486 2487 /* Configure CBS in AVB TX queues */ 2488 if (tx_queues_count > 1) 2489 stmmac_configure_cbs(priv); 2490 2491 /* Map RX MTL to DMA channels */ 2492 stmmac_rx_queue_dma_chan_map(priv); 2493 2494 /* Enable MAC RX Queues */ 2495 stmmac_mac_enable_rx_queues(priv); 2496 2497 /* Set RX priorities */ 2498 if (rx_queues_count > 1) 2499 stmmac_mac_config_rx_queues_prio(priv); 2500 2501 /* Set TX priorities */ 2502 if (tx_queues_count > 1) 2503 stmmac_mac_config_tx_queues_prio(priv); 2504 2505 /* Set RX routing */ 2506 if (rx_queues_count > 1) 2507 stmmac_mac_config_rx_queues_routing(priv); 2508 2509 /* Receive Side Scaling */ 2510 if (rx_queues_count > 1) 2511 stmmac_mac_config_rss(priv); 2512 } 2513 2514 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2515 { 2516 if (priv->dma_cap.asp) { 2517 netdev_info(priv->dev, "Enabling Safety Features\n"); 2518 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2519 } else { 2520 netdev_info(priv->dev, "No Safety Features support found\n"); 2521 } 2522 } 2523 2524 /** 2525 * stmmac_hw_setup - setup mac in a usable state. 2526 * @dev : pointer to the device structure. 2527 * Description: 2528 * this is the main function to setup the HW in a usable state because the 2529 * dma engine is reset, the core registers are configured (e.g. AXI, 2530 * Checksum features, timers). The DMA is ready to start receiving and 2531 * transmitting. 2532 * Return value: 2533 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2534 * file on failure. 2535 */ 2536 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2537 { 2538 struct stmmac_priv *priv = netdev_priv(dev); 2539 u32 rx_cnt = priv->plat->rx_queues_to_use; 2540 u32 tx_cnt = priv->plat->tx_queues_to_use; 2541 u32 chan; 2542 int ret; 2543 2544 /* DMA initialization and SW reset */ 2545 ret = stmmac_init_dma_engine(priv); 2546 if (ret < 0) { 2547 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2548 __func__); 2549 return ret; 2550 } 2551 2552 /* Copy the MAC addr into the HW */ 2553 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2554 2555 /* PS and related bits will be programmed according to the speed */ 2556 if (priv->hw->pcs) { 2557 int speed = priv->plat->mac_port_sel_speed; 2558 2559 if ((speed == SPEED_10) || (speed == SPEED_100) || 2560 (speed == SPEED_1000)) { 2561 priv->hw->ps = speed; 2562 } else { 2563 dev_warn(priv->device, "invalid port speed\n"); 2564 priv->hw->ps = 0; 2565 } 2566 } 2567 2568 /* Initialize the MAC Core */ 2569 stmmac_core_init(priv, priv->hw, dev); 2570 2571 /* Initialize MTL*/ 2572 stmmac_mtl_configuration(priv); 2573 2574 /* Initialize Safety Features */ 2575 stmmac_safety_feat_configuration(priv); 2576 2577 ret = stmmac_rx_ipc(priv, priv->hw); 2578 if (!ret) { 2579 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2580 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2581 priv->hw->rx_csum = 0; 2582 } 2583 2584 /* Enable the MAC Rx/Tx */ 2585 stmmac_mac_set(priv, priv->ioaddr, true); 2586 2587 /* Set the HW DMA mode and the COE */ 2588 stmmac_dma_operation_mode(priv); 2589 2590 stmmac_mmc_setup(priv); 2591 2592 if (init_ptp) { 2593 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2594 if (ret < 0) 2595 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2596 2597 ret = stmmac_init_ptp(priv); 2598 if (ret == -EOPNOTSUPP) 2599 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2600 else if (ret) 2601 netdev_warn(priv->dev, "PTP init failed\n"); 2602 } 2603 2604 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2605 2606 if (priv->use_riwt) { 2607 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt); 2608 if (!ret) 2609 priv->rx_riwt = MIN_DMA_RIWT; 2610 } 2611 2612 if (priv->hw->pcs) 2613 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2614 2615 /* set TX and RX rings length */ 2616 stmmac_set_rings_length(priv); 2617 2618 /* Enable TSO */ 2619 if (priv->tso) { 2620 for (chan = 0; chan < tx_cnt; chan++) 2621 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2622 } 2623 2624 /* Enable Split Header */ 2625 if (priv->sph && priv->hw->rx_csum) { 2626 for (chan = 0; chan < rx_cnt; chan++) 2627 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2628 } 2629 2630 /* VLAN Tag Insertion */ 2631 if (priv->dma_cap.vlins) 2632 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2633 2634 /* Start the ball rolling... */ 2635 stmmac_start_all_dma(priv); 2636 2637 return 0; 2638 } 2639 2640 static void stmmac_hw_teardown(struct net_device *dev) 2641 { 2642 struct stmmac_priv *priv = netdev_priv(dev); 2643 2644 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2645 } 2646 2647 /** 2648 * stmmac_open - open entry point of the driver 2649 * @dev : pointer to the device structure. 2650 * Description: 2651 * This function is the open entry point of the driver. 2652 * Return value: 2653 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2654 * file on failure. 2655 */ 2656 static int stmmac_open(struct net_device *dev) 2657 { 2658 struct stmmac_priv *priv = netdev_priv(dev); 2659 u32 chan; 2660 int ret; 2661 2662 if (priv->hw->pcs != STMMAC_PCS_RGMII && 2663 priv->hw->pcs != STMMAC_PCS_TBI && 2664 priv->hw->pcs != STMMAC_PCS_RTBI) { 2665 ret = stmmac_init_phy(dev); 2666 if (ret) { 2667 netdev_err(priv->dev, 2668 "%s: Cannot attach to PHY (error: %d)\n", 2669 __func__, ret); 2670 return ret; 2671 } 2672 } 2673 2674 /* Extra statistics */ 2675 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2676 priv->xstats.threshold = tc; 2677 2678 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 2679 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2680 2681 ret = alloc_dma_desc_resources(priv); 2682 if (ret < 0) { 2683 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2684 __func__); 2685 goto dma_desc_error; 2686 } 2687 2688 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2689 if (ret < 0) { 2690 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2691 __func__); 2692 goto init_error; 2693 } 2694 2695 ret = stmmac_hw_setup(dev, true); 2696 if (ret < 0) { 2697 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2698 goto init_error; 2699 } 2700 2701 stmmac_init_coalesce(priv); 2702 2703 phylink_start(priv->phylink); 2704 2705 /* Request the IRQ lines */ 2706 ret = request_irq(dev->irq, stmmac_interrupt, 2707 IRQF_SHARED, dev->name, dev); 2708 if (unlikely(ret < 0)) { 2709 netdev_err(priv->dev, 2710 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2711 __func__, dev->irq, ret); 2712 goto irq_error; 2713 } 2714 2715 /* Request the Wake IRQ in case of another line is used for WoL */ 2716 if (priv->wol_irq != dev->irq) { 2717 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2718 IRQF_SHARED, dev->name, dev); 2719 if (unlikely(ret < 0)) { 2720 netdev_err(priv->dev, 2721 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2722 __func__, priv->wol_irq, ret); 2723 goto wolirq_error; 2724 } 2725 } 2726 2727 /* Request the IRQ lines */ 2728 if (priv->lpi_irq > 0) { 2729 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2730 dev->name, dev); 2731 if (unlikely(ret < 0)) { 2732 netdev_err(priv->dev, 2733 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2734 __func__, priv->lpi_irq, ret); 2735 goto lpiirq_error; 2736 } 2737 } 2738 2739 stmmac_enable_all_queues(priv); 2740 stmmac_start_all_queues(priv); 2741 2742 return 0; 2743 2744 lpiirq_error: 2745 if (priv->wol_irq != dev->irq) 2746 free_irq(priv->wol_irq, dev); 2747 wolirq_error: 2748 free_irq(dev->irq, dev); 2749 irq_error: 2750 phylink_stop(priv->phylink); 2751 2752 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2753 del_timer_sync(&priv->tx_queue[chan].txtimer); 2754 2755 stmmac_hw_teardown(dev); 2756 init_error: 2757 free_dma_desc_resources(priv); 2758 dma_desc_error: 2759 phylink_disconnect_phy(priv->phylink); 2760 return ret; 2761 } 2762 2763 /** 2764 * stmmac_release - close entry point of the driver 2765 * @dev : device pointer. 2766 * Description: 2767 * This is the stop entry point of the driver. 2768 */ 2769 static int stmmac_release(struct net_device *dev) 2770 { 2771 struct stmmac_priv *priv = netdev_priv(dev); 2772 u32 chan; 2773 2774 if (priv->eee_enabled) 2775 del_timer_sync(&priv->eee_ctrl_timer); 2776 2777 /* Stop and disconnect the PHY */ 2778 phylink_stop(priv->phylink); 2779 phylink_disconnect_phy(priv->phylink); 2780 2781 stmmac_stop_all_queues(priv); 2782 2783 stmmac_disable_all_queues(priv); 2784 2785 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2786 del_timer_sync(&priv->tx_queue[chan].txtimer); 2787 2788 /* Free the IRQ lines */ 2789 free_irq(dev->irq, dev); 2790 if (priv->wol_irq != dev->irq) 2791 free_irq(priv->wol_irq, dev); 2792 if (priv->lpi_irq > 0) 2793 free_irq(priv->lpi_irq, dev); 2794 2795 /* Stop TX/RX DMA and clear the descriptors */ 2796 stmmac_stop_all_dma(priv); 2797 2798 /* Release and free the Rx/Tx resources */ 2799 free_dma_desc_resources(priv); 2800 2801 /* Disable the MAC Rx/Tx */ 2802 stmmac_mac_set(priv, priv->ioaddr, false); 2803 2804 netif_carrier_off(dev); 2805 2806 stmmac_release_ptp(priv); 2807 2808 return 0; 2809 } 2810 2811 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2812 struct stmmac_tx_queue *tx_q) 2813 { 2814 u16 tag = 0x0, inner_tag = 0x0; 2815 u32 inner_type = 0x0; 2816 struct dma_desc *p; 2817 2818 if (!priv->dma_cap.vlins) 2819 return false; 2820 if (!skb_vlan_tag_present(skb)) 2821 return false; 2822 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2823 inner_tag = skb_vlan_tag_get(skb); 2824 inner_type = STMMAC_VLAN_INSERT; 2825 } 2826 2827 tag = skb_vlan_tag_get(skb); 2828 2829 p = tx_q->dma_tx + tx_q->cur_tx; 2830 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2831 return false; 2832 2833 stmmac_set_tx_owner(priv, p); 2834 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2835 return true; 2836 } 2837 2838 /** 2839 * stmmac_tso_allocator - close entry point of the driver 2840 * @priv: driver private structure 2841 * @des: buffer start address 2842 * @total_len: total length to fill in descriptors 2843 * @last_segmant: condition for the last descriptor 2844 * @queue: TX queue index 2845 * Description: 2846 * This function fills descriptor and request new descriptors according to 2847 * buffer length to fill 2848 */ 2849 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2850 int total_len, bool last_segment, u32 queue) 2851 { 2852 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2853 struct dma_desc *desc; 2854 u32 buff_size; 2855 int tmp_len; 2856 2857 tmp_len = total_len; 2858 2859 while (tmp_len > 0) { 2860 dma_addr_t curr_addr; 2861 2862 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2863 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2864 desc = tx_q->dma_tx + tx_q->cur_tx; 2865 2866 curr_addr = des + (total_len - tmp_len); 2867 if (priv->dma_cap.addr64 <= 32) 2868 desc->des0 = cpu_to_le32(curr_addr); 2869 else 2870 stmmac_set_desc_addr(priv, desc, curr_addr); 2871 2872 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2873 TSO_MAX_BUFF_SIZE : tmp_len; 2874 2875 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2876 0, 1, 2877 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2878 0, 0); 2879 2880 tmp_len -= TSO_MAX_BUFF_SIZE; 2881 } 2882 } 2883 2884 /** 2885 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2886 * @skb : the socket buffer 2887 * @dev : device pointer 2888 * Description: this is the transmit function that is called on TSO frames 2889 * (support available on GMAC4 and newer chips). 2890 * Diagram below show the ring programming in case of TSO frames: 2891 * 2892 * First Descriptor 2893 * -------- 2894 * | DES0 |---> buffer1 = L2/L3/L4 header 2895 * | DES1 |---> TCP Payload (can continue on next descr...) 2896 * | DES2 |---> buffer 1 and 2 len 2897 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2898 * -------- 2899 * | 2900 * ... 2901 * | 2902 * -------- 2903 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2904 * | DES1 | --| 2905 * | DES2 | --> buffer 1 and 2 len 2906 * | DES3 | 2907 * -------- 2908 * 2909 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2910 */ 2911 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2912 { 2913 struct dma_desc *desc, *first, *mss_desc = NULL; 2914 struct stmmac_priv *priv = netdev_priv(dev); 2915 int nfrags = skb_shinfo(skb)->nr_frags; 2916 u32 queue = skb_get_queue_mapping(skb); 2917 struct stmmac_tx_queue *tx_q; 2918 unsigned int first_entry; 2919 int tmp_pay_len = 0; 2920 u32 pay_len, mss; 2921 u8 proto_hdr_len; 2922 dma_addr_t des; 2923 bool has_vlan; 2924 int i; 2925 2926 tx_q = &priv->tx_queue[queue]; 2927 2928 /* Compute header lengths */ 2929 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2930 2931 /* Desc availability based on threshold should be enough safe */ 2932 if (unlikely(stmmac_tx_avail(priv, queue) < 2933 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2934 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2935 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2936 queue)); 2937 /* This is a hard error, log it. */ 2938 netdev_err(priv->dev, 2939 "%s: Tx Ring full when queue awake\n", 2940 __func__); 2941 } 2942 return NETDEV_TX_BUSY; 2943 } 2944 2945 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2946 2947 mss = skb_shinfo(skb)->gso_size; 2948 2949 /* set new MSS value if needed */ 2950 if (mss != tx_q->mss) { 2951 mss_desc = tx_q->dma_tx + tx_q->cur_tx; 2952 stmmac_set_mss(priv, mss_desc, mss); 2953 tx_q->mss = mss; 2954 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2955 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2956 } 2957 2958 if (netif_msg_tx_queued(priv)) { 2959 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2960 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2961 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2962 skb->data_len); 2963 } 2964 2965 /* Check if VLAN can be inserted by HW */ 2966 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 2967 2968 first_entry = tx_q->cur_tx; 2969 WARN_ON(tx_q->tx_skbuff[first_entry]); 2970 2971 desc = tx_q->dma_tx + first_entry; 2972 first = desc; 2973 2974 if (has_vlan) 2975 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 2976 2977 /* first descriptor: fill Headers on Buf1 */ 2978 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2979 DMA_TO_DEVICE); 2980 if (dma_mapping_error(priv->device, des)) 2981 goto dma_map_err; 2982 2983 tx_q->tx_skbuff_dma[first_entry].buf = des; 2984 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2985 2986 if (priv->dma_cap.addr64 <= 32) { 2987 first->des0 = cpu_to_le32(des); 2988 2989 /* Fill start of payload in buff2 of first descriptor */ 2990 if (pay_len) 2991 first->des1 = cpu_to_le32(des + proto_hdr_len); 2992 2993 /* If needed take extra descriptors to fill the remaining payload */ 2994 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2995 } else { 2996 stmmac_set_desc_addr(priv, first, des); 2997 tmp_pay_len = pay_len; 2998 des += proto_hdr_len; 2999 pay_len = 0; 3000 } 3001 3002 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3003 3004 /* Prepare fragments */ 3005 for (i = 0; i < nfrags; i++) { 3006 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3007 3008 des = skb_frag_dma_map(priv->device, frag, 0, 3009 skb_frag_size(frag), 3010 DMA_TO_DEVICE); 3011 if (dma_mapping_error(priv->device, des)) 3012 goto dma_map_err; 3013 3014 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3015 (i == nfrags - 1), queue); 3016 3017 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3018 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3019 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3020 } 3021 3022 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3023 3024 /* Only the last descriptor gets to point to the skb. */ 3025 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3026 3027 /* Manage tx mitigation */ 3028 tx_q->tx_count_frames += nfrags + 1; 3029 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3030 !((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3031 priv->hwts_tx_en)) { 3032 stmmac_tx_timer_arm(priv, queue); 3033 } else { 3034 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3035 tx_q->tx_count_frames = 0; 3036 stmmac_set_tx_ic(priv, desc); 3037 priv->xstats.tx_set_ic_bit++; 3038 } 3039 3040 /* We've used all descriptors we need for this skb, however, 3041 * advance cur_tx so that it references a fresh descriptor. 3042 * ndo_start_xmit will fill this descriptor the next time it's 3043 * called and stmmac_tx_clean may clean up to this descriptor. 3044 */ 3045 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3046 3047 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3048 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3049 __func__); 3050 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3051 } 3052 3053 dev->stats.tx_bytes += skb->len; 3054 priv->xstats.tx_tso_frames++; 3055 priv->xstats.tx_tso_nfrags += nfrags; 3056 3057 if (priv->sarc_type) 3058 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3059 3060 skb_tx_timestamp(skb); 3061 3062 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3063 priv->hwts_tx_en)) { 3064 /* declare that device is doing timestamping */ 3065 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3066 stmmac_enable_tx_timestamp(priv, first); 3067 } 3068 3069 /* Complete the first descriptor before granting the DMA */ 3070 stmmac_prepare_tso_tx_desc(priv, first, 1, 3071 proto_hdr_len, 3072 pay_len, 3073 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3074 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 3075 3076 /* If context desc is used to change MSS */ 3077 if (mss_desc) { 3078 /* Make sure that first descriptor has been completely 3079 * written, including its own bit. This is because MSS is 3080 * actually before first descriptor, so we need to make 3081 * sure that MSS's own bit is the last thing written. 3082 */ 3083 dma_wmb(); 3084 stmmac_set_tx_owner(priv, mss_desc); 3085 } 3086 3087 /* The own bit must be the latest setting done when prepare the 3088 * descriptor and then barrier is needed to make sure that 3089 * all is coherent before granting the DMA engine. 3090 */ 3091 wmb(); 3092 3093 if (netif_msg_pktdata(priv)) { 3094 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3095 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3096 tx_q->cur_tx, first, nfrags); 3097 3098 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0); 3099 3100 pr_info(">>> frame to be transmitted: "); 3101 print_pkt(skb->data, skb_headlen(skb)); 3102 } 3103 3104 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3105 3106 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3107 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3108 3109 return NETDEV_TX_OK; 3110 3111 dma_map_err: 3112 dev_err(priv->device, "Tx dma map failed\n"); 3113 dev_kfree_skb(skb); 3114 priv->dev->stats.tx_dropped++; 3115 return NETDEV_TX_OK; 3116 } 3117 3118 /** 3119 * stmmac_xmit - Tx entry point of the driver 3120 * @skb : the socket buffer 3121 * @dev : device pointer 3122 * Description : this is the tx entry point of the driver. 3123 * It programs the chain or the ring and supports oversized frames 3124 * and SG feature. 3125 */ 3126 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3127 { 3128 struct stmmac_priv *priv = netdev_priv(dev); 3129 unsigned int nopaged_len = skb_headlen(skb); 3130 int i, csum_insertion = 0, is_jumbo = 0; 3131 u32 queue = skb_get_queue_mapping(skb); 3132 int nfrags = skb_shinfo(skb)->nr_frags; 3133 struct dma_desc *desc, *first; 3134 struct stmmac_tx_queue *tx_q; 3135 unsigned int first_entry; 3136 unsigned int enh_desc; 3137 dma_addr_t des; 3138 bool has_vlan; 3139 int entry; 3140 3141 tx_q = &priv->tx_queue[queue]; 3142 3143 if (priv->tx_path_in_lpi_mode) 3144 stmmac_disable_eee_mode(priv); 3145 3146 /* Manage oversized TCP frames for GMAC4 device */ 3147 if (skb_is_gso(skb) && priv->tso) { 3148 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3149 return stmmac_tso_xmit(skb, dev); 3150 } 3151 3152 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3153 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3154 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3155 queue)); 3156 /* This is a hard error, log it. */ 3157 netdev_err(priv->dev, 3158 "%s: Tx Ring full when queue awake\n", 3159 __func__); 3160 } 3161 return NETDEV_TX_BUSY; 3162 } 3163 3164 /* Check if VLAN can be inserted by HW */ 3165 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3166 3167 entry = tx_q->cur_tx; 3168 first_entry = entry; 3169 WARN_ON(tx_q->tx_skbuff[first_entry]); 3170 3171 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3172 3173 if (likely(priv->extend_desc)) 3174 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3175 else 3176 desc = tx_q->dma_tx + entry; 3177 3178 first = desc; 3179 3180 if (has_vlan) 3181 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3182 3183 enh_desc = priv->plat->enh_desc; 3184 /* To program the descriptors according to the size of the frame */ 3185 if (enh_desc) 3186 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3187 3188 if (unlikely(is_jumbo)) { 3189 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3190 if (unlikely(entry < 0) && (entry != -EINVAL)) 3191 goto dma_map_err; 3192 } 3193 3194 for (i = 0; i < nfrags; i++) { 3195 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3196 int len = skb_frag_size(frag); 3197 bool last_segment = (i == (nfrags - 1)); 3198 3199 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3200 WARN_ON(tx_q->tx_skbuff[entry]); 3201 3202 if (likely(priv->extend_desc)) 3203 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3204 else 3205 desc = tx_q->dma_tx + entry; 3206 3207 des = skb_frag_dma_map(priv->device, frag, 0, len, 3208 DMA_TO_DEVICE); 3209 if (dma_mapping_error(priv->device, des)) 3210 goto dma_map_err; /* should reuse desc w/o issues */ 3211 3212 tx_q->tx_skbuff_dma[entry].buf = des; 3213 3214 stmmac_set_desc_addr(priv, desc, des); 3215 3216 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3217 tx_q->tx_skbuff_dma[entry].len = len; 3218 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3219 3220 /* Prepare the descriptor and set the own bit too */ 3221 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3222 priv->mode, 1, last_segment, skb->len); 3223 } 3224 3225 /* Only the last descriptor gets to point to the skb. */ 3226 tx_q->tx_skbuff[entry] = skb; 3227 3228 /* According to the coalesce parameter the IC bit for the latest 3229 * segment is reset and the timer re-started to clean the tx status. 3230 * This approach takes care about the fragments: desc is the first 3231 * element in case of no SG. 3232 */ 3233 tx_q->tx_count_frames += nfrags + 1; 3234 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3235 !((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3236 priv->hwts_tx_en)) { 3237 stmmac_tx_timer_arm(priv, queue); 3238 } else { 3239 if (likely(priv->extend_desc)) 3240 desc = &tx_q->dma_etx[entry].basic; 3241 else 3242 desc = &tx_q->dma_tx[entry]; 3243 3244 tx_q->tx_count_frames = 0; 3245 stmmac_set_tx_ic(priv, desc); 3246 priv->xstats.tx_set_ic_bit++; 3247 } 3248 3249 /* We've used all descriptors we need for this skb, however, 3250 * advance cur_tx so that it references a fresh descriptor. 3251 * ndo_start_xmit will fill this descriptor the next time it's 3252 * called and stmmac_tx_clean may clean up to this descriptor. 3253 */ 3254 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3255 tx_q->cur_tx = entry; 3256 3257 if (netif_msg_pktdata(priv)) { 3258 void *tx_head; 3259 3260 netdev_dbg(priv->dev, 3261 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3262 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3263 entry, first, nfrags); 3264 3265 if (priv->extend_desc) 3266 tx_head = (void *)tx_q->dma_etx; 3267 else 3268 tx_head = (void *)tx_q->dma_tx; 3269 3270 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false); 3271 3272 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3273 print_pkt(skb->data, skb->len); 3274 } 3275 3276 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3277 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3278 __func__); 3279 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3280 } 3281 3282 dev->stats.tx_bytes += skb->len; 3283 3284 if (priv->sarc_type) 3285 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3286 3287 skb_tx_timestamp(skb); 3288 3289 /* Ready to fill the first descriptor and set the OWN bit w/o any 3290 * problems because all the descriptors are actually ready to be 3291 * passed to the DMA engine. 3292 */ 3293 if (likely(!is_jumbo)) { 3294 bool last_segment = (nfrags == 0); 3295 3296 des = dma_map_single(priv->device, skb->data, 3297 nopaged_len, DMA_TO_DEVICE); 3298 if (dma_mapping_error(priv->device, des)) 3299 goto dma_map_err; 3300 3301 tx_q->tx_skbuff_dma[first_entry].buf = des; 3302 3303 stmmac_set_desc_addr(priv, first, des); 3304 3305 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3306 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3307 3308 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3309 priv->hwts_tx_en)) { 3310 /* declare that device is doing timestamping */ 3311 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3312 stmmac_enable_tx_timestamp(priv, first); 3313 } 3314 3315 /* Prepare the first descriptor setting the OWN bit too */ 3316 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3317 csum_insertion, priv->mode, 1, last_segment, 3318 skb->len); 3319 } else { 3320 stmmac_set_tx_owner(priv, first); 3321 } 3322 3323 /* The own bit must be the latest setting done when prepare the 3324 * descriptor and then barrier is needed to make sure that 3325 * all is coherent before granting the DMA engine. 3326 */ 3327 wmb(); 3328 3329 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3330 3331 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3332 3333 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3334 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3335 3336 return NETDEV_TX_OK; 3337 3338 dma_map_err: 3339 netdev_err(priv->dev, "Tx DMA map failed\n"); 3340 dev_kfree_skb(skb); 3341 priv->dev->stats.tx_dropped++; 3342 return NETDEV_TX_OK; 3343 } 3344 3345 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3346 { 3347 struct vlan_ethhdr *veth; 3348 __be16 vlan_proto; 3349 u16 vlanid; 3350 3351 veth = (struct vlan_ethhdr *)skb->data; 3352 vlan_proto = veth->h_vlan_proto; 3353 3354 if ((vlan_proto == htons(ETH_P_8021Q) && 3355 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3356 (vlan_proto == htons(ETH_P_8021AD) && 3357 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3358 /* pop the vlan tag */ 3359 vlanid = ntohs(veth->h_vlan_TCI); 3360 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3361 skb_pull(skb, VLAN_HLEN); 3362 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3363 } 3364 } 3365 3366 3367 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3368 { 3369 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3370 return 0; 3371 3372 return 1; 3373 } 3374 3375 /** 3376 * stmmac_rx_refill - refill used skb preallocated buffers 3377 * @priv: driver private structure 3378 * @queue: RX queue index 3379 * Description : this is to reallocate the skb for the reception process 3380 * that is based on zero-copy. 3381 */ 3382 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3383 { 3384 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3385 int len, dirty = stmmac_rx_dirty(priv, queue); 3386 unsigned int entry = rx_q->dirty_rx; 3387 3388 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3389 3390 while (dirty-- > 0) { 3391 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3392 struct dma_desc *p; 3393 bool use_rx_wd; 3394 3395 if (priv->extend_desc) 3396 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3397 else 3398 p = rx_q->dma_rx + entry; 3399 3400 if (!buf->page) { 3401 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3402 if (!buf->page) 3403 break; 3404 } 3405 3406 if (priv->sph && !buf->sec_page) { 3407 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3408 if (!buf->sec_page) 3409 break; 3410 3411 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3412 3413 dma_sync_single_for_device(priv->device, buf->sec_addr, 3414 len, DMA_FROM_DEVICE); 3415 } 3416 3417 buf->addr = page_pool_get_dma_addr(buf->page); 3418 3419 /* Sync whole allocation to device. This will invalidate old 3420 * data. 3421 */ 3422 dma_sync_single_for_device(priv->device, buf->addr, len, 3423 DMA_FROM_DEVICE); 3424 3425 stmmac_set_desc_addr(priv, p, buf->addr); 3426 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3427 stmmac_refill_desc3(priv, rx_q, p); 3428 3429 rx_q->rx_count_frames++; 3430 rx_q->rx_count_frames += priv->rx_coal_frames; 3431 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3432 rx_q->rx_count_frames = 0; 3433 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames; 3434 3435 dma_wmb(); 3436 stmmac_set_rx_owner(priv, p, use_rx_wd); 3437 3438 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3439 } 3440 rx_q->dirty_rx = entry; 3441 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3442 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3443 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3444 } 3445 3446 /** 3447 * stmmac_rx - manage the receive process 3448 * @priv: driver private structure 3449 * @limit: napi bugget 3450 * @queue: RX queue index. 3451 * Description : this the function called by the napi poll method. 3452 * It gets all the frames inside the ring. 3453 */ 3454 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3455 { 3456 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3457 struct stmmac_channel *ch = &priv->channel[queue]; 3458 unsigned int count = 0, error = 0, len = 0; 3459 int status = 0, coe = priv->hw->rx_csum; 3460 unsigned int next_entry = rx_q->cur_rx; 3461 struct sk_buff *skb = NULL; 3462 3463 if (netif_msg_rx_status(priv)) { 3464 void *rx_head; 3465 3466 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3467 if (priv->extend_desc) 3468 rx_head = (void *)rx_q->dma_erx; 3469 else 3470 rx_head = (void *)rx_q->dma_rx; 3471 3472 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3473 } 3474 while (count < limit) { 3475 unsigned int hlen = 0, prev_len = 0; 3476 enum pkt_hash_types hash_type; 3477 struct stmmac_rx_buffer *buf; 3478 struct dma_desc *np, *p; 3479 unsigned int sec_len; 3480 int entry; 3481 u32 hash; 3482 3483 if (!count && rx_q->state_saved) { 3484 skb = rx_q->state.skb; 3485 error = rx_q->state.error; 3486 len = rx_q->state.len; 3487 } else { 3488 rx_q->state_saved = false; 3489 skb = NULL; 3490 error = 0; 3491 len = 0; 3492 } 3493 3494 if (count >= limit) 3495 break; 3496 3497 read_again: 3498 sec_len = 0; 3499 entry = next_entry; 3500 buf = &rx_q->buf_pool[entry]; 3501 3502 if (priv->extend_desc) 3503 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3504 else 3505 p = rx_q->dma_rx + entry; 3506 3507 /* read the status of the incoming frame */ 3508 status = stmmac_rx_status(priv, &priv->dev->stats, 3509 &priv->xstats, p); 3510 /* check if managed by the DMA otherwise go ahead */ 3511 if (unlikely(status & dma_own)) 3512 break; 3513 3514 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3515 next_entry = rx_q->cur_rx; 3516 3517 if (priv->extend_desc) 3518 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3519 else 3520 np = rx_q->dma_rx + next_entry; 3521 3522 prefetch(np); 3523 prefetch(page_address(buf->page)); 3524 3525 if (priv->extend_desc) 3526 stmmac_rx_extended_status(priv, &priv->dev->stats, 3527 &priv->xstats, rx_q->dma_erx + entry); 3528 if (unlikely(status == discard_frame)) { 3529 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3530 buf->page = NULL; 3531 error = 1; 3532 if (!priv->hwts_rx_en) 3533 priv->dev->stats.rx_errors++; 3534 } 3535 3536 if (unlikely(error && (status & rx_not_ls))) 3537 goto read_again; 3538 if (unlikely(error)) { 3539 dev_kfree_skb(skb); 3540 count++; 3541 continue; 3542 } 3543 3544 /* Buffer is good. Go on. */ 3545 3546 if (likely(status & rx_not_ls)) { 3547 len += priv->dma_buf_sz; 3548 } else { 3549 prev_len = len; 3550 len = stmmac_get_rx_frame_len(priv, p, coe); 3551 3552 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3553 * Type frames (LLC/LLC-SNAP) 3554 * 3555 * llc_snap is never checked in GMAC >= 4, so this ACS 3556 * feature is always disabled and packets need to be 3557 * stripped manually. 3558 */ 3559 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3560 unlikely(status != llc_snap)) 3561 len -= ETH_FCS_LEN; 3562 } 3563 3564 if (!skb) { 3565 int ret = stmmac_get_rx_header_len(priv, p, &hlen); 3566 3567 if (priv->sph && !ret && (hlen > 0)) { 3568 sec_len = len; 3569 if (!(status & rx_not_ls)) 3570 sec_len = sec_len - hlen; 3571 len = hlen; 3572 3573 prefetch(page_address(buf->sec_page)); 3574 priv->xstats.rx_split_hdr_pkt_n++; 3575 } 3576 3577 skb = napi_alloc_skb(&ch->rx_napi, len); 3578 if (!skb) { 3579 priv->dev->stats.rx_dropped++; 3580 count++; 3581 continue; 3582 } 3583 3584 dma_sync_single_for_cpu(priv->device, buf->addr, len, 3585 DMA_FROM_DEVICE); 3586 skb_copy_to_linear_data(skb, page_address(buf->page), 3587 len); 3588 skb_put(skb, len); 3589 3590 /* Data payload copied into SKB, page ready for recycle */ 3591 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3592 buf->page = NULL; 3593 } else { 3594 unsigned int buf_len = len - prev_len; 3595 3596 if (likely(status & rx_not_ls)) 3597 buf_len = priv->dma_buf_sz; 3598 3599 dma_sync_single_for_cpu(priv->device, buf->addr, 3600 buf_len, DMA_FROM_DEVICE); 3601 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3602 buf->page, 0, buf_len, 3603 priv->dma_buf_sz); 3604 3605 /* Data payload appended into SKB */ 3606 page_pool_release_page(rx_q->page_pool, buf->page); 3607 buf->page = NULL; 3608 } 3609 3610 if (sec_len > 0) { 3611 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3612 sec_len, DMA_FROM_DEVICE); 3613 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3614 buf->sec_page, 0, sec_len, 3615 priv->dma_buf_sz); 3616 3617 len += sec_len; 3618 3619 /* Data payload appended into SKB */ 3620 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3621 buf->sec_page = NULL; 3622 } 3623 3624 if (likely(status & rx_not_ls)) 3625 goto read_again; 3626 3627 /* Got entire packet into SKB. Finish it. */ 3628 3629 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3630 stmmac_rx_vlan(priv->dev, skb); 3631 skb->protocol = eth_type_trans(skb, priv->dev); 3632 3633 if (unlikely(!coe)) 3634 skb_checksum_none_assert(skb); 3635 else 3636 skb->ip_summed = CHECKSUM_UNNECESSARY; 3637 3638 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3639 skb_set_hash(skb, hash, hash_type); 3640 3641 skb_record_rx_queue(skb, queue); 3642 napi_gro_receive(&ch->rx_napi, skb); 3643 3644 priv->dev->stats.rx_packets++; 3645 priv->dev->stats.rx_bytes += len; 3646 count++; 3647 } 3648 3649 if (status & rx_not_ls) { 3650 rx_q->state_saved = true; 3651 rx_q->state.skb = skb; 3652 rx_q->state.error = error; 3653 rx_q->state.len = len; 3654 } 3655 3656 stmmac_rx_refill(priv, queue); 3657 3658 priv->xstats.rx_pkt_n += count; 3659 3660 return count; 3661 } 3662 3663 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3664 { 3665 struct stmmac_channel *ch = 3666 container_of(napi, struct stmmac_channel, rx_napi); 3667 struct stmmac_priv *priv = ch->priv_data; 3668 u32 chan = ch->index; 3669 int work_done; 3670 3671 priv->xstats.napi_poll++; 3672 3673 work_done = stmmac_rx(priv, budget, chan); 3674 if (work_done < budget && napi_complete_done(napi, work_done)) 3675 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3676 return work_done; 3677 } 3678 3679 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3680 { 3681 struct stmmac_channel *ch = 3682 container_of(napi, struct stmmac_channel, tx_napi); 3683 struct stmmac_priv *priv = ch->priv_data; 3684 struct stmmac_tx_queue *tx_q; 3685 u32 chan = ch->index; 3686 int work_done; 3687 3688 priv->xstats.napi_poll++; 3689 3690 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3691 work_done = min(work_done, budget); 3692 3693 if (work_done < budget) 3694 napi_complete_done(napi, work_done); 3695 3696 /* Force transmission restart */ 3697 tx_q = &priv->tx_queue[chan]; 3698 if (tx_q->cur_tx != tx_q->dirty_tx) { 3699 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3700 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, 3701 chan); 3702 } 3703 3704 return work_done; 3705 } 3706 3707 /** 3708 * stmmac_tx_timeout 3709 * @dev : Pointer to net device structure 3710 * Description: this function is called when a packet transmission fails to 3711 * complete within a reasonable time. The driver will mark the error in the 3712 * netdev structure and arrange for the device to be reset to a sane state 3713 * in order to transmit a new packet. 3714 */ 3715 static void stmmac_tx_timeout(struct net_device *dev) 3716 { 3717 struct stmmac_priv *priv = netdev_priv(dev); 3718 3719 stmmac_global_err(priv); 3720 } 3721 3722 /** 3723 * stmmac_set_rx_mode - entry point for multicast addressing 3724 * @dev : pointer to the device structure 3725 * Description: 3726 * This function is a driver entry point which gets called by the kernel 3727 * whenever multicast addresses must be enabled/disabled. 3728 * Return value: 3729 * void. 3730 */ 3731 static void stmmac_set_rx_mode(struct net_device *dev) 3732 { 3733 struct stmmac_priv *priv = netdev_priv(dev); 3734 3735 stmmac_set_filter(priv, priv->hw, dev); 3736 } 3737 3738 /** 3739 * stmmac_change_mtu - entry point to change MTU size for the device. 3740 * @dev : device pointer. 3741 * @new_mtu : the new MTU size for the device. 3742 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3743 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3744 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3745 * Return value: 3746 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3747 * file on failure. 3748 */ 3749 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3750 { 3751 struct stmmac_priv *priv = netdev_priv(dev); 3752 3753 if (netif_running(dev)) { 3754 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3755 return -EBUSY; 3756 } 3757 3758 dev->mtu = new_mtu; 3759 3760 netdev_update_features(dev); 3761 3762 return 0; 3763 } 3764 3765 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3766 netdev_features_t features) 3767 { 3768 struct stmmac_priv *priv = netdev_priv(dev); 3769 3770 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3771 features &= ~NETIF_F_RXCSUM; 3772 3773 if (!priv->plat->tx_coe) 3774 features &= ~NETIF_F_CSUM_MASK; 3775 3776 /* Some GMAC devices have a bugged Jumbo frame support that 3777 * needs to have the Tx COE disabled for oversized frames 3778 * (due to limited buffer sizes). In this case we disable 3779 * the TX csum insertion in the TDES and not use SF. 3780 */ 3781 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3782 features &= ~NETIF_F_CSUM_MASK; 3783 3784 /* Disable tso if asked by ethtool */ 3785 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3786 if (features & NETIF_F_TSO) 3787 priv->tso = true; 3788 else 3789 priv->tso = false; 3790 } 3791 3792 return features; 3793 } 3794 3795 static int stmmac_set_features(struct net_device *netdev, 3796 netdev_features_t features) 3797 { 3798 struct stmmac_priv *priv = netdev_priv(netdev); 3799 bool sph_en; 3800 u32 chan; 3801 3802 /* Keep the COE Type in case of csum is supporting */ 3803 if (features & NETIF_F_RXCSUM) 3804 priv->hw->rx_csum = priv->plat->rx_coe; 3805 else 3806 priv->hw->rx_csum = 0; 3807 /* No check needed because rx_coe has been set before and it will be 3808 * fixed in case of issue. 3809 */ 3810 stmmac_rx_ipc(priv, priv->hw); 3811 3812 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3813 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 3814 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3815 3816 return 0; 3817 } 3818 3819 /** 3820 * stmmac_interrupt - main ISR 3821 * @irq: interrupt number. 3822 * @dev_id: to pass the net device pointer. 3823 * Description: this is the main driver interrupt service routine. 3824 * It can call: 3825 * o DMA service routine (to manage incoming frame reception and transmission 3826 * status) 3827 * o Core interrupts to manage: remote wake-up, management counter, LPI 3828 * interrupts. 3829 */ 3830 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 3831 { 3832 struct net_device *dev = (struct net_device *)dev_id; 3833 struct stmmac_priv *priv = netdev_priv(dev); 3834 u32 rx_cnt = priv->plat->rx_queues_to_use; 3835 u32 tx_cnt = priv->plat->tx_queues_to_use; 3836 u32 queues_count; 3837 u32 queue; 3838 bool xmac; 3839 3840 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3841 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 3842 3843 if (priv->irq_wake) 3844 pm_wakeup_event(priv->device, 0); 3845 3846 if (unlikely(!dev)) { 3847 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 3848 return IRQ_NONE; 3849 } 3850 3851 /* Check if adapter is up */ 3852 if (test_bit(STMMAC_DOWN, &priv->state)) 3853 return IRQ_HANDLED; 3854 /* Check if a fatal error happened */ 3855 if (stmmac_safety_feat_interrupt(priv)) 3856 return IRQ_HANDLED; 3857 3858 /* To handle GMAC own interrupts */ 3859 if ((priv->plat->has_gmac) || xmac) { 3860 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 3861 int mtl_status; 3862 3863 if (unlikely(status)) { 3864 /* For LPI we need to save the tx status */ 3865 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 3866 priv->tx_path_in_lpi_mode = true; 3867 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 3868 priv->tx_path_in_lpi_mode = false; 3869 } 3870 3871 for (queue = 0; queue < queues_count; queue++) { 3872 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3873 3874 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 3875 queue); 3876 if (mtl_status != -EINVAL) 3877 status |= mtl_status; 3878 3879 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 3880 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3881 rx_q->rx_tail_addr, 3882 queue); 3883 } 3884 3885 /* PCS link status */ 3886 if (priv->hw->pcs) { 3887 if (priv->xstats.pcs_link) 3888 netif_carrier_on(dev); 3889 else 3890 netif_carrier_off(dev); 3891 } 3892 } 3893 3894 /* To handle DMA interrupts */ 3895 stmmac_dma_interrupt(priv); 3896 3897 return IRQ_HANDLED; 3898 } 3899 3900 #ifdef CONFIG_NET_POLL_CONTROLLER 3901 /* Polling receive - used by NETCONSOLE and other diagnostic tools 3902 * to allow network I/O with interrupts disabled. 3903 */ 3904 static void stmmac_poll_controller(struct net_device *dev) 3905 { 3906 disable_irq(dev->irq); 3907 stmmac_interrupt(dev->irq, dev); 3908 enable_irq(dev->irq); 3909 } 3910 #endif 3911 3912 /** 3913 * stmmac_ioctl - Entry point for the Ioctl 3914 * @dev: Device pointer. 3915 * @rq: An IOCTL specefic structure, that can contain a pointer to 3916 * a proprietary structure used to pass information to the driver. 3917 * @cmd: IOCTL command 3918 * Description: 3919 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 3920 */ 3921 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3922 { 3923 struct stmmac_priv *priv = netdev_priv (dev); 3924 int ret = -EOPNOTSUPP; 3925 3926 if (!netif_running(dev)) 3927 return -EINVAL; 3928 3929 switch (cmd) { 3930 case SIOCGMIIPHY: 3931 case SIOCGMIIREG: 3932 case SIOCSMIIREG: 3933 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 3934 break; 3935 case SIOCSHWTSTAMP: 3936 ret = stmmac_hwtstamp_set(dev, rq); 3937 break; 3938 case SIOCGHWTSTAMP: 3939 ret = stmmac_hwtstamp_get(dev, rq); 3940 break; 3941 default: 3942 break; 3943 } 3944 3945 return ret; 3946 } 3947 3948 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3949 void *cb_priv) 3950 { 3951 struct stmmac_priv *priv = cb_priv; 3952 int ret = -EOPNOTSUPP; 3953 3954 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 3955 return ret; 3956 3957 stmmac_disable_all_queues(priv); 3958 3959 switch (type) { 3960 case TC_SETUP_CLSU32: 3961 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 3962 break; 3963 case TC_SETUP_CLSFLOWER: 3964 ret = stmmac_tc_setup_cls(priv, priv, type_data); 3965 break; 3966 default: 3967 break; 3968 } 3969 3970 stmmac_enable_all_queues(priv); 3971 return ret; 3972 } 3973 3974 static LIST_HEAD(stmmac_block_cb_list); 3975 3976 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 3977 void *type_data) 3978 { 3979 struct stmmac_priv *priv = netdev_priv(ndev); 3980 3981 switch (type) { 3982 case TC_SETUP_BLOCK: 3983 return flow_block_cb_setup_simple(type_data, 3984 &stmmac_block_cb_list, 3985 stmmac_setup_tc_block_cb, 3986 priv, priv, true); 3987 case TC_SETUP_QDISC_CBS: 3988 return stmmac_tc_setup_cbs(priv, priv, type_data); 3989 default: 3990 return -EOPNOTSUPP; 3991 } 3992 } 3993 3994 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 3995 struct net_device *sb_dev) 3996 { 3997 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 3998 /* 3999 * There is no way to determine the number of TSO 4000 * capable Queues. Let's use always the Queue 0 4001 * because if TSO is supported then at least this 4002 * one will be capable. 4003 */ 4004 return 0; 4005 } 4006 4007 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4008 } 4009 4010 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4011 { 4012 struct stmmac_priv *priv = netdev_priv(ndev); 4013 int ret = 0; 4014 4015 ret = eth_mac_addr(ndev, addr); 4016 if (ret) 4017 return ret; 4018 4019 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4020 4021 return ret; 4022 } 4023 4024 #ifdef CONFIG_DEBUG_FS 4025 static struct dentry *stmmac_fs_dir; 4026 4027 static void sysfs_display_ring(void *head, int size, int extend_desc, 4028 struct seq_file *seq) 4029 { 4030 int i; 4031 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4032 struct dma_desc *p = (struct dma_desc *)head; 4033 4034 for (i = 0; i < size; i++) { 4035 if (extend_desc) { 4036 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4037 i, (unsigned int)virt_to_phys(ep), 4038 le32_to_cpu(ep->basic.des0), 4039 le32_to_cpu(ep->basic.des1), 4040 le32_to_cpu(ep->basic.des2), 4041 le32_to_cpu(ep->basic.des3)); 4042 ep++; 4043 } else { 4044 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4045 i, (unsigned int)virt_to_phys(p), 4046 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4047 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4048 p++; 4049 } 4050 seq_printf(seq, "\n"); 4051 } 4052 } 4053 4054 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4055 { 4056 struct net_device *dev = seq->private; 4057 struct stmmac_priv *priv = netdev_priv(dev); 4058 u32 rx_count = priv->plat->rx_queues_to_use; 4059 u32 tx_count = priv->plat->tx_queues_to_use; 4060 u32 queue; 4061 4062 if ((dev->flags & IFF_UP) == 0) 4063 return 0; 4064 4065 for (queue = 0; queue < rx_count; queue++) { 4066 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4067 4068 seq_printf(seq, "RX Queue %d:\n", queue); 4069 4070 if (priv->extend_desc) { 4071 seq_printf(seq, "Extended descriptor ring:\n"); 4072 sysfs_display_ring((void *)rx_q->dma_erx, 4073 DMA_RX_SIZE, 1, seq); 4074 } else { 4075 seq_printf(seq, "Descriptor ring:\n"); 4076 sysfs_display_ring((void *)rx_q->dma_rx, 4077 DMA_RX_SIZE, 0, seq); 4078 } 4079 } 4080 4081 for (queue = 0; queue < tx_count; queue++) { 4082 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4083 4084 seq_printf(seq, "TX Queue %d:\n", queue); 4085 4086 if (priv->extend_desc) { 4087 seq_printf(seq, "Extended descriptor ring:\n"); 4088 sysfs_display_ring((void *)tx_q->dma_etx, 4089 DMA_TX_SIZE, 1, seq); 4090 } else { 4091 seq_printf(seq, "Descriptor ring:\n"); 4092 sysfs_display_ring((void *)tx_q->dma_tx, 4093 DMA_TX_SIZE, 0, seq); 4094 } 4095 } 4096 4097 return 0; 4098 } 4099 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4100 4101 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4102 { 4103 struct net_device *dev = seq->private; 4104 struct stmmac_priv *priv = netdev_priv(dev); 4105 4106 if (!priv->hw_cap_support) { 4107 seq_printf(seq, "DMA HW features not supported\n"); 4108 return 0; 4109 } 4110 4111 seq_printf(seq, "==============================\n"); 4112 seq_printf(seq, "\tDMA HW features\n"); 4113 seq_printf(seq, "==============================\n"); 4114 4115 seq_printf(seq, "\t10/100 Mbps: %s\n", 4116 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4117 seq_printf(seq, "\t1000 Mbps: %s\n", 4118 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4119 seq_printf(seq, "\tHalf duplex: %s\n", 4120 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4121 seq_printf(seq, "\tHash Filter: %s\n", 4122 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4123 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4124 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4125 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4126 (priv->dma_cap.pcs) ? "Y" : "N"); 4127 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4128 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4129 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4130 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4131 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4132 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4133 seq_printf(seq, "\tRMON module: %s\n", 4134 (priv->dma_cap.rmon) ? "Y" : "N"); 4135 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4136 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4137 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4138 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4139 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4140 (priv->dma_cap.eee) ? "Y" : "N"); 4141 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4142 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4143 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4144 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4145 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4146 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4147 } else { 4148 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4149 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4150 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4151 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4152 } 4153 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4154 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4155 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4156 priv->dma_cap.number_rx_channel); 4157 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4158 priv->dma_cap.number_tx_channel); 4159 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4160 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4161 4162 return 0; 4163 } 4164 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4165 4166 static void stmmac_init_fs(struct net_device *dev) 4167 { 4168 struct stmmac_priv *priv = netdev_priv(dev); 4169 4170 /* Create per netdev entries */ 4171 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4172 4173 /* Entry to report DMA RX/TX rings */ 4174 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4175 &stmmac_rings_status_fops); 4176 4177 /* Entry to report the DMA HW features */ 4178 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4179 &stmmac_dma_cap_fops); 4180 } 4181 4182 static void stmmac_exit_fs(struct net_device *dev) 4183 { 4184 struct stmmac_priv *priv = netdev_priv(dev); 4185 4186 debugfs_remove_recursive(priv->dbgfs_dir); 4187 } 4188 #endif /* CONFIG_DEBUG_FS */ 4189 4190 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4191 { 4192 unsigned char *data = (unsigned char *)&vid_le; 4193 unsigned char data_byte = 0; 4194 u32 crc = ~0x0; 4195 u32 temp = 0; 4196 int i, bits; 4197 4198 bits = get_bitmask_order(VLAN_VID_MASK); 4199 for (i = 0; i < bits; i++) { 4200 if ((i % 8) == 0) 4201 data_byte = data[i / 8]; 4202 4203 temp = ((crc & 1) ^ data_byte) & 1; 4204 crc >>= 1; 4205 data_byte >>= 1; 4206 4207 if (temp) 4208 crc ^= 0xedb88320; 4209 } 4210 4211 return crc; 4212 } 4213 4214 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4215 { 4216 u32 crc, hash = 0; 4217 u16 vid; 4218 4219 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4220 __le16 vid_le = cpu_to_le16(vid); 4221 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4222 hash |= (1 << crc); 4223 } 4224 4225 return stmmac_update_vlan_hash(priv, priv->hw, hash, is_double); 4226 } 4227 4228 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4229 { 4230 struct stmmac_priv *priv = netdev_priv(ndev); 4231 bool is_double = false; 4232 int ret; 4233 4234 if (!priv->dma_cap.vlhash) 4235 return -EOPNOTSUPP; 4236 if (be16_to_cpu(proto) == ETH_P_8021AD) 4237 is_double = true; 4238 4239 set_bit(vid, priv->active_vlans); 4240 ret = stmmac_vlan_update(priv, is_double); 4241 if (ret) { 4242 clear_bit(vid, priv->active_vlans); 4243 return ret; 4244 } 4245 4246 return ret; 4247 } 4248 4249 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4250 { 4251 struct stmmac_priv *priv = netdev_priv(ndev); 4252 bool is_double = false; 4253 4254 if (!priv->dma_cap.vlhash) 4255 return -EOPNOTSUPP; 4256 if (be16_to_cpu(proto) == ETH_P_8021AD) 4257 is_double = true; 4258 4259 clear_bit(vid, priv->active_vlans); 4260 return stmmac_vlan_update(priv, is_double); 4261 } 4262 4263 static const struct net_device_ops stmmac_netdev_ops = { 4264 .ndo_open = stmmac_open, 4265 .ndo_start_xmit = stmmac_xmit, 4266 .ndo_stop = stmmac_release, 4267 .ndo_change_mtu = stmmac_change_mtu, 4268 .ndo_fix_features = stmmac_fix_features, 4269 .ndo_set_features = stmmac_set_features, 4270 .ndo_set_rx_mode = stmmac_set_rx_mode, 4271 .ndo_tx_timeout = stmmac_tx_timeout, 4272 .ndo_do_ioctl = stmmac_ioctl, 4273 .ndo_setup_tc = stmmac_setup_tc, 4274 .ndo_select_queue = stmmac_select_queue, 4275 #ifdef CONFIG_NET_POLL_CONTROLLER 4276 .ndo_poll_controller = stmmac_poll_controller, 4277 #endif 4278 .ndo_set_mac_address = stmmac_set_mac_address, 4279 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4280 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4281 }; 4282 4283 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4284 { 4285 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4286 return; 4287 if (test_bit(STMMAC_DOWN, &priv->state)) 4288 return; 4289 4290 netdev_err(priv->dev, "Reset adapter.\n"); 4291 4292 rtnl_lock(); 4293 netif_trans_update(priv->dev); 4294 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4295 usleep_range(1000, 2000); 4296 4297 set_bit(STMMAC_DOWN, &priv->state); 4298 dev_close(priv->dev); 4299 dev_open(priv->dev, NULL); 4300 clear_bit(STMMAC_DOWN, &priv->state); 4301 clear_bit(STMMAC_RESETING, &priv->state); 4302 rtnl_unlock(); 4303 } 4304 4305 static void stmmac_service_task(struct work_struct *work) 4306 { 4307 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4308 service_task); 4309 4310 stmmac_reset_subtask(priv); 4311 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4312 } 4313 4314 /** 4315 * stmmac_hw_init - Init the MAC device 4316 * @priv: driver private structure 4317 * Description: this function is to configure the MAC device according to 4318 * some platform parameters or the HW capability register. It prepares the 4319 * driver to use either ring or chain modes and to setup either enhanced or 4320 * normal descriptors. 4321 */ 4322 static int stmmac_hw_init(struct stmmac_priv *priv) 4323 { 4324 int ret; 4325 4326 /* dwmac-sun8i only work in chain mode */ 4327 if (priv->plat->has_sun8i) 4328 chain_mode = 1; 4329 priv->chain_mode = chain_mode; 4330 4331 /* Initialize HW Interface */ 4332 ret = stmmac_hwif_init(priv); 4333 if (ret) 4334 return ret; 4335 4336 /* Get the HW capability (new GMAC newer than 3.50a) */ 4337 priv->hw_cap_support = stmmac_get_hw_features(priv); 4338 if (priv->hw_cap_support) { 4339 dev_info(priv->device, "DMA HW capability register supported\n"); 4340 4341 /* We can override some gmac/dma configuration fields: e.g. 4342 * enh_desc, tx_coe (e.g. that are passed through the 4343 * platform) with the values from the HW capability 4344 * register (if supported). 4345 */ 4346 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4347 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4348 priv->hw->pmt = priv->plat->pmt; 4349 if (priv->dma_cap.hash_tb_sz) { 4350 priv->hw->multicast_filter_bins = 4351 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4352 priv->hw->mcast_bits_log2 = 4353 ilog2(priv->hw->multicast_filter_bins); 4354 } 4355 4356 /* TXCOE doesn't work in thresh DMA mode */ 4357 if (priv->plat->force_thresh_dma_mode) 4358 priv->plat->tx_coe = 0; 4359 else 4360 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4361 4362 /* In case of GMAC4 rx_coe is from HW cap register. */ 4363 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4364 4365 if (priv->dma_cap.rx_coe_type2) 4366 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4367 else if (priv->dma_cap.rx_coe_type1) 4368 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4369 4370 } else { 4371 dev_info(priv->device, "No HW DMA feature register supported\n"); 4372 } 4373 4374 if (priv->plat->rx_coe) { 4375 priv->hw->rx_csum = priv->plat->rx_coe; 4376 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4377 if (priv->synopsys_id < DWMAC_CORE_4_00) 4378 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4379 } 4380 if (priv->plat->tx_coe) 4381 dev_info(priv->device, "TX Checksum insertion supported\n"); 4382 4383 if (priv->plat->pmt) { 4384 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4385 device_set_wakeup_capable(priv->device, 1); 4386 } 4387 4388 if (priv->dma_cap.tsoen) 4389 dev_info(priv->device, "TSO supported\n"); 4390 4391 /* Run HW quirks, if any */ 4392 if (priv->hwif_quirks) { 4393 ret = priv->hwif_quirks(priv); 4394 if (ret) 4395 return ret; 4396 } 4397 4398 /* Rx Watchdog is available in the COREs newer than the 3.40. 4399 * In some case, for example on bugged HW this feature 4400 * has to be disable and this can be done by passing the 4401 * riwt_off field from the platform. 4402 */ 4403 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4404 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4405 priv->use_riwt = 1; 4406 dev_info(priv->device, 4407 "Enable RX Mitigation via HW Watchdog Timer\n"); 4408 } 4409 4410 return 0; 4411 } 4412 4413 /** 4414 * stmmac_dvr_probe 4415 * @device: device pointer 4416 * @plat_dat: platform data pointer 4417 * @res: stmmac resource pointer 4418 * Description: this is the main probe function used to 4419 * call the alloc_etherdev, allocate the priv structure. 4420 * Return: 4421 * returns 0 on success, otherwise errno. 4422 */ 4423 int stmmac_dvr_probe(struct device *device, 4424 struct plat_stmmacenet_data *plat_dat, 4425 struct stmmac_resources *res) 4426 { 4427 struct net_device *ndev = NULL; 4428 struct stmmac_priv *priv; 4429 u32 queue, rxq, maxq; 4430 int i, ret = 0; 4431 4432 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4433 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4434 if (!ndev) 4435 return -ENOMEM; 4436 4437 SET_NETDEV_DEV(ndev, device); 4438 4439 priv = netdev_priv(ndev); 4440 priv->device = device; 4441 priv->dev = ndev; 4442 4443 stmmac_set_ethtool_ops(ndev); 4444 priv->pause = pause; 4445 priv->plat = plat_dat; 4446 priv->ioaddr = res->addr; 4447 priv->dev->base_addr = (unsigned long)res->addr; 4448 4449 priv->dev->irq = res->irq; 4450 priv->wol_irq = res->wol_irq; 4451 priv->lpi_irq = res->lpi_irq; 4452 4453 if (!IS_ERR_OR_NULL(res->mac)) 4454 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4455 4456 dev_set_drvdata(device, priv->dev); 4457 4458 /* Verify driver arguments */ 4459 stmmac_verify_args(); 4460 4461 /* Allocate workqueue */ 4462 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4463 if (!priv->wq) { 4464 dev_err(priv->device, "failed to create workqueue\n"); 4465 return -ENOMEM; 4466 } 4467 4468 INIT_WORK(&priv->service_task, stmmac_service_task); 4469 4470 /* Override with kernel parameters if supplied XXX CRS XXX 4471 * this needs to have multiple instances 4472 */ 4473 if ((phyaddr >= 0) && (phyaddr <= 31)) 4474 priv->plat->phy_addr = phyaddr; 4475 4476 if (priv->plat->stmmac_rst) { 4477 ret = reset_control_assert(priv->plat->stmmac_rst); 4478 reset_control_deassert(priv->plat->stmmac_rst); 4479 /* Some reset controllers have only reset callback instead of 4480 * assert + deassert callbacks pair. 4481 */ 4482 if (ret == -ENOTSUPP) 4483 reset_control_reset(priv->plat->stmmac_rst); 4484 } 4485 4486 /* Init MAC and get the capabilities */ 4487 ret = stmmac_hw_init(priv); 4488 if (ret) 4489 goto error_hw_init; 4490 4491 stmmac_check_ether_addr(priv); 4492 4493 /* Configure real RX and TX queues */ 4494 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4495 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4496 4497 ndev->netdev_ops = &stmmac_netdev_ops; 4498 4499 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4500 NETIF_F_RXCSUM; 4501 4502 ret = stmmac_tc_init(priv, priv); 4503 if (!ret) { 4504 ndev->hw_features |= NETIF_F_HW_TC; 4505 } 4506 4507 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4508 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4509 priv->tso = true; 4510 dev_info(priv->device, "TSO feature enabled\n"); 4511 } 4512 4513 if (priv->dma_cap.sphen) { 4514 ndev->hw_features |= NETIF_F_GRO; 4515 priv->sph = true; 4516 dev_info(priv->device, "SPH feature enabled\n"); 4517 } 4518 4519 if (priv->dma_cap.addr64) { 4520 ret = dma_set_mask_and_coherent(device, 4521 DMA_BIT_MASK(priv->dma_cap.addr64)); 4522 if (!ret) { 4523 dev_info(priv->device, "Using %d bits DMA width\n", 4524 priv->dma_cap.addr64); 4525 } else { 4526 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4527 if (ret) { 4528 dev_err(priv->device, "Failed to set DMA Mask\n"); 4529 goto error_hw_init; 4530 } 4531 4532 priv->dma_cap.addr64 = 32; 4533 } 4534 } 4535 4536 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4537 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4538 #ifdef STMMAC_VLAN_TAG_USED 4539 /* Both mac100 and gmac support receive VLAN tag detection */ 4540 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4541 if (priv->dma_cap.vlhash) { 4542 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4543 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4544 } 4545 if (priv->dma_cap.vlins) { 4546 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4547 if (priv->dma_cap.dvlan) 4548 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4549 } 4550 #endif 4551 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4552 4553 /* Initialize RSS */ 4554 rxq = priv->plat->rx_queues_to_use; 4555 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4556 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4557 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4558 4559 if (priv->dma_cap.rssen && priv->plat->rss_en) 4560 ndev->features |= NETIF_F_RXHASH; 4561 4562 /* MTU range: 46 - hw-specific max */ 4563 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4564 if (priv->plat->has_xgmac) 4565 ndev->max_mtu = XGMAC_JUMBO_LEN; 4566 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4567 ndev->max_mtu = JUMBO_LEN; 4568 else 4569 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4570 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4571 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4572 */ 4573 if ((priv->plat->maxmtu < ndev->max_mtu) && 4574 (priv->plat->maxmtu >= ndev->min_mtu)) 4575 ndev->max_mtu = priv->plat->maxmtu; 4576 else if (priv->plat->maxmtu < ndev->min_mtu) 4577 dev_warn(priv->device, 4578 "%s: warning: maxmtu having invalid value (%d)\n", 4579 __func__, priv->plat->maxmtu); 4580 4581 if (flow_ctrl) 4582 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4583 4584 /* Setup channels NAPI */ 4585 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4586 4587 for (queue = 0; queue < maxq; queue++) { 4588 struct stmmac_channel *ch = &priv->channel[queue]; 4589 4590 ch->priv_data = priv; 4591 ch->index = queue; 4592 4593 if (queue < priv->plat->rx_queues_to_use) { 4594 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4595 NAPI_POLL_WEIGHT); 4596 } 4597 if (queue < priv->plat->tx_queues_to_use) { 4598 netif_tx_napi_add(ndev, &ch->tx_napi, 4599 stmmac_napi_poll_tx, 4600 NAPI_POLL_WEIGHT); 4601 } 4602 } 4603 4604 mutex_init(&priv->lock); 4605 4606 /* If a specific clk_csr value is passed from the platform 4607 * this means that the CSR Clock Range selection cannot be 4608 * changed at run-time and it is fixed. Viceversa the driver'll try to 4609 * set the MDC clock dynamically according to the csr actual 4610 * clock input. 4611 */ 4612 if (priv->plat->clk_csr >= 0) 4613 priv->clk_csr = priv->plat->clk_csr; 4614 else 4615 stmmac_clk_csr_set(priv); 4616 4617 stmmac_check_pcs_mode(priv); 4618 4619 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4620 priv->hw->pcs != STMMAC_PCS_TBI && 4621 priv->hw->pcs != STMMAC_PCS_RTBI) { 4622 /* MDIO bus Registration */ 4623 ret = stmmac_mdio_register(ndev); 4624 if (ret < 0) { 4625 dev_err(priv->device, 4626 "%s: MDIO bus (id: %d) registration failed", 4627 __func__, priv->plat->bus_id); 4628 goto error_mdio_register; 4629 } 4630 } 4631 4632 ret = stmmac_phy_setup(priv); 4633 if (ret) { 4634 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4635 goto error_phy_setup; 4636 } 4637 4638 ret = register_netdev(ndev); 4639 if (ret) { 4640 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4641 __func__, ret); 4642 goto error_netdev_register; 4643 } 4644 4645 #ifdef CONFIG_DEBUG_FS 4646 stmmac_init_fs(ndev); 4647 #endif 4648 4649 return ret; 4650 4651 error_netdev_register: 4652 phylink_destroy(priv->phylink); 4653 error_phy_setup: 4654 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4655 priv->hw->pcs != STMMAC_PCS_TBI && 4656 priv->hw->pcs != STMMAC_PCS_RTBI) 4657 stmmac_mdio_unregister(ndev); 4658 error_mdio_register: 4659 for (queue = 0; queue < maxq; queue++) { 4660 struct stmmac_channel *ch = &priv->channel[queue]; 4661 4662 if (queue < priv->plat->rx_queues_to_use) 4663 netif_napi_del(&ch->rx_napi); 4664 if (queue < priv->plat->tx_queues_to_use) 4665 netif_napi_del(&ch->tx_napi); 4666 } 4667 error_hw_init: 4668 destroy_workqueue(priv->wq); 4669 4670 return ret; 4671 } 4672 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4673 4674 /** 4675 * stmmac_dvr_remove 4676 * @dev: device pointer 4677 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4678 * changes the link status, releases the DMA descriptor rings. 4679 */ 4680 int stmmac_dvr_remove(struct device *dev) 4681 { 4682 struct net_device *ndev = dev_get_drvdata(dev); 4683 struct stmmac_priv *priv = netdev_priv(ndev); 4684 4685 netdev_info(priv->dev, "%s: removing driver", __func__); 4686 4687 #ifdef CONFIG_DEBUG_FS 4688 stmmac_exit_fs(ndev); 4689 #endif 4690 stmmac_stop_all_dma(priv); 4691 4692 stmmac_mac_set(priv, priv->ioaddr, false); 4693 netif_carrier_off(ndev); 4694 unregister_netdev(ndev); 4695 phylink_destroy(priv->phylink); 4696 if (priv->plat->stmmac_rst) 4697 reset_control_assert(priv->plat->stmmac_rst); 4698 clk_disable_unprepare(priv->plat->pclk); 4699 clk_disable_unprepare(priv->plat->stmmac_clk); 4700 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4701 priv->hw->pcs != STMMAC_PCS_TBI && 4702 priv->hw->pcs != STMMAC_PCS_RTBI) 4703 stmmac_mdio_unregister(ndev); 4704 destroy_workqueue(priv->wq); 4705 mutex_destroy(&priv->lock); 4706 4707 return 0; 4708 } 4709 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4710 4711 /** 4712 * stmmac_suspend - suspend callback 4713 * @dev: device pointer 4714 * Description: this is the function to suspend the device and it is called 4715 * by the platform driver to stop the network queue, release the resources, 4716 * program the PMT register (for WoL), clean and release driver resources. 4717 */ 4718 int stmmac_suspend(struct device *dev) 4719 { 4720 struct net_device *ndev = dev_get_drvdata(dev); 4721 struct stmmac_priv *priv = netdev_priv(ndev); 4722 4723 if (!ndev || !netif_running(ndev)) 4724 return 0; 4725 4726 phylink_mac_change(priv->phylink, false); 4727 4728 mutex_lock(&priv->lock); 4729 4730 netif_device_detach(ndev); 4731 stmmac_stop_all_queues(priv); 4732 4733 stmmac_disable_all_queues(priv); 4734 4735 /* Stop TX/RX DMA */ 4736 stmmac_stop_all_dma(priv); 4737 4738 /* Enable Power down mode by programming the PMT regs */ 4739 if (device_may_wakeup(priv->device)) { 4740 stmmac_pmt(priv, priv->hw, priv->wolopts); 4741 priv->irq_wake = 1; 4742 } else { 4743 mutex_unlock(&priv->lock); 4744 rtnl_lock(); 4745 phylink_stop(priv->phylink); 4746 rtnl_unlock(); 4747 mutex_lock(&priv->lock); 4748 4749 stmmac_mac_set(priv, priv->ioaddr, false); 4750 pinctrl_pm_select_sleep_state(priv->device); 4751 /* Disable clock in case of PWM is off */ 4752 if (priv->plat->clk_ptp_ref) 4753 clk_disable_unprepare(priv->plat->clk_ptp_ref); 4754 clk_disable_unprepare(priv->plat->pclk); 4755 clk_disable_unprepare(priv->plat->stmmac_clk); 4756 } 4757 mutex_unlock(&priv->lock); 4758 4759 priv->speed = SPEED_UNKNOWN; 4760 return 0; 4761 } 4762 EXPORT_SYMBOL_GPL(stmmac_suspend); 4763 4764 /** 4765 * stmmac_reset_queues_param - reset queue parameters 4766 * @dev: device pointer 4767 */ 4768 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 4769 { 4770 u32 rx_cnt = priv->plat->rx_queues_to_use; 4771 u32 tx_cnt = priv->plat->tx_queues_to_use; 4772 u32 queue; 4773 4774 for (queue = 0; queue < rx_cnt; queue++) { 4775 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4776 4777 rx_q->cur_rx = 0; 4778 rx_q->dirty_rx = 0; 4779 } 4780 4781 for (queue = 0; queue < tx_cnt; queue++) { 4782 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4783 4784 tx_q->cur_tx = 0; 4785 tx_q->dirty_tx = 0; 4786 tx_q->mss = 0; 4787 } 4788 } 4789 4790 /** 4791 * stmmac_resume - resume callback 4792 * @dev: device pointer 4793 * Description: when resume this function is invoked to setup the DMA and CORE 4794 * in a usable state. 4795 */ 4796 int stmmac_resume(struct device *dev) 4797 { 4798 struct net_device *ndev = dev_get_drvdata(dev); 4799 struct stmmac_priv *priv = netdev_priv(ndev); 4800 4801 if (!netif_running(ndev)) 4802 return 0; 4803 4804 /* Power Down bit, into the PM register, is cleared 4805 * automatically as soon as a magic packet or a Wake-up frame 4806 * is received. Anyway, it's better to manually clear 4807 * this bit because it can generate problems while resuming 4808 * from another devices (e.g. serial console). 4809 */ 4810 if (device_may_wakeup(priv->device)) { 4811 mutex_lock(&priv->lock); 4812 stmmac_pmt(priv, priv->hw, 0); 4813 mutex_unlock(&priv->lock); 4814 priv->irq_wake = 0; 4815 } else { 4816 pinctrl_pm_select_default_state(priv->device); 4817 /* enable the clk previously disabled */ 4818 clk_prepare_enable(priv->plat->stmmac_clk); 4819 clk_prepare_enable(priv->plat->pclk); 4820 if (priv->plat->clk_ptp_ref) 4821 clk_prepare_enable(priv->plat->clk_ptp_ref); 4822 /* reset the phy so that it's ready */ 4823 if (priv->mii) 4824 stmmac_mdio_reset(priv->mii); 4825 } 4826 4827 netif_device_attach(ndev); 4828 4829 mutex_lock(&priv->lock); 4830 4831 stmmac_reset_queues_param(priv); 4832 4833 stmmac_clear_descriptors(priv); 4834 4835 stmmac_hw_setup(ndev, false); 4836 stmmac_init_coalesce(priv); 4837 stmmac_set_rx_mode(ndev); 4838 4839 stmmac_enable_all_queues(priv); 4840 4841 stmmac_start_all_queues(priv); 4842 4843 mutex_unlock(&priv->lock); 4844 4845 if (!device_may_wakeup(priv->device)) { 4846 rtnl_lock(); 4847 phylink_start(priv->phylink); 4848 rtnl_unlock(); 4849 } 4850 4851 phylink_mac_change(priv->phylink, true); 4852 4853 return 0; 4854 } 4855 EXPORT_SYMBOL_GPL(stmmac_resume); 4856 4857 #ifndef MODULE 4858 static int __init stmmac_cmdline_opt(char *str) 4859 { 4860 char *opt; 4861 4862 if (!str || !*str) 4863 return -EINVAL; 4864 while ((opt = strsep(&str, ",")) != NULL) { 4865 if (!strncmp(opt, "debug:", 6)) { 4866 if (kstrtoint(opt + 6, 0, &debug)) 4867 goto err; 4868 } else if (!strncmp(opt, "phyaddr:", 8)) { 4869 if (kstrtoint(opt + 8, 0, &phyaddr)) 4870 goto err; 4871 } else if (!strncmp(opt, "buf_sz:", 7)) { 4872 if (kstrtoint(opt + 7, 0, &buf_sz)) 4873 goto err; 4874 } else if (!strncmp(opt, "tc:", 3)) { 4875 if (kstrtoint(opt + 3, 0, &tc)) 4876 goto err; 4877 } else if (!strncmp(opt, "watchdog:", 9)) { 4878 if (kstrtoint(opt + 9, 0, &watchdog)) 4879 goto err; 4880 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 4881 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 4882 goto err; 4883 } else if (!strncmp(opt, "pause:", 6)) { 4884 if (kstrtoint(opt + 6, 0, &pause)) 4885 goto err; 4886 } else if (!strncmp(opt, "eee_timer:", 10)) { 4887 if (kstrtoint(opt + 10, 0, &eee_timer)) 4888 goto err; 4889 } else if (!strncmp(opt, "chain_mode:", 11)) { 4890 if (kstrtoint(opt + 11, 0, &chain_mode)) 4891 goto err; 4892 } 4893 } 4894 return 0; 4895 4896 err: 4897 pr_err("%s: ERROR broken module parameter conversion", __func__); 4898 return -EINVAL; 4899 } 4900 4901 __setup("stmmaceth=", stmmac_cmdline_opt); 4902 #endif /* MODULE */ 4903 4904 static int __init stmmac_init(void) 4905 { 4906 #ifdef CONFIG_DEBUG_FS 4907 /* Create debugfs main directory if it doesn't exist yet */ 4908 if (!stmmac_fs_dir) 4909 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 4910 #endif 4911 4912 return 0; 4913 } 4914 4915 static void __exit stmmac_exit(void) 4916 { 4917 #ifdef CONFIG_DEBUG_FS 4918 debugfs_remove_recursive(stmmac_fs_dir); 4919 #endif 4920 } 4921 4922 module_init(stmmac_init) 4923 module_exit(stmmac_exit) 4924 4925 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 4926 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 4927 MODULE_LICENSE("GPL"); 4928