1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 55 56 /* Module parameters */ 57 #define TX_TIMEO 5000 58 static int watchdog = TX_TIMEO; 59 module_param(watchdog, int, 0644); 60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 61 62 static int debug = -1; 63 module_param(debug, int, 0644); 64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 65 66 static int phyaddr = -1; 67 module_param(phyaddr, int, 0444); 68 MODULE_PARM_DESC(phyaddr, "Physical device address"); 69 70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 72 73 /* Limit to make sure XDP TX and slow path can coexist */ 74 #define STMMAC_XSK_TX_BUDGET_MAX 256 75 #define STMMAC_TX_XSK_AVAIL 16 76 #define STMMAC_RX_FILL_BATCH 16 77 78 #define STMMAC_XDP_PASS 0 79 #define STMMAC_XDP_CONSUMED BIT(0) 80 #define STMMAC_XDP_TX BIT(1) 81 #define STMMAC_XDP_REDIRECT BIT(2) 82 83 static int flow_ctrl = FLOW_AUTO; 84 module_param(flow_ctrl, int, 0644); 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 86 87 static int pause = PAUSE_TIME; 88 module_param(pause, int, 0644); 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 90 91 #define TC_DEFAULT 64 92 static int tc = TC_DEFAULT; 93 module_param(tc, int, 0644); 94 MODULE_PARM_DESC(tc, "DMA threshold control value"); 95 96 #define DEFAULT_BUFSIZE 1536 97 static int buf_sz = DEFAULT_BUFSIZE; 98 module_param(buf_sz, int, 0644); 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 100 101 #define STMMAC_RX_COPYBREAK 256 102 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 104 NETIF_MSG_LINK | NETIF_MSG_IFUP | 105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 106 107 #define STMMAC_DEFAULT_LPI_TIMER 1000 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 109 module_param(eee_timer, int, 0644); 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 112 113 /* By default the driver will use the ring mode to manage tx and rx descriptors, 114 * but allow user to force to use the chain instead of the ring 115 */ 116 static unsigned int chain_mode; 117 module_param(chain_mode, int, 0444); 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 119 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 121 /* For MSI interrupts handling */ 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 128 129 #ifdef CONFIG_DEBUG_FS 130 static const struct net_device_ops stmmac_netdev_ops; 131 static void stmmac_init_fs(struct net_device *dev); 132 static void stmmac_exit_fs(struct net_device *dev); 133 #endif 134 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 136 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 138 { 139 int ret = 0; 140 141 if (enabled) { 142 ret = clk_prepare_enable(priv->plat->stmmac_clk); 143 if (ret) 144 return ret; 145 ret = clk_prepare_enable(priv->plat->pclk); 146 if (ret) { 147 clk_disable_unprepare(priv->plat->stmmac_clk); 148 return ret; 149 } 150 if (priv->plat->clks_config) { 151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 152 if (ret) { 153 clk_disable_unprepare(priv->plat->stmmac_clk); 154 clk_disable_unprepare(priv->plat->pclk); 155 return ret; 156 } 157 } 158 } else { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 clk_disable_unprepare(priv->plat->pclk); 161 if (priv->plat->clks_config) 162 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 163 } 164 165 return ret; 166 } 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 168 169 /** 170 * stmmac_verify_args - verify the driver parameters. 171 * Description: it checks the driver parameters and set a default in case of 172 * errors. 173 */ 174 static void stmmac_verify_args(void) 175 { 176 if (unlikely(watchdog < 0)) 177 watchdog = TX_TIMEO; 178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 179 buf_sz = DEFAULT_BUFSIZE; 180 if (unlikely(flow_ctrl > 1)) 181 flow_ctrl = FLOW_AUTO; 182 else if (likely(flow_ctrl < 0)) 183 flow_ctrl = FLOW_OFF; 184 if (unlikely((pause < 0) || (pause > 0xffff))) 185 pause = PAUSE_TIME; 186 if (eee_timer < 0) 187 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 188 } 189 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 191 { 192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 195 u32 queue; 196 197 for (queue = 0; queue < maxq; queue++) { 198 struct stmmac_channel *ch = &priv->channel[queue]; 199 200 if (stmmac_xdp_is_enabled(priv) && 201 test_bit(queue, priv->af_xdp_zc_qps)) { 202 napi_disable(&ch->rxtx_napi); 203 continue; 204 } 205 206 if (queue < rx_queues_cnt) 207 napi_disable(&ch->rx_napi); 208 if (queue < tx_queues_cnt) 209 napi_disable(&ch->tx_napi); 210 } 211 } 212 213 /** 214 * stmmac_disable_all_queues - Disable all queues 215 * @priv: driver private structure 216 */ 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 218 { 219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 220 struct stmmac_rx_queue *rx_q; 221 u32 queue; 222 223 /* synchronize_rcu() needed for pending XDP buffers to drain */ 224 for (queue = 0; queue < rx_queues_cnt; queue++) { 225 rx_q = &priv->rx_queue[queue]; 226 if (rx_q->xsk_pool) { 227 synchronize_rcu(); 228 break; 229 } 230 } 231 232 __stmmac_disable_all_queues(priv); 233 } 234 235 /** 236 * stmmac_enable_all_queues - Enable all queues 237 * @priv: driver private structure 238 */ 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 240 { 241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 244 u32 queue; 245 246 for (queue = 0; queue < maxq; queue++) { 247 struct stmmac_channel *ch = &priv->channel[queue]; 248 249 if (stmmac_xdp_is_enabled(priv) && 250 test_bit(queue, priv->af_xdp_zc_qps)) { 251 napi_enable(&ch->rxtx_napi); 252 continue; 253 } 254 255 if (queue < rx_queues_cnt) 256 napi_enable(&ch->rx_napi); 257 if (queue < tx_queues_cnt) 258 napi_enable(&ch->tx_napi); 259 } 260 } 261 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 263 { 264 if (!test_bit(STMMAC_DOWN, &priv->state) && 265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 266 queue_work(priv->wq, &priv->service_task); 267 } 268 269 static void stmmac_global_err(struct stmmac_priv *priv) 270 { 271 netif_carrier_off(priv->dev); 272 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 273 stmmac_service_event_schedule(priv); 274 } 275 276 /** 277 * stmmac_clk_csr_set - dynamically set the MDC clock 278 * @priv: driver private structure 279 * Description: this is to dynamically set the MDC clock according to the csr 280 * clock input. 281 * Note: 282 * If a specific clk_csr value is passed from the platform 283 * this means that the CSR Clock Range selection cannot be 284 * changed at run-time and it is fixed (as reported in the driver 285 * documentation). Viceversa the driver will try to set the MDC 286 * clock dynamically according to the actual clock input. 287 */ 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 289 { 290 u32 clk_rate; 291 292 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 293 294 /* Platform provided default clk_csr would be assumed valid 295 * for all other cases except for the below mentioned ones. 296 * For values higher than the IEEE 802.3 specified frequency 297 * we can not estimate the proper divider as it is not known 298 * the frequency of clk_csr_i. So we do not change the default 299 * divider. 300 */ 301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 302 if (clk_rate < CSR_F_35M) 303 priv->clk_csr = STMMAC_CSR_20_35M; 304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 305 priv->clk_csr = STMMAC_CSR_35_60M; 306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 307 priv->clk_csr = STMMAC_CSR_60_100M; 308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 309 priv->clk_csr = STMMAC_CSR_100_150M; 310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 311 priv->clk_csr = STMMAC_CSR_150_250M; 312 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 313 priv->clk_csr = STMMAC_CSR_250_300M; 314 } 315 316 if (priv->plat->has_sun8i) { 317 if (clk_rate > 160000000) 318 priv->clk_csr = 0x03; 319 else if (clk_rate > 80000000) 320 priv->clk_csr = 0x02; 321 else if (clk_rate > 40000000) 322 priv->clk_csr = 0x01; 323 else 324 priv->clk_csr = 0; 325 } 326 327 if (priv->plat->has_xgmac) { 328 if (clk_rate > 400000000) 329 priv->clk_csr = 0x5; 330 else if (clk_rate > 350000000) 331 priv->clk_csr = 0x4; 332 else if (clk_rate > 300000000) 333 priv->clk_csr = 0x3; 334 else if (clk_rate > 250000000) 335 priv->clk_csr = 0x2; 336 else if (clk_rate > 150000000) 337 priv->clk_csr = 0x1; 338 else 339 priv->clk_csr = 0x0; 340 } 341 } 342 343 static void print_pkt(unsigned char *buf, int len) 344 { 345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 347 } 348 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 350 { 351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 352 u32 avail; 353 354 if (tx_q->dirty_tx > tx_q->cur_tx) 355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 356 else 357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 358 359 return avail; 360 } 361 362 /** 363 * stmmac_rx_dirty - Get RX queue dirty 364 * @priv: driver private structure 365 * @queue: RX queue index 366 */ 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 368 { 369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 370 u32 dirty; 371 372 if (rx_q->dirty_rx <= rx_q->cur_rx) 373 dirty = rx_q->cur_rx - rx_q->dirty_rx; 374 else 375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 376 377 return dirty; 378 } 379 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 381 { 382 int tx_lpi_timer; 383 384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 385 priv->eee_sw_timer_en = en ? 0 : 1; 386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 388 } 389 390 /** 391 * stmmac_enable_eee_mode - check and enter in LPI mode 392 * @priv: driver private structure 393 * Description: this function is to verify and enter in LPI mode in case of 394 * EEE. 395 */ 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 397 { 398 u32 tx_cnt = priv->plat->tx_queues_to_use; 399 u32 queue; 400 401 /* check if all TX queues have the work finished */ 402 for (queue = 0; queue < tx_cnt; queue++) { 403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 404 405 if (tx_q->dirty_tx != tx_q->cur_tx) 406 return; /* still unfinished work */ 407 } 408 409 /* Check and enter in LPI mode */ 410 if (!priv->tx_path_in_lpi_mode) 411 stmmac_set_eee_mode(priv, priv->hw, 412 priv->plat->en_tx_lpi_clockgating); 413 } 414 415 /** 416 * stmmac_disable_eee_mode - disable and exit from LPI mode 417 * @priv: driver private structure 418 * Description: this function is to exit and disable EEE in case of 419 * LPI state is true. This is called by the xmit. 420 */ 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 422 { 423 if (!priv->eee_sw_timer_en) { 424 stmmac_lpi_entry_timer_config(priv, 0); 425 return; 426 } 427 428 stmmac_reset_eee_mode(priv, priv->hw); 429 del_timer_sync(&priv->eee_ctrl_timer); 430 priv->tx_path_in_lpi_mode = false; 431 } 432 433 /** 434 * stmmac_eee_ctrl_timer - EEE TX SW timer. 435 * @t: timer_list struct containing private info 436 * Description: 437 * if there is no data transfer and if we are not in LPI state, 438 * then MAC Transmitter can be moved to LPI state. 439 */ 440 static void stmmac_eee_ctrl_timer(struct timer_list *t) 441 { 442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 443 444 stmmac_enable_eee_mode(priv); 445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 446 } 447 448 /** 449 * stmmac_eee_init - init EEE 450 * @priv: driver private structure 451 * Description: 452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 453 * can also manage EEE, this function enable the LPI state and start related 454 * timer. 455 */ 456 bool stmmac_eee_init(struct stmmac_priv *priv) 457 { 458 int eee_tw_timer = priv->eee_tw_timer; 459 460 /* Using PCS we cannot dial with the phy registers at this stage 461 * so we do not support extra feature like EEE. 462 */ 463 if (priv->hw->pcs == STMMAC_PCS_TBI || 464 priv->hw->pcs == STMMAC_PCS_RTBI) 465 return false; 466 467 /* Check if MAC core supports the EEE feature. */ 468 if (!priv->dma_cap.eee) 469 return false; 470 471 mutex_lock(&priv->lock); 472 473 /* Check if it needs to be deactivated */ 474 if (!priv->eee_active) { 475 if (priv->eee_enabled) { 476 netdev_dbg(priv->dev, "disable EEE\n"); 477 stmmac_lpi_entry_timer_config(priv, 0); 478 del_timer_sync(&priv->eee_ctrl_timer); 479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 480 if (priv->hw->xpcs) 481 xpcs_config_eee(priv->hw->xpcs, 482 priv->plat->mult_fact_100ns, 483 false); 484 } 485 mutex_unlock(&priv->lock); 486 return false; 487 } 488 489 if (priv->eee_active && !priv->eee_enabled) { 490 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 491 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 492 eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 true); 497 } 498 499 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 500 del_timer_sync(&priv->eee_ctrl_timer); 501 priv->tx_path_in_lpi_mode = false; 502 stmmac_lpi_entry_timer_config(priv, 1); 503 } else { 504 stmmac_lpi_entry_timer_config(priv, 0); 505 mod_timer(&priv->eee_ctrl_timer, 506 STMMAC_LPI_T(priv->tx_lpi_timer)); 507 } 508 509 mutex_unlock(&priv->lock); 510 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 511 return true; 512 } 513 514 static inline u32 stmmac_cdc_adjust(struct stmmac_priv *priv) 515 { 516 /* Correct the clk domain crossing(CDC) error */ 517 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) 518 return (2 * NSEC_PER_SEC) / priv->plat->clk_ptp_rate; 519 return 0; 520 } 521 522 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 523 * @priv: driver private structure 524 * @p : descriptor pointer 525 * @skb : the socket buffer 526 * Description : 527 * This function will read timestamp from the descriptor & pass it to stack. 528 * and also perform some sanity checks. 529 */ 530 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 531 struct dma_desc *p, struct sk_buff *skb) 532 { 533 struct skb_shared_hwtstamps shhwtstamp; 534 bool found = false; 535 u64 ns = 0; 536 537 if (!priv->hwts_tx_en) 538 return; 539 540 /* exit if skb doesn't support hw tstamp */ 541 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 542 return; 543 544 /* check tx tstamp status */ 545 if (stmmac_get_tx_timestamp_status(priv, p)) { 546 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 547 found = true; 548 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 549 found = true; 550 } 551 552 if (found) { 553 ns -= stmmac_cdc_adjust(priv); 554 555 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 556 shhwtstamp.hwtstamp = ns_to_ktime(ns); 557 558 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 559 /* pass tstamp to stack */ 560 skb_tstamp_tx(skb, &shhwtstamp); 561 } 562 } 563 564 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 565 * @priv: driver private structure 566 * @p : descriptor pointer 567 * @np : next descriptor pointer 568 * @skb : the socket buffer 569 * Description : 570 * This function will read received packet's timestamp from the descriptor 571 * and pass it to stack. It also perform some sanity checks. 572 */ 573 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 574 struct dma_desc *np, struct sk_buff *skb) 575 { 576 struct skb_shared_hwtstamps *shhwtstamp = NULL; 577 struct dma_desc *desc = p; 578 u64 ns = 0; 579 580 if (!priv->hwts_rx_en) 581 return; 582 /* For GMAC4, the valid timestamp is from CTX next desc. */ 583 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 584 desc = np; 585 586 /* Check if timestamp is available */ 587 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 588 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 589 590 ns -= stmmac_cdc_adjust(priv); 591 592 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 593 shhwtstamp = skb_hwtstamps(skb); 594 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 595 shhwtstamp->hwtstamp = ns_to_ktime(ns); 596 } else { 597 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 598 } 599 } 600 601 /** 602 * stmmac_hwtstamp_set - control hardware timestamping. 603 * @dev: device pointer. 604 * @ifr: An IOCTL specific structure, that can contain a pointer to 605 * a proprietary structure used to pass information to the driver. 606 * Description: 607 * This function configures the MAC to enable/disable both outgoing(TX) 608 * and incoming(RX) packets time stamping based on user input. 609 * Return Value: 610 * 0 on success and an appropriate -ve integer on failure. 611 */ 612 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 613 { 614 struct stmmac_priv *priv = netdev_priv(dev); 615 struct hwtstamp_config config; 616 struct timespec64 now; 617 u64 temp = 0; 618 u32 ptp_v2 = 0; 619 u32 tstamp_all = 0; 620 u32 ptp_over_ipv4_udp = 0; 621 u32 ptp_over_ipv6_udp = 0; 622 u32 ptp_over_ethernet = 0; 623 u32 snap_type_sel = 0; 624 u32 ts_master_en = 0; 625 u32 ts_event_en = 0; 626 u32 sec_inc = 0; 627 u32 value = 0; 628 bool xmac; 629 630 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 631 632 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 633 netdev_alert(priv->dev, "No support for HW time stamping\n"); 634 priv->hwts_tx_en = 0; 635 priv->hwts_rx_en = 0; 636 637 return -EOPNOTSUPP; 638 } 639 640 if (copy_from_user(&config, ifr->ifr_data, 641 sizeof(config))) 642 return -EFAULT; 643 644 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 645 __func__, config.flags, config.tx_type, config.rx_filter); 646 647 /* reserved for future extensions */ 648 if (config.flags) 649 return -EINVAL; 650 651 if (config.tx_type != HWTSTAMP_TX_OFF && 652 config.tx_type != HWTSTAMP_TX_ON) 653 return -ERANGE; 654 655 if (priv->adv_ts) { 656 switch (config.rx_filter) { 657 case HWTSTAMP_FILTER_NONE: 658 /* time stamp no incoming packet at all */ 659 config.rx_filter = HWTSTAMP_FILTER_NONE; 660 break; 661 662 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 663 /* PTP v1, UDP, any kind of event packet */ 664 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 665 /* 'xmac' hardware can support Sync, Pdelay_Req and 666 * Pdelay_resp by setting bit14 and bits17/16 to 01 667 * This leaves Delay_Req timestamps out. 668 * Enable all events *and* general purpose message 669 * timestamping 670 */ 671 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 672 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 673 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 674 break; 675 676 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 677 /* PTP v1, UDP, Sync packet */ 678 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 679 /* take time stamp for SYNC messages only */ 680 ts_event_en = PTP_TCR_TSEVNTENA; 681 682 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 683 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 684 break; 685 686 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 687 /* PTP v1, UDP, Delay_req packet */ 688 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 689 /* take time stamp for Delay_Req messages only */ 690 ts_master_en = PTP_TCR_TSMSTRENA; 691 ts_event_en = PTP_TCR_TSEVNTENA; 692 693 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 694 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 695 break; 696 697 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 698 /* PTP v2, UDP, any kind of event packet */ 699 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 700 ptp_v2 = PTP_TCR_TSVER2ENA; 701 /* take time stamp for all event messages */ 702 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 703 704 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 705 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 706 break; 707 708 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 709 /* PTP v2, UDP, Sync packet */ 710 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 711 ptp_v2 = PTP_TCR_TSVER2ENA; 712 /* take time stamp for SYNC messages only */ 713 ts_event_en = PTP_TCR_TSEVNTENA; 714 715 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 716 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 717 break; 718 719 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 720 /* PTP v2, UDP, Delay_req packet */ 721 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 722 ptp_v2 = PTP_TCR_TSVER2ENA; 723 /* take time stamp for Delay_Req messages only */ 724 ts_master_en = PTP_TCR_TSMSTRENA; 725 ts_event_en = PTP_TCR_TSEVNTENA; 726 727 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 728 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 729 break; 730 731 case HWTSTAMP_FILTER_PTP_V2_EVENT: 732 /* PTP v2/802.AS1 any layer, any kind of event packet */ 733 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 734 ptp_v2 = PTP_TCR_TSVER2ENA; 735 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 736 if (priv->synopsys_id < DWMAC_CORE_4_10) 737 ts_event_en = PTP_TCR_TSEVNTENA; 738 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 739 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 740 ptp_over_ethernet = PTP_TCR_TSIPENA; 741 break; 742 743 case HWTSTAMP_FILTER_PTP_V2_SYNC: 744 /* PTP v2/802.AS1, any layer, Sync packet */ 745 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 746 ptp_v2 = PTP_TCR_TSVER2ENA; 747 /* take time stamp for SYNC messages only */ 748 ts_event_en = PTP_TCR_TSEVNTENA; 749 750 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 751 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 752 ptp_over_ethernet = PTP_TCR_TSIPENA; 753 break; 754 755 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 756 /* PTP v2/802.AS1, any layer, Delay_req packet */ 757 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 758 ptp_v2 = PTP_TCR_TSVER2ENA; 759 /* take time stamp for Delay_Req messages only */ 760 ts_master_en = PTP_TCR_TSMSTRENA; 761 ts_event_en = PTP_TCR_TSEVNTENA; 762 763 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 764 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 765 ptp_over_ethernet = PTP_TCR_TSIPENA; 766 break; 767 768 case HWTSTAMP_FILTER_NTP_ALL: 769 case HWTSTAMP_FILTER_ALL: 770 /* time stamp any incoming packet */ 771 config.rx_filter = HWTSTAMP_FILTER_ALL; 772 tstamp_all = PTP_TCR_TSENALL; 773 break; 774 775 default: 776 return -ERANGE; 777 } 778 } else { 779 switch (config.rx_filter) { 780 case HWTSTAMP_FILTER_NONE: 781 config.rx_filter = HWTSTAMP_FILTER_NONE; 782 break; 783 default: 784 /* PTP v1, UDP, any kind of event packet */ 785 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 786 break; 787 } 788 } 789 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 790 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 791 792 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 793 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 794 else { 795 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 796 tstamp_all | ptp_v2 | ptp_over_ethernet | 797 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 798 ts_master_en | snap_type_sel); 799 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 800 801 /* program Sub Second Increment reg */ 802 stmmac_config_sub_second_increment(priv, 803 priv->ptpaddr, priv->plat->clk_ptp_rate, 804 xmac, &sec_inc); 805 temp = div_u64(1000000000ULL, sec_inc); 806 807 /* Store sub second increment and flags for later use */ 808 priv->sub_second_inc = sec_inc; 809 priv->systime_flags = value; 810 811 /* calculate default added value: 812 * formula is : 813 * addend = (2^32)/freq_div_ratio; 814 * where, freq_div_ratio = 1e9ns/sec_inc 815 */ 816 temp = (u64)(temp << 32); 817 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 818 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 819 820 /* initialize system time */ 821 ktime_get_real_ts64(&now); 822 823 /* lower 32 bits of tv_sec are safe until y2106 */ 824 stmmac_init_systime(priv, priv->ptpaddr, 825 (u32)now.tv_sec, now.tv_nsec); 826 } 827 828 memcpy(&priv->tstamp_config, &config, sizeof(config)); 829 830 return copy_to_user(ifr->ifr_data, &config, 831 sizeof(config)) ? -EFAULT : 0; 832 } 833 834 /** 835 * stmmac_hwtstamp_get - read hardware timestamping. 836 * @dev: device pointer. 837 * @ifr: An IOCTL specific structure, that can contain a pointer to 838 * a proprietary structure used to pass information to the driver. 839 * Description: 840 * This function obtain the current hardware timestamping settings 841 * as requested. 842 */ 843 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 844 { 845 struct stmmac_priv *priv = netdev_priv(dev); 846 struct hwtstamp_config *config = &priv->tstamp_config; 847 848 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 849 return -EOPNOTSUPP; 850 851 return copy_to_user(ifr->ifr_data, config, 852 sizeof(*config)) ? -EFAULT : 0; 853 } 854 855 /** 856 * stmmac_init_ptp - init PTP 857 * @priv: driver private structure 858 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 859 * This is done by looking at the HW cap. register. 860 * This function also registers the ptp driver. 861 */ 862 static int stmmac_init_ptp(struct stmmac_priv *priv) 863 { 864 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 865 866 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 867 return -EOPNOTSUPP; 868 869 priv->adv_ts = 0; 870 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 871 if (xmac && priv->dma_cap.atime_stamp) 872 priv->adv_ts = 1; 873 /* Dwmac 3.x core with extend_desc can support adv_ts */ 874 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 875 priv->adv_ts = 1; 876 877 if (priv->dma_cap.time_stamp) 878 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 879 880 if (priv->adv_ts) 881 netdev_info(priv->dev, 882 "IEEE 1588-2008 Advanced Timestamp supported\n"); 883 884 priv->hwts_tx_en = 0; 885 priv->hwts_rx_en = 0; 886 887 stmmac_ptp_register(priv); 888 889 return 0; 890 } 891 892 static void stmmac_release_ptp(struct stmmac_priv *priv) 893 { 894 clk_disable_unprepare(priv->plat->clk_ptp_ref); 895 stmmac_ptp_unregister(priv); 896 } 897 898 /** 899 * stmmac_mac_flow_ctrl - Configure flow control in all queues 900 * @priv: driver private structure 901 * @duplex: duplex passed to the next function 902 * Description: It is used for configuring the flow control in all queues 903 */ 904 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 905 { 906 u32 tx_cnt = priv->plat->tx_queues_to_use; 907 908 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 909 priv->pause, tx_cnt); 910 } 911 912 static void stmmac_validate(struct phylink_config *config, 913 unsigned long *supported, 914 struct phylink_link_state *state) 915 { 916 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 917 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 918 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 919 int tx_cnt = priv->plat->tx_queues_to_use; 920 int max_speed = priv->plat->max_speed; 921 922 phylink_set(mac_supported, 10baseT_Half); 923 phylink_set(mac_supported, 10baseT_Full); 924 phylink_set(mac_supported, 100baseT_Half); 925 phylink_set(mac_supported, 100baseT_Full); 926 phylink_set(mac_supported, 1000baseT_Half); 927 phylink_set(mac_supported, 1000baseT_Full); 928 phylink_set(mac_supported, 1000baseKX_Full); 929 930 phylink_set(mac_supported, Autoneg); 931 phylink_set(mac_supported, Pause); 932 phylink_set(mac_supported, Asym_Pause); 933 phylink_set_port_modes(mac_supported); 934 935 /* Cut down 1G if asked to */ 936 if ((max_speed > 0) && (max_speed < 1000)) { 937 phylink_set(mask, 1000baseT_Full); 938 phylink_set(mask, 1000baseX_Full); 939 } else if (priv->plat->has_gmac4) { 940 if (!max_speed || max_speed >= 2500) { 941 phylink_set(mac_supported, 2500baseT_Full); 942 phylink_set(mac_supported, 2500baseX_Full); 943 } 944 } else if (priv->plat->has_xgmac) { 945 if (!max_speed || (max_speed >= 2500)) { 946 phylink_set(mac_supported, 2500baseT_Full); 947 phylink_set(mac_supported, 2500baseX_Full); 948 } 949 if (!max_speed || (max_speed >= 5000)) { 950 phylink_set(mac_supported, 5000baseT_Full); 951 } 952 if (!max_speed || (max_speed >= 10000)) { 953 phylink_set(mac_supported, 10000baseSR_Full); 954 phylink_set(mac_supported, 10000baseLR_Full); 955 phylink_set(mac_supported, 10000baseER_Full); 956 phylink_set(mac_supported, 10000baseLRM_Full); 957 phylink_set(mac_supported, 10000baseT_Full); 958 phylink_set(mac_supported, 10000baseKX4_Full); 959 phylink_set(mac_supported, 10000baseKR_Full); 960 } 961 if (!max_speed || (max_speed >= 25000)) { 962 phylink_set(mac_supported, 25000baseCR_Full); 963 phylink_set(mac_supported, 25000baseKR_Full); 964 phylink_set(mac_supported, 25000baseSR_Full); 965 } 966 if (!max_speed || (max_speed >= 40000)) { 967 phylink_set(mac_supported, 40000baseKR4_Full); 968 phylink_set(mac_supported, 40000baseCR4_Full); 969 phylink_set(mac_supported, 40000baseSR4_Full); 970 phylink_set(mac_supported, 40000baseLR4_Full); 971 } 972 if (!max_speed || (max_speed >= 50000)) { 973 phylink_set(mac_supported, 50000baseCR2_Full); 974 phylink_set(mac_supported, 50000baseKR2_Full); 975 phylink_set(mac_supported, 50000baseSR2_Full); 976 phylink_set(mac_supported, 50000baseKR_Full); 977 phylink_set(mac_supported, 50000baseSR_Full); 978 phylink_set(mac_supported, 50000baseCR_Full); 979 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 980 phylink_set(mac_supported, 50000baseDR_Full); 981 } 982 if (!max_speed || (max_speed >= 100000)) { 983 phylink_set(mac_supported, 100000baseKR4_Full); 984 phylink_set(mac_supported, 100000baseSR4_Full); 985 phylink_set(mac_supported, 100000baseCR4_Full); 986 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 987 phylink_set(mac_supported, 100000baseKR2_Full); 988 phylink_set(mac_supported, 100000baseSR2_Full); 989 phylink_set(mac_supported, 100000baseCR2_Full); 990 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 991 phylink_set(mac_supported, 100000baseDR2_Full); 992 } 993 } 994 995 /* Half-Duplex can only work with single queue */ 996 if (tx_cnt > 1) { 997 phylink_set(mask, 10baseT_Half); 998 phylink_set(mask, 100baseT_Half); 999 phylink_set(mask, 1000baseT_Half); 1000 } 1001 1002 linkmode_and(supported, supported, mac_supported); 1003 linkmode_andnot(supported, supported, mask); 1004 1005 linkmode_and(state->advertising, state->advertising, mac_supported); 1006 linkmode_andnot(state->advertising, state->advertising, mask); 1007 1008 /* If PCS is supported, check which modes it supports. */ 1009 if (priv->hw->xpcs) 1010 xpcs_validate(priv->hw->xpcs, supported, state); 1011 } 1012 1013 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 1014 const struct phylink_link_state *state) 1015 { 1016 /* Nothing to do, xpcs_config() handles everything */ 1017 } 1018 1019 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 1020 { 1021 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 1022 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 1023 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 1024 bool *hs_enable = &fpe_cfg->hs_enable; 1025 1026 if (is_up && *hs_enable) { 1027 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 1028 } else { 1029 *lo_state = FPE_STATE_OFF; 1030 *lp_state = FPE_STATE_OFF; 1031 } 1032 } 1033 1034 static void stmmac_mac_link_down(struct phylink_config *config, 1035 unsigned int mode, phy_interface_t interface) 1036 { 1037 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1038 1039 stmmac_mac_set(priv, priv->ioaddr, false); 1040 priv->eee_active = false; 1041 priv->tx_lpi_enabled = false; 1042 priv->eee_enabled = stmmac_eee_init(priv); 1043 stmmac_set_eee_pls(priv, priv->hw, false); 1044 1045 if (priv->dma_cap.fpesel) 1046 stmmac_fpe_link_state_handle(priv, false); 1047 } 1048 1049 static void stmmac_mac_link_up(struct phylink_config *config, 1050 struct phy_device *phy, 1051 unsigned int mode, phy_interface_t interface, 1052 int speed, int duplex, 1053 bool tx_pause, bool rx_pause) 1054 { 1055 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1056 u32 ctrl; 1057 1058 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 1059 ctrl &= ~priv->hw->link.speed_mask; 1060 1061 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1062 switch (speed) { 1063 case SPEED_10000: 1064 ctrl |= priv->hw->link.xgmii.speed10000; 1065 break; 1066 case SPEED_5000: 1067 ctrl |= priv->hw->link.xgmii.speed5000; 1068 break; 1069 case SPEED_2500: 1070 ctrl |= priv->hw->link.xgmii.speed2500; 1071 break; 1072 default: 1073 return; 1074 } 1075 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1076 switch (speed) { 1077 case SPEED_100000: 1078 ctrl |= priv->hw->link.xlgmii.speed100000; 1079 break; 1080 case SPEED_50000: 1081 ctrl |= priv->hw->link.xlgmii.speed50000; 1082 break; 1083 case SPEED_40000: 1084 ctrl |= priv->hw->link.xlgmii.speed40000; 1085 break; 1086 case SPEED_25000: 1087 ctrl |= priv->hw->link.xlgmii.speed25000; 1088 break; 1089 case SPEED_10000: 1090 ctrl |= priv->hw->link.xgmii.speed10000; 1091 break; 1092 case SPEED_2500: 1093 ctrl |= priv->hw->link.speed2500; 1094 break; 1095 case SPEED_1000: 1096 ctrl |= priv->hw->link.speed1000; 1097 break; 1098 default: 1099 return; 1100 } 1101 } else { 1102 switch (speed) { 1103 case SPEED_2500: 1104 ctrl |= priv->hw->link.speed2500; 1105 break; 1106 case SPEED_1000: 1107 ctrl |= priv->hw->link.speed1000; 1108 break; 1109 case SPEED_100: 1110 ctrl |= priv->hw->link.speed100; 1111 break; 1112 case SPEED_10: 1113 ctrl |= priv->hw->link.speed10; 1114 break; 1115 default: 1116 return; 1117 } 1118 } 1119 1120 priv->speed = speed; 1121 1122 if (priv->plat->fix_mac_speed) 1123 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1124 1125 if (!duplex) 1126 ctrl &= ~priv->hw->link.duplex; 1127 else 1128 ctrl |= priv->hw->link.duplex; 1129 1130 /* Flow Control operation */ 1131 if (tx_pause && rx_pause) 1132 stmmac_mac_flow_ctrl(priv, duplex); 1133 1134 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1135 1136 stmmac_mac_set(priv, priv->ioaddr, true); 1137 if (phy && priv->dma_cap.eee) { 1138 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1139 priv->eee_enabled = stmmac_eee_init(priv); 1140 priv->tx_lpi_enabled = priv->eee_enabled; 1141 stmmac_set_eee_pls(priv, priv->hw, true); 1142 } 1143 1144 if (priv->dma_cap.fpesel) 1145 stmmac_fpe_link_state_handle(priv, true); 1146 } 1147 1148 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1149 .validate = stmmac_validate, 1150 .mac_config = stmmac_mac_config, 1151 .mac_link_down = stmmac_mac_link_down, 1152 .mac_link_up = stmmac_mac_link_up, 1153 }; 1154 1155 /** 1156 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1157 * @priv: driver private structure 1158 * Description: this is to verify if the HW supports the PCS. 1159 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1160 * configured for the TBI, RTBI, or SGMII PHY interface. 1161 */ 1162 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1163 { 1164 int interface = priv->plat->interface; 1165 1166 if (priv->dma_cap.pcs) { 1167 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1168 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1169 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1170 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1171 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1172 priv->hw->pcs = STMMAC_PCS_RGMII; 1173 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1174 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1175 priv->hw->pcs = STMMAC_PCS_SGMII; 1176 } 1177 } 1178 } 1179 1180 /** 1181 * stmmac_init_phy - PHY initialization 1182 * @dev: net device structure 1183 * Description: it initializes the driver's PHY state, and attaches the PHY 1184 * to the mac driver. 1185 * Return value: 1186 * 0 on success 1187 */ 1188 static int stmmac_init_phy(struct net_device *dev) 1189 { 1190 struct stmmac_priv *priv = netdev_priv(dev); 1191 struct device_node *node; 1192 int ret; 1193 1194 node = priv->plat->phylink_node; 1195 1196 if (node) 1197 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1198 1199 /* Some DT bindings do not set-up the PHY handle. Let's try to 1200 * manually parse it 1201 */ 1202 if (!node || ret) { 1203 int addr = priv->plat->phy_addr; 1204 struct phy_device *phydev; 1205 1206 phydev = mdiobus_get_phy(priv->mii, addr); 1207 if (!phydev) { 1208 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1209 return -ENODEV; 1210 } 1211 1212 ret = phylink_connect_phy(priv->phylink, phydev); 1213 } 1214 1215 if (!priv->plat->pmt) { 1216 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1217 1218 phylink_ethtool_get_wol(priv->phylink, &wol); 1219 device_set_wakeup_capable(priv->device, !!wol.supported); 1220 } 1221 1222 return ret; 1223 } 1224 1225 static int stmmac_phy_setup(struct stmmac_priv *priv) 1226 { 1227 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1228 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1229 int mode = priv->plat->phy_interface; 1230 struct phylink *phylink; 1231 1232 priv->phylink_config.dev = &priv->dev->dev; 1233 priv->phylink_config.type = PHYLINK_NETDEV; 1234 priv->phylink_config.pcs_poll = true; 1235 if (priv->plat->mdio_bus_data) 1236 priv->phylink_config.ovr_an_inband = 1237 mdio_bus_data->xpcs_an_inband; 1238 1239 if (!fwnode) 1240 fwnode = dev_fwnode(priv->device); 1241 1242 phylink = phylink_create(&priv->phylink_config, fwnode, 1243 mode, &stmmac_phylink_mac_ops); 1244 if (IS_ERR(phylink)) 1245 return PTR_ERR(phylink); 1246 1247 if (priv->hw->xpcs) 1248 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs); 1249 1250 priv->phylink = phylink; 1251 return 0; 1252 } 1253 1254 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1255 { 1256 u32 rx_cnt = priv->plat->rx_queues_to_use; 1257 unsigned int desc_size; 1258 void *head_rx; 1259 u32 queue; 1260 1261 /* Display RX rings */ 1262 for (queue = 0; queue < rx_cnt; queue++) { 1263 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1264 1265 pr_info("\tRX Queue %u rings\n", queue); 1266 1267 if (priv->extend_desc) { 1268 head_rx = (void *)rx_q->dma_erx; 1269 desc_size = sizeof(struct dma_extended_desc); 1270 } else { 1271 head_rx = (void *)rx_q->dma_rx; 1272 desc_size = sizeof(struct dma_desc); 1273 } 1274 1275 /* Display RX ring */ 1276 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1277 rx_q->dma_rx_phy, desc_size); 1278 } 1279 } 1280 1281 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1282 { 1283 u32 tx_cnt = priv->plat->tx_queues_to_use; 1284 unsigned int desc_size; 1285 void *head_tx; 1286 u32 queue; 1287 1288 /* Display TX rings */ 1289 for (queue = 0; queue < tx_cnt; queue++) { 1290 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1291 1292 pr_info("\tTX Queue %d rings\n", queue); 1293 1294 if (priv->extend_desc) { 1295 head_tx = (void *)tx_q->dma_etx; 1296 desc_size = sizeof(struct dma_extended_desc); 1297 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1298 head_tx = (void *)tx_q->dma_entx; 1299 desc_size = sizeof(struct dma_edesc); 1300 } else { 1301 head_tx = (void *)tx_q->dma_tx; 1302 desc_size = sizeof(struct dma_desc); 1303 } 1304 1305 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1306 tx_q->dma_tx_phy, desc_size); 1307 } 1308 } 1309 1310 static void stmmac_display_rings(struct stmmac_priv *priv) 1311 { 1312 /* Display RX ring */ 1313 stmmac_display_rx_rings(priv); 1314 1315 /* Display TX ring */ 1316 stmmac_display_tx_rings(priv); 1317 } 1318 1319 static int stmmac_set_bfsize(int mtu, int bufsize) 1320 { 1321 int ret = bufsize; 1322 1323 if (mtu >= BUF_SIZE_8KiB) 1324 ret = BUF_SIZE_16KiB; 1325 else if (mtu >= BUF_SIZE_4KiB) 1326 ret = BUF_SIZE_8KiB; 1327 else if (mtu >= BUF_SIZE_2KiB) 1328 ret = BUF_SIZE_4KiB; 1329 else if (mtu > DEFAULT_BUFSIZE) 1330 ret = BUF_SIZE_2KiB; 1331 else 1332 ret = DEFAULT_BUFSIZE; 1333 1334 return ret; 1335 } 1336 1337 /** 1338 * stmmac_clear_rx_descriptors - clear RX descriptors 1339 * @priv: driver private structure 1340 * @queue: RX queue index 1341 * Description: this function is called to clear the RX descriptors 1342 * in case of both basic and extended descriptors are used. 1343 */ 1344 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1345 { 1346 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1347 int i; 1348 1349 /* Clear the RX descriptors */ 1350 for (i = 0; i < priv->dma_rx_size; i++) 1351 if (priv->extend_desc) 1352 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1353 priv->use_riwt, priv->mode, 1354 (i == priv->dma_rx_size - 1), 1355 priv->dma_buf_sz); 1356 else 1357 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1358 priv->use_riwt, priv->mode, 1359 (i == priv->dma_rx_size - 1), 1360 priv->dma_buf_sz); 1361 } 1362 1363 /** 1364 * stmmac_clear_tx_descriptors - clear tx descriptors 1365 * @priv: driver private structure 1366 * @queue: TX queue index. 1367 * Description: this function is called to clear the TX descriptors 1368 * in case of both basic and extended descriptors are used. 1369 */ 1370 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1371 { 1372 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1373 int i; 1374 1375 /* Clear the TX descriptors */ 1376 for (i = 0; i < priv->dma_tx_size; i++) { 1377 int last = (i == (priv->dma_tx_size - 1)); 1378 struct dma_desc *p; 1379 1380 if (priv->extend_desc) 1381 p = &tx_q->dma_etx[i].basic; 1382 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1383 p = &tx_q->dma_entx[i].basic; 1384 else 1385 p = &tx_q->dma_tx[i]; 1386 1387 stmmac_init_tx_desc(priv, p, priv->mode, last); 1388 } 1389 } 1390 1391 /** 1392 * stmmac_clear_descriptors - clear descriptors 1393 * @priv: driver private structure 1394 * Description: this function is called to clear the TX and RX descriptors 1395 * in case of both basic and extended descriptors are used. 1396 */ 1397 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1398 { 1399 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1400 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1401 u32 queue; 1402 1403 /* Clear the RX descriptors */ 1404 for (queue = 0; queue < rx_queue_cnt; queue++) 1405 stmmac_clear_rx_descriptors(priv, queue); 1406 1407 /* Clear the TX descriptors */ 1408 for (queue = 0; queue < tx_queue_cnt; queue++) 1409 stmmac_clear_tx_descriptors(priv, queue); 1410 } 1411 1412 /** 1413 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1414 * @priv: driver private structure 1415 * @p: descriptor pointer 1416 * @i: descriptor index 1417 * @flags: gfp flag 1418 * @queue: RX queue index 1419 * Description: this function is called to allocate a receive buffer, perform 1420 * the DMA mapping and init the descriptor. 1421 */ 1422 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1423 int i, gfp_t flags, u32 queue) 1424 { 1425 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1426 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1427 1428 if (!buf->page) { 1429 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1430 if (!buf->page) 1431 return -ENOMEM; 1432 buf->page_offset = stmmac_rx_offset(priv); 1433 } 1434 1435 if (priv->sph && !buf->sec_page) { 1436 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1437 if (!buf->sec_page) 1438 return -ENOMEM; 1439 1440 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1441 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1442 } else { 1443 buf->sec_page = NULL; 1444 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1445 } 1446 1447 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1448 1449 stmmac_set_desc_addr(priv, p, buf->addr); 1450 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1451 stmmac_init_desc3(priv, p); 1452 1453 return 0; 1454 } 1455 1456 /** 1457 * stmmac_free_rx_buffer - free RX dma buffers 1458 * @priv: private structure 1459 * @queue: RX queue index 1460 * @i: buffer index. 1461 */ 1462 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1463 { 1464 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1465 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1466 1467 if (buf->page) 1468 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1469 buf->page = NULL; 1470 1471 if (buf->sec_page) 1472 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1473 buf->sec_page = NULL; 1474 } 1475 1476 /** 1477 * stmmac_free_tx_buffer - free RX dma buffers 1478 * @priv: private structure 1479 * @queue: RX queue index 1480 * @i: buffer index. 1481 */ 1482 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1483 { 1484 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1485 1486 if (tx_q->tx_skbuff_dma[i].buf && 1487 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1488 if (tx_q->tx_skbuff_dma[i].map_as_page) 1489 dma_unmap_page(priv->device, 1490 tx_q->tx_skbuff_dma[i].buf, 1491 tx_q->tx_skbuff_dma[i].len, 1492 DMA_TO_DEVICE); 1493 else 1494 dma_unmap_single(priv->device, 1495 tx_q->tx_skbuff_dma[i].buf, 1496 tx_q->tx_skbuff_dma[i].len, 1497 DMA_TO_DEVICE); 1498 } 1499 1500 if (tx_q->xdpf[i] && 1501 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1502 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1503 xdp_return_frame(tx_q->xdpf[i]); 1504 tx_q->xdpf[i] = NULL; 1505 } 1506 1507 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1508 tx_q->xsk_frames_done++; 1509 1510 if (tx_q->tx_skbuff[i] && 1511 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1512 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1513 tx_q->tx_skbuff[i] = NULL; 1514 } 1515 1516 tx_q->tx_skbuff_dma[i].buf = 0; 1517 tx_q->tx_skbuff_dma[i].map_as_page = false; 1518 } 1519 1520 /** 1521 * dma_free_rx_skbufs - free RX dma buffers 1522 * @priv: private structure 1523 * @queue: RX queue index 1524 */ 1525 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1526 { 1527 int i; 1528 1529 for (i = 0; i < priv->dma_rx_size; i++) 1530 stmmac_free_rx_buffer(priv, queue, i); 1531 } 1532 1533 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, 1534 gfp_t flags) 1535 { 1536 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1537 int i; 1538 1539 for (i = 0; i < priv->dma_rx_size; i++) { 1540 struct dma_desc *p; 1541 int ret; 1542 1543 if (priv->extend_desc) 1544 p = &((rx_q->dma_erx + i)->basic); 1545 else 1546 p = rx_q->dma_rx + i; 1547 1548 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1549 queue); 1550 if (ret) 1551 return ret; 1552 1553 rx_q->buf_alloc_num++; 1554 } 1555 1556 return 0; 1557 } 1558 1559 /** 1560 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1561 * @priv: private structure 1562 * @queue: RX queue index 1563 */ 1564 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) 1565 { 1566 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1567 int i; 1568 1569 for (i = 0; i < priv->dma_rx_size; i++) { 1570 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1571 1572 if (!buf->xdp) 1573 continue; 1574 1575 xsk_buff_free(buf->xdp); 1576 buf->xdp = NULL; 1577 } 1578 } 1579 1580 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) 1581 { 1582 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1583 int i; 1584 1585 for (i = 0; i < priv->dma_rx_size; i++) { 1586 struct stmmac_rx_buffer *buf; 1587 dma_addr_t dma_addr; 1588 struct dma_desc *p; 1589 1590 if (priv->extend_desc) 1591 p = (struct dma_desc *)(rx_q->dma_erx + i); 1592 else 1593 p = rx_q->dma_rx + i; 1594 1595 buf = &rx_q->buf_pool[i]; 1596 1597 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1598 if (!buf->xdp) 1599 return -ENOMEM; 1600 1601 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1602 stmmac_set_desc_addr(priv, p, dma_addr); 1603 rx_q->buf_alloc_num++; 1604 } 1605 1606 return 0; 1607 } 1608 1609 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1610 { 1611 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1612 return NULL; 1613 1614 return xsk_get_pool_from_qid(priv->dev, queue); 1615 } 1616 1617 /** 1618 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1619 * @priv: driver private structure 1620 * @queue: RX queue index 1621 * @flags: gfp flag. 1622 * Description: this function initializes the DMA RX descriptors 1623 * and allocates the socket buffers. It supports the chained and ring 1624 * modes. 1625 */ 1626 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) 1627 { 1628 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1629 int ret; 1630 1631 netif_dbg(priv, probe, priv->dev, 1632 "(%s) dma_rx_phy=0x%08x\n", __func__, 1633 (u32)rx_q->dma_rx_phy); 1634 1635 stmmac_clear_rx_descriptors(priv, queue); 1636 1637 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1638 1639 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1640 1641 if (rx_q->xsk_pool) { 1642 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1643 MEM_TYPE_XSK_BUFF_POOL, 1644 NULL)); 1645 netdev_info(priv->dev, 1646 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1647 rx_q->queue_index); 1648 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1649 } else { 1650 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1651 MEM_TYPE_PAGE_POOL, 1652 rx_q->page_pool)); 1653 netdev_info(priv->dev, 1654 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1655 rx_q->queue_index); 1656 } 1657 1658 if (rx_q->xsk_pool) { 1659 /* RX XDP ZC buffer pool may not be populated, e.g. 1660 * xdpsock TX-only. 1661 */ 1662 stmmac_alloc_rx_buffers_zc(priv, queue); 1663 } else { 1664 ret = stmmac_alloc_rx_buffers(priv, queue, flags); 1665 if (ret < 0) 1666 return -ENOMEM; 1667 } 1668 1669 rx_q->cur_rx = 0; 1670 rx_q->dirty_rx = 0; 1671 1672 /* Setup the chained descriptor addresses */ 1673 if (priv->mode == STMMAC_CHAIN_MODE) { 1674 if (priv->extend_desc) 1675 stmmac_mode_init(priv, rx_q->dma_erx, 1676 rx_q->dma_rx_phy, 1677 priv->dma_rx_size, 1); 1678 else 1679 stmmac_mode_init(priv, rx_q->dma_rx, 1680 rx_q->dma_rx_phy, 1681 priv->dma_rx_size, 0); 1682 } 1683 1684 return 0; 1685 } 1686 1687 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1688 { 1689 struct stmmac_priv *priv = netdev_priv(dev); 1690 u32 rx_count = priv->plat->rx_queues_to_use; 1691 u32 queue; 1692 int ret; 1693 1694 /* RX INITIALIZATION */ 1695 netif_dbg(priv, probe, priv->dev, 1696 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1697 1698 for (queue = 0; queue < rx_count; queue++) { 1699 ret = __init_dma_rx_desc_rings(priv, queue, flags); 1700 if (ret) 1701 goto err_init_rx_buffers; 1702 } 1703 1704 return 0; 1705 1706 err_init_rx_buffers: 1707 while (queue >= 0) { 1708 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1709 1710 if (rx_q->xsk_pool) 1711 dma_free_rx_xskbufs(priv, queue); 1712 else 1713 dma_free_rx_skbufs(priv, queue); 1714 1715 rx_q->buf_alloc_num = 0; 1716 rx_q->xsk_pool = NULL; 1717 1718 if (queue == 0) 1719 break; 1720 1721 queue--; 1722 } 1723 1724 return ret; 1725 } 1726 1727 /** 1728 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1729 * @priv: driver private structure 1730 * @queue : TX queue index 1731 * Description: this function initializes the DMA TX descriptors 1732 * and allocates the socket buffers. It supports the chained and ring 1733 * modes. 1734 */ 1735 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) 1736 { 1737 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1738 int i; 1739 1740 netif_dbg(priv, probe, priv->dev, 1741 "(%s) dma_tx_phy=0x%08x\n", __func__, 1742 (u32)tx_q->dma_tx_phy); 1743 1744 /* Setup the chained descriptor addresses */ 1745 if (priv->mode == STMMAC_CHAIN_MODE) { 1746 if (priv->extend_desc) 1747 stmmac_mode_init(priv, tx_q->dma_etx, 1748 tx_q->dma_tx_phy, 1749 priv->dma_tx_size, 1); 1750 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1751 stmmac_mode_init(priv, tx_q->dma_tx, 1752 tx_q->dma_tx_phy, 1753 priv->dma_tx_size, 0); 1754 } 1755 1756 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1757 1758 for (i = 0; i < priv->dma_tx_size; i++) { 1759 struct dma_desc *p; 1760 1761 if (priv->extend_desc) 1762 p = &((tx_q->dma_etx + i)->basic); 1763 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1764 p = &((tx_q->dma_entx + i)->basic); 1765 else 1766 p = tx_q->dma_tx + i; 1767 1768 stmmac_clear_desc(priv, p); 1769 1770 tx_q->tx_skbuff_dma[i].buf = 0; 1771 tx_q->tx_skbuff_dma[i].map_as_page = false; 1772 tx_q->tx_skbuff_dma[i].len = 0; 1773 tx_q->tx_skbuff_dma[i].last_segment = false; 1774 tx_q->tx_skbuff[i] = NULL; 1775 } 1776 1777 tx_q->dirty_tx = 0; 1778 tx_q->cur_tx = 0; 1779 tx_q->mss = 0; 1780 1781 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1782 1783 return 0; 1784 } 1785 1786 static int init_dma_tx_desc_rings(struct net_device *dev) 1787 { 1788 struct stmmac_priv *priv = netdev_priv(dev); 1789 u32 tx_queue_cnt; 1790 u32 queue; 1791 1792 tx_queue_cnt = priv->plat->tx_queues_to_use; 1793 1794 for (queue = 0; queue < tx_queue_cnt; queue++) 1795 __init_dma_tx_desc_rings(priv, queue); 1796 1797 return 0; 1798 } 1799 1800 /** 1801 * init_dma_desc_rings - init the RX/TX descriptor rings 1802 * @dev: net device structure 1803 * @flags: gfp flag. 1804 * Description: this function initializes the DMA RX/TX descriptors 1805 * and allocates the socket buffers. It supports the chained and ring 1806 * modes. 1807 */ 1808 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1809 { 1810 struct stmmac_priv *priv = netdev_priv(dev); 1811 int ret; 1812 1813 ret = init_dma_rx_desc_rings(dev, flags); 1814 if (ret) 1815 return ret; 1816 1817 ret = init_dma_tx_desc_rings(dev); 1818 1819 stmmac_clear_descriptors(priv); 1820 1821 if (netif_msg_hw(priv)) 1822 stmmac_display_rings(priv); 1823 1824 return ret; 1825 } 1826 1827 /** 1828 * dma_free_tx_skbufs - free TX dma buffers 1829 * @priv: private structure 1830 * @queue: TX queue index 1831 */ 1832 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1833 { 1834 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1835 int i; 1836 1837 tx_q->xsk_frames_done = 0; 1838 1839 for (i = 0; i < priv->dma_tx_size; i++) 1840 stmmac_free_tx_buffer(priv, queue, i); 1841 1842 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1843 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1844 tx_q->xsk_frames_done = 0; 1845 tx_q->xsk_pool = NULL; 1846 } 1847 } 1848 1849 /** 1850 * stmmac_free_tx_skbufs - free TX skb buffers 1851 * @priv: private structure 1852 */ 1853 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1854 { 1855 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1856 u32 queue; 1857 1858 for (queue = 0; queue < tx_queue_cnt; queue++) 1859 dma_free_tx_skbufs(priv, queue); 1860 } 1861 1862 /** 1863 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1864 * @priv: private structure 1865 * @queue: RX queue index 1866 */ 1867 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1868 { 1869 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1870 1871 /* Release the DMA RX socket buffers */ 1872 if (rx_q->xsk_pool) 1873 dma_free_rx_xskbufs(priv, queue); 1874 else 1875 dma_free_rx_skbufs(priv, queue); 1876 1877 rx_q->buf_alloc_num = 0; 1878 rx_q->xsk_pool = NULL; 1879 1880 /* Free DMA regions of consistent memory previously allocated */ 1881 if (!priv->extend_desc) 1882 dma_free_coherent(priv->device, priv->dma_rx_size * 1883 sizeof(struct dma_desc), 1884 rx_q->dma_rx, rx_q->dma_rx_phy); 1885 else 1886 dma_free_coherent(priv->device, priv->dma_rx_size * 1887 sizeof(struct dma_extended_desc), 1888 rx_q->dma_erx, rx_q->dma_rx_phy); 1889 1890 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1891 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1892 1893 kfree(rx_q->buf_pool); 1894 if (rx_q->page_pool) 1895 page_pool_destroy(rx_q->page_pool); 1896 } 1897 1898 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1899 { 1900 u32 rx_count = priv->plat->rx_queues_to_use; 1901 u32 queue; 1902 1903 /* Free RX queue resources */ 1904 for (queue = 0; queue < rx_count; queue++) 1905 __free_dma_rx_desc_resources(priv, queue); 1906 } 1907 1908 /** 1909 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1910 * @priv: private structure 1911 * @queue: TX queue index 1912 */ 1913 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 1914 { 1915 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1916 size_t size; 1917 void *addr; 1918 1919 /* Release the DMA TX socket buffers */ 1920 dma_free_tx_skbufs(priv, queue); 1921 1922 if (priv->extend_desc) { 1923 size = sizeof(struct dma_extended_desc); 1924 addr = tx_q->dma_etx; 1925 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1926 size = sizeof(struct dma_edesc); 1927 addr = tx_q->dma_entx; 1928 } else { 1929 size = sizeof(struct dma_desc); 1930 addr = tx_q->dma_tx; 1931 } 1932 1933 size *= priv->dma_tx_size; 1934 1935 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1936 1937 kfree(tx_q->tx_skbuff_dma); 1938 kfree(tx_q->tx_skbuff); 1939 } 1940 1941 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1942 { 1943 u32 tx_count = priv->plat->tx_queues_to_use; 1944 u32 queue; 1945 1946 /* Free TX queue resources */ 1947 for (queue = 0; queue < tx_count; queue++) 1948 __free_dma_tx_desc_resources(priv, queue); 1949 } 1950 1951 /** 1952 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1953 * @priv: private structure 1954 * @queue: RX queue index 1955 * Description: according to which descriptor can be used (extend or basic) 1956 * this function allocates the resources for TX and RX paths. In case of 1957 * reception, for example, it pre-allocated the RX socket buffer in order to 1958 * allow zero-copy mechanism. 1959 */ 1960 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1961 { 1962 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1963 struct stmmac_channel *ch = &priv->channel[queue]; 1964 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1965 struct page_pool_params pp_params = { 0 }; 1966 unsigned int num_pages; 1967 unsigned int napi_id; 1968 int ret; 1969 1970 rx_q->queue_index = queue; 1971 rx_q->priv_data = priv; 1972 1973 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1974 pp_params.pool_size = priv->dma_rx_size; 1975 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1976 pp_params.order = ilog2(num_pages); 1977 pp_params.nid = dev_to_node(priv->device); 1978 pp_params.dev = priv->device; 1979 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1980 pp_params.offset = stmmac_rx_offset(priv); 1981 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 1982 1983 rx_q->page_pool = page_pool_create(&pp_params); 1984 if (IS_ERR(rx_q->page_pool)) { 1985 ret = PTR_ERR(rx_q->page_pool); 1986 rx_q->page_pool = NULL; 1987 return ret; 1988 } 1989 1990 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1991 sizeof(*rx_q->buf_pool), 1992 GFP_KERNEL); 1993 if (!rx_q->buf_pool) 1994 return -ENOMEM; 1995 1996 if (priv->extend_desc) { 1997 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1998 priv->dma_rx_size * 1999 sizeof(struct dma_extended_desc), 2000 &rx_q->dma_rx_phy, 2001 GFP_KERNEL); 2002 if (!rx_q->dma_erx) 2003 return -ENOMEM; 2004 2005 } else { 2006 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2007 priv->dma_rx_size * 2008 sizeof(struct dma_desc), 2009 &rx_q->dma_rx_phy, 2010 GFP_KERNEL); 2011 if (!rx_q->dma_rx) 2012 return -ENOMEM; 2013 } 2014 2015 if (stmmac_xdp_is_enabled(priv) && 2016 test_bit(queue, priv->af_xdp_zc_qps)) 2017 napi_id = ch->rxtx_napi.napi_id; 2018 else 2019 napi_id = ch->rx_napi.napi_id; 2020 2021 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2022 rx_q->queue_index, 2023 napi_id); 2024 if (ret) { 2025 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2026 return -EINVAL; 2027 } 2028 2029 return 0; 2030 } 2031 2032 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 2033 { 2034 u32 rx_count = priv->plat->rx_queues_to_use; 2035 u32 queue; 2036 int ret; 2037 2038 /* RX queues buffers and DMA */ 2039 for (queue = 0; queue < rx_count; queue++) { 2040 ret = __alloc_dma_rx_desc_resources(priv, queue); 2041 if (ret) 2042 goto err_dma; 2043 } 2044 2045 return 0; 2046 2047 err_dma: 2048 free_dma_rx_desc_resources(priv); 2049 2050 return ret; 2051 } 2052 2053 /** 2054 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2055 * @priv: private structure 2056 * @queue: TX queue index 2057 * Description: according to which descriptor can be used (extend or basic) 2058 * this function allocates the resources for TX and RX paths. In case of 2059 * reception, for example, it pre-allocated the RX socket buffer in order to 2060 * allow zero-copy mechanism. 2061 */ 2062 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 2063 { 2064 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2065 size_t size; 2066 void *addr; 2067 2068 tx_q->queue_index = queue; 2069 tx_q->priv_data = priv; 2070 2071 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 2072 sizeof(*tx_q->tx_skbuff_dma), 2073 GFP_KERNEL); 2074 if (!tx_q->tx_skbuff_dma) 2075 return -ENOMEM; 2076 2077 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 2078 sizeof(struct sk_buff *), 2079 GFP_KERNEL); 2080 if (!tx_q->tx_skbuff) 2081 return -ENOMEM; 2082 2083 if (priv->extend_desc) 2084 size = sizeof(struct dma_extended_desc); 2085 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2086 size = sizeof(struct dma_edesc); 2087 else 2088 size = sizeof(struct dma_desc); 2089 2090 size *= priv->dma_tx_size; 2091 2092 addr = dma_alloc_coherent(priv->device, size, 2093 &tx_q->dma_tx_phy, GFP_KERNEL); 2094 if (!addr) 2095 return -ENOMEM; 2096 2097 if (priv->extend_desc) 2098 tx_q->dma_etx = addr; 2099 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2100 tx_q->dma_entx = addr; 2101 else 2102 tx_q->dma_tx = addr; 2103 2104 return 0; 2105 } 2106 2107 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 2108 { 2109 u32 tx_count = priv->plat->tx_queues_to_use; 2110 u32 queue; 2111 int ret; 2112 2113 /* TX queues buffers and DMA */ 2114 for (queue = 0; queue < tx_count; queue++) { 2115 ret = __alloc_dma_tx_desc_resources(priv, queue); 2116 if (ret) 2117 goto err_dma; 2118 } 2119 2120 return 0; 2121 2122 err_dma: 2123 free_dma_tx_desc_resources(priv); 2124 return ret; 2125 } 2126 2127 /** 2128 * alloc_dma_desc_resources - alloc TX/RX resources. 2129 * @priv: private structure 2130 * Description: according to which descriptor can be used (extend or basic) 2131 * this function allocates the resources for TX and RX paths. In case of 2132 * reception, for example, it pre-allocated the RX socket buffer in order to 2133 * allow zero-copy mechanism. 2134 */ 2135 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 2136 { 2137 /* RX Allocation */ 2138 int ret = alloc_dma_rx_desc_resources(priv); 2139 2140 if (ret) 2141 return ret; 2142 2143 ret = alloc_dma_tx_desc_resources(priv); 2144 2145 return ret; 2146 } 2147 2148 /** 2149 * free_dma_desc_resources - free dma desc resources 2150 * @priv: private structure 2151 */ 2152 static void free_dma_desc_resources(struct stmmac_priv *priv) 2153 { 2154 /* Release the DMA TX socket buffers */ 2155 free_dma_tx_desc_resources(priv); 2156 2157 /* Release the DMA RX socket buffers later 2158 * to ensure all pending XDP_TX buffers are returned. 2159 */ 2160 free_dma_rx_desc_resources(priv); 2161 } 2162 2163 /** 2164 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2165 * @priv: driver private structure 2166 * Description: It is used for enabling the rx queues in the MAC 2167 */ 2168 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2169 { 2170 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2171 int queue; 2172 u8 mode; 2173 2174 for (queue = 0; queue < rx_queues_count; queue++) { 2175 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2176 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2177 } 2178 } 2179 2180 /** 2181 * stmmac_start_rx_dma - start RX DMA channel 2182 * @priv: driver private structure 2183 * @chan: RX channel index 2184 * Description: 2185 * This starts a RX DMA channel 2186 */ 2187 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2188 { 2189 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2190 stmmac_start_rx(priv, priv->ioaddr, chan); 2191 } 2192 2193 /** 2194 * stmmac_start_tx_dma - start TX DMA channel 2195 * @priv: driver private structure 2196 * @chan: TX channel index 2197 * Description: 2198 * This starts a TX DMA channel 2199 */ 2200 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2201 { 2202 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2203 stmmac_start_tx(priv, priv->ioaddr, chan); 2204 } 2205 2206 /** 2207 * stmmac_stop_rx_dma - stop RX DMA channel 2208 * @priv: driver private structure 2209 * @chan: RX channel index 2210 * Description: 2211 * This stops a RX DMA channel 2212 */ 2213 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2214 { 2215 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2216 stmmac_stop_rx(priv, priv->ioaddr, chan); 2217 } 2218 2219 /** 2220 * stmmac_stop_tx_dma - stop TX DMA channel 2221 * @priv: driver private structure 2222 * @chan: TX channel index 2223 * Description: 2224 * This stops a TX DMA channel 2225 */ 2226 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2227 { 2228 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2229 stmmac_stop_tx(priv, priv->ioaddr, chan); 2230 } 2231 2232 /** 2233 * stmmac_start_all_dma - start all RX and TX DMA channels 2234 * @priv: driver private structure 2235 * Description: 2236 * This starts all the RX and TX DMA channels 2237 */ 2238 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2239 { 2240 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2241 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2242 u32 chan = 0; 2243 2244 for (chan = 0; chan < rx_channels_count; chan++) 2245 stmmac_start_rx_dma(priv, chan); 2246 2247 for (chan = 0; chan < tx_channels_count; chan++) 2248 stmmac_start_tx_dma(priv, chan); 2249 } 2250 2251 /** 2252 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2253 * @priv: driver private structure 2254 * Description: 2255 * This stops the RX and TX DMA channels 2256 */ 2257 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2258 { 2259 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2260 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2261 u32 chan = 0; 2262 2263 for (chan = 0; chan < rx_channels_count; chan++) 2264 stmmac_stop_rx_dma(priv, chan); 2265 2266 for (chan = 0; chan < tx_channels_count; chan++) 2267 stmmac_stop_tx_dma(priv, chan); 2268 } 2269 2270 /** 2271 * stmmac_dma_operation_mode - HW DMA operation mode 2272 * @priv: driver private structure 2273 * Description: it is used for configuring the DMA operation mode register in 2274 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2275 */ 2276 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2277 { 2278 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2279 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2280 int rxfifosz = priv->plat->rx_fifo_size; 2281 int txfifosz = priv->plat->tx_fifo_size; 2282 u32 txmode = 0; 2283 u32 rxmode = 0; 2284 u32 chan = 0; 2285 u8 qmode = 0; 2286 2287 if (rxfifosz == 0) 2288 rxfifosz = priv->dma_cap.rx_fifo_size; 2289 if (txfifosz == 0) 2290 txfifosz = priv->dma_cap.tx_fifo_size; 2291 2292 /* Adjust for real per queue fifo size */ 2293 rxfifosz /= rx_channels_count; 2294 txfifosz /= tx_channels_count; 2295 2296 if (priv->plat->force_thresh_dma_mode) { 2297 txmode = tc; 2298 rxmode = tc; 2299 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2300 /* 2301 * In case of GMAC, SF mode can be enabled 2302 * to perform the TX COE in HW. This depends on: 2303 * 1) TX COE if actually supported 2304 * 2) There is no bugged Jumbo frame support 2305 * that needs to not insert csum in the TDES. 2306 */ 2307 txmode = SF_DMA_MODE; 2308 rxmode = SF_DMA_MODE; 2309 priv->xstats.threshold = SF_DMA_MODE; 2310 } else { 2311 txmode = tc; 2312 rxmode = SF_DMA_MODE; 2313 } 2314 2315 /* configure all channels */ 2316 for (chan = 0; chan < rx_channels_count; chan++) { 2317 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2318 u32 buf_size; 2319 2320 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2321 2322 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2323 rxfifosz, qmode); 2324 2325 if (rx_q->xsk_pool) { 2326 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2327 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2328 buf_size, 2329 chan); 2330 } else { 2331 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2332 priv->dma_buf_sz, 2333 chan); 2334 } 2335 } 2336 2337 for (chan = 0; chan < tx_channels_count; chan++) { 2338 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2339 2340 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2341 txfifosz, qmode); 2342 } 2343 } 2344 2345 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2346 { 2347 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2348 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2349 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2350 unsigned int entry = tx_q->cur_tx; 2351 struct dma_desc *tx_desc = NULL; 2352 struct xdp_desc xdp_desc; 2353 bool work_done = true; 2354 2355 /* Avoids TX time-out as we are sharing with slow path */ 2356 nq->trans_start = jiffies; 2357 2358 budget = min(budget, stmmac_tx_avail(priv, queue)); 2359 2360 while (budget-- > 0) { 2361 dma_addr_t dma_addr; 2362 bool set_ic; 2363 2364 /* We are sharing with slow path and stop XSK TX desc submission when 2365 * available TX ring is less than threshold. 2366 */ 2367 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2368 !netif_carrier_ok(priv->dev)) { 2369 work_done = false; 2370 break; 2371 } 2372 2373 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2374 break; 2375 2376 if (likely(priv->extend_desc)) 2377 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2378 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2379 tx_desc = &tx_q->dma_entx[entry].basic; 2380 else 2381 tx_desc = tx_q->dma_tx + entry; 2382 2383 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2384 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2385 2386 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2387 2388 /* To return XDP buffer to XSK pool, we simple call 2389 * xsk_tx_completed(), so we don't need to fill up 2390 * 'buf' and 'xdpf'. 2391 */ 2392 tx_q->tx_skbuff_dma[entry].buf = 0; 2393 tx_q->xdpf[entry] = NULL; 2394 2395 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2396 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2397 tx_q->tx_skbuff_dma[entry].last_segment = true; 2398 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2399 2400 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2401 2402 tx_q->tx_count_frames++; 2403 2404 if (!priv->tx_coal_frames[queue]) 2405 set_ic = false; 2406 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2407 set_ic = true; 2408 else 2409 set_ic = false; 2410 2411 if (set_ic) { 2412 tx_q->tx_count_frames = 0; 2413 stmmac_set_tx_ic(priv, tx_desc); 2414 priv->xstats.tx_set_ic_bit++; 2415 } 2416 2417 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2418 true, priv->mode, true, true, 2419 xdp_desc.len); 2420 2421 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2422 2423 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2424 entry = tx_q->cur_tx; 2425 } 2426 2427 if (tx_desc) { 2428 stmmac_flush_tx_descriptors(priv, queue); 2429 xsk_tx_release(pool); 2430 } 2431 2432 /* Return true if all of the 3 conditions are met 2433 * a) TX Budget is still available 2434 * b) work_done = true when XSK TX desc peek is empty (no more 2435 * pending XSK TX for transmission) 2436 */ 2437 return !!budget && work_done; 2438 } 2439 2440 /** 2441 * stmmac_tx_clean - to manage the transmission completion 2442 * @priv: driver private structure 2443 * @budget: napi budget limiting this functions packet handling 2444 * @queue: TX queue index 2445 * Description: it reclaims the transmit resources after transmission completes. 2446 */ 2447 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2448 { 2449 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2450 unsigned int bytes_compl = 0, pkts_compl = 0; 2451 unsigned int entry, xmits = 0, count = 0; 2452 2453 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2454 2455 priv->xstats.tx_clean++; 2456 2457 tx_q->xsk_frames_done = 0; 2458 2459 entry = tx_q->dirty_tx; 2460 2461 /* Try to clean all TX complete frame in 1 shot */ 2462 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { 2463 struct xdp_frame *xdpf; 2464 struct sk_buff *skb; 2465 struct dma_desc *p; 2466 int status; 2467 2468 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2469 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2470 xdpf = tx_q->xdpf[entry]; 2471 skb = NULL; 2472 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2473 xdpf = NULL; 2474 skb = tx_q->tx_skbuff[entry]; 2475 } else { 2476 xdpf = NULL; 2477 skb = NULL; 2478 } 2479 2480 if (priv->extend_desc) 2481 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2482 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2483 p = &tx_q->dma_entx[entry].basic; 2484 else 2485 p = tx_q->dma_tx + entry; 2486 2487 status = stmmac_tx_status(priv, &priv->dev->stats, 2488 &priv->xstats, p, priv->ioaddr); 2489 /* Check if the descriptor is owned by the DMA */ 2490 if (unlikely(status & tx_dma_own)) 2491 break; 2492 2493 count++; 2494 2495 /* Make sure descriptor fields are read after reading 2496 * the own bit. 2497 */ 2498 dma_rmb(); 2499 2500 /* Just consider the last segment and ...*/ 2501 if (likely(!(status & tx_not_ls))) { 2502 /* ... verify the status error condition */ 2503 if (unlikely(status & tx_err)) { 2504 priv->dev->stats.tx_errors++; 2505 } else { 2506 priv->dev->stats.tx_packets++; 2507 priv->xstats.tx_pkt_n++; 2508 priv->xstats.txq_stats[queue].tx_pkt_n++; 2509 } 2510 if (skb) 2511 stmmac_get_tx_hwtstamp(priv, p, skb); 2512 } 2513 2514 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2515 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2516 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2517 dma_unmap_page(priv->device, 2518 tx_q->tx_skbuff_dma[entry].buf, 2519 tx_q->tx_skbuff_dma[entry].len, 2520 DMA_TO_DEVICE); 2521 else 2522 dma_unmap_single(priv->device, 2523 tx_q->tx_skbuff_dma[entry].buf, 2524 tx_q->tx_skbuff_dma[entry].len, 2525 DMA_TO_DEVICE); 2526 tx_q->tx_skbuff_dma[entry].buf = 0; 2527 tx_q->tx_skbuff_dma[entry].len = 0; 2528 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2529 } 2530 2531 stmmac_clean_desc3(priv, tx_q, p); 2532 2533 tx_q->tx_skbuff_dma[entry].last_segment = false; 2534 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2535 2536 if (xdpf && 2537 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2538 xdp_return_frame_rx_napi(xdpf); 2539 tx_q->xdpf[entry] = NULL; 2540 } 2541 2542 if (xdpf && 2543 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2544 xdp_return_frame(xdpf); 2545 tx_q->xdpf[entry] = NULL; 2546 } 2547 2548 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2549 tx_q->xsk_frames_done++; 2550 2551 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2552 if (likely(skb)) { 2553 pkts_compl++; 2554 bytes_compl += skb->len; 2555 dev_consume_skb_any(skb); 2556 tx_q->tx_skbuff[entry] = NULL; 2557 } 2558 } 2559 2560 stmmac_release_tx_desc(priv, p, priv->mode); 2561 2562 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2563 } 2564 tx_q->dirty_tx = entry; 2565 2566 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2567 pkts_compl, bytes_compl); 2568 2569 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2570 queue))) && 2571 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2572 2573 netif_dbg(priv, tx_done, priv->dev, 2574 "%s: restart transmit\n", __func__); 2575 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2576 } 2577 2578 if (tx_q->xsk_pool) { 2579 bool work_done; 2580 2581 if (tx_q->xsk_frames_done) 2582 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2583 2584 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2585 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2586 2587 /* For XSK TX, we try to send as many as possible. 2588 * If XSK work done (XSK TX desc empty and budget still 2589 * available), return "budget - 1" to reenable TX IRQ. 2590 * Else, return "budget" to make NAPI continue polling. 2591 */ 2592 work_done = stmmac_xdp_xmit_zc(priv, queue, 2593 STMMAC_XSK_TX_BUDGET_MAX); 2594 if (work_done) 2595 xmits = budget - 1; 2596 else 2597 xmits = budget; 2598 } 2599 2600 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2601 priv->eee_sw_timer_en) { 2602 stmmac_enable_eee_mode(priv); 2603 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2604 } 2605 2606 /* We still have pending packets, let's call for a new scheduling */ 2607 if (tx_q->dirty_tx != tx_q->cur_tx) 2608 hrtimer_start(&tx_q->txtimer, 2609 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2610 HRTIMER_MODE_REL); 2611 2612 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2613 2614 /* Combine decisions from TX clean and XSK TX */ 2615 return max(count, xmits); 2616 } 2617 2618 /** 2619 * stmmac_tx_err - to manage the tx error 2620 * @priv: driver private structure 2621 * @chan: channel index 2622 * Description: it cleans the descriptors and restarts the transmission 2623 * in case of transmission errors. 2624 */ 2625 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2626 { 2627 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2628 2629 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2630 2631 stmmac_stop_tx_dma(priv, chan); 2632 dma_free_tx_skbufs(priv, chan); 2633 stmmac_clear_tx_descriptors(priv, chan); 2634 tx_q->dirty_tx = 0; 2635 tx_q->cur_tx = 0; 2636 tx_q->mss = 0; 2637 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2638 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2639 tx_q->dma_tx_phy, chan); 2640 stmmac_start_tx_dma(priv, chan); 2641 2642 priv->dev->stats.tx_errors++; 2643 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2644 } 2645 2646 /** 2647 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2648 * @priv: driver private structure 2649 * @txmode: TX operating mode 2650 * @rxmode: RX operating mode 2651 * @chan: channel index 2652 * Description: it is used for configuring of the DMA operation mode in 2653 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2654 * mode. 2655 */ 2656 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2657 u32 rxmode, u32 chan) 2658 { 2659 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2660 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2661 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2662 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2663 int rxfifosz = priv->plat->rx_fifo_size; 2664 int txfifosz = priv->plat->tx_fifo_size; 2665 2666 if (rxfifosz == 0) 2667 rxfifosz = priv->dma_cap.rx_fifo_size; 2668 if (txfifosz == 0) 2669 txfifosz = priv->dma_cap.tx_fifo_size; 2670 2671 /* Adjust for real per queue fifo size */ 2672 rxfifosz /= rx_channels_count; 2673 txfifosz /= tx_channels_count; 2674 2675 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2676 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2677 } 2678 2679 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2680 { 2681 int ret; 2682 2683 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2684 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2685 if (ret && (ret != -EINVAL)) { 2686 stmmac_global_err(priv); 2687 return true; 2688 } 2689 2690 return false; 2691 } 2692 2693 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2694 { 2695 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2696 &priv->xstats, chan, dir); 2697 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2698 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2699 struct stmmac_channel *ch = &priv->channel[chan]; 2700 struct napi_struct *rx_napi; 2701 struct napi_struct *tx_napi; 2702 unsigned long flags; 2703 2704 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2705 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2706 2707 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2708 if (napi_schedule_prep(rx_napi)) { 2709 spin_lock_irqsave(&ch->lock, flags); 2710 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2711 spin_unlock_irqrestore(&ch->lock, flags); 2712 __napi_schedule(rx_napi); 2713 } 2714 } 2715 2716 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2717 if (napi_schedule_prep(tx_napi)) { 2718 spin_lock_irqsave(&ch->lock, flags); 2719 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2720 spin_unlock_irqrestore(&ch->lock, flags); 2721 __napi_schedule(tx_napi); 2722 } 2723 } 2724 2725 return status; 2726 } 2727 2728 /** 2729 * stmmac_dma_interrupt - DMA ISR 2730 * @priv: driver private structure 2731 * Description: this is the DMA ISR. It is called by the main ISR. 2732 * It calls the dwmac dma routine and schedule poll method in case of some 2733 * work can be done. 2734 */ 2735 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2736 { 2737 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2738 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2739 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2740 tx_channel_count : rx_channel_count; 2741 u32 chan; 2742 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2743 2744 /* Make sure we never check beyond our status buffer. */ 2745 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2746 channels_to_check = ARRAY_SIZE(status); 2747 2748 for (chan = 0; chan < channels_to_check; chan++) 2749 status[chan] = stmmac_napi_check(priv, chan, 2750 DMA_DIR_RXTX); 2751 2752 for (chan = 0; chan < tx_channel_count; chan++) { 2753 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2754 /* Try to bump up the dma threshold on this failure */ 2755 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2756 (tc <= 256)) { 2757 tc += 64; 2758 if (priv->plat->force_thresh_dma_mode) 2759 stmmac_set_dma_operation_mode(priv, 2760 tc, 2761 tc, 2762 chan); 2763 else 2764 stmmac_set_dma_operation_mode(priv, 2765 tc, 2766 SF_DMA_MODE, 2767 chan); 2768 priv->xstats.threshold = tc; 2769 } 2770 } else if (unlikely(status[chan] == tx_hard_error)) { 2771 stmmac_tx_err(priv, chan); 2772 } 2773 } 2774 } 2775 2776 /** 2777 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2778 * @priv: driver private structure 2779 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2780 */ 2781 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2782 { 2783 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2784 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2785 2786 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2787 2788 if (priv->dma_cap.rmon) { 2789 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2790 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2791 } else 2792 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2793 } 2794 2795 /** 2796 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2797 * @priv: driver private structure 2798 * Description: 2799 * new GMAC chip generations have a new register to indicate the 2800 * presence of the optional feature/functions. 2801 * This can be also used to override the value passed through the 2802 * platform and necessary for old MAC10/100 and GMAC chips. 2803 */ 2804 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2805 { 2806 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2807 } 2808 2809 /** 2810 * stmmac_check_ether_addr - check if the MAC addr is valid 2811 * @priv: driver private structure 2812 * Description: 2813 * it is to verify if the MAC address is valid, in case of failures it 2814 * generates a random MAC address 2815 */ 2816 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2817 { 2818 u8 addr[ETH_ALEN]; 2819 2820 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2821 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2822 if (is_valid_ether_addr(addr)) 2823 eth_hw_addr_set(priv->dev, addr); 2824 else 2825 eth_hw_addr_random(priv->dev); 2826 dev_info(priv->device, "device MAC address %pM\n", 2827 priv->dev->dev_addr); 2828 } 2829 } 2830 2831 /** 2832 * stmmac_init_dma_engine - DMA init. 2833 * @priv: driver private structure 2834 * Description: 2835 * It inits the DMA invoking the specific MAC/GMAC callback. 2836 * Some DMA parameters can be passed from the platform; 2837 * in case of these are not passed a default is kept for the MAC or GMAC. 2838 */ 2839 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2840 { 2841 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2842 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2843 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2844 struct stmmac_rx_queue *rx_q; 2845 struct stmmac_tx_queue *tx_q; 2846 u32 chan = 0; 2847 int atds = 0; 2848 int ret = 0; 2849 2850 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2851 dev_err(priv->device, "Invalid DMA configuration\n"); 2852 return -EINVAL; 2853 } 2854 2855 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2856 atds = 1; 2857 2858 ret = stmmac_reset(priv, priv->ioaddr); 2859 if (ret) { 2860 dev_err(priv->device, "Failed to reset the dma\n"); 2861 return ret; 2862 } 2863 2864 /* DMA Configuration */ 2865 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2866 2867 if (priv->plat->axi) 2868 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2869 2870 /* DMA CSR Channel configuration */ 2871 for (chan = 0; chan < dma_csr_ch; chan++) 2872 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2873 2874 /* DMA RX Channel Configuration */ 2875 for (chan = 0; chan < rx_channels_count; chan++) { 2876 rx_q = &priv->rx_queue[chan]; 2877 2878 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2879 rx_q->dma_rx_phy, chan); 2880 2881 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2882 (rx_q->buf_alloc_num * 2883 sizeof(struct dma_desc)); 2884 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2885 rx_q->rx_tail_addr, chan); 2886 } 2887 2888 /* DMA TX Channel Configuration */ 2889 for (chan = 0; chan < tx_channels_count; chan++) { 2890 tx_q = &priv->tx_queue[chan]; 2891 2892 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2893 tx_q->dma_tx_phy, chan); 2894 2895 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2896 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2897 tx_q->tx_tail_addr, chan); 2898 } 2899 2900 return ret; 2901 } 2902 2903 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2904 { 2905 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2906 2907 hrtimer_start(&tx_q->txtimer, 2908 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2909 HRTIMER_MODE_REL); 2910 } 2911 2912 /** 2913 * stmmac_tx_timer - mitigation sw timer for tx. 2914 * @t: data pointer 2915 * Description: 2916 * This is the timer handler to directly invoke the stmmac_tx_clean. 2917 */ 2918 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2919 { 2920 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2921 struct stmmac_priv *priv = tx_q->priv_data; 2922 struct stmmac_channel *ch; 2923 struct napi_struct *napi; 2924 2925 ch = &priv->channel[tx_q->queue_index]; 2926 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2927 2928 if (likely(napi_schedule_prep(napi))) { 2929 unsigned long flags; 2930 2931 spin_lock_irqsave(&ch->lock, flags); 2932 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2933 spin_unlock_irqrestore(&ch->lock, flags); 2934 __napi_schedule(napi); 2935 } 2936 2937 return HRTIMER_NORESTART; 2938 } 2939 2940 /** 2941 * stmmac_init_coalesce - init mitigation options. 2942 * @priv: driver private structure 2943 * Description: 2944 * This inits the coalesce parameters: i.e. timer rate, 2945 * timer handler and default threshold used for enabling the 2946 * interrupt on completion bit. 2947 */ 2948 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2949 { 2950 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2951 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2952 u32 chan; 2953 2954 for (chan = 0; chan < tx_channel_count; chan++) { 2955 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2956 2957 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 2958 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 2959 2960 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2961 tx_q->txtimer.function = stmmac_tx_timer; 2962 } 2963 2964 for (chan = 0; chan < rx_channel_count; chan++) 2965 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 2966 } 2967 2968 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2969 { 2970 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2971 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2972 u32 chan; 2973 2974 /* set TX ring length */ 2975 for (chan = 0; chan < tx_channels_count; chan++) 2976 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2977 (priv->dma_tx_size - 1), chan); 2978 2979 /* set RX ring length */ 2980 for (chan = 0; chan < rx_channels_count; chan++) 2981 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2982 (priv->dma_rx_size - 1), chan); 2983 } 2984 2985 /** 2986 * stmmac_set_tx_queue_weight - Set TX queue weight 2987 * @priv: driver private structure 2988 * Description: It is used for setting TX queues weight 2989 */ 2990 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2991 { 2992 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2993 u32 weight; 2994 u32 queue; 2995 2996 for (queue = 0; queue < tx_queues_count; queue++) { 2997 weight = priv->plat->tx_queues_cfg[queue].weight; 2998 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2999 } 3000 } 3001 3002 /** 3003 * stmmac_configure_cbs - Configure CBS in TX queue 3004 * @priv: driver private structure 3005 * Description: It is used for configuring CBS in AVB TX queues 3006 */ 3007 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3008 { 3009 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3010 u32 mode_to_use; 3011 u32 queue; 3012 3013 /* queue 0 is reserved for legacy traffic */ 3014 for (queue = 1; queue < tx_queues_count; queue++) { 3015 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3016 if (mode_to_use == MTL_QUEUE_DCB) 3017 continue; 3018 3019 stmmac_config_cbs(priv, priv->hw, 3020 priv->plat->tx_queues_cfg[queue].send_slope, 3021 priv->plat->tx_queues_cfg[queue].idle_slope, 3022 priv->plat->tx_queues_cfg[queue].high_credit, 3023 priv->plat->tx_queues_cfg[queue].low_credit, 3024 queue); 3025 } 3026 } 3027 3028 /** 3029 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3030 * @priv: driver private structure 3031 * Description: It is used for mapping RX queues to RX dma channels 3032 */ 3033 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3034 { 3035 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3036 u32 queue; 3037 u32 chan; 3038 3039 for (queue = 0; queue < rx_queues_count; queue++) { 3040 chan = priv->plat->rx_queues_cfg[queue].chan; 3041 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3042 } 3043 } 3044 3045 /** 3046 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3047 * @priv: driver private structure 3048 * Description: It is used for configuring the RX Queue Priority 3049 */ 3050 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3051 { 3052 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3053 u32 queue; 3054 u32 prio; 3055 3056 for (queue = 0; queue < rx_queues_count; queue++) { 3057 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3058 continue; 3059 3060 prio = priv->plat->rx_queues_cfg[queue].prio; 3061 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3062 } 3063 } 3064 3065 /** 3066 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3067 * @priv: driver private structure 3068 * Description: It is used for configuring the TX Queue Priority 3069 */ 3070 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3071 { 3072 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3073 u32 queue; 3074 u32 prio; 3075 3076 for (queue = 0; queue < tx_queues_count; queue++) { 3077 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3078 continue; 3079 3080 prio = priv->plat->tx_queues_cfg[queue].prio; 3081 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3082 } 3083 } 3084 3085 /** 3086 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3087 * @priv: driver private structure 3088 * Description: It is used for configuring the RX queue routing 3089 */ 3090 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3091 { 3092 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3093 u32 queue; 3094 u8 packet; 3095 3096 for (queue = 0; queue < rx_queues_count; queue++) { 3097 /* no specific packet type routing specified for the queue */ 3098 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3099 continue; 3100 3101 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3102 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3103 } 3104 } 3105 3106 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3107 { 3108 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3109 priv->rss.enable = false; 3110 return; 3111 } 3112 3113 if (priv->dev->features & NETIF_F_RXHASH) 3114 priv->rss.enable = true; 3115 else 3116 priv->rss.enable = false; 3117 3118 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3119 priv->plat->rx_queues_to_use); 3120 } 3121 3122 /** 3123 * stmmac_mtl_configuration - Configure MTL 3124 * @priv: driver private structure 3125 * Description: It is used for configurring MTL 3126 */ 3127 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3128 { 3129 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3130 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3131 3132 if (tx_queues_count > 1) 3133 stmmac_set_tx_queue_weight(priv); 3134 3135 /* Configure MTL RX algorithms */ 3136 if (rx_queues_count > 1) 3137 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3138 priv->plat->rx_sched_algorithm); 3139 3140 /* Configure MTL TX algorithms */ 3141 if (tx_queues_count > 1) 3142 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3143 priv->plat->tx_sched_algorithm); 3144 3145 /* Configure CBS in AVB TX queues */ 3146 if (tx_queues_count > 1) 3147 stmmac_configure_cbs(priv); 3148 3149 /* Map RX MTL to DMA channels */ 3150 stmmac_rx_queue_dma_chan_map(priv); 3151 3152 /* Enable MAC RX Queues */ 3153 stmmac_mac_enable_rx_queues(priv); 3154 3155 /* Set RX priorities */ 3156 if (rx_queues_count > 1) 3157 stmmac_mac_config_rx_queues_prio(priv); 3158 3159 /* Set TX priorities */ 3160 if (tx_queues_count > 1) 3161 stmmac_mac_config_tx_queues_prio(priv); 3162 3163 /* Set RX routing */ 3164 if (rx_queues_count > 1) 3165 stmmac_mac_config_rx_queues_routing(priv); 3166 3167 /* Receive Side Scaling */ 3168 if (rx_queues_count > 1) 3169 stmmac_mac_config_rss(priv); 3170 } 3171 3172 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3173 { 3174 if (priv->dma_cap.asp) { 3175 netdev_info(priv->dev, "Enabling Safety Features\n"); 3176 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3177 priv->plat->safety_feat_cfg); 3178 } else { 3179 netdev_info(priv->dev, "No Safety Features support found\n"); 3180 } 3181 } 3182 3183 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3184 { 3185 char *name; 3186 3187 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3188 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3189 3190 name = priv->wq_name; 3191 sprintf(name, "%s-fpe", priv->dev->name); 3192 3193 priv->fpe_wq = create_singlethread_workqueue(name); 3194 if (!priv->fpe_wq) { 3195 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3196 3197 return -ENOMEM; 3198 } 3199 netdev_info(priv->dev, "FPE workqueue start"); 3200 3201 return 0; 3202 } 3203 3204 /** 3205 * stmmac_hw_setup - setup mac in a usable state. 3206 * @dev : pointer to the device structure. 3207 * @init_ptp: initialize PTP if set 3208 * Description: 3209 * this is the main function to setup the HW in a usable state because the 3210 * dma engine is reset, the core registers are configured (e.g. AXI, 3211 * Checksum features, timers). The DMA is ready to start receiving and 3212 * transmitting. 3213 * Return value: 3214 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3215 * file on failure. 3216 */ 3217 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 3218 { 3219 struct stmmac_priv *priv = netdev_priv(dev); 3220 u32 rx_cnt = priv->plat->rx_queues_to_use; 3221 u32 tx_cnt = priv->plat->tx_queues_to_use; 3222 bool sph_en; 3223 u32 chan; 3224 int ret; 3225 3226 /* DMA initialization and SW reset */ 3227 ret = stmmac_init_dma_engine(priv); 3228 if (ret < 0) { 3229 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3230 __func__); 3231 return ret; 3232 } 3233 3234 /* Copy the MAC addr into the HW */ 3235 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3236 3237 /* PS and related bits will be programmed according to the speed */ 3238 if (priv->hw->pcs) { 3239 int speed = priv->plat->mac_port_sel_speed; 3240 3241 if ((speed == SPEED_10) || (speed == SPEED_100) || 3242 (speed == SPEED_1000)) { 3243 priv->hw->ps = speed; 3244 } else { 3245 dev_warn(priv->device, "invalid port speed\n"); 3246 priv->hw->ps = 0; 3247 } 3248 } 3249 3250 /* Initialize the MAC Core */ 3251 stmmac_core_init(priv, priv->hw, dev); 3252 3253 /* Initialize MTL*/ 3254 stmmac_mtl_configuration(priv); 3255 3256 /* Initialize Safety Features */ 3257 stmmac_safety_feat_configuration(priv); 3258 3259 ret = stmmac_rx_ipc(priv, priv->hw); 3260 if (!ret) { 3261 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3262 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3263 priv->hw->rx_csum = 0; 3264 } 3265 3266 /* Enable the MAC Rx/Tx */ 3267 stmmac_mac_set(priv, priv->ioaddr, true); 3268 3269 /* Set the HW DMA mode and the COE */ 3270 stmmac_dma_operation_mode(priv); 3271 3272 stmmac_mmc_setup(priv); 3273 3274 if (init_ptp) { 3275 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3276 if (ret < 0) 3277 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 3278 3279 ret = stmmac_init_ptp(priv); 3280 if (ret == -EOPNOTSUPP) 3281 netdev_warn(priv->dev, "PTP not supported by HW\n"); 3282 else if (ret) 3283 netdev_warn(priv->dev, "PTP init failed\n"); 3284 } 3285 3286 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3287 3288 /* Convert the timer from msec to usec */ 3289 if (!priv->tx_lpi_timer) 3290 priv->tx_lpi_timer = eee_timer * 1000; 3291 3292 if (priv->use_riwt) { 3293 u32 queue; 3294 3295 for (queue = 0; queue < rx_cnt; queue++) { 3296 if (!priv->rx_riwt[queue]) 3297 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3298 3299 stmmac_rx_watchdog(priv, priv->ioaddr, 3300 priv->rx_riwt[queue], queue); 3301 } 3302 } 3303 3304 if (priv->hw->pcs) 3305 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3306 3307 /* set TX and RX rings length */ 3308 stmmac_set_rings_length(priv); 3309 3310 /* Enable TSO */ 3311 if (priv->tso) { 3312 for (chan = 0; chan < tx_cnt; chan++) { 3313 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3314 3315 /* TSO and TBS cannot co-exist */ 3316 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3317 continue; 3318 3319 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3320 } 3321 } 3322 3323 /* Enable Split Header */ 3324 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3325 for (chan = 0; chan < rx_cnt; chan++) 3326 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3327 3328 3329 /* VLAN Tag Insertion */ 3330 if (priv->dma_cap.vlins) 3331 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3332 3333 /* TBS */ 3334 for (chan = 0; chan < tx_cnt; chan++) { 3335 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3336 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3337 3338 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3339 } 3340 3341 /* Configure real RX and TX queues */ 3342 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3343 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3344 3345 /* Start the ball rolling... */ 3346 stmmac_start_all_dma(priv); 3347 3348 if (priv->dma_cap.fpesel) { 3349 stmmac_fpe_start_wq(priv); 3350 3351 if (priv->plat->fpe_cfg->enable) 3352 stmmac_fpe_handshake(priv, true); 3353 } 3354 3355 return 0; 3356 } 3357 3358 static void stmmac_hw_teardown(struct net_device *dev) 3359 { 3360 struct stmmac_priv *priv = netdev_priv(dev); 3361 3362 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3363 } 3364 3365 static void stmmac_free_irq(struct net_device *dev, 3366 enum request_irq_err irq_err, int irq_idx) 3367 { 3368 struct stmmac_priv *priv = netdev_priv(dev); 3369 int j; 3370 3371 switch (irq_err) { 3372 case REQ_IRQ_ERR_ALL: 3373 irq_idx = priv->plat->tx_queues_to_use; 3374 fallthrough; 3375 case REQ_IRQ_ERR_TX: 3376 for (j = irq_idx - 1; j >= 0; j--) { 3377 if (priv->tx_irq[j] > 0) { 3378 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3379 free_irq(priv->tx_irq[j], &priv->tx_queue[j]); 3380 } 3381 } 3382 irq_idx = priv->plat->rx_queues_to_use; 3383 fallthrough; 3384 case REQ_IRQ_ERR_RX: 3385 for (j = irq_idx - 1; j >= 0; j--) { 3386 if (priv->rx_irq[j] > 0) { 3387 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3388 free_irq(priv->rx_irq[j], &priv->rx_queue[j]); 3389 } 3390 } 3391 3392 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3393 free_irq(priv->sfty_ue_irq, dev); 3394 fallthrough; 3395 case REQ_IRQ_ERR_SFTY_UE: 3396 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3397 free_irq(priv->sfty_ce_irq, dev); 3398 fallthrough; 3399 case REQ_IRQ_ERR_SFTY_CE: 3400 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3401 free_irq(priv->lpi_irq, dev); 3402 fallthrough; 3403 case REQ_IRQ_ERR_LPI: 3404 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3405 free_irq(priv->wol_irq, dev); 3406 fallthrough; 3407 case REQ_IRQ_ERR_WOL: 3408 free_irq(dev->irq, dev); 3409 fallthrough; 3410 case REQ_IRQ_ERR_MAC: 3411 case REQ_IRQ_ERR_NO: 3412 /* If MAC IRQ request error, no more IRQ to free */ 3413 break; 3414 } 3415 } 3416 3417 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3418 { 3419 struct stmmac_priv *priv = netdev_priv(dev); 3420 enum request_irq_err irq_err; 3421 cpumask_t cpu_mask; 3422 int irq_idx = 0; 3423 char *int_name; 3424 int ret; 3425 int i; 3426 3427 /* For common interrupt */ 3428 int_name = priv->int_name_mac; 3429 sprintf(int_name, "%s:%s", dev->name, "mac"); 3430 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3431 0, int_name, dev); 3432 if (unlikely(ret < 0)) { 3433 netdev_err(priv->dev, 3434 "%s: alloc mac MSI %d (error: %d)\n", 3435 __func__, dev->irq, ret); 3436 irq_err = REQ_IRQ_ERR_MAC; 3437 goto irq_error; 3438 } 3439 3440 /* Request the Wake IRQ in case of another line 3441 * is used for WoL 3442 */ 3443 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3444 int_name = priv->int_name_wol; 3445 sprintf(int_name, "%s:%s", dev->name, "wol"); 3446 ret = request_irq(priv->wol_irq, 3447 stmmac_mac_interrupt, 3448 0, int_name, dev); 3449 if (unlikely(ret < 0)) { 3450 netdev_err(priv->dev, 3451 "%s: alloc wol MSI %d (error: %d)\n", 3452 __func__, priv->wol_irq, ret); 3453 irq_err = REQ_IRQ_ERR_WOL; 3454 goto irq_error; 3455 } 3456 } 3457 3458 /* Request the LPI IRQ in case of another line 3459 * is used for LPI 3460 */ 3461 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3462 int_name = priv->int_name_lpi; 3463 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3464 ret = request_irq(priv->lpi_irq, 3465 stmmac_mac_interrupt, 3466 0, int_name, dev); 3467 if (unlikely(ret < 0)) { 3468 netdev_err(priv->dev, 3469 "%s: alloc lpi MSI %d (error: %d)\n", 3470 __func__, priv->lpi_irq, ret); 3471 irq_err = REQ_IRQ_ERR_LPI; 3472 goto irq_error; 3473 } 3474 } 3475 3476 /* Request the Safety Feature Correctible Error line in 3477 * case of another line is used 3478 */ 3479 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3480 int_name = priv->int_name_sfty_ce; 3481 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3482 ret = request_irq(priv->sfty_ce_irq, 3483 stmmac_safety_interrupt, 3484 0, int_name, dev); 3485 if (unlikely(ret < 0)) { 3486 netdev_err(priv->dev, 3487 "%s: alloc sfty ce MSI %d (error: %d)\n", 3488 __func__, priv->sfty_ce_irq, ret); 3489 irq_err = REQ_IRQ_ERR_SFTY_CE; 3490 goto irq_error; 3491 } 3492 } 3493 3494 /* Request the Safety Feature Uncorrectible Error line in 3495 * case of another line is used 3496 */ 3497 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3498 int_name = priv->int_name_sfty_ue; 3499 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3500 ret = request_irq(priv->sfty_ue_irq, 3501 stmmac_safety_interrupt, 3502 0, int_name, dev); 3503 if (unlikely(ret < 0)) { 3504 netdev_err(priv->dev, 3505 "%s: alloc sfty ue MSI %d (error: %d)\n", 3506 __func__, priv->sfty_ue_irq, ret); 3507 irq_err = REQ_IRQ_ERR_SFTY_UE; 3508 goto irq_error; 3509 } 3510 } 3511 3512 /* Request Rx MSI irq */ 3513 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3514 if (i >= MTL_MAX_RX_QUEUES) 3515 break; 3516 if (priv->rx_irq[i] == 0) 3517 continue; 3518 3519 int_name = priv->int_name_rx_irq[i]; 3520 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3521 ret = request_irq(priv->rx_irq[i], 3522 stmmac_msi_intr_rx, 3523 0, int_name, &priv->rx_queue[i]); 3524 if (unlikely(ret < 0)) { 3525 netdev_err(priv->dev, 3526 "%s: alloc rx-%d MSI %d (error: %d)\n", 3527 __func__, i, priv->rx_irq[i], ret); 3528 irq_err = REQ_IRQ_ERR_RX; 3529 irq_idx = i; 3530 goto irq_error; 3531 } 3532 cpumask_clear(&cpu_mask); 3533 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3534 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3535 } 3536 3537 /* Request Tx MSI irq */ 3538 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3539 if (i >= MTL_MAX_TX_QUEUES) 3540 break; 3541 if (priv->tx_irq[i] == 0) 3542 continue; 3543 3544 int_name = priv->int_name_tx_irq[i]; 3545 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3546 ret = request_irq(priv->tx_irq[i], 3547 stmmac_msi_intr_tx, 3548 0, int_name, &priv->tx_queue[i]); 3549 if (unlikely(ret < 0)) { 3550 netdev_err(priv->dev, 3551 "%s: alloc tx-%d MSI %d (error: %d)\n", 3552 __func__, i, priv->tx_irq[i], ret); 3553 irq_err = REQ_IRQ_ERR_TX; 3554 irq_idx = i; 3555 goto irq_error; 3556 } 3557 cpumask_clear(&cpu_mask); 3558 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3559 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3560 } 3561 3562 return 0; 3563 3564 irq_error: 3565 stmmac_free_irq(dev, irq_err, irq_idx); 3566 return ret; 3567 } 3568 3569 static int stmmac_request_irq_single(struct net_device *dev) 3570 { 3571 struct stmmac_priv *priv = netdev_priv(dev); 3572 enum request_irq_err irq_err; 3573 int ret; 3574 3575 ret = request_irq(dev->irq, stmmac_interrupt, 3576 IRQF_SHARED, dev->name, dev); 3577 if (unlikely(ret < 0)) { 3578 netdev_err(priv->dev, 3579 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3580 __func__, dev->irq, ret); 3581 irq_err = REQ_IRQ_ERR_MAC; 3582 goto irq_error; 3583 } 3584 3585 /* Request the Wake IRQ in case of another line 3586 * is used for WoL 3587 */ 3588 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3589 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3590 IRQF_SHARED, dev->name, dev); 3591 if (unlikely(ret < 0)) { 3592 netdev_err(priv->dev, 3593 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3594 __func__, priv->wol_irq, ret); 3595 irq_err = REQ_IRQ_ERR_WOL; 3596 goto irq_error; 3597 } 3598 } 3599 3600 /* Request the IRQ lines */ 3601 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3602 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3603 IRQF_SHARED, dev->name, dev); 3604 if (unlikely(ret < 0)) { 3605 netdev_err(priv->dev, 3606 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3607 __func__, priv->lpi_irq, ret); 3608 irq_err = REQ_IRQ_ERR_LPI; 3609 goto irq_error; 3610 } 3611 } 3612 3613 return 0; 3614 3615 irq_error: 3616 stmmac_free_irq(dev, irq_err, 0); 3617 return ret; 3618 } 3619 3620 static int stmmac_request_irq(struct net_device *dev) 3621 { 3622 struct stmmac_priv *priv = netdev_priv(dev); 3623 int ret; 3624 3625 /* Request the IRQ lines */ 3626 if (priv->plat->multi_msi_en) 3627 ret = stmmac_request_irq_multi_msi(dev); 3628 else 3629 ret = stmmac_request_irq_single(dev); 3630 3631 return ret; 3632 } 3633 3634 /** 3635 * stmmac_open - open entry point of the driver 3636 * @dev : pointer to the device structure. 3637 * Description: 3638 * This function is the open entry point of the driver. 3639 * Return value: 3640 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3641 * file on failure. 3642 */ 3643 int stmmac_open(struct net_device *dev) 3644 { 3645 struct stmmac_priv *priv = netdev_priv(dev); 3646 int mode = priv->plat->phy_interface; 3647 int bfsize = 0; 3648 u32 chan; 3649 int ret; 3650 3651 ret = pm_runtime_get_sync(priv->device); 3652 if (ret < 0) { 3653 pm_runtime_put_noidle(priv->device); 3654 return ret; 3655 } 3656 3657 if (priv->hw->pcs != STMMAC_PCS_TBI && 3658 priv->hw->pcs != STMMAC_PCS_RTBI && 3659 (!priv->hw->xpcs || 3660 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3661 ret = stmmac_init_phy(dev); 3662 if (ret) { 3663 netdev_err(priv->dev, 3664 "%s: Cannot attach to PHY (error: %d)\n", 3665 __func__, ret); 3666 goto init_phy_error; 3667 } 3668 } 3669 3670 /* Extra statistics */ 3671 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3672 priv->xstats.threshold = tc; 3673 3674 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 3675 if (bfsize < 0) 3676 bfsize = 0; 3677 3678 if (bfsize < BUF_SIZE_16KiB) 3679 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 3680 3681 priv->dma_buf_sz = bfsize; 3682 buf_sz = bfsize; 3683 3684 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3685 3686 if (!priv->dma_tx_size) 3687 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3688 if (!priv->dma_rx_size) 3689 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3690 3691 /* Earlier check for TBS */ 3692 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3693 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3694 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3695 3696 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3697 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3698 } 3699 3700 ret = alloc_dma_desc_resources(priv); 3701 if (ret < 0) { 3702 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3703 __func__); 3704 goto dma_desc_error; 3705 } 3706 3707 ret = init_dma_desc_rings(dev, GFP_KERNEL); 3708 if (ret < 0) { 3709 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3710 __func__); 3711 goto init_error; 3712 } 3713 3714 ret = stmmac_hw_setup(dev, true); 3715 if (ret < 0) { 3716 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3717 goto init_error; 3718 } 3719 3720 stmmac_init_coalesce(priv); 3721 3722 phylink_start(priv->phylink); 3723 /* We may have called phylink_speed_down before */ 3724 phylink_speed_up(priv->phylink); 3725 3726 ret = stmmac_request_irq(dev); 3727 if (ret) 3728 goto irq_error; 3729 3730 stmmac_enable_all_queues(priv); 3731 netif_tx_start_all_queues(priv->dev); 3732 3733 return 0; 3734 3735 irq_error: 3736 phylink_stop(priv->phylink); 3737 3738 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3739 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3740 3741 stmmac_hw_teardown(dev); 3742 init_error: 3743 free_dma_desc_resources(priv); 3744 dma_desc_error: 3745 phylink_disconnect_phy(priv->phylink); 3746 init_phy_error: 3747 pm_runtime_put(priv->device); 3748 return ret; 3749 } 3750 3751 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3752 { 3753 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3754 3755 if (priv->fpe_wq) 3756 destroy_workqueue(priv->fpe_wq); 3757 3758 netdev_info(priv->dev, "FPE workqueue stop"); 3759 } 3760 3761 /** 3762 * stmmac_release - close entry point of the driver 3763 * @dev : device pointer. 3764 * Description: 3765 * This is the stop entry point of the driver. 3766 */ 3767 int stmmac_release(struct net_device *dev) 3768 { 3769 struct stmmac_priv *priv = netdev_priv(dev); 3770 u32 chan; 3771 3772 if (device_may_wakeup(priv->device)) 3773 phylink_speed_down(priv->phylink, false); 3774 /* Stop and disconnect the PHY */ 3775 phylink_stop(priv->phylink); 3776 phylink_disconnect_phy(priv->phylink); 3777 3778 stmmac_disable_all_queues(priv); 3779 3780 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3781 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3782 3783 /* Free the IRQ lines */ 3784 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3785 3786 if (priv->eee_enabled) { 3787 priv->tx_path_in_lpi_mode = false; 3788 del_timer_sync(&priv->eee_ctrl_timer); 3789 } 3790 3791 /* Stop TX/RX DMA and clear the descriptors */ 3792 stmmac_stop_all_dma(priv); 3793 3794 /* Release and free the Rx/Tx resources */ 3795 free_dma_desc_resources(priv); 3796 3797 /* Disable the MAC Rx/Tx */ 3798 stmmac_mac_set(priv, priv->ioaddr, false); 3799 3800 netif_carrier_off(dev); 3801 3802 stmmac_release_ptp(priv); 3803 3804 pm_runtime_put(priv->device); 3805 3806 if (priv->dma_cap.fpesel) 3807 stmmac_fpe_stop_wq(priv); 3808 3809 return 0; 3810 } 3811 3812 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3813 struct stmmac_tx_queue *tx_q) 3814 { 3815 u16 tag = 0x0, inner_tag = 0x0; 3816 u32 inner_type = 0x0; 3817 struct dma_desc *p; 3818 3819 if (!priv->dma_cap.vlins) 3820 return false; 3821 if (!skb_vlan_tag_present(skb)) 3822 return false; 3823 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3824 inner_tag = skb_vlan_tag_get(skb); 3825 inner_type = STMMAC_VLAN_INSERT; 3826 } 3827 3828 tag = skb_vlan_tag_get(skb); 3829 3830 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3831 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3832 else 3833 p = &tx_q->dma_tx[tx_q->cur_tx]; 3834 3835 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3836 return false; 3837 3838 stmmac_set_tx_owner(priv, p); 3839 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3840 return true; 3841 } 3842 3843 /** 3844 * stmmac_tso_allocator - close entry point of the driver 3845 * @priv: driver private structure 3846 * @des: buffer start address 3847 * @total_len: total length to fill in descriptors 3848 * @last_segment: condition for the last descriptor 3849 * @queue: TX queue index 3850 * Description: 3851 * This function fills descriptor and request new descriptors according to 3852 * buffer length to fill 3853 */ 3854 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3855 int total_len, bool last_segment, u32 queue) 3856 { 3857 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3858 struct dma_desc *desc; 3859 u32 buff_size; 3860 int tmp_len; 3861 3862 tmp_len = total_len; 3863 3864 while (tmp_len > 0) { 3865 dma_addr_t curr_addr; 3866 3867 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3868 priv->dma_tx_size); 3869 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3870 3871 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3872 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3873 else 3874 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3875 3876 curr_addr = des + (total_len - tmp_len); 3877 if (priv->dma_cap.addr64 <= 32) 3878 desc->des0 = cpu_to_le32(curr_addr); 3879 else 3880 stmmac_set_desc_addr(priv, desc, curr_addr); 3881 3882 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3883 TSO_MAX_BUFF_SIZE : tmp_len; 3884 3885 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3886 0, 1, 3887 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3888 0, 0); 3889 3890 tmp_len -= TSO_MAX_BUFF_SIZE; 3891 } 3892 } 3893 3894 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 3895 { 3896 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3897 int desc_size; 3898 3899 if (likely(priv->extend_desc)) 3900 desc_size = sizeof(struct dma_extended_desc); 3901 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3902 desc_size = sizeof(struct dma_edesc); 3903 else 3904 desc_size = sizeof(struct dma_desc); 3905 3906 /* The own bit must be the latest setting done when prepare the 3907 * descriptor and then barrier is needed to make sure that 3908 * all is coherent before granting the DMA engine. 3909 */ 3910 wmb(); 3911 3912 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3913 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3914 } 3915 3916 /** 3917 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3918 * @skb : the socket buffer 3919 * @dev : device pointer 3920 * Description: this is the transmit function that is called on TSO frames 3921 * (support available on GMAC4 and newer chips). 3922 * Diagram below show the ring programming in case of TSO frames: 3923 * 3924 * First Descriptor 3925 * -------- 3926 * | DES0 |---> buffer1 = L2/L3/L4 header 3927 * | DES1 |---> TCP Payload (can continue on next descr...) 3928 * | DES2 |---> buffer 1 and 2 len 3929 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3930 * -------- 3931 * | 3932 * ... 3933 * | 3934 * -------- 3935 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3936 * | DES1 | --| 3937 * | DES2 | --> buffer 1 and 2 len 3938 * | DES3 | 3939 * -------- 3940 * 3941 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3942 */ 3943 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3944 { 3945 struct dma_desc *desc, *first, *mss_desc = NULL; 3946 struct stmmac_priv *priv = netdev_priv(dev); 3947 int nfrags = skb_shinfo(skb)->nr_frags; 3948 u32 queue = skb_get_queue_mapping(skb); 3949 unsigned int first_entry, tx_packets; 3950 int tmp_pay_len = 0, first_tx; 3951 struct stmmac_tx_queue *tx_q; 3952 bool has_vlan, set_ic; 3953 u8 proto_hdr_len, hdr; 3954 u32 pay_len, mss; 3955 dma_addr_t des; 3956 int i; 3957 3958 tx_q = &priv->tx_queue[queue]; 3959 first_tx = tx_q->cur_tx; 3960 3961 /* Compute header lengths */ 3962 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3963 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3964 hdr = sizeof(struct udphdr); 3965 } else { 3966 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3967 hdr = tcp_hdrlen(skb); 3968 } 3969 3970 /* Desc availability based on threshold should be enough safe */ 3971 if (unlikely(stmmac_tx_avail(priv, queue) < 3972 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3973 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3974 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3975 queue)); 3976 /* This is a hard error, log it. */ 3977 netdev_err(priv->dev, 3978 "%s: Tx Ring full when queue awake\n", 3979 __func__); 3980 } 3981 return NETDEV_TX_BUSY; 3982 } 3983 3984 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3985 3986 mss = skb_shinfo(skb)->gso_size; 3987 3988 /* set new MSS value if needed */ 3989 if (mss != tx_q->mss) { 3990 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3991 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3992 else 3993 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3994 3995 stmmac_set_mss(priv, mss_desc, mss); 3996 tx_q->mss = mss; 3997 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3998 priv->dma_tx_size); 3999 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4000 } 4001 4002 if (netif_msg_tx_queued(priv)) { 4003 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4004 __func__, hdr, proto_hdr_len, pay_len, mss); 4005 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4006 skb->data_len); 4007 } 4008 4009 /* Check if VLAN can be inserted by HW */ 4010 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4011 4012 first_entry = tx_q->cur_tx; 4013 WARN_ON(tx_q->tx_skbuff[first_entry]); 4014 4015 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4016 desc = &tx_q->dma_entx[first_entry].basic; 4017 else 4018 desc = &tx_q->dma_tx[first_entry]; 4019 first = desc; 4020 4021 if (has_vlan) 4022 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4023 4024 /* first descriptor: fill Headers on Buf1 */ 4025 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4026 DMA_TO_DEVICE); 4027 if (dma_mapping_error(priv->device, des)) 4028 goto dma_map_err; 4029 4030 tx_q->tx_skbuff_dma[first_entry].buf = des; 4031 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4032 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4033 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4034 4035 if (priv->dma_cap.addr64 <= 32) { 4036 first->des0 = cpu_to_le32(des); 4037 4038 /* Fill start of payload in buff2 of first descriptor */ 4039 if (pay_len) 4040 first->des1 = cpu_to_le32(des + proto_hdr_len); 4041 4042 /* If needed take extra descriptors to fill the remaining payload */ 4043 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4044 } else { 4045 stmmac_set_desc_addr(priv, first, des); 4046 tmp_pay_len = pay_len; 4047 des += proto_hdr_len; 4048 pay_len = 0; 4049 } 4050 4051 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4052 4053 /* Prepare fragments */ 4054 for (i = 0; i < nfrags; i++) { 4055 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4056 4057 des = skb_frag_dma_map(priv->device, frag, 0, 4058 skb_frag_size(frag), 4059 DMA_TO_DEVICE); 4060 if (dma_mapping_error(priv->device, des)) 4061 goto dma_map_err; 4062 4063 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4064 (i == nfrags - 1), queue); 4065 4066 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4067 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4068 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4069 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4070 } 4071 4072 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4073 4074 /* Only the last descriptor gets to point to the skb. */ 4075 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4076 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4077 4078 /* Manage tx mitigation */ 4079 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4080 tx_q->tx_count_frames += tx_packets; 4081 4082 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4083 set_ic = true; 4084 else if (!priv->tx_coal_frames[queue]) 4085 set_ic = false; 4086 else if (tx_packets > priv->tx_coal_frames[queue]) 4087 set_ic = true; 4088 else if ((tx_q->tx_count_frames % 4089 priv->tx_coal_frames[queue]) < tx_packets) 4090 set_ic = true; 4091 else 4092 set_ic = false; 4093 4094 if (set_ic) { 4095 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4096 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4097 else 4098 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4099 4100 tx_q->tx_count_frames = 0; 4101 stmmac_set_tx_ic(priv, desc); 4102 priv->xstats.tx_set_ic_bit++; 4103 } 4104 4105 /* We've used all descriptors we need for this skb, however, 4106 * advance cur_tx so that it references a fresh descriptor. 4107 * ndo_start_xmit will fill this descriptor the next time it's 4108 * called and stmmac_tx_clean may clean up to this descriptor. 4109 */ 4110 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 4111 4112 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4113 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4114 __func__); 4115 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4116 } 4117 4118 dev->stats.tx_bytes += skb->len; 4119 priv->xstats.tx_tso_frames++; 4120 priv->xstats.tx_tso_nfrags += nfrags; 4121 4122 if (priv->sarc_type) 4123 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4124 4125 skb_tx_timestamp(skb); 4126 4127 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4128 priv->hwts_tx_en)) { 4129 /* declare that device is doing timestamping */ 4130 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4131 stmmac_enable_tx_timestamp(priv, first); 4132 } 4133 4134 /* Complete the first descriptor before granting the DMA */ 4135 stmmac_prepare_tso_tx_desc(priv, first, 1, 4136 proto_hdr_len, 4137 pay_len, 4138 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4139 hdr / 4, (skb->len - proto_hdr_len)); 4140 4141 /* If context desc is used to change MSS */ 4142 if (mss_desc) { 4143 /* Make sure that first descriptor has been completely 4144 * written, including its own bit. This is because MSS is 4145 * actually before first descriptor, so we need to make 4146 * sure that MSS's own bit is the last thing written. 4147 */ 4148 dma_wmb(); 4149 stmmac_set_tx_owner(priv, mss_desc); 4150 } 4151 4152 if (netif_msg_pktdata(priv)) { 4153 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4154 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4155 tx_q->cur_tx, first, nfrags); 4156 pr_info(">>> frame to be transmitted: "); 4157 print_pkt(skb->data, skb_headlen(skb)); 4158 } 4159 4160 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4161 4162 stmmac_flush_tx_descriptors(priv, queue); 4163 stmmac_tx_timer_arm(priv, queue); 4164 4165 return NETDEV_TX_OK; 4166 4167 dma_map_err: 4168 dev_err(priv->device, "Tx dma map failed\n"); 4169 dev_kfree_skb(skb); 4170 priv->dev->stats.tx_dropped++; 4171 return NETDEV_TX_OK; 4172 } 4173 4174 /** 4175 * stmmac_xmit - Tx entry point of the driver 4176 * @skb : the socket buffer 4177 * @dev : device pointer 4178 * Description : this is the tx entry point of the driver. 4179 * It programs the chain or the ring and supports oversized frames 4180 * and SG feature. 4181 */ 4182 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4183 { 4184 unsigned int first_entry, tx_packets, enh_desc; 4185 struct stmmac_priv *priv = netdev_priv(dev); 4186 unsigned int nopaged_len = skb_headlen(skb); 4187 int i, csum_insertion = 0, is_jumbo = 0; 4188 u32 queue = skb_get_queue_mapping(skb); 4189 int nfrags = skb_shinfo(skb)->nr_frags; 4190 int gso = skb_shinfo(skb)->gso_type; 4191 struct dma_edesc *tbs_desc = NULL; 4192 struct dma_desc *desc, *first; 4193 struct stmmac_tx_queue *tx_q; 4194 bool has_vlan, set_ic; 4195 int entry, first_tx; 4196 dma_addr_t des; 4197 4198 tx_q = &priv->tx_queue[queue]; 4199 first_tx = tx_q->cur_tx; 4200 4201 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4202 stmmac_disable_eee_mode(priv); 4203 4204 /* Manage oversized TCP frames for GMAC4 device */ 4205 if (skb_is_gso(skb) && priv->tso) { 4206 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4207 return stmmac_tso_xmit(skb, dev); 4208 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4209 return stmmac_tso_xmit(skb, dev); 4210 } 4211 4212 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4213 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4214 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4215 queue)); 4216 /* This is a hard error, log it. */ 4217 netdev_err(priv->dev, 4218 "%s: Tx Ring full when queue awake\n", 4219 __func__); 4220 } 4221 return NETDEV_TX_BUSY; 4222 } 4223 4224 /* Check if VLAN can be inserted by HW */ 4225 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4226 4227 entry = tx_q->cur_tx; 4228 first_entry = entry; 4229 WARN_ON(tx_q->tx_skbuff[first_entry]); 4230 4231 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4232 4233 if (likely(priv->extend_desc)) 4234 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4235 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4236 desc = &tx_q->dma_entx[entry].basic; 4237 else 4238 desc = tx_q->dma_tx + entry; 4239 4240 first = desc; 4241 4242 if (has_vlan) 4243 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4244 4245 enh_desc = priv->plat->enh_desc; 4246 /* To program the descriptors according to the size of the frame */ 4247 if (enh_desc) 4248 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4249 4250 if (unlikely(is_jumbo)) { 4251 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4252 if (unlikely(entry < 0) && (entry != -EINVAL)) 4253 goto dma_map_err; 4254 } 4255 4256 for (i = 0; i < nfrags; i++) { 4257 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4258 int len = skb_frag_size(frag); 4259 bool last_segment = (i == (nfrags - 1)); 4260 4261 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4262 WARN_ON(tx_q->tx_skbuff[entry]); 4263 4264 if (likely(priv->extend_desc)) 4265 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4266 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4267 desc = &tx_q->dma_entx[entry].basic; 4268 else 4269 desc = tx_q->dma_tx + entry; 4270 4271 des = skb_frag_dma_map(priv->device, frag, 0, len, 4272 DMA_TO_DEVICE); 4273 if (dma_mapping_error(priv->device, des)) 4274 goto dma_map_err; /* should reuse desc w/o issues */ 4275 4276 tx_q->tx_skbuff_dma[entry].buf = des; 4277 4278 stmmac_set_desc_addr(priv, desc, des); 4279 4280 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4281 tx_q->tx_skbuff_dma[entry].len = len; 4282 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4283 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4284 4285 /* Prepare the descriptor and set the own bit too */ 4286 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4287 priv->mode, 1, last_segment, skb->len); 4288 } 4289 4290 /* Only the last descriptor gets to point to the skb. */ 4291 tx_q->tx_skbuff[entry] = skb; 4292 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4293 4294 /* According to the coalesce parameter the IC bit for the latest 4295 * segment is reset and the timer re-started to clean the tx status. 4296 * This approach takes care about the fragments: desc is the first 4297 * element in case of no SG. 4298 */ 4299 tx_packets = (entry + 1) - first_tx; 4300 tx_q->tx_count_frames += tx_packets; 4301 4302 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4303 set_ic = true; 4304 else if (!priv->tx_coal_frames[queue]) 4305 set_ic = false; 4306 else if (tx_packets > priv->tx_coal_frames[queue]) 4307 set_ic = true; 4308 else if ((tx_q->tx_count_frames % 4309 priv->tx_coal_frames[queue]) < tx_packets) 4310 set_ic = true; 4311 else 4312 set_ic = false; 4313 4314 if (set_ic) { 4315 if (likely(priv->extend_desc)) 4316 desc = &tx_q->dma_etx[entry].basic; 4317 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4318 desc = &tx_q->dma_entx[entry].basic; 4319 else 4320 desc = &tx_q->dma_tx[entry]; 4321 4322 tx_q->tx_count_frames = 0; 4323 stmmac_set_tx_ic(priv, desc); 4324 priv->xstats.tx_set_ic_bit++; 4325 } 4326 4327 /* We've used all descriptors we need for this skb, however, 4328 * advance cur_tx so that it references a fresh descriptor. 4329 * ndo_start_xmit will fill this descriptor the next time it's 4330 * called and stmmac_tx_clean may clean up to this descriptor. 4331 */ 4332 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4333 tx_q->cur_tx = entry; 4334 4335 if (netif_msg_pktdata(priv)) { 4336 netdev_dbg(priv->dev, 4337 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4338 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4339 entry, first, nfrags); 4340 4341 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4342 print_pkt(skb->data, skb->len); 4343 } 4344 4345 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4346 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4347 __func__); 4348 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4349 } 4350 4351 dev->stats.tx_bytes += skb->len; 4352 4353 if (priv->sarc_type) 4354 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4355 4356 skb_tx_timestamp(skb); 4357 4358 /* Ready to fill the first descriptor and set the OWN bit w/o any 4359 * problems because all the descriptors are actually ready to be 4360 * passed to the DMA engine. 4361 */ 4362 if (likely(!is_jumbo)) { 4363 bool last_segment = (nfrags == 0); 4364 4365 des = dma_map_single(priv->device, skb->data, 4366 nopaged_len, DMA_TO_DEVICE); 4367 if (dma_mapping_error(priv->device, des)) 4368 goto dma_map_err; 4369 4370 tx_q->tx_skbuff_dma[first_entry].buf = des; 4371 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4372 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4373 4374 stmmac_set_desc_addr(priv, first, des); 4375 4376 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4377 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4378 4379 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4380 priv->hwts_tx_en)) { 4381 /* declare that device is doing timestamping */ 4382 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4383 stmmac_enable_tx_timestamp(priv, first); 4384 } 4385 4386 /* Prepare the first descriptor setting the OWN bit too */ 4387 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4388 csum_insertion, priv->mode, 0, last_segment, 4389 skb->len); 4390 } 4391 4392 if (tx_q->tbs & STMMAC_TBS_EN) { 4393 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4394 4395 tbs_desc = &tx_q->dma_entx[first_entry]; 4396 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4397 } 4398 4399 stmmac_set_tx_owner(priv, first); 4400 4401 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4402 4403 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4404 4405 stmmac_flush_tx_descriptors(priv, queue); 4406 stmmac_tx_timer_arm(priv, queue); 4407 4408 return NETDEV_TX_OK; 4409 4410 dma_map_err: 4411 netdev_err(priv->dev, "Tx DMA map failed\n"); 4412 dev_kfree_skb(skb); 4413 priv->dev->stats.tx_dropped++; 4414 return NETDEV_TX_OK; 4415 } 4416 4417 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4418 { 4419 struct vlan_ethhdr *veth; 4420 __be16 vlan_proto; 4421 u16 vlanid; 4422 4423 veth = (struct vlan_ethhdr *)skb->data; 4424 vlan_proto = veth->h_vlan_proto; 4425 4426 if ((vlan_proto == htons(ETH_P_8021Q) && 4427 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4428 (vlan_proto == htons(ETH_P_8021AD) && 4429 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4430 /* pop the vlan tag */ 4431 vlanid = ntohs(veth->h_vlan_TCI); 4432 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4433 skb_pull(skb, VLAN_HLEN); 4434 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4435 } 4436 } 4437 4438 /** 4439 * stmmac_rx_refill - refill used skb preallocated buffers 4440 * @priv: driver private structure 4441 * @queue: RX queue index 4442 * Description : this is to reallocate the skb for the reception process 4443 * that is based on zero-copy. 4444 */ 4445 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4446 { 4447 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4448 int dirty = stmmac_rx_dirty(priv, queue); 4449 unsigned int entry = rx_q->dirty_rx; 4450 4451 while (dirty-- > 0) { 4452 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4453 struct dma_desc *p; 4454 bool use_rx_wd; 4455 4456 if (priv->extend_desc) 4457 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4458 else 4459 p = rx_q->dma_rx + entry; 4460 4461 if (!buf->page) { 4462 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 4463 if (!buf->page) 4464 break; 4465 } 4466 4467 if (priv->sph && !buf->sec_page) { 4468 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 4469 if (!buf->sec_page) 4470 break; 4471 4472 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4473 } 4474 4475 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4476 4477 stmmac_set_desc_addr(priv, p, buf->addr); 4478 if (priv->sph) 4479 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4480 else 4481 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4482 stmmac_refill_desc3(priv, rx_q, p); 4483 4484 rx_q->rx_count_frames++; 4485 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4486 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4487 rx_q->rx_count_frames = 0; 4488 4489 use_rx_wd = !priv->rx_coal_frames[queue]; 4490 use_rx_wd |= rx_q->rx_count_frames > 0; 4491 if (!priv->use_riwt) 4492 use_rx_wd = false; 4493 4494 dma_wmb(); 4495 stmmac_set_rx_owner(priv, p, use_rx_wd); 4496 4497 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4498 } 4499 rx_q->dirty_rx = entry; 4500 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4501 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4502 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4503 } 4504 4505 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4506 struct dma_desc *p, 4507 int status, unsigned int len) 4508 { 4509 unsigned int plen = 0, hlen = 0; 4510 int coe = priv->hw->rx_csum; 4511 4512 /* Not first descriptor, buffer is always zero */ 4513 if (priv->sph && len) 4514 return 0; 4515 4516 /* First descriptor, get split header length */ 4517 stmmac_get_rx_header_len(priv, p, &hlen); 4518 if (priv->sph && hlen) { 4519 priv->xstats.rx_split_hdr_pkt_n++; 4520 return hlen; 4521 } 4522 4523 /* First descriptor, not last descriptor and not split header */ 4524 if (status & rx_not_ls) 4525 return priv->dma_buf_sz; 4526 4527 plen = stmmac_get_rx_frame_len(priv, p, coe); 4528 4529 /* First descriptor and last descriptor and not split header */ 4530 return min_t(unsigned int, priv->dma_buf_sz, plen); 4531 } 4532 4533 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4534 struct dma_desc *p, 4535 int status, unsigned int len) 4536 { 4537 int coe = priv->hw->rx_csum; 4538 unsigned int plen = 0; 4539 4540 /* Not split header, buffer is not available */ 4541 if (!priv->sph) 4542 return 0; 4543 4544 /* Not last descriptor */ 4545 if (status & rx_not_ls) 4546 return priv->dma_buf_sz; 4547 4548 plen = stmmac_get_rx_frame_len(priv, p, coe); 4549 4550 /* Last descriptor */ 4551 return plen - len; 4552 } 4553 4554 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4555 struct xdp_frame *xdpf, bool dma_map) 4556 { 4557 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4558 unsigned int entry = tx_q->cur_tx; 4559 struct dma_desc *tx_desc; 4560 dma_addr_t dma_addr; 4561 bool set_ic; 4562 4563 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4564 return STMMAC_XDP_CONSUMED; 4565 4566 if (likely(priv->extend_desc)) 4567 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4568 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4569 tx_desc = &tx_q->dma_entx[entry].basic; 4570 else 4571 tx_desc = tx_q->dma_tx + entry; 4572 4573 if (dma_map) { 4574 dma_addr = dma_map_single(priv->device, xdpf->data, 4575 xdpf->len, DMA_TO_DEVICE); 4576 if (dma_mapping_error(priv->device, dma_addr)) 4577 return STMMAC_XDP_CONSUMED; 4578 4579 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4580 } else { 4581 struct page *page = virt_to_page(xdpf->data); 4582 4583 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4584 xdpf->headroom; 4585 dma_sync_single_for_device(priv->device, dma_addr, 4586 xdpf->len, DMA_BIDIRECTIONAL); 4587 4588 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4589 } 4590 4591 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4592 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4593 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4594 tx_q->tx_skbuff_dma[entry].last_segment = true; 4595 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4596 4597 tx_q->xdpf[entry] = xdpf; 4598 4599 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4600 4601 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4602 true, priv->mode, true, true, 4603 xdpf->len); 4604 4605 tx_q->tx_count_frames++; 4606 4607 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4608 set_ic = true; 4609 else 4610 set_ic = false; 4611 4612 if (set_ic) { 4613 tx_q->tx_count_frames = 0; 4614 stmmac_set_tx_ic(priv, tx_desc); 4615 priv->xstats.tx_set_ic_bit++; 4616 } 4617 4618 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4619 4620 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4621 tx_q->cur_tx = entry; 4622 4623 return STMMAC_XDP_TX; 4624 } 4625 4626 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4627 int cpu) 4628 { 4629 int index = cpu; 4630 4631 if (unlikely(index < 0)) 4632 index = 0; 4633 4634 while (index >= priv->plat->tx_queues_to_use) 4635 index -= priv->plat->tx_queues_to_use; 4636 4637 return index; 4638 } 4639 4640 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4641 struct xdp_buff *xdp) 4642 { 4643 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4644 int cpu = smp_processor_id(); 4645 struct netdev_queue *nq; 4646 int queue; 4647 int res; 4648 4649 if (unlikely(!xdpf)) 4650 return STMMAC_XDP_CONSUMED; 4651 4652 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4653 nq = netdev_get_tx_queue(priv->dev, queue); 4654 4655 __netif_tx_lock(nq, cpu); 4656 /* Avoids TX time-out as we are sharing with slow path */ 4657 nq->trans_start = jiffies; 4658 4659 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4660 if (res == STMMAC_XDP_TX) 4661 stmmac_flush_tx_descriptors(priv, queue); 4662 4663 __netif_tx_unlock(nq); 4664 4665 return res; 4666 } 4667 4668 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4669 struct bpf_prog *prog, 4670 struct xdp_buff *xdp) 4671 { 4672 u32 act; 4673 int res; 4674 4675 act = bpf_prog_run_xdp(prog, xdp); 4676 switch (act) { 4677 case XDP_PASS: 4678 res = STMMAC_XDP_PASS; 4679 break; 4680 case XDP_TX: 4681 res = stmmac_xdp_xmit_back(priv, xdp); 4682 break; 4683 case XDP_REDIRECT: 4684 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4685 res = STMMAC_XDP_CONSUMED; 4686 else 4687 res = STMMAC_XDP_REDIRECT; 4688 break; 4689 default: 4690 bpf_warn_invalid_xdp_action(act); 4691 fallthrough; 4692 case XDP_ABORTED: 4693 trace_xdp_exception(priv->dev, prog, act); 4694 fallthrough; 4695 case XDP_DROP: 4696 res = STMMAC_XDP_CONSUMED; 4697 break; 4698 } 4699 4700 return res; 4701 } 4702 4703 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4704 struct xdp_buff *xdp) 4705 { 4706 struct bpf_prog *prog; 4707 int res; 4708 4709 prog = READ_ONCE(priv->xdp_prog); 4710 if (!prog) { 4711 res = STMMAC_XDP_PASS; 4712 goto out; 4713 } 4714 4715 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4716 out: 4717 return ERR_PTR(-res); 4718 } 4719 4720 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4721 int xdp_status) 4722 { 4723 int cpu = smp_processor_id(); 4724 int queue; 4725 4726 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4727 4728 if (xdp_status & STMMAC_XDP_TX) 4729 stmmac_tx_timer_arm(priv, queue); 4730 4731 if (xdp_status & STMMAC_XDP_REDIRECT) 4732 xdp_do_flush(); 4733 } 4734 4735 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4736 struct xdp_buff *xdp) 4737 { 4738 unsigned int metasize = xdp->data - xdp->data_meta; 4739 unsigned int datasize = xdp->data_end - xdp->data; 4740 struct sk_buff *skb; 4741 4742 skb = __napi_alloc_skb(&ch->rxtx_napi, 4743 xdp->data_end - xdp->data_hard_start, 4744 GFP_ATOMIC | __GFP_NOWARN); 4745 if (unlikely(!skb)) 4746 return NULL; 4747 4748 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4749 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4750 if (metasize) 4751 skb_metadata_set(skb, metasize); 4752 4753 return skb; 4754 } 4755 4756 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4757 struct dma_desc *p, struct dma_desc *np, 4758 struct xdp_buff *xdp) 4759 { 4760 struct stmmac_channel *ch = &priv->channel[queue]; 4761 unsigned int len = xdp->data_end - xdp->data; 4762 enum pkt_hash_types hash_type; 4763 int coe = priv->hw->rx_csum; 4764 struct sk_buff *skb; 4765 u32 hash; 4766 4767 skb = stmmac_construct_skb_zc(ch, xdp); 4768 if (!skb) { 4769 priv->dev->stats.rx_dropped++; 4770 return; 4771 } 4772 4773 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4774 stmmac_rx_vlan(priv->dev, skb); 4775 skb->protocol = eth_type_trans(skb, priv->dev); 4776 4777 if (unlikely(!coe)) 4778 skb_checksum_none_assert(skb); 4779 else 4780 skb->ip_summed = CHECKSUM_UNNECESSARY; 4781 4782 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4783 skb_set_hash(skb, hash, hash_type); 4784 4785 skb_record_rx_queue(skb, queue); 4786 napi_gro_receive(&ch->rxtx_napi, skb); 4787 4788 priv->dev->stats.rx_packets++; 4789 priv->dev->stats.rx_bytes += len; 4790 } 4791 4792 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4793 { 4794 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4795 unsigned int entry = rx_q->dirty_rx; 4796 struct dma_desc *rx_desc = NULL; 4797 bool ret = true; 4798 4799 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4800 4801 while (budget-- > 0 && entry != rx_q->cur_rx) { 4802 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4803 dma_addr_t dma_addr; 4804 bool use_rx_wd; 4805 4806 if (!buf->xdp) { 4807 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4808 if (!buf->xdp) { 4809 ret = false; 4810 break; 4811 } 4812 } 4813 4814 if (priv->extend_desc) 4815 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4816 else 4817 rx_desc = rx_q->dma_rx + entry; 4818 4819 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4820 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4821 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4822 stmmac_refill_desc3(priv, rx_q, rx_desc); 4823 4824 rx_q->rx_count_frames++; 4825 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4826 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4827 rx_q->rx_count_frames = 0; 4828 4829 use_rx_wd = !priv->rx_coal_frames[queue]; 4830 use_rx_wd |= rx_q->rx_count_frames > 0; 4831 if (!priv->use_riwt) 4832 use_rx_wd = false; 4833 4834 dma_wmb(); 4835 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4836 4837 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4838 } 4839 4840 if (rx_desc) { 4841 rx_q->dirty_rx = entry; 4842 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4843 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4844 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4845 } 4846 4847 return ret; 4848 } 4849 4850 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4851 { 4852 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4853 unsigned int count = 0, error = 0, len = 0; 4854 int dirty = stmmac_rx_dirty(priv, queue); 4855 unsigned int next_entry = rx_q->cur_rx; 4856 unsigned int desc_size; 4857 struct bpf_prog *prog; 4858 bool failure = false; 4859 int xdp_status = 0; 4860 int status = 0; 4861 4862 if (netif_msg_rx_status(priv)) { 4863 void *rx_head; 4864 4865 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4866 if (priv->extend_desc) { 4867 rx_head = (void *)rx_q->dma_erx; 4868 desc_size = sizeof(struct dma_extended_desc); 4869 } else { 4870 rx_head = (void *)rx_q->dma_rx; 4871 desc_size = sizeof(struct dma_desc); 4872 } 4873 4874 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 4875 rx_q->dma_rx_phy, desc_size); 4876 } 4877 while (count < limit) { 4878 struct stmmac_rx_buffer *buf; 4879 unsigned int buf1_len = 0; 4880 struct dma_desc *np, *p; 4881 int entry; 4882 int res; 4883 4884 if (!count && rx_q->state_saved) { 4885 error = rx_q->state.error; 4886 len = rx_q->state.len; 4887 } else { 4888 rx_q->state_saved = false; 4889 error = 0; 4890 len = 0; 4891 } 4892 4893 if (count >= limit) 4894 break; 4895 4896 read_again: 4897 buf1_len = 0; 4898 entry = next_entry; 4899 buf = &rx_q->buf_pool[entry]; 4900 4901 if (dirty >= STMMAC_RX_FILL_BATCH) { 4902 failure = failure || 4903 !stmmac_rx_refill_zc(priv, queue, dirty); 4904 dirty = 0; 4905 } 4906 4907 if (priv->extend_desc) 4908 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4909 else 4910 p = rx_q->dma_rx + entry; 4911 4912 /* read the status of the incoming frame */ 4913 status = stmmac_rx_status(priv, &priv->dev->stats, 4914 &priv->xstats, p); 4915 /* check if managed by the DMA otherwise go ahead */ 4916 if (unlikely(status & dma_own)) 4917 break; 4918 4919 /* Prefetch the next RX descriptor */ 4920 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 4921 priv->dma_rx_size); 4922 next_entry = rx_q->cur_rx; 4923 4924 if (priv->extend_desc) 4925 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 4926 else 4927 np = rx_q->dma_rx + next_entry; 4928 4929 prefetch(np); 4930 4931 /* Ensure a valid XSK buffer before proceed */ 4932 if (!buf->xdp) 4933 break; 4934 4935 if (priv->extend_desc) 4936 stmmac_rx_extended_status(priv, &priv->dev->stats, 4937 &priv->xstats, 4938 rx_q->dma_erx + entry); 4939 if (unlikely(status == discard_frame)) { 4940 xsk_buff_free(buf->xdp); 4941 buf->xdp = NULL; 4942 dirty++; 4943 error = 1; 4944 if (!priv->hwts_rx_en) 4945 priv->dev->stats.rx_errors++; 4946 } 4947 4948 if (unlikely(error && (status & rx_not_ls))) 4949 goto read_again; 4950 if (unlikely(error)) { 4951 count++; 4952 continue; 4953 } 4954 4955 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 4956 if (likely(status & rx_not_ls)) { 4957 xsk_buff_free(buf->xdp); 4958 buf->xdp = NULL; 4959 dirty++; 4960 count++; 4961 goto read_again; 4962 } 4963 4964 /* XDP ZC Frame only support primary buffers for now */ 4965 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 4966 len += buf1_len; 4967 4968 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 4969 * Type frames (LLC/LLC-SNAP) 4970 * 4971 * llc_snap is never checked in GMAC >= 4, so this ACS 4972 * feature is always disabled and packets need to be 4973 * stripped manually. 4974 */ 4975 if (likely(!(status & rx_not_ls)) && 4976 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 4977 unlikely(status != llc_snap))) { 4978 buf1_len -= ETH_FCS_LEN; 4979 len -= ETH_FCS_LEN; 4980 } 4981 4982 /* RX buffer is good and fit into a XSK pool buffer */ 4983 buf->xdp->data_end = buf->xdp->data + buf1_len; 4984 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 4985 4986 prog = READ_ONCE(priv->xdp_prog); 4987 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 4988 4989 switch (res) { 4990 case STMMAC_XDP_PASS: 4991 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 4992 xsk_buff_free(buf->xdp); 4993 break; 4994 case STMMAC_XDP_CONSUMED: 4995 xsk_buff_free(buf->xdp); 4996 priv->dev->stats.rx_dropped++; 4997 break; 4998 case STMMAC_XDP_TX: 4999 case STMMAC_XDP_REDIRECT: 5000 xdp_status |= res; 5001 break; 5002 } 5003 5004 buf->xdp = NULL; 5005 dirty++; 5006 count++; 5007 } 5008 5009 if (status & rx_not_ls) { 5010 rx_q->state_saved = true; 5011 rx_q->state.error = error; 5012 rx_q->state.len = len; 5013 } 5014 5015 stmmac_finalize_xdp_rx(priv, xdp_status); 5016 5017 priv->xstats.rx_pkt_n += count; 5018 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5019 5020 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5021 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5022 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5023 else 5024 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5025 5026 return (int)count; 5027 } 5028 5029 return failure ? limit : (int)count; 5030 } 5031 5032 /** 5033 * stmmac_rx - manage the receive process 5034 * @priv: driver private structure 5035 * @limit: napi bugget 5036 * @queue: RX queue index. 5037 * Description : this the function called by the napi poll method. 5038 * It gets all the frames inside the ring. 5039 */ 5040 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5041 { 5042 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5043 struct stmmac_channel *ch = &priv->channel[queue]; 5044 unsigned int count = 0, error = 0, len = 0; 5045 int status = 0, coe = priv->hw->rx_csum; 5046 unsigned int next_entry = rx_q->cur_rx; 5047 enum dma_data_direction dma_dir; 5048 unsigned int desc_size; 5049 struct sk_buff *skb = NULL; 5050 struct xdp_buff xdp; 5051 int xdp_status = 0; 5052 int buf_sz; 5053 5054 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5055 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5056 5057 if (netif_msg_rx_status(priv)) { 5058 void *rx_head; 5059 5060 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5061 if (priv->extend_desc) { 5062 rx_head = (void *)rx_q->dma_erx; 5063 desc_size = sizeof(struct dma_extended_desc); 5064 } else { 5065 rx_head = (void *)rx_q->dma_rx; 5066 desc_size = sizeof(struct dma_desc); 5067 } 5068 5069 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 5070 rx_q->dma_rx_phy, desc_size); 5071 } 5072 while (count < limit) { 5073 unsigned int buf1_len = 0, buf2_len = 0; 5074 enum pkt_hash_types hash_type; 5075 struct stmmac_rx_buffer *buf; 5076 struct dma_desc *np, *p; 5077 int entry; 5078 u32 hash; 5079 5080 if (!count && rx_q->state_saved) { 5081 skb = rx_q->state.skb; 5082 error = rx_q->state.error; 5083 len = rx_q->state.len; 5084 } else { 5085 rx_q->state_saved = false; 5086 skb = NULL; 5087 error = 0; 5088 len = 0; 5089 } 5090 5091 if (count >= limit) 5092 break; 5093 5094 read_again: 5095 buf1_len = 0; 5096 buf2_len = 0; 5097 entry = next_entry; 5098 buf = &rx_q->buf_pool[entry]; 5099 5100 if (priv->extend_desc) 5101 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5102 else 5103 p = rx_q->dma_rx + entry; 5104 5105 /* read the status of the incoming frame */ 5106 status = stmmac_rx_status(priv, &priv->dev->stats, 5107 &priv->xstats, p); 5108 /* check if managed by the DMA otherwise go ahead */ 5109 if (unlikely(status & dma_own)) 5110 break; 5111 5112 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5113 priv->dma_rx_size); 5114 next_entry = rx_q->cur_rx; 5115 5116 if (priv->extend_desc) 5117 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5118 else 5119 np = rx_q->dma_rx + next_entry; 5120 5121 prefetch(np); 5122 5123 if (priv->extend_desc) 5124 stmmac_rx_extended_status(priv, &priv->dev->stats, 5125 &priv->xstats, rx_q->dma_erx + entry); 5126 if (unlikely(status == discard_frame)) { 5127 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5128 buf->page = NULL; 5129 error = 1; 5130 if (!priv->hwts_rx_en) 5131 priv->dev->stats.rx_errors++; 5132 } 5133 5134 if (unlikely(error && (status & rx_not_ls))) 5135 goto read_again; 5136 if (unlikely(error)) { 5137 dev_kfree_skb(skb); 5138 skb = NULL; 5139 count++; 5140 continue; 5141 } 5142 5143 /* Buffer is good. Go on. */ 5144 5145 prefetch(page_address(buf->page) + buf->page_offset); 5146 if (buf->sec_page) 5147 prefetch(page_address(buf->sec_page)); 5148 5149 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5150 len += buf1_len; 5151 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5152 len += buf2_len; 5153 5154 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 5155 * Type frames (LLC/LLC-SNAP) 5156 * 5157 * llc_snap is never checked in GMAC >= 4, so this ACS 5158 * feature is always disabled and packets need to be 5159 * stripped manually. 5160 */ 5161 if (likely(!(status & rx_not_ls)) && 5162 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 5163 unlikely(status != llc_snap))) { 5164 if (buf2_len) 5165 buf2_len -= ETH_FCS_LEN; 5166 else 5167 buf1_len -= ETH_FCS_LEN; 5168 5169 len -= ETH_FCS_LEN; 5170 } 5171 5172 if (!skb) { 5173 unsigned int pre_len, sync_len; 5174 5175 dma_sync_single_for_cpu(priv->device, buf->addr, 5176 buf1_len, dma_dir); 5177 5178 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5179 xdp_prepare_buff(&xdp, page_address(buf->page), 5180 buf->page_offset, buf1_len, false); 5181 5182 pre_len = xdp.data_end - xdp.data_hard_start - 5183 buf->page_offset; 5184 skb = stmmac_xdp_run_prog(priv, &xdp); 5185 /* Due xdp_adjust_tail: DMA sync for_device 5186 * cover max len CPU touch 5187 */ 5188 sync_len = xdp.data_end - xdp.data_hard_start - 5189 buf->page_offset; 5190 sync_len = max(sync_len, pre_len); 5191 5192 /* For Not XDP_PASS verdict */ 5193 if (IS_ERR(skb)) { 5194 unsigned int xdp_res = -PTR_ERR(skb); 5195 5196 if (xdp_res & STMMAC_XDP_CONSUMED) { 5197 page_pool_put_page(rx_q->page_pool, 5198 virt_to_head_page(xdp.data), 5199 sync_len, true); 5200 buf->page = NULL; 5201 priv->dev->stats.rx_dropped++; 5202 5203 /* Clear skb as it was set as 5204 * status by XDP program. 5205 */ 5206 skb = NULL; 5207 5208 if (unlikely((status & rx_not_ls))) 5209 goto read_again; 5210 5211 count++; 5212 continue; 5213 } else if (xdp_res & (STMMAC_XDP_TX | 5214 STMMAC_XDP_REDIRECT)) { 5215 xdp_status |= xdp_res; 5216 buf->page = NULL; 5217 skb = NULL; 5218 count++; 5219 continue; 5220 } 5221 } 5222 } 5223 5224 if (!skb) { 5225 /* XDP program may expand or reduce tail */ 5226 buf1_len = xdp.data_end - xdp.data; 5227 5228 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5229 if (!skb) { 5230 priv->dev->stats.rx_dropped++; 5231 count++; 5232 goto drain_data; 5233 } 5234 5235 /* XDP program may adjust header */ 5236 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5237 skb_put(skb, buf1_len); 5238 5239 /* Data payload copied into SKB, page ready for recycle */ 5240 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5241 buf->page = NULL; 5242 } else if (buf1_len) { 5243 dma_sync_single_for_cpu(priv->device, buf->addr, 5244 buf1_len, dma_dir); 5245 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5246 buf->page, buf->page_offset, buf1_len, 5247 priv->dma_buf_sz); 5248 5249 /* Data payload appended into SKB */ 5250 page_pool_release_page(rx_q->page_pool, buf->page); 5251 buf->page = NULL; 5252 } 5253 5254 if (buf2_len) { 5255 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5256 buf2_len, dma_dir); 5257 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5258 buf->sec_page, 0, buf2_len, 5259 priv->dma_buf_sz); 5260 5261 /* Data payload appended into SKB */ 5262 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5263 buf->sec_page = NULL; 5264 } 5265 5266 drain_data: 5267 if (likely(status & rx_not_ls)) 5268 goto read_again; 5269 if (!skb) 5270 continue; 5271 5272 /* Got entire packet into SKB. Finish it. */ 5273 5274 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5275 stmmac_rx_vlan(priv->dev, skb); 5276 skb->protocol = eth_type_trans(skb, priv->dev); 5277 5278 if (unlikely(!coe)) 5279 skb_checksum_none_assert(skb); 5280 else 5281 skb->ip_summed = CHECKSUM_UNNECESSARY; 5282 5283 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5284 skb_set_hash(skb, hash, hash_type); 5285 5286 skb_record_rx_queue(skb, queue); 5287 napi_gro_receive(&ch->rx_napi, skb); 5288 skb = NULL; 5289 5290 priv->dev->stats.rx_packets++; 5291 priv->dev->stats.rx_bytes += len; 5292 count++; 5293 } 5294 5295 if (status & rx_not_ls || skb) { 5296 rx_q->state_saved = true; 5297 rx_q->state.skb = skb; 5298 rx_q->state.error = error; 5299 rx_q->state.len = len; 5300 } 5301 5302 stmmac_finalize_xdp_rx(priv, xdp_status); 5303 5304 stmmac_rx_refill(priv, queue); 5305 5306 priv->xstats.rx_pkt_n += count; 5307 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5308 5309 return count; 5310 } 5311 5312 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5313 { 5314 struct stmmac_channel *ch = 5315 container_of(napi, struct stmmac_channel, rx_napi); 5316 struct stmmac_priv *priv = ch->priv_data; 5317 u32 chan = ch->index; 5318 int work_done; 5319 5320 priv->xstats.napi_poll++; 5321 5322 work_done = stmmac_rx(priv, budget, chan); 5323 if (work_done < budget && napi_complete_done(napi, work_done)) { 5324 unsigned long flags; 5325 5326 spin_lock_irqsave(&ch->lock, flags); 5327 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5328 spin_unlock_irqrestore(&ch->lock, flags); 5329 } 5330 5331 return work_done; 5332 } 5333 5334 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5335 { 5336 struct stmmac_channel *ch = 5337 container_of(napi, struct stmmac_channel, tx_napi); 5338 struct stmmac_priv *priv = ch->priv_data; 5339 u32 chan = ch->index; 5340 int work_done; 5341 5342 priv->xstats.napi_poll++; 5343 5344 work_done = stmmac_tx_clean(priv, budget, chan); 5345 work_done = min(work_done, budget); 5346 5347 if (work_done < budget && napi_complete_done(napi, work_done)) { 5348 unsigned long flags; 5349 5350 spin_lock_irqsave(&ch->lock, flags); 5351 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5352 spin_unlock_irqrestore(&ch->lock, flags); 5353 } 5354 5355 return work_done; 5356 } 5357 5358 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5359 { 5360 struct stmmac_channel *ch = 5361 container_of(napi, struct stmmac_channel, rxtx_napi); 5362 struct stmmac_priv *priv = ch->priv_data; 5363 int rx_done, tx_done, rxtx_done; 5364 u32 chan = ch->index; 5365 5366 priv->xstats.napi_poll++; 5367 5368 tx_done = stmmac_tx_clean(priv, budget, chan); 5369 tx_done = min(tx_done, budget); 5370 5371 rx_done = stmmac_rx_zc(priv, budget, chan); 5372 5373 rxtx_done = max(tx_done, rx_done); 5374 5375 /* If either TX or RX work is not complete, return budget 5376 * and keep pooling 5377 */ 5378 if (rxtx_done >= budget) 5379 return budget; 5380 5381 /* all work done, exit the polling mode */ 5382 if (napi_complete_done(napi, rxtx_done)) { 5383 unsigned long flags; 5384 5385 spin_lock_irqsave(&ch->lock, flags); 5386 /* Both RX and TX work done are compelte, 5387 * so enable both RX & TX IRQs. 5388 */ 5389 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5390 spin_unlock_irqrestore(&ch->lock, flags); 5391 } 5392 5393 return min(rxtx_done, budget - 1); 5394 } 5395 5396 /** 5397 * stmmac_tx_timeout 5398 * @dev : Pointer to net device structure 5399 * @txqueue: the index of the hanging transmit queue 5400 * Description: this function is called when a packet transmission fails to 5401 * complete within a reasonable time. The driver will mark the error in the 5402 * netdev structure and arrange for the device to be reset to a sane state 5403 * in order to transmit a new packet. 5404 */ 5405 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5406 { 5407 struct stmmac_priv *priv = netdev_priv(dev); 5408 5409 stmmac_global_err(priv); 5410 } 5411 5412 /** 5413 * stmmac_set_rx_mode - entry point for multicast addressing 5414 * @dev : pointer to the device structure 5415 * Description: 5416 * This function is a driver entry point which gets called by the kernel 5417 * whenever multicast addresses must be enabled/disabled. 5418 * Return value: 5419 * void. 5420 */ 5421 static void stmmac_set_rx_mode(struct net_device *dev) 5422 { 5423 struct stmmac_priv *priv = netdev_priv(dev); 5424 5425 stmmac_set_filter(priv, priv->hw, dev); 5426 } 5427 5428 /** 5429 * stmmac_change_mtu - entry point to change MTU size for the device. 5430 * @dev : device pointer. 5431 * @new_mtu : the new MTU size for the device. 5432 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5433 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5434 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5435 * Return value: 5436 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5437 * file on failure. 5438 */ 5439 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5440 { 5441 struct stmmac_priv *priv = netdev_priv(dev); 5442 int txfifosz = priv->plat->tx_fifo_size; 5443 const int mtu = new_mtu; 5444 5445 if (txfifosz == 0) 5446 txfifosz = priv->dma_cap.tx_fifo_size; 5447 5448 txfifosz /= priv->plat->tx_queues_to_use; 5449 5450 if (netif_running(dev)) { 5451 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 5452 return -EBUSY; 5453 } 5454 5455 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5456 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5457 return -EINVAL; 5458 } 5459 5460 new_mtu = STMMAC_ALIGN(new_mtu); 5461 5462 /* If condition true, FIFO is too small or MTU too large */ 5463 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5464 return -EINVAL; 5465 5466 dev->mtu = mtu; 5467 5468 netdev_update_features(dev); 5469 5470 return 0; 5471 } 5472 5473 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5474 netdev_features_t features) 5475 { 5476 struct stmmac_priv *priv = netdev_priv(dev); 5477 5478 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5479 features &= ~NETIF_F_RXCSUM; 5480 5481 if (!priv->plat->tx_coe) 5482 features &= ~NETIF_F_CSUM_MASK; 5483 5484 /* Some GMAC devices have a bugged Jumbo frame support that 5485 * needs to have the Tx COE disabled for oversized frames 5486 * (due to limited buffer sizes). In this case we disable 5487 * the TX csum insertion in the TDES and not use SF. 5488 */ 5489 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5490 features &= ~NETIF_F_CSUM_MASK; 5491 5492 /* Disable tso if asked by ethtool */ 5493 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5494 if (features & NETIF_F_TSO) 5495 priv->tso = true; 5496 else 5497 priv->tso = false; 5498 } 5499 5500 return features; 5501 } 5502 5503 static int stmmac_set_features(struct net_device *netdev, 5504 netdev_features_t features) 5505 { 5506 struct stmmac_priv *priv = netdev_priv(netdev); 5507 bool sph_en; 5508 u32 chan; 5509 5510 /* Keep the COE Type in case of csum is supporting */ 5511 if (features & NETIF_F_RXCSUM) 5512 priv->hw->rx_csum = priv->plat->rx_coe; 5513 else 5514 priv->hw->rx_csum = 0; 5515 /* No check needed because rx_coe has been set before and it will be 5516 * fixed in case of issue. 5517 */ 5518 stmmac_rx_ipc(priv, priv->hw); 5519 5520 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5521 5522 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5523 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5524 5525 return 0; 5526 } 5527 5528 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5529 { 5530 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5531 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5532 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5533 bool *hs_enable = &fpe_cfg->hs_enable; 5534 5535 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5536 return; 5537 5538 /* If LP has sent verify mPacket, LP is FPE capable */ 5539 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5540 if (*lp_state < FPE_STATE_CAPABLE) 5541 *lp_state = FPE_STATE_CAPABLE; 5542 5543 /* If user has requested FPE enable, quickly response */ 5544 if (*hs_enable) 5545 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5546 MPACKET_RESPONSE); 5547 } 5548 5549 /* If Local has sent verify mPacket, Local is FPE capable */ 5550 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5551 if (*lo_state < FPE_STATE_CAPABLE) 5552 *lo_state = FPE_STATE_CAPABLE; 5553 } 5554 5555 /* If LP has sent response mPacket, LP is entering FPE ON */ 5556 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5557 *lp_state = FPE_STATE_ENTERING_ON; 5558 5559 /* If Local has sent response mPacket, Local is entering FPE ON */ 5560 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5561 *lo_state = FPE_STATE_ENTERING_ON; 5562 5563 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5564 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5565 priv->fpe_wq) { 5566 queue_work(priv->fpe_wq, &priv->fpe_task); 5567 } 5568 } 5569 5570 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5571 { 5572 u32 rx_cnt = priv->plat->rx_queues_to_use; 5573 u32 tx_cnt = priv->plat->tx_queues_to_use; 5574 u32 queues_count; 5575 u32 queue; 5576 bool xmac; 5577 5578 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5579 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5580 5581 if (priv->irq_wake) 5582 pm_wakeup_event(priv->device, 0); 5583 5584 if (priv->dma_cap.estsel) 5585 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5586 &priv->xstats, tx_cnt); 5587 5588 if (priv->dma_cap.fpesel) { 5589 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5590 priv->dev); 5591 5592 stmmac_fpe_event_status(priv, status); 5593 } 5594 5595 /* To handle GMAC own interrupts */ 5596 if ((priv->plat->has_gmac) || xmac) { 5597 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5598 5599 if (unlikely(status)) { 5600 /* For LPI we need to save the tx status */ 5601 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5602 priv->tx_path_in_lpi_mode = true; 5603 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5604 priv->tx_path_in_lpi_mode = false; 5605 } 5606 5607 for (queue = 0; queue < queues_count; queue++) { 5608 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5609 queue); 5610 } 5611 5612 /* PCS link status */ 5613 if (priv->hw->pcs) { 5614 if (priv->xstats.pcs_link) 5615 netif_carrier_on(priv->dev); 5616 else 5617 netif_carrier_off(priv->dev); 5618 } 5619 5620 stmmac_timestamp_interrupt(priv, priv); 5621 } 5622 } 5623 5624 /** 5625 * stmmac_interrupt - main ISR 5626 * @irq: interrupt number. 5627 * @dev_id: to pass the net device pointer. 5628 * Description: this is the main driver interrupt service routine. 5629 * It can call: 5630 * o DMA service routine (to manage incoming frame reception and transmission 5631 * status) 5632 * o Core interrupts to manage: remote wake-up, management counter, LPI 5633 * interrupts. 5634 */ 5635 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5636 { 5637 struct net_device *dev = (struct net_device *)dev_id; 5638 struct stmmac_priv *priv = netdev_priv(dev); 5639 5640 /* Check if adapter is up */ 5641 if (test_bit(STMMAC_DOWN, &priv->state)) 5642 return IRQ_HANDLED; 5643 5644 /* Check if a fatal error happened */ 5645 if (stmmac_safety_feat_interrupt(priv)) 5646 return IRQ_HANDLED; 5647 5648 /* To handle Common interrupts */ 5649 stmmac_common_interrupt(priv); 5650 5651 /* To handle DMA interrupts */ 5652 stmmac_dma_interrupt(priv); 5653 5654 return IRQ_HANDLED; 5655 } 5656 5657 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5658 { 5659 struct net_device *dev = (struct net_device *)dev_id; 5660 struct stmmac_priv *priv = netdev_priv(dev); 5661 5662 if (unlikely(!dev)) { 5663 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5664 return IRQ_NONE; 5665 } 5666 5667 /* Check if adapter is up */ 5668 if (test_bit(STMMAC_DOWN, &priv->state)) 5669 return IRQ_HANDLED; 5670 5671 /* To handle Common interrupts */ 5672 stmmac_common_interrupt(priv); 5673 5674 return IRQ_HANDLED; 5675 } 5676 5677 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5678 { 5679 struct net_device *dev = (struct net_device *)dev_id; 5680 struct stmmac_priv *priv = netdev_priv(dev); 5681 5682 if (unlikely(!dev)) { 5683 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5684 return IRQ_NONE; 5685 } 5686 5687 /* Check if adapter is up */ 5688 if (test_bit(STMMAC_DOWN, &priv->state)) 5689 return IRQ_HANDLED; 5690 5691 /* Check if a fatal error happened */ 5692 stmmac_safety_feat_interrupt(priv); 5693 5694 return IRQ_HANDLED; 5695 } 5696 5697 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5698 { 5699 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5700 int chan = tx_q->queue_index; 5701 struct stmmac_priv *priv; 5702 int status; 5703 5704 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); 5705 5706 if (unlikely(!data)) { 5707 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5708 return IRQ_NONE; 5709 } 5710 5711 /* Check if adapter is up */ 5712 if (test_bit(STMMAC_DOWN, &priv->state)) 5713 return IRQ_HANDLED; 5714 5715 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5716 5717 if (unlikely(status & tx_hard_error_bump_tc)) { 5718 /* Try to bump up the dma threshold on this failure */ 5719 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 5720 tc <= 256) { 5721 tc += 64; 5722 if (priv->plat->force_thresh_dma_mode) 5723 stmmac_set_dma_operation_mode(priv, 5724 tc, 5725 tc, 5726 chan); 5727 else 5728 stmmac_set_dma_operation_mode(priv, 5729 tc, 5730 SF_DMA_MODE, 5731 chan); 5732 priv->xstats.threshold = tc; 5733 } 5734 } else if (unlikely(status == tx_hard_error)) { 5735 stmmac_tx_err(priv, chan); 5736 } 5737 5738 return IRQ_HANDLED; 5739 } 5740 5741 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5742 { 5743 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5744 int chan = rx_q->queue_index; 5745 struct stmmac_priv *priv; 5746 5747 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); 5748 5749 if (unlikely(!data)) { 5750 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5751 return IRQ_NONE; 5752 } 5753 5754 /* Check if adapter is up */ 5755 if (test_bit(STMMAC_DOWN, &priv->state)) 5756 return IRQ_HANDLED; 5757 5758 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5759 5760 return IRQ_HANDLED; 5761 } 5762 5763 #ifdef CONFIG_NET_POLL_CONTROLLER 5764 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5765 * to allow network I/O with interrupts disabled. 5766 */ 5767 static void stmmac_poll_controller(struct net_device *dev) 5768 { 5769 struct stmmac_priv *priv = netdev_priv(dev); 5770 int i; 5771 5772 /* If adapter is down, do nothing */ 5773 if (test_bit(STMMAC_DOWN, &priv->state)) 5774 return; 5775 5776 if (priv->plat->multi_msi_en) { 5777 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5778 stmmac_msi_intr_rx(0, &priv->rx_queue[i]); 5779 5780 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5781 stmmac_msi_intr_tx(0, &priv->tx_queue[i]); 5782 } else { 5783 disable_irq(dev->irq); 5784 stmmac_interrupt(dev->irq, dev); 5785 enable_irq(dev->irq); 5786 } 5787 } 5788 #endif 5789 5790 /** 5791 * stmmac_ioctl - Entry point for the Ioctl 5792 * @dev: Device pointer. 5793 * @rq: An IOCTL specefic structure, that can contain a pointer to 5794 * a proprietary structure used to pass information to the driver. 5795 * @cmd: IOCTL command 5796 * Description: 5797 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5798 */ 5799 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5800 { 5801 struct stmmac_priv *priv = netdev_priv (dev); 5802 int ret = -EOPNOTSUPP; 5803 5804 if (!netif_running(dev)) 5805 return -EINVAL; 5806 5807 switch (cmd) { 5808 case SIOCGMIIPHY: 5809 case SIOCGMIIREG: 5810 case SIOCSMIIREG: 5811 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5812 break; 5813 case SIOCSHWTSTAMP: 5814 ret = stmmac_hwtstamp_set(dev, rq); 5815 break; 5816 case SIOCGHWTSTAMP: 5817 ret = stmmac_hwtstamp_get(dev, rq); 5818 break; 5819 default: 5820 break; 5821 } 5822 5823 return ret; 5824 } 5825 5826 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5827 void *cb_priv) 5828 { 5829 struct stmmac_priv *priv = cb_priv; 5830 int ret = -EOPNOTSUPP; 5831 5832 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5833 return ret; 5834 5835 __stmmac_disable_all_queues(priv); 5836 5837 switch (type) { 5838 case TC_SETUP_CLSU32: 5839 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5840 break; 5841 case TC_SETUP_CLSFLOWER: 5842 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5843 break; 5844 default: 5845 break; 5846 } 5847 5848 stmmac_enable_all_queues(priv); 5849 return ret; 5850 } 5851 5852 static LIST_HEAD(stmmac_block_cb_list); 5853 5854 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5855 void *type_data) 5856 { 5857 struct stmmac_priv *priv = netdev_priv(ndev); 5858 5859 switch (type) { 5860 case TC_SETUP_BLOCK: 5861 return flow_block_cb_setup_simple(type_data, 5862 &stmmac_block_cb_list, 5863 stmmac_setup_tc_block_cb, 5864 priv, priv, true); 5865 case TC_SETUP_QDISC_CBS: 5866 return stmmac_tc_setup_cbs(priv, priv, type_data); 5867 case TC_SETUP_QDISC_TAPRIO: 5868 return stmmac_tc_setup_taprio(priv, priv, type_data); 5869 case TC_SETUP_QDISC_ETF: 5870 return stmmac_tc_setup_etf(priv, priv, type_data); 5871 default: 5872 return -EOPNOTSUPP; 5873 } 5874 } 5875 5876 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5877 struct net_device *sb_dev) 5878 { 5879 int gso = skb_shinfo(skb)->gso_type; 5880 5881 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5882 /* 5883 * There is no way to determine the number of TSO/USO 5884 * capable Queues. Let's use always the Queue 0 5885 * because if TSO/USO is supported then at least this 5886 * one will be capable. 5887 */ 5888 return 0; 5889 } 5890 5891 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5892 } 5893 5894 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 5895 { 5896 struct stmmac_priv *priv = netdev_priv(ndev); 5897 int ret = 0; 5898 5899 ret = pm_runtime_get_sync(priv->device); 5900 if (ret < 0) { 5901 pm_runtime_put_noidle(priv->device); 5902 return ret; 5903 } 5904 5905 ret = eth_mac_addr(ndev, addr); 5906 if (ret) 5907 goto set_mac_error; 5908 5909 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 5910 5911 set_mac_error: 5912 pm_runtime_put(priv->device); 5913 5914 return ret; 5915 } 5916 5917 #ifdef CONFIG_DEBUG_FS 5918 static struct dentry *stmmac_fs_dir; 5919 5920 static void sysfs_display_ring(void *head, int size, int extend_desc, 5921 struct seq_file *seq, dma_addr_t dma_phy_addr) 5922 { 5923 int i; 5924 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 5925 struct dma_desc *p = (struct dma_desc *)head; 5926 dma_addr_t dma_addr; 5927 5928 for (i = 0; i < size; i++) { 5929 if (extend_desc) { 5930 dma_addr = dma_phy_addr + i * sizeof(*ep); 5931 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5932 i, &dma_addr, 5933 le32_to_cpu(ep->basic.des0), 5934 le32_to_cpu(ep->basic.des1), 5935 le32_to_cpu(ep->basic.des2), 5936 le32_to_cpu(ep->basic.des3)); 5937 ep++; 5938 } else { 5939 dma_addr = dma_phy_addr + i * sizeof(*p); 5940 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5941 i, &dma_addr, 5942 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 5943 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 5944 p++; 5945 } 5946 seq_printf(seq, "\n"); 5947 } 5948 } 5949 5950 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 5951 { 5952 struct net_device *dev = seq->private; 5953 struct stmmac_priv *priv = netdev_priv(dev); 5954 u32 rx_count = priv->plat->rx_queues_to_use; 5955 u32 tx_count = priv->plat->tx_queues_to_use; 5956 u32 queue; 5957 5958 if ((dev->flags & IFF_UP) == 0) 5959 return 0; 5960 5961 for (queue = 0; queue < rx_count; queue++) { 5962 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5963 5964 seq_printf(seq, "RX Queue %d:\n", queue); 5965 5966 if (priv->extend_desc) { 5967 seq_printf(seq, "Extended descriptor ring:\n"); 5968 sysfs_display_ring((void *)rx_q->dma_erx, 5969 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 5970 } else { 5971 seq_printf(seq, "Descriptor ring:\n"); 5972 sysfs_display_ring((void *)rx_q->dma_rx, 5973 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 5974 } 5975 } 5976 5977 for (queue = 0; queue < tx_count; queue++) { 5978 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5979 5980 seq_printf(seq, "TX Queue %d:\n", queue); 5981 5982 if (priv->extend_desc) { 5983 seq_printf(seq, "Extended descriptor ring:\n"); 5984 sysfs_display_ring((void *)tx_q->dma_etx, 5985 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 5986 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 5987 seq_printf(seq, "Descriptor ring:\n"); 5988 sysfs_display_ring((void *)tx_q->dma_tx, 5989 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 5990 } 5991 } 5992 5993 return 0; 5994 } 5995 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 5996 5997 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 5998 { 5999 struct net_device *dev = seq->private; 6000 struct stmmac_priv *priv = netdev_priv(dev); 6001 6002 if (!priv->hw_cap_support) { 6003 seq_printf(seq, "DMA HW features not supported\n"); 6004 return 0; 6005 } 6006 6007 seq_printf(seq, "==============================\n"); 6008 seq_printf(seq, "\tDMA HW features\n"); 6009 seq_printf(seq, "==============================\n"); 6010 6011 seq_printf(seq, "\t10/100 Mbps: %s\n", 6012 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6013 seq_printf(seq, "\t1000 Mbps: %s\n", 6014 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6015 seq_printf(seq, "\tHalf duplex: %s\n", 6016 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6017 seq_printf(seq, "\tHash Filter: %s\n", 6018 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6019 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6020 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6021 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6022 (priv->dma_cap.pcs) ? "Y" : "N"); 6023 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6024 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6025 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6026 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6027 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6028 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6029 seq_printf(seq, "\tRMON module: %s\n", 6030 (priv->dma_cap.rmon) ? "Y" : "N"); 6031 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6032 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6033 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6034 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6035 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6036 (priv->dma_cap.eee) ? "Y" : "N"); 6037 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6038 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6039 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6040 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6041 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6042 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6043 } else { 6044 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6045 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6046 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6047 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6048 } 6049 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6050 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6051 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6052 priv->dma_cap.number_rx_channel); 6053 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6054 priv->dma_cap.number_tx_channel); 6055 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6056 priv->dma_cap.number_rx_queues); 6057 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6058 priv->dma_cap.number_tx_queues); 6059 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6060 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6061 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6062 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6063 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6064 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6065 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6066 priv->dma_cap.pps_out_num); 6067 seq_printf(seq, "\tSafety Features: %s\n", 6068 priv->dma_cap.asp ? "Y" : "N"); 6069 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6070 priv->dma_cap.frpsel ? "Y" : "N"); 6071 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6072 priv->dma_cap.addr64); 6073 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6074 priv->dma_cap.rssen ? "Y" : "N"); 6075 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6076 priv->dma_cap.vlhash ? "Y" : "N"); 6077 seq_printf(seq, "\tSplit Header: %s\n", 6078 priv->dma_cap.sphen ? "Y" : "N"); 6079 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6080 priv->dma_cap.vlins ? "Y" : "N"); 6081 seq_printf(seq, "\tDouble VLAN: %s\n", 6082 priv->dma_cap.dvlan ? "Y" : "N"); 6083 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6084 priv->dma_cap.l3l4fnum); 6085 seq_printf(seq, "\tARP Offloading: %s\n", 6086 priv->dma_cap.arpoffsel ? "Y" : "N"); 6087 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6088 priv->dma_cap.estsel ? "Y" : "N"); 6089 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6090 priv->dma_cap.fpesel ? "Y" : "N"); 6091 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6092 priv->dma_cap.tbssel ? "Y" : "N"); 6093 return 0; 6094 } 6095 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6096 6097 /* Use network device events to rename debugfs file entries. 6098 */ 6099 static int stmmac_device_event(struct notifier_block *unused, 6100 unsigned long event, void *ptr) 6101 { 6102 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6103 struct stmmac_priv *priv = netdev_priv(dev); 6104 6105 if (dev->netdev_ops != &stmmac_netdev_ops) 6106 goto done; 6107 6108 switch (event) { 6109 case NETDEV_CHANGENAME: 6110 if (priv->dbgfs_dir) 6111 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6112 priv->dbgfs_dir, 6113 stmmac_fs_dir, 6114 dev->name); 6115 break; 6116 } 6117 done: 6118 return NOTIFY_DONE; 6119 } 6120 6121 static struct notifier_block stmmac_notifier = { 6122 .notifier_call = stmmac_device_event, 6123 }; 6124 6125 static void stmmac_init_fs(struct net_device *dev) 6126 { 6127 struct stmmac_priv *priv = netdev_priv(dev); 6128 6129 rtnl_lock(); 6130 6131 /* Create per netdev entries */ 6132 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6133 6134 /* Entry to report DMA RX/TX rings */ 6135 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6136 &stmmac_rings_status_fops); 6137 6138 /* Entry to report the DMA HW features */ 6139 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6140 &stmmac_dma_cap_fops); 6141 6142 rtnl_unlock(); 6143 } 6144 6145 static void stmmac_exit_fs(struct net_device *dev) 6146 { 6147 struct stmmac_priv *priv = netdev_priv(dev); 6148 6149 debugfs_remove_recursive(priv->dbgfs_dir); 6150 } 6151 #endif /* CONFIG_DEBUG_FS */ 6152 6153 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6154 { 6155 unsigned char *data = (unsigned char *)&vid_le; 6156 unsigned char data_byte = 0; 6157 u32 crc = ~0x0; 6158 u32 temp = 0; 6159 int i, bits; 6160 6161 bits = get_bitmask_order(VLAN_VID_MASK); 6162 for (i = 0; i < bits; i++) { 6163 if ((i % 8) == 0) 6164 data_byte = data[i / 8]; 6165 6166 temp = ((crc & 1) ^ data_byte) & 1; 6167 crc >>= 1; 6168 data_byte >>= 1; 6169 6170 if (temp) 6171 crc ^= 0xedb88320; 6172 } 6173 6174 return crc; 6175 } 6176 6177 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6178 { 6179 u32 crc, hash = 0; 6180 __le16 pmatch = 0; 6181 int count = 0; 6182 u16 vid = 0; 6183 6184 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6185 __le16 vid_le = cpu_to_le16(vid); 6186 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6187 hash |= (1 << crc); 6188 count++; 6189 } 6190 6191 if (!priv->dma_cap.vlhash) { 6192 if (count > 2) /* VID = 0 always passes filter */ 6193 return -EOPNOTSUPP; 6194 6195 pmatch = cpu_to_le16(vid); 6196 hash = 0; 6197 } 6198 6199 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6200 } 6201 6202 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6203 { 6204 struct stmmac_priv *priv = netdev_priv(ndev); 6205 bool is_double = false; 6206 int ret; 6207 6208 if (be16_to_cpu(proto) == ETH_P_8021AD) 6209 is_double = true; 6210 6211 set_bit(vid, priv->active_vlans); 6212 ret = stmmac_vlan_update(priv, is_double); 6213 if (ret) { 6214 clear_bit(vid, priv->active_vlans); 6215 return ret; 6216 } 6217 6218 if (priv->hw->num_vlan) { 6219 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6220 if (ret) 6221 return ret; 6222 } 6223 6224 return 0; 6225 } 6226 6227 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6228 { 6229 struct stmmac_priv *priv = netdev_priv(ndev); 6230 bool is_double = false; 6231 int ret; 6232 6233 ret = pm_runtime_get_sync(priv->device); 6234 if (ret < 0) { 6235 pm_runtime_put_noidle(priv->device); 6236 return ret; 6237 } 6238 6239 if (be16_to_cpu(proto) == ETH_P_8021AD) 6240 is_double = true; 6241 6242 clear_bit(vid, priv->active_vlans); 6243 6244 if (priv->hw->num_vlan) { 6245 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6246 if (ret) 6247 goto del_vlan_error; 6248 } 6249 6250 ret = stmmac_vlan_update(priv, is_double); 6251 6252 del_vlan_error: 6253 pm_runtime_put(priv->device); 6254 6255 return ret; 6256 } 6257 6258 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6259 { 6260 struct stmmac_priv *priv = netdev_priv(dev); 6261 6262 switch (bpf->command) { 6263 case XDP_SETUP_PROG: 6264 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6265 case XDP_SETUP_XSK_POOL: 6266 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6267 bpf->xsk.queue_id); 6268 default: 6269 return -EOPNOTSUPP; 6270 } 6271 } 6272 6273 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6274 struct xdp_frame **frames, u32 flags) 6275 { 6276 struct stmmac_priv *priv = netdev_priv(dev); 6277 int cpu = smp_processor_id(); 6278 struct netdev_queue *nq; 6279 int i, nxmit = 0; 6280 int queue; 6281 6282 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6283 return -ENETDOWN; 6284 6285 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6286 return -EINVAL; 6287 6288 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6289 nq = netdev_get_tx_queue(priv->dev, queue); 6290 6291 __netif_tx_lock(nq, cpu); 6292 /* Avoids TX time-out as we are sharing with slow path */ 6293 nq->trans_start = jiffies; 6294 6295 for (i = 0; i < num_frames; i++) { 6296 int res; 6297 6298 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6299 if (res == STMMAC_XDP_CONSUMED) 6300 break; 6301 6302 nxmit++; 6303 } 6304 6305 if (flags & XDP_XMIT_FLUSH) { 6306 stmmac_flush_tx_descriptors(priv, queue); 6307 stmmac_tx_timer_arm(priv, queue); 6308 } 6309 6310 __netif_tx_unlock(nq); 6311 6312 return nxmit; 6313 } 6314 6315 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6316 { 6317 struct stmmac_channel *ch = &priv->channel[queue]; 6318 unsigned long flags; 6319 6320 spin_lock_irqsave(&ch->lock, flags); 6321 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6322 spin_unlock_irqrestore(&ch->lock, flags); 6323 6324 stmmac_stop_rx_dma(priv, queue); 6325 __free_dma_rx_desc_resources(priv, queue); 6326 } 6327 6328 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6329 { 6330 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 6331 struct stmmac_channel *ch = &priv->channel[queue]; 6332 unsigned long flags; 6333 u32 buf_size; 6334 int ret; 6335 6336 ret = __alloc_dma_rx_desc_resources(priv, queue); 6337 if (ret) { 6338 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6339 return; 6340 } 6341 6342 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); 6343 if (ret) { 6344 __free_dma_rx_desc_resources(priv, queue); 6345 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6346 return; 6347 } 6348 6349 stmmac_clear_rx_descriptors(priv, queue); 6350 6351 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6352 rx_q->dma_rx_phy, rx_q->queue_index); 6353 6354 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6355 sizeof(struct dma_desc)); 6356 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6357 rx_q->rx_tail_addr, rx_q->queue_index); 6358 6359 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6360 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6361 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6362 buf_size, 6363 rx_q->queue_index); 6364 } else { 6365 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6366 priv->dma_buf_sz, 6367 rx_q->queue_index); 6368 } 6369 6370 stmmac_start_rx_dma(priv, queue); 6371 6372 spin_lock_irqsave(&ch->lock, flags); 6373 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6374 spin_unlock_irqrestore(&ch->lock, flags); 6375 } 6376 6377 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6378 { 6379 struct stmmac_channel *ch = &priv->channel[queue]; 6380 unsigned long flags; 6381 6382 spin_lock_irqsave(&ch->lock, flags); 6383 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6384 spin_unlock_irqrestore(&ch->lock, flags); 6385 6386 stmmac_stop_tx_dma(priv, queue); 6387 __free_dma_tx_desc_resources(priv, queue); 6388 } 6389 6390 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6391 { 6392 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 6393 struct stmmac_channel *ch = &priv->channel[queue]; 6394 unsigned long flags; 6395 int ret; 6396 6397 ret = __alloc_dma_tx_desc_resources(priv, queue); 6398 if (ret) { 6399 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6400 return; 6401 } 6402 6403 ret = __init_dma_tx_desc_rings(priv, queue); 6404 if (ret) { 6405 __free_dma_tx_desc_resources(priv, queue); 6406 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6407 return; 6408 } 6409 6410 stmmac_clear_tx_descriptors(priv, queue); 6411 6412 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6413 tx_q->dma_tx_phy, tx_q->queue_index); 6414 6415 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6416 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6417 6418 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6419 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6420 tx_q->tx_tail_addr, tx_q->queue_index); 6421 6422 stmmac_start_tx_dma(priv, queue); 6423 6424 spin_lock_irqsave(&ch->lock, flags); 6425 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6426 spin_unlock_irqrestore(&ch->lock, flags); 6427 } 6428 6429 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6430 { 6431 struct stmmac_priv *priv = netdev_priv(dev); 6432 struct stmmac_rx_queue *rx_q; 6433 struct stmmac_tx_queue *tx_q; 6434 struct stmmac_channel *ch; 6435 6436 if (test_bit(STMMAC_DOWN, &priv->state) || 6437 !netif_carrier_ok(priv->dev)) 6438 return -ENETDOWN; 6439 6440 if (!stmmac_xdp_is_enabled(priv)) 6441 return -ENXIO; 6442 6443 if (queue >= priv->plat->rx_queues_to_use || 6444 queue >= priv->plat->tx_queues_to_use) 6445 return -EINVAL; 6446 6447 rx_q = &priv->rx_queue[queue]; 6448 tx_q = &priv->tx_queue[queue]; 6449 ch = &priv->channel[queue]; 6450 6451 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6452 return -ENXIO; 6453 6454 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6455 /* EQoS does not have per-DMA channel SW interrupt, 6456 * so we schedule RX Napi straight-away. 6457 */ 6458 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6459 __napi_schedule(&ch->rxtx_napi); 6460 } 6461 6462 return 0; 6463 } 6464 6465 static const struct net_device_ops stmmac_netdev_ops = { 6466 .ndo_open = stmmac_open, 6467 .ndo_start_xmit = stmmac_xmit, 6468 .ndo_stop = stmmac_release, 6469 .ndo_change_mtu = stmmac_change_mtu, 6470 .ndo_fix_features = stmmac_fix_features, 6471 .ndo_set_features = stmmac_set_features, 6472 .ndo_set_rx_mode = stmmac_set_rx_mode, 6473 .ndo_tx_timeout = stmmac_tx_timeout, 6474 .ndo_eth_ioctl = stmmac_ioctl, 6475 .ndo_setup_tc = stmmac_setup_tc, 6476 .ndo_select_queue = stmmac_select_queue, 6477 #ifdef CONFIG_NET_POLL_CONTROLLER 6478 .ndo_poll_controller = stmmac_poll_controller, 6479 #endif 6480 .ndo_set_mac_address = stmmac_set_mac_address, 6481 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6482 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6483 .ndo_bpf = stmmac_bpf, 6484 .ndo_xdp_xmit = stmmac_xdp_xmit, 6485 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6486 }; 6487 6488 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6489 { 6490 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6491 return; 6492 if (test_bit(STMMAC_DOWN, &priv->state)) 6493 return; 6494 6495 netdev_err(priv->dev, "Reset adapter.\n"); 6496 6497 rtnl_lock(); 6498 netif_trans_update(priv->dev); 6499 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6500 usleep_range(1000, 2000); 6501 6502 set_bit(STMMAC_DOWN, &priv->state); 6503 dev_close(priv->dev); 6504 dev_open(priv->dev, NULL); 6505 clear_bit(STMMAC_DOWN, &priv->state); 6506 clear_bit(STMMAC_RESETING, &priv->state); 6507 rtnl_unlock(); 6508 } 6509 6510 static void stmmac_service_task(struct work_struct *work) 6511 { 6512 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6513 service_task); 6514 6515 stmmac_reset_subtask(priv); 6516 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6517 } 6518 6519 /** 6520 * stmmac_hw_init - Init the MAC device 6521 * @priv: driver private structure 6522 * Description: this function is to configure the MAC device according to 6523 * some platform parameters or the HW capability register. It prepares the 6524 * driver to use either ring or chain modes and to setup either enhanced or 6525 * normal descriptors. 6526 */ 6527 static int stmmac_hw_init(struct stmmac_priv *priv) 6528 { 6529 int ret; 6530 6531 /* dwmac-sun8i only work in chain mode */ 6532 if (priv->plat->has_sun8i) 6533 chain_mode = 1; 6534 priv->chain_mode = chain_mode; 6535 6536 /* Initialize HW Interface */ 6537 ret = stmmac_hwif_init(priv); 6538 if (ret) 6539 return ret; 6540 6541 /* Get the HW capability (new GMAC newer than 3.50a) */ 6542 priv->hw_cap_support = stmmac_get_hw_features(priv); 6543 if (priv->hw_cap_support) { 6544 dev_info(priv->device, "DMA HW capability register supported\n"); 6545 6546 /* We can override some gmac/dma configuration fields: e.g. 6547 * enh_desc, tx_coe (e.g. that are passed through the 6548 * platform) with the values from the HW capability 6549 * register (if supported). 6550 */ 6551 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6552 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6553 !priv->plat->use_phy_wol; 6554 priv->hw->pmt = priv->plat->pmt; 6555 if (priv->dma_cap.hash_tb_sz) { 6556 priv->hw->multicast_filter_bins = 6557 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6558 priv->hw->mcast_bits_log2 = 6559 ilog2(priv->hw->multicast_filter_bins); 6560 } 6561 6562 /* TXCOE doesn't work in thresh DMA mode */ 6563 if (priv->plat->force_thresh_dma_mode) 6564 priv->plat->tx_coe = 0; 6565 else 6566 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6567 6568 /* In case of GMAC4 rx_coe is from HW cap register. */ 6569 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6570 6571 if (priv->dma_cap.rx_coe_type2) 6572 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6573 else if (priv->dma_cap.rx_coe_type1) 6574 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6575 6576 } else { 6577 dev_info(priv->device, "No HW DMA feature register supported\n"); 6578 } 6579 6580 if (priv->plat->rx_coe) { 6581 priv->hw->rx_csum = priv->plat->rx_coe; 6582 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6583 if (priv->synopsys_id < DWMAC_CORE_4_00) 6584 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6585 } 6586 if (priv->plat->tx_coe) 6587 dev_info(priv->device, "TX Checksum insertion supported\n"); 6588 6589 if (priv->plat->pmt) { 6590 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6591 device_set_wakeup_capable(priv->device, 1); 6592 } 6593 6594 if (priv->dma_cap.tsoen) 6595 dev_info(priv->device, "TSO supported\n"); 6596 6597 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6598 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6599 6600 /* Run HW quirks, if any */ 6601 if (priv->hwif_quirks) { 6602 ret = priv->hwif_quirks(priv); 6603 if (ret) 6604 return ret; 6605 } 6606 6607 /* Rx Watchdog is available in the COREs newer than the 3.40. 6608 * In some case, for example on bugged HW this feature 6609 * has to be disable and this can be done by passing the 6610 * riwt_off field from the platform. 6611 */ 6612 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6613 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6614 priv->use_riwt = 1; 6615 dev_info(priv->device, 6616 "Enable RX Mitigation via HW Watchdog Timer\n"); 6617 } 6618 6619 return 0; 6620 } 6621 6622 static void stmmac_napi_add(struct net_device *dev) 6623 { 6624 struct stmmac_priv *priv = netdev_priv(dev); 6625 u32 queue, maxq; 6626 6627 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6628 6629 for (queue = 0; queue < maxq; queue++) { 6630 struct stmmac_channel *ch = &priv->channel[queue]; 6631 6632 ch->priv_data = priv; 6633 ch->index = queue; 6634 spin_lock_init(&ch->lock); 6635 6636 if (queue < priv->plat->rx_queues_to_use) { 6637 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6638 NAPI_POLL_WEIGHT); 6639 } 6640 if (queue < priv->plat->tx_queues_to_use) { 6641 netif_tx_napi_add(dev, &ch->tx_napi, 6642 stmmac_napi_poll_tx, 6643 NAPI_POLL_WEIGHT); 6644 } 6645 if (queue < priv->plat->rx_queues_to_use && 6646 queue < priv->plat->tx_queues_to_use) { 6647 netif_napi_add(dev, &ch->rxtx_napi, 6648 stmmac_napi_poll_rxtx, 6649 NAPI_POLL_WEIGHT); 6650 } 6651 } 6652 } 6653 6654 static void stmmac_napi_del(struct net_device *dev) 6655 { 6656 struct stmmac_priv *priv = netdev_priv(dev); 6657 u32 queue, maxq; 6658 6659 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6660 6661 for (queue = 0; queue < maxq; queue++) { 6662 struct stmmac_channel *ch = &priv->channel[queue]; 6663 6664 if (queue < priv->plat->rx_queues_to_use) 6665 netif_napi_del(&ch->rx_napi); 6666 if (queue < priv->plat->tx_queues_to_use) 6667 netif_napi_del(&ch->tx_napi); 6668 if (queue < priv->plat->rx_queues_to_use && 6669 queue < priv->plat->tx_queues_to_use) { 6670 netif_napi_del(&ch->rxtx_napi); 6671 } 6672 } 6673 } 6674 6675 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6676 { 6677 struct stmmac_priv *priv = netdev_priv(dev); 6678 int ret = 0; 6679 6680 if (netif_running(dev)) 6681 stmmac_release(dev); 6682 6683 stmmac_napi_del(dev); 6684 6685 priv->plat->rx_queues_to_use = rx_cnt; 6686 priv->plat->tx_queues_to_use = tx_cnt; 6687 6688 stmmac_napi_add(dev); 6689 6690 if (netif_running(dev)) 6691 ret = stmmac_open(dev); 6692 6693 return ret; 6694 } 6695 6696 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6697 { 6698 struct stmmac_priv *priv = netdev_priv(dev); 6699 int ret = 0; 6700 6701 if (netif_running(dev)) 6702 stmmac_release(dev); 6703 6704 priv->dma_rx_size = rx_size; 6705 priv->dma_tx_size = tx_size; 6706 6707 if (netif_running(dev)) 6708 ret = stmmac_open(dev); 6709 6710 return ret; 6711 } 6712 6713 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6714 static void stmmac_fpe_lp_task(struct work_struct *work) 6715 { 6716 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6717 fpe_task); 6718 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6719 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6720 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6721 bool *hs_enable = &fpe_cfg->hs_enable; 6722 bool *enable = &fpe_cfg->enable; 6723 int retries = 20; 6724 6725 while (retries-- > 0) { 6726 /* Bail out immediately if FPE handshake is OFF */ 6727 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6728 break; 6729 6730 if (*lo_state == FPE_STATE_ENTERING_ON && 6731 *lp_state == FPE_STATE_ENTERING_ON) { 6732 stmmac_fpe_configure(priv, priv->ioaddr, 6733 priv->plat->tx_queues_to_use, 6734 priv->plat->rx_queues_to_use, 6735 *enable); 6736 6737 netdev_info(priv->dev, "configured FPE\n"); 6738 6739 *lo_state = FPE_STATE_ON; 6740 *lp_state = FPE_STATE_ON; 6741 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6742 break; 6743 } 6744 6745 if ((*lo_state == FPE_STATE_CAPABLE || 6746 *lo_state == FPE_STATE_ENTERING_ON) && 6747 *lp_state != FPE_STATE_ON) { 6748 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6749 *lo_state, *lp_state); 6750 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6751 MPACKET_VERIFY); 6752 } 6753 /* Sleep then retry */ 6754 msleep(500); 6755 } 6756 6757 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6758 } 6759 6760 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 6761 { 6762 if (priv->plat->fpe_cfg->hs_enable != enable) { 6763 if (enable) { 6764 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6765 MPACKET_VERIFY); 6766 } else { 6767 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 6768 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 6769 } 6770 6771 priv->plat->fpe_cfg->hs_enable = enable; 6772 } 6773 } 6774 6775 /** 6776 * stmmac_dvr_probe 6777 * @device: device pointer 6778 * @plat_dat: platform data pointer 6779 * @res: stmmac resource pointer 6780 * Description: this is the main probe function used to 6781 * call the alloc_etherdev, allocate the priv structure. 6782 * Return: 6783 * returns 0 on success, otherwise errno. 6784 */ 6785 int stmmac_dvr_probe(struct device *device, 6786 struct plat_stmmacenet_data *plat_dat, 6787 struct stmmac_resources *res) 6788 { 6789 struct net_device *ndev = NULL; 6790 struct stmmac_priv *priv; 6791 u32 rxq; 6792 int i, ret = 0; 6793 6794 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 6795 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 6796 if (!ndev) 6797 return -ENOMEM; 6798 6799 SET_NETDEV_DEV(ndev, device); 6800 6801 priv = netdev_priv(ndev); 6802 priv->device = device; 6803 priv->dev = ndev; 6804 6805 stmmac_set_ethtool_ops(ndev); 6806 priv->pause = pause; 6807 priv->plat = plat_dat; 6808 priv->ioaddr = res->addr; 6809 priv->dev->base_addr = (unsigned long)res->addr; 6810 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 6811 6812 priv->dev->irq = res->irq; 6813 priv->wol_irq = res->wol_irq; 6814 priv->lpi_irq = res->lpi_irq; 6815 priv->sfty_ce_irq = res->sfty_ce_irq; 6816 priv->sfty_ue_irq = res->sfty_ue_irq; 6817 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 6818 priv->rx_irq[i] = res->rx_irq[i]; 6819 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 6820 priv->tx_irq[i] = res->tx_irq[i]; 6821 6822 if (!is_zero_ether_addr(res->mac)) 6823 eth_hw_addr_set(priv->dev, res->mac); 6824 6825 dev_set_drvdata(device, priv->dev); 6826 6827 /* Verify driver arguments */ 6828 stmmac_verify_args(); 6829 6830 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 6831 if (!priv->af_xdp_zc_qps) 6832 return -ENOMEM; 6833 6834 /* Allocate workqueue */ 6835 priv->wq = create_singlethread_workqueue("stmmac_wq"); 6836 if (!priv->wq) { 6837 dev_err(priv->device, "failed to create workqueue\n"); 6838 return -ENOMEM; 6839 } 6840 6841 INIT_WORK(&priv->service_task, stmmac_service_task); 6842 6843 /* Initialize Link Partner FPE workqueue */ 6844 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 6845 6846 /* Override with kernel parameters if supplied XXX CRS XXX 6847 * this needs to have multiple instances 6848 */ 6849 if ((phyaddr >= 0) && (phyaddr <= 31)) 6850 priv->plat->phy_addr = phyaddr; 6851 6852 if (priv->plat->stmmac_rst) { 6853 ret = reset_control_assert(priv->plat->stmmac_rst); 6854 reset_control_deassert(priv->plat->stmmac_rst); 6855 /* Some reset controllers have only reset callback instead of 6856 * assert + deassert callbacks pair. 6857 */ 6858 if (ret == -ENOTSUPP) 6859 reset_control_reset(priv->plat->stmmac_rst); 6860 } 6861 6862 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 6863 if (ret == -ENOTSUPP) 6864 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 6865 ERR_PTR(ret)); 6866 6867 /* Init MAC and get the capabilities */ 6868 ret = stmmac_hw_init(priv); 6869 if (ret) 6870 goto error_hw_init; 6871 6872 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 6873 */ 6874 if (priv->synopsys_id < DWMAC_CORE_5_20) 6875 priv->plat->dma_cfg->dche = false; 6876 6877 stmmac_check_ether_addr(priv); 6878 6879 ndev->netdev_ops = &stmmac_netdev_ops; 6880 6881 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6882 NETIF_F_RXCSUM; 6883 6884 ret = stmmac_tc_init(priv, priv); 6885 if (!ret) { 6886 ndev->hw_features |= NETIF_F_HW_TC; 6887 } 6888 6889 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 6890 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 6891 if (priv->plat->has_gmac4) 6892 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 6893 priv->tso = true; 6894 dev_info(priv->device, "TSO feature enabled\n"); 6895 } 6896 6897 if (priv->dma_cap.sphen) { 6898 ndev->hw_features |= NETIF_F_GRO; 6899 priv->sph_cap = true; 6900 priv->sph = priv->sph_cap; 6901 dev_info(priv->device, "SPH feature enabled\n"); 6902 } 6903 6904 /* The current IP register MAC_HW_Feature1[ADDR64] only define 6905 * 32/40/64 bit width, but some SOC support others like i.MX8MP 6906 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 6907 * So overwrite dma_cap.addr64 according to HW real design. 6908 */ 6909 if (priv->plat->addr64) 6910 priv->dma_cap.addr64 = priv->plat->addr64; 6911 6912 if (priv->dma_cap.addr64) { 6913 ret = dma_set_mask_and_coherent(device, 6914 DMA_BIT_MASK(priv->dma_cap.addr64)); 6915 if (!ret) { 6916 dev_info(priv->device, "Using %d bits DMA width\n", 6917 priv->dma_cap.addr64); 6918 6919 /* 6920 * If more than 32 bits can be addressed, make sure to 6921 * enable enhanced addressing mode. 6922 */ 6923 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 6924 priv->plat->dma_cfg->eame = true; 6925 } else { 6926 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 6927 if (ret) { 6928 dev_err(priv->device, "Failed to set DMA Mask\n"); 6929 goto error_hw_init; 6930 } 6931 6932 priv->dma_cap.addr64 = 32; 6933 } 6934 } 6935 6936 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 6937 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 6938 #ifdef STMMAC_VLAN_TAG_USED 6939 /* Both mac100 and gmac support receive VLAN tag detection */ 6940 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 6941 if (priv->dma_cap.vlhash) { 6942 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6943 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 6944 } 6945 if (priv->dma_cap.vlins) { 6946 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 6947 if (priv->dma_cap.dvlan) 6948 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 6949 } 6950 #endif 6951 priv->msg_enable = netif_msg_init(debug, default_msg_level); 6952 6953 /* Initialize RSS */ 6954 rxq = priv->plat->rx_queues_to_use; 6955 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 6956 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 6957 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 6958 6959 if (priv->dma_cap.rssen && priv->plat->rss_en) 6960 ndev->features |= NETIF_F_RXHASH; 6961 6962 /* MTU range: 46 - hw-specific max */ 6963 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 6964 if (priv->plat->has_xgmac) 6965 ndev->max_mtu = XGMAC_JUMBO_LEN; 6966 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 6967 ndev->max_mtu = JUMBO_LEN; 6968 else 6969 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 6970 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 6971 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 6972 */ 6973 if ((priv->plat->maxmtu < ndev->max_mtu) && 6974 (priv->plat->maxmtu >= ndev->min_mtu)) 6975 ndev->max_mtu = priv->plat->maxmtu; 6976 else if (priv->plat->maxmtu < ndev->min_mtu) 6977 dev_warn(priv->device, 6978 "%s: warning: maxmtu having invalid value (%d)\n", 6979 __func__, priv->plat->maxmtu); 6980 6981 if (flow_ctrl) 6982 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 6983 6984 /* Setup channels NAPI */ 6985 stmmac_napi_add(ndev); 6986 6987 mutex_init(&priv->lock); 6988 6989 /* If a specific clk_csr value is passed from the platform 6990 * this means that the CSR Clock Range selection cannot be 6991 * changed at run-time and it is fixed. Viceversa the driver'll try to 6992 * set the MDC clock dynamically according to the csr actual 6993 * clock input. 6994 */ 6995 if (priv->plat->clk_csr >= 0) 6996 priv->clk_csr = priv->plat->clk_csr; 6997 else 6998 stmmac_clk_csr_set(priv); 6999 7000 stmmac_check_pcs_mode(priv); 7001 7002 pm_runtime_get_noresume(device); 7003 pm_runtime_set_active(device); 7004 pm_runtime_enable(device); 7005 7006 if (priv->hw->pcs != STMMAC_PCS_TBI && 7007 priv->hw->pcs != STMMAC_PCS_RTBI) { 7008 /* MDIO bus Registration */ 7009 ret = stmmac_mdio_register(ndev); 7010 if (ret < 0) { 7011 dev_err(priv->device, 7012 "%s: MDIO bus (id: %d) registration failed", 7013 __func__, priv->plat->bus_id); 7014 goto error_mdio_register; 7015 } 7016 } 7017 7018 if (priv->plat->speed_mode_2500) 7019 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7020 7021 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7022 ret = stmmac_xpcs_setup(priv->mii); 7023 if (ret) 7024 goto error_xpcs_setup; 7025 } 7026 7027 ret = stmmac_phy_setup(priv); 7028 if (ret) { 7029 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7030 goto error_phy_setup; 7031 } 7032 7033 ret = register_netdev(ndev); 7034 if (ret) { 7035 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7036 __func__, ret); 7037 goto error_netdev_register; 7038 } 7039 7040 if (priv->plat->serdes_powerup) { 7041 ret = priv->plat->serdes_powerup(ndev, 7042 priv->plat->bsp_priv); 7043 7044 if (ret < 0) 7045 goto error_serdes_powerup; 7046 } 7047 7048 #ifdef CONFIG_DEBUG_FS 7049 stmmac_init_fs(ndev); 7050 #endif 7051 7052 /* Let pm_runtime_put() disable the clocks. 7053 * If CONFIG_PM is not enabled, the clocks will stay powered. 7054 */ 7055 pm_runtime_put(device); 7056 7057 return ret; 7058 7059 error_serdes_powerup: 7060 unregister_netdev(ndev); 7061 error_netdev_register: 7062 phylink_destroy(priv->phylink); 7063 error_xpcs_setup: 7064 error_phy_setup: 7065 if (priv->hw->pcs != STMMAC_PCS_TBI && 7066 priv->hw->pcs != STMMAC_PCS_RTBI) 7067 stmmac_mdio_unregister(ndev); 7068 error_mdio_register: 7069 stmmac_napi_del(ndev); 7070 error_hw_init: 7071 destroy_workqueue(priv->wq); 7072 bitmap_free(priv->af_xdp_zc_qps); 7073 7074 return ret; 7075 } 7076 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7077 7078 /** 7079 * stmmac_dvr_remove 7080 * @dev: device pointer 7081 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7082 * changes the link status, releases the DMA descriptor rings. 7083 */ 7084 int stmmac_dvr_remove(struct device *dev) 7085 { 7086 struct net_device *ndev = dev_get_drvdata(dev); 7087 struct stmmac_priv *priv = netdev_priv(ndev); 7088 7089 netdev_info(priv->dev, "%s: removing driver", __func__); 7090 7091 stmmac_stop_all_dma(priv); 7092 stmmac_mac_set(priv, priv->ioaddr, false); 7093 netif_carrier_off(ndev); 7094 unregister_netdev(ndev); 7095 7096 /* Serdes power down needs to happen after VLAN filter 7097 * is deleted that is triggered by unregister_netdev(). 7098 */ 7099 if (priv->plat->serdes_powerdown) 7100 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7101 7102 #ifdef CONFIG_DEBUG_FS 7103 stmmac_exit_fs(ndev); 7104 #endif 7105 phylink_destroy(priv->phylink); 7106 if (priv->plat->stmmac_rst) 7107 reset_control_assert(priv->plat->stmmac_rst); 7108 reset_control_assert(priv->plat->stmmac_ahb_rst); 7109 pm_runtime_put(dev); 7110 pm_runtime_disable(dev); 7111 if (priv->hw->pcs != STMMAC_PCS_TBI && 7112 priv->hw->pcs != STMMAC_PCS_RTBI) 7113 stmmac_mdio_unregister(ndev); 7114 destroy_workqueue(priv->wq); 7115 mutex_destroy(&priv->lock); 7116 bitmap_free(priv->af_xdp_zc_qps); 7117 7118 return 0; 7119 } 7120 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7121 7122 /** 7123 * stmmac_suspend - suspend callback 7124 * @dev: device pointer 7125 * Description: this is the function to suspend the device and it is called 7126 * by the platform driver to stop the network queue, release the resources, 7127 * program the PMT register (for WoL), clean and release driver resources. 7128 */ 7129 int stmmac_suspend(struct device *dev) 7130 { 7131 struct net_device *ndev = dev_get_drvdata(dev); 7132 struct stmmac_priv *priv = netdev_priv(ndev); 7133 u32 chan; 7134 7135 if (!ndev || !netif_running(ndev)) 7136 return 0; 7137 7138 mutex_lock(&priv->lock); 7139 7140 netif_device_detach(ndev); 7141 7142 stmmac_disable_all_queues(priv); 7143 7144 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7145 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 7146 7147 if (priv->eee_enabled) { 7148 priv->tx_path_in_lpi_mode = false; 7149 del_timer_sync(&priv->eee_ctrl_timer); 7150 } 7151 7152 /* Stop TX/RX DMA */ 7153 stmmac_stop_all_dma(priv); 7154 7155 if (priv->plat->serdes_powerdown) 7156 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7157 7158 /* Enable Power down mode by programming the PMT regs */ 7159 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7160 stmmac_pmt(priv, priv->hw, priv->wolopts); 7161 priv->irq_wake = 1; 7162 } else { 7163 stmmac_mac_set(priv, priv->ioaddr, false); 7164 pinctrl_pm_select_sleep_state(priv->device); 7165 } 7166 7167 mutex_unlock(&priv->lock); 7168 7169 rtnl_lock(); 7170 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7171 phylink_suspend(priv->phylink, true); 7172 } else { 7173 if (device_may_wakeup(priv->device)) 7174 phylink_speed_down(priv->phylink, false); 7175 phylink_suspend(priv->phylink, false); 7176 } 7177 rtnl_unlock(); 7178 7179 if (priv->dma_cap.fpesel) { 7180 /* Disable FPE */ 7181 stmmac_fpe_configure(priv, priv->ioaddr, 7182 priv->plat->tx_queues_to_use, 7183 priv->plat->rx_queues_to_use, false); 7184 7185 stmmac_fpe_handshake(priv, false); 7186 stmmac_fpe_stop_wq(priv); 7187 } 7188 7189 priv->speed = SPEED_UNKNOWN; 7190 return 0; 7191 } 7192 EXPORT_SYMBOL_GPL(stmmac_suspend); 7193 7194 /** 7195 * stmmac_reset_queues_param - reset queue parameters 7196 * @priv: device pointer 7197 */ 7198 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7199 { 7200 u32 rx_cnt = priv->plat->rx_queues_to_use; 7201 u32 tx_cnt = priv->plat->tx_queues_to_use; 7202 u32 queue; 7203 7204 for (queue = 0; queue < rx_cnt; queue++) { 7205 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 7206 7207 rx_q->cur_rx = 0; 7208 rx_q->dirty_rx = 0; 7209 } 7210 7211 for (queue = 0; queue < tx_cnt; queue++) { 7212 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 7213 7214 tx_q->cur_tx = 0; 7215 tx_q->dirty_tx = 0; 7216 tx_q->mss = 0; 7217 7218 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7219 } 7220 } 7221 7222 /** 7223 * stmmac_resume - resume callback 7224 * @dev: device pointer 7225 * Description: when resume this function is invoked to setup the DMA and CORE 7226 * in a usable state. 7227 */ 7228 int stmmac_resume(struct device *dev) 7229 { 7230 struct net_device *ndev = dev_get_drvdata(dev); 7231 struct stmmac_priv *priv = netdev_priv(ndev); 7232 int ret; 7233 7234 if (!netif_running(ndev)) 7235 return 0; 7236 7237 /* Power Down bit, into the PM register, is cleared 7238 * automatically as soon as a magic packet or a Wake-up frame 7239 * is received. Anyway, it's better to manually clear 7240 * this bit because it can generate problems while resuming 7241 * from another devices (e.g. serial console). 7242 */ 7243 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7244 mutex_lock(&priv->lock); 7245 stmmac_pmt(priv, priv->hw, 0); 7246 mutex_unlock(&priv->lock); 7247 priv->irq_wake = 0; 7248 } else { 7249 pinctrl_pm_select_default_state(priv->device); 7250 /* reset the phy so that it's ready */ 7251 if (priv->mii) 7252 stmmac_mdio_reset(priv->mii); 7253 } 7254 7255 if (priv->plat->serdes_powerup) { 7256 ret = priv->plat->serdes_powerup(ndev, 7257 priv->plat->bsp_priv); 7258 7259 if (ret < 0) 7260 return ret; 7261 } 7262 7263 rtnl_lock(); 7264 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7265 phylink_resume(priv->phylink); 7266 } else { 7267 phylink_resume(priv->phylink); 7268 if (device_may_wakeup(priv->device)) 7269 phylink_speed_up(priv->phylink); 7270 } 7271 rtnl_unlock(); 7272 7273 rtnl_lock(); 7274 mutex_lock(&priv->lock); 7275 7276 stmmac_reset_queues_param(priv); 7277 7278 stmmac_free_tx_skbufs(priv); 7279 stmmac_clear_descriptors(priv); 7280 7281 stmmac_hw_setup(ndev, false); 7282 stmmac_init_coalesce(priv); 7283 stmmac_set_rx_mode(ndev); 7284 7285 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7286 7287 stmmac_enable_all_queues(priv); 7288 7289 mutex_unlock(&priv->lock); 7290 rtnl_unlock(); 7291 7292 netif_device_attach(ndev); 7293 7294 return 0; 7295 } 7296 EXPORT_SYMBOL_GPL(stmmac_resume); 7297 7298 #ifndef MODULE 7299 static int __init stmmac_cmdline_opt(char *str) 7300 { 7301 char *opt; 7302 7303 if (!str || !*str) 7304 return -EINVAL; 7305 while ((opt = strsep(&str, ",")) != NULL) { 7306 if (!strncmp(opt, "debug:", 6)) { 7307 if (kstrtoint(opt + 6, 0, &debug)) 7308 goto err; 7309 } else if (!strncmp(opt, "phyaddr:", 8)) { 7310 if (kstrtoint(opt + 8, 0, &phyaddr)) 7311 goto err; 7312 } else if (!strncmp(opt, "buf_sz:", 7)) { 7313 if (kstrtoint(opt + 7, 0, &buf_sz)) 7314 goto err; 7315 } else if (!strncmp(opt, "tc:", 3)) { 7316 if (kstrtoint(opt + 3, 0, &tc)) 7317 goto err; 7318 } else if (!strncmp(opt, "watchdog:", 9)) { 7319 if (kstrtoint(opt + 9, 0, &watchdog)) 7320 goto err; 7321 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7322 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7323 goto err; 7324 } else if (!strncmp(opt, "pause:", 6)) { 7325 if (kstrtoint(opt + 6, 0, &pause)) 7326 goto err; 7327 } else if (!strncmp(opt, "eee_timer:", 10)) { 7328 if (kstrtoint(opt + 10, 0, &eee_timer)) 7329 goto err; 7330 } else if (!strncmp(opt, "chain_mode:", 11)) { 7331 if (kstrtoint(opt + 11, 0, &chain_mode)) 7332 goto err; 7333 } 7334 } 7335 return 0; 7336 7337 err: 7338 pr_err("%s: ERROR broken module parameter conversion", __func__); 7339 return -EINVAL; 7340 } 7341 7342 __setup("stmmaceth=", stmmac_cmdline_opt); 7343 #endif /* MODULE */ 7344 7345 static int __init stmmac_init(void) 7346 { 7347 #ifdef CONFIG_DEBUG_FS 7348 /* Create debugfs main directory if it doesn't exist yet */ 7349 if (!stmmac_fs_dir) 7350 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7351 register_netdevice_notifier(&stmmac_notifier); 7352 #endif 7353 7354 return 0; 7355 } 7356 7357 static void __exit stmmac_exit(void) 7358 { 7359 #ifdef CONFIG_DEBUG_FS 7360 unregister_netdevice_notifier(&stmmac_notifier); 7361 debugfs_remove_recursive(stmmac_fs_dir); 7362 #endif 7363 } 7364 7365 module_init(stmmac_init) 7366 module_exit(stmmac_exit) 7367 7368 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7369 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7370 MODULE_LICENSE("GPL"); 7371