1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 57 58 /* Module parameters */ 59 #define TX_TIMEO 5000 60 static int watchdog = TX_TIMEO; 61 module_param(watchdog, int, S_IRUGO | S_IWUSR); 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 63 64 static int debug = -1; 65 module_param(debug, int, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 67 68 static int phyaddr = -1; 69 module_param(phyaddr, int, S_IRUGO); 70 MODULE_PARM_DESC(phyaddr, "Physical device address"); 71 72 #define DMA_TX_SIZE 256 73 static int dma_txsize = DMA_TX_SIZE; 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 76 77 #define DMA_RX_SIZE 256 78 static int dma_rxsize = DMA_RX_SIZE; 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 81 82 static int flow_ctrl = FLOW_OFF; 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 85 86 static int pause = PAUSE_TIME; 87 module_param(pause, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 89 90 #define TC_DEFAULT 64 91 static int tc = TC_DEFAULT; 92 module_param(tc, int, S_IRUGO | S_IWUSR); 93 MODULE_PARM_DESC(tc, "DMA threshold control value"); 94 95 #define DEFAULT_BUFSIZE 1536 96 static int buf_sz = DEFAULT_BUFSIZE; 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 99 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 101 NETIF_MSG_LINK | NETIF_MSG_IFUP | 102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 103 104 #define STMMAC_DEFAULT_LPI_TIMER 1000 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 109 110 /* By default the driver will use the ring mode to manage tx and rx descriptors 111 * but passing this value so user can force to use the chain instead of the ring 112 */ 113 static unsigned int chain_mode; 114 module_param(chain_mode, int, S_IRUGO); 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 116 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 118 119 #ifdef CONFIG_DEBUG_FS 120 static int stmmac_init_fs(struct net_device *dev); 121 static void stmmac_exit_fs(void); 122 #endif 123 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 125 126 /** 127 * stmmac_verify_args - verify the driver parameters. 128 * Description: it checks the driver parameters and set a default in case of 129 * errors. 130 */ 131 static void stmmac_verify_args(void) 132 { 133 if (unlikely(watchdog < 0)) 134 watchdog = TX_TIMEO; 135 if (unlikely(dma_rxsize < 0)) 136 dma_rxsize = DMA_RX_SIZE; 137 if (unlikely(dma_txsize < 0)) 138 dma_txsize = DMA_TX_SIZE; 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 140 buf_sz = DEFAULT_BUFSIZE; 141 if (unlikely(flow_ctrl > 1)) 142 flow_ctrl = FLOW_AUTO; 143 else if (likely(flow_ctrl < 0)) 144 flow_ctrl = FLOW_OFF; 145 if (unlikely((pause < 0) || (pause > 0xffff))) 146 pause = PAUSE_TIME; 147 if (eee_timer < 0) 148 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 149 } 150 151 /** 152 * stmmac_clk_csr_set - dynamically set the MDC clock 153 * @priv: driver private structure 154 * Description: this is to dynamically set the MDC clock according to the csr 155 * clock input. 156 * Note: 157 * If a specific clk_csr value is passed from the platform 158 * this means that the CSR Clock Range selection cannot be 159 * changed at run-time and it is fixed (as reported in the driver 160 * documentation). Viceversa the driver will try to set the MDC 161 * clock dynamically according to the actual clock input. 162 */ 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 164 { 165 u32 clk_rate; 166 167 clk_rate = clk_get_rate(priv->stmmac_clk); 168 169 /* Platform provided default clk_csr would be assumed valid 170 * for all other cases except for the below mentioned ones. 171 * For values higher than the IEEE 802.3 specified frequency 172 * we can not estimate the proper divider as it is not known 173 * the frequency of clk_csr_i. So we do not change the default 174 * divider. 175 */ 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 177 if (clk_rate < CSR_F_35M) 178 priv->clk_csr = STMMAC_CSR_20_35M; 179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 180 priv->clk_csr = STMMAC_CSR_35_60M; 181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 182 priv->clk_csr = STMMAC_CSR_60_100M; 183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 184 priv->clk_csr = STMMAC_CSR_100_150M; 185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 186 priv->clk_csr = STMMAC_CSR_150_250M; 187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 188 priv->clk_csr = STMMAC_CSR_250_300M; 189 } 190 } 191 192 static void print_pkt(unsigned char *buf, int len) 193 { 194 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 195 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 196 } 197 198 /* minimum number of free TX descriptors required to wake up TX process */ 199 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 200 201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 202 { 203 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 204 } 205 206 /** 207 * stmmac_hw_fix_mac_speed - callback for speed selection 208 * @priv: driver private structure 209 * Description: on some platforms (e.g. ST), some HW system configuraton 210 * registers have to be set according to the link speed negotiated. 211 */ 212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 213 { 214 struct phy_device *phydev = priv->phydev; 215 216 if (likely(priv->plat->fix_mac_speed)) 217 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 218 } 219 220 /** 221 * stmmac_enable_eee_mode - check and enter in LPI mode 222 * @priv: driver private structure 223 * Description: this function is to verify and enter in LPI mode in case of 224 * EEE. 225 */ 226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 227 { 228 /* Check and enter in LPI mode */ 229 if ((priv->dirty_tx == priv->cur_tx) && 230 (priv->tx_path_in_lpi_mode == false)) 231 priv->hw->mac->set_eee_mode(priv->hw); 232 } 233 234 /** 235 * stmmac_disable_eee_mode - disable and exit from LPI mode 236 * @priv: driver private structure 237 * Description: this function is to exit and disable EEE in case of 238 * LPI state is true. This is called by the xmit. 239 */ 240 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 241 { 242 priv->hw->mac->reset_eee_mode(priv->hw); 243 del_timer_sync(&priv->eee_ctrl_timer); 244 priv->tx_path_in_lpi_mode = false; 245 } 246 247 /** 248 * stmmac_eee_ctrl_timer - EEE TX SW timer. 249 * @arg : data hook 250 * Description: 251 * if there is no data transfer and if we are not in LPI state, 252 * then MAC Transmitter can be moved to LPI state. 253 */ 254 static void stmmac_eee_ctrl_timer(unsigned long arg) 255 { 256 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 257 258 stmmac_enable_eee_mode(priv); 259 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 260 } 261 262 /** 263 * stmmac_eee_init - init EEE 264 * @priv: driver private structure 265 * Description: 266 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 267 * can also manage EEE, this function enable the LPI state and start related 268 * timer. 269 */ 270 bool stmmac_eee_init(struct stmmac_priv *priv) 271 { 272 char *phy_bus_name = priv->plat->phy_bus_name; 273 unsigned long flags; 274 bool ret = false; 275 276 /* Using PCS we cannot dial with the phy registers at this stage 277 * so we do not support extra feature like EEE. 278 */ 279 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 280 (priv->pcs == STMMAC_PCS_RTBI)) 281 goto out; 282 283 /* Never init EEE in case of a switch is attached */ 284 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) 285 goto out; 286 287 /* MAC core supports the EEE feature. */ 288 if (priv->dma_cap.eee) { 289 int tx_lpi_timer = priv->tx_lpi_timer; 290 291 /* Check if the PHY supports EEE */ 292 if (phy_init_eee(priv->phydev, 1)) { 293 /* To manage at run-time if the EEE cannot be supported 294 * anymore (for example because the lp caps have been 295 * changed). 296 * In that case the driver disable own timers. 297 */ 298 spin_lock_irqsave(&priv->lock, flags); 299 if (priv->eee_active) { 300 pr_debug("stmmac: disable EEE\n"); 301 del_timer_sync(&priv->eee_ctrl_timer); 302 priv->hw->mac->set_eee_timer(priv->hw, 0, 303 tx_lpi_timer); 304 } 305 priv->eee_active = 0; 306 spin_unlock_irqrestore(&priv->lock, flags); 307 goto out; 308 } 309 /* Activate the EEE and start timers */ 310 spin_lock_irqsave(&priv->lock, flags); 311 if (!priv->eee_active) { 312 priv->eee_active = 1; 313 init_timer(&priv->eee_ctrl_timer); 314 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 315 priv->eee_ctrl_timer.data = (unsigned long)priv; 316 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 317 add_timer(&priv->eee_ctrl_timer); 318 319 priv->hw->mac->set_eee_timer(priv->hw, 320 STMMAC_DEFAULT_LIT_LS, 321 tx_lpi_timer); 322 } 323 /* Set HW EEE according to the speed */ 324 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); 325 326 ret = true; 327 spin_unlock_irqrestore(&priv->lock, flags); 328 329 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 330 } 331 out: 332 return ret; 333 } 334 335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 336 * @priv: driver private structure 337 * @entry : descriptor index to be used. 338 * @skb : the socket buffer 339 * Description : 340 * This function will read timestamp from the descriptor & pass it to stack. 341 * and also perform some sanity checks. 342 */ 343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 344 unsigned int entry, struct sk_buff *skb) 345 { 346 struct skb_shared_hwtstamps shhwtstamp; 347 u64 ns; 348 void *desc = NULL; 349 350 if (!priv->hwts_tx_en) 351 return; 352 353 /* exit if skb doesn't support hw tstamp */ 354 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 355 return; 356 357 if (priv->adv_ts) 358 desc = (priv->dma_etx + entry); 359 else 360 desc = (priv->dma_tx + entry); 361 362 /* check tx tstamp status */ 363 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 364 return; 365 366 /* get the valid tstamp */ 367 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 368 369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 370 shhwtstamp.hwtstamp = ns_to_ktime(ns); 371 /* pass tstamp to stack */ 372 skb_tstamp_tx(skb, &shhwtstamp); 373 374 return; 375 } 376 377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 378 * @priv: driver private structure 379 * @entry : descriptor index to be used. 380 * @skb : the socket buffer 381 * Description : 382 * This function will read received packet's timestamp from the descriptor 383 * and pass it to stack. It also perform some sanity checks. 384 */ 385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 386 unsigned int entry, struct sk_buff *skb) 387 { 388 struct skb_shared_hwtstamps *shhwtstamp = NULL; 389 u64 ns; 390 void *desc = NULL; 391 392 if (!priv->hwts_rx_en) 393 return; 394 395 if (priv->adv_ts) 396 desc = (priv->dma_erx + entry); 397 else 398 desc = (priv->dma_rx + entry); 399 400 /* exit if rx tstamp is not valid */ 401 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 402 return; 403 404 /* get valid tstamp */ 405 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 406 shhwtstamp = skb_hwtstamps(skb); 407 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 408 shhwtstamp->hwtstamp = ns_to_ktime(ns); 409 } 410 411 /** 412 * stmmac_hwtstamp_ioctl - control hardware timestamping. 413 * @dev: device pointer. 414 * @ifr: An IOCTL specefic structure, that can contain a pointer to 415 * a proprietary structure used to pass information to the driver. 416 * Description: 417 * This function configures the MAC to enable/disable both outgoing(TX) 418 * and incoming(RX) packets time stamping based on user input. 419 * Return Value: 420 * 0 on success and an appropriate -ve integer on failure. 421 */ 422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 423 { 424 struct stmmac_priv *priv = netdev_priv(dev); 425 struct hwtstamp_config config; 426 struct timespec now; 427 u64 temp = 0; 428 u32 ptp_v2 = 0; 429 u32 tstamp_all = 0; 430 u32 ptp_over_ipv4_udp = 0; 431 u32 ptp_over_ipv6_udp = 0; 432 u32 ptp_over_ethernet = 0; 433 u32 snap_type_sel = 0; 434 u32 ts_master_en = 0; 435 u32 ts_event_en = 0; 436 u32 value = 0; 437 438 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 439 netdev_alert(priv->dev, "No support for HW time stamping\n"); 440 priv->hwts_tx_en = 0; 441 priv->hwts_rx_en = 0; 442 443 return -EOPNOTSUPP; 444 } 445 446 if (copy_from_user(&config, ifr->ifr_data, 447 sizeof(struct hwtstamp_config))) 448 return -EFAULT; 449 450 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 451 __func__, config.flags, config.tx_type, config.rx_filter); 452 453 /* reserved for future extensions */ 454 if (config.flags) 455 return -EINVAL; 456 457 if (config.tx_type != HWTSTAMP_TX_OFF && 458 config.tx_type != HWTSTAMP_TX_ON) 459 return -ERANGE; 460 461 if (priv->adv_ts) { 462 switch (config.rx_filter) { 463 case HWTSTAMP_FILTER_NONE: 464 /* time stamp no incoming packet at all */ 465 config.rx_filter = HWTSTAMP_FILTER_NONE; 466 break; 467 468 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 469 /* PTP v1, UDP, any kind of event packet */ 470 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 471 /* take time stamp for all event messages */ 472 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 473 474 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 475 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 476 break; 477 478 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 479 /* PTP v1, UDP, Sync packet */ 480 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 481 /* take time stamp for SYNC messages only */ 482 ts_event_en = PTP_TCR_TSEVNTENA; 483 484 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 485 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 486 break; 487 488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 489 /* PTP v1, UDP, Delay_req packet */ 490 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 491 /* take time stamp for Delay_Req messages only */ 492 ts_master_en = PTP_TCR_TSMSTRENA; 493 ts_event_en = PTP_TCR_TSEVNTENA; 494 495 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 496 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 497 break; 498 499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 500 /* PTP v2, UDP, any kind of event packet */ 501 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 502 ptp_v2 = PTP_TCR_TSVER2ENA; 503 /* take time stamp for all event messages */ 504 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 505 506 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 507 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 508 break; 509 510 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 511 /* PTP v2, UDP, Sync packet */ 512 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 513 ptp_v2 = PTP_TCR_TSVER2ENA; 514 /* take time stamp for SYNC messages only */ 515 ts_event_en = PTP_TCR_TSEVNTENA; 516 517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 519 break; 520 521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 522 /* PTP v2, UDP, Delay_req packet */ 523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 524 ptp_v2 = PTP_TCR_TSVER2ENA; 525 /* take time stamp for Delay_Req messages only */ 526 ts_master_en = PTP_TCR_TSMSTRENA; 527 ts_event_en = PTP_TCR_TSEVNTENA; 528 529 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 530 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 531 break; 532 533 case HWTSTAMP_FILTER_PTP_V2_EVENT: 534 /* PTP v2/802.AS1 any layer, any kind of event packet */ 535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 536 ptp_v2 = PTP_TCR_TSVER2ENA; 537 /* take time stamp for all event messages */ 538 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 539 540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 542 ptp_over_ethernet = PTP_TCR_TSIPENA; 543 break; 544 545 case HWTSTAMP_FILTER_PTP_V2_SYNC: 546 /* PTP v2/802.AS1, any layer, Sync packet */ 547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 548 ptp_v2 = PTP_TCR_TSVER2ENA; 549 /* take time stamp for SYNC messages only */ 550 ts_event_en = PTP_TCR_TSEVNTENA; 551 552 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 553 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 554 ptp_over_ethernet = PTP_TCR_TSIPENA; 555 break; 556 557 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 558 /* PTP v2/802.AS1, any layer, Delay_req packet */ 559 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 560 ptp_v2 = PTP_TCR_TSVER2ENA; 561 /* take time stamp for Delay_Req messages only */ 562 ts_master_en = PTP_TCR_TSMSTRENA; 563 ts_event_en = PTP_TCR_TSEVNTENA; 564 565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 567 ptp_over_ethernet = PTP_TCR_TSIPENA; 568 break; 569 570 case HWTSTAMP_FILTER_ALL: 571 /* time stamp any incoming packet */ 572 config.rx_filter = HWTSTAMP_FILTER_ALL; 573 tstamp_all = PTP_TCR_TSENALL; 574 break; 575 576 default: 577 return -ERANGE; 578 } 579 } else { 580 switch (config.rx_filter) { 581 case HWTSTAMP_FILTER_NONE: 582 config.rx_filter = HWTSTAMP_FILTER_NONE; 583 break; 584 default: 585 /* PTP v1, UDP, any kind of event packet */ 586 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 587 break; 588 } 589 } 590 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 591 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 592 593 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 594 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 595 else { 596 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 597 tstamp_all | ptp_v2 | ptp_over_ethernet | 598 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 599 ts_master_en | snap_type_sel); 600 601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 602 603 /* program Sub Second Increment reg */ 604 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 605 606 /* calculate default added value: 607 * formula is : 608 * addend = (2^32)/freq_div_ratio; 609 * where, freq_div_ratio = clk_ptp_ref_i/50MHz 610 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; 611 * NOTE: clk_ptp_ref_i should be >= 50MHz to 612 * achive 20ns accuracy. 613 * 614 * 2^x * y == (y << x), hence 615 * 2^32 * 50000000 ==> (50000000 << 32) 616 */ 617 temp = (u64) (50000000ULL << 32); 618 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 619 priv->hw->ptp->config_addend(priv->ioaddr, 620 priv->default_addend); 621 622 /* initialize system time */ 623 getnstimeofday(&now); 624 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 625 now.tv_nsec); 626 } 627 628 return copy_to_user(ifr->ifr_data, &config, 629 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 630 } 631 632 /** 633 * stmmac_init_ptp - init PTP 634 * @priv: driver private structure 635 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 636 * This is done by looking at the HW cap. register. 637 * This function also registers the ptp driver. 638 */ 639 static int stmmac_init_ptp(struct stmmac_priv *priv) 640 { 641 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 642 return -EOPNOTSUPP; 643 644 /* Fall-back to main clock in case of no PTP ref is passed */ 645 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 646 if (IS_ERR(priv->clk_ptp_ref)) { 647 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 648 priv->clk_ptp_ref = NULL; 649 } else { 650 clk_prepare_enable(priv->clk_ptp_ref); 651 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 652 } 653 654 priv->adv_ts = 0; 655 if (priv->dma_cap.atime_stamp && priv->extend_desc) 656 priv->adv_ts = 1; 657 658 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 659 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 660 661 if (netif_msg_hw(priv) && priv->adv_ts) 662 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 663 664 priv->hw->ptp = &stmmac_ptp; 665 priv->hwts_tx_en = 0; 666 priv->hwts_rx_en = 0; 667 668 return stmmac_ptp_register(priv); 669 } 670 671 static void stmmac_release_ptp(struct stmmac_priv *priv) 672 { 673 if (priv->clk_ptp_ref) 674 clk_disable_unprepare(priv->clk_ptp_ref); 675 stmmac_ptp_unregister(priv); 676 } 677 678 /** 679 * stmmac_adjust_link - adjusts the link parameters 680 * @dev: net device structure 681 * Description: this is the helper called by the physical abstraction layer 682 * drivers to communicate the phy link status. According the speed and duplex 683 * this driver can invoke registered glue-logic as well. 684 * It also invoke the eee initialization because it could happen when switch 685 * on different networks (that are eee capable). 686 */ 687 static void stmmac_adjust_link(struct net_device *dev) 688 { 689 struct stmmac_priv *priv = netdev_priv(dev); 690 struct phy_device *phydev = priv->phydev; 691 unsigned long flags; 692 int new_state = 0; 693 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 694 695 if (phydev == NULL) 696 return; 697 698 spin_lock_irqsave(&priv->lock, flags); 699 700 if (phydev->link) { 701 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 702 703 /* Now we make sure that we can be in full duplex mode. 704 * If not, we operate in half-duplex mode. */ 705 if (phydev->duplex != priv->oldduplex) { 706 new_state = 1; 707 if (!(phydev->duplex)) 708 ctrl &= ~priv->hw->link.duplex; 709 else 710 ctrl |= priv->hw->link.duplex; 711 priv->oldduplex = phydev->duplex; 712 } 713 /* Flow Control operation */ 714 if (phydev->pause) 715 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 716 fc, pause_time); 717 718 if (phydev->speed != priv->speed) { 719 new_state = 1; 720 switch (phydev->speed) { 721 case 1000: 722 if (likely(priv->plat->has_gmac)) 723 ctrl &= ~priv->hw->link.port; 724 stmmac_hw_fix_mac_speed(priv); 725 break; 726 case 100: 727 case 10: 728 if (priv->plat->has_gmac) { 729 ctrl |= priv->hw->link.port; 730 if (phydev->speed == SPEED_100) { 731 ctrl |= priv->hw->link.speed; 732 } else { 733 ctrl &= ~(priv->hw->link.speed); 734 } 735 } else { 736 ctrl &= ~priv->hw->link.port; 737 } 738 stmmac_hw_fix_mac_speed(priv); 739 break; 740 default: 741 if (netif_msg_link(priv)) 742 pr_warn("%s: Speed (%d) not 10/100\n", 743 dev->name, phydev->speed); 744 break; 745 } 746 747 priv->speed = phydev->speed; 748 } 749 750 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 751 752 if (!priv->oldlink) { 753 new_state = 1; 754 priv->oldlink = 1; 755 } 756 } else if (priv->oldlink) { 757 new_state = 1; 758 priv->oldlink = 0; 759 priv->speed = 0; 760 priv->oldduplex = -1; 761 } 762 763 if (new_state && netif_msg_link(priv)) 764 phy_print_status(phydev); 765 766 spin_unlock_irqrestore(&priv->lock, flags); 767 768 /* At this stage, it could be needed to setup the EEE or adjust some 769 * MAC related HW registers. 770 */ 771 priv->eee_enabled = stmmac_eee_init(priv); 772 } 773 774 /** 775 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 776 * @priv: driver private structure 777 * Description: this is to verify if the HW supports the PCS. 778 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 779 * configured for the TBI, RTBI, or SGMII PHY interface. 780 */ 781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 782 { 783 int interface = priv->plat->interface; 784 785 if (priv->dma_cap.pcs) { 786 if ((interface == PHY_INTERFACE_MODE_RGMII) || 787 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 788 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 789 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 790 pr_debug("STMMAC: PCS RGMII support enable\n"); 791 priv->pcs = STMMAC_PCS_RGMII; 792 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 793 pr_debug("STMMAC: PCS SGMII support enable\n"); 794 priv->pcs = STMMAC_PCS_SGMII; 795 } 796 } 797 } 798 799 /** 800 * stmmac_init_phy - PHY initialization 801 * @dev: net device structure 802 * Description: it initializes the driver's PHY state, and attaches the PHY 803 * to the mac driver. 804 * Return value: 805 * 0 on success 806 */ 807 static int stmmac_init_phy(struct net_device *dev) 808 { 809 struct stmmac_priv *priv = netdev_priv(dev); 810 struct phy_device *phydev; 811 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 812 char bus_id[MII_BUS_ID_SIZE]; 813 int interface = priv->plat->interface; 814 int max_speed = priv->plat->max_speed; 815 priv->oldlink = 0; 816 priv->speed = 0; 817 priv->oldduplex = -1; 818 819 if (priv->plat->phy_bus_name) 820 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 821 priv->plat->phy_bus_name, priv->plat->bus_id); 822 else 823 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 824 priv->plat->bus_id); 825 826 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 827 priv->plat->phy_addr); 828 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 829 830 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 831 832 if (IS_ERR(phydev)) { 833 pr_err("%s: Could not attach to PHY\n", dev->name); 834 return PTR_ERR(phydev); 835 } 836 837 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 838 if ((interface == PHY_INTERFACE_MODE_MII) || 839 (interface == PHY_INTERFACE_MODE_RMII) || 840 (max_speed < 1000 && max_speed > 0)) 841 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 842 SUPPORTED_1000baseT_Full); 843 844 /* 845 * Broken HW is sometimes missing the pull-up resistor on the 846 * MDIO line, which results in reads to non-existent devices returning 847 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 848 * device as well. 849 * Note: phydev->phy_id is the result of reading the UID PHY registers. 850 */ 851 if (phydev->phy_id == 0) { 852 phy_disconnect(phydev); 853 return -ENODEV; 854 } 855 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 856 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 857 858 priv->phydev = phydev; 859 860 return 0; 861 } 862 863 /** 864 * stmmac_display_ring - display ring 865 * @head: pointer to the head of the ring passed. 866 * @size: size of the ring. 867 * @extend_desc: to verify if extended descriptors are used. 868 * Description: display the control/status and buffer descriptors. 869 */ 870 static void stmmac_display_ring(void *head, int size, int extend_desc) 871 { 872 int i; 873 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 874 struct dma_desc *p = (struct dma_desc *)head; 875 876 for (i = 0; i < size; i++) { 877 u64 x; 878 if (extend_desc) { 879 x = *(u64 *) ep; 880 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 881 i, (unsigned int)virt_to_phys(ep), 882 (unsigned int)x, (unsigned int)(x >> 32), 883 ep->basic.des2, ep->basic.des3); 884 ep++; 885 } else { 886 x = *(u64 *) p; 887 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 888 i, (unsigned int)virt_to_phys(p), 889 (unsigned int)x, (unsigned int)(x >> 32), 890 p->des2, p->des3); 891 p++; 892 } 893 pr_info("\n"); 894 } 895 } 896 897 static void stmmac_display_rings(struct stmmac_priv *priv) 898 { 899 unsigned int txsize = priv->dma_tx_size; 900 unsigned int rxsize = priv->dma_rx_size; 901 902 if (priv->extend_desc) { 903 pr_info("Extended RX descriptor ring:\n"); 904 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 905 pr_info("Extended TX descriptor ring:\n"); 906 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 907 } else { 908 pr_info("RX descriptor ring:\n"); 909 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 910 pr_info("TX descriptor ring:\n"); 911 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 912 } 913 } 914 915 static int stmmac_set_bfsize(int mtu, int bufsize) 916 { 917 int ret = bufsize; 918 919 if (mtu >= BUF_SIZE_4KiB) 920 ret = BUF_SIZE_8KiB; 921 else if (mtu >= BUF_SIZE_2KiB) 922 ret = BUF_SIZE_4KiB; 923 else if (mtu > DEFAULT_BUFSIZE) 924 ret = BUF_SIZE_2KiB; 925 else 926 ret = DEFAULT_BUFSIZE; 927 928 return ret; 929 } 930 931 /** 932 * stmmac_clear_descriptors - clear descriptors 933 * @priv: driver private structure 934 * Description: this function is called to clear the tx and rx descriptors 935 * in case of both basic and extended descriptors are used. 936 */ 937 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 938 { 939 int i; 940 unsigned int txsize = priv->dma_tx_size; 941 unsigned int rxsize = priv->dma_rx_size; 942 943 /* Clear the Rx/Tx descriptors */ 944 for (i = 0; i < rxsize; i++) 945 if (priv->extend_desc) 946 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 947 priv->use_riwt, priv->mode, 948 (i == rxsize - 1)); 949 else 950 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 951 priv->use_riwt, priv->mode, 952 (i == rxsize - 1)); 953 for (i = 0; i < txsize; i++) 954 if (priv->extend_desc) 955 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 956 priv->mode, 957 (i == txsize - 1)); 958 else 959 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 960 priv->mode, 961 (i == txsize - 1)); 962 } 963 964 /** 965 * stmmac_init_rx_buffers - init the RX descriptor buffer. 966 * @priv: driver private structure 967 * @p: descriptor pointer 968 * @i: descriptor index 969 * @flags: gfp flag. 970 * Description: this function is called to allocate a receive buffer, perform 971 * the DMA mapping and init the descriptor. 972 */ 973 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 974 int i, gfp_t flags) 975 { 976 struct sk_buff *skb; 977 978 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 979 flags); 980 if (!skb) { 981 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 982 return -ENOMEM; 983 } 984 skb_reserve(skb, NET_IP_ALIGN); 985 priv->rx_skbuff[i] = skb; 986 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 987 priv->dma_buf_sz, 988 DMA_FROM_DEVICE); 989 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 990 pr_err("%s: DMA mapping error\n", __func__); 991 dev_kfree_skb_any(skb); 992 return -EINVAL; 993 } 994 995 p->des2 = priv->rx_skbuff_dma[i]; 996 997 if ((priv->hw->mode->init_desc3) && 998 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 999 priv->hw->mode->init_desc3(p); 1000 1001 return 0; 1002 } 1003 1004 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 1005 { 1006 if (priv->rx_skbuff[i]) { 1007 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1008 priv->dma_buf_sz, DMA_FROM_DEVICE); 1009 dev_kfree_skb_any(priv->rx_skbuff[i]); 1010 } 1011 priv->rx_skbuff[i] = NULL; 1012 } 1013 1014 /** 1015 * init_dma_desc_rings - init the RX/TX descriptor rings 1016 * @dev: net device structure 1017 * @flags: gfp flag. 1018 * Description: this function initializes the DMA RX/TX descriptors 1019 * and allocates the socket buffers. It suppors the chained and ring 1020 * modes. 1021 */ 1022 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1023 { 1024 int i; 1025 struct stmmac_priv *priv = netdev_priv(dev); 1026 unsigned int txsize = priv->dma_tx_size; 1027 unsigned int rxsize = priv->dma_rx_size; 1028 unsigned int bfsize = 0; 1029 int ret = -ENOMEM; 1030 1031 if (priv->hw->mode->set_16kib_bfsize) 1032 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1033 1034 if (bfsize < BUF_SIZE_16KiB) 1035 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1036 1037 priv->dma_buf_sz = bfsize; 1038 1039 if (netif_msg_probe(priv)) 1040 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1041 txsize, rxsize, bfsize); 1042 1043 if (netif_msg_probe(priv)) { 1044 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1045 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1046 1047 /* RX INITIALIZATION */ 1048 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1049 } 1050 for (i = 0; i < rxsize; i++) { 1051 struct dma_desc *p; 1052 if (priv->extend_desc) 1053 p = &((priv->dma_erx + i)->basic); 1054 else 1055 p = priv->dma_rx + i; 1056 1057 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1058 if (ret) 1059 goto err_init_rx_buffers; 1060 1061 if (netif_msg_probe(priv)) 1062 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1063 priv->rx_skbuff[i]->data, 1064 (unsigned int)priv->rx_skbuff_dma[i]); 1065 } 1066 priv->cur_rx = 0; 1067 priv->dirty_rx = (unsigned int)(i - rxsize); 1068 buf_sz = bfsize; 1069 1070 /* Setup the chained descriptor addresses */ 1071 if (priv->mode == STMMAC_CHAIN_MODE) { 1072 if (priv->extend_desc) { 1073 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1074 rxsize, 1); 1075 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1076 txsize, 1); 1077 } else { 1078 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1079 rxsize, 0); 1080 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1081 txsize, 0); 1082 } 1083 } 1084 1085 /* TX INITIALIZATION */ 1086 for (i = 0; i < txsize; i++) { 1087 struct dma_desc *p; 1088 if (priv->extend_desc) 1089 p = &((priv->dma_etx + i)->basic); 1090 else 1091 p = priv->dma_tx + i; 1092 p->des2 = 0; 1093 priv->tx_skbuff_dma[i].buf = 0; 1094 priv->tx_skbuff_dma[i].map_as_page = false; 1095 priv->tx_skbuff[i] = NULL; 1096 } 1097 1098 priv->dirty_tx = 0; 1099 priv->cur_tx = 0; 1100 netdev_reset_queue(priv->dev); 1101 1102 stmmac_clear_descriptors(priv); 1103 1104 if (netif_msg_hw(priv)) 1105 stmmac_display_rings(priv); 1106 1107 return 0; 1108 err_init_rx_buffers: 1109 while (--i >= 0) 1110 stmmac_free_rx_buffers(priv, i); 1111 return ret; 1112 } 1113 1114 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1115 { 1116 int i; 1117 1118 for (i = 0; i < priv->dma_rx_size; i++) 1119 stmmac_free_rx_buffers(priv, i); 1120 } 1121 1122 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1123 { 1124 int i; 1125 1126 for (i = 0; i < priv->dma_tx_size; i++) { 1127 struct dma_desc *p; 1128 1129 if (priv->extend_desc) 1130 p = &((priv->dma_etx + i)->basic); 1131 else 1132 p = priv->dma_tx + i; 1133 1134 if (priv->tx_skbuff_dma[i].buf) { 1135 if (priv->tx_skbuff_dma[i].map_as_page) 1136 dma_unmap_page(priv->device, 1137 priv->tx_skbuff_dma[i].buf, 1138 priv->hw->desc->get_tx_len(p), 1139 DMA_TO_DEVICE); 1140 else 1141 dma_unmap_single(priv->device, 1142 priv->tx_skbuff_dma[i].buf, 1143 priv->hw->desc->get_tx_len(p), 1144 DMA_TO_DEVICE); 1145 } 1146 1147 if (priv->tx_skbuff[i] != NULL) { 1148 dev_kfree_skb_any(priv->tx_skbuff[i]); 1149 priv->tx_skbuff[i] = NULL; 1150 priv->tx_skbuff_dma[i].buf = 0; 1151 priv->tx_skbuff_dma[i].map_as_page = false; 1152 } 1153 } 1154 } 1155 1156 /** 1157 * alloc_dma_desc_resources - alloc TX/RX resources. 1158 * @priv: private structure 1159 * Description: according to which descriptor can be used (extend or basic) 1160 * this function allocates the resources for TX and RX paths. In case of 1161 * reception, for example, it pre-allocated the RX socket buffer in order to 1162 * allow zero-copy mechanism. 1163 */ 1164 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1165 { 1166 unsigned int txsize = priv->dma_tx_size; 1167 unsigned int rxsize = priv->dma_rx_size; 1168 int ret = -ENOMEM; 1169 1170 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1171 GFP_KERNEL); 1172 if (!priv->rx_skbuff_dma) 1173 return -ENOMEM; 1174 1175 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1176 GFP_KERNEL); 1177 if (!priv->rx_skbuff) 1178 goto err_rx_skbuff; 1179 1180 priv->tx_skbuff_dma = kmalloc_array(txsize, 1181 sizeof(*priv->tx_skbuff_dma), 1182 GFP_KERNEL); 1183 if (!priv->tx_skbuff_dma) 1184 goto err_tx_skbuff_dma; 1185 1186 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1187 GFP_KERNEL); 1188 if (!priv->tx_skbuff) 1189 goto err_tx_skbuff; 1190 1191 if (priv->extend_desc) { 1192 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1193 sizeof(struct 1194 dma_extended_desc), 1195 &priv->dma_rx_phy, 1196 GFP_KERNEL); 1197 if (!priv->dma_erx) 1198 goto err_dma; 1199 1200 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1201 sizeof(struct 1202 dma_extended_desc), 1203 &priv->dma_tx_phy, 1204 GFP_KERNEL); 1205 if (!priv->dma_etx) { 1206 dma_free_coherent(priv->device, priv->dma_rx_size * 1207 sizeof(struct dma_extended_desc), 1208 priv->dma_erx, priv->dma_rx_phy); 1209 goto err_dma; 1210 } 1211 } else { 1212 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1213 sizeof(struct dma_desc), 1214 &priv->dma_rx_phy, 1215 GFP_KERNEL); 1216 if (!priv->dma_rx) 1217 goto err_dma; 1218 1219 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1220 sizeof(struct dma_desc), 1221 &priv->dma_tx_phy, 1222 GFP_KERNEL); 1223 if (!priv->dma_tx) { 1224 dma_free_coherent(priv->device, priv->dma_rx_size * 1225 sizeof(struct dma_desc), 1226 priv->dma_rx, priv->dma_rx_phy); 1227 goto err_dma; 1228 } 1229 } 1230 1231 return 0; 1232 1233 err_dma: 1234 kfree(priv->tx_skbuff); 1235 err_tx_skbuff: 1236 kfree(priv->tx_skbuff_dma); 1237 err_tx_skbuff_dma: 1238 kfree(priv->rx_skbuff); 1239 err_rx_skbuff: 1240 kfree(priv->rx_skbuff_dma); 1241 return ret; 1242 } 1243 1244 static void free_dma_desc_resources(struct stmmac_priv *priv) 1245 { 1246 /* Release the DMA TX/RX socket buffers */ 1247 dma_free_rx_skbufs(priv); 1248 dma_free_tx_skbufs(priv); 1249 1250 /* Free DMA regions of consistent memory previously allocated */ 1251 if (!priv->extend_desc) { 1252 dma_free_coherent(priv->device, 1253 priv->dma_tx_size * sizeof(struct dma_desc), 1254 priv->dma_tx, priv->dma_tx_phy); 1255 dma_free_coherent(priv->device, 1256 priv->dma_rx_size * sizeof(struct dma_desc), 1257 priv->dma_rx, priv->dma_rx_phy); 1258 } else { 1259 dma_free_coherent(priv->device, priv->dma_tx_size * 1260 sizeof(struct dma_extended_desc), 1261 priv->dma_etx, priv->dma_tx_phy); 1262 dma_free_coherent(priv->device, priv->dma_rx_size * 1263 sizeof(struct dma_extended_desc), 1264 priv->dma_erx, priv->dma_rx_phy); 1265 } 1266 kfree(priv->rx_skbuff_dma); 1267 kfree(priv->rx_skbuff); 1268 kfree(priv->tx_skbuff_dma); 1269 kfree(priv->tx_skbuff); 1270 } 1271 1272 /** 1273 * stmmac_dma_operation_mode - HW DMA operation mode 1274 * @priv: driver private structure 1275 * Description: it is used for configuring the DMA operation mode register in 1276 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1277 */ 1278 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1279 { 1280 if (priv->plat->force_thresh_dma_mode) 1281 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1282 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1283 /* 1284 * In case of GMAC, SF mode can be enabled 1285 * to perform the TX COE in HW. This depends on: 1286 * 1) TX COE if actually supported 1287 * 2) There is no bugged Jumbo frame support 1288 * that needs to not insert csum in the TDES. 1289 */ 1290 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1291 priv->xstats.threshold = SF_DMA_MODE; 1292 } else 1293 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1294 } 1295 1296 /** 1297 * stmmac_tx_clean - to manage the transmission completion 1298 * @priv: driver private structure 1299 * Description: it reclaims the transmit resources after transmission completes. 1300 */ 1301 static void stmmac_tx_clean(struct stmmac_priv *priv) 1302 { 1303 unsigned int txsize = priv->dma_tx_size; 1304 unsigned int bytes_compl = 0, pkts_compl = 0; 1305 1306 spin_lock(&priv->tx_lock); 1307 1308 priv->xstats.tx_clean++; 1309 1310 while (priv->dirty_tx != priv->cur_tx) { 1311 int last; 1312 unsigned int entry = priv->dirty_tx % txsize; 1313 struct sk_buff *skb = priv->tx_skbuff[entry]; 1314 struct dma_desc *p; 1315 1316 if (priv->extend_desc) 1317 p = (struct dma_desc *)(priv->dma_etx + entry); 1318 else 1319 p = priv->dma_tx + entry; 1320 1321 /* Check if the descriptor is owned by the DMA. */ 1322 if (priv->hw->desc->get_tx_owner(p)) 1323 break; 1324 1325 /* Verify tx error by looking at the last segment. */ 1326 last = priv->hw->desc->get_tx_ls(p); 1327 if (likely(last)) { 1328 int tx_error = 1329 priv->hw->desc->tx_status(&priv->dev->stats, 1330 &priv->xstats, p, 1331 priv->ioaddr); 1332 if (likely(tx_error == 0)) { 1333 priv->dev->stats.tx_packets++; 1334 priv->xstats.tx_pkt_n++; 1335 } else 1336 priv->dev->stats.tx_errors++; 1337 1338 stmmac_get_tx_hwtstamp(priv, entry, skb); 1339 } 1340 if (netif_msg_tx_done(priv)) 1341 pr_debug("%s: curr %d, dirty %d\n", __func__, 1342 priv->cur_tx, priv->dirty_tx); 1343 1344 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1345 if (priv->tx_skbuff_dma[entry].map_as_page) 1346 dma_unmap_page(priv->device, 1347 priv->tx_skbuff_dma[entry].buf, 1348 priv->hw->desc->get_tx_len(p), 1349 DMA_TO_DEVICE); 1350 else 1351 dma_unmap_single(priv->device, 1352 priv->tx_skbuff_dma[entry].buf, 1353 priv->hw->desc->get_tx_len(p), 1354 DMA_TO_DEVICE); 1355 priv->tx_skbuff_dma[entry].buf = 0; 1356 priv->tx_skbuff_dma[entry].map_as_page = false; 1357 } 1358 priv->hw->mode->clean_desc3(priv, p); 1359 1360 if (likely(skb != NULL)) { 1361 pkts_compl++; 1362 bytes_compl += skb->len; 1363 dev_consume_skb_any(skb); 1364 priv->tx_skbuff[entry] = NULL; 1365 } 1366 1367 priv->hw->desc->release_tx_desc(p, priv->mode); 1368 1369 priv->dirty_tx++; 1370 } 1371 1372 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1373 1374 if (unlikely(netif_queue_stopped(priv->dev) && 1375 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1376 netif_tx_lock(priv->dev); 1377 if (netif_queue_stopped(priv->dev) && 1378 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1379 if (netif_msg_tx_done(priv)) 1380 pr_debug("%s: restart transmit\n", __func__); 1381 netif_wake_queue(priv->dev); 1382 } 1383 netif_tx_unlock(priv->dev); 1384 } 1385 1386 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1387 stmmac_enable_eee_mode(priv); 1388 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1389 } 1390 spin_unlock(&priv->tx_lock); 1391 } 1392 1393 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1394 { 1395 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1396 } 1397 1398 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1399 { 1400 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1401 } 1402 1403 /** 1404 * stmmac_tx_err - to manage the tx error 1405 * @priv: driver private structure 1406 * Description: it cleans the descriptors and restarts the transmission 1407 * in case of transmission errors. 1408 */ 1409 static void stmmac_tx_err(struct stmmac_priv *priv) 1410 { 1411 int i; 1412 int txsize = priv->dma_tx_size; 1413 netif_stop_queue(priv->dev); 1414 1415 priv->hw->dma->stop_tx(priv->ioaddr); 1416 dma_free_tx_skbufs(priv); 1417 for (i = 0; i < txsize; i++) 1418 if (priv->extend_desc) 1419 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1420 priv->mode, 1421 (i == txsize - 1)); 1422 else 1423 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1424 priv->mode, 1425 (i == txsize - 1)); 1426 priv->dirty_tx = 0; 1427 priv->cur_tx = 0; 1428 netdev_reset_queue(priv->dev); 1429 priv->hw->dma->start_tx(priv->ioaddr); 1430 1431 priv->dev->stats.tx_errors++; 1432 netif_wake_queue(priv->dev); 1433 } 1434 1435 /** 1436 * stmmac_dma_interrupt - DMA ISR 1437 * @priv: driver private structure 1438 * Description: this is the DMA ISR. It is called by the main ISR. 1439 * It calls the dwmac dma routine and schedule poll method in case of some 1440 * work can be done. 1441 */ 1442 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1443 { 1444 int status; 1445 1446 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1447 if (likely((status & handle_rx)) || (status & handle_tx)) { 1448 if (likely(napi_schedule_prep(&priv->napi))) { 1449 stmmac_disable_dma_irq(priv); 1450 __napi_schedule(&priv->napi); 1451 } 1452 } 1453 if (unlikely(status & tx_hard_error_bump_tc)) { 1454 /* Try to bump up the dma threshold on this failure */ 1455 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1456 (tc <= 256)) { 1457 tc += 64; 1458 if (priv->plat->force_thresh_dma_mode) 1459 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1460 else 1461 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1462 SF_DMA_MODE); 1463 priv->xstats.threshold = tc; 1464 } 1465 } else if (unlikely(status == tx_hard_error)) 1466 stmmac_tx_err(priv); 1467 } 1468 1469 /** 1470 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1471 * @priv: driver private structure 1472 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1473 */ 1474 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1475 { 1476 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1477 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1478 1479 dwmac_mmc_intr_all_mask(priv->ioaddr); 1480 1481 if (priv->dma_cap.rmon) { 1482 dwmac_mmc_ctrl(priv->ioaddr, mode); 1483 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1484 } else 1485 pr_info(" No MAC Management Counters available\n"); 1486 } 1487 1488 /** 1489 * stmmac_get_synopsys_id - return the SYINID. 1490 * @priv: driver private structure 1491 * Description: this simple function is to decode and return the SYINID 1492 * starting from the HW core register. 1493 */ 1494 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1495 { 1496 u32 hwid = priv->hw->synopsys_uid; 1497 1498 /* Check Synopsys Id (not available on old chips) */ 1499 if (likely(hwid)) { 1500 u32 uid = ((hwid & 0x0000ff00) >> 8); 1501 u32 synid = (hwid & 0x000000ff); 1502 1503 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1504 uid, synid); 1505 1506 return synid; 1507 } 1508 return 0; 1509 } 1510 1511 /** 1512 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1513 * @priv: driver private structure 1514 * Description: select the Enhanced/Alternate or Normal descriptors. 1515 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1516 * supported by the HW capability register. 1517 */ 1518 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1519 { 1520 if (priv->plat->enh_desc) { 1521 pr_info(" Enhanced/Alternate descriptors\n"); 1522 1523 /* GMAC older than 3.50 has no extended descriptors */ 1524 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1525 pr_info("\tEnabled extended descriptors\n"); 1526 priv->extend_desc = 1; 1527 } else 1528 pr_warn("Extended descriptors not supported\n"); 1529 1530 priv->hw->desc = &enh_desc_ops; 1531 } else { 1532 pr_info(" Normal descriptors\n"); 1533 priv->hw->desc = &ndesc_ops; 1534 } 1535 } 1536 1537 /** 1538 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1539 * @priv: driver private structure 1540 * Description: 1541 * new GMAC chip generations have a new register to indicate the 1542 * presence of the optional feature/functions. 1543 * This can be also used to override the value passed through the 1544 * platform and necessary for old MAC10/100 and GMAC chips. 1545 */ 1546 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1547 { 1548 u32 hw_cap = 0; 1549 1550 if (priv->hw->dma->get_hw_feature) { 1551 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1552 1553 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1554 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1555 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1556 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1557 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1558 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1559 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1560 priv->dma_cap.pmt_remote_wake_up = 1561 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1562 priv->dma_cap.pmt_magic_frame = 1563 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1564 /* MMC */ 1565 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1566 /* IEEE 1588-2002 */ 1567 priv->dma_cap.time_stamp = 1568 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1569 /* IEEE 1588-2008 */ 1570 priv->dma_cap.atime_stamp = 1571 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1572 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1573 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1574 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1575 /* TX and RX csum */ 1576 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1577 priv->dma_cap.rx_coe_type1 = 1578 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1579 priv->dma_cap.rx_coe_type2 = 1580 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1581 priv->dma_cap.rxfifo_over_2048 = 1582 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1583 /* TX and RX number of channels */ 1584 priv->dma_cap.number_rx_channel = 1585 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1586 priv->dma_cap.number_tx_channel = 1587 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1588 /* Alternate (enhanced) DESC mode */ 1589 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1590 } 1591 1592 return hw_cap; 1593 } 1594 1595 /** 1596 * stmmac_check_ether_addr - check if the MAC addr is valid 1597 * @priv: driver private structure 1598 * Description: 1599 * it is to verify if the MAC address is valid, in case of failures it 1600 * generates a random MAC address 1601 */ 1602 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1603 { 1604 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1605 priv->hw->mac->get_umac_addr(priv->hw, 1606 priv->dev->dev_addr, 0); 1607 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1608 eth_hw_addr_random(priv->dev); 1609 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1610 priv->dev->dev_addr); 1611 } 1612 } 1613 1614 /** 1615 * stmmac_init_dma_engine - DMA init. 1616 * @priv: driver private structure 1617 * Description: 1618 * It inits the DMA invoking the specific MAC/GMAC callback. 1619 * Some DMA parameters can be passed from the platform; 1620 * in case of these are not passed a default is kept for the MAC or GMAC. 1621 */ 1622 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1623 { 1624 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1625 int mixed_burst = 0; 1626 int atds = 0; 1627 1628 if (priv->plat->dma_cfg) { 1629 pbl = priv->plat->dma_cfg->pbl; 1630 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1631 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1632 burst_len = priv->plat->dma_cfg->burst_len; 1633 } 1634 1635 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1636 atds = 1; 1637 1638 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1639 burst_len, priv->dma_tx_phy, 1640 priv->dma_rx_phy, atds); 1641 } 1642 1643 /** 1644 * stmmac_tx_timer - mitigation sw timer for tx. 1645 * @data: data pointer 1646 * Description: 1647 * This is the timer handler to directly invoke the stmmac_tx_clean. 1648 */ 1649 static void stmmac_tx_timer(unsigned long data) 1650 { 1651 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1652 1653 stmmac_tx_clean(priv); 1654 } 1655 1656 /** 1657 * stmmac_init_tx_coalesce - init tx mitigation options. 1658 * @priv: driver private structure 1659 * Description: 1660 * This inits the transmit coalesce parameters: i.e. timer rate, 1661 * timer handler and default threshold used for enabling the 1662 * interrupt on completion bit. 1663 */ 1664 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1665 { 1666 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1667 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1668 init_timer(&priv->txtimer); 1669 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1670 priv->txtimer.data = (unsigned long)priv; 1671 priv->txtimer.function = stmmac_tx_timer; 1672 add_timer(&priv->txtimer); 1673 } 1674 1675 /** 1676 * stmmac_hw_setup - setup mac in a usable state. 1677 * @dev : pointer to the device structure. 1678 * Description: 1679 * this is the main function to setup the HW in a usable state because the 1680 * dma engine is reset, the core registers are configured (e.g. AXI, 1681 * Checksum features, timers). The DMA is ready to start receiving and 1682 * transmitting. 1683 * Return value: 1684 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1685 * file on failure. 1686 */ 1687 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1688 { 1689 struct stmmac_priv *priv = netdev_priv(dev); 1690 int ret; 1691 1692 /* DMA initialization and SW reset */ 1693 ret = stmmac_init_dma_engine(priv); 1694 if (ret < 0) { 1695 pr_err("%s: DMA engine initialization failed\n", __func__); 1696 return ret; 1697 } 1698 1699 /* Copy the MAC addr into the HW */ 1700 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1701 1702 /* If required, perform hw setup of the bus. */ 1703 if (priv->plat->bus_setup) 1704 priv->plat->bus_setup(priv->ioaddr); 1705 1706 /* Initialize the MAC Core */ 1707 priv->hw->mac->core_init(priv->hw, dev->mtu); 1708 1709 ret = priv->hw->mac->rx_ipc(priv->hw); 1710 if (!ret) { 1711 pr_warn(" RX IPC Checksum Offload disabled\n"); 1712 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1713 priv->hw->rx_csum = 0; 1714 } 1715 1716 /* Enable the MAC Rx/Tx */ 1717 stmmac_set_mac(priv->ioaddr, true); 1718 1719 /* Set the HW DMA mode and the COE */ 1720 stmmac_dma_operation_mode(priv); 1721 1722 stmmac_mmc_setup(priv); 1723 1724 if (init_ptp) { 1725 ret = stmmac_init_ptp(priv); 1726 if (ret && ret != -EOPNOTSUPP) 1727 pr_warn("%s: failed PTP initialisation\n", __func__); 1728 } 1729 1730 #ifdef CONFIG_DEBUG_FS 1731 ret = stmmac_init_fs(dev); 1732 if (ret < 0) 1733 pr_warn("%s: failed debugFS registration\n", __func__); 1734 #endif 1735 /* Start the ball rolling... */ 1736 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1737 priv->hw->dma->start_tx(priv->ioaddr); 1738 priv->hw->dma->start_rx(priv->ioaddr); 1739 1740 /* Dump DMA/MAC registers */ 1741 if (netif_msg_hw(priv)) { 1742 priv->hw->mac->dump_regs(priv->hw); 1743 priv->hw->dma->dump_regs(priv->ioaddr); 1744 } 1745 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1746 1747 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1748 priv->rx_riwt = MAX_DMA_RIWT; 1749 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1750 } 1751 1752 if (priv->pcs && priv->hw->mac->ctrl_ane) 1753 priv->hw->mac->ctrl_ane(priv->hw, 0); 1754 1755 return 0; 1756 } 1757 1758 /** 1759 * stmmac_open - open entry point of the driver 1760 * @dev : pointer to the device structure. 1761 * Description: 1762 * This function is the open entry point of the driver. 1763 * Return value: 1764 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1765 * file on failure. 1766 */ 1767 static int stmmac_open(struct net_device *dev) 1768 { 1769 struct stmmac_priv *priv = netdev_priv(dev); 1770 int ret; 1771 1772 stmmac_check_ether_addr(priv); 1773 1774 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1775 priv->pcs != STMMAC_PCS_RTBI) { 1776 ret = stmmac_init_phy(dev); 1777 if (ret) { 1778 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1779 __func__, ret); 1780 return ret; 1781 } 1782 } 1783 1784 /* Extra statistics */ 1785 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1786 priv->xstats.threshold = tc; 1787 1788 /* Create and initialize the TX/RX descriptors chains. */ 1789 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1790 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1791 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1792 1793 ret = alloc_dma_desc_resources(priv); 1794 if (ret < 0) { 1795 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1796 goto dma_desc_error; 1797 } 1798 1799 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1800 if (ret < 0) { 1801 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1802 goto init_error; 1803 } 1804 1805 ret = stmmac_hw_setup(dev, true); 1806 if (ret < 0) { 1807 pr_err("%s: Hw setup failed\n", __func__); 1808 goto init_error; 1809 } 1810 1811 stmmac_init_tx_coalesce(priv); 1812 1813 if (priv->phydev) 1814 phy_start(priv->phydev); 1815 1816 /* Request the IRQ lines */ 1817 ret = request_irq(dev->irq, stmmac_interrupt, 1818 IRQF_SHARED, dev->name, dev); 1819 if (unlikely(ret < 0)) { 1820 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1821 __func__, dev->irq, ret); 1822 goto init_error; 1823 } 1824 1825 /* Request the Wake IRQ in case of another line is used for WoL */ 1826 if (priv->wol_irq != dev->irq) { 1827 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1828 IRQF_SHARED, dev->name, dev); 1829 if (unlikely(ret < 0)) { 1830 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1831 __func__, priv->wol_irq, ret); 1832 goto wolirq_error; 1833 } 1834 } 1835 1836 /* Request the IRQ lines */ 1837 if (priv->lpi_irq > 0) { 1838 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1839 dev->name, dev); 1840 if (unlikely(ret < 0)) { 1841 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1842 __func__, priv->lpi_irq, ret); 1843 goto lpiirq_error; 1844 } 1845 } 1846 1847 napi_enable(&priv->napi); 1848 netif_start_queue(dev); 1849 1850 return 0; 1851 1852 lpiirq_error: 1853 if (priv->wol_irq != dev->irq) 1854 free_irq(priv->wol_irq, dev); 1855 wolirq_error: 1856 free_irq(dev->irq, dev); 1857 1858 init_error: 1859 free_dma_desc_resources(priv); 1860 dma_desc_error: 1861 if (priv->phydev) 1862 phy_disconnect(priv->phydev); 1863 1864 return ret; 1865 } 1866 1867 /** 1868 * stmmac_release - close entry point of the driver 1869 * @dev : device pointer. 1870 * Description: 1871 * This is the stop entry point of the driver. 1872 */ 1873 static int stmmac_release(struct net_device *dev) 1874 { 1875 struct stmmac_priv *priv = netdev_priv(dev); 1876 1877 if (priv->eee_enabled) 1878 del_timer_sync(&priv->eee_ctrl_timer); 1879 1880 /* Stop and disconnect the PHY */ 1881 if (priv->phydev) { 1882 phy_stop(priv->phydev); 1883 phy_disconnect(priv->phydev); 1884 priv->phydev = NULL; 1885 } 1886 1887 netif_stop_queue(dev); 1888 1889 napi_disable(&priv->napi); 1890 1891 del_timer_sync(&priv->txtimer); 1892 1893 /* Free the IRQ lines */ 1894 free_irq(dev->irq, dev); 1895 if (priv->wol_irq != dev->irq) 1896 free_irq(priv->wol_irq, dev); 1897 if (priv->lpi_irq > 0) 1898 free_irq(priv->lpi_irq, dev); 1899 1900 /* Stop TX/RX DMA and clear the descriptors */ 1901 priv->hw->dma->stop_tx(priv->ioaddr); 1902 priv->hw->dma->stop_rx(priv->ioaddr); 1903 1904 /* Release and free the Rx/Tx resources */ 1905 free_dma_desc_resources(priv); 1906 1907 /* Disable the MAC Rx/Tx */ 1908 stmmac_set_mac(priv->ioaddr, false); 1909 1910 netif_carrier_off(dev); 1911 1912 #ifdef CONFIG_DEBUG_FS 1913 stmmac_exit_fs(); 1914 #endif 1915 1916 stmmac_release_ptp(priv); 1917 1918 return 0; 1919 } 1920 1921 /** 1922 * stmmac_xmit - Tx entry point of the driver 1923 * @skb : the socket buffer 1924 * @dev : device pointer 1925 * Description : this is the tx entry point of the driver. 1926 * It programs the chain or the ring and supports oversized frames 1927 * and SG feature. 1928 */ 1929 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1930 { 1931 struct stmmac_priv *priv = netdev_priv(dev); 1932 unsigned int txsize = priv->dma_tx_size; 1933 unsigned int entry; 1934 int i, csum_insertion = 0, is_jumbo = 0; 1935 int nfrags = skb_shinfo(skb)->nr_frags; 1936 struct dma_desc *desc, *first; 1937 unsigned int nopaged_len = skb_headlen(skb); 1938 unsigned int enh_desc = priv->plat->enh_desc; 1939 1940 spin_lock(&priv->tx_lock); 1941 1942 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1943 spin_unlock(&priv->tx_lock); 1944 if (!netif_queue_stopped(dev)) { 1945 netif_stop_queue(dev); 1946 /* This is a hard error, log it. */ 1947 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1948 } 1949 return NETDEV_TX_BUSY; 1950 } 1951 1952 if (priv->tx_path_in_lpi_mode) 1953 stmmac_disable_eee_mode(priv); 1954 1955 entry = priv->cur_tx % txsize; 1956 1957 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1958 1959 if (priv->extend_desc) 1960 desc = (struct dma_desc *)(priv->dma_etx + entry); 1961 else 1962 desc = priv->dma_tx + entry; 1963 1964 first = desc; 1965 1966 /* To program the descriptors according to the size of the frame */ 1967 if (enh_desc) 1968 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 1969 1970 if (likely(!is_jumbo)) { 1971 desc->des2 = dma_map_single(priv->device, skb->data, 1972 nopaged_len, DMA_TO_DEVICE); 1973 if (dma_mapping_error(priv->device, desc->des2)) 1974 goto dma_map_err; 1975 priv->tx_skbuff_dma[entry].buf = desc->des2; 1976 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1977 csum_insertion, priv->mode); 1978 } else { 1979 desc = first; 1980 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 1981 if (unlikely(entry < 0)) 1982 goto dma_map_err; 1983 } 1984 1985 for (i = 0; i < nfrags; i++) { 1986 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1987 int len = skb_frag_size(frag); 1988 1989 priv->tx_skbuff[entry] = NULL; 1990 entry = (++priv->cur_tx) % txsize; 1991 if (priv->extend_desc) 1992 desc = (struct dma_desc *)(priv->dma_etx + entry); 1993 else 1994 desc = priv->dma_tx + entry; 1995 1996 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1997 DMA_TO_DEVICE); 1998 if (dma_mapping_error(priv->device, desc->des2)) 1999 goto dma_map_err; /* should reuse desc w/o issues */ 2000 2001 priv->tx_skbuff_dma[entry].buf = desc->des2; 2002 priv->tx_skbuff_dma[entry].map_as_page = true; 2003 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2004 priv->mode); 2005 wmb(); 2006 priv->hw->desc->set_tx_owner(desc); 2007 wmb(); 2008 } 2009 2010 priv->tx_skbuff[entry] = skb; 2011 2012 /* Finalize the latest segment. */ 2013 priv->hw->desc->close_tx_desc(desc); 2014 2015 wmb(); 2016 /* According to the coalesce parameter the IC bit for the latest 2017 * segment could be reset and the timer re-started to invoke the 2018 * stmmac_tx function. This approach takes care about the fragments. 2019 */ 2020 priv->tx_count_frames += nfrags + 1; 2021 if (priv->tx_coal_frames > priv->tx_count_frames) { 2022 priv->hw->desc->clear_tx_ic(desc); 2023 priv->xstats.tx_reset_ic_bit++; 2024 mod_timer(&priv->txtimer, 2025 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2026 } else 2027 priv->tx_count_frames = 0; 2028 2029 /* To avoid raise condition */ 2030 priv->hw->desc->set_tx_owner(first); 2031 wmb(); 2032 2033 priv->cur_tx++; 2034 2035 if (netif_msg_pktdata(priv)) { 2036 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 2037 __func__, (priv->cur_tx % txsize), 2038 (priv->dirty_tx % txsize), entry, first, nfrags); 2039 2040 if (priv->extend_desc) 2041 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 2042 else 2043 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 2044 2045 pr_debug(">>> frame to be transmitted: "); 2046 print_pkt(skb->data, skb->len); 2047 } 2048 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2049 if (netif_msg_hw(priv)) 2050 pr_debug("%s: stop transmitted packets\n", __func__); 2051 netif_stop_queue(dev); 2052 } 2053 2054 dev->stats.tx_bytes += skb->len; 2055 2056 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2057 priv->hwts_tx_en)) { 2058 /* declare that device is doing timestamping */ 2059 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2060 priv->hw->desc->enable_tx_timestamp(first); 2061 } 2062 2063 if (!priv->hwts_tx_en) 2064 skb_tx_timestamp(skb); 2065 2066 netdev_sent_queue(dev, skb->len); 2067 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2068 2069 spin_unlock(&priv->tx_lock); 2070 return NETDEV_TX_OK; 2071 2072 dma_map_err: 2073 spin_unlock(&priv->tx_lock); 2074 dev_err(priv->device, "Tx dma map failed\n"); 2075 dev_kfree_skb(skb); 2076 priv->dev->stats.tx_dropped++; 2077 return NETDEV_TX_OK; 2078 } 2079 2080 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2081 { 2082 struct ethhdr *ehdr; 2083 u16 vlanid; 2084 2085 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2086 NETIF_F_HW_VLAN_CTAG_RX && 2087 !__vlan_get_tag(skb, &vlanid)) { 2088 /* pop the vlan tag */ 2089 ehdr = (struct ethhdr *)skb->data; 2090 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2091 skb_pull(skb, VLAN_HLEN); 2092 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2093 } 2094 } 2095 2096 2097 /** 2098 * stmmac_rx_refill - refill used skb preallocated buffers 2099 * @priv: driver private structure 2100 * Description : this is to reallocate the skb for the reception process 2101 * that is based on zero-copy. 2102 */ 2103 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2104 { 2105 unsigned int rxsize = priv->dma_rx_size; 2106 int bfsize = priv->dma_buf_sz; 2107 2108 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2109 unsigned int entry = priv->dirty_rx % rxsize; 2110 struct dma_desc *p; 2111 2112 if (priv->extend_desc) 2113 p = (struct dma_desc *)(priv->dma_erx + entry); 2114 else 2115 p = priv->dma_rx + entry; 2116 2117 if (likely(priv->rx_skbuff[entry] == NULL)) { 2118 struct sk_buff *skb; 2119 2120 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2121 2122 if (unlikely(skb == NULL)) 2123 break; 2124 2125 priv->rx_skbuff[entry] = skb; 2126 priv->rx_skbuff_dma[entry] = 2127 dma_map_single(priv->device, skb->data, bfsize, 2128 DMA_FROM_DEVICE); 2129 if (dma_mapping_error(priv->device, 2130 priv->rx_skbuff_dma[entry])) { 2131 dev_err(priv->device, "Rx dma map failed\n"); 2132 dev_kfree_skb(skb); 2133 break; 2134 } 2135 p->des2 = priv->rx_skbuff_dma[entry]; 2136 2137 priv->hw->mode->refill_desc3(priv, p); 2138 2139 if (netif_msg_rx_status(priv)) 2140 pr_debug("\trefill entry #%d\n", entry); 2141 } 2142 wmb(); 2143 priv->hw->desc->set_rx_owner(p); 2144 wmb(); 2145 } 2146 } 2147 2148 /** 2149 * stmmac_rx - manage the receive process 2150 * @priv: driver private structure 2151 * @limit: napi bugget. 2152 * Description : this the function called by the napi poll method. 2153 * It gets all the frames inside the ring. 2154 */ 2155 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2156 { 2157 unsigned int rxsize = priv->dma_rx_size; 2158 unsigned int entry = priv->cur_rx % rxsize; 2159 unsigned int next_entry; 2160 unsigned int count = 0; 2161 int coe = priv->hw->rx_csum; 2162 2163 if (netif_msg_rx_status(priv)) { 2164 pr_debug("%s: descriptor ring:\n", __func__); 2165 if (priv->extend_desc) 2166 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2167 else 2168 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2169 } 2170 while (count < limit) { 2171 int status; 2172 struct dma_desc *p; 2173 2174 if (priv->extend_desc) 2175 p = (struct dma_desc *)(priv->dma_erx + entry); 2176 else 2177 p = priv->dma_rx + entry; 2178 2179 if (priv->hw->desc->get_rx_owner(p)) 2180 break; 2181 2182 count++; 2183 2184 next_entry = (++priv->cur_rx) % rxsize; 2185 if (priv->extend_desc) 2186 prefetch(priv->dma_erx + next_entry); 2187 else 2188 prefetch(priv->dma_rx + next_entry); 2189 2190 /* read the status of the incoming frame */ 2191 status = priv->hw->desc->rx_status(&priv->dev->stats, 2192 &priv->xstats, p); 2193 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2194 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2195 &priv->xstats, 2196 priv->dma_erx + 2197 entry); 2198 if (unlikely(status == discard_frame)) { 2199 priv->dev->stats.rx_errors++; 2200 if (priv->hwts_rx_en && !priv->extend_desc) { 2201 /* DESC2 & DESC3 will be overwitten by device 2202 * with timestamp value, hence reinitialize 2203 * them in stmmac_rx_refill() function so that 2204 * device can reuse it. 2205 */ 2206 priv->rx_skbuff[entry] = NULL; 2207 dma_unmap_single(priv->device, 2208 priv->rx_skbuff_dma[entry], 2209 priv->dma_buf_sz, 2210 DMA_FROM_DEVICE); 2211 } 2212 } else { 2213 struct sk_buff *skb; 2214 int frame_len; 2215 2216 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2217 2218 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2219 * Type frames (LLC/LLC-SNAP) 2220 */ 2221 if (unlikely(status != llc_snap)) 2222 frame_len -= ETH_FCS_LEN; 2223 2224 if (netif_msg_rx_status(priv)) { 2225 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2226 p, entry, p->des2); 2227 if (frame_len > ETH_FRAME_LEN) 2228 pr_debug("\tframe size %d, COE: %d\n", 2229 frame_len, status); 2230 } 2231 skb = priv->rx_skbuff[entry]; 2232 if (unlikely(!skb)) { 2233 pr_err("%s: Inconsistent Rx descriptor chain\n", 2234 priv->dev->name); 2235 priv->dev->stats.rx_dropped++; 2236 break; 2237 } 2238 prefetch(skb->data - NET_IP_ALIGN); 2239 priv->rx_skbuff[entry] = NULL; 2240 2241 stmmac_get_rx_hwtstamp(priv, entry, skb); 2242 2243 skb_put(skb, frame_len); 2244 dma_unmap_single(priv->device, 2245 priv->rx_skbuff_dma[entry], 2246 priv->dma_buf_sz, DMA_FROM_DEVICE); 2247 2248 if (netif_msg_pktdata(priv)) { 2249 pr_debug("frame received (%dbytes)", frame_len); 2250 print_pkt(skb->data, frame_len); 2251 } 2252 2253 stmmac_rx_vlan(priv->dev, skb); 2254 2255 skb->protocol = eth_type_trans(skb, priv->dev); 2256 2257 if (unlikely(!coe)) 2258 skb_checksum_none_assert(skb); 2259 else 2260 skb->ip_summed = CHECKSUM_UNNECESSARY; 2261 2262 napi_gro_receive(&priv->napi, skb); 2263 2264 priv->dev->stats.rx_packets++; 2265 priv->dev->stats.rx_bytes += frame_len; 2266 } 2267 entry = next_entry; 2268 } 2269 2270 stmmac_rx_refill(priv); 2271 2272 priv->xstats.rx_pkt_n += count; 2273 2274 return count; 2275 } 2276 2277 /** 2278 * stmmac_poll - stmmac poll method (NAPI) 2279 * @napi : pointer to the napi structure. 2280 * @budget : maximum number of packets that the current CPU can receive from 2281 * all interfaces. 2282 * Description : 2283 * To look at the incoming frames and clear the tx resources. 2284 */ 2285 static int stmmac_poll(struct napi_struct *napi, int budget) 2286 { 2287 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2288 int work_done = 0; 2289 2290 priv->xstats.napi_poll++; 2291 stmmac_tx_clean(priv); 2292 2293 work_done = stmmac_rx(priv, budget); 2294 if (work_done < budget) { 2295 napi_complete(napi); 2296 stmmac_enable_dma_irq(priv); 2297 } 2298 return work_done; 2299 } 2300 2301 /** 2302 * stmmac_tx_timeout 2303 * @dev : Pointer to net device structure 2304 * Description: this function is called when a packet transmission fails to 2305 * complete within a reasonable time. The driver will mark the error in the 2306 * netdev structure and arrange for the device to be reset to a sane state 2307 * in order to transmit a new packet. 2308 */ 2309 static void stmmac_tx_timeout(struct net_device *dev) 2310 { 2311 struct stmmac_priv *priv = netdev_priv(dev); 2312 2313 /* Clear Tx resources and restart transmitting again */ 2314 stmmac_tx_err(priv); 2315 } 2316 2317 /** 2318 * stmmac_set_rx_mode - entry point for multicast addressing 2319 * @dev : pointer to the device structure 2320 * Description: 2321 * This function is a driver entry point which gets called by the kernel 2322 * whenever multicast addresses must be enabled/disabled. 2323 * Return value: 2324 * void. 2325 */ 2326 static void stmmac_set_rx_mode(struct net_device *dev) 2327 { 2328 struct stmmac_priv *priv = netdev_priv(dev); 2329 2330 priv->hw->mac->set_filter(priv->hw, dev); 2331 } 2332 2333 /** 2334 * stmmac_change_mtu - entry point to change MTU size for the device. 2335 * @dev : device pointer. 2336 * @new_mtu : the new MTU size for the device. 2337 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2338 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2339 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2340 * Return value: 2341 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2342 * file on failure. 2343 */ 2344 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2345 { 2346 struct stmmac_priv *priv = netdev_priv(dev); 2347 int max_mtu; 2348 2349 if (netif_running(dev)) { 2350 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2351 return -EBUSY; 2352 } 2353 2354 if (priv->plat->enh_desc) 2355 max_mtu = JUMBO_LEN; 2356 else 2357 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2358 2359 if (priv->plat->maxmtu < max_mtu) 2360 max_mtu = priv->plat->maxmtu; 2361 2362 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2363 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2364 return -EINVAL; 2365 } 2366 2367 dev->mtu = new_mtu; 2368 netdev_update_features(dev); 2369 2370 return 0; 2371 } 2372 2373 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2374 netdev_features_t features) 2375 { 2376 struct stmmac_priv *priv = netdev_priv(dev); 2377 2378 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2379 features &= ~NETIF_F_RXCSUM; 2380 2381 if (!priv->plat->tx_coe) 2382 features &= ~NETIF_F_ALL_CSUM; 2383 2384 /* Some GMAC devices have a bugged Jumbo frame support that 2385 * needs to have the Tx COE disabled for oversized frames 2386 * (due to limited buffer sizes). In this case we disable 2387 * the TX csum insertionin the TDES and not use SF. 2388 */ 2389 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2390 features &= ~NETIF_F_ALL_CSUM; 2391 2392 return features; 2393 } 2394 2395 static int stmmac_set_features(struct net_device *netdev, 2396 netdev_features_t features) 2397 { 2398 struct stmmac_priv *priv = netdev_priv(netdev); 2399 2400 /* Keep the COE Type in case of csum is supporting */ 2401 if (features & NETIF_F_RXCSUM) 2402 priv->hw->rx_csum = priv->plat->rx_coe; 2403 else 2404 priv->hw->rx_csum = 0; 2405 /* No check needed because rx_coe has been set before and it will be 2406 * fixed in case of issue. 2407 */ 2408 priv->hw->mac->rx_ipc(priv->hw); 2409 2410 return 0; 2411 } 2412 2413 /** 2414 * stmmac_interrupt - main ISR 2415 * @irq: interrupt number. 2416 * @dev_id: to pass the net device pointer. 2417 * Description: this is the main driver interrupt service routine. 2418 * It can call: 2419 * o DMA service routine (to manage incoming frame reception and transmission 2420 * status) 2421 * o Core interrupts to manage: remote wake-up, management counter, LPI 2422 * interrupts. 2423 */ 2424 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2425 { 2426 struct net_device *dev = (struct net_device *)dev_id; 2427 struct stmmac_priv *priv = netdev_priv(dev); 2428 2429 if (priv->irq_wake) 2430 pm_wakeup_event(priv->device, 0); 2431 2432 if (unlikely(!dev)) { 2433 pr_err("%s: invalid dev pointer\n", __func__); 2434 return IRQ_NONE; 2435 } 2436 2437 /* To handle GMAC own interrupts */ 2438 if (priv->plat->has_gmac) { 2439 int status = priv->hw->mac->host_irq_status(priv->hw, 2440 &priv->xstats); 2441 if (unlikely(status)) { 2442 /* For LPI we need to save the tx status */ 2443 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2444 priv->tx_path_in_lpi_mode = true; 2445 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2446 priv->tx_path_in_lpi_mode = false; 2447 } 2448 } 2449 2450 /* To handle DMA interrupts */ 2451 stmmac_dma_interrupt(priv); 2452 2453 return IRQ_HANDLED; 2454 } 2455 2456 #ifdef CONFIG_NET_POLL_CONTROLLER 2457 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2458 * to allow network I/O with interrupts disabled. 2459 */ 2460 static void stmmac_poll_controller(struct net_device *dev) 2461 { 2462 disable_irq(dev->irq); 2463 stmmac_interrupt(dev->irq, dev); 2464 enable_irq(dev->irq); 2465 } 2466 #endif 2467 2468 /** 2469 * stmmac_ioctl - Entry point for the Ioctl 2470 * @dev: Device pointer. 2471 * @rq: An IOCTL specefic structure, that can contain a pointer to 2472 * a proprietary structure used to pass information to the driver. 2473 * @cmd: IOCTL command 2474 * Description: 2475 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2476 */ 2477 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2478 { 2479 struct stmmac_priv *priv = netdev_priv(dev); 2480 int ret = -EOPNOTSUPP; 2481 2482 if (!netif_running(dev)) 2483 return -EINVAL; 2484 2485 switch (cmd) { 2486 case SIOCGMIIPHY: 2487 case SIOCGMIIREG: 2488 case SIOCSMIIREG: 2489 if (!priv->phydev) 2490 return -EINVAL; 2491 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2492 break; 2493 case SIOCSHWTSTAMP: 2494 ret = stmmac_hwtstamp_ioctl(dev, rq); 2495 break; 2496 default: 2497 break; 2498 } 2499 2500 return ret; 2501 } 2502 2503 #ifdef CONFIG_DEBUG_FS 2504 static struct dentry *stmmac_fs_dir; 2505 static struct dentry *stmmac_rings_status; 2506 static struct dentry *stmmac_dma_cap; 2507 2508 static void sysfs_display_ring(void *head, int size, int extend_desc, 2509 struct seq_file *seq) 2510 { 2511 int i; 2512 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2513 struct dma_desc *p = (struct dma_desc *)head; 2514 2515 for (i = 0; i < size; i++) { 2516 u64 x; 2517 if (extend_desc) { 2518 x = *(u64 *) ep; 2519 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2520 i, (unsigned int)virt_to_phys(ep), 2521 (unsigned int)x, (unsigned int)(x >> 32), 2522 ep->basic.des2, ep->basic.des3); 2523 ep++; 2524 } else { 2525 x = *(u64 *) p; 2526 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2527 i, (unsigned int)virt_to_phys(ep), 2528 (unsigned int)x, (unsigned int)(x >> 32), 2529 p->des2, p->des3); 2530 p++; 2531 } 2532 seq_printf(seq, "\n"); 2533 } 2534 } 2535 2536 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2537 { 2538 struct net_device *dev = seq->private; 2539 struct stmmac_priv *priv = netdev_priv(dev); 2540 unsigned int txsize = priv->dma_tx_size; 2541 unsigned int rxsize = priv->dma_rx_size; 2542 2543 if (priv->extend_desc) { 2544 seq_printf(seq, "Extended RX descriptor ring:\n"); 2545 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2546 seq_printf(seq, "Extended TX descriptor ring:\n"); 2547 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2548 } else { 2549 seq_printf(seq, "RX descriptor ring:\n"); 2550 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2551 seq_printf(seq, "TX descriptor ring:\n"); 2552 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2559 { 2560 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2561 } 2562 2563 static const struct file_operations stmmac_rings_status_fops = { 2564 .owner = THIS_MODULE, 2565 .open = stmmac_sysfs_ring_open, 2566 .read = seq_read, 2567 .llseek = seq_lseek, 2568 .release = single_release, 2569 }; 2570 2571 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2572 { 2573 struct net_device *dev = seq->private; 2574 struct stmmac_priv *priv = netdev_priv(dev); 2575 2576 if (!priv->hw_cap_support) { 2577 seq_printf(seq, "DMA HW features not supported\n"); 2578 return 0; 2579 } 2580 2581 seq_printf(seq, "==============================\n"); 2582 seq_printf(seq, "\tDMA HW features\n"); 2583 seq_printf(seq, "==============================\n"); 2584 2585 seq_printf(seq, "\t10/100 Mbps %s\n", 2586 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2587 seq_printf(seq, "\t1000 Mbps %s\n", 2588 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2589 seq_printf(seq, "\tHalf duple %s\n", 2590 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2591 seq_printf(seq, "\tHash Filter: %s\n", 2592 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2593 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2594 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2595 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2596 (priv->dma_cap.pcs) ? "Y" : "N"); 2597 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2598 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2599 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2600 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2601 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2602 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2603 seq_printf(seq, "\tRMON module: %s\n", 2604 (priv->dma_cap.rmon) ? "Y" : "N"); 2605 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2606 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2607 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2608 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2609 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2610 (priv->dma_cap.eee) ? "Y" : "N"); 2611 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2612 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2613 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2614 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2615 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2616 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2617 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2618 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2619 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2620 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2621 priv->dma_cap.number_rx_channel); 2622 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2623 priv->dma_cap.number_tx_channel); 2624 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2625 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2626 2627 return 0; 2628 } 2629 2630 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2631 { 2632 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2633 } 2634 2635 static const struct file_operations stmmac_dma_cap_fops = { 2636 .owner = THIS_MODULE, 2637 .open = stmmac_sysfs_dma_cap_open, 2638 .read = seq_read, 2639 .llseek = seq_lseek, 2640 .release = single_release, 2641 }; 2642 2643 static int stmmac_init_fs(struct net_device *dev) 2644 { 2645 /* Create debugfs entries */ 2646 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2647 2648 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2649 pr_err("ERROR %s, debugfs create directory failed\n", 2650 STMMAC_RESOURCE_NAME); 2651 2652 return -ENOMEM; 2653 } 2654 2655 /* Entry to report DMA RX/TX rings */ 2656 stmmac_rings_status = debugfs_create_file("descriptors_status", 2657 S_IRUGO, stmmac_fs_dir, dev, 2658 &stmmac_rings_status_fops); 2659 2660 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2661 pr_info("ERROR creating stmmac ring debugfs file\n"); 2662 debugfs_remove(stmmac_fs_dir); 2663 2664 return -ENOMEM; 2665 } 2666 2667 /* Entry to report the DMA HW features */ 2668 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2669 dev, &stmmac_dma_cap_fops); 2670 2671 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2672 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2673 debugfs_remove(stmmac_rings_status); 2674 debugfs_remove(stmmac_fs_dir); 2675 2676 return -ENOMEM; 2677 } 2678 2679 return 0; 2680 } 2681 2682 static void stmmac_exit_fs(void) 2683 { 2684 debugfs_remove(stmmac_rings_status); 2685 debugfs_remove(stmmac_dma_cap); 2686 debugfs_remove(stmmac_fs_dir); 2687 } 2688 #endif /* CONFIG_DEBUG_FS */ 2689 2690 static const struct net_device_ops stmmac_netdev_ops = { 2691 .ndo_open = stmmac_open, 2692 .ndo_start_xmit = stmmac_xmit, 2693 .ndo_stop = stmmac_release, 2694 .ndo_change_mtu = stmmac_change_mtu, 2695 .ndo_fix_features = stmmac_fix_features, 2696 .ndo_set_features = stmmac_set_features, 2697 .ndo_set_rx_mode = stmmac_set_rx_mode, 2698 .ndo_tx_timeout = stmmac_tx_timeout, 2699 .ndo_do_ioctl = stmmac_ioctl, 2700 #ifdef CONFIG_NET_POLL_CONTROLLER 2701 .ndo_poll_controller = stmmac_poll_controller, 2702 #endif 2703 .ndo_set_mac_address = eth_mac_addr, 2704 }; 2705 2706 /** 2707 * stmmac_hw_init - Init the MAC device 2708 * @priv: driver private structure 2709 * Description: this function is to configure the MAC device according to 2710 * some platform parameters or the HW capability register. It prepares the 2711 * driver to use either ring or chain modes and to setup either enhanced or 2712 * normal descriptors. 2713 */ 2714 static int stmmac_hw_init(struct stmmac_priv *priv) 2715 { 2716 struct mac_device_info *mac; 2717 2718 /* Identify the MAC HW device */ 2719 if (priv->plat->has_gmac) { 2720 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2721 mac = dwmac1000_setup(priv->ioaddr, 2722 priv->plat->multicast_filter_bins, 2723 priv->plat->unicast_filter_entries); 2724 } else { 2725 mac = dwmac100_setup(priv->ioaddr); 2726 } 2727 if (!mac) 2728 return -ENOMEM; 2729 2730 priv->hw = mac; 2731 2732 /* Get and dump the chip ID */ 2733 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2734 2735 /* To use the chained or ring mode */ 2736 if (chain_mode) { 2737 priv->hw->mode = &chain_mode_ops; 2738 pr_info(" Chain mode enabled\n"); 2739 priv->mode = STMMAC_CHAIN_MODE; 2740 } else { 2741 priv->hw->mode = &ring_mode_ops; 2742 pr_info(" Ring mode enabled\n"); 2743 priv->mode = STMMAC_RING_MODE; 2744 } 2745 2746 /* Get the HW capability (new GMAC newer than 3.50a) */ 2747 priv->hw_cap_support = stmmac_get_hw_features(priv); 2748 if (priv->hw_cap_support) { 2749 pr_info(" DMA HW capability register supported"); 2750 2751 /* We can override some gmac/dma configuration fields: e.g. 2752 * enh_desc, tx_coe (e.g. that are passed through the 2753 * platform) with the values from the HW capability 2754 * register (if supported). 2755 */ 2756 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2757 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2758 2759 /* TXCOE doesn't work in thresh DMA mode */ 2760 if (priv->plat->force_thresh_dma_mode) 2761 priv->plat->tx_coe = 0; 2762 else 2763 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2764 2765 if (priv->dma_cap.rx_coe_type2) 2766 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2767 else if (priv->dma_cap.rx_coe_type1) 2768 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2769 2770 } else 2771 pr_info(" No HW DMA feature register supported"); 2772 2773 /* To use alternate (extended) or normal descriptor structures */ 2774 stmmac_selec_desc_mode(priv); 2775 2776 if (priv->plat->rx_coe) { 2777 priv->hw->rx_csum = priv->plat->rx_coe; 2778 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2779 priv->plat->rx_coe); 2780 } 2781 if (priv->plat->tx_coe) 2782 pr_info(" TX Checksum insertion supported\n"); 2783 2784 if (priv->plat->pmt) { 2785 pr_info(" Wake-Up On Lan supported\n"); 2786 device_set_wakeup_capable(priv->device, 1); 2787 } 2788 2789 return 0; 2790 } 2791 2792 /** 2793 * stmmac_dvr_probe 2794 * @device: device pointer 2795 * @plat_dat: platform data pointer 2796 * @addr: iobase memory address 2797 * Description: this is the main probe function used to 2798 * call the alloc_etherdev, allocate the priv structure. 2799 * Return: 2800 * on success the new private structure is returned, otherwise the error 2801 * pointer. 2802 */ 2803 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2804 struct plat_stmmacenet_data *plat_dat, 2805 void __iomem *addr) 2806 { 2807 int ret = 0; 2808 struct net_device *ndev = NULL; 2809 struct stmmac_priv *priv; 2810 2811 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2812 if (!ndev) 2813 return ERR_PTR(-ENOMEM); 2814 2815 SET_NETDEV_DEV(ndev, device); 2816 2817 priv = netdev_priv(ndev); 2818 priv->device = device; 2819 priv->dev = ndev; 2820 2821 stmmac_set_ethtool_ops(ndev); 2822 priv->pause = pause; 2823 priv->plat = plat_dat; 2824 priv->ioaddr = addr; 2825 priv->dev->base_addr = (unsigned long)addr; 2826 2827 /* Verify driver arguments */ 2828 stmmac_verify_args(); 2829 2830 /* Override with kernel parameters if supplied XXX CRS XXX 2831 * this needs to have multiple instances 2832 */ 2833 if ((phyaddr >= 0) && (phyaddr <= 31)) 2834 priv->plat->phy_addr = phyaddr; 2835 2836 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2837 if (IS_ERR(priv->stmmac_clk)) { 2838 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2839 __func__); 2840 /* If failed to obtain stmmac_clk and specific clk_csr value 2841 * is NOT passed from the platform, probe fail. 2842 */ 2843 if (!priv->plat->clk_csr) { 2844 ret = PTR_ERR(priv->stmmac_clk); 2845 goto error_clk_get; 2846 } else { 2847 priv->stmmac_clk = NULL; 2848 } 2849 } 2850 clk_prepare_enable(priv->stmmac_clk); 2851 2852 priv->stmmac_rst = devm_reset_control_get(priv->device, 2853 STMMAC_RESOURCE_NAME); 2854 if (IS_ERR(priv->stmmac_rst)) { 2855 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2856 ret = -EPROBE_DEFER; 2857 goto error_hw_init; 2858 } 2859 dev_info(priv->device, "no reset control found\n"); 2860 priv->stmmac_rst = NULL; 2861 } 2862 if (priv->stmmac_rst) 2863 reset_control_deassert(priv->stmmac_rst); 2864 2865 /* Init MAC and get the capabilities */ 2866 ret = stmmac_hw_init(priv); 2867 if (ret) 2868 goto error_hw_init; 2869 2870 ndev->netdev_ops = &stmmac_netdev_ops; 2871 2872 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2873 NETIF_F_RXCSUM; 2874 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2875 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2876 #ifdef STMMAC_VLAN_TAG_USED 2877 /* Both mac100 and gmac support receive VLAN tag detection */ 2878 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2879 #endif 2880 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2881 2882 if (flow_ctrl) 2883 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2884 2885 /* Rx Watchdog is available in the COREs newer than the 3.40. 2886 * In some case, for example on bugged HW this feature 2887 * has to be disable and this can be done by passing the 2888 * riwt_off field from the platform. 2889 */ 2890 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2891 priv->use_riwt = 1; 2892 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2893 } 2894 2895 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2896 2897 spin_lock_init(&priv->lock); 2898 spin_lock_init(&priv->tx_lock); 2899 2900 ret = register_netdev(ndev); 2901 if (ret) { 2902 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2903 goto error_netdev_register; 2904 } 2905 2906 /* If a specific clk_csr value is passed from the platform 2907 * this means that the CSR Clock Range selection cannot be 2908 * changed at run-time and it is fixed. Viceversa the driver'll try to 2909 * set the MDC clock dynamically according to the csr actual 2910 * clock input. 2911 */ 2912 if (!priv->plat->clk_csr) 2913 stmmac_clk_csr_set(priv); 2914 else 2915 priv->clk_csr = priv->plat->clk_csr; 2916 2917 stmmac_check_pcs_mode(priv); 2918 2919 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2920 priv->pcs != STMMAC_PCS_RTBI) { 2921 /* MDIO bus Registration */ 2922 ret = stmmac_mdio_register(ndev); 2923 if (ret < 0) { 2924 pr_debug("%s: MDIO bus (id: %d) registration failed", 2925 __func__, priv->plat->bus_id); 2926 goto error_mdio_register; 2927 } 2928 } 2929 2930 return priv; 2931 2932 error_mdio_register: 2933 unregister_netdev(ndev); 2934 error_netdev_register: 2935 netif_napi_del(&priv->napi); 2936 error_hw_init: 2937 clk_disable_unprepare(priv->stmmac_clk); 2938 error_clk_get: 2939 free_netdev(ndev); 2940 2941 return ERR_PTR(ret); 2942 } 2943 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 2944 2945 /** 2946 * stmmac_dvr_remove 2947 * @ndev: net device pointer 2948 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2949 * changes the link status, releases the DMA descriptor rings. 2950 */ 2951 int stmmac_dvr_remove(struct net_device *ndev) 2952 { 2953 struct stmmac_priv *priv = netdev_priv(ndev); 2954 2955 pr_info("%s:\n\tremoving driver", __func__); 2956 2957 priv->hw->dma->stop_rx(priv->ioaddr); 2958 priv->hw->dma->stop_tx(priv->ioaddr); 2959 2960 stmmac_set_mac(priv->ioaddr, false); 2961 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2962 priv->pcs != STMMAC_PCS_RTBI) 2963 stmmac_mdio_unregister(ndev); 2964 netif_carrier_off(ndev); 2965 unregister_netdev(ndev); 2966 if (priv->stmmac_rst) 2967 reset_control_assert(priv->stmmac_rst); 2968 clk_disable_unprepare(priv->stmmac_clk); 2969 free_netdev(ndev); 2970 2971 return 0; 2972 } 2973 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 2974 2975 /** 2976 * stmmac_suspend - suspend callback 2977 * @ndev: net device pointer 2978 * Description: this is the function to suspend the device and it is called 2979 * by the platform driver to stop the network queue, release the resources, 2980 * program the PMT register (for WoL), clean and release driver resources. 2981 */ 2982 int stmmac_suspend(struct net_device *ndev) 2983 { 2984 struct stmmac_priv *priv = netdev_priv(ndev); 2985 unsigned long flags; 2986 2987 if (!ndev || !netif_running(ndev)) 2988 return 0; 2989 2990 if (priv->phydev) 2991 phy_stop(priv->phydev); 2992 2993 spin_lock_irqsave(&priv->lock, flags); 2994 2995 netif_device_detach(ndev); 2996 netif_stop_queue(ndev); 2997 2998 napi_disable(&priv->napi); 2999 3000 /* Stop TX/RX DMA */ 3001 priv->hw->dma->stop_tx(priv->ioaddr); 3002 priv->hw->dma->stop_rx(priv->ioaddr); 3003 3004 stmmac_clear_descriptors(priv); 3005 3006 /* Enable Power down mode by programming the PMT regs */ 3007 if (device_may_wakeup(priv->device)) { 3008 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3009 priv->irq_wake = 1; 3010 } else { 3011 stmmac_set_mac(priv->ioaddr, false); 3012 pinctrl_pm_select_sleep_state(priv->device); 3013 /* Disable clock in case of PWM is off */ 3014 clk_disable(priv->stmmac_clk); 3015 } 3016 spin_unlock_irqrestore(&priv->lock, flags); 3017 3018 priv->oldlink = 0; 3019 priv->speed = 0; 3020 priv->oldduplex = -1; 3021 return 0; 3022 } 3023 EXPORT_SYMBOL_GPL(stmmac_suspend); 3024 3025 /** 3026 * stmmac_resume - resume callback 3027 * @ndev: net device pointer 3028 * Description: when resume this function is invoked to setup the DMA and CORE 3029 * in a usable state. 3030 */ 3031 int stmmac_resume(struct net_device *ndev) 3032 { 3033 struct stmmac_priv *priv = netdev_priv(ndev); 3034 unsigned long flags; 3035 3036 if (!netif_running(ndev)) 3037 return 0; 3038 3039 spin_lock_irqsave(&priv->lock, flags); 3040 3041 /* Power Down bit, into the PM register, is cleared 3042 * automatically as soon as a magic packet or a Wake-up frame 3043 * is received. Anyway, it's better to manually clear 3044 * this bit because it can generate problems while resuming 3045 * from another devices (e.g. serial console). 3046 */ 3047 if (device_may_wakeup(priv->device)) { 3048 priv->hw->mac->pmt(priv->hw, 0); 3049 priv->irq_wake = 0; 3050 } else { 3051 pinctrl_pm_select_default_state(priv->device); 3052 /* enable the clk prevously disabled */ 3053 clk_enable(priv->stmmac_clk); 3054 /* reset the phy so that it's ready */ 3055 if (priv->mii) 3056 stmmac_mdio_reset(priv->mii); 3057 } 3058 3059 netif_device_attach(ndev); 3060 3061 init_dma_desc_rings(ndev, GFP_ATOMIC); 3062 stmmac_hw_setup(ndev, false); 3063 stmmac_init_tx_coalesce(priv); 3064 3065 napi_enable(&priv->napi); 3066 3067 netif_start_queue(ndev); 3068 3069 spin_unlock_irqrestore(&priv->lock, flags); 3070 3071 if (priv->phydev) 3072 phy_start(priv->phydev); 3073 3074 return 0; 3075 } 3076 EXPORT_SYMBOL_GPL(stmmac_resume); 3077 3078 #ifndef MODULE 3079 static int __init stmmac_cmdline_opt(char *str) 3080 { 3081 char *opt; 3082 3083 if (!str || !*str) 3084 return -EINVAL; 3085 while ((opt = strsep(&str, ",")) != NULL) { 3086 if (!strncmp(opt, "debug:", 6)) { 3087 if (kstrtoint(opt + 6, 0, &debug)) 3088 goto err; 3089 } else if (!strncmp(opt, "phyaddr:", 8)) { 3090 if (kstrtoint(opt + 8, 0, &phyaddr)) 3091 goto err; 3092 } else if (!strncmp(opt, "dma_txsize:", 11)) { 3093 if (kstrtoint(opt + 11, 0, &dma_txsize)) 3094 goto err; 3095 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 3096 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 3097 goto err; 3098 } else if (!strncmp(opt, "buf_sz:", 7)) { 3099 if (kstrtoint(opt + 7, 0, &buf_sz)) 3100 goto err; 3101 } else if (!strncmp(opt, "tc:", 3)) { 3102 if (kstrtoint(opt + 3, 0, &tc)) 3103 goto err; 3104 } else if (!strncmp(opt, "watchdog:", 9)) { 3105 if (kstrtoint(opt + 9, 0, &watchdog)) 3106 goto err; 3107 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3108 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3109 goto err; 3110 } else if (!strncmp(opt, "pause:", 6)) { 3111 if (kstrtoint(opt + 6, 0, &pause)) 3112 goto err; 3113 } else if (!strncmp(opt, "eee_timer:", 10)) { 3114 if (kstrtoint(opt + 10, 0, &eee_timer)) 3115 goto err; 3116 } else if (!strncmp(opt, "chain_mode:", 11)) { 3117 if (kstrtoint(opt + 11, 0, &chain_mode)) 3118 goto err; 3119 } 3120 } 3121 return 0; 3122 3123 err: 3124 pr_err("%s: ERROR broken module parameter conversion", __func__); 3125 return -EINVAL; 3126 } 3127 3128 __setup("stmmaceth=", stmmac_cmdline_opt); 3129 #endif /* MODULE */ 3130 3131 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3132 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3133 MODULE_LICENSE("GPL"); 3134