1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 55 56 /* Module parameters */ 57 #define TX_TIMEO 5000 58 static int watchdog = TX_TIMEO; 59 module_param(watchdog, int, 0644); 60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 61 62 static int debug = -1; 63 module_param(debug, int, 0644); 64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 65 66 static int phyaddr = -1; 67 module_param(phyaddr, int, 0444); 68 MODULE_PARM_DESC(phyaddr, "Physical device address"); 69 70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 72 73 /* Limit to make sure XDP TX and slow path can coexist */ 74 #define STMMAC_XSK_TX_BUDGET_MAX 256 75 #define STMMAC_TX_XSK_AVAIL 16 76 #define STMMAC_RX_FILL_BATCH 16 77 78 #define STMMAC_XDP_PASS 0 79 #define STMMAC_XDP_CONSUMED BIT(0) 80 #define STMMAC_XDP_TX BIT(1) 81 #define STMMAC_XDP_REDIRECT BIT(2) 82 83 static int flow_ctrl = FLOW_AUTO; 84 module_param(flow_ctrl, int, 0644); 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 86 87 static int pause = PAUSE_TIME; 88 module_param(pause, int, 0644); 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 90 91 #define TC_DEFAULT 64 92 static int tc = TC_DEFAULT; 93 module_param(tc, int, 0644); 94 MODULE_PARM_DESC(tc, "DMA threshold control value"); 95 96 #define DEFAULT_BUFSIZE 1536 97 static int buf_sz = DEFAULT_BUFSIZE; 98 module_param(buf_sz, int, 0644); 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 100 101 #define STMMAC_RX_COPYBREAK 256 102 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 104 NETIF_MSG_LINK | NETIF_MSG_IFUP | 105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 106 107 #define STMMAC_DEFAULT_LPI_TIMER 1000 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 109 module_param(eee_timer, int, 0644); 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 112 113 /* By default the driver will use the ring mode to manage tx and rx descriptors, 114 * but allow user to force to use the chain instead of the ring 115 */ 116 static unsigned int chain_mode; 117 module_param(chain_mode, int, 0444); 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 119 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 121 /* For MSI interrupts handling */ 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 128 129 #ifdef CONFIG_DEBUG_FS 130 static const struct net_device_ops stmmac_netdev_ops; 131 static void stmmac_init_fs(struct net_device *dev); 132 static void stmmac_exit_fs(struct net_device *dev); 133 #endif 134 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 136 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 138 { 139 int ret = 0; 140 141 if (enabled) { 142 ret = clk_prepare_enable(priv->plat->stmmac_clk); 143 if (ret) 144 return ret; 145 ret = clk_prepare_enable(priv->plat->pclk); 146 if (ret) { 147 clk_disable_unprepare(priv->plat->stmmac_clk); 148 return ret; 149 } 150 if (priv->plat->clks_config) { 151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 152 if (ret) { 153 clk_disable_unprepare(priv->plat->stmmac_clk); 154 clk_disable_unprepare(priv->plat->pclk); 155 return ret; 156 } 157 } 158 } else { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 clk_disable_unprepare(priv->plat->pclk); 161 if (priv->plat->clks_config) 162 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 163 } 164 165 return ret; 166 } 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 168 169 /** 170 * stmmac_verify_args - verify the driver parameters. 171 * Description: it checks the driver parameters and set a default in case of 172 * errors. 173 */ 174 static void stmmac_verify_args(void) 175 { 176 if (unlikely(watchdog < 0)) 177 watchdog = TX_TIMEO; 178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 179 buf_sz = DEFAULT_BUFSIZE; 180 if (unlikely(flow_ctrl > 1)) 181 flow_ctrl = FLOW_AUTO; 182 else if (likely(flow_ctrl < 0)) 183 flow_ctrl = FLOW_OFF; 184 if (unlikely((pause < 0) || (pause > 0xffff))) 185 pause = PAUSE_TIME; 186 if (eee_timer < 0) 187 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 188 } 189 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 191 { 192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 195 u32 queue; 196 197 for (queue = 0; queue < maxq; queue++) { 198 struct stmmac_channel *ch = &priv->channel[queue]; 199 200 if (stmmac_xdp_is_enabled(priv) && 201 test_bit(queue, priv->af_xdp_zc_qps)) { 202 napi_disable(&ch->rxtx_napi); 203 continue; 204 } 205 206 if (queue < rx_queues_cnt) 207 napi_disable(&ch->rx_napi); 208 if (queue < tx_queues_cnt) 209 napi_disable(&ch->tx_napi); 210 } 211 } 212 213 /** 214 * stmmac_disable_all_queues - Disable all queues 215 * @priv: driver private structure 216 */ 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 218 { 219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 220 struct stmmac_rx_queue *rx_q; 221 u32 queue; 222 223 /* synchronize_rcu() needed for pending XDP buffers to drain */ 224 for (queue = 0; queue < rx_queues_cnt; queue++) { 225 rx_q = &priv->rx_queue[queue]; 226 if (rx_q->xsk_pool) { 227 synchronize_rcu(); 228 break; 229 } 230 } 231 232 __stmmac_disable_all_queues(priv); 233 } 234 235 /** 236 * stmmac_enable_all_queues - Enable all queues 237 * @priv: driver private structure 238 */ 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 240 { 241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 244 u32 queue; 245 246 for (queue = 0; queue < maxq; queue++) { 247 struct stmmac_channel *ch = &priv->channel[queue]; 248 249 if (stmmac_xdp_is_enabled(priv) && 250 test_bit(queue, priv->af_xdp_zc_qps)) { 251 napi_enable(&ch->rxtx_napi); 252 continue; 253 } 254 255 if (queue < rx_queues_cnt) 256 napi_enable(&ch->rx_napi); 257 if (queue < tx_queues_cnt) 258 napi_enable(&ch->tx_napi); 259 } 260 } 261 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 263 { 264 if (!test_bit(STMMAC_DOWN, &priv->state) && 265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 266 queue_work(priv->wq, &priv->service_task); 267 } 268 269 static void stmmac_global_err(struct stmmac_priv *priv) 270 { 271 netif_carrier_off(priv->dev); 272 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 273 stmmac_service_event_schedule(priv); 274 } 275 276 /** 277 * stmmac_clk_csr_set - dynamically set the MDC clock 278 * @priv: driver private structure 279 * Description: this is to dynamically set the MDC clock according to the csr 280 * clock input. 281 * Note: 282 * If a specific clk_csr value is passed from the platform 283 * this means that the CSR Clock Range selection cannot be 284 * changed at run-time and it is fixed (as reported in the driver 285 * documentation). Viceversa the driver will try to set the MDC 286 * clock dynamically according to the actual clock input. 287 */ 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 289 { 290 u32 clk_rate; 291 292 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 293 294 /* Platform provided default clk_csr would be assumed valid 295 * for all other cases except for the below mentioned ones. 296 * For values higher than the IEEE 802.3 specified frequency 297 * we can not estimate the proper divider as it is not known 298 * the frequency of clk_csr_i. So we do not change the default 299 * divider. 300 */ 301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 302 if (clk_rate < CSR_F_35M) 303 priv->clk_csr = STMMAC_CSR_20_35M; 304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 305 priv->clk_csr = STMMAC_CSR_35_60M; 306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 307 priv->clk_csr = STMMAC_CSR_60_100M; 308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 309 priv->clk_csr = STMMAC_CSR_100_150M; 310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 311 priv->clk_csr = STMMAC_CSR_150_250M; 312 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 313 priv->clk_csr = STMMAC_CSR_250_300M; 314 } 315 316 if (priv->plat->has_sun8i) { 317 if (clk_rate > 160000000) 318 priv->clk_csr = 0x03; 319 else if (clk_rate > 80000000) 320 priv->clk_csr = 0x02; 321 else if (clk_rate > 40000000) 322 priv->clk_csr = 0x01; 323 else 324 priv->clk_csr = 0; 325 } 326 327 if (priv->plat->has_xgmac) { 328 if (clk_rate > 400000000) 329 priv->clk_csr = 0x5; 330 else if (clk_rate > 350000000) 331 priv->clk_csr = 0x4; 332 else if (clk_rate > 300000000) 333 priv->clk_csr = 0x3; 334 else if (clk_rate > 250000000) 335 priv->clk_csr = 0x2; 336 else if (clk_rate > 150000000) 337 priv->clk_csr = 0x1; 338 else 339 priv->clk_csr = 0x0; 340 } 341 } 342 343 static void print_pkt(unsigned char *buf, int len) 344 { 345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 347 } 348 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 350 { 351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 352 u32 avail; 353 354 if (tx_q->dirty_tx > tx_q->cur_tx) 355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 356 else 357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 358 359 return avail; 360 } 361 362 /** 363 * stmmac_rx_dirty - Get RX queue dirty 364 * @priv: driver private structure 365 * @queue: RX queue index 366 */ 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 368 { 369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 370 u32 dirty; 371 372 if (rx_q->dirty_rx <= rx_q->cur_rx) 373 dirty = rx_q->cur_rx - rx_q->dirty_rx; 374 else 375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 376 377 return dirty; 378 } 379 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 381 { 382 int tx_lpi_timer; 383 384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 385 priv->eee_sw_timer_en = en ? 0 : 1; 386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 388 } 389 390 /** 391 * stmmac_enable_eee_mode - check and enter in LPI mode 392 * @priv: driver private structure 393 * Description: this function is to verify and enter in LPI mode in case of 394 * EEE. 395 */ 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 397 { 398 u32 tx_cnt = priv->plat->tx_queues_to_use; 399 u32 queue; 400 401 /* check if all TX queues have the work finished */ 402 for (queue = 0; queue < tx_cnt; queue++) { 403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 404 405 if (tx_q->dirty_tx != tx_q->cur_tx) 406 return; /* still unfinished work */ 407 } 408 409 /* Check and enter in LPI mode */ 410 if (!priv->tx_path_in_lpi_mode) 411 stmmac_set_eee_mode(priv, priv->hw, 412 priv->plat->en_tx_lpi_clockgating); 413 } 414 415 /** 416 * stmmac_disable_eee_mode - disable and exit from LPI mode 417 * @priv: driver private structure 418 * Description: this function is to exit and disable EEE in case of 419 * LPI state is true. This is called by the xmit. 420 */ 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 422 { 423 if (!priv->eee_sw_timer_en) { 424 stmmac_lpi_entry_timer_config(priv, 0); 425 return; 426 } 427 428 stmmac_reset_eee_mode(priv, priv->hw); 429 del_timer_sync(&priv->eee_ctrl_timer); 430 priv->tx_path_in_lpi_mode = false; 431 } 432 433 /** 434 * stmmac_eee_ctrl_timer - EEE TX SW timer. 435 * @t: timer_list struct containing private info 436 * Description: 437 * if there is no data transfer and if we are not in LPI state, 438 * then MAC Transmitter can be moved to LPI state. 439 */ 440 static void stmmac_eee_ctrl_timer(struct timer_list *t) 441 { 442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 443 444 stmmac_enable_eee_mode(priv); 445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 446 } 447 448 /** 449 * stmmac_eee_init - init EEE 450 * @priv: driver private structure 451 * Description: 452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 453 * can also manage EEE, this function enable the LPI state and start related 454 * timer. 455 */ 456 bool stmmac_eee_init(struct stmmac_priv *priv) 457 { 458 int eee_tw_timer = priv->eee_tw_timer; 459 460 /* Using PCS we cannot dial with the phy registers at this stage 461 * so we do not support extra feature like EEE. 462 */ 463 if (priv->hw->pcs == STMMAC_PCS_TBI || 464 priv->hw->pcs == STMMAC_PCS_RTBI) 465 return false; 466 467 /* Check if MAC core supports the EEE feature. */ 468 if (!priv->dma_cap.eee) 469 return false; 470 471 mutex_lock(&priv->lock); 472 473 /* Check if it needs to be deactivated */ 474 if (!priv->eee_active) { 475 if (priv->eee_enabled) { 476 netdev_dbg(priv->dev, "disable EEE\n"); 477 stmmac_lpi_entry_timer_config(priv, 0); 478 del_timer_sync(&priv->eee_ctrl_timer); 479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 480 } 481 mutex_unlock(&priv->lock); 482 return false; 483 } 484 485 if (priv->eee_active && !priv->eee_enabled) { 486 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 487 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 488 eee_tw_timer); 489 } 490 491 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 492 del_timer_sync(&priv->eee_ctrl_timer); 493 priv->tx_path_in_lpi_mode = false; 494 stmmac_lpi_entry_timer_config(priv, 1); 495 } else { 496 stmmac_lpi_entry_timer_config(priv, 0); 497 mod_timer(&priv->eee_ctrl_timer, 498 STMMAC_LPI_T(priv->tx_lpi_timer)); 499 } 500 501 mutex_unlock(&priv->lock); 502 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 503 return true; 504 } 505 506 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 507 * @priv: driver private structure 508 * @p : descriptor pointer 509 * @skb : the socket buffer 510 * Description : 511 * This function will read timestamp from the descriptor & pass it to stack. 512 * and also perform some sanity checks. 513 */ 514 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 515 struct dma_desc *p, struct sk_buff *skb) 516 { 517 struct skb_shared_hwtstamps shhwtstamp; 518 bool found = false; 519 s64 adjust = 0; 520 u64 ns = 0; 521 522 if (!priv->hwts_tx_en) 523 return; 524 525 /* exit if skb doesn't support hw tstamp */ 526 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 527 return; 528 529 /* check tx tstamp status */ 530 if (stmmac_get_tx_timestamp_status(priv, p)) { 531 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 532 found = true; 533 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 534 found = true; 535 } 536 537 if (found) { 538 /* Correct the clk domain crossing(CDC) error */ 539 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 540 adjust += -(2 * (NSEC_PER_SEC / 541 priv->plat->clk_ptp_rate)); 542 ns += adjust; 543 } 544 545 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 546 shhwtstamp.hwtstamp = ns_to_ktime(ns); 547 548 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 549 /* pass tstamp to stack */ 550 skb_tstamp_tx(skb, &shhwtstamp); 551 } 552 } 553 554 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 555 * @priv: driver private structure 556 * @p : descriptor pointer 557 * @np : next descriptor pointer 558 * @skb : the socket buffer 559 * Description : 560 * This function will read received packet's timestamp from the descriptor 561 * and pass it to stack. It also perform some sanity checks. 562 */ 563 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 564 struct dma_desc *np, struct sk_buff *skb) 565 { 566 struct skb_shared_hwtstamps *shhwtstamp = NULL; 567 struct dma_desc *desc = p; 568 u64 adjust = 0; 569 u64 ns = 0; 570 571 if (!priv->hwts_rx_en) 572 return; 573 /* For GMAC4, the valid timestamp is from CTX next desc. */ 574 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 575 desc = np; 576 577 /* Check if timestamp is available */ 578 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 579 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 580 581 /* Correct the clk domain crossing(CDC) error */ 582 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 583 adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate); 584 ns -= adjust; 585 } 586 587 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 588 shhwtstamp = skb_hwtstamps(skb); 589 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 590 shhwtstamp->hwtstamp = ns_to_ktime(ns); 591 } else { 592 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 593 } 594 } 595 596 /** 597 * stmmac_hwtstamp_set - control hardware timestamping. 598 * @dev: device pointer. 599 * @ifr: An IOCTL specific structure, that can contain a pointer to 600 * a proprietary structure used to pass information to the driver. 601 * Description: 602 * This function configures the MAC to enable/disable both outgoing(TX) 603 * and incoming(RX) packets time stamping based on user input. 604 * Return Value: 605 * 0 on success and an appropriate -ve integer on failure. 606 */ 607 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 608 { 609 struct stmmac_priv *priv = netdev_priv(dev); 610 struct hwtstamp_config config; 611 struct timespec64 now; 612 u64 temp = 0; 613 u32 ptp_v2 = 0; 614 u32 tstamp_all = 0; 615 u32 ptp_over_ipv4_udp = 0; 616 u32 ptp_over_ipv6_udp = 0; 617 u32 ptp_over_ethernet = 0; 618 u32 snap_type_sel = 0; 619 u32 ts_master_en = 0; 620 u32 ts_event_en = 0; 621 u32 sec_inc = 0; 622 u32 value = 0; 623 bool xmac; 624 625 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 626 627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 628 netdev_alert(priv->dev, "No support for HW time stamping\n"); 629 priv->hwts_tx_en = 0; 630 priv->hwts_rx_en = 0; 631 632 return -EOPNOTSUPP; 633 } 634 635 if (copy_from_user(&config, ifr->ifr_data, 636 sizeof(config))) 637 return -EFAULT; 638 639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 640 __func__, config.flags, config.tx_type, config.rx_filter); 641 642 /* reserved for future extensions */ 643 if (config.flags) 644 return -EINVAL; 645 646 if (config.tx_type != HWTSTAMP_TX_OFF && 647 config.tx_type != HWTSTAMP_TX_ON) 648 return -ERANGE; 649 650 if (priv->adv_ts) { 651 switch (config.rx_filter) { 652 case HWTSTAMP_FILTER_NONE: 653 /* time stamp no incoming packet at all */ 654 config.rx_filter = HWTSTAMP_FILTER_NONE; 655 break; 656 657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 658 /* PTP v1, UDP, any kind of event packet */ 659 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 660 /* 'xmac' hardware can support Sync, Pdelay_Req and 661 * Pdelay_resp by setting bit14 and bits17/16 to 01 662 * This leaves Delay_Req timestamps out. 663 * Enable all events *and* general purpose message 664 * timestamping 665 */ 666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 669 break; 670 671 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 672 /* PTP v1, UDP, Sync packet */ 673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 674 /* take time stamp for SYNC messages only */ 675 ts_event_en = PTP_TCR_TSEVNTENA; 676 677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 679 break; 680 681 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 682 /* PTP v1, UDP, Delay_req packet */ 683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 684 /* take time stamp for Delay_Req messages only */ 685 ts_master_en = PTP_TCR_TSMSTRENA; 686 ts_event_en = PTP_TCR_TSEVNTENA; 687 688 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 689 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 690 break; 691 692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 693 /* PTP v2, UDP, any kind of event packet */ 694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 695 ptp_v2 = PTP_TCR_TSVER2ENA; 696 /* take time stamp for all event messages */ 697 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 698 699 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 700 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 701 break; 702 703 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 704 /* PTP v2, UDP, Sync packet */ 705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 706 ptp_v2 = PTP_TCR_TSVER2ENA; 707 /* take time stamp for SYNC messages only */ 708 ts_event_en = PTP_TCR_TSEVNTENA; 709 710 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 711 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 712 break; 713 714 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 715 /* PTP v2, UDP, Delay_req packet */ 716 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 717 ptp_v2 = PTP_TCR_TSVER2ENA; 718 /* take time stamp for Delay_Req messages only */ 719 ts_master_en = PTP_TCR_TSMSTRENA; 720 ts_event_en = PTP_TCR_TSEVNTENA; 721 722 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 723 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 724 break; 725 726 case HWTSTAMP_FILTER_PTP_V2_EVENT: 727 /* PTP v2/802.AS1 any layer, any kind of event packet */ 728 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 729 ptp_v2 = PTP_TCR_TSVER2ENA; 730 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 731 if (priv->synopsys_id != DWMAC_CORE_5_10) 732 ts_event_en = PTP_TCR_TSEVNTENA; 733 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 734 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 735 ptp_over_ethernet = PTP_TCR_TSIPENA; 736 break; 737 738 case HWTSTAMP_FILTER_PTP_V2_SYNC: 739 /* PTP v2/802.AS1, any layer, Sync packet */ 740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 741 ptp_v2 = PTP_TCR_TSVER2ENA; 742 /* take time stamp for SYNC messages only */ 743 ts_event_en = PTP_TCR_TSEVNTENA; 744 745 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 746 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 747 ptp_over_ethernet = PTP_TCR_TSIPENA; 748 break; 749 750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 751 /* PTP v2/802.AS1, any layer, Delay_req packet */ 752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 753 ptp_v2 = PTP_TCR_TSVER2ENA; 754 /* take time stamp for Delay_Req messages only */ 755 ts_master_en = PTP_TCR_TSMSTRENA; 756 ts_event_en = PTP_TCR_TSEVNTENA; 757 758 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 759 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 760 ptp_over_ethernet = PTP_TCR_TSIPENA; 761 break; 762 763 case HWTSTAMP_FILTER_NTP_ALL: 764 case HWTSTAMP_FILTER_ALL: 765 /* time stamp any incoming packet */ 766 config.rx_filter = HWTSTAMP_FILTER_ALL; 767 tstamp_all = PTP_TCR_TSENALL; 768 break; 769 770 default: 771 return -ERANGE; 772 } 773 } else { 774 switch (config.rx_filter) { 775 case HWTSTAMP_FILTER_NONE: 776 config.rx_filter = HWTSTAMP_FILTER_NONE; 777 break; 778 default: 779 /* PTP v1, UDP, any kind of event packet */ 780 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 781 break; 782 } 783 } 784 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 785 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 786 787 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 788 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 789 else { 790 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 791 tstamp_all | ptp_v2 | ptp_over_ethernet | 792 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 793 ts_master_en | snap_type_sel); 794 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 795 796 /* program Sub Second Increment reg */ 797 stmmac_config_sub_second_increment(priv, 798 priv->ptpaddr, priv->plat->clk_ptp_rate, 799 xmac, &sec_inc); 800 temp = div_u64(1000000000ULL, sec_inc); 801 802 /* Store sub second increment and flags for later use */ 803 priv->sub_second_inc = sec_inc; 804 priv->systime_flags = value; 805 806 /* calculate default added value: 807 * formula is : 808 * addend = (2^32)/freq_div_ratio; 809 * where, freq_div_ratio = 1e9ns/sec_inc 810 */ 811 temp = (u64)(temp << 32); 812 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 813 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 814 815 /* initialize system time */ 816 ktime_get_real_ts64(&now); 817 818 /* lower 32 bits of tv_sec are safe until y2106 */ 819 stmmac_init_systime(priv, priv->ptpaddr, 820 (u32)now.tv_sec, now.tv_nsec); 821 } 822 823 memcpy(&priv->tstamp_config, &config, sizeof(config)); 824 825 return copy_to_user(ifr->ifr_data, &config, 826 sizeof(config)) ? -EFAULT : 0; 827 } 828 829 /** 830 * stmmac_hwtstamp_get - read hardware timestamping. 831 * @dev: device pointer. 832 * @ifr: An IOCTL specific structure, that can contain a pointer to 833 * a proprietary structure used to pass information to the driver. 834 * Description: 835 * This function obtain the current hardware timestamping settings 836 * as requested. 837 */ 838 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 839 { 840 struct stmmac_priv *priv = netdev_priv(dev); 841 struct hwtstamp_config *config = &priv->tstamp_config; 842 843 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 844 return -EOPNOTSUPP; 845 846 return copy_to_user(ifr->ifr_data, config, 847 sizeof(*config)) ? -EFAULT : 0; 848 } 849 850 /** 851 * stmmac_init_ptp - init PTP 852 * @priv: driver private structure 853 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 854 * This is done by looking at the HW cap. register. 855 * This function also registers the ptp driver. 856 */ 857 static int stmmac_init_ptp(struct stmmac_priv *priv) 858 { 859 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 860 861 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 862 return -EOPNOTSUPP; 863 864 priv->adv_ts = 0; 865 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 866 if (xmac && priv->dma_cap.atime_stamp) 867 priv->adv_ts = 1; 868 /* Dwmac 3.x core with extend_desc can support adv_ts */ 869 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 870 priv->adv_ts = 1; 871 872 if (priv->dma_cap.time_stamp) 873 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 874 875 if (priv->adv_ts) 876 netdev_info(priv->dev, 877 "IEEE 1588-2008 Advanced Timestamp supported\n"); 878 879 priv->hwts_tx_en = 0; 880 priv->hwts_rx_en = 0; 881 882 stmmac_ptp_register(priv); 883 884 return 0; 885 } 886 887 static void stmmac_release_ptp(struct stmmac_priv *priv) 888 { 889 clk_disable_unprepare(priv->plat->clk_ptp_ref); 890 stmmac_ptp_unregister(priv); 891 } 892 893 /** 894 * stmmac_mac_flow_ctrl - Configure flow control in all queues 895 * @priv: driver private structure 896 * @duplex: duplex passed to the next function 897 * Description: It is used for configuring the flow control in all queues 898 */ 899 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 900 { 901 u32 tx_cnt = priv->plat->tx_queues_to_use; 902 903 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 904 priv->pause, tx_cnt); 905 } 906 907 static void stmmac_validate(struct phylink_config *config, 908 unsigned long *supported, 909 struct phylink_link_state *state) 910 { 911 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 912 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 913 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 914 int tx_cnt = priv->plat->tx_queues_to_use; 915 int max_speed = priv->plat->max_speed; 916 917 phylink_set(mac_supported, 10baseT_Half); 918 phylink_set(mac_supported, 10baseT_Full); 919 phylink_set(mac_supported, 100baseT_Half); 920 phylink_set(mac_supported, 100baseT_Full); 921 phylink_set(mac_supported, 1000baseT_Half); 922 phylink_set(mac_supported, 1000baseT_Full); 923 phylink_set(mac_supported, 1000baseKX_Full); 924 925 phylink_set(mac_supported, Autoneg); 926 phylink_set(mac_supported, Pause); 927 phylink_set(mac_supported, Asym_Pause); 928 phylink_set_port_modes(mac_supported); 929 930 /* Cut down 1G if asked to */ 931 if ((max_speed > 0) && (max_speed < 1000)) { 932 phylink_set(mask, 1000baseT_Full); 933 phylink_set(mask, 1000baseX_Full); 934 } else if (priv->plat->has_xgmac) { 935 if (!max_speed || (max_speed >= 2500)) { 936 phylink_set(mac_supported, 2500baseT_Full); 937 phylink_set(mac_supported, 2500baseX_Full); 938 } 939 if (!max_speed || (max_speed >= 5000)) { 940 phylink_set(mac_supported, 5000baseT_Full); 941 } 942 if (!max_speed || (max_speed >= 10000)) { 943 phylink_set(mac_supported, 10000baseSR_Full); 944 phylink_set(mac_supported, 10000baseLR_Full); 945 phylink_set(mac_supported, 10000baseER_Full); 946 phylink_set(mac_supported, 10000baseLRM_Full); 947 phylink_set(mac_supported, 10000baseT_Full); 948 phylink_set(mac_supported, 10000baseKX4_Full); 949 phylink_set(mac_supported, 10000baseKR_Full); 950 } 951 if (!max_speed || (max_speed >= 25000)) { 952 phylink_set(mac_supported, 25000baseCR_Full); 953 phylink_set(mac_supported, 25000baseKR_Full); 954 phylink_set(mac_supported, 25000baseSR_Full); 955 } 956 if (!max_speed || (max_speed >= 40000)) { 957 phylink_set(mac_supported, 40000baseKR4_Full); 958 phylink_set(mac_supported, 40000baseCR4_Full); 959 phylink_set(mac_supported, 40000baseSR4_Full); 960 phylink_set(mac_supported, 40000baseLR4_Full); 961 } 962 if (!max_speed || (max_speed >= 50000)) { 963 phylink_set(mac_supported, 50000baseCR2_Full); 964 phylink_set(mac_supported, 50000baseKR2_Full); 965 phylink_set(mac_supported, 50000baseSR2_Full); 966 phylink_set(mac_supported, 50000baseKR_Full); 967 phylink_set(mac_supported, 50000baseSR_Full); 968 phylink_set(mac_supported, 50000baseCR_Full); 969 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 970 phylink_set(mac_supported, 50000baseDR_Full); 971 } 972 if (!max_speed || (max_speed >= 100000)) { 973 phylink_set(mac_supported, 100000baseKR4_Full); 974 phylink_set(mac_supported, 100000baseSR4_Full); 975 phylink_set(mac_supported, 100000baseCR4_Full); 976 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 977 phylink_set(mac_supported, 100000baseKR2_Full); 978 phylink_set(mac_supported, 100000baseSR2_Full); 979 phylink_set(mac_supported, 100000baseCR2_Full); 980 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 981 phylink_set(mac_supported, 100000baseDR2_Full); 982 } 983 } 984 985 /* Half-Duplex can only work with single queue */ 986 if (tx_cnt > 1) { 987 phylink_set(mask, 10baseT_Half); 988 phylink_set(mask, 100baseT_Half); 989 phylink_set(mask, 1000baseT_Half); 990 } 991 992 linkmode_and(supported, supported, mac_supported); 993 linkmode_andnot(supported, supported, mask); 994 995 linkmode_and(state->advertising, state->advertising, mac_supported); 996 linkmode_andnot(state->advertising, state->advertising, mask); 997 998 /* If PCS is supported, check which modes it supports. */ 999 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 1000 } 1001 1002 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 1003 struct phylink_link_state *state) 1004 { 1005 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1006 1007 state->link = 0; 1008 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 1009 } 1010 1011 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 1012 const struct phylink_link_state *state) 1013 { 1014 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1015 1016 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 1017 } 1018 1019 static void stmmac_mac_an_restart(struct phylink_config *config) 1020 { 1021 /* Not Supported */ 1022 } 1023 1024 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 1025 { 1026 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 1027 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 1028 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 1029 bool *hs_enable = &fpe_cfg->hs_enable; 1030 1031 if (is_up && *hs_enable) { 1032 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 1033 } else { 1034 *lo_state = FPE_EVENT_UNKNOWN; 1035 *lp_state = FPE_EVENT_UNKNOWN; 1036 } 1037 } 1038 1039 static void stmmac_mac_link_down(struct phylink_config *config, 1040 unsigned int mode, phy_interface_t interface) 1041 { 1042 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1043 1044 stmmac_mac_set(priv, priv->ioaddr, false); 1045 priv->eee_active = false; 1046 priv->tx_lpi_enabled = false; 1047 stmmac_eee_init(priv); 1048 stmmac_set_eee_pls(priv, priv->hw, false); 1049 1050 if (priv->dma_cap.fpesel) 1051 stmmac_fpe_link_state_handle(priv, false); 1052 } 1053 1054 static void stmmac_mac_link_up(struct phylink_config *config, 1055 struct phy_device *phy, 1056 unsigned int mode, phy_interface_t interface, 1057 int speed, int duplex, 1058 bool tx_pause, bool rx_pause) 1059 { 1060 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1061 u32 ctrl; 1062 1063 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 1064 1065 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 1066 ctrl &= ~priv->hw->link.speed_mask; 1067 1068 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1069 switch (speed) { 1070 case SPEED_10000: 1071 ctrl |= priv->hw->link.xgmii.speed10000; 1072 break; 1073 case SPEED_5000: 1074 ctrl |= priv->hw->link.xgmii.speed5000; 1075 break; 1076 case SPEED_2500: 1077 ctrl |= priv->hw->link.xgmii.speed2500; 1078 break; 1079 default: 1080 return; 1081 } 1082 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1083 switch (speed) { 1084 case SPEED_100000: 1085 ctrl |= priv->hw->link.xlgmii.speed100000; 1086 break; 1087 case SPEED_50000: 1088 ctrl |= priv->hw->link.xlgmii.speed50000; 1089 break; 1090 case SPEED_40000: 1091 ctrl |= priv->hw->link.xlgmii.speed40000; 1092 break; 1093 case SPEED_25000: 1094 ctrl |= priv->hw->link.xlgmii.speed25000; 1095 break; 1096 case SPEED_10000: 1097 ctrl |= priv->hw->link.xgmii.speed10000; 1098 break; 1099 case SPEED_2500: 1100 ctrl |= priv->hw->link.speed2500; 1101 break; 1102 case SPEED_1000: 1103 ctrl |= priv->hw->link.speed1000; 1104 break; 1105 default: 1106 return; 1107 } 1108 } else { 1109 switch (speed) { 1110 case SPEED_2500: 1111 ctrl |= priv->hw->link.speed2500; 1112 break; 1113 case SPEED_1000: 1114 ctrl |= priv->hw->link.speed1000; 1115 break; 1116 case SPEED_100: 1117 ctrl |= priv->hw->link.speed100; 1118 break; 1119 case SPEED_10: 1120 ctrl |= priv->hw->link.speed10; 1121 break; 1122 default: 1123 return; 1124 } 1125 } 1126 1127 priv->speed = speed; 1128 1129 if (priv->plat->fix_mac_speed) 1130 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1131 1132 if (!duplex) 1133 ctrl &= ~priv->hw->link.duplex; 1134 else 1135 ctrl |= priv->hw->link.duplex; 1136 1137 /* Flow Control operation */ 1138 if (tx_pause && rx_pause) 1139 stmmac_mac_flow_ctrl(priv, duplex); 1140 1141 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1142 1143 stmmac_mac_set(priv, priv->ioaddr, true); 1144 if (phy && priv->dma_cap.eee) { 1145 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1146 priv->eee_enabled = stmmac_eee_init(priv); 1147 priv->tx_lpi_enabled = priv->eee_enabled; 1148 stmmac_set_eee_pls(priv, priv->hw, true); 1149 } 1150 1151 if (priv->dma_cap.fpesel) 1152 stmmac_fpe_link_state_handle(priv, true); 1153 } 1154 1155 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1156 .validate = stmmac_validate, 1157 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1158 .mac_config = stmmac_mac_config, 1159 .mac_an_restart = stmmac_mac_an_restart, 1160 .mac_link_down = stmmac_mac_link_down, 1161 .mac_link_up = stmmac_mac_link_up, 1162 }; 1163 1164 /** 1165 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1166 * @priv: driver private structure 1167 * Description: this is to verify if the HW supports the PCS. 1168 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1169 * configured for the TBI, RTBI, or SGMII PHY interface. 1170 */ 1171 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1172 { 1173 int interface = priv->plat->interface; 1174 1175 if (priv->dma_cap.pcs) { 1176 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1177 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1178 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1179 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1180 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1181 priv->hw->pcs = STMMAC_PCS_RGMII; 1182 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1183 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1184 priv->hw->pcs = STMMAC_PCS_SGMII; 1185 } 1186 } 1187 } 1188 1189 /** 1190 * stmmac_init_phy - PHY initialization 1191 * @dev: net device structure 1192 * Description: it initializes the driver's PHY state, and attaches the PHY 1193 * to the mac driver. 1194 * Return value: 1195 * 0 on success 1196 */ 1197 static int stmmac_init_phy(struct net_device *dev) 1198 { 1199 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1200 struct stmmac_priv *priv = netdev_priv(dev); 1201 struct device_node *node; 1202 int ret; 1203 1204 node = priv->plat->phylink_node; 1205 1206 if (node) 1207 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1208 1209 /* Some DT bindings do not set-up the PHY handle. Let's try to 1210 * manually parse it 1211 */ 1212 if (!node || ret) { 1213 int addr = priv->plat->phy_addr; 1214 struct phy_device *phydev; 1215 1216 phydev = mdiobus_get_phy(priv->mii, addr); 1217 if (!phydev) { 1218 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1219 return -ENODEV; 1220 } 1221 1222 ret = phylink_connect_phy(priv->phylink, phydev); 1223 } 1224 1225 phylink_ethtool_get_wol(priv->phylink, &wol); 1226 device_set_wakeup_capable(priv->device, !!wol.supported); 1227 1228 return ret; 1229 } 1230 1231 static int stmmac_phy_setup(struct stmmac_priv *priv) 1232 { 1233 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1234 int mode = priv->plat->phy_interface; 1235 struct phylink *phylink; 1236 1237 priv->phylink_config.dev = &priv->dev->dev; 1238 priv->phylink_config.type = PHYLINK_NETDEV; 1239 priv->phylink_config.pcs_poll = true; 1240 priv->phylink_config.ovr_an_inband = 1241 priv->plat->mdio_bus_data->xpcs_an_inband; 1242 1243 if (!fwnode) 1244 fwnode = dev_fwnode(priv->device); 1245 1246 phylink = phylink_create(&priv->phylink_config, fwnode, 1247 mode, &stmmac_phylink_mac_ops); 1248 if (IS_ERR(phylink)) 1249 return PTR_ERR(phylink); 1250 1251 priv->phylink = phylink; 1252 return 0; 1253 } 1254 1255 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1256 { 1257 u32 rx_cnt = priv->plat->rx_queues_to_use; 1258 unsigned int desc_size; 1259 void *head_rx; 1260 u32 queue; 1261 1262 /* Display RX rings */ 1263 for (queue = 0; queue < rx_cnt; queue++) { 1264 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1265 1266 pr_info("\tRX Queue %u rings\n", queue); 1267 1268 if (priv->extend_desc) { 1269 head_rx = (void *)rx_q->dma_erx; 1270 desc_size = sizeof(struct dma_extended_desc); 1271 } else { 1272 head_rx = (void *)rx_q->dma_rx; 1273 desc_size = sizeof(struct dma_desc); 1274 } 1275 1276 /* Display RX ring */ 1277 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1278 rx_q->dma_rx_phy, desc_size); 1279 } 1280 } 1281 1282 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1283 { 1284 u32 tx_cnt = priv->plat->tx_queues_to_use; 1285 unsigned int desc_size; 1286 void *head_tx; 1287 u32 queue; 1288 1289 /* Display TX rings */ 1290 for (queue = 0; queue < tx_cnt; queue++) { 1291 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1292 1293 pr_info("\tTX Queue %d rings\n", queue); 1294 1295 if (priv->extend_desc) { 1296 head_tx = (void *)tx_q->dma_etx; 1297 desc_size = sizeof(struct dma_extended_desc); 1298 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1299 head_tx = (void *)tx_q->dma_entx; 1300 desc_size = sizeof(struct dma_edesc); 1301 } else { 1302 head_tx = (void *)tx_q->dma_tx; 1303 desc_size = sizeof(struct dma_desc); 1304 } 1305 1306 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1307 tx_q->dma_tx_phy, desc_size); 1308 } 1309 } 1310 1311 static void stmmac_display_rings(struct stmmac_priv *priv) 1312 { 1313 /* Display RX ring */ 1314 stmmac_display_rx_rings(priv); 1315 1316 /* Display TX ring */ 1317 stmmac_display_tx_rings(priv); 1318 } 1319 1320 static int stmmac_set_bfsize(int mtu, int bufsize) 1321 { 1322 int ret = bufsize; 1323 1324 if (mtu >= BUF_SIZE_8KiB) 1325 ret = BUF_SIZE_16KiB; 1326 else if (mtu >= BUF_SIZE_4KiB) 1327 ret = BUF_SIZE_8KiB; 1328 else if (mtu >= BUF_SIZE_2KiB) 1329 ret = BUF_SIZE_4KiB; 1330 else if (mtu > DEFAULT_BUFSIZE) 1331 ret = BUF_SIZE_2KiB; 1332 else 1333 ret = DEFAULT_BUFSIZE; 1334 1335 return ret; 1336 } 1337 1338 /** 1339 * stmmac_clear_rx_descriptors - clear RX descriptors 1340 * @priv: driver private structure 1341 * @queue: RX queue index 1342 * Description: this function is called to clear the RX descriptors 1343 * in case of both basic and extended descriptors are used. 1344 */ 1345 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1346 { 1347 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1348 int i; 1349 1350 /* Clear the RX descriptors */ 1351 for (i = 0; i < priv->dma_rx_size; i++) 1352 if (priv->extend_desc) 1353 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1354 priv->use_riwt, priv->mode, 1355 (i == priv->dma_rx_size - 1), 1356 priv->dma_buf_sz); 1357 else 1358 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1359 priv->use_riwt, priv->mode, 1360 (i == priv->dma_rx_size - 1), 1361 priv->dma_buf_sz); 1362 } 1363 1364 /** 1365 * stmmac_clear_tx_descriptors - clear tx descriptors 1366 * @priv: driver private structure 1367 * @queue: TX queue index. 1368 * Description: this function is called to clear the TX descriptors 1369 * in case of both basic and extended descriptors are used. 1370 */ 1371 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1372 { 1373 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1374 int i; 1375 1376 /* Clear the TX descriptors */ 1377 for (i = 0; i < priv->dma_tx_size; i++) { 1378 int last = (i == (priv->dma_tx_size - 1)); 1379 struct dma_desc *p; 1380 1381 if (priv->extend_desc) 1382 p = &tx_q->dma_etx[i].basic; 1383 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1384 p = &tx_q->dma_entx[i].basic; 1385 else 1386 p = &tx_q->dma_tx[i]; 1387 1388 stmmac_init_tx_desc(priv, p, priv->mode, last); 1389 } 1390 } 1391 1392 /** 1393 * stmmac_clear_descriptors - clear descriptors 1394 * @priv: driver private structure 1395 * Description: this function is called to clear the TX and RX descriptors 1396 * in case of both basic and extended descriptors are used. 1397 */ 1398 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1399 { 1400 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1401 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1402 u32 queue; 1403 1404 /* Clear the RX descriptors */ 1405 for (queue = 0; queue < rx_queue_cnt; queue++) 1406 stmmac_clear_rx_descriptors(priv, queue); 1407 1408 /* Clear the TX descriptors */ 1409 for (queue = 0; queue < tx_queue_cnt; queue++) 1410 stmmac_clear_tx_descriptors(priv, queue); 1411 } 1412 1413 /** 1414 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1415 * @priv: driver private structure 1416 * @p: descriptor pointer 1417 * @i: descriptor index 1418 * @flags: gfp flag 1419 * @queue: RX queue index 1420 * Description: this function is called to allocate a receive buffer, perform 1421 * the DMA mapping and init the descriptor. 1422 */ 1423 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1424 int i, gfp_t flags, u32 queue) 1425 { 1426 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1427 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1428 1429 if (!buf->page) { 1430 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1431 if (!buf->page) 1432 return -ENOMEM; 1433 buf->page_offset = stmmac_rx_offset(priv); 1434 } 1435 1436 if (priv->sph && !buf->sec_page) { 1437 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1438 if (!buf->sec_page) 1439 return -ENOMEM; 1440 1441 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1442 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1443 } else { 1444 buf->sec_page = NULL; 1445 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1446 } 1447 1448 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1449 1450 stmmac_set_desc_addr(priv, p, buf->addr); 1451 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1452 stmmac_init_desc3(priv, p); 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * stmmac_free_rx_buffer - free RX dma buffers 1459 * @priv: private structure 1460 * @queue: RX queue index 1461 * @i: buffer index. 1462 */ 1463 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1464 { 1465 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1466 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1467 1468 if (buf->page) 1469 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1470 buf->page = NULL; 1471 1472 if (buf->sec_page) 1473 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1474 buf->sec_page = NULL; 1475 } 1476 1477 /** 1478 * stmmac_free_tx_buffer - free RX dma buffers 1479 * @priv: private structure 1480 * @queue: RX queue index 1481 * @i: buffer index. 1482 */ 1483 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1484 { 1485 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1486 1487 if (tx_q->tx_skbuff_dma[i].buf && 1488 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1489 if (tx_q->tx_skbuff_dma[i].map_as_page) 1490 dma_unmap_page(priv->device, 1491 tx_q->tx_skbuff_dma[i].buf, 1492 tx_q->tx_skbuff_dma[i].len, 1493 DMA_TO_DEVICE); 1494 else 1495 dma_unmap_single(priv->device, 1496 tx_q->tx_skbuff_dma[i].buf, 1497 tx_q->tx_skbuff_dma[i].len, 1498 DMA_TO_DEVICE); 1499 } 1500 1501 if (tx_q->xdpf[i] && 1502 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1503 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1504 xdp_return_frame(tx_q->xdpf[i]); 1505 tx_q->xdpf[i] = NULL; 1506 } 1507 1508 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1509 tx_q->xsk_frames_done++; 1510 1511 if (tx_q->tx_skbuff[i] && 1512 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1513 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1514 tx_q->tx_skbuff[i] = NULL; 1515 } 1516 1517 tx_q->tx_skbuff_dma[i].buf = 0; 1518 tx_q->tx_skbuff_dma[i].map_as_page = false; 1519 } 1520 1521 /** 1522 * dma_free_rx_skbufs - free RX dma buffers 1523 * @priv: private structure 1524 * @queue: RX queue index 1525 */ 1526 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1527 { 1528 int i; 1529 1530 for (i = 0; i < priv->dma_rx_size; i++) 1531 stmmac_free_rx_buffer(priv, queue, i); 1532 } 1533 1534 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, 1535 gfp_t flags) 1536 { 1537 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1538 int i; 1539 1540 for (i = 0; i < priv->dma_rx_size; i++) { 1541 struct dma_desc *p; 1542 int ret; 1543 1544 if (priv->extend_desc) 1545 p = &((rx_q->dma_erx + i)->basic); 1546 else 1547 p = rx_q->dma_rx + i; 1548 1549 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1550 queue); 1551 if (ret) 1552 return ret; 1553 1554 rx_q->buf_alloc_num++; 1555 } 1556 1557 return 0; 1558 } 1559 1560 /** 1561 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1562 * @priv: private structure 1563 * @queue: RX queue index 1564 */ 1565 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) 1566 { 1567 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1568 int i; 1569 1570 for (i = 0; i < priv->dma_rx_size; i++) { 1571 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1572 1573 if (!buf->xdp) 1574 continue; 1575 1576 xsk_buff_free(buf->xdp); 1577 buf->xdp = NULL; 1578 } 1579 } 1580 1581 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) 1582 { 1583 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1584 int i; 1585 1586 for (i = 0; i < priv->dma_rx_size; i++) { 1587 struct stmmac_rx_buffer *buf; 1588 dma_addr_t dma_addr; 1589 struct dma_desc *p; 1590 1591 if (priv->extend_desc) 1592 p = (struct dma_desc *)(rx_q->dma_erx + i); 1593 else 1594 p = rx_q->dma_rx + i; 1595 1596 buf = &rx_q->buf_pool[i]; 1597 1598 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1599 if (!buf->xdp) 1600 return -ENOMEM; 1601 1602 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1603 stmmac_set_desc_addr(priv, p, dma_addr); 1604 rx_q->buf_alloc_num++; 1605 } 1606 1607 return 0; 1608 } 1609 1610 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1611 { 1612 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1613 return NULL; 1614 1615 return xsk_get_pool_from_qid(priv->dev, queue); 1616 } 1617 1618 /** 1619 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1620 * @priv: driver private structure 1621 * @queue: RX queue index 1622 * @flags: gfp flag. 1623 * Description: this function initializes the DMA RX descriptors 1624 * and allocates the socket buffers. It supports the chained and ring 1625 * modes. 1626 */ 1627 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) 1628 { 1629 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1630 int ret; 1631 1632 netif_dbg(priv, probe, priv->dev, 1633 "(%s) dma_rx_phy=0x%08x\n", __func__, 1634 (u32)rx_q->dma_rx_phy); 1635 1636 stmmac_clear_rx_descriptors(priv, queue); 1637 1638 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1639 1640 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1641 1642 if (rx_q->xsk_pool) { 1643 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1644 MEM_TYPE_XSK_BUFF_POOL, 1645 NULL)); 1646 netdev_info(priv->dev, 1647 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1648 rx_q->queue_index); 1649 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1650 } else { 1651 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1652 MEM_TYPE_PAGE_POOL, 1653 rx_q->page_pool)); 1654 netdev_info(priv->dev, 1655 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1656 rx_q->queue_index); 1657 } 1658 1659 if (rx_q->xsk_pool) { 1660 /* RX XDP ZC buffer pool may not be populated, e.g. 1661 * xdpsock TX-only. 1662 */ 1663 stmmac_alloc_rx_buffers_zc(priv, queue); 1664 } else { 1665 ret = stmmac_alloc_rx_buffers(priv, queue, flags); 1666 if (ret < 0) 1667 return -ENOMEM; 1668 } 1669 1670 rx_q->cur_rx = 0; 1671 rx_q->dirty_rx = 0; 1672 1673 /* Setup the chained descriptor addresses */ 1674 if (priv->mode == STMMAC_CHAIN_MODE) { 1675 if (priv->extend_desc) 1676 stmmac_mode_init(priv, rx_q->dma_erx, 1677 rx_q->dma_rx_phy, 1678 priv->dma_rx_size, 1); 1679 else 1680 stmmac_mode_init(priv, rx_q->dma_rx, 1681 rx_q->dma_rx_phy, 1682 priv->dma_rx_size, 0); 1683 } 1684 1685 return 0; 1686 } 1687 1688 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1689 { 1690 struct stmmac_priv *priv = netdev_priv(dev); 1691 u32 rx_count = priv->plat->rx_queues_to_use; 1692 u32 queue; 1693 int ret; 1694 1695 /* RX INITIALIZATION */ 1696 netif_dbg(priv, probe, priv->dev, 1697 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1698 1699 for (queue = 0; queue < rx_count; queue++) { 1700 ret = __init_dma_rx_desc_rings(priv, queue, flags); 1701 if (ret) 1702 goto err_init_rx_buffers; 1703 } 1704 1705 return 0; 1706 1707 err_init_rx_buffers: 1708 while (queue >= 0) { 1709 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1710 1711 if (rx_q->xsk_pool) 1712 dma_free_rx_xskbufs(priv, queue); 1713 else 1714 dma_free_rx_skbufs(priv, queue); 1715 1716 rx_q->buf_alloc_num = 0; 1717 rx_q->xsk_pool = NULL; 1718 1719 if (queue == 0) 1720 break; 1721 1722 queue--; 1723 } 1724 1725 return ret; 1726 } 1727 1728 /** 1729 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1730 * @priv: driver private structure 1731 * @queue : TX queue index 1732 * Description: this function initializes the DMA TX descriptors 1733 * and allocates the socket buffers. It supports the chained and ring 1734 * modes. 1735 */ 1736 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) 1737 { 1738 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1739 int i; 1740 1741 netif_dbg(priv, probe, priv->dev, 1742 "(%s) dma_tx_phy=0x%08x\n", __func__, 1743 (u32)tx_q->dma_tx_phy); 1744 1745 /* Setup the chained descriptor addresses */ 1746 if (priv->mode == STMMAC_CHAIN_MODE) { 1747 if (priv->extend_desc) 1748 stmmac_mode_init(priv, tx_q->dma_etx, 1749 tx_q->dma_tx_phy, 1750 priv->dma_tx_size, 1); 1751 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1752 stmmac_mode_init(priv, tx_q->dma_tx, 1753 tx_q->dma_tx_phy, 1754 priv->dma_tx_size, 0); 1755 } 1756 1757 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1758 1759 for (i = 0; i < priv->dma_tx_size; i++) { 1760 struct dma_desc *p; 1761 1762 if (priv->extend_desc) 1763 p = &((tx_q->dma_etx + i)->basic); 1764 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1765 p = &((tx_q->dma_entx + i)->basic); 1766 else 1767 p = tx_q->dma_tx + i; 1768 1769 stmmac_clear_desc(priv, p); 1770 1771 tx_q->tx_skbuff_dma[i].buf = 0; 1772 tx_q->tx_skbuff_dma[i].map_as_page = false; 1773 tx_q->tx_skbuff_dma[i].len = 0; 1774 tx_q->tx_skbuff_dma[i].last_segment = false; 1775 tx_q->tx_skbuff[i] = NULL; 1776 } 1777 1778 tx_q->dirty_tx = 0; 1779 tx_q->cur_tx = 0; 1780 tx_q->mss = 0; 1781 1782 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1783 1784 return 0; 1785 } 1786 1787 static int init_dma_tx_desc_rings(struct net_device *dev) 1788 { 1789 struct stmmac_priv *priv = netdev_priv(dev); 1790 u32 tx_queue_cnt; 1791 u32 queue; 1792 1793 tx_queue_cnt = priv->plat->tx_queues_to_use; 1794 1795 for (queue = 0; queue < tx_queue_cnt; queue++) 1796 __init_dma_tx_desc_rings(priv, queue); 1797 1798 return 0; 1799 } 1800 1801 /** 1802 * init_dma_desc_rings - init the RX/TX descriptor rings 1803 * @dev: net device structure 1804 * @flags: gfp flag. 1805 * Description: this function initializes the DMA RX/TX descriptors 1806 * and allocates the socket buffers. It supports the chained and ring 1807 * modes. 1808 */ 1809 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1810 { 1811 struct stmmac_priv *priv = netdev_priv(dev); 1812 int ret; 1813 1814 ret = init_dma_rx_desc_rings(dev, flags); 1815 if (ret) 1816 return ret; 1817 1818 ret = init_dma_tx_desc_rings(dev); 1819 1820 stmmac_clear_descriptors(priv); 1821 1822 if (netif_msg_hw(priv)) 1823 stmmac_display_rings(priv); 1824 1825 return ret; 1826 } 1827 1828 /** 1829 * dma_free_tx_skbufs - free TX dma buffers 1830 * @priv: private structure 1831 * @queue: TX queue index 1832 */ 1833 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1834 { 1835 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1836 int i; 1837 1838 tx_q->xsk_frames_done = 0; 1839 1840 for (i = 0; i < priv->dma_tx_size; i++) 1841 stmmac_free_tx_buffer(priv, queue, i); 1842 1843 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1844 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1845 tx_q->xsk_frames_done = 0; 1846 tx_q->xsk_pool = NULL; 1847 } 1848 } 1849 1850 /** 1851 * stmmac_free_tx_skbufs - free TX skb buffers 1852 * @priv: private structure 1853 */ 1854 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1855 { 1856 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1857 u32 queue; 1858 1859 for (queue = 0; queue < tx_queue_cnt; queue++) 1860 dma_free_tx_skbufs(priv, queue); 1861 } 1862 1863 /** 1864 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1865 * @priv: private structure 1866 * @queue: RX queue index 1867 */ 1868 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1869 { 1870 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1871 1872 /* Release the DMA RX socket buffers */ 1873 if (rx_q->xsk_pool) 1874 dma_free_rx_xskbufs(priv, queue); 1875 else 1876 dma_free_rx_skbufs(priv, queue); 1877 1878 rx_q->buf_alloc_num = 0; 1879 rx_q->xsk_pool = NULL; 1880 1881 /* Free DMA regions of consistent memory previously allocated */ 1882 if (!priv->extend_desc) 1883 dma_free_coherent(priv->device, priv->dma_rx_size * 1884 sizeof(struct dma_desc), 1885 rx_q->dma_rx, rx_q->dma_rx_phy); 1886 else 1887 dma_free_coherent(priv->device, priv->dma_rx_size * 1888 sizeof(struct dma_extended_desc), 1889 rx_q->dma_erx, rx_q->dma_rx_phy); 1890 1891 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1892 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1893 1894 kfree(rx_q->buf_pool); 1895 if (rx_q->page_pool) 1896 page_pool_destroy(rx_q->page_pool); 1897 } 1898 1899 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1900 { 1901 u32 rx_count = priv->plat->rx_queues_to_use; 1902 u32 queue; 1903 1904 /* Free RX queue resources */ 1905 for (queue = 0; queue < rx_count; queue++) 1906 __free_dma_rx_desc_resources(priv, queue); 1907 } 1908 1909 /** 1910 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1911 * @priv: private structure 1912 * @queue: TX queue index 1913 */ 1914 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 1915 { 1916 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1917 size_t size; 1918 void *addr; 1919 1920 /* Release the DMA TX socket buffers */ 1921 dma_free_tx_skbufs(priv, queue); 1922 1923 if (priv->extend_desc) { 1924 size = sizeof(struct dma_extended_desc); 1925 addr = tx_q->dma_etx; 1926 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1927 size = sizeof(struct dma_edesc); 1928 addr = tx_q->dma_entx; 1929 } else { 1930 size = sizeof(struct dma_desc); 1931 addr = tx_q->dma_tx; 1932 } 1933 1934 size *= priv->dma_tx_size; 1935 1936 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1937 1938 kfree(tx_q->tx_skbuff_dma); 1939 kfree(tx_q->tx_skbuff); 1940 } 1941 1942 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1943 { 1944 u32 tx_count = priv->plat->tx_queues_to_use; 1945 u32 queue; 1946 1947 /* Free TX queue resources */ 1948 for (queue = 0; queue < tx_count; queue++) 1949 __free_dma_tx_desc_resources(priv, queue); 1950 } 1951 1952 /** 1953 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1954 * @priv: private structure 1955 * @queue: RX queue index 1956 * Description: according to which descriptor can be used (extend or basic) 1957 * this function allocates the resources for TX and RX paths. In case of 1958 * reception, for example, it pre-allocated the RX socket buffer in order to 1959 * allow zero-copy mechanism. 1960 */ 1961 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1962 { 1963 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1964 struct stmmac_channel *ch = &priv->channel[queue]; 1965 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1966 struct page_pool_params pp_params = { 0 }; 1967 unsigned int num_pages; 1968 unsigned int napi_id; 1969 int ret; 1970 1971 rx_q->queue_index = queue; 1972 rx_q->priv_data = priv; 1973 1974 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1975 pp_params.pool_size = priv->dma_rx_size; 1976 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1977 pp_params.order = ilog2(num_pages); 1978 pp_params.nid = dev_to_node(priv->device); 1979 pp_params.dev = priv->device; 1980 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1981 pp_params.offset = stmmac_rx_offset(priv); 1982 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 1983 1984 rx_q->page_pool = page_pool_create(&pp_params); 1985 if (IS_ERR(rx_q->page_pool)) { 1986 ret = PTR_ERR(rx_q->page_pool); 1987 rx_q->page_pool = NULL; 1988 return ret; 1989 } 1990 1991 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1992 sizeof(*rx_q->buf_pool), 1993 GFP_KERNEL); 1994 if (!rx_q->buf_pool) 1995 return -ENOMEM; 1996 1997 if (priv->extend_desc) { 1998 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1999 priv->dma_rx_size * 2000 sizeof(struct dma_extended_desc), 2001 &rx_q->dma_rx_phy, 2002 GFP_KERNEL); 2003 if (!rx_q->dma_erx) 2004 return -ENOMEM; 2005 2006 } else { 2007 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2008 priv->dma_rx_size * 2009 sizeof(struct dma_desc), 2010 &rx_q->dma_rx_phy, 2011 GFP_KERNEL); 2012 if (!rx_q->dma_rx) 2013 return -ENOMEM; 2014 } 2015 2016 if (stmmac_xdp_is_enabled(priv) && 2017 test_bit(queue, priv->af_xdp_zc_qps)) 2018 napi_id = ch->rxtx_napi.napi_id; 2019 else 2020 napi_id = ch->rx_napi.napi_id; 2021 2022 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2023 rx_q->queue_index, 2024 napi_id); 2025 if (ret) { 2026 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2027 return -EINVAL; 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 2034 { 2035 u32 rx_count = priv->plat->rx_queues_to_use; 2036 u32 queue; 2037 int ret; 2038 2039 /* RX queues buffers and DMA */ 2040 for (queue = 0; queue < rx_count; queue++) { 2041 ret = __alloc_dma_rx_desc_resources(priv, queue); 2042 if (ret) 2043 goto err_dma; 2044 } 2045 2046 return 0; 2047 2048 err_dma: 2049 free_dma_rx_desc_resources(priv); 2050 2051 return ret; 2052 } 2053 2054 /** 2055 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2056 * @priv: private structure 2057 * @queue: TX queue index 2058 * Description: according to which descriptor can be used (extend or basic) 2059 * this function allocates the resources for TX and RX paths. In case of 2060 * reception, for example, it pre-allocated the RX socket buffer in order to 2061 * allow zero-copy mechanism. 2062 */ 2063 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 2064 { 2065 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2066 size_t size; 2067 void *addr; 2068 2069 tx_q->queue_index = queue; 2070 tx_q->priv_data = priv; 2071 2072 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 2073 sizeof(*tx_q->tx_skbuff_dma), 2074 GFP_KERNEL); 2075 if (!tx_q->tx_skbuff_dma) 2076 return -ENOMEM; 2077 2078 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 2079 sizeof(struct sk_buff *), 2080 GFP_KERNEL); 2081 if (!tx_q->tx_skbuff) 2082 return -ENOMEM; 2083 2084 if (priv->extend_desc) 2085 size = sizeof(struct dma_extended_desc); 2086 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2087 size = sizeof(struct dma_edesc); 2088 else 2089 size = sizeof(struct dma_desc); 2090 2091 size *= priv->dma_tx_size; 2092 2093 addr = dma_alloc_coherent(priv->device, size, 2094 &tx_q->dma_tx_phy, GFP_KERNEL); 2095 if (!addr) 2096 return -ENOMEM; 2097 2098 if (priv->extend_desc) 2099 tx_q->dma_etx = addr; 2100 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2101 tx_q->dma_entx = addr; 2102 else 2103 tx_q->dma_tx = addr; 2104 2105 return 0; 2106 } 2107 2108 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 2109 { 2110 u32 tx_count = priv->plat->tx_queues_to_use; 2111 u32 queue; 2112 int ret; 2113 2114 /* TX queues buffers and DMA */ 2115 for (queue = 0; queue < tx_count; queue++) { 2116 ret = __alloc_dma_tx_desc_resources(priv, queue); 2117 if (ret) 2118 goto err_dma; 2119 } 2120 2121 return 0; 2122 2123 err_dma: 2124 free_dma_tx_desc_resources(priv); 2125 return ret; 2126 } 2127 2128 /** 2129 * alloc_dma_desc_resources - alloc TX/RX resources. 2130 * @priv: private structure 2131 * Description: according to which descriptor can be used (extend or basic) 2132 * this function allocates the resources for TX and RX paths. In case of 2133 * reception, for example, it pre-allocated the RX socket buffer in order to 2134 * allow zero-copy mechanism. 2135 */ 2136 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 2137 { 2138 /* RX Allocation */ 2139 int ret = alloc_dma_rx_desc_resources(priv); 2140 2141 if (ret) 2142 return ret; 2143 2144 ret = alloc_dma_tx_desc_resources(priv); 2145 2146 return ret; 2147 } 2148 2149 /** 2150 * free_dma_desc_resources - free dma desc resources 2151 * @priv: private structure 2152 */ 2153 static void free_dma_desc_resources(struct stmmac_priv *priv) 2154 { 2155 /* Release the DMA TX socket buffers */ 2156 free_dma_tx_desc_resources(priv); 2157 2158 /* Release the DMA RX socket buffers later 2159 * to ensure all pending XDP_TX buffers are returned. 2160 */ 2161 free_dma_rx_desc_resources(priv); 2162 } 2163 2164 /** 2165 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2166 * @priv: driver private structure 2167 * Description: It is used for enabling the rx queues in the MAC 2168 */ 2169 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2170 { 2171 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2172 int queue; 2173 u8 mode; 2174 2175 for (queue = 0; queue < rx_queues_count; queue++) { 2176 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2177 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2178 } 2179 } 2180 2181 /** 2182 * stmmac_start_rx_dma - start RX DMA channel 2183 * @priv: driver private structure 2184 * @chan: RX channel index 2185 * Description: 2186 * This starts a RX DMA channel 2187 */ 2188 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2189 { 2190 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2191 stmmac_start_rx(priv, priv->ioaddr, chan); 2192 } 2193 2194 /** 2195 * stmmac_start_tx_dma - start TX DMA channel 2196 * @priv: driver private structure 2197 * @chan: TX channel index 2198 * Description: 2199 * This starts a TX DMA channel 2200 */ 2201 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2202 { 2203 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2204 stmmac_start_tx(priv, priv->ioaddr, chan); 2205 } 2206 2207 /** 2208 * stmmac_stop_rx_dma - stop RX DMA channel 2209 * @priv: driver private structure 2210 * @chan: RX channel index 2211 * Description: 2212 * This stops a RX DMA channel 2213 */ 2214 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2215 { 2216 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2217 stmmac_stop_rx(priv, priv->ioaddr, chan); 2218 } 2219 2220 /** 2221 * stmmac_stop_tx_dma - stop TX DMA channel 2222 * @priv: driver private structure 2223 * @chan: TX channel index 2224 * Description: 2225 * This stops a TX DMA channel 2226 */ 2227 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2228 { 2229 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2230 stmmac_stop_tx(priv, priv->ioaddr, chan); 2231 } 2232 2233 /** 2234 * stmmac_start_all_dma - start all RX and TX DMA channels 2235 * @priv: driver private structure 2236 * Description: 2237 * This starts all the RX and TX DMA channels 2238 */ 2239 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2240 { 2241 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2242 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2243 u32 chan = 0; 2244 2245 for (chan = 0; chan < rx_channels_count; chan++) 2246 stmmac_start_rx_dma(priv, chan); 2247 2248 for (chan = 0; chan < tx_channels_count; chan++) 2249 stmmac_start_tx_dma(priv, chan); 2250 } 2251 2252 /** 2253 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2254 * @priv: driver private structure 2255 * Description: 2256 * This stops the RX and TX DMA channels 2257 */ 2258 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2259 { 2260 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2261 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2262 u32 chan = 0; 2263 2264 for (chan = 0; chan < rx_channels_count; chan++) 2265 stmmac_stop_rx_dma(priv, chan); 2266 2267 for (chan = 0; chan < tx_channels_count; chan++) 2268 stmmac_stop_tx_dma(priv, chan); 2269 } 2270 2271 /** 2272 * stmmac_dma_operation_mode - HW DMA operation mode 2273 * @priv: driver private structure 2274 * Description: it is used for configuring the DMA operation mode register in 2275 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2276 */ 2277 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2278 { 2279 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2280 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2281 int rxfifosz = priv->plat->rx_fifo_size; 2282 int txfifosz = priv->plat->tx_fifo_size; 2283 u32 txmode = 0; 2284 u32 rxmode = 0; 2285 u32 chan = 0; 2286 u8 qmode = 0; 2287 2288 if (rxfifosz == 0) 2289 rxfifosz = priv->dma_cap.rx_fifo_size; 2290 if (txfifosz == 0) 2291 txfifosz = priv->dma_cap.tx_fifo_size; 2292 2293 /* Adjust for real per queue fifo size */ 2294 rxfifosz /= rx_channels_count; 2295 txfifosz /= tx_channels_count; 2296 2297 if (priv->plat->force_thresh_dma_mode) { 2298 txmode = tc; 2299 rxmode = tc; 2300 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2301 /* 2302 * In case of GMAC, SF mode can be enabled 2303 * to perform the TX COE in HW. This depends on: 2304 * 1) TX COE if actually supported 2305 * 2) There is no bugged Jumbo frame support 2306 * that needs to not insert csum in the TDES. 2307 */ 2308 txmode = SF_DMA_MODE; 2309 rxmode = SF_DMA_MODE; 2310 priv->xstats.threshold = SF_DMA_MODE; 2311 } else { 2312 txmode = tc; 2313 rxmode = SF_DMA_MODE; 2314 } 2315 2316 /* configure all channels */ 2317 for (chan = 0; chan < rx_channels_count; chan++) { 2318 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2319 u32 buf_size; 2320 2321 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2322 2323 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2324 rxfifosz, qmode); 2325 2326 if (rx_q->xsk_pool) { 2327 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2328 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2329 buf_size, 2330 chan); 2331 } else { 2332 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2333 priv->dma_buf_sz, 2334 chan); 2335 } 2336 } 2337 2338 for (chan = 0; chan < tx_channels_count; chan++) { 2339 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2340 2341 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2342 txfifosz, qmode); 2343 } 2344 } 2345 2346 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2347 { 2348 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2349 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2350 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2351 unsigned int entry = tx_q->cur_tx; 2352 struct dma_desc *tx_desc = NULL; 2353 struct xdp_desc xdp_desc; 2354 bool work_done = true; 2355 2356 /* Avoids TX time-out as we are sharing with slow path */ 2357 nq->trans_start = jiffies; 2358 2359 budget = min(budget, stmmac_tx_avail(priv, queue)); 2360 2361 while (budget-- > 0) { 2362 dma_addr_t dma_addr; 2363 bool set_ic; 2364 2365 /* We are sharing with slow path and stop XSK TX desc submission when 2366 * available TX ring is less than threshold. 2367 */ 2368 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2369 !netif_carrier_ok(priv->dev)) { 2370 work_done = false; 2371 break; 2372 } 2373 2374 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2375 break; 2376 2377 if (likely(priv->extend_desc)) 2378 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2379 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2380 tx_desc = &tx_q->dma_entx[entry].basic; 2381 else 2382 tx_desc = tx_q->dma_tx + entry; 2383 2384 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2385 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2386 2387 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2388 2389 /* To return XDP buffer to XSK pool, we simple call 2390 * xsk_tx_completed(), so we don't need to fill up 2391 * 'buf' and 'xdpf'. 2392 */ 2393 tx_q->tx_skbuff_dma[entry].buf = 0; 2394 tx_q->xdpf[entry] = NULL; 2395 2396 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2397 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2398 tx_q->tx_skbuff_dma[entry].last_segment = true; 2399 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2400 2401 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2402 2403 tx_q->tx_count_frames++; 2404 2405 if (!priv->tx_coal_frames[queue]) 2406 set_ic = false; 2407 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2408 set_ic = true; 2409 else 2410 set_ic = false; 2411 2412 if (set_ic) { 2413 tx_q->tx_count_frames = 0; 2414 stmmac_set_tx_ic(priv, tx_desc); 2415 priv->xstats.tx_set_ic_bit++; 2416 } 2417 2418 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2419 true, priv->mode, true, true, 2420 xdp_desc.len); 2421 2422 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2423 2424 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2425 entry = tx_q->cur_tx; 2426 } 2427 2428 if (tx_desc) { 2429 stmmac_flush_tx_descriptors(priv, queue); 2430 xsk_tx_release(pool); 2431 } 2432 2433 /* Return true if all of the 3 conditions are met 2434 * a) TX Budget is still available 2435 * b) work_done = true when XSK TX desc peek is empty (no more 2436 * pending XSK TX for transmission) 2437 */ 2438 return !!budget && work_done; 2439 } 2440 2441 /** 2442 * stmmac_tx_clean - to manage the transmission completion 2443 * @priv: driver private structure 2444 * @budget: napi budget limiting this functions packet handling 2445 * @queue: TX queue index 2446 * Description: it reclaims the transmit resources after transmission completes. 2447 */ 2448 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2449 { 2450 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2451 unsigned int bytes_compl = 0, pkts_compl = 0; 2452 unsigned int entry, xmits = 0, count = 0; 2453 2454 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2455 2456 priv->xstats.tx_clean++; 2457 2458 tx_q->xsk_frames_done = 0; 2459 2460 entry = tx_q->dirty_tx; 2461 2462 /* Try to clean all TX complete frame in 1 shot */ 2463 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { 2464 struct xdp_frame *xdpf; 2465 struct sk_buff *skb; 2466 struct dma_desc *p; 2467 int status; 2468 2469 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2470 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2471 xdpf = tx_q->xdpf[entry]; 2472 skb = NULL; 2473 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2474 xdpf = NULL; 2475 skb = tx_q->tx_skbuff[entry]; 2476 } else { 2477 xdpf = NULL; 2478 skb = NULL; 2479 } 2480 2481 if (priv->extend_desc) 2482 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2483 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2484 p = &tx_q->dma_entx[entry].basic; 2485 else 2486 p = tx_q->dma_tx + entry; 2487 2488 status = stmmac_tx_status(priv, &priv->dev->stats, 2489 &priv->xstats, p, priv->ioaddr); 2490 /* Check if the descriptor is owned by the DMA */ 2491 if (unlikely(status & tx_dma_own)) 2492 break; 2493 2494 count++; 2495 2496 /* Make sure descriptor fields are read after reading 2497 * the own bit. 2498 */ 2499 dma_rmb(); 2500 2501 /* Just consider the last segment and ...*/ 2502 if (likely(!(status & tx_not_ls))) { 2503 /* ... verify the status error condition */ 2504 if (unlikely(status & tx_err)) { 2505 priv->dev->stats.tx_errors++; 2506 } else { 2507 priv->dev->stats.tx_packets++; 2508 priv->xstats.tx_pkt_n++; 2509 } 2510 if (skb) 2511 stmmac_get_tx_hwtstamp(priv, p, skb); 2512 } 2513 2514 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2515 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2516 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2517 dma_unmap_page(priv->device, 2518 tx_q->tx_skbuff_dma[entry].buf, 2519 tx_q->tx_skbuff_dma[entry].len, 2520 DMA_TO_DEVICE); 2521 else 2522 dma_unmap_single(priv->device, 2523 tx_q->tx_skbuff_dma[entry].buf, 2524 tx_q->tx_skbuff_dma[entry].len, 2525 DMA_TO_DEVICE); 2526 tx_q->tx_skbuff_dma[entry].buf = 0; 2527 tx_q->tx_skbuff_dma[entry].len = 0; 2528 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2529 } 2530 2531 stmmac_clean_desc3(priv, tx_q, p); 2532 2533 tx_q->tx_skbuff_dma[entry].last_segment = false; 2534 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2535 2536 if (xdpf && 2537 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2538 xdp_return_frame_rx_napi(xdpf); 2539 tx_q->xdpf[entry] = NULL; 2540 } 2541 2542 if (xdpf && 2543 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2544 xdp_return_frame(xdpf); 2545 tx_q->xdpf[entry] = NULL; 2546 } 2547 2548 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2549 tx_q->xsk_frames_done++; 2550 2551 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2552 if (likely(skb)) { 2553 pkts_compl++; 2554 bytes_compl += skb->len; 2555 dev_consume_skb_any(skb); 2556 tx_q->tx_skbuff[entry] = NULL; 2557 } 2558 } 2559 2560 stmmac_release_tx_desc(priv, p, priv->mode); 2561 2562 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2563 } 2564 tx_q->dirty_tx = entry; 2565 2566 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2567 pkts_compl, bytes_compl); 2568 2569 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2570 queue))) && 2571 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2572 2573 netif_dbg(priv, tx_done, priv->dev, 2574 "%s: restart transmit\n", __func__); 2575 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2576 } 2577 2578 if (tx_q->xsk_pool) { 2579 bool work_done; 2580 2581 if (tx_q->xsk_frames_done) 2582 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2583 2584 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2585 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2586 2587 /* For XSK TX, we try to send as many as possible. 2588 * If XSK work done (XSK TX desc empty and budget still 2589 * available), return "budget - 1" to reenable TX IRQ. 2590 * Else, return "budget" to make NAPI continue polling. 2591 */ 2592 work_done = stmmac_xdp_xmit_zc(priv, queue, 2593 STMMAC_XSK_TX_BUDGET_MAX); 2594 if (work_done) 2595 xmits = budget - 1; 2596 else 2597 xmits = budget; 2598 } 2599 2600 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2601 priv->eee_sw_timer_en) { 2602 stmmac_enable_eee_mode(priv); 2603 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2604 } 2605 2606 /* We still have pending packets, let's call for a new scheduling */ 2607 if (tx_q->dirty_tx != tx_q->cur_tx) 2608 hrtimer_start(&tx_q->txtimer, 2609 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2610 HRTIMER_MODE_REL); 2611 2612 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2613 2614 /* Combine decisions from TX clean and XSK TX */ 2615 return max(count, xmits); 2616 } 2617 2618 /** 2619 * stmmac_tx_err - to manage the tx error 2620 * @priv: driver private structure 2621 * @chan: channel index 2622 * Description: it cleans the descriptors and restarts the transmission 2623 * in case of transmission errors. 2624 */ 2625 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2626 { 2627 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2628 2629 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2630 2631 stmmac_stop_tx_dma(priv, chan); 2632 dma_free_tx_skbufs(priv, chan); 2633 stmmac_clear_tx_descriptors(priv, chan); 2634 tx_q->dirty_tx = 0; 2635 tx_q->cur_tx = 0; 2636 tx_q->mss = 0; 2637 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2638 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2639 tx_q->dma_tx_phy, chan); 2640 stmmac_start_tx_dma(priv, chan); 2641 2642 priv->dev->stats.tx_errors++; 2643 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2644 } 2645 2646 /** 2647 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2648 * @priv: driver private structure 2649 * @txmode: TX operating mode 2650 * @rxmode: RX operating mode 2651 * @chan: channel index 2652 * Description: it is used for configuring of the DMA operation mode in 2653 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2654 * mode. 2655 */ 2656 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2657 u32 rxmode, u32 chan) 2658 { 2659 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2660 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2661 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2662 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2663 int rxfifosz = priv->plat->rx_fifo_size; 2664 int txfifosz = priv->plat->tx_fifo_size; 2665 2666 if (rxfifosz == 0) 2667 rxfifosz = priv->dma_cap.rx_fifo_size; 2668 if (txfifosz == 0) 2669 txfifosz = priv->dma_cap.tx_fifo_size; 2670 2671 /* Adjust for real per queue fifo size */ 2672 rxfifosz /= rx_channels_count; 2673 txfifosz /= tx_channels_count; 2674 2675 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2676 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2677 } 2678 2679 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2680 { 2681 int ret; 2682 2683 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2684 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2685 if (ret && (ret != -EINVAL)) { 2686 stmmac_global_err(priv); 2687 return true; 2688 } 2689 2690 return false; 2691 } 2692 2693 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2694 { 2695 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2696 &priv->xstats, chan, dir); 2697 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2698 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2699 struct stmmac_channel *ch = &priv->channel[chan]; 2700 struct napi_struct *rx_napi; 2701 struct napi_struct *tx_napi; 2702 unsigned long flags; 2703 2704 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2705 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2706 2707 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2708 if (napi_schedule_prep(rx_napi)) { 2709 spin_lock_irqsave(&ch->lock, flags); 2710 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2711 spin_unlock_irqrestore(&ch->lock, flags); 2712 __napi_schedule(rx_napi); 2713 } 2714 } 2715 2716 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2717 if (napi_schedule_prep(tx_napi)) { 2718 spin_lock_irqsave(&ch->lock, flags); 2719 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2720 spin_unlock_irqrestore(&ch->lock, flags); 2721 __napi_schedule(tx_napi); 2722 } 2723 } 2724 2725 return status; 2726 } 2727 2728 /** 2729 * stmmac_dma_interrupt - DMA ISR 2730 * @priv: driver private structure 2731 * Description: this is the DMA ISR. It is called by the main ISR. 2732 * It calls the dwmac dma routine and schedule poll method in case of some 2733 * work can be done. 2734 */ 2735 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2736 { 2737 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2738 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2739 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2740 tx_channel_count : rx_channel_count; 2741 u32 chan; 2742 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2743 2744 /* Make sure we never check beyond our status buffer. */ 2745 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2746 channels_to_check = ARRAY_SIZE(status); 2747 2748 for (chan = 0; chan < channels_to_check; chan++) 2749 status[chan] = stmmac_napi_check(priv, chan, 2750 DMA_DIR_RXTX); 2751 2752 for (chan = 0; chan < tx_channel_count; chan++) { 2753 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2754 /* Try to bump up the dma threshold on this failure */ 2755 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2756 (tc <= 256)) { 2757 tc += 64; 2758 if (priv->plat->force_thresh_dma_mode) 2759 stmmac_set_dma_operation_mode(priv, 2760 tc, 2761 tc, 2762 chan); 2763 else 2764 stmmac_set_dma_operation_mode(priv, 2765 tc, 2766 SF_DMA_MODE, 2767 chan); 2768 priv->xstats.threshold = tc; 2769 } 2770 } else if (unlikely(status[chan] == tx_hard_error)) { 2771 stmmac_tx_err(priv, chan); 2772 } 2773 } 2774 } 2775 2776 /** 2777 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2778 * @priv: driver private structure 2779 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2780 */ 2781 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2782 { 2783 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2784 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2785 2786 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2787 2788 if (priv->dma_cap.rmon) { 2789 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2790 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2791 } else 2792 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2793 } 2794 2795 /** 2796 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2797 * @priv: driver private structure 2798 * Description: 2799 * new GMAC chip generations have a new register to indicate the 2800 * presence of the optional feature/functions. 2801 * This can be also used to override the value passed through the 2802 * platform and necessary for old MAC10/100 and GMAC chips. 2803 */ 2804 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2805 { 2806 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2807 } 2808 2809 /** 2810 * stmmac_check_ether_addr - check if the MAC addr is valid 2811 * @priv: driver private structure 2812 * Description: 2813 * it is to verify if the MAC address is valid, in case of failures it 2814 * generates a random MAC address 2815 */ 2816 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2817 { 2818 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2819 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2820 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2821 eth_hw_addr_random(priv->dev); 2822 dev_info(priv->device, "device MAC address %pM\n", 2823 priv->dev->dev_addr); 2824 } 2825 } 2826 2827 /** 2828 * stmmac_init_dma_engine - DMA init. 2829 * @priv: driver private structure 2830 * Description: 2831 * It inits the DMA invoking the specific MAC/GMAC callback. 2832 * Some DMA parameters can be passed from the platform; 2833 * in case of these are not passed a default is kept for the MAC or GMAC. 2834 */ 2835 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2836 { 2837 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2838 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2839 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2840 struct stmmac_rx_queue *rx_q; 2841 struct stmmac_tx_queue *tx_q; 2842 u32 chan = 0; 2843 int atds = 0; 2844 int ret = 0; 2845 2846 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2847 dev_err(priv->device, "Invalid DMA configuration\n"); 2848 return -EINVAL; 2849 } 2850 2851 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2852 atds = 1; 2853 2854 ret = stmmac_reset(priv, priv->ioaddr); 2855 if (ret) { 2856 dev_err(priv->device, "Failed to reset the dma\n"); 2857 return ret; 2858 } 2859 2860 /* DMA Configuration */ 2861 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2862 2863 if (priv->plat->axi) 2864 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2865 2866 /* DMA CSR Channel configuration */ 2867 for (chan = 0; chan < dma_csr_ch; chan++) 2868 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2869 2870 /* DMA RX Channel Configuration */ 2871 for (chan = 0; chan < rx_channels_count; chan++) { 2872 rx_q = &priv->rx_queue[chan]; 2873 2874 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2875 rx_q->dma_rx_phy, chan); 2876 2877 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2878 (rx_q->buf_alloc_num * 2879 sizeof(struct dma_desc)); 2880 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2881 rx_q->rx_tail_addr, chan); 2882 } 2883 2884 /* DMA TX Channel Configuration */ 2885 for (chan = 0; chan < tx_channels_count; chan++) { 2886 tx_q = &priv->tx_queue[chan]; 2887 2888 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2889 tx_q->dma_tx_phy, chan); 2890 2891 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2892 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2893 tx_q->tx_tail_addr, chan); 2894 } 2895 2896 return ret; 2897 } 2898 2899 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2900 { 2901 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2902 2903 hrtimer_start(&tx_q->txtimer, 2904 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2905 HRTIMER_MODE_REL); 2906 } 2907 2908 /** 2909 * stmmac_tx_timer - mitigation sw timer for tx. 2910 * @t: data pointer 2911 * Description: 2912 * This is the timer handler to directly invoke the stmmac_tx_clean. 2913 */ 2914 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2915 { 2916 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2917 struct stmmac_priv *priv = tx_q->priv_data; 2918 struct stmmac_channel *ch; 2919 struct napi_struct *napi; 2920 2921 ch = &priv->channel[tx_q->queue_index]; 2922 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2923 2924 if (likely(napi_schedule_prep(napi))) { 2925 unsigned long flags; 2926 2927 spin_lock_irqsave(&ch->lock, flags); 2928 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2929 spin_unlock_irqrestore(&ch->lock, flags); 2930 __napi_schedule(napi); 2931 } 2932 2933 return HRTIMER_NORESTART; 2934 } 2935 2936 /** 2937 * stmmac_init_coalesce - init mitigation options. 2938 * @priv: driver private structure 2939 * Description: 2940 * This inits the coalesce parameters: i.e. timer rate, 2941 * timer handler and default threshold used for enabling the 2942 * interrupt on completion bit. 2943 */ 2944 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2945 { 2946 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2947 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2948 u32 chan; 2949 2950 for (chan = 0; chan < tx_channel_count; chan++) { 2951 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2952 2953 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 2954 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 2955 2956 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2957 tx_q->txtimer.function = stmmac_tx_timer; 2958 } 2959 2960 for (chan = 0; chan < rx_channel_count; chan++) 2961 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 2962 } 2963 2964 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2965 { 2966 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2967 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2968 u32 chan; 2969 2970 /* set TX ring length */ 2971 for (chan = 0; chan < tx_channels_count; chan++) 2972 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2973 (priv->dma_tx_size - 1), chan); 2974 2975 /* set RX ring length */ 2976 for (chan = 0; chan < rx_channels_count; chan++) 2977 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2978 (priv->dma_rx_size - 1), chan); 2979 } 2980 2981 /** 2982 * stmmac_set_tx_queue_weight - Set TX queue weight 2983 * @priv: driver private structure 2984 * Description: It is used for setting TX queues weight 2985 */ 2986 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2987 { 2988 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2989 u32 weight; 2990 u32 queue; 2991 2992 for (queue = 0; queue < tx_queues_count; queue++) { 2993 weight = priv->plat->tx_queues_cfg[queue].weight; 2994 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2995 } 2996 } 2997 2998 /** 2999 * stmmac_configure_cbs - Configure CBS in TX queue 3000 * @priv: driver private structure 3001 * Description: It is used for configuring CBS in AVB TX queues 3002 */ 3003 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3004 { 3005 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3006 u32 mode_to_use; 3007 u32 queue; 3008 3009 /* queue 0 is reserved for legacy traffic */ 3010 for (queue = 1; queue < tx_queues_count; queue++) { 3011 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3012 if (mode_to_use == MTL_QUEUE_DCB) 3013 continue; 3014 3015 stmmac_config_cbs(priv, priv->hw, 3016 priv->plat->tx_queues_cfg[queue].send_slope, 3017 priv->plat->tx_queues_cfg[queue].idle_slope, 3018 priv->plat->tx_queues_cfg[queue].high_credit, 3019 priv->plat->tx_queues_cfg[queue].low_credit, 3020 queue); 3021 } 3022 } 3023 3024 /** 3025 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3026 * @priv: driver private structure 3027 * Description: It is used for mapping RX queues to RX dma channels 3028 */ 3029 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3030 { 3031 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3032 u32 queue; 3033 u32 chan; 3034 3035 for (queue = 0; queue < rx_queues_count; queue++) { 3036 chan = priv->plat->rx_queues_cfg[queue].chan; 3037 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3038 } 3039 } 3040 3041 /** 3042 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3043 * @priv: driver private structure 3044 * Description: It is used for configuring the RX Queue Priority 3045 */ 3046 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3047 { 3048 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3049 u32 queue; 3050 u32 prio; 3051 3052 for (queue = 0; queue < rx_queues_count; queue++) { 3053 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3054 continue; 3055 3056 prio = priv->plat->rx_queues_cfg[queue].prio; 3057 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3058 } 3059 } 3060 3061 /** 3062 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3063 * @priv: driver private structure 3064 * Description: It is used for configuring the TX Queue Priority 3065 */ 3066 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3067 { 3068 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3069 u32 queue; 3070 u32 prio; 3071 3072 for (queue = 0; queue < tx_queues_count; queue++) { 3073 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3074 continue; 3075 3076 prio = priv->plat->tx_queues_cfg[queue].prio; 3077 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3078 } 3079 } 3080 3081 /** 3082 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3083 * @priv: driver private structure 3084 * Description: It is used for configuring the RX queue routing 3085 */ 3086 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3087 { 3088 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3089 u32 queue; 3090 u8 packet; 3091 3092 for (queue = 0; queue < rx_queues_count; queue++) { 3093 /* no specific packet type routing specified for the queue */ 3094 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3095 continue; 3096 3097 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3098 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3099 } 3100 } 3101 3102 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3103 { 3104 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3105 priv->rss.enable = false; 3106 return; 3107 } 3108 3109 if (priv->dev->features & NETIF_F_RXHASH) 3110 priv->rss.enable = true; 3111 else 3112 priv->rss.enable = false; 3113 3114 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3115 priv->plat->rx_queues_to_use); 3116 } 3117 3118 /** 3119 * stmmac_mtl_configuration - Configure MTL 3120 * @priv: driver private structure 3121 * Description: It is used for configurring MTL 3122 */ 3123 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3124 { 3125 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3126 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3127 3128 if (tx_queues_count > 1) 3129 stmmac_set_tx_queue_weight(priv); 3130 3131 /* Configure MTL RX algorithms */ 3132 if (rx_queues_count > 1) 3133 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3134 priv->plat->rx_sched_algorithm); 3135 3136 /* Configure MTL TX algorithms */ 3137 if (tx_queues_count > 1) 3138 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3139 priv->plat->tx_sched_algorithm); 3140 3141 /* Configure CBS in AVB TX queues */ 3142 if (tx_queues_count > 1) 3143 stmmac_configure_cbs(priv); 3144 3145 /* Map RX MTL to DMA channels */ 3146 stmmac_rx_queue_dma_chan_map(priv); 3147 3148 /* Enable MAC RX Queues */ 3149 stmmac_mac_enable_rx_queues(priv); 3150 3151 /* Set RX priorities */ 3152 if (rx_queues_count > 1) 3153 stmmac_mac_config_rx_queues_prio(priv); 3154 3155 /* Set TX priorities */ 3156 if (tx_queues_count > 1) 3157 stmmac_mac_config_tx_queues_prio(priv); 3158 3159 /* Set RX routing */ 3160 if (rx_queues_count > 1) 3161 stmmac_mac_config_rx_queues_routing(priv); 3162 3163 /* Receive Side Scaling */ 3164 if (rx_queues_count > 1) 3165 stmmac_mac_config_rss(priv); 3166 } 3167 3168 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3169 { 3170 if (priv->dma_cap.asp) { 3171 netdev_info(priv->dev, "Enabling Safety Features\n"); 3172 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 3173 } else { 3174 netdev_info(priv->dev, "No Safety Features support found\n"); 3175 } 3176 } 3177 3178 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3179 { 3180 char *name; 3181 3182 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3183 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3184 3185 name = priv->wq_name; 3186 sprintf(name, "%s-fpe", priv->dev->name); 3187 3188 priv->fpe_wq = create_singlethread_workqueue(name); 3189 if (!priv->fpe_wq) { 3190 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3191 3192 return -ENOMEM; 3193 } 3194 netdev_info(priv->dev, "FPE workqueue start"); 3195 3196 return 0; 3197 } 3198 3199 /** 3200 * stmmac_hw_setup - setup mac in a usable state. 3201 * @dev : pointer to the device structure. 3202 * @init_ptp: initialize PTP if set 3203 * Description: 3204 * this is the main function to setup the HW in a usable state because the 3205 * dma engine is reset, the core registers are configured (e.g. AXI, 3206 * Checksum features, timers). The DMA is ready to start receiving and 3207 * transmitting. 3208 * Return value: 3209 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3210 * file on failure. 3211 */ 3212 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 3213 { 3214 struct stmmac_priv *priv = netdev_priv(dev); 3215 u32 rx_cnt = priv->plat->rx_queues_to_use; 3216 u32 tx_cnt = priv->plat->tx_queues_to_use; 3217 bool sph_en; 3218 u32 chan; 3219 int ret; 3220 3221 /* DMA initialization and SW reset */ 3222 ret = stmmac_init_dma_engine(priv); 3223 if (ret < 0) { 3224 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3225 __func__); 3226 return ret; 3227 } 3228 3229 /* Copy the MAC addr into the HW */ 3230 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3231 3232 /* PS and related bits will be programmed according to the speed */ 3233 if (priv->hw->pcs) { 3234 int speed = priv->plat->mac_port_sel_speed; 3235 3236 if ((speed == SPEED_10) || (speed == SPEED_100) || 3237 (speed == SPEED_1000)) { 3238 priv->hw->ps = speed; 3239 } else { 3240 dev_warn(priv->device, "invalid port speed\n"); 3241 priv->hw->ps = 0; 3242 } 3243 } 3244 3245 /* Initialize the MAC Core */ 3246 stmmac_core_init(priv, priv->hw, dev); 3247 3248 /* Initialize MTL*/ 3249 stmmac_mtl_configuration(priv); 3250 3251 /* Initialize Safety Features */ 3252 stmmac_safety_feat_configuration(priv); 3253 3254 ret = stmmac_rx_ipc(priv, priv->hw); 3255 if (!ret) { 3256 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3257 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3258 priv->hw->rx_csum = 0; 3259 } 3260 3261 /* Enable the MAC Rx/Tx */ 3262 stmmac_mac_set(priv, priv->ioaddr, true); 3263 3264 /* Set the HW DMA mode and the COE */ 3265 stmmac_dma_operation_mode(priv); 3266 3267 stmmac_mmc_setup(priv); 3268 3269 if (init_ptp) { 3270 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3271 if (ret < 0) 3272 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 3273 3274 ret = stmmac_init_ptp(priv); 3275 if (ret == -EOPNOTSUPP) 3276 netdev_warn(priv->dev, "PTP not supported by HW\n"); 3277 else if (ret) 3278 netdev_warn(priv->dev, "PTP init failed\n"); 3279 } 3280 3281 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3282 3283 /* Convert the timer from msec to usec */ 3284 if (!priv->tx_lpi_timer) 3285 priv->tx_lpi_timer = eee_timer * 1000; 3286 3287 if (priv->use_riwt) { 3288 u32 queue; 3289 3290 for (queue = 0; queue < rx_cnt; queue++) { 3291 if (!priv->rx_riwt[queue]) 3292 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3293 3294 stmmac_rx_watchdog(priv, priv->ioaddr, 3295 priv->rx_riwt[queue], queue); 3296 } 3297 } 3298 3299 if (priv->hw->pcs) 3300 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3301 3302 /* set TX and RX rings length */ 3303 stmmac_set_rings_length(priv); 3304 3305 /* Enable TSO */ 3306 if (priv->tso) { 3307 for (chan = 0; chan < tx_cnt; chan++) { 3308 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3309 3310 /* TSO and TBS cannot co-exist */ 3311 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3312 continue; 3313 3314 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3315 } 3316 } 3317 3318 /* Enable Split Header */ 3319 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3320 for (chan = 0; chan < rx_cnt; chan++) 3321 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3322 3323 3324 /* VLAN Tag Insertion */ 3325 if (priv->dma_cap.vlins) 3326 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3327 3328 /* TBS */ 3329 for (chan = 0; chan < tx_cnt; chan++) { 3330 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3331 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3332 3333 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3334 } 3335 3336 /* Configure real RX and TX queues */ 3337 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3338 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3339 3340 /* Start the ball rolling... */ 3341 stmmac_start_all_dma(priv); 3342 3343 if (priv->dma_cap.fpesel) { 3344 stmmac_fpe_start_wq(priv); 3345 3346 if (priv->plat->fpe_cfg->enable) 3347 stmmac_fpe_handshake(priv, true); 3348 } 3349 3350 return 0; 3351 } 3352 3353 static void stmmac_hw_teardown(struct net_device *dev) 3354 { 3355 struct stmmac_priv *priv = netdev_priv(dev); 3356 3357 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3358 } 3359 3360 static void stmmac_free_irq(struct net_device *dev, 3361 enum request_irq_err irq_err, int irq_idx) 3362 { 3363 struct stmmac_priv *priv = netdev_priv(dev); 3364 int j; 3365 3366 switch (irq_err) { 3367 case REQ_IRQ_ERR_ALL: 3368 irq_idx = priv->plat->tx_queues_to_use; 3369 fallthrough; 3370 case REQ_IRQ_ERR_TX: 3371 for (j = irq_idx - 1; j >= 0; j--) { 3372 if (priv->tx_irq[j] > 0) { 3373 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3374 free_irq(priv->tx_irq[j], &priv->tx_queue[j]); 3375 } 3376 } 3377 irq_idx = priv->plat->rx_queues_to_use; 3378 fallthrough; 3379 case REQ_IRQ_ERR_RX: 3380 for (j = irq_idx - 1; j >= 0; j--) { 3381 if (priv->rx_irq[j] > 0) { 3382 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3383 free_irq(priv->rx_irq[j], &priv->rx_queue[j]); 3384 } 3385 } 3386 3387 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3388 free_irq(priv->sfty_ue_irq, dev); 3389 fallthrough; 3390 case REQ_IRQ_ERR_SFTY_UE: 3391 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3392 free_irq(priv->sfty_ce_irq, dev); 3393 fallthrough; 3394 case REQ_IRQ_ERR_SFTY_CE: 3395 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3396 free_irq(priv->lpi_irq, dev); 3397 fallthrough; 3398 case REQ_IRQ_ERR_LPI: 3399 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3400 free_irq(priv->wol_irq, dev); 3401 fallthrough; 3402 case REQ_IRQ_ERR_WOL: 3403 free_irq(dev->irq, dev); 3404 fallthrough; 3405 case REQ_IRQ_ERR_MAC: 3406 case REQ_IRQ_ERR_NO: 3407 /* If MAC IRQ request error, no more IRQ to free */ 3408 break; 3409 } 3410 } 3411 3412 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3413 { 3414 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3415 struct stmmac_priv *priv = netdev_priv(dev); 3416 cpumask_t cpu_mask; 3417 int irq_idx = 0; 3418 char *int_name; 3419 int ret; 3420 int i; 3421 3422 /* For common interrupt */ 3423 int_name = priv->int_name_mac; 3424 sprintf(int_name, "%s:%s", dev->name, "mac"); 3425 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3426 0, int_name, dev); 3427 if (unlikely(ret < 0)) { 3428 netdev_err(priv->dev, 3429 "%s: alloc mac MSI %d (error: %d)\n", 3430 __func__, dev->irq, ret); 3431 irq_err = REQ_IRQ_ERR_MAC; 3432 goto irq_error; 3433 } 3434 3435 /* Request the Wake IRQ in case of another line 3436 * is used for WoL 3437 */ 3438 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3439 int_name = priv->int_name_wol; 3440 sprintf(int_name, "%s:%s", dev->name, "wol"); 3441 ret = request_irq(priv->wol_irq, 3442 stmmac_mac_interrupt, 3443 0, int_name, dev); 3444 if (unlikely(ret < 0)) { 3445 netdev_err(priv->dev, 3446 "%s: alloc wol MSI %d (error: %d)\n", 3447 __func__, priv->wol_irq, ret); 3448 irq_err = REQ_IRQ_ERR_WOL; 3449 goto irq_error; 3450 } 3451 } 3452 3453 /* Request the LPI IRQ in case of another line 3454 * is used for LPI 3455 */ 3456 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3457 int_name = priv->int_name_lpi; 3458 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3459 ret = request_irq(priv->lpi_irq, 3460 stmmac_mac_interrupt, 3461 0, int_name, dev); 3462 if (unlikely(ret < 0)) { 3463 netdev_err(priv->dev, 3464 "%s: alloc lpi MSI %d (error: %d)\n", 3465 __func__, priv->lpi_irq, ret); 3466 irq_err = REQ_IRQ_ERR_LPI; 3467 goto irq_error; 3468 } 3469 } 3470 3471 /* Request the Safety Feature Correctible Error line in 3472 * case of another line is used 3473 */ 3474 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3475 int_name = priv->int_name_sfty_ce; 3476 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3477 ret = request_irq(priv->sfty_ce_irq, 3478 stmmac_safety_interrupt, 3479 0, int_name, dev); 3480 if (unlikely(ret < 0)) { 3481 netdev_err(priv->dev, 3482 "%s: alloc sfty ce MSI %d (error: %d)\n", 3483 __func__, priv->sfty_ce_irq, ret); 3484 irq_err = REQ_IRQ_ERR_SFTY_CE; 3485 goto irq_error; 3486 } 3487 } 3488 3489 /* Request the Safety Feature Uncorrectible Error line in 3490 * case of another line is used 3491 */ 3492 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3493 int_name = priv->int_name_sfty_ue; 3494 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3495 ret = request_irq(priv->sfty_ue_irq, 3496 stmmac_safety_interrupt, 3497 0, int_name, dev); 3498 if (unlikely(ret < 0)) { 3499 netdev_err(priv->dev, 3500 "%s: alloc sfty ue MSI %d (error: %d)\n", 3501 __func__, priv->sfty_ue_irq, ret); 3502 irq_err = REQ_IRQ_ERR_SFTY_UE; 3503 goto irq_error; 3504 } 3505 } 3506 3507 /* Request Rx MSI irq */ 3508 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3509 if (priv->rx_irq[i] == 0) 3510 continue; 3511 3512 int_name = priv->int_name_rx_irq[i]; 3513 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3514 ret = request_irq(priv->rx_irq[i], 3515 stmmac_msi_intr_rx, 3516 0, int_name, &priv->rx_queue[i]); 3517 if (unlikely(ret < 0)) { 3518 netdev_err(priv->dev, 3519 "%s: alloc rx-%d MSI %d (error: %d)\n", 3520 __func__, i, priv->rx_irq[i], ret); 3521 irq_err = REQ_IRQ_ERR_RX; 3522 irq_idx = i; 3523 goto irq_error; 3524 } 3525 cpumask_clear(&cpu_mask); 3526 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3527 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3528 } 3529 3530 /* Request Tx MSI irq */ 3531 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3532 if (priv->tx_irq[i] == 0) 3533 continue; 3534 3535 int_name = priv->int_name_tx_irq[i]; 3536 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3537 ret = request_irq(priv->tx_irq[i], 3538 stmmac_msi_intr_tx, 3539 0, int_name, &priv->tx_queue[i]); 3540 if (unlikely(ret < 0)) { 3541 netdev_err(priv->dev, 3542 "%s: alloc tx-%d MSI %d (error: %d)\n", 3543 __func__, i, priv->tx_irq[i], ret); 3544 irq_err = REQ_IRQ_ERR_TX; 3545 irq_idx = i; 3546 goto irq_error; 3547 } 3548 cpumask_clear(&cpu_mask); 3549 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3550 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3551 } 3552 3553 return 0; 3554 3555 irq_error: 3556 stmmac_free_irq(dev, irq_err, irq_idx); 3557 return ret; 3558 } 3559 3560 static int stmmac_request_irq_single(struct net_device *dev) 3561 { 3562 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3563 struct stmmac_priv *priv = netdev_priv(dev); 3564 int ret; 3565 3566 ret = request_irq(dev->irq, stmmac_interrupt, 3567 IRQF_SHARED, dev->name, dev); 3568 if (unlikely(ret < 0)) { 3569 netdev_err(priv->dev, 3570 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3571 __func__, dev->irq, ret); 3572 irq_err = REQ_IRQ_ERR_MAC; 3573 return ret; 3574 } 3575 3576 /* Request the Wake IRQ in case of another line 3577 * is used for WoL 3578 */ 3579 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3580 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3581 IRQF_SHARED, dev->name, dev); 3582 if (unlikely(ret < 0)) { 3583 netdev_err(priv->dev, 3584 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3585 __func__, priv->wol_irq, ret); 3586 irq_err = REQ_IRQ_ERR_WOL; 3587 return ret; 3588 } 3589 } 3590 3591 /* Request the IRQ lines */ 3592 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3593 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3594 IRQF_SHARED, dev->name, dev); 3595 if (unlikely(ret < 0)) { 3596 netdev_err(priv->dev, 3597 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3598 __func__, priv->lpi_irq, ret); 3599 irq_err = REQ_IRQ_ERR_LPI; 3600 goto irq_error; 3601 } 3602 } 3603 3604 return 0; 3605 3606 irq_error: 3607 stmmac_free_irq(dev, irq_err, 0); 3608 return ret; 3609 } 3610 3611 static int stmmac_request_irq(struct net_device *dev) 3612 { 3613 struct stmmac_priv *priv = netdev_priv(dev); 3614 int ret; 3615 3616 /* Request the IRQ lines */ 3617 if (priv->plat->multi_msi_en) 3618 ret = stmmac_request_irq_multi_msi(dev); 3619 else 3620 ret = stmmac_request_irq_single(dev); 3621 3622 return ret; 3623 } 3624 3625 /** 3626 * stmmac_open - open entry point of the driver 3627 * @dev : pointer to the device structure. 3628 * Description: 3629 * This function is the open entry point of the driver. 3630 * Return value: 3631 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3632 * file on failure. 3633 */ 3634 int stmmac_open(struct net_device *dev) 3635 { 3636 struct stmmac_priv *priv = netdev_priv(dev); 3637 int bfsize = 0; 3638 u32 chan; 3639 int ret; 3640 3641 ret = pm_runtime_get_sync(priv->device); 3642 if (ret < 0) { 3643 pm_runtime_put_noidle(priv->device); 3644 return ret; 3645 } 3646 3647 if (priv->hw->pcs != STMMAC_PCS_TBI && 3648 priv->hw->pcs != STMMAC_PCS_RTBI && 3649 priv->hw->xpcs_args.an_mode != DW_AN_C73) { 3650 ret = stmmac_init_phy(dev); 3651 if (ret) { 3652 netdev_err(priv->dev, 3653 "%s: Cannot attach to PHY (error: %d)\n", 3654 __func__, ret); 3655 goto init_phy_error; 3656 } 3657 } 3658 3659 /* Extra statistics */ 3660 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3661 priv->xstats.threshold = tc; 3662 3663 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 3664 if (bfsize < 0) 3665 bfsize = 0; 3666 3667 if (bfsize < BUF_SIZE_16KiB) 3668 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 3669 3670 priv->dma_buf_sz = bfsize; 3671 buf_sz = bfsize; 3672 3673 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3674 3675 if (!priv->dma_tx_size) 3676 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3677 if (!priv->dma_rx_size) 3678 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3679 3680 /* Earlier check for TBS */ 3681 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3682 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3683 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3684 3685 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3686 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3687 } 3688 3689 ret = alloc_dma_desc_resources(priv); 3690 if (ret < 0) { 3691 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3692 __func__); 3693 goto dma_desc_error; 3694 } 3695 3696 ret = init_dma_desc_rings(dev, GFP_KERNEL); 3697 if (ret < 0) { 3698 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3699 __func__); 3700 goto init_error; 3701 } 3702 3703 ret = stmmac_hw_setup(dev, true); 3704 if (ret < 0) { 3705 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3706 goto init_error; 3707 } 3708 3709 stmmac_init_coalesce(priv); 3710 3711 phylink_start(priv->phylink); 3712 /* We may have called phylink_speed_down before */ 3713 phylink_speed_up(priv->phylink); 3714 3715 ret = stmmac_request_irq(dev); 3716 if (ret) 3717 goto irq_error; 3718 3719 stmmac_enable_all_queues(priv); 3720 netif_tx_start_all_queues(priv->dev); 3721 3722 return 0; 3723 3724 irq_error: 3725 phylink_stop(priv->phylink); 3726 3727 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3728 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3729 3730 stmmac_hw_teardown(dev); 3731 init_error: 3732 free_dma_desc_resources(priv); 3733 dma_desc_error: 3734 phylink_disconnect_phy(priv->phylink); 3735 init_phy_error: 3736 pm_runtime_put(priv->device); 3737 return ret; 3738 } 3739 3740 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3741 { 3742 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3743 3744 if (priv->fpe_wq) 3745 destroy_workqueue(priv->fpe_wq); 3746 3747 netdev_info(priv->dev, "FPE workqueue stop"); 3748 } 3749 3750 /** 3751 * stmmac_release - close entry point of the driver 3752 * @dev : device pointer. 3753 * Description: 3754 * This is the stop entry point of the driver. 3755 */ 3756 int stmmac_release(struct net_device *dev) 3757 { 3758 struct stmmac_priv *priv = netdev_priv(dev); 3759 u32 chan; 3760 3761 if (device_may_wakeup(priv->device)) 3762 phylink_speed_down(priv->phylink, false); 3763 /* Stop and disconnect the PHY */ 3764 phylink_stop(priv->phylink); 3765 phylink_disconnect_phy(priv->phylink); 3766 3767 stmmac_disable_all_queues(priv); 3768 3769 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3770 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3771 3772 /* Free the IRQ lines */ 3773 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3774 3775 if (priv->eee_enabled) { 3776 priv->tx_path_in_lpi_mode = false; 3777 del_timer_sync(&priv->eee_ctrl_timer); 3778 } 3779 3780 /* Stop TX/RX DMA and clear the descriptors */ 3781 stmmac_stop_all_dma(priv); 3782 3783 /* Release and free the Rx/Tx resources */ 3784 free_dma_desc_resources(priv); 3785 3786 /* Disable the MAC Rx/Tx */ 3787 stmmac_mac_set(priv, priv->ioaddr, false); 3788 3789 netif_carrier_off(dev); 3790 3791 stmmac_release_ptp(priv); 3792 3793 pm_runtime_put(priv->device); 3794 3795 if (priv->dma_cap.fpesel) 3796 stmmac_fpe_stop_wq(priv); 3797 3798 return 0; 3799 } 3800 3801 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3802 struct stmmac_tx_queue *tx_q) 3803 { 3804 u16 tag = 0x0, inner_tag = 0x0; 3805 u32 inner_type = 0x0; 3806 struct dma_desc *p; 3807 3808 if (!priv->dma_cap.vlins) 3809 return false; 3810 if (!skb_vlan_tag_present(skb)) 3811 return false; 3812 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3813 inner_tag = skb_vlan_tag_get(skb); 3814 inner_type = STMMAC_VLAN_INSERT; 3815 } 3816 3817 tag = skb_vlan_tag_get(skb); 3818 3819 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3820 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3821 else 3822 p = &tx_q->dma_tx[tx_q->cur_tx]; 3823 3824 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3825 return false; 3826 3827 stmmac_set_tx_owner(priv, p); 3828 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3829 return true; 3830 } 3831 3832 /** 3833 * stmmac_tso_allocator - close entry point of the driver 3834 * @priv: driver private structure 3835 * @des: buffer start address 3836 * @total_len: total length to fill in descriptors 3837 * @last_segment: condition for the last descriptor 3838 * @queue: TX queue index 3839 * Description: 3840 * This function fills descriptor and request new descriptors according to 3841 * buffer length to fill 3842 */ 3843 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3844 int total_len, bool last_segment, u32 queue) 3845 { 3846 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3847 struct dma_desc *desc; 3848 u32 buff_size; 3849 int tmp_len; 3850 3851 tmp_len = total_len; 3852 3853 while (tmp_len > 0) { 3854 dma_addr_t curr_addr; 3855 3856 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3857 priv->dma_tx_size); 3858 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3859 3860 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3861 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3862 else 3863 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3864 3865 curr_addr = des + (total_len - tmp_len); 3866 if (priv->dma_cap.addr64 <= 32) 3867 desc->des0 = cpu_to_le32(curr_addr); 3868 else 3869 stmmac_set_desc_addr(priv, desc, curr_addr); 3870 3871 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3872 TSO_MAX_BUFF_SIZE : tmp_len; 3873 3874 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3875 0, 1, 3876 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3877 0, 0); 3878 3879 tmp_len -= TSO_MAX_BUFF_SIZE; 3880 } 3881 } 3882 3883 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 3884 { 3885 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3886 int desc_size; 3887 3888 if (likely(priv->extend_desc)) 3889 desc_size = sizeof(struct dma_extended_desc); 3890 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3891 desc_size = sizeof(struct dma_edesc); 3892 else 3893 desc_size = sizeof(struct dma_desc); 3894 3895 /* The own bit must be the latest setting done when prepare the 3896 * descriptor and then barrier is needed to make sure that 3897 * all is coherent before granting the DMA engine. 3898 */ 3899 wmb(); 3900 3901 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3902 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3903 } 3904 3905 /** 3906 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3907 * @skb : the socket buffer 3908 * @dev : device pointer 3909 * Description: this is the transmit function that is called on TSO frames 3910 * (support available on GMAC4 and newer chips). 3911 * Diagram below show the ring programming in case of TSO frames: 3912 * 3913 * First Descriptor 3914 * -------- 3915 * | DES0 |---> buffer1 = L2/L3/L4 header 3916 * | DES1 |---> TCP Payload (can continue on next descr...) 3917 * | DES2 |---> buffer 1 and 2 len 3918 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3919 * -------- 3920 * | 3921 * ... 3922 * | 3923 * -------- 3924 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3925 * | DES1 | --| 3926 * | DES2 | --> buffer 1 and 2 len 3927 * | DES3 | 3928 * -------- 3929 * 3930 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3931 */ 3932 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3933 { 3934 struct dma_desc *desc, *first, *mss_desc = NULL; 3935 struct stmmac_priv *priv = netdev_priv(dev); 3936 int nfrags = skb_shinfo(skb)->nr_frags; 3937 u32 queue = skb_get_queue_mapping(skb); 3938 unsigned int first_entry, tx_packets; 3939 int tmp_pay_len = 0, first_tx; 3940 struct stmmac_tx_queue *tx_q; 3941 bool has_vlan, set_ic; 3942 u8 proto_hdr_len, hdr; 3943 u32 pay_len, mss; 3944 dma_addr_t des; 3945 int i; 3946 3947 tx_q = &priv->tx_queue[queue]; 3948 first_tx = tx_q->cur_tx; 3949 3950 /* Compute header lengths */ 3951 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3952 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3953 hdr = sizeof(struct udphdr); 3954 } else { 3955 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3956 hdr = tcp_hdrlen(skb); 3957 } 3958 3959 /* Desc availability based on threshold should be enough safe */ 3960 if (unlikely(stmmac_tx_avail(priv, queue) < 3961 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3962 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3963 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3964 queue)); 3965 /* This is a hard error, log it. */ 3966 netdev_err(priv->dev, 3967 "%s: Tx Ring full when queue awake\n", 3968 __func__); 3969 } 3970 return NETDEV_TX_BUSY; 3971 } 3972 3973 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3974 3975 mss = skb_shinfo(skb)->gso_size; 3976 3977 /* set new MSS value if needed */ 3978 if (mss != tx_q->mss) { 3979 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3980 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3981 else 3982 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3983 3984 stmmac_set_mss(priv, mss_desc, mss); 3985 tx_q->mss = mss; 3986 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3987 priv->dma_tx_size); 3988 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3989 } 3990 3991 if (netif_msg_tx_queued(priv)) { 3992 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3993 __func__, hdr, proto_hdr_len, pay_len, mss); 3994 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3995 skb->data_len); 3996 } 3997 3998 /* Check if VLAN can be inserted by HW */ 3999 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4000 4001 first_entry = tx_q->cur_tx; 4002 WARN_ON(tx_q->tx_skbuff[first_entry]); 4003 4004 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4005 desc = &tx_q->dma_entx[first_entry].basic; 4006 else 4007 desc = &tx_q->dma_tx[first_entry]; 4008 first = desc; 4009 4010 if (has_vlan) 4011 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4012 4013 /* first descriptor: fill Headers on Buf1 */ 4014 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4015 DMA_TO_DEVICE); 4016 if (dma_mapping_error(priv->device, des)) 4017 goto dma_map_err; 4018 4019 tx_q->tx_skbuff_dma[first_entry].buf = des; 4020 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4021 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4022 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4023 4024 if (priv->dma_cap.addr64 <= 32) { 4025 first->des0 = cpu_to_le32(des); 4026 4027 /* Fill start of payload in buff2 of first descriptor */ 4028 if (pay_len) 4029 first->des1 = cpu_to_le32(des + proto_hdr_len); 4030 4031 /* If needed take extra descriptors to fill the remaining payload */ 4032 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4033 } else { 4034 stmmac_set_desc_addr(priv, first, des); 4035 tmp_pay_len = pay_len; 4036 des += proto_hdr_len; 4037 pay_len = 0; 4038 } 4039 4040 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4041 4042 /* Prepare fragments */ 4043 for (i = 0; i < nfrags; i++) { 4044 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4045 4046 des = skb_frag_dma_map(priv->device, frag, 0, 4047 skb_frag_size(frag), 4048 DMA_TO_DEVICE); 4049 if (dma_mapping_error(priv->device, des)) 4050 goto dma_map_err; 4051 4052 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4053 (i == nfrags - 1), queue); 4054 4055 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4056 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4057 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4058 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4059 } 4060 4061 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4062 4063 /* Only the last descriptor gets to point to the skb. */ 4064 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4065 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4066 4067 /* Manage tx mitigation */ 4068 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4069 tx_q->tx_count_frames += tx_packets; 4070 4071 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4072 set_ic = true; 4073 else if (!priv->tx_coal_frames[queue]) 4074 set_ic = false; 4075 else if (tx_packets > priv->tx_coal_frames[queue]) 4076 set_ic = true; 4077 else if ((tx_q->tx_count_frames % 4078 priv->tx_coal_frames[queue]) < tx_packets) 4079 set_ic = true; 4080 else 4081 set_ic = false; 4082 4083 if (set_ic) { 4084 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4085 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4086 else 4087 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4088 4089 tx_q->tx_count_frames = 0; 4090 stmmac_set_tx_ic(priv, desc); 4091 priv->xstats.tx_set_ic_bit++; 4092 } 4093 4094 /* We've used all descriptors we need for this skb, however, 4095 * advance cur_tx so that it references a fresh descriptor. 4096 * ndo_start_xmit will fill this descriptor the next time it's 4097 * called and stmmac_tx_clean may clean up to this descriptor. 4098 */ 4099 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 4100 4101 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4102 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4103 __func__); 4104 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4105 } 4106 4107 dev->stats.tx_bytes += skb->len; 4108 priv->xstats.tx_tso_frames++; 4109 priv->xstats.tx_tso_nfrags += nfrags; 4110 4111 if (priv->sarc_type) 4112 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4113 4114 skb_tx_timestamp(skb); 4115 4116 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4117 priv->hwts_tx_en)) { 4118 /* declare that device is doing timestamping */ 4119 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4120 stmmac_enable_tx_timestamp(priv, first); 4121 } 4122 4123 /* Complete the first descriptor before granting the DMA */ 4124 stmmac_prepare_tso_tx_desc(priv, first, 1, 4125 proto_hdr_len, 4126 pay_len, 4127 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4128 hdr / 4, (skb->len - proto_hdr_len)); 4129 4130 /* If context desc is used to change MSS */ 4131 if (mss_desc) { 4132 /* Make sure that first descriptor has been completely 4133 * written, including its own bit. This is because MSS is 4134 * actually before first descriptor, so we need to make 4135 * sure that MSS's own bit is the last thing written. 4136 */ 4137 dma_wmb(); 4138 stmmac_set_tx_owner(priv, mss_desc); 4139 } 4140 4141 if (netif_msg_pktdata(priv)) { 4142 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4143 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4144 tx_q->cur_tx, first, nfrags); 4145 pr_info(">>> frame to be transmitted: "); 4146 print_pkt(skb->data, skb_headlen(skb)); 4147 } 4148 4149 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4150 4151 stmmac_flush_tx_descriptors(priv, queue); 4152 stmmac_tx_timer_arm(priv, queue); 4153 4154 return NETDEV_TX_OK; 4155 4156 dma_map_err: 4157 dev_err(priv->device, "Tx dma map failed\n"); 4158 dev_kfree_skb(skb); 4159 priv->dev->stats.tx_dropped++; 4160 return NETDEV_TX_OK; 4161 } 4162 4163 /** 4164 * stmmac_xmit - Tx entry point of the driver 4165 * @skb : the socket buffer 4166 * @dev : device pointer 4167 * Description : this is the tx entry point of the driver. 4168 * It programs the chain or the ring and supports oversized frames 4169 * and SG feature. 4170 */ 4171 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4172 { 4173 unsigned int first_entry, tx_packets, enh_desc; 4174 struct stmmac_priv *priv = netdev_priv(dev); 4175 unsigned int nopaged_len = skb_headlen(skb); 4176 int i, csum_insertion = 0, is_jumbo = 0; 4177 u32 queue = skb_get_queue_mapping(skb); 4178 int nfrags = skb_shinfo(skb)->nr_frags; 4179 int gso = skb_shinfo(skb)->gso_type; 4180 struct dma_edesc *tbs_desc = NULL; 4181 struct dma_desc *desc, *first; 4182 struct stmmac_tx_queue *tx_q; 4183 bool has_vlan, set_ic; 4184 int entry, first_tx; 4185 dma_addr_t des; 4186 4187 tx_q = &priv->tx_queue[queue]; 4188 first_tx = tx_q->cur_tx; 4189 4190 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4191 stmmac_disable_eee_mode(priv); 4192 4193 /* Manage oversized TCP frames for GMAC4 device */ 4194 if (skb_is_gso(skb) && priv->tso) { 4195 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4196 return stmmac_tso_xmit(skb, dev); 4197 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4198 return stmmac_tso_xmit(skb, dev); 4199 } 4200 4201 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4202 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4203 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4204 queue)); 4205 /* This is a hard error, log it. */ 4206 netdev_err(priv->dev, 4207 "%s: Tx Ring full when queue awake\n", 4208 __func__); 4209 } 4210 return NETDEV_TX_BUSY; 4211 } 4212 4213 /* Check if VLAN can be inserted by HW */ 4214 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4215 4216 entry = tx_q->cur_tx; 4217 first_entry = entry; 4218 WARN_ON(tx_q->tx_skbuff[first_entry]); 4219 4220 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4221 4222 if (likely(priv->extend_desc)) 4223 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4224 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4225 desc = &tx_q->dma_entx[entry].basic; 4226 else 4227 desc = tx_q->dma_tx + entry; 4228 4229 first = desc; 4230 4231 if (has_vlan) 4232 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4233 4234 enh_desc = priv->plat->enh_desc; 4235 /* To program the descriptors according to the size of the frame */ 4236 if (enh_desc) 4237 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4238 4239 if (unlikely(is_jumbo)) { 4240 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4241 if (unlikely(entry < 0) && (entry != -EINVAL)) 4242 goto dma_map_err; 4243 } 4244 4245 for (i = 0; i < nfrags; i++) { 4246 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4247 int len = skb_frag_size(frag); 4248 bool last_segment = (i == (nfrags - 1)); 4249 4250 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4251 WARN_ON(tx_q->tx_skbuff[entry]); 4252 4253 if (likely(priv->extend_desc)) 4254 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4255 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4256 desc = &tx_q->dma_entx[entry].basic; 4257 else 4258 desc = tx_q->dma_tx + entry; 4259 4260 des = skb_frag_dma_map(priv->device, frag, 0, len, 4261 DMA_TO_DEVICE); 4262 if (dma_mapping_error(priv->device, des)) 4263 goto dma_map_err; /* should reuse desc w/o issues */ 4264 4265 tx_q->tx_skbuff_dma[entry].buf = des; 4266 4267 stmmac_set_desc_addr(priv, desc, des); 4268 4269 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4270 tx_q->tx_skbuff_dma[entry].len = len; 4271 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4272 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4273 4274 /* Prepare the descriptor and set the own bit too */ 4275 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4276 priv->mode, 1, last_segment, skb->len); 4277 } 4278 4279 /* Only the last descriptor gets to point to the skb. */ 4280 tx_q->tx_skbuff[entry] = skb; 4281 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4282 4283 /* According to the coalesce parameter the IC bit for the latest 4284 * segment is reset and the timer re-started to clean the tx status. 4285 * This approach takes care about the fragments: desc is the first 4286 * element in case of no SG. 4287 */ 4288 tx_packets = (entry + 1) - first_tx; 4289 tx_q->tx_count_frames += tx_packets; 4290 4291 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4292 set_ic = true; 4293 else if (!priv->tx_coal_frames[queue]) 4294 set_ic = false; 4295 else if (tx_packets > priv->tx_coal_frames[queue]) 4296 set_ic = true; 4297 else if ((tx_q->tx_count_frames % 4298 priv->tx_coal_frames[queue]) < tx_packets) 4299 set_ic = true; 4300 else 4301 set_ic = false; 4302 4303 if (set_ic) { 4304 if (likely(priv->extend_desc)) 4305 desc = &tx_q->dma_etx[entry].basic; 4306 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4307 desc = &tx_q->dma_entx[entry].basic; 4308 else 4309 desc = &tx_q->dma_tx[entry]; 4310 4311 tx_q->tx_count_frames = 0; 4312 stmmac_set_tx_ic(priv, desc); 4313 priv->xstats.tx_set_ic_bit++; 4314 } 4315 4316 /* We've used all descriptors we need for this skb, however, 4317 * advance cur_tx so that it references a fresh descriptor. 4318 * ndo_start_xmit will fill this descriptor the next time it's 4319 * called and stmmac_tx_clean may clean up to this descriptor. 4320 */ 4321 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4322 tx_q->cur_tx = entry; 4323 4324 if (netif_msg_pktdata(priv)) { 4325 netdev_dbg(priv->dev, 4326 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4327 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4328 entry, first, nfrags); 4329 4330 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4331 print_pkt(skb->data, skb->len); 4332 } 4333 4334 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4335 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4336 __func__); 4337 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4338 } 4339 4340 dev->stats.tx_bytes += skb->len; 4341 4342 if (priv->sarc_type) 4343 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4344 4345 skb_tx_timestamp(skb); 4346 4347 /* Ready to fill the first descriptor and set the OWN bit w/o any 4348 * problems because all the descriptors are actually ready to be 4349 * passed to the DMA engine. 4350 */ 4351 if (likely(!is_jumbo)) { 4352 bool last_segment = (nfrags == 0); 4353 4354 des = dma_map_single(priv->device, skb->data, 4355 nopaged_len, DMA_TO_DEVICE); 4356 if (dma_mapping_error(priv->device, des)) 4357 goto dma_map_err; 4358 4359 tx_q->tx_skbuff_dma[first_entry].buf = des; 4360 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4361 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4362 4363 stmmac_set_desc_addr(priv, first, des); 4364 4365 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4366 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4367 4368 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4369 priv->hwts_tx_en)) { 4370 /* declare that device is doing timestamping */ 4371 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4372 stmmac_enable_tx_timestamp(priv, first); 4373 } 4374 4375 /* Prepare the first descriptor setting the OWN bit too */ 4376 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4377 csum_insertion, priv->mode, 0, last_segment, 4378 skb->len); 4379 } 4380 4381 if (tx_q->tbs & STMMAC_TBS_EN) { 4382 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4383 4384 tbs_desc = &tx_q->dma_entx[first_entry]; 4385 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4386 } 4387 4388 stmmac_set_tx_owner(priv, first); 4389 4390 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4391 4392 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4393 4394 stmmac_flush_tx_descriptors(priv, queue); 4395 stmmac_tx_timer_arm(priv, queue); 4396 4397 return NETDEV_TX_OK; 4398 4399 dma_map_err: 4400 netdev_err(priv->dev, "Tx DMA map failed\n"); 4401 dev_kfree_skb(skb); 4402 priv->dev->stats.tx_dropped++; 4403 return NETDEV_TX_OK; 4404 } 4405 4406 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4407 { 4408 struct vlan_ethhdr *veth; 4409 __be16 vlan_proto; 4410 u16 vlanid; 4411 4412 veth = (struct vlan_ethhdr *)skb->data; 4413 vlan_proto = veth->h_vlan_proto; 4414 4415 if ((vlan_proto == htons(ETH_P_8021Q) && 4416 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4417 (vlan_proto == htons(ETH_P_8021AD) && 4418 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4419 /* pop the vlan tag */ 4420 vlanid = ntohs(veth->h_vlan_TCI); 4421 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4422 skb_pull(skb, VLAN_HLEN); 4423 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4424 } 4425 } 4426 4427 /** 4428 * stmmac_rx_refill - refill used skb preallocated buffers 4429 * @priv: driver private structure 4430 * @queue: RX queue index 4431 * Description : this is to reallocate the skb for the reception process 4432 * that is based on zero-copy. 4433 */ 4434 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4435 { 4436 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4437 int dirty = stmmac_rx_dirty(priv, queue); 4438 unsigned int entry = rx_q->dirty_rx; 4439 4440 while (dirty-- > 0) { 4441 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4442 struct dma_desc *p; 4443 bool use_rx_wd; 4444 4445 if (priv->extend_desc) 4446 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4447 else 4448 p = rx_q->dma_rx + entry; 4449 4450 if (!buf->page) { 4451 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 4452 if (!buf->page) 4453 break; 4454 } 4455 4456 if (priv->sph && !buf->sec_page) { 4457 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 4458 if (!buf->sec_page) 4459 break; 4460 4461 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4462 } 4463 4464 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4465 4466 stmmac_set_desc_addr(priv, p, buf->addr); 4467 if (priv->sph) 4468 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4469 else 4470 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4471 stmmac_refill_desc3(priv, rx_q, p); 4472 4473 rx_q->rx_count_frames++; 4474 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4475 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4476 rx_q->rx_count_frames = 0; 4477 4478 use_rx_wd = !priv->rx_coal_frames[queue]; 4479 use_rx_wd |= rx_q->rx_count_frames > 0; 4480 if (!priv->use_riwt) 4481 use_rx_wd = false; 4482 4483 dma_wmb(); 4484 stmmac_set_rx_owner(priv, p, use_rx_wd); 4485 4486 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4487 } 4488 rx_q->dirty_rx = entry; 4489 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4490 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4491 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4492 } 4493 4494 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4495 struct dma_desc *p, 4496 int status, unsigned int len) 4497 { 4498 unsigned int plen = 0, hlen = 0; 4499 int coe = priv->hw->rx_csum; 4500 4501 /* Not first descriptor, buffer is always zero */ 4502 if (priv->sph && len) 4503 return 0; 4504 4505 /* First descriptor, get split header length */ 4506 stmmac_get_rx_header_len(priv, p, &hlen); 4507 if (priv->sph && hlen) { 4508 priv->xstats.rx_split_hdr_pkt_n++; 4509 return hlen; 4510 } 4511 4512 /* First descriptor, not last descriptor and not split header */ 4513 if (status & rx_not_ls) 4514 return priv->dma_buf_sz; 4515 4516 plen = stmmac_get_rx_frame_len(priv, p, coe); 4517 4518 /* First descriptor and last descriptor and not split header */ 4519 return min_t(unsigned int, priv->dma_buf_sz, plen); 4520 } 4521 4522 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4523 struct dma_desc *p, 4524 int status, unsigned int len) 4525 { 4526 int coe = priv->hw->rx_csum; 4527 unsigned int plen = 0; 4528 4529 /* Not split header, buffer is not available */ 4530 if (!priv->sph) 4531 return 0; 4532 4533 /* Not last descriptor */ 4534 if (status & rx_not_ls) 4535 return priv->dma_buf_sz; 4536 4537 plen = stmmac_get_rx_frame_len(priv, p, coe); 4538 4539 /* Last descriptor */ 4540 return plen - len; 4541 } 4542 4543 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4544 struct xdp_frame *xdpf, bool dma_map) 4545 { 4546 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4547 unsigned int entry = tx_q->cur_tx; 4548 struct dma_desc *tx_desc; 4549 dma_addr_t dma_addr; 4550 bool set_ic; 4551 4552 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4553 return STMMAC_XDP_CONSUMED; 4554 4555 if (likely(priv->extend_desc)) 4556 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4557 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4558 tx_desc = &tx_q->dma_entx[entry].basic; 4559 else 4560 tx_desc = tx_q->dma_tx + entry; 4561 4562 if (dma_map) { 4563 dma_addr = dma_map_single(priv->device, xdpf->data, 4564 xdpf->len, DMA_TO_DEVICE); 4565 if (dma_mapping_error(priv->device, dma_addr)) 4566 return STMMAC_XDP_CONSUMED; 4567 4568 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4569 } else { 4570 struct page *page = virt_to_page(xdpf->data); 4571 4572 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4573 xdpf->headroom; 4574 dma_sync_single_for_device(priv->device, dma_addr, 4575 xdpf->len, DMA_BIDIRECTIONAL); 4576 4577 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4578 } 4579 4580 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4581 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4582 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4583 tx_q->tx_skbuff_dma[entry].last_segment = true; 4584 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4585 4586 tx_q->xdpf[entry] = xdpf; 4587 4588 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4589 4590 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4591 true, priv->mode, true, true, 4592 xdpf->len); 4593 4594 tx_q->tx_count_frames++; 4595 4596 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4597 set_ic = true; 4598 else 4599 set_ic = false; 4600 4601 if (set_ic) { 4602 tx_q->tx_count_frames = 0; 4603 stmmac_set_tx_ic(priv, tx_desc); 4604 priv->xstats.tx_set_ic_bit++; 4605 } 4606 4607 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4608 4609 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4610 tx_q->cur_tx = entry; 4611 4612 return STMMAC_XDP_TX; 4613 } 4614 4615 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4616 int cpu) 4617 { 4618 int index = cpu; 4619 4620 if (unlikely(index < 0)) 4621 index = 0; 4622 4623 while (index >= priv->plat->tx_queues_to_use) 4624 index -= priv->plat->tx_queues_to_use; 4625 4626 return index; 4627 } 4628 4629 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4630 struct xdp_buff *xdp) 4631 { 4632 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4633 int cpu = smp_processor_id(); 4634 struct netdev_queue *nq; 4635 int queue; 4636 int res; 4637 4638 if (unlikely(!xdpf)) 4639 return STMMAC_XDP_CONSUMED; 4640 4641 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4642 nq = netdev_get_tx_queue(priv->dev, queue); 4643 4644 __netif_tx_lock(nq, cpu); 4645 /* Avoids TX time-out as we are sharing with slow path */ 4646 nq->trans_start = jiffies; 4647 4648 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4649 if (res == STMMAC_XDP_TX) 4650 stmmac_flush_tx_descriptors(priv, queue); 4651 4652 __netif_tx_unlock(nq); 4653 4654 return res; 4655 } 4656 4657 /* This function assumes rcu_read_lock() is held by the caller. */ 4658 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4659 struct bpf_prog *prog, 4660 struct xdp_buff *xdp) 4661 { 4662 u32 act; 4663 int res; 4664 4665 act = bpf_prog_run_xdp(prog, xdp); 4666 switch (act) { 4667 case XDP_PASS: 4668 res = STMMAC_XDP_PASS; 4669 break; 4670 case XDP_TX: 4671 res = stmmac_xdp_xmit_back(priv, xdp); 4672 break; 4673 case XDP_REDIRECT: 4674 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4675 res = STMMAC_XDP_CONSUMED; 4676 else 4677 res = STMMAC_XDP_REDIRECT; 4678 break; 4679 default: 4680 bpf_warn_invalid_xdp_action(act); 4681 fallthrough; 4682 case XDP_ABORTED: 4683 trace_xdp_exception(priv->dev, prog, act); 4684 fallthrough; 4685 case XDP_DROP: 4686 res = STMMAC_XDP_CONSUMED; 4687 break; 4688 } 4689 4690 return res; 4691 } 4692 4693 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4694 struct xdp_buff *xdp) 4695 { 4696 struct bpf_prog *prog; 4697 int res; 4698 4699 rcu_read_lock(); 4700 4701 prog = READ_ONCE(priv->xdp_prog); 4702 if (!prog) { 4703 res = STMMAC_XDP_PASS; 4704 goto unlock; 4705 } 4706 4707 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4708 unlock: 4709 rcu_read_unlock(); 4710 return ERR_PTR(-res); 4711 } 4712 4713 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4714 int xdp_status) 4715 { 4716 int cpu = smp_processor_id(); 4717 int queue; 4718 4719 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4720 4721 if (xdp_status & STMMAC_XDP_TX) 4722 stmmac_tx_timer_arm(priv, queue); 4723 4724 if (xdp_status & STMMAC_XDP_REDIRECT) 4725 xdp_do_flush(); 4726 } 4727 4728 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4729 struct xdp_buff *xdp) 4730 { 4731 unsigned int metasize = xdp->data - xdp->data_meta; 4732 unsigned int datasize = xdp->data_end - xdp->data; 4733 struct sk_buff *skb; 4734 4735 skb = __napi_alloc_skb(&ch->rxtx_napi, 4736 xdp->data_end - xdp->data_hard_start, 4737 GFP_ATOMIC | __GFP_NOWARN); 4738 if (unlikely(!skb)) 4739 return NULL; 4740 4741 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4742 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4743 if (metasize) 4744 skb_metadata_set(skb, metasize); 4745 4746 return skb; 4747 } 4748 4749 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4750 struct dma_desc *p, struct dma_desc *np, 4751 struct xdp_buff *xdp) 4752 { 4753 struct stmmac_channel *ch = &priv->channel[queue]; 4754 unsigned int len = xdp->data_end - xdp->data; 4755 enum pkt_hash_types hash_type; 4756 int coe = priv->hw->rx_csum; 4757 struct sk_buff *skb; 4758 u32 hash; 4759 4760 skb = stmmac_construct_skb_zc(ch, xdp); 4761 if (!skb) { 4762 priv->dev->stats.rx_dropped++; 4763 return; 4764 } 4765 4766 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4767 stmmac_rx_vlan(priv->dev, skb); 4768 skb->protocol = eth_type_trans(skb, priv->dev); 4769 4770 if (unlikely(!coe)) 4771 skb_checksum_none_assert(skb); 4772 else 4773 skb->ip_summed = CHECKSUM_UNNECESSARY; 4774 4775 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4776 skb_set_hash(skb, hash, hash_type); 4777 4778 skb_record_rx_queue(skb, queue); 4779 napi_gro_receive(&ch->rxtx_napi, skb); 4780 4781 priv->dev->stats.rx_packets++; 4782 priv->dev->stats.rx_bytes += len; 4783 } 4784 4785 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4786 { 4787 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4788 unsigned int entry = rx_q->dirty_rx; 4789 struct dma_desc *rx_desc = NULL; 4790 bool ret = true; 4791 4792 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4793 4794 while (budget-- > 0 && entry != rx_q->cur_rx) { 4795 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4796 dma_addr_t dma_addr; 4797 bool use_rx_wd; 4798 4799 if (!buf->xdp) { 4800 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4801 if (!buf->xdp) { 4802 ret = false; 4803 break; 4804 } 4805 } 4806 4807 if (priv->extend_desc) 4808 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4809 else 4810 rx_desc = rx_q->dma_rx + entry; 4811 4812 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4813 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4814 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4815 stmmac_refill_desc3(priv, rx_q, rx_desc); 4816 4817 rx_q->rx_count_frames++; 4818 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4819 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4820 rx_q->rx_count_frames = 0; 4821 4822 use_rx_wd = !priv->rx_coal_frames[queue]; 4823 use_rx_wd |= rx_q->rx_count_frames > 0; 4824 if (!priv->use_riwt) 4825 use_rx_wd = false; 4826 4827 dma_wmb(); 4828 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4829 4830 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4831 } 4832 4833 if (rx_desc) { 4834 rx_q->dirty_rx = entry; 4835 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4836 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4837 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4838 } 4839 4840 return ret; 4841 } 4842 4843 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4844 { 4845 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4846 unsigned int count = 0, error = 0, len = 0; 4847 int dirty = stmmac_rx_dirty(priv, queue); 4848 unsigned int next_entry = rx_q->cur_rx; 4849 unsigned int desc_size; 4850 struct bpf_prog *prog; 4851 bool failure = false; 4852 int xdp_status = 0; 4853 int status = 0; 4854 4855 if (netif_msg_rx_status(priv)) { 4856 void *rx_head; 4857 4858 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4859 if (priv->extend_desc) { 4860 rx_head = (void *)rx_q->dma_erx; 4861 desc_size = sizeof(struct dma_extended_desc); 4862 } else { 4863 rx_head = (void *)rx_q->dma_rx; 4864 desc_size = sizeof(struct dma_desc); 4865 } 4866 4867 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 4868 rx_q->dma_rx_phy, desc_size); 4869 } 4870 while (count < limit) { 4871 struct stmmac_rx_buffer *buf; 4872 unsigned int buf1_len = 0; 4873 struct dma_desc *np, *p; 4874 int entry; 4875 int res; 4876 4877 if (!count && rx_q->state_saved) { 4878 error = rx_q->state.error; 4879 len = rx_q->state.len; 4880 } else { 4881 rx_q->state_saved = false; 4882 error = 0; 4883 len = 0; 4884 } 4885 4886 if (count >= limit) 4887 break; 4888 4889 read_again: 4890 buf1_len = 0; 4891 entry = next_entry; 4892 buf = &rx_q->buf_pool[entry]; 4893 4894 if (dirty >= STMMAC_RX_FILL_BATCH) { 4895 failure = failure || 4896 !stmmac_rx_refill_zc(priv, queue, dirty); 4897 dirty = 0; 4898 } 4899 4900 if (priv->extend_desc) 4901 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4902 else 4903 p = rx_q->dma_rx + entry; 4904 4905 /* read the status of the incoming frame */ 4906 status = stmmac_rx_status(priv, &priv->dev->stats, 4907 &priv->xstats, p); 4908 /* check if managed by the DMA otherwise go ahead */ 4909 if (unlikely(status & dma_own)) 4910 break; 4911 4912 /* Prefetch the next RX descriptor */ 4913 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 4914 priv->dma_rx_size); 4915 next_entry = rx_q->cur_rx; 4916 4917 if (priv->extend_desc) 4918 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 4919 else 4920 np = rx_q->dma_rx + next_entry; 4921 4922 prefetch(np); 4923 4924 if (priv->extend_desc) 4925 stmmac_rx_extended_status(priv, &priv->dev->stats, 4926 &priv->xstats, 4927 rx_q->dma_erx + entry); 4928 if (unlikely(status == discard_frame)) { 4929 xsk_buff_free(buf->xdp); 4930 buf->xdp = NULL; 4931 dirty++; 4932 error = 1; 4933 if (!priv->hwts_rx_en) 4934 priv->dev->stats.rx_errors++; 4935 } 4936 4937 if (unlikely(error && (status & rx_not_ls))) 4938 goto read_again; 4939 if (unlikely(error)) { 4940 count++; 4941 continue; 4942 } 4943 4944 /* Ensure a valid XSK buffer before proceed */ 4945 if (!buf->xdp) 4946 break; 4947 4948 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 4949 if (likely(status & rx_not_ls)) { 4950 xsk_buff_free(buf->xdp); 4951 buf->xdp = NULL; 4952 dirty++; 4953 count++; 4954 goto read_again; 4955 } 4956 4957 /* XDP ZC Frame only support primary buffers for now */ 4958 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 4959 len += buf1_len; 4960 4961 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 4962 * Type frames (LLC/LLC-SNAP) 4963 * 4964 * llc_snap is never checked in GMAC >= 4, so this ACS 4965 * feature is always disabled and packets need to be 4966 * stripped manually. 4967 */ 4968 if (likely(!(status & rx_not_ls)) && 4969 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 4970 unlikely(status != llc_snap))) { 4971 buf1_len -= ETH_FCS_LEN; 4972 len -= ETH_FCS_LEN; 4973 } 4974 4975 /* RX buffer is good and fit into a XSK pool buffer */ 4976 buf->xdp->data_end = buf->xdp->data + buf1_len; 4977 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 4978 4979 rcu_read_lock(); 4980 prog = READ_ONCE(priv->xdp_prog); 4981 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 4982 rcu_read_unlock(); 4983 4984 switch (res) { 4985 case STMMAC_XDP_PASS: 4986 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 4987 xsk_buff_free(buf->xdp); 4988 break; 4989 case STMMAC_XDP_CONSUMED: 4990 xsk_buff_free(buf->xdp); 4991 priv->dev->stats.rx_dropped++; 4992 break; 4993 case STMMAC_XDP_TX: 4994 case STMMAC_XDP_REDIRECT: 4995 xdp_status |= res; 4996 break; 4997 } 4998 4999 buf->xdp = NULL; 5000 dirty++; 5001 count++; 5002 } 5003 5004 if (status & rx_not_ls) { 5005 rx_q->state_saved = true; 5006 rx_q->state.error = error; 5007 rx_q->state.len = len; 5008 } 5009 5010 stmmac_finalize_xdp_rx(priv, xdp_status); 5011 5012 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5013 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5014 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5015 else 5016 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5017 5018 return (int)count; 5019 } 5020 5021 return failure ? limit : (int)count; 5022 } 5023 5024 /** 5025 * stmmac_rx - manage the receive process 5026 * @priv: driver private structure 5027 * @limit: napi bugget 5028 * @queue: RX queue index. 5029 * Description : this the function called by the napi poll method. 5030 * It gets all the frames inside the ring. 5031 */ 5032 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5033 { 5034 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5035 struct stmmac_channel *ch = &priv->channel[queue]; 5036 unsigned int count = 0, error = 0, len = 0; 5037 int status = 0, coe = priv->hw->rx_csum; 5038 unsigned int next_entry = rx_q->cur_rx; 5039 enum dma_data_direction dma_dir; 5040 unsigned int desc_size; 5041 struct sk_buff *skb = NULL; 5042 struct xdp_buff xdp; 5043 int xdp_status = 0; 5044 int buf_sz; 5045 5046 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5047 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5048 5049 if (netif_msg_rx_status(priv)) { 5050 void *rx_head; 5051 5052 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5053 if (priv->extend_desc) { 5054 rx_head = (void *)rx_q->dma_erx; 5055 desc_size = sizeof(struct dma_extended_desc); 5056 } else { 5057 rx_head = (void *)rx_q->dma_rx; 5058 desc_size = sizeof(struct dma_desc); 5059 } 5060 5061 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 5062 rx_q->dma_rx_phy, desc_size); 5063 } 5064 while (count < limit) { 5065 unsigned int buf1_len = 0, buf2_len = 0; 5066 enum pkt_hash_types hash_type; 5067 struct stmmac_rx_buffer *buf; 5068 struct dma_desc *np, *p; 5069 int entry; 5070 u32 hash; 5071 5072 if (!count && rx_q->state_saved) { 5073 skb = rx_q->state.skb; 5074 error = rx_q->state.error; 5075 len = rx_q->state.len; 5076 } else { 5077 rx_q->state_saved = false; 5078 skb = NULL; 5079 error = 0; 5080 len = 0; 5081 } 5082 5083 if (count >= limit) 5084 break; 5085 5086 read_again: 5087 buf1_len = 0; 5088 buf2_len = 0; 5089 entry = next_entry; 5090 buf = &rx_q->buf_pool[entry]; 5091 5092 if (priv->extend_desc) 5093 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5094 else 5095 p = rx_q->dma_rx + entry; 5096 5097 /* read the status of the incoming frame */ 5098 status = stmmac_rx_status(priv, &priv->dev->stats, 5099 &priv->xstats, p); 5100 /* check if managed by the DMA otherwise go ahead */ 5101 if (unlikely(status & dma_own)) 5102 break; 5103 5104 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5105 priv->dma_rx_size); 5106 next_entry = rx_q->cur_rx; 5107 5108 if (priv->extend_desc) 5109 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5110 else 5111 np = rx_q->dma_rx + next_entry; 5112 5113 prefetch(np); 5114 5115 if (priv->extend_desc) 5116 stmmac_rx_extended_status(priv, &priv->dev->stats, 5117 &priv->xstats, rx_q->dma_erx + entry); 5118 if (unlikely(status == discard_frame)) { 5119 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5120 buf->page = NULL; 5121 error = 1; 5122 if (!priv->hwts_rx_en) 5123 priv->dev->stats.rx_errors++; 5124 } 5125 5126 if (unlikely(error && (status & rx_not_ls))) 5127 goto read_again; 5128 if (unlikely(error)) { 5129 dev_kfree_skb(skb); 5130 skb = NULL; 5131 count++; 5132 continue; 5133 } 5134 5135 /* Buffer is good. Go on. */ 5136 5137 prefetch(page_address(buf->page)); 5138 if (buf->sec_page) 5139 prefetch(page_address(buf->sec_page)); 5140 5141 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5142 len += buf1_len; 5143 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5144 len += buf2_len; 5145 5146 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 5147 * Type frames (LLC/LLC-SNAP) 5148 * 5149 * llc_snap is never checked in GMAC >= 4, so this ACS 5150 * feature is always disabled and packets need to be 5151 * stripped manually. 5152 */ 5153 if (likely(!(status & rx_not_ls)) && 5154 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 5155 unlikely(status != llc_snap))) { 5156 if (buf2_len) 5157 buf2_len -= ETH_FCS_LEN; 5158 else 5159 buf1_len -= ETH_FCS_LEN; 5160 5161 len -= ETH_FCS_LEN; 5162 } 5163 5164 if (!skb) { 5165 unsigned int pre_len, sync_len; 5166 5167 dma_sync_single_for_cpu(priv->device, buf->addr, 5168 buf1_len, dma_dir); 5169 5170 xdp.data = page_address(buf->page) + buf->page_offset; 5171 xdp.data_end = xdp.data + buf1_len; 5172 xdp.data_hard_start = page_address(buf->page); 5173 xdp_set_data_meta_invalid(&xdp); 5174 xdp.frame_sz = buf_sz; 5175 xdp.rxq = &rx_q->xdp_rxq; 5176 5177 pre_len = xdp.data_end - xdp.data_hard_start - 5178 buf->page_offset; 5179 skb = stmmac_xdp_run_prog(priv, &xdp); 5180 /* Due xdp_adjust_tail: DMA sync for_device 5181 * cover max len CPU touch 5182 */ 5183 sync_len = xdp.data_end - xdp.data_hard_start - 5184 buf->page_offset; 5185 sync_len = max(sync_len, pre_len); 5186 5187 /* For Not XDP_PASS verdict */ 5188 if (IS_ERR(skb)) { 5189 unsigned int xdp_res = -PTR_ERR(skb); 5190 5191 if (xdp_res & STMMAC_XDP_CONSUMED) { 5192 page_pool_put_page(rx_q->page_pool, 5193 virt_to_head_page(xdp.data), 5194 sync_len, true); 5195 buf->page = NULL; 5196 priv->dev->stats.rx_dropped++; 5197 5198 /* Clear skb as it was set as 5199 * status by XDP program. 5200 */ 5201 skb = NULL; 5202 5203 if (unlikely((status & rx_not_ls))) 5204 goto read_again; 5205 5206 count++; 5207 continue; 5208 } else if (xdp_res & (STMMAC_XDP_TX | 5209 STMMAC_XDP_REDIRECT)) { 5210 xdp_status |= xdp_res; 5211 buf->page = NULL; 5212 skb = NULL; 5213 count++; 5214 continue; 5215 } 5216 } 5217 } 5218 5219 if (!skb) { 5220 /* XDP program may expand or reduce tail */ 5221 buf1_len = xdp.data_end - xdp.data; 5222 5223 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5224 if (!skb) { 5225 priv->dev->stats.rx_dropped++; 5226 count++; 5227 goto drain_data; 5228 } 5229 5230 /* XDP program may adjust header */ 5231 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5232 skb_put(skb, buf1_len); 5233 5234 /* Data payload copied into SKB, page ready for recycle */ 5235 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5236 buf->page = NULL; 5237 } else if (buf1_len) { 5238 dma_sync_single_for_cpu(priv->device, buf->addr, 5239 buf1_len, dma_dir); 5240 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5241 buf->page, buf->page_offset, buf1_len, 5242 priv->dma_buf_sz); 5243 5244 /* Data payload appended into SKB */ 5245 page_pool_release_page(rx_q->page_pool, buf->page); 5246 buf->page = NULL; 5247 } 5248 5249 if (buf2_len) { 5250 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5251 buf2_len, dma_dir); 5252 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5253 buf->sec_page, 0, buf2_len, 5254 priv->dma_buf_sz); 5255 5256 /* Data payload appended into SKB */ 5257 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5258 buf->sec_page = NULL; 5259 } 5260 5261 drain_data: 5262 if (likely(status & rx_not_ls)) 5263 goto read_again; 5264 if (!skb) 5265 continue; 5266 5267 /* Got entire packet into SKB. Finish it. */ 5268 5269 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5270 stmmac_rx_vlan(priv->dev, skb); 5271 skb->protocol = eth_type_trans(skb, priv->dev); 5272 5273 if (unlikely(!coe)) 5274 skb_checksum_none_assert(skb); 5275 else 5276 skb->ip_summed = CHECKSUM_UNNECESSARY; 5277 5278 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5279 skb_set_hash(skb, hash, hash_type); 5280 5281 skb_record_rx_queue(skb, queue); 5282 napi_gro_receive(&ch->rx_napi, skb); 5283 skb = NULL; 5284 5285 priv->dev->stats.rx_packets++; 5286 priv->dev->stats.rx_bytes += len; 5287 count++; 5288 } 5289 5290 if (status & rx_not_ls || skb) { 5291 rx_q->state_saved = true; 5292 rx_q->state.skb = skb; 5293 rx_q->state.error = error; 5294 rx_q->state.len = len; 5295 } 5296 5297 stmmac_finalize_xdp_rx(priv, xdp_status); 5298 5299 stmmac_rx_refill(priv, queue); 5300 5301 priv->xstats.rx_pkt_n += count; 5302 5303 return count; 5304 } 5305 5306 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5307 { 5308 struct stmmac_channel *ch = 5309 container_of(napi, struct stmmac_channel, rx_napi); 5310 struct stmmac_priv *priv = ch->priv_data; 5311 u32 chan = ch->index; 5312 int work_done; 5313 5314 priv->xstats.napi_poll++; 5315 5316 work_done = stmmac_rx(priv, budget, chan); 5317 if (work_done < budget && napi_complete_done(napi, work_done)) { 5318 unsigned long flags; 5319 5320 spin_lock_irqsave(&ch->lock, flags); 5321 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5322 spin_unlock_irqrestore(&ch->lock, flags); 5323 } 5324 5325 return work_done; 5326 } 5327 5328 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5329 { 5330 struct stmmac_channel *ch = 5331 container_of(napi, struct stmmac_channel, tx_napi); 5332 struct stmmac_priv *priv = ch->priv_data; 5333 u32 chan = ch->index; 5334 int work_done; 5335 5336 priv->xstats.napi_poll++; 5337 5338 work_done = stmmac_tx_clean(priv, budget, chan); 5339 work_done = min(work_done, budget); 5340 5341 if (work_done < budget && napi_complete_done(napi, work_done)) { 5342 unsigned long flags; 5343 5344 spin_lock_irqsave(&ch->lock, flags); 5345 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5346 spin_unlock_irqrestore(&ch->lock, flags); 5347 } 5348 5349 return work_done; 5350 } 5351 5352 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5353 { 5354 struct stmmac_channel *ch = 5355 container_of(napi, struct stmmac_channel, rxtx_napi); 5356 struct stmmac_priv *priv = ch->priv_data; 5357 int rx_done, tx_done; 5358 u32 chan = ch->index; 5359 5360 priv->xstats.napi_poll++; 5361 5362 tx_done = stmmac_tx_clean(priv, budget, chan); 5363 tx_done = min(tx_done, budget); 5364 5365 rx_done = stmmac_rx_zc(priv, budget, chan); 5366 5367 /* If either TX or RX work is not complete, return budget 5368 * and keep pooling 5369 */ 5370 if (tx_done >= budget || rx_done >= budget) 5371 return budget; 5372 5373 /* all work done, exit the polling mode */ 5374 if (napi_complete_done(napi, rx_done)) { 5375 unsigned long flags; 5376 5377 spin_lock_irqsave(&ch->lock, flags); 5378 /* Both RX and TX work done are compelte, 5379 * so enable both RX & TX IRQs. 5380 */ 5381 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5382 spin_unlock_irqrestore(&ch->lock, flags); 5383 } 5384 5385 return min(rx_done, budget - 1); 5386 } 5387 5388 /** 5389 * stmmac_tx_timeout 5390 * @dev : Pointer to net device structure 5391 * @txqueue: the index of the hanging transmit queue 5392 * Description: this function is called when a packet transmission fails to 5393 * complete within a reasonable time. The driver will mark the error in the 5394 * netdev structure and arrange for the device to be reset to a sane state 5395 * in order to transmit a new packet. 5396 */ 5397 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5398 { 5399 struct stmmac_priv *priv = netdev_priv(dev); 5400 5401 stmmac_global_err(priv); 5402 } 5403 5404 /** 5405 * stmmac_set_rx_mode - entry point for multicast addressing 5406 * @dev : pointer to the device structure 5407 * Description: 5408 * This function is a driver entry point which gets called by the kernel 5409 * whenever multicast addresses must be enabled/disabled. 5410 * Return value: 5411 * void. 5412 */ 5413 static void stmmac_set_rx_mode(struct net_device *dev) 5414 { 5415 struct stmmac_priv *priv = netdev_priv(dev); 5416 5417 stmmac_set_filter(priv, priv->hw, dev); 5418 } 5419 5420 /** 5421 * stmmac_change_mtu - entry point to change MTU size for the device. 5422 * @dev : device pointer. 5423 * @new_mtu : the new MTU size for the device. 5424 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5425 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5426 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5427 * Return value: 5428 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5429 * file on failure. 5430 */ 5431 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5432 { 5433 struct stmmac_priv *priv = netdev_priv(dev); 5434 int txfifosz = priv->plat->tx_fifo_size; 5435 const int mtu = new_mtu; 5436 5437 if (txfifosz == 0) 5438 txfifosz = priv->dma_cap.tx_fifo_size; 5439 5440 txfifosz /= priv->plat->tx_queues_to_use; 5441 5442 if (netif_running(dev)) { 5443 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 5444 return -EBUSY; 5445 } 5446 5447 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5448 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5449 return -EINVAL; 5450 } 5451 5452 new_mtu = STMMAC_ALIGN(new_mtu); 5453 5454 /* If condition true, FIFO is too small or MTU too large */ 5455 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5456 return -EINVAL; 5457 5458 dev->mtu = mtu; 5459 5460 netdev_update_features(dev); 5461 5462 return 0; 5463 } 5464 5465 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5466 netdev_features_t features) 5467 { 5468 struct stmmac_priv *priv = netdev_priv(dev); 5469 5470 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5471 features &= ~NETIF_F_RXCSUM; 5472 5473 if (!priv->plat->tx_coe) 5474 features &= ~NETIF_F_CSUM_MASK; 5475 5476 /* Some GMAC devices have a bugged Jumbo frame support that 5477 * needs to have the Tx COE disabled for oversized frames 5478 * (due to limited buffer sizes). In this case we disable 5479 * the TX csum insertion in the TDES and not use SF. 5480 */ 5481 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5482 features &= ~NETIF_F_CSUM_MASK; 5483 5484 /* Disable tso if asked by ethtool */ 5485 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5486 if (features & NETIF_F_TSO) 5487 priv->tso = true; 5488 else 5489 priv->tso = false; 5490 } 5491 5492 return features; 5493 } 5494 5495 static int stmmac_set_features(struct net_device *netdev, 5496 netdev_features_t features) 5497 { 5498 struct stmmac_priv *priv = netdev_priv(netdev); 5499 bool sph_en; 5500 u32 chan; 5501 5502 /* Keep the COE Type in case of csum is supporting */ 5503 if (features & NETIF_F_RXCSUM) 5504 priv->hw->rx_csum = priv->plat->rx_coe; 5505 else 5506 priv->hw->rx_csum = 0; 5507 /* No check needed because rx_coe has been set before and it will be 5508 * fixed in case of issue. 5509 */ 5510 stmmac_rx_ipc(priv, priv->hw); 5511 5512 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5513 5514 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5515 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5516 5517 return 0; 5518 } 5519 5520 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5521 { 5522 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5523 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5524 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5525 bool *hs_enable = &fpe_cfg->hs_enable; 5526 5527 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5528 return; 5529 5530 /* If LP has sent verify mPacket, LP is FPE capable */ 5531 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5532 if (*lp_state < FPE_STATE_CAPABLE) 5533 *lp_state = FPE_STATE_CAPABLE; 5534 5535 /* If user has requested FPE enable, quickly response */ 5536 if (*hs_enable) 5537 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5538 MPACKET_RESPONSE); 5539 } 5540 5541 /* If Local has sent verify mPacket, Local is FPE capable */ 5542 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5543 if (*lo_state < FPE_STATE_CAPABLE) 5544 *lo_state = FPE_STATE_CAPABLE; 5545 } 5546 5547 /* If LP has sent response mPacket, LP is entering FPE ON */ 5548 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5549 *lp_state = FPE_STATE_ENTERING_ON; 5550 5551 /* If Local has sent response mPacket, Local is entering FPE ON */ 5552 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5553 *lo_state = FPE_STATE_ENTERING_ON; 5554 5555 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5556 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5557 priv->fpe_wq) { 5558 queue_work(priv->fpe_wq, &priv->fpe_task); 5559 } 5560 } 5561 5562 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5563 { 5564 u32 rx_cnt = priv->plat->rx_queues_to_use; 5565 u32 tx_cnt = priv->plat->tx_queues_to_use; 5566 u32 queues_count; 5567 u32 queue; 5568 bool xmac; 5569 5570 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5571 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5572 5573 if (priv->irq_wake) 5574 pm_wakeup_event(priv->device, 0); 5575 5576 if (priv->dma_cap.estsel) 5577 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5578 &priv->xstats, tx_cnt); 5579 5580 if (priv->dma_cap.fpesel) { 5581 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5582 priv->dev); 5583 5584 stmmac_fpe_event_status(priv, status); 5585 } 5586 5587 /* To handle GMAC own interrupts */ 5588 if ((priv->plat->has_gmac) || xmac) { 5589 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5590 5591 if (unlikely(status)) { 5592 /* For LPI we need to save the tx status */ 5593 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5594 priv->tx_path_in_lpi_mode = true; 5595 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5596 priv->tx_path_in_lpi_mode = false; 5597 } 5598 5599 for (queue = 0; queue < queues_count; queue++) { 5600 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5601 queue); 5602 } 5603 5604 /* PCS link status */ 5605 if (priv->hw->pcs) { 5606 if (priv->xstats.pcs_link) 5607 netif_carrier_on(priv->dev); 5608 else 5609 netif_carrier_off(priv->dev); 5610 } 5611 5612 stmmac_timestamp_interrupt(priv, priv); 5613 } 5614 } 5615 5616 /** 5617 * stmmac_interrupt - main ISR 5618 * @irq: interrupt number. 5619 * @dev_id: to pass the net device pointer. 5620 * Description: this is the main driver interrupt service routine. 5621 * It can call: 5622 * o DMA service routine (to manage incoming frame reception and transmission 5623 * status) 5624 * o Core interrupts to manage: remote wake-up, management counter, LPI 5625 * interrupts. 5626 */ 5627 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5628 { 5629 struct net_device *dev = (struct net_device *)dev_id; 5630 struct stmmac_priv *priv = netdev_priv(dev); 5631 5632 /* Check if adapter is up */ 5633 if (test_bit(STMMAC_DOWN, &priv->state)) 5634 return IRQ_HANDLED; 5635 5636 /* Check if a fatal error happened */ 5637 if (stmmac_safety_feat_interrupt(priv)) 5638 return IRQ_HANDLED; 5639 5640 /* To handle Common interrupts */ 5641 stmmac_common_interrupt(priv); 5642 5643 /* To handle DMA interrupts */ 5644 stmmac_dma_interrupt(priv); 5645 5646 return IRQ_HANDLED; 5647 } 5648 5649 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5650 { 5651 struct net_device *dev = (struct net_device *)dev_id; 5652 struct stmmac_priv *priv = netdev_priv(dev); 5653 5654 if (unlikely(!dev)) { 5655 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5656 return IRQ_NONE; 5657 } 5658 5659 /* Check if adapter is up */ 5660 if (test_bit(STMMAC_DOWN, &priv->state)) 5661 return IRQ_HANDLED; 5662 5663 /* To handle Common interrupts */ 5664 stmmac_common_interrupt(priv); 5665 5666 return IRQ_HANDLED; 5667 } 5668 5669 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5670 { 5671 struct net_device *dev = (struct net_device *)dev_id; 5672 struct stmmac_priv *priv = netdev_priv(dev); 5673 5674 if (unlikely(!dev)) { 5675 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5676 return IRQ_NONE; 5677 } 5678 5679 /* Check if adapter is up */ 5680 if (test_bit(STMMAC_DOWN, &priv->state)) 5681 return IRQ_HANDLED; 5682 5683 /* Check if a fatal error happened */ 5684 stmmac_safety_feat_interrupt(priv); 5685 5686 return IRQ_HANDLED; 5687 } 5688 5689 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5690 { 5691 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5692 int chan = tx_q->queue_index; 5693 struct stmmac_priv *priv; 5694 int status; 5695 5696 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); 5697 5698 if (unlikely(!data)) { 5699 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5700 return IRQ_NONE; 5701 } 5702 5703 /* Check if adapter is up */ 5704 if (test_bit(STMMAC_DOWN, &priv->state)) 5705 return IRQ_HANDLED; 5706 5707 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5708 5709 if (unlikely(status & tx_hard_error_bump_tc)) { 5710 /* Try to bump up the dma threshold on this failure */ 5711 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 5712 tc <= 256) { 5713 tc += 64; 5714 if (priv->plat->force_thresh_dma_mode) 5715 stmmac_set_dma_operation_mode(priv, 5716 tc, 5717 tc, 5718 chan); 5719 else 5720 stmmac_set_dma_operation_mode(priv, 5721 tc, 5722 SF_DMA_MODE, 5723 chan); 5724 priv->xstats.threshold = tc; 5725 } 5726 } else if (unlikely(status == tx_hard_error)) { 5727 stmmac_tx_err(priv, chan); 5728 } 5729 5730 return IRQ_HANDLED; 5731 } 5732 5733 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5734 { 5735 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5736 int chan = rx_q->queue_index; 5737 struct stmmac_priv *priv; 5738 5739 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); 5740 5741 if (unlikely(!data)) { 5742 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5743 return IRQ_NONE; 5744 } 5745 5746 /* Check if adapter is up */ 5747 if (test_bit(STMMAC_DOWN, &priv->state)) 5748 return IRQ_HANDLED; 5749 5750 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5751 5752 return IRQ_HANDLED; 5753 } 5754 5755 #ifdef CONFIG_NET_POLL_CONTROLLER 5756 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5757 * to allow network I/O with interrupts disabled. 5758 */ 5759 static void stmmac_poll_controller(struct net_device *dev) 5760 { 5761 struct stmmac_priv *priv = netdev_priv(dev); 5762 int i; 5763 5764 /* If adapter is down, do nothing */ 5765 if (test_bit(STMMAC_DOWN, &priv->state)) 5766 return; 5767 5768 if (priv->plat->multi_msi_en) { 5769 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5770 stmmac_msi_intr_rx(0, &priv->rx_queue[i]); 5771 5772 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5773 stmmac_msi_intr_tx(0, &priv->tx_queue[i]); 5774 } else { 5775 disable_irq(dev->irq); 5776 stmmac_interrupt(dev->irq, dev); 5777 enable_irq(dev->irq); 5778 } 5779 } 5780 #endif 5781 5782 /** 5783 * stmmac_ioctl - Entry point for the Ioctl 5784 * @dev: Device pointer. 5785 * @rq: An IOCTL specefic structure, that can contain a pointer to 5786 * a proprietary structure used to pass information to the driver. 5787 * @cmd: IOCTL command 5788 * Description: 5789 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5790 */ 5791 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5792 { 5793 struct stmmac_priv *priv = netdev_priv (dev); 5794 int ret = -EOPNOTSUPP; 5795 5796 if (!netif_running(dev)) 5797 return -EINVAL; 5798 5799 switch (cmd) { 5800 case SIOCGMIIPHY: 5801 case SIOCGMIIREG: 5802 case SIOCSMIIREG: 5803 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5804 break; 5805 case SIOCSHWTSTAMP: 5806 ret = stmmac_hwtstamp_set(dev, rq); 5807 break; 5808 case SIOCGHWTSTAMP: 5809 ret = stmmac_hwtstamp_get(dev, rq); 5810 break; 5811 default: 5812 break; 5813 } 5814 5815 return ret; 5816 } 5817 5818 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5819 void *cb_priv) 5820 { 5821 struct stmmac_priv *priv = cb_priv; 5822 int ret = -EOPNOTSUPP; 5823 5824 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5825 return ret; 5826 5827 __stmmac_disable_all_queues(priv); 5828 5829 switch (type) { 5830 case TC_SETUP_CLSU32: 5831 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5832 break; 5833 case TC_SETUP_CLSFLOWER: 5834 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5835 break; 5836 default: 5837 break; 5838 } 5839 5840 stmmac_enable_all_queues(priv); 5841 return ret; 5842 } 5843 5844 static LIST_HEAD(stmmac_block_cb_list); 5845 5846 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5847 void *type_data) 5848 { 5849 struct stmmac_priv *priv = netdev_priv(ndev); 5850 5851 switch (type) { 5852 case TC_SETUP_BLOCK: 5853 return flow_block_cb_setup_simple(type_data, 5854 &stmmac_block_cb_list, 5855 stmmac_setup_tc_block_cb, 5856 priv, priv, true); 5857 case TC_SETUP_QDISC_CBS: 5858 return stmmac_tc_setup_cbs(priv, priv, type_data); 5859 case TC_SETUP_QDISC_TAPRIO: 5860 return stmmac_tc_setup_taprio(priv, priv, type_data); 5861 case TC_SETUP_QDISC_ETF: 5862 return stmmac_tc_setup_etf(priv, priv, type_data); 5863 default: 5864 return -EOPNOTSUPP; 5865 } 5866 } 5867 5868 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5869 struct net_device *sb_dev) 5870 { 5871 int gso = skb_shinfo(skb)->gso_type; 5872 5873 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5874 /* 5875 * There is no way to determine the number of TSO/USO 5876 * capable Queues. Let's use always the Queue 0 5877 * because if TSO/USO is supported then at least this 5878 * one will be capable. 5879 */ 5880 return 0; 5881 } 5882 5883 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5884 } 5885 5886 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 5887 { 5888 struct stmmac_priv *priv = netdev_priv(ndev); 5889 int ret = 0; 5890 5891 ret = eth_mac_addr(ndev, addr); 5892 if (ret) 5893 return ret; 5894 5895 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 5896 5897 return ret; 5898 } 5899 5900 #ifdef CONFIG_DEBUG_FS 5901 static struct dentry *stmmac_fs_dir; 5902 5903 static void sysfs_display_ring(void *head, int size, int extend_desc, 5904 struct seq_file *seq, dma_addr_t dma_phy_addr) 5905 { 5906 int i; 5907 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 5908 struct dma_desc *p = (struct dma_desc *)head; 5909 dma_addr_t dma_addr; 5910 5911 for (i = 0; i < size; i++) { 5912 if (extend_desc) { 5913 dma_addr = dma_phy_addr + i * sizeof(*ep); 5914 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5915 i, &dma_addr, 5916 le32_to_cpu(ep->basic.des0), 5917 le32_to_cpu(ep->basic.des1), 5918 le32_to_cpu(ep->basic.des2), 5919 le32_to_cpu(ep->basic.des3)); 5920 ep++; 5921 } else { 5922 dma_addr = dma_phy_addr + i * sizeof(*p); 5923 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5924 i, &dma_addr, 5925 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 5926 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 5927 p++; 5928 } 5929 seq_printf(seq, "\n"); 5930 } 5931 } 5932 5933 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 5934 { 5935 struct net_device *dev = seq->private; 5936 struct stmmac_priv *priv = netdev_priv(dev); 5937 u32 rx_count = priv->plat->rx_queues_to_use; 5938 u32 tx_count = priv->plat->tx_queues_to_use; 5939 u32 queue; 5940 5941 if ((dev->flags & IFF_UP) == 0) 5942 return 0; 5943 5944 for (queue = 0; queue < rx_count; queue++) { 5945 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5946 5947 seq_printf(seq, "RX Queue %d:\n", queue); 5948 5949 if (priv->extend_desc) { 5950 seq_printf(seq, "Extended descriptor ring:\n"); 5951 sysfs_display_ring((void *)rx_q->dma_erx, 5952 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 5953 } else { 5954 seq_printf(seq, "Descriptor ring:\n"); 5955 sysfs_display_ring((void *)rx_q->dma_rx, 5956 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 5957 } 5958 } 5959 5960 for (queue = 0; queue < tx_count; queue++) { 5961 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5962 5963 seq_printf(seq, "TX Queue %d:\n", queue); 5964 5965 if (priv->extend_desc) { 5966 seq_printf(seq, "Extended descriptor ring:\n"); 5967 sysfs_display_ring((void *)tx_q->dma_etx, 5968 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 5969 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 5970 seq_printf(seq, "Descriptor ring:\n"); 5971 sysfs_display_ring((void *)tx_q->dma_tx, 5972 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 5973 } 5974 } 5975 5976 return 0; 5977 } 5978 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 5979 5980 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 5981 { 5982 struct net_device *dev = seq->private; 5983 struct stmmac_priv *priv = netdev_priv(dev); 5984 5985 if (!priv->hw_cap_support) { 5986 seq_printf(seq, "DMA HW features not supported\n"); 5987 return 0; 5988 } 5989 5990 seq_printf(seq, "==============================\n"); 5991 seq_printf(seq, "\tDMA HW features\n"); 5992 seq_printf(seq, "==============================\n"); 5993 5994 seq_printf(seq, "\t10/100 Mbps: %s\n", 5995 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 5996 seq_printf(seq, "\t1000 Mbps: %s\n", 5997 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 5998 seq_printf(seq, "\tHalf duplex: %s\n", 5999 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6000 seq_printf(seq, "\tHash Filter: %s\n", 6001 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6002 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6003 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6004 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6005 (priv->dma_cap.pcs) ? "Y" : "N"); 6006 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6007 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6008 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6009 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6010 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6011 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6012 seq_printf(seq, "\tRMON module: %s\n", 6013 (priv->dma_cap.rmon) ? "Y" : "N"); 6014 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6015 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6016 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6017 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6018 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6019 (priv->dma_cap.eee) ? "Y" : "N"); 6020 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6021 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6022 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6023 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6024 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6025 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6026 } else { 6027 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6028 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6029 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6030 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6031 } 6032 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6033 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6034 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6035 priv->dma_cap.number_rx_channel); 6036 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6037 priv->dma_cap.number_tx_channel); 6038 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6039 priv->dma_cap.number_rx_queues); 6040 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6041 priv->dma_cap.number_tx_queues); 6042 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6043 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6044 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6045 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6046 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6047 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6048 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6049 priv->dma_cap.pps_out_num); 6050 seq_printf(seq, "\tSafety Features: %s\n", 6051 priv->dma_cap.asp ? "Y" : "N"); 6052 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6053 priv->dma_cap.frpsel ? "Y" : "N"); 6054 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6055 priv->dma_cap.addr64); 6056 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6057 priv->dma_cap.rssen ? "Y" : "N"); 6058 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6059 priv->dma_cap.vlhash ? "Y" : "N"); 6060 seq_printf(seq, "\tSplit Header: %s\n", 6061 priv->dma_cap.sphen ? "Y" : "N"); 6062 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6063 priv->dma_cap.vlins ? "Y" : "N"); 6064 seq_printf(seq, "\tDouble VLAN: %s\n", 6065 priv->dma_cap.dvlan ? "Y" : "N"); 6066 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6067 priv->dma_cap.l3l4fnum); 6068 seq_printf(seq, "\tARP Offloading: %s\n", 6069 priv->dma_cap.arpoffsel ? "Y" : "N"); 6070 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6071 priv->dma_cap.estsel ? "Y" : "N"); 6072 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6073 priv->dma_cap.fpesel ? "Y" : "N"); 6074 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6075 priv->dma_cap.tbssel ? "Y" : "N"); 6076 return 0; 6077 } 6078 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6079 6080 /* Use network device events to rename debugfs file entries. 6081 */ 6082 static int stmmac_device_event(struct notifier_block *unused, 6083 unsigned long event, void *ptr) 6084 { 6085 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6086 struct stmmac_priv *priv = netdev_priv(dev); 6087 6088 if (dev->netdev_ops != &stmmac_netdev_ops) 6089 goto done; 6090 6091 switch (event) { 6092 case NETDEV_CHANGENAME: 6093 if (priv->dbgfs_dir) 6094 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6095 priv->dbgfs_dir, 6096 stmmac_fs_dir, 6097 dev->name); 6098 break; 6099 } 6100 done: 6101 return NOTIFY_DONE; 6102 } 6103 6104 static struct notifier_block stmmac_notifier = { 6105 .notifier_call = stmmac_device_event, 6106 }; 6107 6108 static void stmmac_init_fs(struct net_device *dev) 6109 { 6110 struct stmmac_priv *priv = netdev_priv(dev); 6111 6112 rtnl_lock(); 6113 6114 /* Create per netdev entries */ 6115 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6116 6117 /* Entry to report DMA RX/TX rings */ 6118 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6119 &stmmac_rings_status_fops); 6120 6121 /* Entry to report the DMA HW features */ 6122 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6123 &stmmac_dma_cap_fops); 6124 6125 rtnl_unlock(); 6126 } 6127 6128 static void stmmac_exit_fs(struct net_device *dev) 6129 { 6130 struct stmmac_priv *priv = netdev_priv(dev); 6131 6132 debugfs_remove_recursive(priv->dbgfs_dir); 6133 } 6134 #endif /* CONFIG_DEBUG_FS */ 6135 6136 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6137 { 6138 unsigned char *data = (unsigned char *)&vid_le; 6139 unsigned char data_byte = 0; 6140 u32 crc = ~0x0; 6141 u32 temp = 0; 6142 int i, bits; 6143 6144 bits = get_bitmask_order(VLAN_VID_MASK); 6145 for (i = 0; i < bits; i++) { 6146 if ((i % 8) == 0) 6147 data_byte = data[i / 8]; 6148 6149 temp = ((crc & 1) ^ data_byte) & 1; 6150 crc >>= 1; 6151 data_byte >>= 1; 6152 6153 if (temp) 6154 crc ^= 0xedb88320; 6155 } 6156 6157 return crc; 6158 } 6159 6160 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6161 { 6162 u32 crc, hash = 0; 6163 __le16 pmatch = 0; 6164 int count = 0; 6165 u16 vid = 0; 6166 6167 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6168 __le16 vid_le = cpu_to_le16(vid); 6169 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6170 hash |= (1 << crc); 6171 count++; 6172 } 6173 6174 if (!priv->dma_cap.vlhash) { 6175 if (count > 2) /* VID = 0 always passes filter */ 6176 return -EOPNOTSUPP; 6177 6178 pmatch = cpu_to_le16(vid); 6179 hash = 0; 6180 } 6181 6182 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6183 } 6184 6185 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6186 { 6187 struct stmmac_priv *priv = netdev_priv(ndev); 6188 bool is_double = false; 6189 int ret; 6190 6191 ret = pm_runtime_get_sync(priv->device); 6192 if (ret < 0) { 6193 pm_runtime_put_noidle(priv->device); 6194 return ret; 6195 } 6196 6197 if (be16_to_cpu(proto) == ETH_P_8021AD) 6198 is_double = true; 6199 6200 set_bit(vid, priv->active_vlans); 6201 ret = stmmac_vlan_update(priv, is_double); 6202 if (ret) { 6203 clear_bit(vid, priv->active_vlans); 6204 return ret; 6205 } 6206 6207 if (priv->hw->num_vlan) { 6208 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6209 if (ret) 6210 return ret; 6211 } 6212 6213 return 0; 6214 } 6215 6216 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6217 { 6218 struct stmmac_priv *priv = netdev_priv(ndev); 6219 bool is_double = false; 6220 int ret; 6221 6222 if (be16_to_cpu(proto) == ETH_P_8021AD) 6223 is_double = true; 6224 6225 clear_bit(vid, priv->active_vlans); 6226 6227 if (priv->hw->num_vlan) { 6228 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6229 if (ret) 6230 goto del_vlan_error; 6231 } 6232 6233 ret = stmmac_vlan_update(priv, is_double); 6234 6235 del_vlan_error: 6236 pm_runtime_put(priv->device); 6237 6238 return ret; 6239 } 6240 6241 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6242 { 6243 struct stmmac_priv *priv = netdev_priv(dev); 6244 6245 switch (bpf->command) { 6246 case XDP_SETUP_PROG: 6247 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6248 case XDP_SETUP_XSK_POOL: 6249 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6250 bpf->xsk.queue_id); 6251 default: 6252 return -EOPNOTSUPP; 6253 } 6254 } 6255 6256 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6257 struct xdp_frame **frames, u32 flags) 6258 { 6259 struct stmmac_priv *priv = netdev_priv(dev); 6260 int cpu = smp_processor_id(); 6261 struct netdev_queue *nq; 6262 int i, nxmit = 0; 6263 int queue; 6264 6265 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6266 return -ENETDOWN; 6267 6268 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6269 return -EINVAL; 6270 6271 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6272 nq = netdev_get_tx_queue(priv->dev, queue); 6273 6274 __netif_tx_lock(nq, cpu); 6275 /* Avoids TX time-out as we are sharing with slow path */ 6276 nq->trans_start = jiffies; 6277 6278 for (i = 0; i < num_frames; i++) { 6279 int res; 6280 6281 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6282 if (res == STMMAC_XDP_CONSUMED) 6283 break; 6284 6285 nxmit++; 6286 } 6287 6288 if (flags & XDP_XMIT_FLUSH) { 6289 stmmac_flush_tx_descriptors(priv, queue); 6290 stmmac_tx_timer_arm(priv, queue); 6291 } 6292 6293 __netif_tx_unlock(nq); 6294 6295 return nxmit; 6296 } 6297 6298 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6299 { 6300 struct stmmac_channel *ch = &priv->channel[queue]; 6301 unsigned long flags; 6302 6303 spin_lock_irqsave(&ch->lock, flags); 6304 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6305 spin_unlock_irqrestore(&ch->lock, flags); 6306 6307 stmmac_stop_rx_dma(priv, queue); 6308 __free_dma_rx_desc_resources(priv, queue); 6309 } 6310 6311 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6312 { 6313 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 6314 struct stmmac_channel *ch = &priv->channel[queue]; 6315 unsigned long flags; 6316 u32 buf_size; 6317 int ret; 6318 6319 ret = __alloc_dma_rx_desc_resources(priv, queue); 6320 if (ret) { 6321 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6322 return; 6323 } 6324 6325 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); 6326 if (ret) { 6327 __free_dma_rx_desc_resources(priv, queue); 6328 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6329 return; 6330 } 6331 6332 stmmac_clear_rx_descriptors(priv, queue); 6333 6334 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6335 rx_q->dma_rx_phy, rx_q->queue_index); 6336 6337 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6338 sizeof(struct dma_desc)); 6339 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6340 rx_q->rx_tail_addr, rx_q->queue_index); 6341 6342 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6343 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6344 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6345 buf_size, 6346 rx_q->queue_index); 6347 } else { 6348 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6349 priv->dma_buf_sz, 6350 rx_q->queue_index); 6351 } 6352 6353 stmmac_start_rx_dma(priv, queue); 6354 6355 spin_lock_irqsave(&ch->lock, flags); 6356 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6357 spin_unlock_irqrestore(&ch->lock, flags); 6358 } 6359 6360 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6361 { 6362 struct stmmac_channel *ch = &priv->channel[queue]; 6363 unsigned long flags; 6364 6365 spin_lock_irqsave(&ch->lock, flags); 6366 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6367 spin_unlock_irqrestore(&ch->lock, flags); 6368 6369 stmmac_stop_tx_dma(priv, queue); 6370 __free_dma_tx_desc_resources(priv, queue); 6371 } 6372 6373 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6374 { 6375 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 6376 struct stmmac_channel *ch = &priv->channel[queue]; 6377 unsigned long flags; 6378 int ret; 6379 6380 ret = __alloc_dma_tx_desc_resources(priv, queue); 6381 if (ret) { 6382 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6383 return; 6384 } 6385 6386 ret = __init_dma_tx_desc_rings(priv, queue); 6387 if (ret) { 6388 __free_dma_tx_desc_resources(priv, queue); 6389 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6390 return; 6391 } 6392 6393 stmmac_clear_tx_descriptors(priv, queue); 6394 6395 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6396 tx_q->dma_tx_phy, tx_q->queue_index); 6397 6398 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6399 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6400 6401 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6402 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6403 tx_q->tx_tail_addr, tx_q->queue_index); 6404 6405 stmmac_start_tx_dma(priv, queue); 6406 6407 spin_lock_irqsave(&ch->lock, flags); 6408 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6409 spin_unlock_irqrestore(&ch->lock, flags); 6410 } 6411 6412 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6413 { 6414 struct stmmac_priv *priv = netdev_priv(dev); 6415 struct stmmac_rx_queue *rx_q; 6416 struct stmmac_tx_queue *tx_q; 6417 struct stmmac_channel *ch; 6418 6419 if (test_bit(STMMAC_DOWN, &priv->state) || 6420 !netif_carrier_ok(priv->dev)) 6421 return -ENETDOWN; 6422 6423 if (!stmmac_xdp_is_enabled(priv)) 6424 return -ENXIO; 6425 6426 if (queue >= priv->plat->rx_queues_to_use || 6427 queue >= priv->plat->tx_queues_to_use) 6428 return -EINVAL; 6429 6430 rx_q = &priv->rx_queue[queue]; 6431 tx_q = &priv->tx_queue[queue]; 6432 ch = &priv->channel[queue]; 6433 6434 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6435 return -ENXIO; 6436 6437 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6438 /* EQoS does not have per-DMA channel SW interrupt, 6439 * so we schedule RX Napi straight-away. 6440 */ 6441 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6442 __napi_schedule(&ch->rxtx_napi); 6443 } 6444 6445 return 0; 6446 } 6447 6448 static const struct net_device_ops stmmac_netdev_ops = { 6449 .ndo_open = stmmac_open, 6450 .ndo_start_xmit = stmmac_xmit, 6451 .ndo_stop = stmmac_release, 6452 .ndo_change_mtu = stmmac_change_mtu, 6453 .ndo_fix_features = stmmac_fix_features, 6454 .ndo_set_features = stmmac_set_features, 6455 .ndo_set_rx_mode = stmmac_set_rx_mode, 6456 .ndo_tx_timeout = stmmac_tx_timeout, 6457 .ndo_do_ioctl = stmmac_ioctl, 6458 .ndo_setup_tc = stmmac_setup_tc, 6459 .ndo_select_queue = stmmac_select_queue, 6460 #ifdef CONFIG_NET_POLL_CONTROLLER 6461 .ndo_poll_controller = stmmac_poll_controller, 6462 #endif 6463 .ndo_set_mac_address = stmmac_set_mac_address, 6464 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6465 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6466 .ndo_bpf = stmmac_bpf, 6467 .ndo_xdp_xmit = stmmac_xdp_xmit, 6468 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6469 }; 6470 6471 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6472 { 6473 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6474 return; 6475 if (test_bit(STMMAC_DOWN, &priv->state)) 6476 return; 6477 6478 netdev_err(priv->dev, "Reset adapter.\n"); 6479 6480 rtnl_lock(); 6481 netif_trans_update(priv->dev); 6482 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6483 usleep_range(1000, 2000); 6484 6485 set_bit(STMMAC_DOWN, &priv->state); 6486 dev_close(priv->dev); 6487 dev_open(priv->dev, NULL); 6488 clear_bit(STMMAC_DOWN, &priv->state); 6489 clear_bit(STMMAC_RESETING, &priv->state); 6490 rtnl_unlock(); 6491 } 6492 6493 static void stmmac_service_task(struct work_struct *work) 6494 { 6495 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6496 service_task); 6497 6498 stmmac_reset_subtask(priv); 6499 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6500 } 6501 6502 /** 6503 * stmmac_hw_init - Init the MAC device 6504 * @priv: driver private structure 6505 * Description: this function is to configure the MAC device according to 6506 * some platform parameters or the HW capability register. It prepares the 6507 * driver to use either ring or chain modes and to setup either enhanced or 6508 * normal descriptors. 6509 */ 6510 static int stmmac_hw_init(struct stmmac_priv *priv) 6511 { 6512 int ret; 6513 6514 /* dwmac-sun8i only work in chain mode */ 6515 if (priv->plat->has_sun8i) 6516 chain_mode = 1; 6517 priv->chain_mode = chain_mode; 6518 6519 /* Initialize HW Interface */ 6520 ret = stmmac_hwif_init(priv); 6521 if (ret) 6522 return ret; 6523 6524 /* Get the HW capability (new GMAC newer than 3.50a) */ 6525 priv->hw_cap_support = stmmac_get_hw_features(priv); 6526 if (priv->hw_cap_support) { 6527 dev_info(priv->device, "DMA HW capability register supported\n"); 6528 6529 /* We can override some gmac/dma configuration fields: e.g. 6530 * enh_desc, tx_coe (e.g. that are passed through the 6531 * platform) with the values from the HW capability 6532 * register (if supported). 6533 */ 6534 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6535 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 6536 priv->hw->pmt = priv->plat->pmt; 6537 if (priv->dma_cap.hash_tb_sz) { 6538 priv->hw->multicast_filter_bins = 6539 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6540 priv->hw->mcast_bits_log2 = 6541 ilog2(priv->hw->multicast_filter_bins); 6542 } 6543 6544 /* TXCOE doesn't work in thresh DMA mode */ 6545 if (priv->plat->force_thresh_dma_mode) 6546 priv->plat->tx_coe = 0; 6547 else 6548 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6549 6550 /* In case of GMAC4 rx_coe is from HW cap register. */ 6551 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6552 6553 if (priv->dma_cap.rx_coe_type2) 6554 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6555 else if (priv->dma_cap.rx_coe_type1) 6556 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6557 6558 } else { 6559 dev_info(priv->device, "No HW DMA feature register supported\n"); 6560 } 6561 6562 if (priv->plat->rx_coe) { 6563 priv->hw->rx_csum = priv->plat->rx_coe; 6564 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6565 if (priv->synopsys_id < DWMAC_CORE_4_00) 6566 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6567 } 6568 if (priv->plat->tx_coe) 6569 dev_info(priv->device, "TX Checksum insertion supported\n"); 6570 6571 if (priv->plat->pmt) { 6572 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6573 device_set_wakeup_capable(priv->device, 1); 6574 } 6575 6576 if (priv->dma_cap.tsoen) 6577 dev_info(priv->device, "TSO supported\n"); 6578 6579 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6580 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6581 6582 /* Run HW quirks, if any */ 6583 if (priv->hwif_quirks) { 6584 ret = priv->hwif_quirks(priv); 6585 if (ret) 6586 return ret; 6587 } 6588 6589 /* Rx Watchdog is available in the COREs newer than the 3.40. 6590 * In some case, for example on bugged HW this feature 6591 * has to be disable and this can be done by passing the 6592 * riwt_off field from the platform. 6593 */ 6594 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6595 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6596 priv->use_riwt = 1; 6597 dev_info(priv->device, 6598 "Enable RX Mitigation via HW Watchdog Timer\n"); 6599 } 6600 6601 return 0; 6602 } 6603 6604 static void stmmac_napi_add(struct net_device *dev) 6605 { 6606 struct stmmac_priv *priv = netdev_priv(dev); 6607 u32 queue, maxq; 6608 6609 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6610 6611 for (queue = 0; queue < maxq; queue++) { 6612 struct stmmac_channel *ch = &priv->channel[queue]; 6613 6614 ch->priv_data = priv; 6615 ch->index = queue; 6616 spin_lock_init(&ch->lock); 6617 6618 if (queue < priv->plat->rx_queues_to_use) { 6619 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6620 NAPI_POLL_WEIGHT); 6621 } 6622 if (queue < priv->plat->tx_queues_to_use) { 6623 netif_tx_napi_add(dev, &ch->tx_napi, 6624 stmmac_napi_poll_tx, 6625 NAPI_POLL_WEIGHT); 6626 } 6627 if (queue < priv->plat->rx_queues_to_use && 6628 queue < priv->plat->tx_queues_to_use) { 6629 netif_napi_add(dev, &ch->rxtx_napi, 6630 stmmac_napi_poll_rxtx, 6631 NAPI_POLL_WEIGHT); 6632 } 6633 } 6634 } 6635 6636 static void stmmac_napi_del(struct net_device *dev) 6637 { 6638 struct stmmac_priv *priv = netdev_priv(dev); 6639 u32 queue, maxq; 6640 6641 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6642 6643 for (queue = 0; queue < maxq; queue++) { 6644 struct stmmac_channel *ch = &priv->channel[queue]; 6645 6646 if (queue < priv->plat->rx_queues_to_use) 6647 netif_napi_del(&ch->rx_napi); 6648 if (queue < priv->plat->tx_queues_to_use) 6649 netif_napi_del(&ch->tx_napi); 6650 if (queue < priv->plat->rx_queues_to_use && 6651 queue < priv->plat->tx_queues_to_use) { 6652 netif_napi_del(&ch->rxtx_napi); 6653 } 6654 } 6655 } 6656 6657 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6658 { 6659 struct stmmac_priv *priv = netdev_priv(dev); 6660 int ret = 0; 6661 6662 if (netif_running(dev)) 6663 stmmac_release(dev); 6664 6665 stmmac_napi_del(dev); 6666 6667 priv->plat->rx_queues_to_use = rx_cnt; 6668 priv->plat->tx_queues_to_use = tx_cnt; 6669 6670 stmmac_napi_add(dev); 6671 6672 if (netif_running(dev)) 6673 ret = stmmac_open(dev); 6674 6675 return ret; 6676 } 6677 6678 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6679 { 6680 struct stmmac_priv *priv = netdev_priv(dev); 6681 int ret = 0; 6682 6683 if (netif_running(dev)) 6684 stmmac_release(dev); 6685 6686 priv->dma_rx_size = rx_size; 6687 priv->dma_tx_size = tx_size; 6688 6689 if (netif_running(dev)) 6690 ret = stmmac_open(dev); 6691 6692 return ret; 6693 } 6694 6695 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6696 static void stmmac_fpe_lp_task(struct work_struct *work) 6697 { 6698 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6699 fpe_task); 6700 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6701 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6702 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6703 bool *hs_enable = &fpe_cfg->hs_enable; 6704 bool *enable = &fpe_cfg->enable; 6705 int retries = 20; 6706 6707 while (retries-- > 0) { 6708 /* Bail out immediately if FPE handshake is OFF */ 6709 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6710 break; 6711 6712 if (*lo_state == FPE_STATE_ENTERING_ON && 6713 *lp_state == FPE_STATE_ENTERING_ON) { 6714 stmmac_fpe_configure(priv, priv->ioaddr, 6715 priv->plat->tx_queues_to_use, 6716 priv->plat->rx_queues_to_use, 6717 *enable); 6718 6719 netdev_info(priv->dev, "configured FPE\n"); 6720 6721 *lo_state = FPE_STATE_ON; 6722 *lp_state = FPE_STATE_ON; 6723 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6724 break; 6725 } 6726 6727 if ((*lo_state == FPE_STATE_CAPABLE || 6728 *lo_state == FPE_STATE_ENTERING_ON) && 6729 *lp_state != FPE_STATE_ON) { 6730 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6731 *lo_state, *lp_state); 6732 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6733 MPACKET_VERIFY); 6734 } 6735 /* Sleep then retry */ 6736 msleep(500); 6737 } 6738 6739 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6740 } 6741 6742 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 6743 { 6744 if (priv->plat->fpe_cfg->hs_enable != enable) { 6745 if (enable) { 6746 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6747 MPACKET_VERIFY); 6748 } else { 6749 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 6750 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 6751 } 6752 6753 priv->plat->fpe_cfg->hs_enable = enable; 6754 } 6755 } 6756 6757 /** 6758 * stmmac_dvr_probe 6759 * @device: device pointer 6760 * @plat_dat: platform data pointer 6761 * @res: stmmac resource pointer 6762 * Description: this is the main probe function used to 6763 * call the alloc_etherdev, allocate the priv structure. 6764 * Return: 6765 * returns 0 on success, otherwise errno. 6766 */ 6767 int stmmac_dvr_probe(struct device *device, 6768 struct plat_stmmacenet_data *plat_dat, 6769 struct stmmac_resources *res) 6770 { 6771 struct net_device *ndev = NULL; 6772 struct stmmac_priv *priv; 6773 u32 rxq; 6774 int i, ret = 0; 6775 6776 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 6777 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 6778 if (!ndev) 6779 return -ENOMEM; 6780 6781 SET_NETDEV_DEV(ndev, device); 6782 6783 priv = netdev_priv(ndev); 6784 priv->device = device; 6785 priv->dev = ndev; 6786 6787 stmmac_set_ethtool_ops(ndev); 6788 priv->pause = pause; 6789 priv->plat = plat_dat; 6790 priv->ioaddr = res->addr; 6791 priv->dev->base_addr = (unsigned long)res->addr; 6792 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 6793 6794 priv->dev->irq = res->irq; 6795 priv->wol_irq = res->wol_irq; 6796 priv->lpi_irq = res->lpi_irq; 6797 priv->sfty_ce_irq = res->sfty_ce_irq; 6798 priv->sfty_ue_irq = res->sfty_ue_irq; 6799 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 6800 priv->rx_irq[i] = res->rx_irq[i]; 6801 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 6802 priv->tx_irq[i] = res->tx_irq[i]; 6803 6804 if (!is_zero_ether_addr(res->mac)) 6805 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 6806 6807 dev_set_drvdata(device, priv->dev); 6808 6809 /* Verify driver arguments */ 6810 stmmac_verify_args(); 6811 6812 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 6813 if (!priv->af_xdp_zc_qps) 6814 return -ENOMEM; 6815 6816 /* Allocate workqueue */ 6817 priv->wq = create_singlethread_workqueue("stmmac_wq"); 6818 if (!priv->wq) { 6819 dev_err(priv->device, "failed to create workqueue\n"); 6820 return -ENOMEM; 6821 } 6822 6823 INIT_WORK(&priv->service_task, stmmac_service_task); 6824 6825 /* Initialize Link Partner FPE workqueue */ 6826 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 6827 6828 /* Override with kernel parameters if supplied XXX CRS XXX 6829 * this needs to have multiple instances 6830 */ 6831 if ((phyaddr >= 0) && (phyaddr <= 31)) 6832 priv->plat->phy_addr = phyaddr; 6833 6834 if (priv->plat->stmmac_rst) { 6835 ret = reset_control_assert(priv->plat->stmmac_rst); 6836 reset_control_deassert(priv->plat->stmmac_rst); 6837 /* Some reset controllers have only reset callback instead of 6838 * assert + deassert callbacks pair. 6839 */ 6840 if (ret == -ENOTSUPP) 6841 reset_control_reset(priv->plat->stmmac_rst); 6842 } 6843 6844 /* Init MAC and get the capabilities */ 6845 ret = stmmac_hw_init(priv); 6846 if (ret) 6847 goto error_hw_init; 6848 6849 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 6850 */ 6851 if (priv->synopsys_id < DWMAC_CORE_5_20) 6852 priv->plat->dma_cfg->dche = false; 6853 6854 stmmac_check_ether_addr(priv); 6855 6856 ndev->netdev_ops = &stmmac_netdev_ops; 6857 6858 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6859 NETIF_F_RXCSUM; 6860 6861 ret = stmmac_tc_init(priv, priv); 6862 if (!ret) { 6863 ndev->hw_features |= NETIF_F_HW_TC; 6864 } 6865 6866 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 6867 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 6868 if (priv->plat->has_gmac4) 6869 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 6870 priv->tso = true; 6871 dev_info(priv->device, "TSO feature enabled\n"); 6872 } 6873 6874 if (priv->dma_cap.sphen) { 6875 ndev->hw_features |= NETIF_F_GRO; 6876 priv->sph_cap = true; 6877 priv->sph = priv->sph_cap; 6878 dev_info(priv->device, "SPH feature enabled\n"); 6879 } 6880 6881 /* The current IP register MAC_HW_Feature1[ADDR64] only define 6882 * 32/40/64 bit width, but some SOC support others like i.MX8MP 6883 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 6884 * So overwrite dma_cap.addr64 according to HW real design. 6885 */ 6886 if (priv->plat->addr64) 6887 priv->dma_cap.addr64 = priv->plat->addr64; 6888 6889 if (priv->dma_cap.addr64) { 6890 ret = dma_set_mask_and_coherent(device, 6891 DMA_BIT_MASK(priv->dma_cap.addr64)); 6892 if (!ret) { 6893 dev_info(priv->device, "Using %d bits DMA width\n", 6894 priv->dma_cap.addr64); 6895 6896 /* 6897 * If more than 32 bits can be addressed, make sure to 6898 * enable enhanced addressing mode. 6899 */ 6900 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 6901 priv->plat->dma_cfg->eame = true; 6902 } else { 6903 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 6904 if (ret) { 6905 dev_err(priv->device, "Failed to set DMA Mask\n"); 6906 goto error_hw_init; 6907 } 6908 6909 priv->dma_cap.addr64 = 32; 6910 } 6911 } 6912 6913 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 6914 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 6915 #ifdef STMMAC_VLAN_TAG_USED 6916 /* Both mac100 and gmac support receive VLAN tag detection */ 6917 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 6918 if (priv->dma_cap.vlhash) { 6919 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6920 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 6921 } 6922 if (priv->dma_cap.vlins) { 6923 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 6924 if (priv->dma_cap.dvlan) 6925 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 6926 } 6927 #endif 6928 priv->msg_enable = netif_msg_init(debug, default_msg_level); 6929 6930 /* Initialize RSS */ 6931 rxq = priv->plat->rx_queues_to_use; 6932 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 6933 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 6934 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 6935 6936 if (priv->dma_cap.rssen && priv->plat->rss_en) 6937 ndev->features |= NETIF_F_RXHASH; 6938 6939 /* MTU range: 46 - hw-specific max */ 6940 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 6941 if (priv->plat->has_xgmac) 6942 ndev->max_mtu = XGMAC_JUMBO_LEN; 6943 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 6944 ndev->max_mtu = JUMBO_LEN; 6945 else 6946 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 6947 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 6948 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 6949 */ 6950 if ((priv->plat->maxmtu < ndev->max_mtu) && 6951 (priv->plat->maxmtu >= ndev->min_mtu)) 6952 ndev->max_mtu = priv->plat->maxmtu; 6953 else if (priv->plat->maxmtu < ndev->min_mtu) 6954 dev_warn(priv->device, 6955 "%s: warning: maxmtu having invalid value (%d)\n", 6956 __func__, priv->plat->maxmtu); 6957 6958 if (flow_ctrl) 6959 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 6960 6961 /* Setup channels NAPI */ 6962 stmmac_napi_add(ndev); 6963 6964 mutex_init(&priv->lock); 6965 6966 /* If a specific clk_csr value is passed from the platform 6967 * this means that the CSR Clock Range selection cannot be 6968 * changed at run-time and it is fixed. Viceversa the driver'll try to 6969 * set the MDC clock dynamically according to the csr actual 6970 * clock input. 6971 */ 6972 if (priv->plat->clk_csr >= 0) 6973 priv->clk_csr = priv->plat->clk_csr; 6974 else 6975 stmmac_clk_csr_set(priv); 6976 6977 stmmac_check_pcs_mode(priv); 6978 6979 pm_runtime_get_noresume(device); 6980 pm_runtime_set_active(device); 6981 pm_runtime_enable(device); 6982 6983 if (priv->hw->pcs != STMMAC_PCS_TBI && 6984 priv->hw->pcs != STMMAC_PCS_RTBI) { 6985 /* MDIO bus Registration */ 6986 ret = stmmac_mdio_register(ndev); 6987 if (ret < 0) { 6988 dev_err(priv->device, 6989 "%s: MDIO bus (id: %d) registration failed", 6990 __func__, priv->plat->bus_id); 6991 goto error_mdio_register; 6992 } 6993 } 6994 6995 ret = stmmac_phy_setup(priv); 6996 if (ret) { 6997 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 6998 goto error_phy_setup; 6999 } 7000 7001 ret = register_netdev(ndev); 7002 if (ret) { 7003 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7004 __func__, ret); 7005 goto error_netdev_register; 7006 } 7007 7008 if (priv->plat->serdes_powerup) { 7009 ret = priv->plat->serdes_powerup(ndev, 7010 priv->plat->bsp_priv); 7011 7012 if (ret < 0) 7013 goto error_serdes_powerup; 7014 } 7015 7016 #ifdef CONFIG_DEBUG_FS 7017 stmmac_init_fs(ndev); 7018 #endif 7019 7020 /* Let pm_runtime_put() disable the clocks. 7021 * If CONFIG_PM is not enabled, the clocks will stay powered. 7022 */ 7023 pm_runtime_put(device); 7024 7025 return ret; 7026 7027 error_serdes_powerup: 7028 unregister_netdev(ndev); 7029 error_netdev_register: 7030 phylink_destroy(priv->phylink); 7031 error_phy_setup: 7032 if (priv->hw->pcs != STMMAC_PCS_TBI && 7033 priv->hw->pcs != STMMAC_PCS_RTBI) 7034 stmmac_mdio_unregister(ndev); 7035 error_mdio_register: 7036 stmmac_napi_del(ndev); 7037 error_hw_init: 7038 destroy_workqueue(priv->wq); 7039 stmmac_bus_clks_config(priv, false); 7040 bitmap_free(priv->af_xdp_zc_qps); 7041 7042 return ret; 7043 } 7044 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7045 7046 /** 7047 * stmmac_dvr_remove 7048 * @dev: device pointer 7049 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7050 * changes the link status, releases the DMA descriptor rings. 7051 */ 7052 int stmmac_dvr_remove(struct device *dev) 7053 { 7054 struct net_device *ndev = dev_get_drvdata(dev); 7055 struct stmmac_priv *priv = netdev_priv(ndev); 7056 7057 netdev_info(priv->dev, "%s: removing driver", __func__); 7058 7059 stmmac_stop_all_dma(priv); 7060 stmmac_mac_set(priv, priv->ioaddr, false); 7061 netif_carrier_off(ndev); 7062 unregister_netdev(ndev); 7063 7064 /* Serdes power down needs to happen after VLAN filter 7065 * is deleted that is triggered by unregister_netdev(). 7066 */ 7067 if (priv->plat->serdes_powerdown) 7068 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7069 7070 #ifdef CONFIG_DEBUG_FS 7071 stmmac_exit_fs(ndev); 7072 #endif 7073 phylink_destroy(priv->phylink); 7074 if (priv->plat->stmmac_rst) 7075 reset_control_assert(priv->plat->stmmac_rst); 7076 pm_runtime_put(dev); 7077 pm_runtime_disable(dev); 7078 if (priv->hw->pcs != STMMAC_PCS_TBI && 7079 priv->hw->pcs != STMMAC_PCS_RTBI) 7080 stmmac_mdio_unregister(ndev); 7081 destroy_workqueue(priv->wq); 7082 mutex_destroy(&priv->lock); 7083 bitmap_free(priv->af_xdp_zc_qps); 7084 7085 return 0; 7086 } 7087 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7088 7089 /** 7090 * stmmac_suspend - suspend callback 7091 * @dev: device pointer 7092 * Description: this is the function to suspend the device and it is called 7093 * by the platform driver to stop the network queue, release the resources, 7094 * program the PMT register (for WoL), clean and release driver resources. 7095 */ 7096 int stmmac_suspend(struct device *dev) 7097 { 7098 struct net_device *ndev = dev_get_drvdata(dev); 7099 struct stmmac_priv *priv = netdev_priv(ndev); 7100 u32 chan; 7101 int ret; 7102 7103 if (!ndev || !netif_running(ndev)) 7104 return 0; 7105 7106 phylink_mac_change(priv->phylink, false); 7107 7108 mutex_lock(&priv->lock); 7109 7110 netif_device_detach(ndev); 7111 7112 stmmac_disable_all_queues(priv); 7113 7114 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7115 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 7116 7117 if (priv->eee_enabled) { 7118 priv->tx_path_in_lpi_mode = false; 7119 del_timer_sync(&priv->eee_ctrl_timer); 7120 } 7121 7122 /* Stop TX/RX DMA */ 7123 stmmac_stop_all_dma(priv); 7124 7125 if (priv->plat->serdes_powerdown) 7126 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7127 7128 /* Enable Power down mode by programming the PMT regs */ 7129 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7130 stmmac_pmt(priv, priv->hw, priv->wolopts); 7131 priv->irq_wake = 1; 7132 } else { 7133 mutex_unlock(&priv->lock); 7134 rtnl_lock(); 7135 if (device_may_wakeup(priv->device)) 7136 phylink_speed_down(priv->phylink, false); 7137 phylink_stop(priv->phylink); 7138 rtnl_unlock(); 7139 mutex_lock(&priv->lock); 7140 7141 stmmac_mac_set(priv, priv->ioaddr, false); 7142 pinctrl_pm_select_sleep_state(priv->device); 7143 /* Disable clock in case of PWM is off */ 7144 clk_disable_unprepare(priv->plat->clk_ptp_ref); 7145 ret = pm_runtime_force_suspend(dev); 7146 if (ret) { 7147 mutex_unlock(&priv->lock); 7148 return ret; 7149 } 7150 } 7151 7152 mutex_unlock(&priv->lock); 7153 7154 if (priv->dma_cap.fpesel) { 7155 /* Disable FPE */ 7156 stmmac_fpe_configure(priv, priv->ioaddr, 7157 priv->plat->tx_queues_to_use, 7158 priv->plat->rx_queues_to_use, false); 7159 7160 stmmac_fpe_handshake(priv, false); 7161 } 7162 7163 priv->speed = SPEED_UNKNOWN; 7164 return 0; 7165 } 7166 EXPORT_SYMBOL_GPL(stmmac_suspend); 7167 7168 /** 7169 * stmmac_reset_queues_param - reset queue parameters 7170 * @priv: device pointer 7171 */ 7172 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7173 { 7174 u32 rx_cnt = priv->plat->rx_queues_to_use; 7175 u32 tx_cnt = priv->plat->tx_queues_to_use; 7176 u32 queue; 7177 7178 for (queue = 0; queue < rx_cnt; queue++) { 7179 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 7180 7181 rx_q->cur_rx = 0; 7182 rx_q->dirty_rx = 0; 7183 } 7184 7185 for (queue = 0; queue < tx_cnt; queue++) { 7186 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 7187 7188 tx_q->cur_tx = 0; 7189 tx_q->dirty_tx = 0; 7190 tx_q->mss = 0; 7191 7192 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7193 } 7194 } 7195 7196 /** 7197 * stmmac_resume - resume callback 7198 * @dev: device pointer 7199 * Description: when resume this function is invoked to setup the DMA and CORE 7200 * in a usable state. 7201 */ 7202 int stmmac_resume(struct device *dev) 7203 { 7204 struct net_device *ndev = dev_get_drvdata(dev); 7205 struct stmmac_priv *priv = netdev_priv(ndev); 7206 int ret; 7207 7208 if (!netif_running(ndev)) 7209 return 0; 7210 7211 /* Power Down bit, into the PM register, is cleared 7212 * automatically as soon as a magic packet or a Wake-up frame 7213 * is received. Anyway, it's better to manually clear 7214 * this bit because it can generate problems while resuming 7215 * from another devices (e.g. serial console). 7216 */ 7217 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7218 mutex_lock(&priv->lock); 7219 stmmac_pmt(priv, priv->hw, 0); 7220 mutex_unlock(&priv->lock); 7221 priv->irq_wake = 0; 7222 } else { 7223 pinctrl_pm_select_default_state(priv->device); 7224 /* enable the clk previously disabled */ 7225 ret = pm_runtime_force_resume(dev); 7226 if (ret) 7227 return ret; 7228 if (priv->plat->clk_ptp_ref) 7229 clk_prepare_enable(priv->plat->clk_ptp_ref); 7230 /* reset the phy so that it's ready */ 7231 if (priv->mii) 7232 stmmac_mdio_reset(priv->mii); 7233 } 7234 7235 if (priv->plat->serdes_powerup) { 7236 ret = priv->plat->serdes_powerup(ndev, 7237 priv->plat->bsp_priv); 7238 7239 if (ret < 0) 7240 return ret; 7241 } 7242 7243 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 7244 rtnl_lock(); 7245 phylink_start(priv->phylink); 7246 /* We may have called phylink_speed_down before */ 7247 phylink_speed_up(priv->phylink); 7248 rtnl_unlock(); 7249 } 7250 7251 rtnl_lock(); 7252 mutex_lock(&priv->lock); 7253 7254 stmmac_reset_queues_param(priv); 7255 7256 stmmac_free_tx_skbufs(priv); 7257 stmmac_clear_descriptors(priv); 7258 7259 stmmac_hw_setup(ndev, false); 7260 stmmac_init_coalesce(priv); 7261 stmmac_set_rx_mode(ndev); 7262 7263 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7264 7265 stmmac_enable_all_queues(priv); 7266 7267 mutex_unlock(&priv->lock); 7268 rtnl_unlock(); 7269 7270 phylink_mac_change(priv->phylink, true); 7271 7272 netif_device_attach(ndev); 7273 7274 return 0; 7275 } 7276 EXPORT_SYMBOL_GPL(stmmac_resume); 7277 7278 #ifndef MODULE 7279 static int __init stmmac_cmdline_opt(char *str) 7280 { 7281 char *opt; 7282 7283 if (!str || !*str) 7284 return -EINVAL; 7285 while ((opt = strsep(&str, ",")) != NULL) { 7286 if (!strncmp(opt, "debug:", 6)) { 7287 if (kstrtoint(opt + 6, 0, &debug)) 7288 goto err; 7289 } else if (!strncmp(opt, "phyaddr:", 8)) { 7290 if (kstrtoint(opt + 8, 0, &phyaddr)) 7291 goto err; 7292 } else if (!strncmp(opt, "buf_sz:", 7)) { 7293 if (kstrtoint(opt + 7, 0, &buf_sz)) 7294 goto err; 7295 } else if (!strncmp(opt, "tc:", 3)) { 7296 if (kstrtoint(opt + 3, 0, &tc)) 7297 goto err; 7298 } else if (!strncmp(opt, "watchdog:", 9)) { 7299 if (kstrtoint(opt + 9, 0, &watchdog)) 7300 goto err; 7301 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7302 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7303 goto err; 7304 } else if (!strncmp(opt, "pause:", 6)) { 7305 if (kstrtoint(opt + 6, 0, &pause)) 7306 goto err; 7307 } else if (!strncmp(opt, "eee_timer:", 10)) { 7308 if (kstrtoint(opt + 10, 0, &eee_timer)) 7309 goto err; 7310 } else if (!strncmp(opt, "chain_mode:", 11)) { 7311 if (kstrtoint(opt + 11, 0, &chain_mode)) 7312 goto err; 7313 } 7314 } 7315 return 0; 7316 7317 err: 7318 pr_err("%s: ERROR broken module parameter conversion", __func__); 7319 return -EINVAL; 7320 } 7321 7322 __setup("stmmaceth=", stmmac_cmdline_opt); 7323 #endif /* MODULE */ 7324 7325 static int __init stmmac_init(void) 7326 { 7327 #ifdef CONFIG_DEBUG_FS 7328 /* Create debugfs main directory if it doesn't exist yet */ 7329 if (!stmmac_fs_dir) 7330 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7331 register_netdevice_notifier(&stmmac_notifier); 7332 #endif 7333 7334 return 0; 7335 } 7336 7337 static void __exit stmmac_exit(void) 7338 { 7339 #ifdef CONFIG_DEBUG_FS 7340 unregister_netdevice_notifier(&stmmac_notifier); 7341 debugfs_remove_recursive(stmmac_fs_dir); 7342 #endif 7343 } 7344 7345 module_init(stmmac_init) 7346 module_exit(stmmac_exit) 7347 7348 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7349 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7350 MODULE_LICENSE("GPL"); 7351