1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 57 58 /* Module parameters */ 59 #define TX_TIMEO 5000 60 static int watchdog = TX_TIMEO; 61 module_param(watchdog, int, S_IRUGO | S_IWUSR); 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 63 64 static int debug = -1; 65 module_param(debug, int, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 67 68 static int phyaddr = -1; 69 module_param(phyaddr, int, S_IRUGO); 70 MODULE_PARM_DESC(phyaddr, "Physical device address"); 71 72 #define DMA_TX_SIZE 256 73 static int dma_txsize = DMA_TX_SIZE; 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 76 77 #define DMA_RX_SIZE 256 78 static int dma_rxsize = DMA_RX_SIZE; 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 81 82 static int flow_ctrl = FLOW_OFF; 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 85 86 static int pause = PAUSE_TIME; 87 module_param(pause, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 89 90 #define TC_DEFAULT 64 91 static int tc = TC_DEFAULT; 92 module_param(tc, int, S_IRUGO | S_IWUSR); 93 MODULE_PARM_DESC(tc, "DMA threshold control value"); 94 95 #define DEFAULT_BUFSIZE 1536 96 static int buf_sz = DEFAULT_BUFSIZE; 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 99 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 101 NETIF_MSG_LINK | NETIF_MSG_IFUP | 102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 103 104 #define STMMAC_DEFAULT_LPI_TIMER 1000 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 109 110 /* By default the driver will use the ring mode to manage tx and rx descriptors 111 * but passing this value so user can force to use the chain instead of the ring 112 */ 113 static unsigned int chain_mode; 114 module_param(chain_mode, int, S_IRUGO); 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 116 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 118 119 #ifdef CONFIG_DEBUG_FS 120 static int stmmac_init_fs(struct net_device *dev); 121 static void stmmac_exit_fs(void); 122 #endif 123 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 125 126 /** 127 * stmmac_verify_args - verify the driver parameters. 128 * Description: it checks the driver parameters and set a default in case of 129 * errors. 130 */ 131 static void stmmac_verify_args(void) 132 { 133 if (unlikely(watchdog < 0)) 134 watchdog = TX_TIMEO; 135 if (unlikely(dma_rxsize < 0)) 136 dma_rxsize = DMA_RX_SIZE; 137 if (unlikely(dma_txsize < 0)) 138 dma_txsize = DMA_TX_SIZE; 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 140 buf_sz = DEFAULT_BUFSIZE; 141 if (unlikely(flow_ctrl > 1)) 142 flow_ctrl = FLOW_AUTO; 143 else if (likely(flow_ctrl < 0)) 144 flow_ctrl = FLOW_OFF; 145 if (unlikely((pause < 0) || (pause > 0xffff))) 146 pause = PAUSE_TIME; 147 if (eee_timer < 0) 148 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 149 } 150 151 /** 152 * stmmac_clk_csr_set - dynamically set the MDC clock 153 * @priv: driver private structure 154 * Description: this is to dynamically set the MDC clock according to the csr 155 * clock input. 156 * Note: 157 * If a specific clk_csr value is passed from the platform 158 * this means that the CSR Clock Range selection cannot be 159 * changed at run-time and it is fixed (as reported in the driver 160 * documentation). Viceversa the driver will try to set the MDC 161 * clock dynamically according to the actual clock input. 162 */ 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 164 { 165 u32 clk_rate; 166 167 clk_rate = clk_get_rate(priv->stmmac_clk); 168 169 /* Platform provided default clk_csr would be assumed valid 170 * for all other cases except for the below mentioned ones. 171 * For values higher than the IEEE 802.3 specified frequency 172 * we can not estimate the proper divider as it is not known 173 * the frequency of clk_csr_i. So we do not change the default 174 * divider. 175 */ 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 177 if (clk_rate < CSR_F_35M) 178 priv->clk_csr = STMMAC_CSR_20_35M; 179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 180 priv->clk_csr = STMMAC_CSR_35_60M; 181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 182 priv->clk_csr = STMMAC_CSR_60_100M; 183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 184 priv->clk_csr = STMMAC_CSR_100_150M; 185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 186 priv->clk_csr = STMMAC_CSR_150_250M; 187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 188 priv->clk_csr = STMMAC_CSR_250_300M; 189 } 190 } 191 192 static void print_pkt(unsigned char *buf, int len) 193 { 194 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 195 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 196 } 197 198 /* minimum number of free TX descriptors required to wake up TX process */ 199 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 200 201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 202 { 203 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 204 } 205 206 /** 207 * stmmac_hw_fix_mac_speed - callback for speed selection 208 * @priv: driver private structure 209 * Description: on some platforms (e.g. ST), some HW system configuraton 210 * registers have to be set according to the link speed negotiated. 211 */ 212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 213 { 214 struct phy_device *phydev = priv->phydev; 215 216 if (likely(priv->plat->fix_mac_speed)) 217 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 218 } 219 220 /** 221 * stmmac_enable_eee_mode - check and enter in LPI mode 222 * @priv: driver private structure 223 * Description: this function is to verify and enter in LPI mode in case of 224 * EEE. 225 */ 226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 227 { 228 /* Check and enter in LPI mode */ 229 if ((priv->dirty_tx == priv->cur_tx) && 230 (priv->tx_path_in_lpi_mode == false)) 231 priv->hw->mac->set_eee_mode(priv->hw); 232 } 233 234 /** 235 * stmmac_disable_eee_mode - disable and exit from LPI mode 236 * @priv: driver private structure 237 * Description: this function is to exit and disable EEE in case of 238 * LPI state is true. This is called by the xmit. 239 */ 240 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 241 { 242 priv->hw->mac->reset_eee_mode(priv->hw); 243 del_timer_sync(&priv->eee_ctrl_timer); 244 priv->tx_path_in_lpi_mode = false; 245 } 246 247 /** 248 * stmmac_eee_ctrl_timer - EEE TX SW timer. 249 * @arg : data hook 250 * Description: 251 * if there is no data transfer and if we are not in LPI state, 252 * then MAC Transmitter can be moved to LPI state. 253 */ 254 static void stmmac_eee_ctrl_timer(unsigned long arg) 255 { 256 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 257 258 stmmac_enable_eee_mode(priv); 259 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 260 } 261 262 /** 263 * stmmac_eee_init - init EEE 264 * @priv: driver private structure 265 * Description: 266 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 267 * can also manage EEE, this function enable the LPI state and start related 268 * timer. 269 */ 270 bool stmmac_eee_init(struct stmmac_priv *priv) 271 { 272 char *phy_bus_name = priv->plat->phy_bus_name; 273 unsigned long flags; 274 bool ret = false; 275 276 /* Using PCS we cannot dial with the phy registers at this stage 277 * so we do not support extra feature like EEE. 278 */ 279 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 280 (priv->pcs == STMMAC_PCS_RTBI)) 281 goto out; 282 283 /* Never init EEE in case of a switch is attached */ 284 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) 285 goto out; 286 287 /* MAC core supports the EEE feature. */ 288 if (priv->dma_cap.eee) { 289 int tx_lpi_timer = priv->tx_lpi_timer; 290 291 /* Check if the PHY supports EEE */ 292 if (phy_init_eee(priv->phydev, 1)) { 293 /* To manage at run-time if the EEE cannot be supported 294 * anymore (for example because the lp caps have been 295 * changed). 296 * In that case the driver disable own timers. 297 */ 298 spin_lock_irqsave(&priv->lock, flags); 299 if (priv->eee_active) { 300 pr_debug("stmmac: disable EEE\n"); 301 del_timer_sync(&priv->eee_ctrl_timer); 302 priv->hw->mac->set_eee_timer(priv->hw, 0, 303 tx_lpi_timer); 304 } 305 priv->eee_active = 0; 306 spin_unlock_irqrestore(&priv->lock, flags); 307 goto out; 308 } 309 /* Activate the EEE and start timers */ 310 spin_lock_irqsave(&priv->lock, flags); 311 if (!priv->eee_active) { 312 priv->eee_active = 1; 313 init_timer(&priv->eee_ctrl_timer); 314 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 315 priv->eee_ctrl_timer.data = (unsigned long)priv; 316 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 317 add_timer(&priv->eee_ctrl_timer); 318 319 priv->hw->mac->set_eee_timer(priv->hw, 320 STMMAC_DEFAULT_LIT_LS, 321 tx_lpi_timer); 322 } 323 /* Set HW EEE according to the speed */ 324 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); 325 326 ret = true; 327 spin_unlock_irqrestore(&priv->lock, flags); 328 329 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 330 } 331 out: 332 return ret; 333 } 334 335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 336 * @priv: driver private structure 337 * @entry : descriptor index to be used. 338 * @skb : the socket buffer 339 * Description : 340 * This function will read timestamp from the descriptor & pass it to stack. 341 * and also perform some sanity checks. 342 */ 343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 344 unsigned int entry, struct sk_buff *skb) 345 { 346 struct skb_shared_hwtstamps shhwtstamp; 347 u64 ns; 348 void *desc = NULL; 349 350 if (!priv->hwts_tx_en) 351 return; 352 353 /* exit if skb doesn't support hw tstamp */ 354 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 355 return; 356 357 if (priv->adv_ts) 358 desc = (priv->dma_etx + entry); 359 else 360 desc = (priv->dma_tx + entry); 361 362 /* check tx tstamp status */ 363 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 364 return; 365 366 /* get the valid tstamp */ 367 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 368 369 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 370 shhwtstamp.hwtstamp = ns_to_ktime(ns); 371 /* pass tstamp to stack */ 372 skb_tstamp_tx(skb, &shhwtstamp); 373 374 return; 375 } 376 377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 378 * @priv: driver private structure 379 * @entry : descriptor index to be used. 380 * @skb : the socket buffer 381 * Description : 382 * This function will read received packet's timestamp from the descriptor 383 * and pass it to stack. It also perform some sanity checks. 384 */ 385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 386 unsigned int entry, struct sk_buff *skb) 387 { 388 struct skb_shared_hwtstamps *shhwtstamp = NULL; 389 u64 ns; 390 void *desc = NULL; 391 392 if (!priv->hwts_rx_en) 393 return; 394 395 if (priv->adv_ts) 396 desc = (priv->dma_erx + entry); 397 else 398 desc = (priv->dma_rx + entry); 399 400 /* exit if rx tstamp is not valid */ 401 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 402 return; 403 404 /* get valid tstamp */ 405 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 406 shhwtstamp = skb_hwtstamps(skb); 407 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 408 shhwtstamp->hwtstamp = ns_to_ktime(ns); 409 } 410 411 /** 412 * stmmac_hwtstamp_ioctl - control hardware timestamping. 413 * @dev: device pointer. 414 * @ifr: An IOCTL specefic structure, that can contain a pointer to 415 * a proprietary structure used to pass information to the driver. 416 * Description: 417 * This function configures the MAC to enable/disable both outgoing(TX) 418 * and incoming(RX) packets time stamping based on user input. 419 * Return Value: 420 * 0 on success and an appropriate -ve integer on failure. 421 */ 422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 423 { 424 struct stmmac_priv *priv = netdev_priv(dev); 425 struct hwtstamp_config config; 426 struct timespec now; 427 u64 temp = 0; 428 u32 ptp_v2 = 0; 429 u32 tstamp_all = 0; 430 u32 ptp_over_ipv4_udp = 0; 431 u32 ptp_over_ipv6_udp = 0; 432 u32 ptp_over_ethernet = 0; 433 u32 snap_type_sel = 0; 434 u32 ts_master_en = 0; 435 u32 ts_event_en = 0; 436 u32 value = 0; 437 438 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 439 netdev_alert(priv->dev, "No support for HW time stamping\n"); 440 priv->hwts_tx_en = 0; 441 priv->hwts_rx_en = 0; 442 443 return -EOPNOTSUPP; 444 } 445 446 if (copy_from_user(&config, ifr->ifr_data, 447 sizeof(struct hwtstamp_config))) 448 return -EFAULT; 449 450 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 451 __func__, config.flags, config.tx_type, config.rx_filter); 452 453 /* reserved for future extensions */ 454 if (config.flags) 455 return -EINVAL; 456 457 if (config.tx_type != HWTSTAMP_TX_OFF && 458 config.tx_type != HWTSTAMP_TX_ON) 459 return -ERANGE; 460 461 if (priv->adv_ts) { 462 switch (config.rx_filter) { 463 case HWTSTAMP_FILTER_NONE: 464 /* time stamp no incoming packet at all */ 465 config.rx_filter = HWTSTAMP_FILTER_NONE; 466 break; 467 468 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 469 /* PTP v1, UDP, any kind of event packet */ 470 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 471 /* take time stamp for all event messages */ 472 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 473 474 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 475 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 476 break; 477 478 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 479 /* PTP v1, UDP, Sync packet */ 480 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 481 /* take time stamp for SYNC messages only */ 482 ts_event_en = PTP_TCR_TSEVNTENA; 483 484 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 485 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 486 break; 487 488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 489 /* PTP v1, UDP, Delay_req packet */ 490 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 491 /* take time stamp for Delay_Req messages only */ 492 ts_master_en = PTP_TCR_TSMSTRENA; 493 ts_event_en = PTP_TCR_TSEVNTENA; 494 495 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 496 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 497 break; 498 499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 500 /* PTP v2, UDP, any kind of event packet */ 501 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 502 ptp_v2 = PTP_TCR_TSVER2ENA; 503 /* take time stamp for all event messages */ 504 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 505 506 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 507 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 508 break; 509 510 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 511 /* PTP v2, UDP, Sync packet */ 512 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 513 ptp_v2 = PTP_TCR_TSVER2ENA; 514 /* take time stamp for SYNC messages only */ 515 ts_event_en = PTP_TCR_TSEVNTENA; 516 517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 519 break; 520 521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 522 /* PTP v2, UDP, Delay_req packet */ 523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 524 ptp_v2 = PTP_TCR_TSVER2ENA; 525 /* take time stamp for Delay_Req messages only */ 526 ts_master_en = PTP_TCR_TSMSTRENA; 527 ts_event_en = PTP_TCR_TSEVNTENA; 528 529 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 530 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 531 break; 532 533 case HWTSTAMP_FILTER_PTP_V2_EVENT: 534 /* PTP v2/802.AS1 any layer, any kind of event packet */ 535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 536 ptp_v2 = PTP_TCR_TSVER2ENA; 537 /* take time stamp for all event messages */ 538 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 539 540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 542 ptp_over_ethernet = PTP_TCR_TSIPENA; 543 break; 544 545 case HWTSTAMP_FILTER_PTP_V2_SYNC: 546 /* PTP v2/802.AS1, any layer, Sync packet */ 547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 548 ptp_v2 = PTP_TCR_TSVER2ENA; 549 /* take time stamp for SYNC messages only */ 550 ts_event_en = PTP_TCR_TSEVNTENA; 551 552 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 553 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 554 ptp_over_ethernet = PTP_TCR_TSIPENA; 555 break; 556 557 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 558 /* PTP v2/802.AS1, any layer, Delay_req packet */ 559 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 560 ptp_v2 = PTP_TCR_TSVER2ENA; 561 /* take time stamp for Delay_Req messages only */ 562 ts_master_en = PTP_TCR_TSMSTRENA; 563 ts_event_en = PTP_TCR_TSEVNTENA; 564 565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 567 ptp_over_ethernet = PTP_TCR_TSIPENA; 568 break; 569 570 case HWTSTAMP_FILTER_ALL: 571 /* time stamp any incoming packet */ 572 config.rx_filter = HWTSTAMP_FILTER_ALL; 573 tstamp_all = PTP_TCR_TSENALL; 574 break; 575 576 default: 577 return -ERANGE; 578 } 579 } else { 580 switch (config.rx_filter) { 581 case HWTSTAMP_FILTER_NONE: 582 config.rx_filter = HWTSTAMP_FILTER_NONE; 583 break; 584 default: 585 /* PTP v1, UDP, any kind of event packet */ 586 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 587 break; 588 } 589 } 590 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 591 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 592 593 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 594 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 595 else { 596 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 597 tstamp_all | ptp_v2 | ptp_over_ethernet | 598 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 599 ts_master_en | snap_type_sel); 600 601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 602 603 /* program Sub Second Increment reg */ 604 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 605 606 /* calculate default added value: 607 * formula is : 608 * addend = (2^32)/freq_div_ratio; 609 * where, freq_div_ratio = clk_ptp_ref_i/50MHz 610 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; 611 * NOTE: clk_ptp_ref_i should be >= 50MHz to 612 * achive 20ns accuracy. 613 * 614 * 2^x * y == (y << x), hence 615 * 2^32 * 50000000 ==> (50000000 << 32) 616 */ 617 temp = (u64) (50000000ULL << 32); 618 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 619 priv->hw->ptp->config_addend(priv->ioaddr, 620 priv->default_addend); 621 622 /* initialize system time */ 623 getnstimeofday(&now); 624 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 625 now.tv_nsec); 626 } 627 628 return copy_to_user(ifr->ifr_data, &config, 629 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 630 } 631 632 /** 633 * stmmac_init_ptp - init PTP 634 * @priv: driver private structure 635 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 636 * This is done by looking at the HW cap. register. 637 * This function also registers the ptp driver. 638 */ 639 static int stmmac_init_ptp(struct stmmac_priv *priv) 640 { 641 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 642 return -EOPNOTSUPP; 643 644 /* Fall-back to main clock in case of no PTP ref is passed */ 645 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 646 if (IS_ERR(priv->clk_ptp_ref)) { 647 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 648 priv->clk_ptp_ref = NULL; 649 } else { 650 clk_prepare_enable(priv->clk_ptp_ref); 651 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 652 } 653 654 priv->adv_ts = 0; 655 if (priv->dma_cap.atime_stamp && priv->extend_desc) 656 priv->adv_ts = 1; 657 658 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 659 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 660 661 if (netif_msg_hw(priv) && priv->adv_ts) 662 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 663 664 priv->hw->ptp = &stmmac_ptp; 665 priv->hwts_tx_en = 0; 666 priv->hwts_rx_en = 0; 667 668 return stmmac_ptp_register(priv); 669 } 670 671 static void stmmac_release_ptp(struct stmmac_priv *priv) 672 { 673 if (priv->clk_ptp_ref) 674 clk_disable_unprepare(priv->clk_ptp_ref); 675 stmmac_ptp_unregister(priv); 676 } 677 678 /** 679 * stmmac_adjust_link - adjusts the link parameters 680 * @dev: net device structure 681 * Description: this is the helper called by the physical abstraction layer 682 * drivers to communicate the phy link status. According the speed and duplex 683 * this driver can invoke registered glue-logic as well. 684 * It also invoke the eee initialization because it could happen when switch 685 * on different networks (that are eee capable). 686 */ 687 static void stmmac_adjust_link(struct net_device *dev) 688 { 689 struct stmmac_priv *priv = netdev_priv(dev); 690 struct phy_device *phydev = priv->phydev; 691 unsigned long flags; 692 int new_state = 0; 693 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 694 695 if (phydev == NULL) 696 return; 697 698 spin_lock_irqsave(&priv->lock, flags); 699 700 if (phydev->link) { 701 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 702 703 /* Now we make sure that we can be in full duplex mode. 704 * If not, we operate in half-duplex mode. */ 705 if (phydev->duplex != priv->oldduplex) { 706 new_state = 1; 707 if (!(phydev->duplex)) 708 ctrl &= ~priv->hw->link.duplex; 709 else 710 ctrl |= priv->hw->link.duplex; 711 priv->oldduplex = phydev->duplex; 712 } 713 /* Flow Control operation */ 714 if (phydev->pause) 715 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 716 fc, pause_time); 717 718 if (phydev->speed != priv->speed) { 719 new_state = 1; 720 switch (phydev->speed) { 721 case 1000: 722 if (likely(priv->plat->has_gmac)) 723 ctrl &= ~priv->hw->link.port; 724 stmmac_hw_fix_mac_speed(priv); 725 break; 726 case 100: 727 case 10: 728 if (priv->plat->has_gmac) { 729 ctrl |= priv->hw->link.port; 730 if (phydev->speed == SPEED_100) { 731 ctrl |= priv->hw->link.speed; 732 } else { 733 ctrl &= ~(priv->hw->link.speed); 734 } 735 } else { 736 ctrl &= ~priv->hw->link.port; 737 } 738 stmmac_hw_fix_mac_speed(priv); 739 break; 740 default: 741 if (netif_msg_link(priv)) 742 pr_warn("%s: Speed (%d) not 10/100\n", 743 dev->name, phydev->speed); 744 break; 745 } 746 747 priv->speed = phydev->speed; 748 } 749 750 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 751 752 if (!priv->oldlink) { 753 new_state = 1; 754 priv->oldlink = 1; 755 } 756 } else if (priv->oldlink) { 757 new_state = 1; 758 priv->oldlink = 0; 759 priv->speed = 0; 760 priv->oldduplex = -1; 761 } 762 763 if (new_state && netif_msg_link(priv)) 764 phy_print_status(phydev); 765 766 spin_unlock_irqrestore(&priv->lock, flags); 767 768 /* At this stage, it could be needed to setup the EEE or adjust some 769 * MAC related HW registers. 770 */ 771 priv->eee_enabled = stmmac_eee_init(priv); 772 } 773 774 /** 775 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 776 * @priv: driver private structure 777 * Description: this is to verify if the HW supports the PCS. 778 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 779 * configured for the TBI, RTBI, or SGMII PHY interface. 780 */ 781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 782 { 783 int interface = priv->plat->interface; 784 785 if (priv->dma_cap.pcs) { 786 if ((interface == PHY_INTERFACE_MODE_RGMII) || 787 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 788 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 789 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 790 pr_debug("STMMAC: PCS RGMII support enable\n"); 791 priv->pcs = STMMAC_PCS_RGMII; 792 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 793 pr_debug("STMMAC: PCS SGMII support enable\n"); 794 priv->pcs = STMMAC_PCS_SGMII; 795 } 796 } 797 } 798 799 /** 800 * stmmac_init_phy - PHY initialization 801 * @dev: net device structure 802 * Description: it initializes the driver's PHY state, and attaches the PHY 803 * to the mac driver. 804 * Return value: 805 * 0 on success 806 */ 807 static int stmmac_init_phy(struct net_device *dev) 808 { 809 struct stmmac_priv *priv = netdev_priv(dev); 810 struct phy_device *phydev; 811 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 812 char bus_id[MII_BUS_ID_SIZE]; 813 int interface = priv->plat->interface; 814 int max_speed = priv->plat->max_speed; 815 priv->oldlink = 0; 816 priv->speed = 0; 817 priv->oldduplex = -1; 818 819 if (priv->plat->phy_bus_name) 820 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 821 priv->plat->phy_bus_name, priv->plat->bus_id); 822 else 823 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 824 priv->plat->bus_id); 825 826 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 827 priv->plat->phy_addr); 828 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 829 830 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 831 832 if (IS_ERR(phydev)) { 833 pr_err("%s: Could not attach to PHY\n", dev->name); 834 return PTR_ERR(phydev); 835 } 836 837 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 838 if ((interface == PHY_INTERFACE_MODE_MII) || 839 (interface == PHY_INTERFACE_MODE_RMII) || 840 (max_speed < 1000 && max_speed > 0)) 841 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 842 SUPPORTED_1000baseT_Full); 843 844 /* 845 * Broken HW is sometimes missing the pull-up resistor on the 846 * MDIO line, which results in reads to non-existent devices returning 847 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 848 * device as well. 849 * Note: phydev->phy_id is the result of reading the UID PHY registers. 850 */ 851 if (phydev->phy_id == 0) { 852 phy_disconnect(phydev); 853 return -ENODEV; 854 } 855 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 856 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 857 858 priv->phydev = phydev; 859 860 return 0; 861 } 862 863 /** 864 * stmmac_display_ring - display ring 865 * @head: pointer to the head of the ring passed. 866 * @size: size of the ring. 867 * @extend_desc: to verify if extended descriptors are used. 868 * Description: display the control/status and buffer descriptors. 869 */ 870 static void stmmac_display_ring(void *head, int size, int extend_desc) 871 { 872 int i; 873 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 874 struct dma_desc *p = (struct dma_desc *)head; 875 876 for (i = 0; i < size; i++) { 877 u64 x; 878 if (extend_desc) { 879 x = *(u64 *) ep; 880 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 881 i, (unsigned int)virt_to_phys(ep), 882 (unsigned int)x, (unsigned int)(x >> 32), 883 ep->basic.des2, ep->basic.des3); 884 ep++; 885 } else { 886 x = *(u64 *) p; 887 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 888 i, (unsigned int)virt_to_phys(p), 889 (unsigned int)x, (unsigned int)(x >> 32), 890 p->des2, p->des3); 891 p++; 892 } 893 pr_info("\n"); 894 } 895 } 896 897 static void stmmac_display_rings(struct stmmac_priv *priv) 898 { 899 unsigned int txsize = priv->dma_tx_size; 900 unsigned int rxsize = priv->dma_rx_size; 901 902 if (priv->extend_desc) { 903 pr_info("Extended RX descriptor ring:\n"); 904 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 905 pr_info("Extended TX descriptor ring:\n"); 906 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 907 } else { 908 pr_info("RX descriptor ring:\n"); 909 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 910 pr_info("TX descriptor ring:\n"); 911 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 912 } 913 } 914 915 static int stmmac_set_bfsize(int mtu, int bufsize) 916 { 917 int ret = bufsize; 918 919 if (mtu >= BUF_SIZE_4KiB) 920 ret = BUF_SIZE_8KiB; 921 else if (mtu >= BUF_SIZE_2KiB) 922 ret = BUF_SIZE_4KiB; 923 else if (mtu > DEFAULT_BUFSIZE) 924 ret = BUF_SIZE_2KiB; 925 else 926 ret = DEFAULT_BUFSIZE; 927 928 return ret; 929 } 930 931 /** 932 * stmmac_clear_descriptors - clear descriptors 933 * @priv: driver private structure 934 * Description: this function is called to clear the tx and rx descriptors 935 * in case of both basic and extended descriptors are used. 936 */ 937 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 938 { 939 int i; 940 unsigned int txsize = priv->dma_tx_size; 941 unsigned int rxsize = priv->dma_rx_size; 942 943 /* Clear the Rx/Tx descriptors */ 944 for (i = 0; i < rxsize; i++) 945 if (priv->extend_desc) 946 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 947 priv->use_riwt, priv->mode, 948 (i == rxsize - 1)); 949 else 950 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 951 priv->use_riwt, priv->mode, 952 (i == rxsize - 1)); 953 for (i = 0; i < txsize; i++) 954 if (priv->extend_desc) 955 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 956 priv->mode, 957 (i == txsize - 1)); 958 else 959 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 960 priv->mode, 961 (i == txsize - 1)); 962 } 963 964 /** 965 * stmmac_init_rx_buffers - init the RX descriptor buffer. 966 * @priv: driver private structure 967 * @p: descriptor pointer 968 * @i: descriptor index 969 * @flags: gfp flag. 970 * Description: this function is called to allocate a receive buffer, perform 971 * the DMA mapping and init the descriptor. 972 */ 973 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 974 int i, gfp_t flags) 975 { 976 struct sk_buff *skb; 977 978 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 979 flags); 980 if (!skb) { 981 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 982 return -ENOMEM; 983 } 984 skb_reserve(skb, NET_IP_ALIGN); 985 priv->rx_skbuff[i] = skb; 986 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 987 priv->dma_buf_sz, 988 DMA_FROM_DEVICE); 989 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 990 pr_err("%s: DMA mapping error\n", __func__); 991 dev_kfree_skb_any(skb); 992 return -EINVAL; 993 } 994 995 p->des2 = priv->rx_skbuff_dma[i]; 996 997 if ((priv->hw->mode->init_desc3) && 998 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 999 priv->hw->mode->init_desc3(p); 1000 1001 return 0; 1002 } 1003 1004 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 1005 { 1006 if (priv->rx_skbuff[i]) { 1007 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1008 priv->dma_buf_sz, DMA_FROM_DEVICE); 1009 dev_kfree_skb_any(priv->rx_skbuff[i]); 1010 } 1011 priv->rx_skbuff[i] = NULL; 1012 } 1013 1014 /** 1015 * init_dma_desc_rings - init the RX/TX descriptor rings 1016 * @dev: net device structure 1017 * @flags: gfp flag. 1018 * Description: this function initializes the DMA RX/TX descriptors 1019 * and allocates the socket buffers. It suppors the chained and ring 1020 * modes. 1021 */ 1022 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1023 { 1024 int i; 1025 struct stmmac_priv *priv = netdev_priv(dev); 1026 unsigned int txsize = priv->dma_tx_size; 1027 unsigned int rxsize = priv->dma_rx_size; 1028 unsigned int bfsize = 0; 1029 int ret = -ENOMEM; 1030 1031 if (priv->hw->mode->set_16kib_bfsize) 1032 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1033 1034 if (bfsize < BUF_SIZE_16KiB) 1035 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1036 1037 priv->dma_buf_sz = bfsize; 1038 1039 if (netif_msg_probe(priv)) 1040 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1041 txsize, rxsize, bfsize); 1042 1043 if (netif_msg_probe(priv)) { 1044 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1045 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1046 1047 /* RX INITIALIZATION */ 1048 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1049 } 1050 for (i = 0; i < rxsize; i++) { 1051 struct dma_desc *p; 1052 if (priv->extend_desc) 1053 p = &((priv->dma_erx + i)->basic); 1054 else 1055 p = priv->dma_rx + i; 1056 1057 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1058 if (ret) 1059 goto err_init_rx_buffers; 1060 1061 if (netif_msg_probe(priv)) 1062 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1063 priv->rx_skbuff[i]->data, 1064 (unsigned int)priv->rx_skbuff_dma[i]); 1065 } 1066 priv->cur_rx = 0; 1067 priv->dirty_rx = (unsigned int)(i - rxsize); 1068 buf_sz = bfsize; 1069 1070 /* Setup the chained descriptor addresses */ 1071 if (priv->mode == STMMAC_CHAIN_MODE) { 1072 if (priv->extend_desc) { 1073 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1074 rxsize, 1); 1075 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1076 txsize, 1); 1077 } else { 1078 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1079 rxsize, 0); 1080 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1081 txsize, 0); 1082 } 1083 } 1084 1085 /* TX INITIALIZATION */ 1086 for (i = 0; i < txsize; i++) { 1087 struct dma_desc *p; 1088 if (priv->extend_desc) 1089 p = &((priv->dma_etx + i)->basic); 1090 else 1091 p = priv->dma_tx + i; 1092 p->des2 = 0; 1093 priv->tx_skbuff_dma[i].buf = 0; 1094 priv->tx_skbuff_dma[i].map_as_page = false; 1095 priv->tx_skbuff[i] = NULL; 1096 } 1097 1098 priv->dirty_tx = 0; 1099 priv->cur_tx = 0; 1100 1101 stmmac_clear_descriptors(priv); 1102 1103 if (netif_msg_hw(priv)) 1104 stmmac_display_rings(priv); 1105 1106 return 0; 1107 err_init_rx_buffers: 1108 while (--i >= 0) 1109 stmmac_free_rx_buffers(priv, i); 1110 return ret; 1111 } 1112 1113 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1114 { 1115 int i; 1116 1117 for (i = 0; i < priv->dma_rx_size; i++) 1118 stmmac_free_rx_buffers(priv, i); 1119 } 1120 1121 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1122 { 1123 int i; 1124 1125 for (i = 0; i < priv->dma_tx_size; i++) { 1126 struct dma_desc *p; 1127 1128 if (priv->extend_desc) 1129 p = &((priv->dma_etx + i)->basic); 1130 else 1131 p = priv->dma_tx + i; 1132 1133 if (priv->tx_skbuff_dma[i].buf) { 1134 if (priv->tx_skbuff_dma[i].map_as_page) 1135 dma_unmap_page(priv->device, 1136 priv->tx_skbuff_dma[i].buf, 1137 priv->hw->desc->get_tx_len(p), 1138 DMA_TO_DEVICE); 1139 else 1140 dma_unmap_single(priv->device, 1141 priv->tx_skbuff_dma[i].buf, 1142 priv->hw->desc->get_tx_len(p), 1143 DMA_TO_DEVICE); 1144 } 1145 1146 if (priv->tx_skbuff[i] != NULL) { 1147 dev_kfree_skb_any(priv->tx_skbuff[i]); 1148 priv->tx_skbuff[i] = NULL; 1149 priv->tx_skbuff_dma[i].buf = 0; 1150 priv->tx_skbuff_dma[i].map_as_page = false; 1151 } 1152 } 1153 } 1154 1155 /** 1156 * alloc_dma_desc_resources - alloc TX/RX resources. 1157 * @priv: private structure 1158 * Description: according to which descriptor can be used (extend or basic) 1159 * this function allocates the resources for TX and RX paths. In case of 1160 * reception, for example, it pre-allocated the RX socket buffer in order to 1161 * allow zero-copy mechanism. 1162 */ 1163 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1164 { 1165 unsigned int txsize = priv->dma_tx_size; 1166 unsigned int rxsize = priv->dma_rx_size; 1167 int ret = -ENOMEM; 1168 1169 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1170 GFP_KERNEL); 1171 if (!priv->rx_skbuff_dma) 1172 return -ENOMEM; 1173 1174 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1175 GFP_KERNEL); 1176 if (!priv->rx_skbuff) 1177 goto err_rx_skbuff; 1178 1179 priv->tx_skbuff_dma = kmalloc_array(txsize, 1180 sizeof(*priv->tx_skbuff_dma), 1181 GFP_KERNEL); 1182 if (!priv->tx_skbuff_dma) 1183 goto err_tx_skbuff_dma; 1184 1185 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1186 GFP_KERNEL); 1187 if (!priv->tx_skbuff) 1188 goto err_tx_skbuff; 1189 1190 if (priv->extend_desc) { 1191 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1192 sizeof(struct 1193 dma_extended_desc), 1194 &priv->dma_rx_phy, 1195 GFP_KERNEL); 1196 if (!priv->dma_erx) 1197 goto err_dma; 1198 1199 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1200 sizeof(struct 1201 dma_extended_desc), 1202 &priv->dma_tx_phy, 1203 GFP_KERNEL); 1204 if (!priv->dma_etx) { 1205 dma_free_coherent(priv->device, priv->dma_rx_size * 1206 sizeof(struct dma_extended_desc), 1207 priv->dma_erx, priv->dma_rx_phy); 1208 goto err_dma; 1209 } 1210 } else { 1211 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1212 sizeof(struct dma_desc), 1213 &priv->dma_rx_phy, 1214 GFP_KERNEL); 1215 if (!priv->dma_rx) 1216 goto err_dma; 1217 1218 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1219 sizeof(struct dma_desc), 1220 &priv->dma_tx_phy, 1221 GFP_KERNEL); 1222 if (!priv->dma_tx) { 1223 dma_free_coherent(priv->device, priv->dma_rx_size * 1224 sizeof(struct dma_desc), 1225 priv->dma_rx, priv->dma_rx_phy); 1226 goto err_dma; 1227 } 1228 } 1229 1230 return 0; 1231 1232 err_dma: 1233 kfree(priv->tx_skbuff); 1234 err_tx_skbuff: 1235 kfree(priv->tx_skbuff_dma); 1236 err_tx_skbuff_dma: 1237 kfree(priv->rx_skbuff); 1238 err_rx_skbuff: 1239 kfree(priv->rx_skbuff_dma); 1240 return ret; 1241 } 1242 1243 static void free_dma_desc_resources(struct stmmac_priv *priv) 1244 { 1245 /* Release the DMA TX/RX socket buffers */ 1246 dma_free_rx_skbufs(priv); 1247 dma_free_tx_skbufs(priv); 1248 1249 /* Free DMA regions of consistent memory previously allocated */ 1250 if (!priv->extend_desc) { 1251 dma_free_coherent(priv->device, 1252 priv->dma_tx_size * sizeof(struct dma_desc), 1253 priv->dma_tx, priv->dma_tx_phy); 1254 dma_free_coherent(priv->device, 1255 priv->dma_rx_size * sizeof(struct dma_desc), 1256 priv->dma_rx, priv->dma_rx_phy); 1257 } else { 1258 dma_free_coherent(priv->device, priv->dma_tx_size * 1259 sizeof(struct dma_extended_desc), 1260 priv->dma_etx, priv->dma_tx_phy); 1261 dma_free_coherent(priv->device, priv->dma_rx_size * 1262 sizeof(struct dma_extended_desc), 1263 priv->dma_erx, priv->dma_rx_phy); 1264 } 1265 kfree(priv->rx_skbuff_dma); 1266 kfree(priv->rx_skbuff); 1267 kfree(priv->tx_skbuff_dma); 1268 kfree(priv->tx_skbuff); 1269 } 1270 1271 /** 1272 * stmmac_dma_operation_mode - HW DMA operation mode 1273 * @priv: driver private structure 1274 * Description: it is used for configuring the DMA operation mode register in 1275 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1276 */ 1277 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1278 { 1279 if (priv->plat->force_thresh_dma_mode) 1280 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1281 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1282 /* 1283 * In case of GMAC, SF mode can be enabled 1284 * to perform the TX COE in HW. This depends on: 1285 * 1) TX COE if actually supported 1286 * 2) There is no bugged Jumbo frame support 1287 * that needs to not insert csum in the TDES. 1288 */ 1289 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1290 tc = SF_DMA_MODE; 1291 } else 1292 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1293 } 1294 1295 /** 1296 * stmmac_tx_clean - to manage the transmission completion 1297 * @priv: driver private structure 1298 * Description: it reclaims the transmit resources after transmission completes. 1299 */ 1300 static void stmmac_tx_clean(struct stmmac_priv *priv) 1301 { 1302 unsigned int txsize = priv->dma_tx_size; 1303 1304 spin_lock(&priv->tx_lock); 1305 1306 priv->xstats.tx_clean++; 1307 1308 while (priv->dirty_tx != priv->cur_tx) { 1309 int last; 1310 unsigned int entry = priv->dirty_tx % txsize; 1311 struct sk_buff *skb = priv->tx_skbuff[entry]; 1312 struct dma_desc *p; 1313 1314 if (priv->extend_desc) 1315 p = (struct dma_desc *)(priv->dma_etx + entry); 1316 else 1317 p = priv->dma_tx + entry; 1318 1319 /* Check if the descriptor is owned by the DMA. */ 1320 if (priv->hw->desc->get_tx_owner(p)) 1321 break; 1322 1323 /* Verify tx error by looking at the last segment. */ 1324 last = priv->hw->desc->get_tx_ls(p); 1325 if (likely(last)) { 1326 int tx_error = 1327 priv->hw->desc->tx_status(&priv->dev->stats, 1328 &priv->xstats, p, 1329 priv->ioaddr); 1330 if (likely(tx_error == 0)) { 1331 priv->dev->stats.tx_packets++; 1332 priv->xstats.tx_pkt_n++; 1333 } else 1334 priv->dev->stats.tx_errors++; 1335 1336 stmmac_get_tx_hwtstamp(priv, entry, skb); 1337 } 1338 if (netif_msg_tx_done(priv)) 1339 pr_debug("%s: curr %d, dirty %d\n", __func__, 1340 priv->cur_tx, priv->dirty_tx); 1341 1342 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1343 if (priv->tx_skbuff_dma[entry].map_as_page) 1344 dma_unmap_page(priv->device, 1345 priv->tx_skbuff_dma[entry].buf, 1346 priv->hw->desc->get_tx_len(p), 1347 DMA_TO_DEVICE); 1348 else 1349 dma_unmap_single(priv->device, 1350 priv->tx_skbuff_dma[entry].buf, 1351 priv->hw->desc->get_tx_len(p), 1352 DMA_TO_DEVICE); 1353 priv->tx_skbuff_dma[entry].buf = 0; 1354 priv->tx_skbuff_dma[entry].map_as_page = false; 1355 } 1356 priv->hw->mode->clean_desc3(priv, p); 1357 1358 if (likely(skb != NULL)) { 1359 dev_consume_skb_any(skb); 1360 priv->tx_skbuff[entry] = NULL; 1361 } 1362 1363 priv->hw->desc->release_tx_desc(p, priv->mode); 1364 1365 priv->dirty_tx++; 1366 } 1367 if (unlikely(netif_queue_stopped(priv->dev) && 1368 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1369 netif_tx_lock(priv->dev); 1370 if (netif_queue_stopped(priv->dev) && 1371 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1372 if (netif_msg_tx_done(priv)) 1373 pr_debug("%s: restart transmit\n", __func__); 1374 netif_wake_queue(priv->dev); 1375 } 1376 netif_tx_unlock(priv->dev); 1377 } 1378 1379 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1380 stmmac_enable_eee_mode(priv); 1381 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1382 } 1383 spin_unlock(&priv->tx_lock); 1384 } 1385 1386 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1387 { 1388 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1389 } 1390 1391 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1392 { 1393 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1394 } 1395 1396 /** 1397 * stmmac_tx_err - to manage the tx error 1398 * @priv: driver private structure 1399 * Description: it cleans the descriptors and restarts the transmission 1400 * in case of transmission errors. 1401 */ 1402 static void stmmac_tx_err(struct stmmac_priv *priv) 1403 { 1404 int i; 1405 int txsize = priv->dma_tx_size; 1406 netif_stop_queue(priv->dev); 1407 1408 priv->hw->dma->stop_tx(priv->ioaddr); 1409 dma_free_tx_skbufs(priv); 1410 for (i = 0; i < txsize; i++) 1411 if (priv->extend_desc) 1412 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1413 priv->mode, 1414 (i == txsize - 1)); 1415 else 1416 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1417 priv->mode, 1418 (i == txsize - 1)); 1419 priv->dirty_tx = 0; 1420 priv->cur_tx = 0; 1421 priv->hw->dma->start_tx(priv->ioaddr); 1422 1423 priv->dev->stats.tx_errors++; 1424 netif_wake_queue(priv->dev); 1425 } 1426 1427 /** 1428 * stmmac_dma_interrupt - DMA ISR 1429 * @priv: driver private structure 1430 * Description: this is the DMA ISR. It is called by the main ISR. 1431 * It calls the dwmac dma routine and schedule poll method in case of some 1432 * work can be done. 1433 */ 1434 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1435 { 1436 int status; 1437 1438 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1439 if (likely((status & handle_rx)) || (status & handle_tx)) { 1440 if (likely(napi_schedule_prep(&priv->napi))) { 1441 stmmac_disable_dma_irq(priv); 1442 __napi_schedule(&priv->napi); 1443 } 1444 } 1445 if (unlikely(status & tx_hard_error_bump_tc)) { 1446 /* Try to bump up the dma threshold on this failure */ 1447 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1448 tc += 64; 1449 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1450 priv->xstats.threshold = tc; 1451 } 1452 } else if (unlikely(status == tx_hard_error)) 1453 stmmac_tx_err(priv); 1454 } 1455 1456 /** 1457 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1458 * @priv: driver private structure 1459 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1460 */ 1461 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1462 { 1463 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1464 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1465 1466 dwmac_mmc_intr_all_mask(priv->ioaddr); 1467 1468 if (priv->dma_cap.rmon) { 1469 dwmac_mmc_ctrl(priv->ioaddr, mode); 1470 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1471 } else 1472 pr_info(" No MAC Management Counters available\n"); 1473 } 1474 1475 /** 1476 * stmmac_get_synopsys_id - return the SYINID. 1477 * @priv: driver private structure 1478 * Description: this simple function is to decode and return the SYINID 1479 * starting from the HW core register. 1480 */ 1481 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1482 { 1483 u32 hwid = priv->hw->synopsys_uid; 1484 1485 /* Check Synopsys Id (not available on old chips) */ 1486 if (likely(hwid)) { 1487 u32 uid = ((hwid & 0x0000ff00) >> 8); 1488 u32 synid = (hwid & 0x000000ff); 1489 1490 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1491 uid, synid); 1492 1493 return synid; 1494 } 1495 return 0; 1496 } 1497 1498 /** 1499 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1500 * @priv: driver private structure 1501 * Description: select the Enhanced/Alternate or Normal descriptors. 1502 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1503 * supported by the HW capability register. 1504 */ 1505 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1506 { 1507 if (priv->plat->enh_desc) { 1508 pr_info(" Enhanced/Alternate descriptors\n"); 1509 1510 /* GMAC older than 3.50 has no extended descriptors */ 1511 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1512 pr_info("\tEnabled extended descriptors\n"); 1513 priv->extend_desc = 1; 1514 } else 1515 pr_warn("Extended descriptors not supported\n"); 1516 1517 priv->hw->desc = &enh_desc_ops; 1518 } else { 1519 pr_info(" Normal descriptors\n"); 1520 priv->hw->desc = &ndesc_ops; 1521 } 1522 } 1523 1524 /** 1525 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1526 * @priv: driver private structure 1527 * Description: 1528 * new GMAC chip generations have a new register to indicate the 1529 * presence of the optional feature/functions. 1530 * This can be also used to override the value passed through the 1531 * platform and necessary for old MAC10/100 and GMAC chips. 1532 */ 1533 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1534 { 1535 u32 hw_cap = 0; 1536 1537 if (priv->hw->dma->get_hw_feature) { 1538 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1539 1540 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1541 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1542 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1543 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1544 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1545 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1546 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1547 priv->dma_cap.pmt_remote_wake_up = 1548 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1549 priv->dma_cap.pmt_magic_frame = 1550 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1551 /* MMC */ 1552 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1553 /* IEEE 1588-2002 */ 1554 priv->dma_cap.time_stamp = 1555 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1556 /* IEEE 1588-2008 */ 1557 priv->dma_cap.atime_stamp = 1558 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1559 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1560 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1561 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1562 /* TX and RX csum */ 1563 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1564 priv->dma_cap.rx_coe_type1 = 1565 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1566 priv->dma_cap.rx_coe_type2 = 1567 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1568 priv->dma_cap.rxfifo_over_2048 = 1569 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1570 /* TX and RX number of channels */ 1571 priv->dma_cap.number_rx_channel = 1572 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1573 priv->dma_cap.number_tx_channel = 1574 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1575 /* Alternate (enhanced) DESC mode */ 1576 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1577 } 1578 1579 return hw_cap; 1580 } 1581 1582 /** 1583 * stmmac_check_ether_addr - check if the MAC addr is valid 1584 * @priv: driver private structure 1585 * Description: 1586 * it is to verify if the MAC address is valid, in case of failures it 1587 * generates a random MAC address 1588 */ 1589 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1590 { 1591 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1592 priv->hw->mac->get_umac_addr(priv->hw, 1593 priv->dev->dev_addr, 0); 1594 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1595 eth_hw_addr_random(priv->dev); 1596 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1597 priv->dev->dev_addr); 1598 } 1599 } 1600 1601 /** 1602 * stmmac_init_dma_engine - DMA init. 1603 * @priv: driver private structure 1604 * Description: 1605 * It inits the DMA invoking the specific MAC/GMAC callback. 1606 * Some DMA parameters can be passed from the platform; 1607 * in case of these are not passed a default is kept for the MAC or GMAC. 1608 */ 1609 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1610 { 1611 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1612 int mixed_burst = 0; 1613 int atds = 0; 1614 1615 if (priv->plat->dma_cfg) { 1616 pbl = priv->plat->dma_cfg->pbl; 1617 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1618 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1619 burst_len = priv->plat->dma_cfg->burst_len; 1620 } 1621 1622 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1623 atds = 1; 1624 1625 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1626 burst_len, priv->dma_tx_phy, 1627 priv->dma_rx_phy, atds); 1628 } 1629 1630 /** 1631 * stmmac_tx_timer - mitigation sw timer for tx. 1632 * @data: data pointer 1633 * Description: 1634 * This is the timer handler to directly invoke the stmmac_tx_clean. 1635 */ 1636 static void stmmac_tx_timer(unsigned long data) 1637 { 1638 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1639 1640 stmmac_tx_clean(priv); 1641 } 1642 1643 /** 1644 * stmmac_init_tx_coalesce - init tx mitigation options. 1645 * @priv: driver private structure 1646 * Description: 1647 * This inits the transmit coalesce parameters: i.e. timer rate, 1648 * timer handler and default threshold used for enabling the 1649 * interrupt on completion bit. 1650 */ 1651 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1652 { 1653 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1654 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1655 init_timer(&priv->txtimer); 1656 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1657 priv->txtimer.data = (unsigned long)priv; 1658 priv->txtimer.function = stmmac_tx_timer; 1659 add_timer(&priv->txtimer); 1660 } 1661 1662 /** 1663 * stmmac_hw_setup - setup mac in a usable state. 1664 * @dev : pointer to the device structure. 1665 * Description: 1666 * this is the main function to setup the HW in a usable state because the 1667 * dma engine is reset, the core registers are configured (e.g. AXI, 1668 * Checksum features, timers). The DMA is ready to start receiving and 1669 * transmitting. 1670 * Return value: 1671 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1672 * file on failure. 1673 */ 1674 static int stmmac_hw_setup(struct net_device *dev) 1675 { 1676 struct stmmac_priv *priv = netdev_priv(dev); 1677 int ret; 1678 1679 /* DMA initialization and SW reset */ 1680 ret = stmmac_init_dma_engine(priv); 1681 if (ret < 0) { 1682 pr_err("%s: DMA engine initialization failed\n", __func__); 1683 return ret; 1684 } 1685 1686 /* Copy the MAC addr into the HW */ 1687 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1688 1689 /* If required, perform hw setup of the bus. */ 1690 if (priv->plat->bus_setup) 1691 priv->plat->bus_setup(priv->ioaddr); 1692 1693 /* Initialize the MAC Core */ 1694 priv->hw->mac->core_init(priv->hw, dev->mtu); 1695 1696 ret = priv->hw->mac->rx_ipc(priv->hw); 1697 if (!ret) { 1698 pr_warn(" RX IPC Checksum Offload disabled\n"); 1699 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1700 priv->hw->rx_csum = 0; 1701 } 1702 1703 /* Enable the MAC Rx/Tx */ 1704 stmmac_set_mac(priv->ioaddr, true); 1705 1706 /* Set the HW DMA mode and the COE */ 1707 stmmac_dma_operation_mode(priv); 1708 1709 stmmac_mmc_setup(priv); 1710 1711 ret = stmmac_init_ptp(priv); 1712 if (ret && ret != -EOPNOTSUPP) 1713 pr_warn("%s: failed PTP initialisation\n", __func__); 1714 1715 #ifdef CONFIG_DEBUG_FS 1716 ret = stmmac_init_fs(dev); 1717 if (ret < 0) 1718 pr_warn("%s: failed debugFS registration\n", __func__); 1719 #endif 1720 /* Start the ball rolling... */ 1721 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1722 priv->hw->dma->start_tx(priv->ioaddr); 1723 priv->hw->dma->start_rx(priv->ioaddr); 1724 1725 /* Dump DMA/MAC registers */ 1726 if (netif_msg_hw(priv)) { 1727 priv->hw->mac->dump_regs(priv->hw); 1728 priv->hw->dma->dump_regs(priv->ioaddr); 1729 } 1730 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1731 1732 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1733 priv->rx_riwt = MAX_DMA_RIWT; 1734 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1735 } 1736 1737 if (priv->pcs && priv->hw->mac->ctrl_ane) 1738 priv->hw->mac->ctrl_ane(priv->hw, 0); 1739 1740 return 0; 1741 } 1742 1743 /** 1744 * stmmac_open - open entry point of the driver 1745 * @dev : pointer to the device structure. 1746 * Description: 1747 * This function is the open entry point of the driver. 1748 * Return value: 1749 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1750 * file on failure. 1751 */ 1752 static int stmmac_open(struct net_device *dev) 1753 { 1754 struct stmmac_priv *priv = netdev_priv(dev); 1755 int ret; 1756 1757 stmmac_check_ether_addr(priv); 1758 1759 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1760 priv->pcs != STMMAC_PCS_RTBI) { 1761 ret = stmmac_init_phy(dev); 1762 if (ret) { 1763 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1764 __func__, ret); 1765 return ret; 1766 } 1767 } 1768 1769 /* Extra statistics */ 1770 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1771 priv->xstats.threshold = tc; 1772 1773 /* Create and initialize the TX/RX descriptors chains. */ 1774 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1775 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1776 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1777 1778 ret = alloc_dma_desc_resources(priv); 1779 if (ret < 0) { 1780 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1781 goto dma_desc_error; 1782 } 1783 1784 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1785 if (ret < 0) { 1786 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1787 goto init_error; 1788 } 1789 1790 ret = stmmac_hw_setup(dev); 1791 if (ret < 0) { 1792 pr_err("%s: Hw setup failed\n", __func__); 1793 goto init_error; 1794 } 1795 1796 stmmac_init_tx_coalesce(priv); 1797 1798 if (priv->phydev) 1799 phy_start(priv->phydev); 1800 1801 /* Request the IRQ lines */ 1802 ret = request_irq(dev->irq, stmmac_interrupt, 1803 IRQF_SHARED, dev->name, dev); 1804 if (unlikely(ret < 0)) { 1805 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1806 __func__, dev->irq, ret); 1807 goto init_error; 1808 } 1809 1810 /* Request the Wake IRQ in case of another line is used for WoL */ 1811 if (priv->wol_irq != dev->irq) { 1812 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1813 IRQF_SHARED, dev->name, dev); 1814 if (unlikely(ret < 0)) { 1815 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1816 __func__, priv->wol_irq, ret); 1817 goto wolirq_error; 1818 } 1819 } 1820 1821 /* Request the IRQ lines */ 1822 if (priv->lpi_irq > 0) { 1823 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1824 dev->name, dev); 1825 if (unlikely(ret < 0)) { 1826 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1827 __func__, priv->lpi_irq, ret); 1828 goto lpiirq_error; 1829 } 1830 } 1831 1832 napi_enable(&priv->napi); 1833 netif_start_queue(dev); 1834 1835 return 0; 1836 1837 lpiirq_error: 1838 if (priv->wol_irq != dev->irq) 1839 free_irq(priv->wol_irq, dev); 1840 wolirq_error: 1841 free_irq(dev->irq, dev); 1842 1843 init_error: 1844 free_dma_desc_resources(priv); 1845 dma_desc_error: 1846 if (priv->phydev) 1847 phy_disconnect(priv->phydev); 1848 1849 return ret; 1850 } 1851 1852 /** 1853 * stmmac_release - close entry point of the driver 1854 * @dev : device pointer. 1855 * Description: 1856 * This is the stop entry point of the driver. 1857 */ 1858 static int stmmac_release(struct net_device *dev) 1859 { 1860 struct stmmac_priv *priv = netdev_priv(dev); 1861 1862 if (priv->eee_enabled) 1863 del_timer_sync(&priv->eee_ctrl_timer); 1864 1865 /* Stop and disconnect the PHY */ 1866 if (priv->phydev) { 1867 phy_stop(priv->phydev); 1868 phy_disconnect(priv->phydev); 1869 priv->phydev = NULL; 1870 } 1871 1872 netif_stop_queue(dev); 1873 1874 napi_disable(&priv->napi); 1875 1876 del_timer_sync(&priv->txtimer); 1877 1878 /* Free the IRQ lines */ 1879 free_irq(dev->irq, dev); 1880 if (priv->wol_irq != dev->irq) 1881 free_irq(priv->wol_irq, dev); 1882 if (priv->lpi_irq > 0) 1883 free_irq(priv->lpi_irq, dev); 1884 1885 /* Stop TX/RX DMA and clear the descriptors */ 1886 priv->hw->dma->stop_tx(priv->ioaddr); 1887 priv->hw->dma->stop_rx(priv->ioaddr); 1888 1889 /* Release and free the Rx/Tx resources */ 1890 free_dma_desc_resources(priv); 1891 1892 /* Disable the MAC Rx/Tx */ 1893 stmmac_set_mac(priv->ioaddr, false); 1894 1895 netif_carrier_off(dev); 1896 1897 #ifdef CONFIG_DEBUG_FS 1898 stmmac_exit_fs(); 1899 #endif 1900 1901 stmmac_release_ptp(priv); 1902 1903 return 0; 1904 } 1905 1906 /** 1907 * stmmac_xmit - Tx entry point of the driver 1908 * @skb : the socket buffer 1909 * @dev : device pointer 1910 * Description : this is the tx entry point of the driver. 1911 * It programs the chain or the ring and supports oversized frames 1912 * and SG feature. 1913 */ 1914 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1915 { 1916 struct stmmac_priv *priv = netdev_priv(dev); 1917 unsigned int txsize = priv->dma_tx_size; 1918 unsigned int entry; 1919 int i, csum_insertion = 0, is_jumbo = 0; 1920 int nfrags = skb_shinfo(skb)->nr_frags; 1921 struct dma_desc *desc, *first; 1922 unsigned int nopaged_len = skb_headlen(skb); 1923 unsigned int enh_desc = priv->plat->enh_desc; 1924 1925 spin_lock(&priv->tx_lock); 1926 1927 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1928 spin_unlock(&priv->tx_lock); 1929 if (!netif_queue_stopped(dev)) { 1930 netif_stop_queue(dev); 1931 /* This is a hard error, log it. */ 1932 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1933 } 1934 return NETDEV_TX_BUSY; 1935 } 1936 1937 if (priv->tx_path_in_lpi_mode) 1938 stmmac_disable_eee_mode(priv); 1939 1940 entry = priv->cur_tx % txsize; 1941 1942 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1943 1944 if (priv->extend_desc) 1945 desc = (struct dma_desc *)(priv->dma_etx + entry); 1946 else 1947 desc = priv->dma_tx + entry; 1948 1949 first = desc; 1950 1951 /* To program the descriptors according to the size of the frame */ 1952 if (enh_desc) 1953 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 1954 1955 if (likely(!is_jumbo)) { 1956 desc->des2 = dma_map_single(priv->device, skb->data, 1957 nopaged_len, DMA_TO_DEVICE); 1958 if (dma_mapping_error(priv->device, desc->des2)) 1959 goto dma_map_err; 1960 priv->tx_skbuff_dma[entry].buf = desc->des2; 1961 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1962 csum_insertion, priv->mode); 1963 } else { 1964 desc = first; 1965 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 1966 if (unlikely(entry < 0)) 1967 goto dma_map_err; 1968 } 1969 1970 for (i = 0; i < nfrags; i++) { 1971 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1972 int len = skb_frag_size(frag); 1973 1974 priv->tx_skbuff[entry] = NULL; 1975 entry = (++priv->cur_tx) % txsize; 1976 if (priv->extend_desc) 1977 desc = (struct dma_desc *)(priv->dma_etx + entry); 1978 else 1979 desc = priv->dma_tx + entry; 1980 1981 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1982 DMA_TO_DEVICE); 1983 if (dma_mapping_error(priv->device, desc->des2)) 1984 goto dma_map_err; /* should reuse desc w/o issues */ 1985 1986 priv->tx_skbuff_dma[entry].buf = desc->des2; 1987 priv->tx_skbuff_dma[entry].map_as_page = true; 1988 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1989 priv->mode); 1990 wmb(); 1991 priv->hw->desc->set_tx_owner(desc); 1992 wmb(); 1993 } 1994 1995 priv->tx_skbuff[entry] = skb; 1996 1997 /* Finalize the latest segment. */ 1998 priv->hw->desc->close_tx_desc(desc); 1999 2000 wmb(); 2001 /* According to the coalesce parameter the IC bit for the latest 2002 * segment could be reset and the timer re-started to invoke the 2003 * stmmac_tx function. This approach takes care about the fragments. 2004 */ 2005 priv->tx_count_frames += nfrags + 1; 2006 if (priv->tx_coal_frames > priv->tx_count_frames) { 2007 priv->hw->desc->clear_tx_ic(desc); 2008 priv->xstats.tx_reset_ic_bit++; 2009 mod_timer(&priv->txtimer, 2010 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2011 } else 2012 priv->tx_count_frames = 0; 2013 2014 /* To avoid raise condition */ 2015 priv->hw->desc->set_tx_owner(first); 2016 wmb(); 2017 2018 priv->cur_tx++; 2019 2020 if (netif_msg_pktdata(priv)) { 2021 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 2022 __func__, (priv->cur_tx % txsize), 2023 (priv->dirty_tx % txsize), entry, first, nfrags); 2024 2025 if (priv->extend_desc) 2026 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 2027 else 2028 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 2029 2030 pr_debug(">>> frame to be transmitted: "); 2031 print_pkt(skb->data, skb->len); 2032 } 2033 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2034 if (netif_msg_hw(priv)) 2035 pr_debug("%s: stop transmitted packets\n", __func__); 2036 netif_stop_queue(dev); 2037 } 2038 2039 dev->stats.tx_bytes += skb->len; 2040 2041 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2042 priv->hwts_tx_en)) { 2043 /* declare that device is doing timestamping */ 2044 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2045 priv->hw->desc->enable_tx_timestamp(first); 2046 } 2047 2048 if (!priv->hwts_tx_en) 2049 skb_tx_timestamp(skb); 2050 2051 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2052 2053 spin_unlock(&priv->tx_lock); 2054 return NETDEV_TX_OK; 2055 2056 dma_map_err: 2057 spin_unlock(&priv->tx_lock); 2058 dev_err(priv->device, "Tx dma map failed\n"); 2059 dev_kfree_skb(skb); 2060 priv->dev->stats.tx_dropped++; 2061 return NETDEV_TX_OK; 2062 } 2063 2064 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2065 { 2066 struct ethhdr *ehdr; 2067 u16 vlanid; 2068 2069 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2070 NETIF_F_HW_VLAN_CTAG_RX && 2071 !__vlan_get_tag(skb, &vlanid)) { 2072 /* pop the vlan tag */ 2073 ehdr = (struct ethhdr *)skb->data; 2074 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2075 skb_pull(skb, VLAN_HLEN); 2076 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2077 } 2078 } 2079 2080 2081 /** 2082 * stmmac_rx_refill - refill used skb preallocated buffers 2083 * @priv: driver private structure 2084 * Description : this is to reallocate the skb for the reception process 2085 * that is based on zero-copy. 2086 */ 2087 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2088 { 2089 unsigned int rxsize = priv->dma_rx_size; 2090 int bfsize = priv->dma_buf_sz; 2091 2092 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2093 unsigned int entry = priv->dirty_rx % rxsize; 2094 struct dma_desc *p; 2095 2096 if (priv->extend_desc) 2097 p = (struct dma_desc *)(priv->dma_erx + entry); 2098 else 2099 p = priv->dma_rx + entry; 2100 2101 if (likely(priv->rx_skbuff[entry] == NULL)) { 2102 struct sk_buff *skb; 2103 2104 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2105 2106 if (unlikely(skb == NULL)) 2107 break; 2108 2109 priv->rx_skbuff[entry] = skb; 2110 priv->rx_skbuff_dma[entry] = 2111 dma_map_single(priv->device, skb->data, bfsize, 2112 DMA_FROM_DEVICE); 2113 if (dma_mapping_error(priv->device, 2114 priv->rx_skbuff_dma[entry])) { 2115 dev_err(priv->device, "Rx dma map failed\n"); 2116 dev_kfree_skb(skb); 2117 break; 2118 } 2119 p->des2 = priv->rx_skbuff_dma[entry]; 2120 2121 priv->hw->mode->refill_desc3(priv, p); 2122 2123 if (netif_msg_rx_status(priv)) 2124 pr_debug("\trefill entry #%d\n", entry); 2125 } 2126 wmb(); 2127 priv->hw->desc->set_rx_owner(p); 2128 wmb(); 2129 } 2130 } 2131 2132 /** 2133 * stmmac_rx - manage the receive process 2134 * @priv: driver private structure 2135 * @limit: napi bugget. 2136 * Description : this the function called by the napi poll method. 2137 * It gets all the frames inside the ring. 2138 */ 2139 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2140 { 2141 unsigned int rxsize = priv->dma_rx_size; 2142 unsigned int entry = priv->cur_rx % rxsize; 2143 unsigned int next_entry; 2144 unsigned int count = 0; 2145 int coe = priv->hw->rx_csum; 2146 2147 if (netif_msg_rx_status(priv)) { 2148 pr_debug("%s: descriptor ring:\n", __func__); 2149 if (priv->extend_desc) 2150 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2151 else 2152 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2153 } 2154 while (count < limit) { 2155 int status; 2156 struct dma_desc *p; 2157 2158 if (priv->extend_desc) 2159 p = (struct dma_desc *)(priv->dma_erx + entry); 2160 else 2161 p = priv->dma_rx + entry; 2162 2163 if (priv->hw->desc->get_rx_owner(p)) 2164 break; 2165 2166 count++; 2167 2168 next_entry = (++priv->cur_rx) % rxsize; 2169 if (priv->extend_desc) 2170 prefetch(priv->dma_erx + next_entry); 2171 else 2172 prefetch(priv->dma_rx + next_entry); 2173 2174 /* read the status of the incoming frame */ 2175 status = priv->hw->desc->rx_status(&priv->dev->stats, 2176 &priv->xstats, p); 2177 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2178 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2179 &priv->xstats, 2180 priv->dma_erx + 2181 entry); 2182 if (unlikely(status == discard_frame)) { 2183 priv->dev->stats.rx_errors++; 2184 if (priv->hwts_rx_en && !priv->extend_desc) { 2185 /* DESC2 & DESC3 will be overwitten by device 2186 * with timestamp value, hence reinitialize 2187 * them in stmmac_rx_refill() function so that 2188 * device can reuse it. 2189 */ 2190 priv->rx_skbuff[entry] = NULL; 2191 dma_unmap_single(priv->device, 2192 priv->rx_skbuff_dma[entry], 2193 priv->dma_buf_sz, 2194 DMA_FROM_DEVICE); 2195 } 2196 } else { 2197 struct sk_buff *skb; 2198 int frame_len; 2199 2200 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2201 2202 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2203 * Type frames (LLC/LLC-SNAP) 2204 */ 2205 if (unlikely(status != llc_snap)) 2206 frame_len -= ETH_FCS_LEN; 2207 2208 if (netif_msg_rx_status(priv)) { 2209 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2210 p, entry, p->des2); 2211 if (frame_len > ETH_FRAME_LEN) 2212 pr_debug("\tframe size %d, COE: %d\n", 2213 frame_len, status); 2214 } 2215 skb = priv->rx_skbuff[entry]; 2216 if (unlikely(!skb)) { 2217 pr_err("%s: Inconsistent Rx descriptor chain\n", 2218 priv->dev->name); 2219 priv->dev->stats.rx_dropped++; 2220 break; 2221 } 2222 prefetch(skb->data - NET_IP_ALIGN); 2223 priv->rx_skbuff[entry] = NULL; 2224 2225 stmmac_get_rx_hwtstamp(priv, entry, skb); 2226 2227 skb_put(skb, frame_len); 2228 dma_unmap_single(priv->device, 2229 priv->rx_skbuff_dma[entry], 2230 priv->dma_buf_sz, DMA_FROM_DEVICE); 2231 2232 if (netif_msg_pktdata(priv)) { 2233 pr_debug("frame received (%dbytes)", frame_len); 2234 print_pkt(skb->data, frame_len); 2235 } 2236 2237 stmmac_rx_vlan(priv->dev, skb); 2238 2239 skb->protocol = eth_type_trans(skb, priv->dev); 2240 2241 if (unlikely(!coe)) 2242 skb_checksum_none_assert(skb); 2243 else 2244 skb->ip_summed = CHECKSUM_UNNECESSARY; 2245 2246 napi_gro_receive(&priv->napi, skb); 2247 2248 priv->dev->stats.rx_packets++; 2249 priv->dev->stats.rx_bytes += frame_len; 2250 } 2251 entry = next_entry; 2252 } 2253 2254 stmmac_rx_refill(priv); 2255 2256 priv->xstats.rx_pkt_n += count; 2257 2258 return count; 2259 } 2260 2261 /** 2262 * stmmac_poll - stmmac poll method (NAPI) 2263 * @napi : pointer to the napi structure. 2264 * @budget : maximum number of packets that the current CPU can receive from 2265 * all interfaces. 2266 * Description : 2267 * To look at the incoming frames and clear the tx resources. 2268 */ 2269 static int stmmac_poll(struct napi_struct *napi, int budget) 2270 { 2271 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2272 int work_done = 0; 2273 2274 priv->xstats.napi_poll++; 2275 stmmac_tx_clean(priv); 2276 2277 work_done = stmmac_rx(priv, budget); 2278 if (work_done < budget) { 2279 napi_complete(napi); 2280 stmmac_enable_dma_irq(priv); 2281 } 2282 return work_done; 2283 } 2284 2285 /** 2286 * stmmac_tx_timeout 2287 * @dev : Pointer to net device structure 2288 * Description: this function is called when a packet transmission fails to 2289 * complete within a reasonable time. The driver will mark the error in the 2290 * netdev structure and arrange for the device to be reset to a sane state 2291 * in order to transmit a new packet. 2292 */ 2293 static void stmmac_tx_timeout(struct net_device *dev) 2294 { 2295 struct stmmac_priv *priv = netdev_priv(dev); 2296 2297 /* Clear Tx resources and restart transmitting again */ 2298 stmmac_tx_err(priv); 2299 } 2300 2301 /** 2302 * stmmac_set_rx_mode - entry point for multicast addressing 2303 * @dev : pointer to the device structure 2304 * Description: 2305 * This function is a driver entry point which gets called by the kernel 2306 * whenever multicast addresses must be enabled/disabled. 2307 * Return value: 2308 * void. 2309 */ 2310 static void stmmac_set_rx_mode(struct net_device *dev) 2311 { 2312 struct stmmac_priv *priv = netdev_priv(dev); 2313 2314 priv->hw->mac->set_filter(priv->hw, dev); 2315 } 2316 2317 /** 2318 * stmmac_change_mtu - entry point to change MTU size for the device. 2319 * @dev : device pointer. 2320 * @new_mtu : the new MTU size for the device. 2321 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2322 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2323 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2324 * Return value: 2325 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2326 * file on failure. 2327 */ 2328 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2329 { 2330 struct stmmac_priv *priv = netdev_priv(dev); 2331 int max_mtu; 2332 2333 if (netif_running(dev)) { 2334 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2335 return -EBUSY; 2336 } 2337 2338 if (priv->plat->enh_desc) 2339 max_mtu = JUMBO_LEN; 2340 else 2341 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2342 2343 if (priv->plat->maxmtu < max_mtu) 2344 max_mtu = priv->plat->maxmtu; 2345 2346 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2347 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2348 return -EINVAL; 2349 } 2350 2351 dev->mtu = new_mtu; 2352 netdev_update_features(dev); 2353 2354 return 0; 2355 } 2356 2357 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2358 netdev_features_t features) 2359 { 2360 struct stmmac_priv *priv = netdev_priv(dev); 2361 2362 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2363 features &= ~NETIF_F_RXCSUM; 2364 2365 if (!priv->plat->tx_coe) 2366 features &= ~NETIF_F_ALL_CSUM; 2367 2368 /* Some GMAC devices have a bugged Jumbo frame support that 2369 * needs to have the Tx COE disabled for oversized frames 2370 * (due to limited buffer sizes). In this case we disable 2371 * the TX csum insertionin the TDES and not use SF. 2372 */ 2373 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2374 features &= ~NETIF_F_ALL_CSUM; 2375 2376 return features; 2377 } 2378 2379 static int stmmac_set_features(struct net_device *netdev, 2380 netdev_features_t features) 2381 { 2382 struct stmmac_priv *priv = netdev_priv(netdev); 2383 2384 /* Keep the COE Type in case of csum is supporting */ 2385 if (features & NETIF_F_RXCSUM) 2386 priv->hw->rx_csum = priv->plat->rx_coe; 2387 else 2388 priv->hw->rx_csum = 0; 2389 /* No check needed because rx_coe has been set before and it will be 2390 * fixed in case of issue. 2391 */ 2392 priv->hw->mac->rx_ipc(priv->hw); 2393 2394 return 0; 2395 } 2396 2397 /** 2398 * stmmac_interrupt - main ISR 2399 * @irq: interrupt number. 2400 * @dev_id: to pass the net device pointer. 2401 * Description: this is the main driver interrupt service routine. 2402 * It can call: 2403 * o DMA service routine (to manage incoming frame reception and transmission 2404 * status) 2405 * o Core interrupts to manage: remote wake-up, management counter, LPI 2406 * interrupts. 2407 */ 2408 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2409 { 2410 struct net_device *dev = (struct net_device *)dev_id; 2411 struct stmmac_priv *priv = netdev_priv(dev); 2412 2413 if (priv->irq_wake) 2414 pm_wakeup_event(priv->device, 0); 2415 2416 if (unlikely(!dev)) { 2417 pr_err("%s: invalid dev pointer\n", __func__); 2418 return IRQ_NONE; 2419 } 2420 2421 /* To handle GMAC own interrupts */ 2422 if (priv->plat->has_gmac) { 2423 int status = priv->hw->mac->host_irq_status(priv->hw, 2424 &priv->xstats); 2425 if (unlikely(status)) { 2426 /* For LPI we need to save the tx status */ 2427 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2428 priv->tx_path_in_lpi_mode = true; 2429 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2430 priv->tx_path_in_lpi_mode = false; 2431 } 2432 } 2433 2434 /* To handle DMA interrupts */ 2435 stmmac_dma_interrupt(priv); 2436 2437 return IRQ_HANDLED; 2438 } 2439 2440 #ifdef CONFIG_NET_POLL_CONTROLLER 2441 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2442 * to allow network I/O with interrupts disabled. 2443 */ 2444 static void stmmac_poll_controller(struct net_device *dev) 2445 { 2446 disable_irq(dev->irq); 2447 stmmac_interrupt(dev->irq, dev); 2448 enable_irq(dev->irq); 2449 } 2450 #endif 2451 2452 /** 2453 * stmmac_ioctl - Entry point for the Ioctl 2454 * @dev: Device pointer. 2455 * @rq: An IOCTL specefic structure, that can contain a pointer to 2456 * a proprietary structure used to pass information to the driver. 2457 * @cmd: IOCTL command 2458 * Description: 2459 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2460 */ 2461 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2462 { 2463 struct stmmac_priv *priv = netdev_priv(dev); 2464 int ret = -EOPNOTSUPP; 2465 2466 if (!netif_running(dev)) 2467 return -EINVAL; 2468 2469 switch (cmd) { 2470 case SIOCGMIIPHY: 2471 case SIOCGMIIREG: 2472 case SIOCSMIIREG: 2473 if (!priv->phydev) 2474 return -EINVAL; 2475 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2476 break; 2477 case SIOCSHWTSTAMP: 2478 ret = stmmac_hwtstamp_ioctl(dev, rq); 2479 break; 2480 default: 2481 break; 2482 } 2483 2484 return ret; 2485 } 2486 2487 #ifdef CONFIG_DEBUG_FS 2488 static struct dentry *stmmac_fs_dir; 2489 static struct dentry *stmmac_rings_status; 2490 static struct dentry *stmmac_dma_cap; 2491 2492 static void sysfs_display_ring(void *head, int size, int extend_desc, 2493 struct seq_file *seq) 2494 { 2495 int i; 2496 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2497 struct dma_desc *p = (struct dma_desc *)head; 2498 2499 for (i = 0; i < size; i++) { 2500 u64 x; 2501 if (extend_desc) { 2502 x = *(u64 *) ep; 2503 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2504 i, (unsigned int)virt_to_phys(ep), 2505 (unsigned int)x, (unsigned int)(x >> 32), 2506 ep->basic.des2, ep->basic.des3); 2507 ep++; 2508 } else { 2509 x = *(u64 *) p; 2510 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2511 i, (unsigned int)virt_to_phys(ep), 2512 (unsigned int)x, (unsigned int)(x >> 32), 2513 p->des2, p->des3); 2514 p++; 2515 } 2516 seq_printf(seq, "\n"); 2517 } 2518 } 2519 2520 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2521 { 2522 struct net_device *dev = seq->private; 2523 struct stmmac_priv *priv = netdev_priv(dev); 2524 unsigned int txsize = priv->dma_tx_size; 2525 unsigned int rxsize = priv->dma_rx_size; 2526 2527 if (priv->extend_desc) { 2528 seq_printf(seq, "Extended RX descriptor ring:\n"); 2529 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2530 seq_printf(seq, "Extended TX descriptor ring:\n"); 2531 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2532 } else { 2533 seq_printf(seq, "RX descriptor ring:\n"); 2534 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2535 seq_printf(seq, "TX descriptor ring:\n"); 2536 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2537 } 2538 2539 return 0; 2540 } 2541 2542 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2543 { 2544 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2545 } 2546 2547 static const struct file_operations stmmac_rings_status_fops = { 2548 .owner = THIS_MODULE, 2549 .open = stmmac_sysfs_ring_open, 2550 .read = seq_read, 2551 .llseek = seq_lseek, 2552 .release = single_release, 2553 }; 2554 2555 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2556 { 2557 struct net_device *dev = seq->private; 2558 struct stmmac_priv *priv = netdev_priv(dev); 2559 2560 if (!priv->hw_cap_support) { 2561 seq_printf(seq, "DMA HW features not supported\n"); 2562 return 0; 2563 } 2564 2565 seq_printf(seq, "==============================\n"); 2566 seq_printf(seq, "\tDMA HW features\n"); 2567 seq_printf(seq, "==============================\n"); 2568 2569 seq_printf(seq, "\t10/100 Mbps %s\n", 2570 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2571 seq_printf(seq, "\t1000 Mbps %s\n", 2572 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2573 seq_printf(seq, "\tHalf duple %s\n", 2574 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2575 seq_printf(seq, "\tHash Filter: %s\n", 2576 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2577 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2578 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2579 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2580 (priv->dma_cap.pcs) ? "Y" : "N"); 2581 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2582 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2583 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2584 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2585 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2586 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2587 seq_printf(seq, "\tRMON module: %s\n", 2588 (priv->dma_cap.rmon) ? "Y" : "N"); 2589 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2590 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2591 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2592 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2593 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2594 (priv->dma_cap.eee) ? "Y" : "N"); 2595 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2596 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2597 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2598 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2599 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2600 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2601 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2602 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2603 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2604 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2605 priv->dma_cap.number_rx_channel); 2606 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2607 priv->dma_cap.number_tx_channel); 2608 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2609 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2610 2611 return 0; 2612 } 2613 2614 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2615 { 2616 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2617 } 2618 2619 static const struct file_operations stmmac_dma_cap_fops = { 2620 .owner = THIS_MODULE, 2621 .open = stmmac_sysfs_dma_cap_open, 2622 .read = seq_read, 2623 .llseek = seq_lseek, 2624 .release = single_release, 2625 }; 2626 2627 static int stmmac_init_fs(struct net_device *dev) 2628 { 2629 /* Create debugfs entries */ 2630 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2631 2632 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2633 pr_err("ERROR %s, debugfs create directory failed\n", 2634 STMMAC_RESOURCE_NAME); 2635 2636 return -ENOMEM; 2637 } 2638 2639 /* Entry to report DMA RX/TX rings */ 2640 stmmac_rings_status = debugfs_create_file("descriptors_status", 2641 S_IRUGO, stmmac_fs_dir, dev, 2642 &stmmac_rings_status_fops); 2643 2644 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2645 pr_info("ERROR creating stmmac ring debugfs file\n"); 2646 debugfs_remove(stmmac_fs_dir); 2647 2648 return -ENOMEM; 2649 } 2650 2651 /* Entry to report the DMA HW features */ 2652 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2653 dev, &stmmac_dma_cap_fops); 2654 2655 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2656 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2657 debugfs_remove(stmmac_rings_status); 2658 debugfs_remove(stmmac_fs_dir); 2659 2660 return -ENOMEM; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static void stmmac_exit_fs(void) 2667 { 2668 debugfs_remove(stmmac_rings_status); 2669 debugfs_remove(stmmac_dma_cap); 2670 debugfs_remove(stmmac_fs_dir); 2671 } 2672 #endif /* CONFIG_DEBUG_FS */ 2673 2674 static const struct net_device_ops stmmac_netdev_ops = { 2675 .ndo_open = stmmac_open, 2676 .ndo_start_xmit = stmmac_xmit, 2677 .ndo_stop = stmmac_release, 2678 .ndo_change_mtu = stmmac_change_mtu, 2679 .ndo_fix_features = stmmac_fix_features, 2680 .ndo_set_features = stmmac_set_features, 2681 .ndo_set_rx_mode = stmmac_set_rx_mode, 2682 .ndo_tx_timeout = stmmac_tx_timeout, 2683 .ndo_do_ioctl = stmmac_ioctl, 2684 #ifdef CONFIG_NET_POLL_CONTROLLER 2685 .ndo_poll_controller = stmmac_poll_controller, 2686 #endif 2687 .ndo_set_mac_address = eth_mac_addr, 2688 }; 2689 2690 /** 2691 * stmmac_hw_init - Init the MAC device 2692 * @priv: driver private structure 2693 * Description: this function is to configure the MAC device according to 2694 * some platform parameters or the HW capability register. It prepares the 2695 * driver to use either ring or chain modes and to setup either enhanced or 2696 * normal descriptors. 2697 */ 2698 static int stmmac_hw_init(struct stmmac_priv *priv) 2699 { 2700 struct mac_device_info *mac; 2701 2702 /* Identify the MAC HW device */ 2703 if (priv->plat->has_gmac) { 2704 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2705 mac = dwmac1000_setup(priv->ioaddr, 2706 priv->plat->multicast_filter_bins, 2707 priv->plat->unicast_filter_entries); 2708 } else { 2709 mac = dwmac100_setup(priv->ioaddr); 2710 } 2711 if (!mac) 2712 return -ENOMEM; 2713 2714 priv->hw = mac; 2715 2716 /* Get and dump the chip ID */ 2717 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2718 2719 /* To use the chained or ring mode */ 2720 if (chain_mode) { 2721 priv->hw->mode = &chain_mode_ops; 2722 pr_info(" Chain mode enabled\n"); 2723 priv->mode = STMMAC_CHAIN_MODE; 2724 } else { 2725 priv->hw->mode = &ring_mode_ops; 2726 pr_info(" Ring mode enabled\n"); 2727 priv->mode = STMMAC_RING_MODE; 2728 } 2729 2730 /* Get the HW capability (new GMAC newer than 3.50a) */ 2731 priv->hw_cap_support = stmmac_get_hw_features(priv); 2732 if (priv->hw_cap_support) { 2733 pr_info(" DMA HW capability register supported"); 2734 2735 /* We can override some gmac/dma configuration fields: e.g. 2736 * enh_desc, tx_coe (e.g. that are passed through the 2737 * platform) with the values from the HW capability 2738 * register (if supported). 2739 */ 2740 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2741 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2742 2743 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2744 2745 if (priv->dma_cap.rx_coe_type2) 2746 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2747 else if (priv->dma_cap.rx_coe_type1) 2748 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2749 2750 } else 2751 pr_info(" No HW DMA feature register supported"); 2752 2753 /* To use alternate (extended) or normal descriptor structures */ 2754 stmmac_selec_desc_mode(priv); 2755 2756 if (priv->plat->rx_coe) { 2757 priv->hw->rx_csum = priv->plat->rx_coe; 2758 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2759 priv->plat->rx_coe); 2760 } 2761 if (priv->plat->tx_coe) 2762 pr_info(" TX Checksum insertion supported\n"); 2763 2764 if (priv->plat->pmt) { 2765 pr_info(" Wake-Up On Lan supported\n"); 2766 device_set_wakeup_capable(priv->device, 1); 2767 } 2768 2769 return 0; 2770 } 2771 2772 /** 2773 * stmmac_dvr_probe 2774 * @device: device pointer 2775 * @plat_dat: platform data pointer 2776 * @addr: iobase memory address 2777 * Description: this is the main probe function used to 2778 * call the alloc_etherdev, allocate the priv structure. 2779 */ 2780 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2781 struct plat_stmmacenet_data *plat_dat, 2782 void __iomem *addr) 2783 { 2784 int ret = 0; 2785 struct net_device *ndev = NULL; 2786 struct stmmac_priv *priv; 2787 2788 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2789 if (!ndev) 2790 return NULL; 2791 2792 SET_NETDEV_DEV(ndev, device); 2793 2794 priv = netdev_priv(ndev); 2795 priv->device = device; 2796 priv->dev = ndev; 2797 2798 stmmac_set_ethtool_ops(ndev); 2799 priv->pause = pause; 2800 priv->plat = plat_dat; 2801 priv->ioaddr = addr; 2802 priv->dev->base_addr = (unsigned long)addr; 2803 2804 /* Verify driver arguments */ 2805 stmmac_verify_args(); 2806 2807 /* Override with kernel parameters if supplied XXX CRS XXX 2808 * this needs to have multiple instances 2809 */ 2810 if ((phyaddr >= 0) && (phyaddr <= 31)) 2811 priv->plat->phy_addr = phyaddr; 2812 2813 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2814 if (IS_ERR(priv->stmmac_clk)) { 2815 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2816 __func__); 2817 /* If failed to obtain stmmac_clk and specific clk_csr value 2818 * is NOT passed from the platform, probe fail. 2819 */ 2820 if (!priv->plat->clk_csr) { 2821 ret = PTR_ERR(priv->stmmac_clk); 2822 goto error_clk_get; 2823 } else { 2824 priv->stmmac_clk = NULL; 2825 } 2826 } 2827 clk_prepare_enable(priv->stmmac_clk); 2828 2829 priv->stmmac_rst = devm_reset_control_get(priv->device, 2830 STMMAC_RESOURCE_NAME); 2831 if (IS_ERR(priv->stmmac_rst)) { 2832 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2833 ret = -EPROBE_DEFER; 2834 goto error_hw_init; 2835 } 2836 dev_info(priv->device, "no reset control found\n"); 2837 priv->stmmac_rst = NULL; 2838 } 2839 if (priv->stmmac_rst) 2840 reset_control_deassert(priv->stmmac_rst); 2841 2842 /* Init MAC and get the capabilities */ 2843 ret = stmmac_hw_init(priv); 2844 if (ret) 2845 goto error_hw_init; 2846 2847 ndev->netdev_ops = &stmmac_netdev_ops; 2848 2849 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2850 NETIF_F_RXCSUM; 2851 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2852 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2853 #ifdef STMMAC_VLAN_TAG_USED 2854 /* Both mac100 and gmac support receive VLAN tag detection */ 2855 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2856 #endif 2857 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2858 2859 if (flow_ctrl) 2860 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2861 2862 /* Rx Watchdog is available in the COREs newer than the 3.40. 2863 * In some case, for example on bugged HW this feature 2864 * has to be disable and this can be done by passing the 2865 * riwt_off field from the platform. 2866 */ 2867 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2868 priv->use_riwt = 1; 2869 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2870 } 2871 2872 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2873 2874 spin_lock_init(&priv->lock); 2875 spin_lock_init(&priv->tx_lock); 2876 2877 ret = register_netdev(ndev); 2878 if (ret) { 2879 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2880 goto error_netdev_register; 2881 } 2882 2883 /* If a specific clk_csr value is passed from the platform 2884 * this means that the CSR Clock Range selection cannot be 2885 * changed at run-time and it is fixed. Viceversa the driver'll try to 2886 * set the MDC clock dynamically according to the csr actual 2887 * clock input. 2888 */ 2889 if (!priv->plat->clk_csr) 2890 stmmac_clk_csr_set(priv); 2891 else 2892 priv->clk_csr = priv->plat->clk_csr; 2893 2894 stmmac_check_pcs_mode(priv); 2895 2896 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2897 priv->pcs != STMMAC_PCS_RTBI) { 2898 /* MDIO bus Registration */ 2899 ret = stmmac_mdio_register(ndev); 2900 if (ret < 0) { 2901 pr_debug("%s: MDIO bus (id: %d) registration failed", 2902 __func__, priv->plat->bus_id); 2903 goto error_mdio_register; 2904 } 2905 } 2906 2907 return priv; 2908 2909 error_mdio_register: 2910 unregister_netdev(ndev); 2911 error_netdev_register: 2912 netif_napi_del(&priv->napi); 2913 error_hw_init: 2914 clk_disable_unprepare(priv->stmmac_clk); 2915 error_clk_get: 2916 free_netdev(ndev); 2917 2918 return ERR_PTR(ret); 2919 } 2920 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 2921 2922 /** 2923 * stmmac_dvr_remove 2924 * @ndev: net device pointer 2925 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2926 * changes the link status, releases the DMA descriptor rings. 2927 */ 2928 int stmmac_dvr_remove(struct net_device *ndev) 2929 { 2930 struct stmmac_priv *priv = netdev_priv(ndev); 2931 2932 pr_info("%s:\n\tremoving driver", __func__); 2933 2934 priv->hw->dma->stop_rx(priv->ioaddr); 2935 priv->hw->dma->stop_tx(priv->ioaddr); 2936 2937 stmmac_set_mac(priv->ioaddr, false); 2938 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2939 priv->pcs != STMMAC_PCS_RTBI) 2940 stmmac_mdio_unregister(ndev); 2941 netif_carrier_off(ndev); 2942 unregister_netdev(ndev); 2943 if (priv->stmmac_rst) 2944 reset_control_assert(priv->stmmac_rst); 2945 clk_disable_unprepare(priv->stmmac_clk); 2946 free_netdev(ndev); 2947 2948 return 0; 2949 } 2950 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 2951 2952 /** 2953 * stmmac_suspend - suspend callback 2954 * @ndev: net device pointer 2955 * Description: this is the function to suspend the device and it is called 2956 * by the platform driver to stop the network queue, release the resources, 2957 * program the PMT register (for WoL), clean and release driver resources. 2958 */ 2959 int stmmac_suspend(struct net_device *ndev) 2960 { 2961 struct stmmac_priv *priv = netdev_priv(ndev); 2962 unsigned long flags; 2963 2964 if (!ndev || !netif_running(ndev)) 2965 return 0; 2966 2967 if (priv->phydev) 2968 phy_stop(priv->phydev); 2969 2970 spin_lock_irqsave(&priv->lock, flags); 2971 2972 netif_device_detach(ndev); 2973 netif_stop_queue(ndev); 2974 2975 napi_disable(&priv->napi); 2976 2977 /* Stop TX/RX DMA */ 2978 priv->hw->dma->stop_tx(priv->ioaddr); 2979 priv->hw->dma->stop_rx(priv->ioaddr); 2980 2981 stmmac_clear_descriptors(priv); 2982 2983 /* Enable Power down mode by programming the PMT regs */ 2984 if (device_may_wakeup(priv->device)) { 2985 priv->hw->mac->pmt(priv->hw, priv->wolopts); 2986 priv->irq_wake = 1; 2987 } else { 2988 stmmac_set_mac(priv->ioaddr, false); 2989 pinctrl_pm_select_sleep_state(priv->device); 2990 /* Disable clock in case of PWM is off */ 2991 clk_disable(priv->stmmac_clk); 2992 } 2993 spin_unlock_irqrestore(&priv->lock, flags); 2994 2995 priv->oldlink = 0; 2996 priv->speed = 0; 2997 priv->oldduplex = -1; 2998 return 0; 2999 } 3000 EXPORT_SYMBOL_GPL(stmmac_suspend); 3001 3002 /** 3003 * stmmac_resume - resume callback 3004 * @ndev: net device pointer 3005 * Description: when resume this function is invoked to setup the DMA and CORE 3006 * in a usable state. 3007 */ 3008 int stmmac_resume(struct net_device *ndev) 3009 { 3010 struct stmmac_priv *priv = netdev_priv(ndev); 3011 unsigned long flags; 3012 3013 if (!netif_running(ndev)) 3014 return 0; 3015 3016 spin_lock_irqsave(&priv->lock, flags); 3017 3018 /* Power Down bit, into the PM register, is cleared 3019 * automatically as soon as a magic packet or a Wake-up frame 3020 * is received. Anyway, it's better to manually clear 3021 * this bit because it can generate problems while resuming 3022 * from another devices (e.g. serial console). 3023 */ 3024 if (device_may_wakeup(priv->device)) { 3025 priv->hw->mac->pmt(priv->hw, 0); 3026 priv->irq_wake = 0; 3027 } else { 3028 pinctrl_pm_select_default_state(priv->device); 3029 /* enable the clk prevously disabled */ 3030 clk_enable(priv->stmmac_clk); 3031 /* reset the phy so that it's ready */ 3032 if (priv->mii) 3033 stmmac_mdio_reset(priv->mii); 3034 } 3035 3036 netif_device_attach(ndev); 3037 3038 init_dma_desc_rings(ndev, GFP_ATOMIC); 3039 stmmac_hw_setup(ndev); 3040 stmmac_init_tx_coalesce(priv); 3041 3042 napi_enable(&priv->napi); 3043 3044 netif_start_queue(ndev); 3045 3046 spin_unlock_irqrestore(&priv->lock, flags); 3047 3048 if (priv->phydev) 3049 phy_start(priv->phydev); 3050 3051 return 0; 3052 } 3053 EXPORT_SYMBOL_GPL(stmmac_resume); 3054 3055 #ifndef MODULE 3056 static int __init stmmac_cmdline_opt(char *str) 3057 { 3058 char *opt; 3059 3060 if (!str || !*str) 3061 return -EINVAL; 3062 while ((opt = strsep(&str, ",")) != NULL) { 3063 if (!strncmp(opt, "debug:", 6)) { 3064 if (kstrtoint(opt + 6, 0, &debug)) 3065 goto err; 3066 } else if (!strncmp(opt, "phyaddr:", 8)) { 3067 if (kstrtoint(opt + 8, 0, &phyaddr)) 3068 goto err; 3069 } else if (!strncmp(opt, "dma_txsize:", 11)) { 3070 if (kstrtoint(opt + 11, 0, &dma_txsize)) 3071 goto err; 3072 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 3073 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 3074 goto err; 3075 } else if (!strncmp(opt, "buf_sz:", 7)) { 3076 if (kstrtoint(opt + 7, 0, &buf_sz)) 3077 goto err; 3078 } else if (!strncmp(opt, "tc:", 3)) { 3079 if (kstrtoint(opt + 3, 0, &tc)) 3080 goto err; 3081 } else if (!strncmp(opt, "watchdog:", 9)) { 3082 if (kstrtoint(opt + 9, 0, &watchdog)) 3083 goto err; 3084 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3085 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3086 goto err; 3087 } else if (!strncmp(opt, "pause:", 6)) { 3088 if (kstrtoint(opt + 6, 0, &pause)) 3089 goto err; 3090 } else if (!strncmp(opt, "eee_timer:", 10)) { 3091 if (kstrtoint(opt + 10, 0, &eee_timer)) 3092 goto err; 3093 } else if (!strncmp(opt, "chain_mode:", 11)) { 3094 if (kstrtoint(opt + 11, 0, &chain_mode)) 3095 goto err; 3096 } 3097 } 3098 return 0; 3099 3100 err: 3101 pr_err("%s: ERROR broken module parameter conversion", __func__); 3102 return -EINVAL; 3103 } 3104 3105 __setup("stmmaceth=", stmmac_cmdline_opt); 3106 #endif /* MODULE */ 3107 3108 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3109 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3110 MODULE_LICENSE("GPL"); 3111