1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 /** 180 * stmmac_stop_all_queues - Stop all queues 181 * @priv: driver private structure 182 */ 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 184 { 185 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 186 u32 queue; 187 188 for (queue = 0; queue < tx_queues_cnt; queue++) 189 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 190 } 191 192 /** 193 * stmmac_start_all_queues - Start all queues 194 * @priv: driver private structure 195 */ 196 static void stmmac_start_all_queues(struct stmmac_priv *priv) 197 { 198 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 199 u32 queue; 200 201 for (queue = 0; queue < tx_queues_cnt; queue++) 202 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 203 } 204 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 206 { 207 if (!test_bit(STMMAC_DOWN, &priv->state) && 208 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 209 queue_work(priv->wq, &priv->service_task); 210 } 211 212 static void stmmac_global_err(struct stmmac_priv *priv) 213 { 214 netif_carrier_off(priv->dev); 215 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 216 stmmac_service_event_schedule(priv); 217 } 218 219 /** 220 * stmmac_clk_csr_set - dynamically set the MDC clock 221 * @priv: driver private structure 222 * Description: this is to dynamically set the MDC clock according to the csr 223 * clock input. 224 * Note: 225 * If a specific clk_csr value is passed from the platform 226 * this means that the CSR Clock Range selection cannot be 227 * changed at run-time and it is fixed (as reported in the driver 228 * documentation). Viceversa the driver will try to set the MDC 229 * clock dynamically according to the actual clock input. 230 */ 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 232 { 233 u32 clk_rate; 234 235 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 236 237 /* Platform provided default clk_csr would be assumed valid 238 * for all other cases except for the below mentioned ones. 239 * For values higher than the IEEE 802.3 specified frequency 240 * we can not estimate the proper divider as it is not known 241 * the frequency of clk_csr_i. So we do not change the default 242 * divider. 243 */ 244 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 245 if (clk_rate < CSR_F_35M) 246 priv->clk_csr = STMMAC_CSR_20_35M; 247 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 248 priv->clk_csr = STMMAC_CSR_35_60M; 249 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 250 priv->clk_csr = STMMAC_CSR_60_100M; 251 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 252 priv->clk_csr = STMMAC_CSR_100_150M; 253 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 254 priv->clk_csr = STMMAC_CSR_150_250M; 255 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 256 priv->clk_csr = STMMAC_CSR_250_300M; 257 } 258 259 if (priv->plat->has_sun8i) { 260 if (clk_rate > 160000000) 261 priv->clk_csr = 0x03; 262 else if (clk_rate > 80000000) 263 priv->clk_csr = 0x02; 264 else if (clk_rate > 40000000) 265 priv->clk_csr = 0x01; 266 else 267 priv->clk_csr = 0; 268 } 269 270 if (priv->plat->has_xgmac) { 271 if (clk_rate > 400000000) 272 priv->clk_csr = 0x5; 273 else if (clk_rate > 350000000) 274 priv->clk_csr = 0x4; 275 else if (clk_rate > 300000000) 276 priv->clk_csr = 0x3; 277 else if (clk_rate > 250000000) 278 priv->clk_csr = 0x2; 279 else if (clk_rate > 150000000) 280 priv->clk_csr = 0x1; 281 else 282 priv->clk_csr = 0x0; 283 } 284 } 285 286 static void print_pkt(unsigned char *buf, int len) 287 { 288 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 289 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 290 } 291 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 293 { 294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 295 u32 avail; 296 297 if (tx_q->dirty_tx > tx_q->cur_tx) 298 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 299 else 300 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 301 302 return avail; 303 } 304 305 /** 306 * stmmac_rx_dirty - Get RX queue dirty 307 * @priv: driver private structure 308 * @queue: RX queue index 309 */ 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 311 { 312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 313 u32 dirty; 314 315 if (rx_q->dirty_rx <= rx_q->cur_rx) 316 dirty = rx_q->cur_rx - rx_q->dirty_rx; 317 else 318 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 319 320 return dirty; 321 } 322 323 /** 324 * stmmac_enable_eee_mode - check and enter in LPI mode 325 * @priv: driver private structure 326 * Description: this function is to verify and enter in LPI mode in case of 327 * EEE. 328 */ 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 330 { 331 u32 tx_cnt = priv->plat->tx_queues_to_use; 332 u32 queue; 333 334 /* check if all TX queues have the work finished */ 335 for (queue = 0; queue < tx_cnt; queue++) { 336 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 337 338 if (tx_q->dirty_tx != tx_q->cur_tx) 339 return; /* still unfinished work */ 340 } 341 342 /* Check and enter in LPI mode */ 343 if (!priv->tx_path_in_lpi_mode) 344 stmmac_set_eee_mode(priv, priv->hw, 345 priv->plat->en_tx_lpi_clockgating); 346 } 347 348 /** 349 * stmmac_disable_eee_mode - disable and exit from LPI mode 350 * @priv: driver private structure 351 * Description: this function is to exit and disable EEE in case of 352 * LPI state is true. This is called by the xmit. 353 */ 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 355 { 356 stmmac_reset_eee_mode(priv, priv->hw); 357 del_timer_sync(&priv->eee_ctrl_timer); 358 priv->tx_path_in_lpi_mode = false; 359 } 360 361 /** 362 * stmmac_eee_ctrl_timer - EEE TX SW timer. 363 * @arg : data hook 364 * Description: 365 * if there is no data transfer and if we are not in LPI state, 366 * then MAC Transmitter can be moved to LPI state. 367 */ 368 static void stmmac_eee_ctrl_timer(struct timer_list *t) 369 { 370 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 371 372 stmmac_enable_eee_mode(priv); 373 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 374 } 375 376 /** 377 * stmmac_eee_init - init EEE 378 * @priv: driver private structure 379 * Description: 380 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 381 * can also manage EEE, this function enable the LPI state and start related 382 * timer. 383 */ 384 bool stmmac_eee_init(struct stmmac_priv *priv) 385 { 386 int tx_lpi_timer = priv->tx_lpi_timer; 387 388 /* Using PCS we cannot dial with the phy registers at this stage 389 * so we do not support extra feature like EEE. 390 */ 391 if (priv->hw->pcs == STMMAC_PCS_TBI || 392 priv->hw->pcs == STMMAC_PCS_RTBI) 393 return false; 394 395 /* Check if MAC core supports the EEE feature. */ 396 if (!priv->dma_cap.eee) 397 return false; 398 399 mutex_lock(&priv->lock); 400 401 /* Check if it needs to be deactivated */ 402 if (!priv->eee_active) { 403 if (priv->eee_enabled) { 404 netdev_dbg(priv->dev, "disable EEE\n"); 405 del_timer_sync(&priv->eee_ctrl_timer); 406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 407 } 408 mutex_unlock(&priv->lock); 409 return false; 410 } 411 412 if (priv->eee_active && !priv->eee_enabled) { 413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 416 tx_lpi_timer); 417 } 418 419 mutex_unlock(&priv->lock); 420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 421 return true; 422 } 423 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 425 * @priv: driver private structure 426 * @p : descriptor pointer 427 * @skb : the socket buffer 428 * Description : 429 * This function will read timestamp from the descriptor & pass it to stack. 430 * and also perform some sanity checks. 431 */ 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 433 struct dma_desc *p, struct sk_buff *skb) 434 { 435 struct skb_shared_hwtstamps shhwtstamp; 436 bool found = false; 437 u64 ns = 0; 438 439 if (!priv->hwts_tx_en) 440 return; 441 442 /* exit if skb doesn't support hw tstamp */ 443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 444 return; 445 446 /* check tx tstamp status */ 447 if (stmmac_get_tx_timestamp_status(priv, p)) { 448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 449 found = true; 450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 451 found = true; 452 } 453 454 if (found) { 455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 456 shhwtstamp.hwtstamp = ns_to_ktime(ns); 457 458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 459 /* pass tstamp to stack */ 460 skb_tstamp_tx(skb, &shhwtstamp); 461 } 462 } 463 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 465 * @priv: driver private structure 466 * @p : descriptor pointer 467 * @np : next descriptor pointer 468 * @skb : the socket buffer 469 * Description : 470 * This function will read received packet's timestamp from the descriptor 471 * and pass it to stack. It also perform some sanity checks. 472 */ 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 474 struct dma_desc *np, struct sk_buff *skb) 475 { 476 struct skb_shared_hwtstamps *shhwtstamp = NULL; 477 struct dma_desc *desc = p; 478 u64 ns = 0; 479 480 if (!priv->hwts_rx_en) 481 return; 482 /* For GMAC4, the valid timestamp is from CTX next desc. */ 483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 484 desc = np; 485 486 /* Check if timestamp is available */ 487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 490 shhwtstamp = skb_hwtstamps(skb); 491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 492 shhwtstamp->hwtstamp = ns_to_ktime(ns); 493 } else { 494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 495 } 496 } 497 498 /** 499 * stmmac_hwtstamp_set - control hardware timestamping. 500 * @dev: device pointer. 501 * @ifr: An IOCTL specific structure, that can contain a pointer to 502 * a proprietary structure used to pass information to the driver. 503 * Description: 504 * This function configures the MAC to enable/disable both outgoing(TX) 505 * and incoming(RX) packets time stamping based on user input. 506 * Return Value: 507 * 0 on success and an appropriate -ve integer on failure. 508 */ 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 510 { 511 struct stmmac_priv *priv = netdev_priv(dev); 512 struct hwtstamp_config config; 513 struct timespec64 now; 514 u64 temp = 0; 515 u32 ptp_v2 = 0; 516 u32 tstamp_all = 0; 517 u32 ptp_over_ipv4_udp = 0; 518 u32 ptp_over_ipv6_udp = 0; 519 u32 ptp_over_ethernet = 0; 520 u32 snap_type_sel = 0; 521 u32 ts_master_en = 0; 522 u32 ts_event_en = 0; 523 u32 sec_inc = 0; 524 u32 value = 0; 525 bool xmac; 526 527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 528 529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 530 netdev_alert(priv->dev, "No support for HW time stamping\n"); 531 priv->hwts_tx_en = 0; 532 priv->hwts_rx_en = 0; 533 534 return -EOPNOTSUPP; 535 } 536 537 if (copy_from_user(&config, ifr->ifr_data, 538 sizeof(config))) 539 return -EFAULT; 540 541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 542 __func__, config.flags, config.tx_type, config.rx_filter); 543 544 /* reserved for future extensions */ 545 if (config.flags) 546 return -EINVAL; 547 548 if (config.tx_type != HWTSTAMP_TX_OFF && 549 config.tx_type != HWTSTAMP_TX_ON) 550 return -ERANGE; 551 552 if (priv->adv_ts) { 553 switch (config.rx_filter) { 554 case HWTSTAMP_FILTER_NONE: 555 /* time stamp no incoming packet at all */ 556 config.rx_filter = HWTSTAMP_FILTER_NONE; 557 break; 558 559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 560 /* PTP v1, UDP, any kind of event packet */ 561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 562 /* 'xmac' hardware can support Sync, Pdelay_Req and 563 * Pdelay_resp by setting bit14 and bits17/16 to 01 564 * This leaves Delay_Req timestamps out. 565 * Enable all events *and* general purpose message 566 * timestamping 567 */ 568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 571 break; 572 573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 574 /* PTP v1, UDP, Sync packet */ 575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 576 /* take time stamp for SYNC messages only */ 577 ts_event_en = PTP_TCR_TSEVNTENA; 578 579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 581 break; 582 583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 584 /* PTP v1, UDP, Delay_req packet */ 585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 586 /* take time stamp for Delay_Req messages only */ 587 ts_master_en = PTP_TCR_TSMSTRENA; 588 ts_event_en = PTP_TCR_TSEVNTENA; 589 590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 592 break; 593 594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 595 /* PTP v2, UDP, any kind of event packet */ 596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 597 ptp_v2 = PTP_TCR_TSVER2ENA; 598 /* take time stamp for all event messages */ 599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 600 601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 603 break; 604 605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 606 /* PTP v2, UDP, Sync packet */ 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 608 ptp_v2 = PTP_TCR_TSVER2ENA; 609 /* take time stamp for SYNC messages only */ 610 ts_event_en = PTP_TCR_TSEVNTENA; 611 612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 614 break; 615 616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 617 /* PTP v2, UDP, Delay_req packet */ 618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 619 ptp_v2 = PTP_TCR_TSVER2ENA; 620 /* take time stamp for Delay_Req messages only */ 621 ts_master_en = PTP_TCR_TSMSTRENA; 622 ts_event_en = PTP_TCR_TSEVNTENA; 623 624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 626 break; 627 628 case HWTSTAMP_FILTER_PTP_V2_EVENT: 629 /* PTP v2/802.AS1 any layer, any kind of event packet */ 630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 631 ptp_v2 = PTP_TCR_TSVER2ENA; 632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 if (priv->plat->clk_ptp_ref) 791 clk_disable_unprepare(priv->plat->clk_ptp_ref); 792 stmmac_ptp_unregister(priv); 793 } 794 795 /** 796 * stmmac_mac_flow_ctrl - Configure flow control in all queues 797 * @priv: driver private structure 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 } 853 854 /* Half-Duplex can only work with single queue */ 855 if (tx_cnt > 1) { 856 phylink_set(mask, 10baseT_Half); 857 phylink_set(mask, 100baseT_Half); 858 phylink_set(mask, 1000baseT_Half); 859 } 860 861 linkmode_and(supported, supported, mac_supported); 862 linkmode_andnot(supported, supported, mask); 863 864 linkmode_and(state->advertising, state->advertising, mac_supported); 865 linkmode_andnot(state->advertising, state->advertising, mask); 866 867 /* If PCS is supported, check which modes it supports. */ 868 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 869 } 870 871 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 872 struct phylink_link_state *state) 873 { 874 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 875 876 state->link = 0; 877 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 878 } 879 880 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 881 const struct phylink_link_state *state) 882 { 883 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 884 885 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 886 } 887 888 static void stmmac_mac_an_restart(struct phylink_config *config) 889 { 890 /* Not Supported */ 891 } 892 893 static void stmmac_mac_link_down(struct phylink_config *config, 894 unsigned int mode, phy_interface_t interface) 895 { 896 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 897 898 stmmac_mac_set(priv, priv->ioaddr, false); 899 priv->eee_active = false; 900 stmmac_eee_init(priv); 901 stmmac_set_eee_pls(priv, priv->hw, false); 902 } 903 904 static void stmmac_mac_link_up(struct phylink_config *config, 905 struct phy_device *phy, 906 unsigned int mode, phy_interface_t interface, 907 int speed, int duplex, 908 bool tx_pause, bool rx_pause) 909 { 910 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 911 u32 ctrl; 912 913 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 914 915 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 916 ctrl &= ~priv->hw->link.speed_mask; 917 918 if (interface == PHY_INTERFACE_MODE_USXGMII) { 919 switch (speed) { 920 case SPEED_10000: 921 ctrl |= priv->hw->link.xgmii.speed10000; 922 break; 923 case SPEED_5000: 924 ctrl |= priv->hw->link.xgmii.speed5000; 925 break; 926 case SPEED_2500: 927 ctrl |= priv->hw->link.xgmii.speed2500; 928 break; 929 default: 930 return; 931 } 932 } else { 933 switch (speed) { 934 case SPEED_2500: 935 ctrl |= priv->hw->link.speed2500; 936 break; 937 case SPEED_1000: 938 ctrl |= priv->hw->link.speed1000; 939 break; 940 case SPEED_100: 941 ctrl |= priv->hw->link.speed100; 942 break; 943 case SPEED_10: 944 ctrl |= priv->hw->link.speed10; 945 break; 946 default: 947 return; 948 } 949 } 950 951 priv->speed = speed; 952 953 if (priv->plat->fix_mac_speed) 954 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 955 956 if (!duplex) 957 ctrl &= ~priv->hw->link.duplex; 958 else 959 ctrl |= priv->hw->link.duplex; 960 961 /* Flow Control operation */ 962 if (tx_pause && rx_pause) 963 stmmac_mac_flow_ctrl(priv, duplex); 964 965 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 966 967 stmmac_mac_set(priv, priv->ioaddr, true); 968 if (phy && priv->dma_cap.eee) { 969 priv->eee_active = phy_init_eee(phy, 1) >= 0; 970 priv->eee_enabled = stmmac_eee_init(priv); 971 stmmac_set_eee_pls(priv, priv->hw, true); 972 } 973 } 974 975 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 976 .validate = stmmac_validate, 977 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 978 .mac_config = stmmac_mac_config, 979 .mac_an_restart = stmmac_mac_an_restart, 980 .mac_link_down = stmmac_mac_link_down, 981 .mac_link_up = stmmac_mac_link_up, 982 }; 983 984 /** 985 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 986 * @priv: driver private structure 987 * Description: this is to verify if the HW supports the PCS. 988 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 989 * configured for the TBI, RTBI, or SGMII PHY interface. 990 */ 991 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 992 { 993 int interface = priv->plat->interface; 994 995 if (priv->dma_cap.pcs) { 996 if ((interface == PHY_INTERFACE_MODE_RGMII) || 997 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 998 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 999 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1000 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1001 priv->hw->pcs = STMMAC_PCS_RGMII; 1002 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1003 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1004 priv->hw->pcs = STMMAC_PCS_SGMII; 1005 } 1006 } 1007 } 1008 1009 /** 1010 * stmmac_init_phy - PHY initialization 1011 * @dev: net device structure 1012 * Description: it initializes the driver's PHY state, and attaches the PHY 1013 * to the mac driver. 1014 * Return value: 1015 * 0 on success 1016 */ 1017 static int stmmac_init_phy(struct net_device *dev) 1018 { 1019 struct stmmac_priv *priv = netdev_priv(dev); 1020 struct device_node *node; 1021 int ret; 1022 1023 node = priv->plat->phylink_node; 1024 1025 if (node) 1026 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1027 1028 /* Some DT bindings do not set-up the PHY handle. Let's try to 1029 * manually parse it 1030 */ 1031 if (!node || ret) { 1032 int addr = priv->plat->phy_addr; 1033 struct phy_device *phydev; 1034 1035 phydev = mdiobus_get_phy(priv->mii, addr); 1036 if (!phydev) { 1037 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1038 return -ENODEV; 1039 } 1040 1041 ret = phylink_connect_phy(priv->phylink, phydev); 1042 } 1043 1044 return ret; 1045 } 1046 1047 static int stmmac_phy_setup(struct stmmac_priv *priv) 1048 { 1049 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1050 int mode = priv->plat->phy_interface; 1051 struct phylink *phylink; 1052 1053 priv->phylink_config.dev = &priv->dev->dev; 1054 priv->phylink_config.type = PHYLINK_NETDEV; 1055 priv->phylink_config.pcs_poll = true; 1056 1057 if (!fwnode) 1058 fwnode = dev_fwnode(priv->device); 1059 1060 phylink = phylink_create(&priv->phylink_config, fwnode, 1061 mode, &stmmac_phylink_mac_ops); 1062 if (IS_ERR(phylink)) 1063 return PTR_ERR(phylink); 1064 1065 priv->phylink = phylink; 1066 return 0; 1067 } 1068 1069 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1070 { 1071 u32 rx_cnt = priv->plat->rx_queues_to_use; 1072 void *head_rx; 1073 u32 queue; 1074 1075 /* Display RX rings */ 1076 for (queue = 0; queue < rx_cnt; queue++) { 1077 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1078 1079 pr_info("\tRX Queue %u rings\n", queue); 1080 1081 if (priv->extend_desc) 1082 head_rx = (void *)rx_q->dma_erx; 1083 else 1084 head_rx = (void *)rx_q->dma_rx; 1085 1086 /* Display RX ring */ 1087 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1088 } 1089 } 1090 1091 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1092 { 1093 u32 tx_cnt = priv->plat->tx_queues_to_use; 1094 void *head_tx; 1095 u32 queue; 1096 1097 /* Display TX rings */ 1098 for (queue = 0; queue < tx_cnt; queue++) { 1099 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1100 1101 pr_info("\tTX Queue %d rings\n", queue); 1102 1103 if (priv->extend_desc) 1104 head_tx = (void *)tx_q->dma_etx; 1105 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1106 head_tx = (void *)tx_q->dma_entx; 1107 else 1108 head_tx = (void *)tx_q->dma_tx; 1109 1110 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1111 } 1112 } 1113 1114 static void stmmac_display_rings(struct stmmac_priv *priv) 1115 { 1116 /* Display RX ring */ 1117 stmmac_display_rx_rings(priv); 1118 1119 /* Display TX ring */ 1120 stmmac_display_tx_rings(priv); 1121 } 1122 1123 static int stmmac_set_bfsize(int mtu, int bufsize) 1124 { 1125 int ret = bufsize; 1126 1127 if (mtu >= BUF_SIZE_8KiB) 1128 ret = BUF_SIZE_16KiB; 1129 else if (mtu >= BUF_SIZE_4KiB) 1130 ret = BUF_SIZE_8KiB; 1131 else if (mtu >= BUF_SIZE_2KiB) 1132 ret = BUF_SIZE_4KiB; 1133 else if (mtu > DEFAULT_BUFSIZE) 1134 ret = BUF_SIZE_2KiB; 1135 else 1136 ret = DEFAULT_BUFSIZE; 1137 1138 return ret; 1139 } 1140 1141 /** 1142 * stmmac_clear_rx_descriptors - clear RX descriptors 1143 * @priv: driver private structure 1144 * @queue: RX queue index 1145 * Description: this function is called to clear the RX descriptors 1146 * in case of both basic and extended descriptors are used. 1147 */ 1148 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1149 { 1150 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1151 int i; 1152 1153 /* Clear the RX descriptors */ 1154 for (i = 0; i < DMA_RX_SIZE; i++) 1155 if (priv->extend_desc) 1156 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1157 priv->use_riwt, priv->mode, 1158 (i == DMA_RX_SIZE - 1), 1159 priv->dma_buf_sz); 1160 else 1161 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1162 priv->use_riwt, priv->mode, 1163 (i == DMA_RX_SIZE - 1), 1164 priv->dma_buf_sz); 1165 } 1166 1167 /** 1168 * stmmac_clear_tx_descriptors - clear tx descriptors 1169 * @priv: driver private structure 1170 * @queue: TX queue index. 1171 * Description: this function is called to clear the TX descriptors 1172 * in case of both basic and extended descriptors are used. 1173 */ 1174 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1175 { 1176 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1177 int i; 1178 1179 /* Clear the TX descriptors */ 1180 for (i = 0; i < DMA_TX_SIZE; i++) { 1181 int last = (i == (DMA_TX_SIZE - 1)); 1182 struct dma_desc *p; 1183 1184 if (priv->extend_desc) 1185 p = &tx_q->dma_etx[i].basic; 1186 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1187 p = &tx_q->dma_entx[i].basic; 1188 else 1189 p = &tx_q->dma_tx[i]; 1190 1191 stmmac_init_tx_desc(priv, p, priv->mode, last); 1192 } 1193 } 1194 1195 /** 1196 * stmmac_clear_descriptors - clear descriptors 1197 * @priv: driver private structure 1198 * Description: this function is called to clear the TX and RX descriptors 1199 * in case of both basic and extended descriptors are used. 1200 */ 1201 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1202 { 1203 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1204 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1205 u32 queue; 1206 1207 /* Clear the RX descriptors */ 1208 for (queue = 0; queue < rx_queue_cnt; queue++) 1209 stmmac_clear_rx_descriptors(priv, queue); 1210 1211 /* Clear the TX descriptors */ 1212 for (queue = 0; queue < tx_queue_cnt; queue++) 1213 stmmac_clear_tx_descriptors(priv, queue); 1214 } 1215 1216 /** 1217 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1218 * @priv: driver private structure 1219 * @p: descriptor pointer 1220 * @i: descriptor index 1221 * @flags: gfp flag 1222 * @queue: RX queue index 1223 * Description: this function is called to allocate a receive buffer, perform 1224 * the DMA mapping and init the descriptor. 1225 */ 1226 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1227 int i, gfp_t flags, u32 queue) 1228 { 1229 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1230 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1231 1232 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1233 if (!buf->page) 1234 return -ENOMEM; 1235 1236 if (priv->sph) { 1237 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1238 if (!buf->sec_page) 1239 return -ENOMEM; 1240 1241 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1242 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1243 } else { 1244 buf->sec_page = NULL; 1245 } 1246 1247 buf->addr = page_pool_get_dma_addr(buf->page); 1248 stmmac_set_desc_addr(priv, p, buf->addr); 1249 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1250 stmmac_init_desc3(priv, p); 1251 1252 return 0; 1253 } 1254 1255 /** 1256 * stmmac_free_rx_buffer - free RX dma buffers 1257 * @priv: private structure 1258 * @queue: RX queue index 1259 * @i: buffer index. 1260 */ 1261 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1262 { 1263 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1264 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1265 1266 if (buf->page) 1267 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1268 buf->page = NULL; 1269 1270 if (buf->sec_page) 1271 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1272 buf->sec_page = NULL; 1273 } 1274 1275 /** 1276 * stmmac_free_tx_buffer - free RX dma buffers 1277 * @priv: private structure 1278 * @queue: RX queue index 1279 * @i: buffer index. 1280 */ 1281 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1282 { 1283 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1284 1285 if (tx_q->tx_skbuff_dma[i].buf) { 1286 if (tx_q->tx_skbuff_dma[i].map_as_page) 1287 dma_unmap_page(priv->device, 1288 tx_q->tx_skbuff_dma[i].buf, 1289 tx_q->tx_skbuff_dma[i].len, 1290 DMA_TO_DEVICE); 1291 else 1292 dma_unmap_single(priv->device, 1293 tx_q->tx_skbuff_dma[i].buf, 1294 tx_q->tx_skbuff_dma[i].len, 1295 DMA_TO_DEVICE); 1296 } 1297 1298 if (tx_q->tx_skbuff[i]) { 1299 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1300 tx_q->tx_skbuff[i] = NULL; 1301 tx_q->tx_skbuff_dma[i].buf = 0; 1302 tx_q->tx_skbuff_dma[i].map_as_page = false; 1303 } 1304 } 1305 1306 /** 1307 * init_dma_rx_desc_rings - init the RX descriptor rings 1308 * @dev: net device structure 1309 * @flags: gfp flag. 1310 * Description: this function initializes the DMA RX descriptors 1311 * and allocates the socket buffers. It supports the chained and ring 1312 * modes. 1313 */ 1314 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1315 { 1316 struct stmmac_priv *priv = netdev_priv(dev); 1317 u32 rx_count = priv->plat->rx_queues_to_use; 1318 int ret = -ENOMEM; 1319 int queue; 1320 int i; 1321 1322 /* RX INITIALIZATION */ 1323 netif_dbg(priv, probe, priv->dev, 1324 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1325 1326 for (queue = 0; queue < rx_count; queue++) { 1327 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1328 1329 netif_dbg(priv, probe, priv->dev, 1330 "(%s) dma_rx_phy=0x%08x\n", __func__, 1331 (u32)rx_q->dma_rx_phy); 1332 1333 stmmac_clear_rx_descriptors(priv, queue); 1334 1335 for (i = 0; i < DMA_RX_SIZE; i++) { 1336 struct dma_desc *p; 1337 1338 if (priv->extend_desc) 1339 p = &((rx_q->dma_erx + i)->basic); 1340 else 1341 p = rx_q->dma_rx + i; 1342 1343 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1344 queue); 1345 if (ret) 1346 goto err_init_rx_buffers; 1347 } 1348 1349 rx_q->cur_rx = 0; 1350 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1351 1352 /* Setup the chained descriptor addresses */ 1353 if (priv->mode == STMMAC_CHAIN_MODE) { 1354 if (priv->extend_desc) 1355 stmmac_mode_init(priv, rx_q->dma_erx, 1356 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1357 else 1358 stmmac_mode_init(priv, rx_q->dma_rx, 1359 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1360 } 1361 } 1362 1363 return 0; 1364 1365 err_init_rx_buffers: 1366 while (queue >= 0) { 1367 while (--i >= 0) 1368 stmmac_free_rx_buffer(priv, queue, i); 1369 1370 if (queue == 0) 1371 break; 1372 1373 i = DMA_RX_SIZE; 1374 queue--; 1375 } 1376 1377 return ret; 1378 } 1379 1380 /** 1381 * init_dma_tx_desc_rings - init the TX descriptor rings 1382 * @dev: net device structure. 1383 * Description: this function initializes the DMA TX descriptors 1384 * and allocates the socket buffers. It supports the chained and ring 1385 * modes. 1386 */ 1387 static int init_dma_tx_desc_rings(struct net_device *dev) 1388 { 1389 struct stmmac_priv *priv = netdev_priv(dev); 1390 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1391 u32 queue; 1392 int i; 1393 1394 for (queue = 0; queue < tx_queue_cnt; queue++) { 1395 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1396 1397 netif_dbg(priv, probe, priv->dev, 1398 "(%s) dma_tx_phy=0x%08x\n", __func__, 1399 (u32)tx_q->dma_tx_phy); 1400 1401 /* Setup the chained descriptor addresses */ 1402 if (priv->mode == STMMAC_CHAIN_MODE) { 1403 if (priv->extend_desc) 1404 stmmac_mode_init(priv, tx_q->dma_etx, 1405 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1406 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1407 stmmac_mode_init(priv, tx_q->dma_tx, 1408 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1409 } 1410 1411 for (i = 0; i < DMA_TX_SIZE; i++) { 1412 struct dma_desc *p; 1413 if (priv->extend_desc) 1414 p = &((tx_q->dma_etx + i)->basic); 1415 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1416 p = &((tx_q->dma_entx + i)->basic); 1417 else 1418 p = tx_q->dma_tx + i; 1419 1420 stmmac_clear_desc(priv, p); 1421 1422 tx_q->tx_skbuff_dma[i].buf = 0; 1423 tx_q->tx_skbuff_dma[i].map_as_page = false; 1424 tx_q->tx_skbuff_dma[i].len = 0; 1425 tx_q->tx_skbuff_dma[i].last_segment = false; 1426 tx_q->tx_skbuff[i] = NULL; 1427 } 1428 1429 tx_q->dirty_tx = 0; 1430 tx_q->cur_tx = 0; 1431 tx_q->mss = 0; 1432 1433 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1434 } 1435 1436 return 0; 1437 } 1438 1439 /** 1440 * init_dma_desc_rings - init the RX/TX descriptor rings 1441 * @dev: net device structure 1442 * @flags: gfp flag. 1443 * Description: this function initializes the DMA RX/TX descriptors 1444 * and allocates the socket buffers. It supports the chained and ring 1445 * modes. 1446 */ 1447 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1448 { 1449 struct stmmac_priv *priv = netdev_priv(dev); 1450 int ret; 1451 1452 ret = init_dma_rx_desc_rings(dev, flags); 1453 if (ret) 1454 return ret; 1455 1456 ret = init_dma_tx_desc_rings(dev); 1457 1458 stmmac_clear_descriptors(priv); 1459 1460 if (netif_msg_hw(priv)) 1461 stmmac_display_rings(priv); 1462 1463 return ret; 1464 } 1465 1466 /** 1467 * dma_free_rx_skbufs - free RX dma buffers 1468 * @priv: private structure 1469 * @queue: RX queue index 1470 */ 1471 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1472 { 1473 int i; 1474 1475 for (i = 0; i < DMA_RX_SIZE; i++) 1476 stmmac_free_rx_buffer(priv, queue, i); 1477 } 1478 1479 /** 1480 * dma_free_tx_skbufs - free TX dma buffers 1481 * @priv: private structure 1482 * @queue: TX queue index 1483 */ 1484 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1485 { 1486 int i; 1487 1488 for (i = 0; i < DMA_TX_SIZE; i++) 1489 stmmac_free_tx_buffer(priv, queue, i); 1490 } 1491 1492 /** 1493 * free_dma_rx_desc_resources - free RX dma desc resources 1494 * @priv: private structure 1495 */ 1496 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1497 { 1498 u32 rx_count = priv->plat->rx_queues_to_use; 1499 u32 queue; 1500 1501 /* Free RX queue resources */ 1502 for (queue = 0; queue < rx_count; queue++) { 1503 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1504 1505 /* Release the DMA RX socket buffers */ 1506 dma_free_rx_skbufs(priv, queue); 1507 1508 /* Free DMA regions of consistent memory previously allocated */ 1509 if (!priv->extend_desc) 1510 dma_free_coherent(priv->device, 1511 DMA_RX_SIZE * sizeof(struct dma_desc), 1512 rx_q->dma_rx, rx_q->dma_rx_phy); 1513 else 1514 dma_free_coherent(priv->device, DMA_RX_SIZE * 1515 sizeof(struct dma_extended_desc), 1516 rx_q->dma_erx, rx_q->dma_rx_phy); 1517 1518 kfree(rx_q->buf_pool); 1519 if (rx_q->page_pool) 1520 page_pool_destroy(rx_q->page_pool); 1521 } 1522 } 1523 1524 /** 1525 * free_dma_tx_desc_resources - free TX dma desc resources 1526 * @priv: private structure 1527 */ 1528 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1529 { 1530 u32 tx_count = priv->plat->tx_queues_to_use; 1531 u32 queue; 1532 1533 /* Free TX queue resources */ 1534 for (queue = 0; queue < tx_count; queue++) { 1535 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1536 size_t size; 1537 void *addr; 1538 1539 /* Release the DMA TX socket buffers */ 1540 dma_free_tx_skbufs(priv, queue); 1541 1542 if (priv->extend_desc) { 1543 size = sizeof(struct dma_extended_desc); 1544 addr = tx_q->dma_etx; 1545 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1546 size = sizeof(struct dma_edesc); 1547 addr = tx_q->dma_entx; 1548 } else { 1549 size = sizeof(struct dma_desc); 1550 addr = tx_q->dma_tx; 1551 } 1552 1553 size *= DMA_TX_SIZE; 1554 1555 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1556 1557 kfree(tx_q->tx_skbuff_dma); 1558 kfree(tx_q->tx_skbuff); 1559 } 1560 } 1561 1562 /** 1563 * alloc_dma_rx_desc_resources - alloc RX resources. 1564 * @priv: private structure 1565 * Description: according to which descriptor can be used (extend or basic) 1566 * this function allocates the resources for TX and RX paths. In case of 1567 * reception, for example, it pre-allocated the RX socket buffer in order to 1568 * allow zero-copy mechanism. 1569 */ 1570 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1571 { 1572 u32 rx_count = priv->plat->rx_queues_to_use; 1573 int ret = -ENOMEM; 1574 u32 queue; 1575 1576 /* RX queues buffers and DMA */ 1577 for (queue = 0; queue < rx_count; queue++) { 1578 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1579 struct page_pool_params pp_params = { 0 }; 1580 unsigned int num_pages; 1581 1582 rx_q->queue_index = queue; 1583 rx_q->priv_data = priv; 1584 1585 pp_params.flags = PP_FLAG_DMA_MAP; 1586 pp_params.pool_size = DMA_RX_SIZE; 1587 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1588 pp_params.order = ilog2(num_pages); 1589 pp_params.nid = dev_to_node(priv->device); 1590 pp_params.dev = priv->device; 1591 pp_params.dma_dir = DMA_FROM_DEVICE; 1592 1593 rx_q->page_pool = page_pool_create(&pp_params); 1594 if (IS_ERR(rx_q->page_pool)) { 1595 ret = PTR_ERR(rx_q->page_pool); 1596 rx_q->page_pool = NULL; 1597 goto err_dma; 1598 } 1599 1600 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1601 GFP_KERNEL); 1602 if (!rx_q->buf_pool) 1603 goto err_dma; 1604 1605 if (priv->extend_desc) { 1606 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1607 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1608 &rx_q->dma_rx_phy, 1609 GFP_KERNEL); 1610 if (!rx_q->dma_erx) 1611 goto err_dma; 1612 1613 } else { 1614 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1615 DMA_RX_SIZE * sizeof(struct dma_desc), 1616 &rx_q->dma_rx_phy, 1617 GFP_KERNEL); 1618 if (!rx_q->dma_rx) 1619 goto err_dma; 1620 } 1621 } 1622 1623 return 0; 1624 1625 err_dma: 1626 free_dma_rx_desc_resources(priv); 1627 1628 return ret; 1629 } 1630 1631 /** 1632 * alloc_dma_tx_desc_resources - alloc TX resources. 1633 * @priv: private structure 1634 * Description: according to which descriptor can be used (extend or basic) 1635 * this function allocates the resources for TX and RX paths. In case of 1636 * reception, for example, it pre-allocated the RX socket buffer in order to 1637 * allow zero-copy mechanism. 1638 */ 1639 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1640 { 1641 u32 tx_count = priv->plat->tx_queues_to_use; 1642 int ret = -ENOMEM; 1643 u32 queue; 1644 1645 /* TX queues buffers and DMA */ 1646 for (queue = 0; queue < tx_count; queue++) { 1647 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1648 size_t size; 1649 void *addr; 1650 1651 tx_q->queue_index = queue; 1652 tx_q->priv_data = priv; 1653 1654 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1655 sizeof(*tx_q->tx_skbuff_dma), 1656 GFP_KERNEL); 1657 if (!tx_q->tx_skbuff_dma) 1658 goto err_dma; 1659 1660 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1661 sizeof(struct sk_buff *), 1662 GFP_KERNEL); 1663 if (!tx_q->tx_skbuff) 1664 goto err_dma; 1665 1666 if (priv->extend_desc) 1667 size = sizeof(struct dma_extended_desc); 1668 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1669 size = sizeof(struct dma_edesc); 1670 else 1671 size = sizeof(struct dma_desc); 1672 1673 size *= DMA_TX_SIZE; 1674 1675 addr = dma_alloc_coherent(priv->device, size, 1676 &tx_q->dma_tx_phy, GFP_KERNEL); 1677 if (!addr) 1678 goto err_dma; 1679 1680 if (priv->extend_desc) 1681 tx_q->dma_etx = addr; 1682 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1683 tx_q->dma_entx = addr; 1684 else 1685 tx_q->dma_tx = addr; 1686 } 1687 1688 return 0; 1689 1690 err_dma: 1691 free_dma_tx_desc_resources(priv); 1692 return ret; 1693 } 1694 1695 /** 1696 * alloc_dma_desc_resources - alloc TX/RX resources. 1697 * @priv: private structure 1698 * Description: according to which descriptor can be used (extend or basic) 1699 * this function allocates the resources for TX and RX paths. In case of 1700 * reception, for example, it pre-allocated the RX socket buffer in order to 1701 * allow zero-copy mechanism. 1702 */ 1703 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1704 { 1705 /* RX Allocation */ 1706 int ret = alloc_dma_rx_desc_resources(priv); 1707 1708 if (ret) 1709 return ret; 1710 1711 ret = alloc_dma_tx_desc_resources(priv); 1712 1713 return ret; 1714 } 1715 1716 /** 1717 * free_dma_desc_resources - free dma desc resources 1718 * @priv: private structure 1719 */ 1720 static void free_dma_desc_resources(struct stmmac_priv *priv) 1721 { 1722 /* Release the DMA RX socket buffers */ 1723 free_dma_rx_desc_resources(priv); 1724 1725 /* Release the DMA TX socket buffers */ 1726 free_dma_tx_desc_resources(priv); 1727 } 1728 1729 /** 1730 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1731 * @priv: driver private structure 1732 * Description: It is used for enabling the rx queues in the MAC 1733 */ 1734 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1735 { 1736 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1737 int queue; 1738 u8 mode; 1739 1740 for (queue = 0; queue < rx_queues_count; queue++) { 1741 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1742 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1743 } 1744 } 1745 1746 /** 1747 * stmmac_start_rx_dma - start RX DMA channel 1748 * @priv: driver private structure 1749 * @chan: RX channel index 1750 * Description: 1751 * This starts a RX DMA channel 1752 */ 1753 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1754 { 1755 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1756 stmmac_start_rx(priv, priv->ioaddr, chan); 1757 } 1758 1759 /** 1760 * stmmac_start_tx_dma - start TX DMA channel 1761 * @priv: driver private structure 1762 * @chan: TX channel index 1763 * Description: 1764 * This starts a TX DMA channel 1765 */ 1766 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1767 { 1768 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1769 stmmac_start_tx(priv, priv->ioaddr, chan); 1770 } 1771 1772 /** 1773 * stmmac_stop_rx_dma - stop RX DMA channel 1774 * @priv: driver private structure 1775 * @chan: RX channel index 1776 * Description: 1777 * This stops a RX DMA channel 1778 */ 1779 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1780 { 1781 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1782 stmmac_stop_rx(priv, priv->ioaddr, chan); 1783 } 1784 1785 /** 1786 * stmmac_stop_tx_dma - stop TX DMA channel 1787 * @priv: driver private structure 1788 * @chan: TX channel index 1789 * Description: 1790 * This stops a TX DMA channel 1791 */ 1792 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1793 { 1794 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1795 stmmac_stop_tx(priv, priv->ioaddr, chan); 1796 } 1797 1798 /** 1799 * stmmac_start_all_dma - start all RX and TX DMA channels 1800 * @priv: driver private structure 1801 * Description: 1802 * This starts all the RX and TX DMA channels 1803 */ 1804 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1805 { 1806 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1807 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1808 u32 chan = 0; 1809 1810 for (chan = 0; chan < rx_channels_count; chan++) 1811 stmmac_start_rx_dma(priv, chan); 1812 1813 for (chan = 0; chan < tx_channels_count; chan++) 1814 stmmac_start_tx_dma(priv, chan); 1815 } 1816 1817 /** 1818 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1819 * @priv: driver private structure 1820 * Description: 1821 * This stops the RX and TX DMA channels 1822 */ 1823 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1824 { 1825 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1826 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1827 u32 chan = 0; 1828 1829 for (chan = 0; chan < rx_channels_count; chan++) 1830 stmmac_stop_rx_dma(priv, chan); 1831 1832 for (chan = 0; chan < tx_channels_count; chan++) 1833 stmmac_stop_tx_dma(priv, chan); 1834 } 1835 1836 /** 1837 * stmmac_dma_operation_mode - HW DMA operation mode 1838 * @priv: driver private structure 1839 * Description: it is used for configuring the DMA operation mode register in 1840 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1841 */ 1842 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1843 { 1844 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1845 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1846 int rxfifosz = priv->plat->rx_fifo_size; 1847 int txfifosz = priv->plat->tx_fifo_size; 1848 u32 txmode = 0; 1849 u32 rxmode = 0; 1850 u32 chan = 0; 1851 u8 qmode = 0; 1852 1853 if (rxfifosz == 0) 1854 rxfifosz = priv->dma_cap.rx_fifo_size; 1855 if (txfifosz == 0) 1856 txfifosz = priv->dma_cap.tx_fifo_size; 1857 1858 /* Adjust for real per queue fifo size */ 1859 rxfifosz /= rx_channels_count; 1860 txfifosz /= tx_channels_count; 1861 1862 if (priv->plat->force_thresh_dma_mode) { 1863 txmode = tc; 1864 rxmode = tc; 1865 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1866 /* 1867 * In case of GMAC, SF mode can be enabled 1868 * to perform the TX COE in HW. This depends on: 1869 * 1) TX COE if actually supported 1870 * 2) There is no bugged Jumbo frame support 1871 * that needs to not insert csum in the TDES. 1872 */ 1873 txmode = SF_DMA_MODE; 1874 rxmode = SF_DMA_MODE; 1875 priv->xstats.threshold = SF_DMA_MODE; 1876 } else { 1877 txmode = tc; 1878 rxmode = SF_DMA_MODE; 1879 } 1880 1881 /* configure all channels */ 1882 for (chan = 0; chan < rx_channels_count; chan++) { 1883 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1884 1885 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1886 rxfifosz, qmode); 1887 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1888 chan); 1889 } 1890 1891 for (chan = 0; chan < tx_channels_count; chan++) { 1892 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1893 1894 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1895 txfifosz, qmode); 1896 } 1897 } 1898 1899 /** 1900 * stmmac_tx_clean - to manage the transmission completion 1901 * @priv: driver private structure 1902 * @queue: TX queue index 1903 * Description: it reclaims the transmit resources after transmission completes. 1904 */ 1905 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1906 { 1907 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1908 unsigned int bytes_compl = 0, pkts_compl = 0; 1909 unsigned int entry, count = 0; 1910 1911 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1912 1913 priv->xstats.tx_clean++; 1914 1915 entry = tx_q->dirty_tx; 1916 while ((entry != tx_q->cur_tx) && (count < budget)) { 1917 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1918 struct dma_desc *p; 1919 int status; 1920 1921 if (priv->extend_desc) 1922 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1923 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1924 p = &tx_q->dma_entx[entry].basic; 1925 else 1926 p = tx_q->dma_tx + entry; 1927 1928 status = stmmac_tx_status(priv, &priv->dev->stats, 1929 &priv->xstats, p, priv->ioaddr); 1930 /* Check if the descriptor is owned by the DMA */ 1931 if (unlikely(status & tx_dma_own)) 1932 break; 1933 1934 count++; 1935 1936 /* Make sure descriptor fields are read after reading 1937 * the own bit. 1938 */ 1939 dma_rmb(); 1940 1941 /* Just consider the last segment and ...*/ 1942 if (likely(!(status & tx_not_ls))) { 1943 /* ... verify the status error condition */ 1944 if (unlikely(status & tx_err)) { 1945 priv->dev->stats.tx_errors++; 1946 } else { 1947 priv->dev->stats.tx_packets++; 1948 priv->xstats.tx_pkt_n++; 1949 } 1950 stmmac_get_tx_hwtstamp(priv, p, skb); 1951 } 1952 1953 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1954 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1955 dma_unmap_page(priv->device, 1956 tx_q->tx_skbuff_dma[entry].buf, 1957 tx_q->tx_skbuff_dma[entry].len, 1958 DMA_TO_DEVICE); 1959 else 1960 dma_unmap_single(priv->device, 1961 tx_q->tx_skbuff_dma[entry].buf, 1962 tx_q->tx_skbuff_dma[entry].len, 1963 DMA_TO_DEVICE); 1964 tx_q->tx_skbuff_dma[entry].buf = 0; 1965 tx_q->tx_skbuff_dma[entry].len = 0; 1966 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1967 } 1968 1969 stmmac_clean_desc3(priv, tx_q, p); 1970 1971 tx_q->tx_skbuff_dma[entry].last_segment = false; 1972 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1973 1974 if (likely(skb != NULL)) { 1975 pkts_compl++; 1976 bytes_compl += skb->len; 1977 dev_consume_skb_any(skb); 1978 tx_q->tx_skbuff[entry] = NULL; 1979 } 1980 1981 stmmac_release_tx_desc(priv, p, priv->mode); 1982 1983 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1984 } 1985 tx_q->dirty_tx = entry; 1986 1987 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1988 pkts_compl, bytes_compl); 1989 1990 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1991 queue))) && 1992 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1993 1994 netif_dbg(priv, tx_done, priv->dev, 1995 "%s: restart transmit\n", __func__); 1996 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1997 } 1998 1999 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 2000 stmmac_enable_eee_mode(priv); 2001 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 2002 } 2003 2004 /* We still have pending packets, let's call for a new scheduling */ 2005 if (tx_q->dirty_tx != tx_q->cur_tx) 2006 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2007 2008 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2009 2010 return count; 2011 } 2012 2013 /** 2014 * stmmac_tx_err - to manage the tx error 2015 * @priv: driver private structure 2016 * @chan: channel index 2017 * Description: it cleans the descriptors and restarts the transmission 2018 * in case of transmission errors. 2019 */ 2020 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2021 { 2022 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2023 2024 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2025 2026 stmmac_stop_tx_dma(priv, chan); 2027 dma_free_tx_skbufs(priv, chan); 2028 stmmac_clear_tx_descriptors(priv, chan); 2029 tx_q->dirty_tx = 0; 2030 tx_q->cur_tx = 0; 2031 tx_q->mss = 0; 2032 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2033 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2034 tx_q->dma_tx_phy, chan); 2035 stmmac_start_tx_dma(priv, chan); 2036 2037 priv->dev->stats.tx_errors++; 2038 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2039 } 2040 2041 /** 2042 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2043 * @priv: driver private structure 2044 * @txmode: TX operating mode 2045 * @rxmode: RX operating mode 2046 * @chan: channel index 2047 * Description: it is used for configuring of the DMA operation mode in 2048 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2049 * mode. 2050 */ 2051 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2052 u32 rxmode, u32 chan) 2053 { 2054 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2055 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2056 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2057 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2058 int rxfifosz = priv->plat->rx_fifo_size; 2059 int txfifosz = priv->plat->tx_fifo_size; 2060 2061 if (rxfifosz == 0) 2062 rxfifosz = priv->dma_cap.rx_fifo_size; 2063 if (txfifosz == 0) 2064 txfifosz = priv->dma_cap.tx_fifo_size; 2065 2066 /* Adjust for real per queue fifo size */ 2067 rxfifosz /= rx_channels_count; 2068 txfifosz /= tx_channels_count; 2069 2070 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2071 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2072 } 2073 2074 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2075 { 2076 int ret; 2077 2078 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2079 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2080 if (ret && (ret != -EINVAL)) { 2081 stmmac_global_err(priv); 2082 return true; 2083 } 2084 2085 return false; 2086 } 2087 2088 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2089 { 2090 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2091 &priv->xstats, chan); 2092 struct stmmac_channel *ch = &priv->channel[chan]; 2093 unsigned long flags; 2094 2095 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2096 if (napi_schedule_prep(&ch->rx_napi)) { 2097 spin_lock_irqsave(&ch->lock, flags); 2098 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2099 spin_unlock_irqrestore(&ch->lock, flags); 2100 __napi_schedule_irqoff(&ch->rx_napi); 2101 } 2102 } 2103 2104 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2105 if (napi_schedule_prep(&ch->tx_napi)) { 2106 spin_lock_irqsave(&ch->lock, flags); 2107 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2108 spin_unlock_irqrestore(&ch->lock, flags); 2109 __napi_schedule_irqoff(&ch->tx_napi); 2110 } 2111 } 2112 2113 return status; 2114 } 2115 2116 /** 2117 * stmmac_dma_interrupt - DMA ISR 2118 * @priv: driver private structure 2119 * Description: this is the DMA ISR. It is called by the main ISR. 2120 * It calls the dwmac dma routine and schedule poll method in case of some 2121 * work can be done. 2122 */ 2123 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2124 { 2125 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2126 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2127 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2128 tx_channel_count : rx_channel_count; 2129 u32 chan; 2130 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2131 2132 /* Make sure we never check beyond our status buffer. */ 2133 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2134 channels_to_check = ARRAY_SIZE(status); 2135 2136 for (chan = 0; chan < channels_to_check; chan++) 2137 status[chan] = stmmac_napi_check(priv, chan); 2138 2139 for (chan = 0; chan < tx_channel_count; chan++) { 2140 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2141 /* Try to bump up the dma threshold on this failure */ 2142 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2143 (tc <= 256)) { 2144 tc += 64; 2145 if (priv->plat->force_thresh_dma_mode) 2146 stmmac_set_dma_operation_mode(priv, 2147 tc, 2148 tc, 2149 chan); 2150 else 2151 stmmac_set_dma_operation_mode(priv, 2152 tc, 2153 SF_DMA_MODE, 2154 chan); 2155 priv->xstats.threshold = tc; 2156 } 2157 } else if (unlikely(status[chan] == tx_hard_error)) { 2158 stmmac_tx_err(priv, chan); 2159 } 2160 } 2161 } 2162 2163 /** 2164 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2165 * @priv: driver private structure 2166 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2167 */ 2168 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2169 { 2170 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2171 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2172 2173 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2174 2175 if (priv->dma_cap.rmon) { 2176 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2177 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2178 } else 2179 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2180 } 2181 2182 /** 2183 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2184 * @priv: driver private structure 2185 * Description: 2186 * new GMAC chip generations have a new register to indicate the 2187 * presence of the optional feature/functions. 2188 * This can be also used to override the value passed through the 2189 * platform and necessary for old MAC10/100 and GMAC chips. 2190 */ 2191 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2192 { 2193 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2194 } 2195 2196 /** 2197 * stmmac_check_ether_addr - check if the MAC addr is valid 2198 * @priv: driver private structure 2199 * Description: 2200 * it is to verify if the MAC address is valid, in case of failures it 2201 * generates a random MAC address 2202 */ 2203 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2204 { 2205 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2206 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2207 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2208 eth_hw_addr_random(priv->dev); 2209 dev_info(priv->device, "device MAC address %pM\n", 2210 priv->dev->dev_addr); 2211 } 2212 } 2213 2214 /** 2215 * stmmac_init_dma_engine - DMA init. 2216 * @priv: driver private structure 2217 * Description: 2218 * It inits the DMA invoking the specific MAC/GMAC callback. 2219 * Some DMA parameters can be passed from the platform; 2220 * in case of these are not passed a default is kept for the MAC or GMAC. 2221 */ 2222 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2223 { 2224 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2225 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2226 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2227 struct stmmac_rx_queue *rx_q; 2228 struct stmmac_tx_queue *tx_q; 2229 u32 chan = 0; 2230 int atds = 0; 2231 int ret = 0; 2232 2233 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2234 dev_err(priv->device, "Invalid DMA configuration\n"); 2235 return -EINVAL; 2236 } 2237 2238 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2239 atds = 1; 2240 2241 ret = stmmac_reset(priv, priv->ioaddr); 2242 if (ret) { 2243 dev_err(priv->device, "Failed to reset the dma\n"); 2244 return ret; 2245 } 2246 2247 /* DMA Configuration */ 2248 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2249 2250 if (priv->plat->axi) 2251 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2252 2253 /* DMA CSR Channel configuration */ 2254 for (chan = 0; chan < dma_csr_ch; chan++) 2255 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2256 2257 /* DMA RX Channel Configuration */ 2258 for (chan = 0; chan < rx_channels_count; chan++) { 2259 rx_q = &priv->rx_queue[chan]; 2260 2261 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2262 rx_q->dma_rx_phy, chan); 2263 2264 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2265 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2266 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2267 rx_q->rx_tail_addr, chan); 2268 } 2269 2270 /* DMA TX Channel Configuration */ 2271 for (chan = 0; chan < tx_channels_count; chan++) { 2272 tx_q = &priv->tx_queue[chan]; 2273 2274 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2275 tx_q->dma_tx_phy, chan); 2276 2277 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2278 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2279 tx_q->tx_tail_addr, chan); 2280 } 2281 2282 return ret; 2283 } 2284 2285 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2286 { 2287 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2288 2289 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2290 } 2291 2292 /** 2293 * stmmac_tx_timer - mitigation sw timer for tx. 2294 * @data: data pointer 2295 * Description: 2296 * This is the timer handler to directly invoke the stmmac_tx_clean. 2297 */ 2298 static void stmmac_tx_timer(struct timer_list *t) 2299 { 2300 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2301 struct stmmac_priv *priv = tx_q->priv_data; 2302 struct stmmac_channel *ch; 2303 2304 ch = &priv->channel[tx_q->queue_index]; 2305 2306 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2307 unsigned long flags; 2308 2309 spin_lock_irqsave(&ch->lock, flags); 2310 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2311 spin_unlock_irqrestore(&ch->lock, flags); 2312 __napi_schedule(&ch->tx_napi); 2313 } 2314 } 2315 2316 /** 2317 * stmmac_init_coalesce - init mitigation options. 2318 * @priv: driver private structure 2319 * Description: 2320 * This inits the coalesce parameters: i.e. timer rate, 2321 * timer handler and default threshold used for enabling the 2322 * interrupt on completion bit. 2323 */ 2324 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2325 { 2326 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2327 u32 chan; 2328 2329 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2330 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2331 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2332 2333 for (chan = 0; chan < tx_channel_count; chan++) { 2334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2335 2336 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2337 } 2338 } 2339 2340 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2341 { 2342 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2343 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2344 u32 chan; 2345 2346 /* set TX ring length */ 2347 for (chan = 0; chan < tx_channels_count; chan++) 2348 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2349 (DMA_TX_SIZE - 1), chan); 2350 2351 /* set RX ring length */ 2352 for (chan = 0; chan < rx_channels_count; chan++) 2353 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2354 (DMA_RX_SIZE - 1), chan); 2355 } 2356 2357 /** 2358 * stmmac_set_tx_queue_weight - Set TX queue weight 2359 * @priv: driver private structure 2360 * Description: It is used for setting TX queues weight 2361 */ 2362 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2363 { 2364 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2365 u32 weight; 2366 u32 queue; 2367 2368 for (queue = 0; queue < tx_queues_count; queue++) { 2369 weight = priv->plat->tx_queues_cfg[queue].weight; 2370 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2371 } 2372 } 2373 2374 /** 2375 * stmmac_configure_cbs - Configure CBS in TX queue 2376 * @priv: driver private structure 2377 * Description: It is used for configuring CBS in AVB TX queues 2378 */ 2379 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2380 { 2381 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2382 u32 mode_to_use; 2383 u32 queue; 2384 2385 /* queue 0 is reserved for legacy traffic */ 2386 for (queue = 1; queue < tx_queues_count; queue++) { 2387 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2388 if (mode_to_use == MTL_QUEUE_DCB) 2389 continue; 2390 2391 stmmac_config_cbs(priv, priv->hw, 2392 priv->plat->tx_queues_cfg[queue].send_slope, 2393 priv->plat->tx_queues_cfg[queue].idle_slope, 2394 priv->plat->tx_queues_cfg[queue].high_credit, 2395 priv->plat->tx_queues_cfg[queue].low_credit, 2396 queue); 2397 } 2398 } 2399 2400 /** 2401 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2402 * @priv: driver private structure 2403 * Description: It is used for mapping RX queues to RX dma channels 2404 */ 2405 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2406 { 2407 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2408 u32 queue; 2409 u32 chan; 2410 2411 for (queue = 0; queue < rx_queues_count; queue++) { 2412 chan = priv->plat->rx_queues_cfg[queue].chan; 2413 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2414 } 2415 } 2416 2417 /** 2418 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2419 * @priv: driver private structure 2420 * Description: It is used for configuring the RX Queue Priority 2421 */ 2422 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2423 { 2424 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2425 u32 queue; 2426 u32 prio; 2427 2428 for (queue = 0; queue < rx_queues_count; queue++) { 2429 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2430 continue; 2431 2432 prio = priv->plat->rx_queues_cfg[queue].prio; 2433 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2434 } 2435 } 2436 2437 /** 2438 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2439 * @priv: driver private structure 2440 * Description: It is used for configuring the TX Queue Priority 2441 */ 2442 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2443 { 2444 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2445 u32 queue; 2446 u32 prio; 2447 2448 for (queue = 0; queue < tx_queues_count; queue++) { 2449 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2450 continue; 2451 2452 prio = priv->plat->tx_queues_cfg[queue].prio; 2453 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2454 } 2455 } 2456 2457 /** 2458 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2459 * @priv: driver private structure 2460 * Description: It is used for configuring the RX queue routing 2461 */ 2462 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2463 { 2464 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2465 u32 queue; 2466 u8 packet; 2467 2468 for (queue = 0; queue < rx_queues_count; queue++) { 2469 /* no specific packet type routing specified for the queue */ 2470 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2471 continue; 2472 2473 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2474 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2475 } 2476 } 2477 2478 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2479 { 2480 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2481 priv->rss.enable = false; 2482 return; 2483 } 2484 2485 if (priv->dev->features & NETIF_F_RXHASH) 2486 priv->rss.enable = true; 2487 else 2488 priv->rss.enable = false; 2489 2490 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2491 priv->plat->rx_queues_to_use); 2492 } 2493 2494 /** 2495 * stmmac_mtl_configuration - Configure MTL 2496 * @priv: driver private structure 2497 * Description: It is used for configurring MTL 2498 */ 2499 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2500 { 2501 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2502 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2503 2504 if (tx_queues_count > 1) 2505 stmmac_set_tx_queue_weight(priv); 2506 2507 /* Configure MTL RX algorithms */ 2508 if (rx_queues_count > 1) 2509 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2510 priv->plat->rx_sched_algorithm); 2511 2512 /* Configure MTL TX algorithms */ 2513 if (tx_queues_count > 1) 2514 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2515 priv->plat->tx_sched_algorithm); 2516 2517 /* Configure CBS in AVB TX queues */ 2518 if (tx_queues_count > 1) 2519 stmmac_configure_cbs(priv); 2520 2521 /* Map RX MTL to DMA channels */ 2522 stmmac_rx_queue_dma_chan_map(priv); 2523 2524 /* Enable MAC RX Queues */ 2525 stmmac_mac_enable_rx_queues(priv); 2526 2527 /* Set RX priorities */ 2528 if (rx_queues_count > 1) 2529 stmmac_mac_config_rx_queues_prio(priv); 2530 2531 /* Set TX priorities */ 2532 if (tx_queues_count > 1) 2533 stmmac_mac_config_tx_queues_prio(priv); 2534 2535 /* Set RX routing */ 2536 if (rx_queues_count > 1) 2537 stmmac_mac_config_rx_queues_routing(priv); 2538 2539 /* Receive Side Scaling */ 2540 if (rx_queues_count > 1) 2541 stmmac_mac_config_rss(priv); 2542 } 2543 2544 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2545 { 2546 if (priv->dma_cap.asp) { 2547 netdev_info(priv->dev, "Enabling Safety Features\n"); 2548 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2549 } else { 2550 netdev_info(priv->dev, "No Safety Features support found\n"); 2551 } 2552 } 2553 2554 /** 2555 * stmmac_hw_setup - setup mac in a usable state. 2556 * @dev : pointer to the device structure. 2557 * Description: 2558 * this is the main function to setup the HW in a usable state because the 2559 * dma engine is reset, the core registers are configured (e.g. AXI, 2560 * Checksum features, timers). The DMA is ready to start receiving and 2561 * transmitting. 2562 * Return value: 2563 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2564 * file on failure. 2565 */ 2566 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2567 { 2568 struct stmmac_priv *priv = netdev_priv(dev); 2569 u32 rx_cnt = priv->plat->rx_queues_to_use; 2570 u32 tx_cnt = priv->plat->tx_queues_to_use; 2571 u32 chan; 2572 int ret; 2573 2574 /* DMA initialization and SW reset */ 2575 ret = stmmac_init_dma_engine(priv); 2576 if (ret < 0) { 2577 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2578 __func__); 2579 return ret; 2580 } 2581 2582 /* Copy the MAC addr into the HW */ 2583 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2584 2585 /* PS and related bits will be programmed according to the speed */ 2586 if (priv->hw->pcs) { 2587 int speed = priv->plat->mac_port_sel_speed; 2588 2589 if ((speed == SPEED_10) || (speed == SPEED_100) || 2590 (speed == SPEED_1000)) { 2591 priv->hw->ps = speed; 2592 } else { 2593 dev_warn(priv->device, "invalid port speed\n"); 2594 priv->hw->ps = 0; 2595 } 2596 } 2597 2598 /* Initialize the MAC Core */ 2599 stmmac_core_init(priv, priv->hw, dev); 2600 2601 /* Initialize MTL*/ 2602 stmmac_mtl_configuration(priv); 2603 2604 /* Initialize Safety Features */ 2605 stmmac_safety_feat_configuration(priv); 2606 2607 ret = stmmac_rx_ipc(priv, priv->hw); 2608 if (!ret) { 2609 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2610 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2611 priv->hw->rx_csum = 0; 2612 } 2613 2614 /* Enable the MAC Rx/Tx */ 2615 stmmac_mac_set(priv, priv->ioaddr, true); 2616 2617 /* Set the HW DMA mode and the COE */ 2618 stmmac_dma_operation_mode(priv); 2619 2620 stmmac_mmc_setup(priv); 2621 2622 if (init_ptp) { 2623 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2624 if (ret < 0) 2625 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2626 2627 ret = stmmac_init_ptp(priv); 2628 if (ret == -EOPNOTSUPP) 2629 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2630 else if (ret) 2631 netdev_warn(priv->dev, "PTP init failed\n"); 2632 } 2633 2634 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2635 2636 if (priv->use_riwt) { 2637 if (!priv->rx_riwt) 2638 priv->rx_riwt = DEF_DMA_RIWT; 2639 2640 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2641 } 2642 2643 if (priv->hw->pcs) 2644 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2645 2646 /* set TX and RX rings length */ 2647 stmmac_set_rings_length(priv); 2648 2649 /* Enable TSO */ 2650 if (priv->tso) { 2651 for (chan = 0; chan < tx_cnt; chan++) 2652 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2653 } 2654 2655 /* Enable Split Header */ 2656 if (priv->sph && priv->hw->rx_csum) { 2657 for (chan = 0; chan < rx_cnt; chan++) 2658 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2659 } 2660 2661 /* VLAN Tag Insertion */ 2662 if (priv->dma_cap.vlins) 2663 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2664 2665 /* TBS */ 2666 for (chan = 0; chan < tx_cnt; chan++) { 2667 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2668 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2669 2670 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2671 } 2672 2673 /* Start the ball rolling... */ 2674 stmmac_start_all_dma(priv); 2675 2676 return 0; 2677 } 2678 2679 static void stmmac_hw_teardown(struct net_device *dev) 2680 { 2681 struct stmmac_priv *priv = netdev_priv(dev); 2682 2683 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2684 } 2685 2686 /** 2687 * stmmac_open - open entry point of the driver 2688 * @dev : pointer to the device structure. 2689 * Description: 2690 * This function is the open entry point of the driver. 2691 * Return value: 2692 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2693 * file on failure. 2694 */ 2695 static int stmmac_open(struct net_device *dev) 2696 { 2697 struct stmmac_priv *priv = netdev_priv(dev); 2698 int bfsize = 0; 2699 u32 chan; 2700 int ret; 2701 2702 if (priv->hw->pcs != STMMAC_PCS_TBI && 2703 priv->hw->pcs != STMMAC_PCS_RTBI && 2704 priv->hw->xpcs == NULL) { 2705 ret = stmmac_init_phy(dev); 2706 if (ret) { 2707 netdev_err(priv->dev, 2708 "%s: Cannot attach to PHY (error: %d)\n", 2709 __func__, ret); 2710 return ret; 2711 } 2712 } 2713 2714 /* Extra statistics */ 2715 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2716 priv->xstats.threshold = tc; 2717 2718 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2719 if (bfsize < 0) 2720 bfsize = 0; 2721 2722 if (bfsize < BUF_SIZE_16KiB) 2723 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2724 2725 priv->dma_buf_sz = bfsize; 2726 buf_sz = bfsize; 2727 2728 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2729 2730 /* Earlier check for TBS */ 2731 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2732 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2733 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2734 2735 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2736 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2737 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2738 } 2739 2740 ret = alloc_dma_desc_resources(priv); 2741 if (ret < 0) { 2742 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2743 __func__); 2744 goto dma_desc_error; 2745 } 2746 2747 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2748 if (ret < 0) { 2749 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2750 __func__); 2751 goto init_error; 2752 } 2753 2754 ret = stmmac_hw_setup(dev, true); 2755 if (ret < 0) { 2756 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2757 goto init_error; 2758 } 2759 2760 stmmac_init_coalesce(priv); 2761 2762 phylink_start(priv->phylink); 2763 2764 /* Request the IRQ lines */ 2765 ret = request_irq(dev->irq, stmmac_interrupt, 2766 IRQF_SHARED, dev->name, dev); 2767 if (unlikely(ret < 0)) { 2768 netdev_err(priv->dev, 2769 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2770 __func__, dev->irq, ret); 2771 goto irq_error; 2772 } 2773 2774 /* Request the Wake IRQ in case of another line is used for WoL */ 2775 if (priv->wol_irq != dev->irq) { 2776 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2777 IRQF_SHARED, dev->name, dev); 2778 if (unlikely(ret < 0)) { 2779 netdev_err(priv->dev, 2780 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2781 __func__, priv->wol_irq, ret); 2782 goto wolirq_error; 2783 } 2784 } 2785 2786 /* Request the IRQ lines */ 2787 if (priv->lpi_irq > 0) { 2788 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2789 dev->name, dev); 2790 if (unlikely(ret < 0)) { 2791 netdev_err(priv->dev, 2792 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2793 __func__, priv->lpi_irq, ret); 2794 goto lpiirq_error; 2795 } 2796 } 2797 2798 stmmac_enable_all_queues(priv); 2799 stmmac_start_all_queues(priv); 2800 2801 return 0; 2802 2803 lpiirq_error: 2804 if (priv->wol_irq != dev->irq) 2805 free_irq(priv->wol_irq, dev); 2806 wolirq_error: 2807 free_irq(dev->irq, dev); 2808 irq_error: 2809 phylink_stop(priv->phylink); 2810 2811 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2812 del_timer_sync(&priv->tx_queue[chan].txtimer); 2813 2814 stmmac_hw_teardown(dev); 2815 init_error: 2816 free_dma_desc_resources(priv); 2817 dma_desc_error: 2818 phylink_disconnect_phy(priv->phylink); 2819 return ret; 2820 } 2821 2822 /** 2823 * stmmac_release - close entry point of the driver 2824 * @dev : device pointer. 2825 * Description: 2826 * This is the stop entry point of the driver. 2827 */ 2828 static int stmmac_release(struct net_device *dev) 2829 { 2830 struct stmmac_priv *priv = netdev_priv(dev); 2831 u32 chan; 2832 2833 if (priv->eee_enabled) 2834 del_timer_sync(&priv->eee_ctrl_timer); 2835 2836 /* Stop and disconnect the PHY */ 2837 phylink_stop(priv->phylink); 2838 phylink_disconnect_phy(priv->phylink); 2839 2840 stmmac_stop_all_queues(priv); 2841 2842 stmmac_disable_all_queues(priv); 2843 2844 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2845 del_timer_sync(&priv->tx_queue[chan].txtimer); 2846 2847 /* Free the IRQ lines */ 2848 free_irq(dev->irq, dev); 2849 if (priv->wol_irq != dev->irq) 2850 free_irq(priv->wol_irq, dev); 2851 if (priv->lpi_irq > 0) 2852 free_irq(priv->lpi_irq, dev); 2853 2854 /* Stop TX/RX DMA and clear the descriptors */ 2855 stmmac_stop_all_dma(priv); 2856 2857 /* Release and free the Rx/Tx resources */ 2858 free_dma_desc_resources(priv); 2859 2860 /* Disable the MAC Rx/Tx */ 2861 stmmac_mac_set(priv, priv->ioaddr, false); 2862 2863 netif_carrier_off(dev); 2864 2865 stmmac_release_ptp(priv); 2866 2867 return 0; 2868 } 2869 2870 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2871 struct stmmac_tx_queue *tx_q) 2872 { 2873 u16 tag = 0x0, inner_tag = 0x0; 2874 u32 inner_type = 0x0; 2875 struct dma_desc *p; 2876 2877 if (!priv->dma_cap.vlins) 2878 return false; 2879 if (!skb_vlan_tag_present(skb)) 2880 return false; 2881 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2882 inner_tag = skb_vlan_tag_get(skb); 2883 inner_type = STMMAC_VLAN_INSERT; 2884 } 2885 2886 tag = skb_vlan_tag_get(skb); 2887 2888 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2889 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2890 else 2891 p = &tx_q->dma_tx[tx_q->cur_tx]; 2892 2893 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2894 return false; 2895 2896 stmmac_set_tx_owner(priv, p); 2897 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2898 return true; 2899 } 2900 2901 /** 2902 * stmmac_tso_allocator - close entry point of the driver 2903 * @priv: driver private structure 2904 * @des: buffer start address 2905 * @total_len: total length to fill in descriptors 2906 * @last_segmant: condition for the last descriptor 2907 * @queue: TX queue index 2908 * Description: 2909 * This function fills descriptor and request new descriptors according to 2910 * buffer length to fill 2911 */ 2912 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2913 int total_len, bool last_segment, u32 queue) 2914 { 2915 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2916 struct dma_desc *desc; 2917 u32 buff_size; 2918 int tmp_len; 2919 2920 tmp_len = total_len; 2921 2922 while (tmp_len > 0) { 2923 dma_addr_t curr_addr; 2924 2925 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2926 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2927 2928 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2929 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 2930 else 2931 desc = &tx_q->dma_tx[tx_q->cur_tx]; 2932 2933 curr_addr = des + (total_len - tmp_len); 2934 if (priv->dma_cap.addr64 <= 32) 2935 desc->des0 = cpu_to_le32(curr_addr); 2936 else 2937 stmmac_set_desc_addr(priv, desc, curr_addr); 2938 2939 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2940 TSO_MAX_BUFF_SIZE : tmp_len; 2941 2942 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2943 0, 1, 2944 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2945 0, 0); 2946 2947 tmp_len -= TSO_MAX_BUFF_SIZE; 2948 } 2949 } 2950 2951 /** 2952 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2953 * @skb : the socket buffer 2954 * @dev : device pointer 2955 * Description: this is the transmit function that is called on TSO frames 2956 * (support available on GMAC4 and newer chips). 2957 * Diagram below show the ring programming in case of TSO frames: 2958 * 2959 * First Descriptor 2960 * -------- 2961 * | DES0 |---> buffer1 = L2/L3/L4 header 2962 * | DES1 |---> TCP Payload (can continue on next descr...) 2963 * | DES2 |---> buffer 1 and 2 len 2964 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2965 * -------- 2966 * | 2967 * ... 2968 * | 2969 * -------- 2970 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2971 * | DES1 | --| 2972 * | DES2 | --> buffer 1 and 2 len 2973 * | DES3 | 2974 * -------- 2975 * 2976 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2977 */ 2978 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2979 { 2980 struct dma_desc *desc, *first, *mss_desc = NULL; 2981 struct stmmac_priv *priv = netdev_priv(dev); 2982 int desc_size, tmp_pay_len = 0, first_tx; 2983 int nfrags = skb_shinfo(skb)->nr_frags; 2984 u32 queue = skb_get_queue_mapping(skb); 2985 unsigned int first_entry, tx_packets; 2986 struct stmmac_tx_queue *tx_q; 2987 bool has_vlan, set_ic; 2988 u8 proto_hdr_len, hdr; 2989 u32 pay_len, mss; 2990 dma_addr_t des; 2991 int i; 2992 2993 tx_q = &priv->tx_queue[queue]; 2994 first_tx = tx_q->cur_tx; 2995 2996 /* Compute header lengths */ 2997 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 2998 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 2999 hdr = sizeof(struct udphdr); 3000 } else { 3001 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3002 hdr = tcp_hdrlen(skb); 3003 } 3004 3005 /* Desc availability based on threshold should be enough safe */ 3006 if (unlikely(stmmac_tx_avail(priv, queue) < 3007 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3008 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3009 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3010 queue)); 3011 /* This is a hard error, log it. */ 3012 netdev_err(priv->dev, 3013 "%s: Tx Ring full when queue awake\n", 3014 __func__); 3015 } 3016 return NETDEV_TX_BUSY; 3017 } 3018 3019 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3020 3021 mss = skb_shinfo(skb)->gso_size; 3022 3023 /* set new MSS value if needed */ 3024 if (mss != tx_q->mss) { 3025 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3026 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3027 else 3028 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3029 3030 stmmac_set_mss(priv, mss_desc, mss); 3031 tx_q->mss = mss; 3032 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3033 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3034 } 3035 3036 if (netif_msg_tx_queued(priv)) { 3037 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3038 __func__, hdr, proto_hdr_len, pay_len, mss); 3039 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3040 skb->data_len); 3041 } 3042 3043 /* Check if VLAN can be inserted by HW */ 3044 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3045 3046 first_entry = tx_q->cur_tx; 3047 WARN_ON(tx_q->tx_skbuff[first_entry]); 3048 3049 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3050 desc = &tx_q->dma_entx[first_entry].basic; 3051 else 3052 desc = &tx_q->dma_tx[first_entry]; 3053 first = desc; 3054 3055 if (has_vlan) 3056 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3057 3058 /* first descriptor: fill Headers on Buf1 */ 3059 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3060 DMA_TO_DEVICE); 3061 if (dma_mapping_error(priv->device, des)) 3062 goto dma_map_err; 3063 3064 tx_q->tx_skbuff_dma[first_entry].buf = des; 3065 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3066 3067 if (priv->dma_cap.addr64 <= 32) { 3068 first->des0 = cpu_to_le32(des); 3069 3070 /* Fill start of payload in buff2 of first descriptor */ 3071 if (pay_len) 3072 first->des1 = cpu_to_le32(des + proto_hdr_len); 3073 3074 /* If needed take extra descriptors to fill the remaining payload */ 3075 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3076 } else { 3077 stmmac_set_desc_addr(priv, first, des); 3078 tmp_pay_len = pay_len; 3079 des += proto_hdr_len; 3080 pay_len = 0; 3081 } 3082 3083 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3084 3085 /* Prepare fragments */ 3086 for (i = 0; i < nfrags; i++) { 3087 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3088 3089 des = skb_frag_dma_map(priv->device, frag, 0, 3090 skb_frag_size(frag), 3091 DMA_TO_DEVICE); 3092 if (dma_mapping_error(priv->device, des)) 3093 goto dma_map_err; 3094 3095 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3096 (i == nfrags - 1), queue); 3097 3098 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3099 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3100 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3101 } 3102 3103 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3104 3105 /* Only the last descriptor gets to point to the skb. */ 3106 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3107 3108 /* Manage tx mitigation */ 3109 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3110 tx_q->tx_count_frames += tx_packets; 3111 3112 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3113 set_ic = true; 3114 else if (!priv->tx_coal_frames) 3115 set_ic = false; 3116 else if (tx_packets > priv->tx_coal_frames) 3117 set_ic = true; 3118 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3119 set_ic = true; 3120 else 3121 set_ic = false; 3122 3123 if (set_ic) { 3124 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3125 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3126 else 3127 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3128 3129 tx_q->tx_count_frames = 0; 3130 stmmac_set_tx_ic(priv, desc); 3131 priv->xstats.tx_set_ic_bit++; 3132 } 3133 3134 /* We've used all descriptors we need for this skb, however, 3135 * advance cur_tx so that it references a fresh descriptor. 3136 * ndo_start_xmit will fill this descriptor the next time it's 3137 * called and stmmac_tx_clean may clean up to this descriptor. 3138 */ 3139 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3140 3141 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3142 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3143 __func__); 3144 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3145 } 3146 3147 dev->stats.tx_bytes += skb->len; 3148 priv->xstats.tx_tso_frames++; 3149 priv->xstats.tx_tso_nfrags += nfrags; 3150 3151 if (priv->sarc_type) 3152 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3153 3154 skb_tx_timestamp(skb); 3155 3156 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3157 priv->hwts_tx_en)) { 3158 /* declare that device is doing timestamping */ 3159 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3160 stmmac_enable_tx_timestamp(priv, first); 3161 } 3162 3163 /* Complete the first descriptor before granting the DMA */ 3164 stmmac_prepare_tso_tx_desc(priv, first, 1, 3165 proto_hdr_len, 3166 pay_len, 3167 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3168 hdr / 4, (skb->len - proto_hdr_len)); 3169 3170 /* If context desc is used to change MSS */ 3171 if (mss_desc) { 3172 /* Make sure that first descriptor has been completely 3173 * written, including its own bit. This is because MSS is 3174 * actually before first descriptor, so we need to make 3175 * sure that MSS's own bit is the last thing written. 3176 */ 3177 dma_wmb(); 3178 stmmac_set_tx_owner(priv, mss_desc); 3179 } 3180 3181 /* The own bit must be the latest setting done when prepare the 3182 * descriptor and then barrier is needed to make sure that 3183 * all is coherent before granting the DMA engine. 3184 */ 3185 wmb(); 3186 3187 if (netif_msg_pktdata(priv)) { 3188 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3189 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3190 tx_q->cur_tx, first, nfrags); 3191 pr_info(">>> frame to be transmitted: "); 3192 print_pkt(skb->data, skb_headlen(skb)); 3193 } 3194 3195 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3196 3197 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3198 desc_size = sizeof(struct dma_edesc); 3199 else 3200 desc_size = sizeof(struct dma_desc); 3201 3202 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3203 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3204 stmmac_tx_timer_arm(priv, queue); 3205 3206 return NETDEV_TX_OK; 3207 3208 dma_map_err: 3209 dev_err(priv->device, "Tx dma map failed\n"); 3210 dev_kfree_skb(skb); 3211 priv->dev->stats.tx_dropped++; 3212 return NETDEV_TX_OK; 3213 } 3214 3215 /** 3216 * stmmac_xmit - Tx entry point of the driver 3217 * @skb : the socket buffer 3218 * @dev : device pointer 3219 * Description : this is the tx entry point of the driver. 3220 * It programs the chain or the ring and supports oversized frames 3221 * and SG feature. 3222 */ 3223 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3224 { 3225 unsigned int first_entry, tx_packets, enh_desc; 3226 struct stmmac_priv *priv = netdev_priv(dev); 3227 unsigned int nopaged_len = skb_headlen(skb); 3228 int i, csum_insertion = 0, is_jumbo = 0; 3229 u32 queue = skb_get_queue_mapping(skb); 3230 int nfrags = skb_shinfo(skb)->nr_frags; 3231 int gso = skb_shinfo(skb)->gso_type; 3232 struct dma_edesc *tbs_desc = NULL; 3233 int entry, desc_size, first_tx; 3234 struct dma_desc *desc, *first; 3235 struct stmmac_tx_queue *tx_q; 3236 bool has_vlan, set_ic; 3237 dma_addr_t des; 3238 3239 tx_q = &priv->tx_queue[queue]; 3240 first_tx = tx_q->cur_tx; 3241 3242 if (priv->tx_path_in_lpi_mode) 3243 stmmac_disable_eee_mode(priv); 3244 3245 /* Manage oversized TCP frames for GMAC4 device */ 3246 if (skb_is_gso(skb) && priv->tso) { 3247 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3248 return stmmac_tso_xmit(skb, dev); 3249 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3250 return stmmac_tso_xmit(skb, dev); 3251 } 3252 3253 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3254 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3255 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3256 queue)); 3257 /* This is a hard error, log it. */ 3258 netdev_err(priv->dev, 3259 "%s: Tx Ring full when queue awake\n", 3260 __func__); 3261 } 3262 return NETDEV_TX_BUSY; 3263 } 3264 3265 /* Check if VLAN can be inserted by HW */ 3266 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3267 3268 entry = tx_q->cur_tx; 3269 first_entry = entry; 3270 WARN_ON(tx_q->tx_skbuff[first_entry]); 3271 3272 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3273 3274 if (likely(priv->extend_desc)) 3275 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3276 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3277 desc = &tx_q->dma_entx[entry].basic; 3278 else 3279 desc = tx_q->dma_tx + entry; 3280 3281 first = desc; 3282 3283 if (has_vlan) 3284 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3285 3286 enh_desc = priv->plat->enh_desc; 3287 /* To program the descriptors according to the size of the frame */ 3288 if (enh_desc) 3289 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3290 3291 if (unlikely(is_jumbo)) { 3292 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3293 if (unlikely(entry < 0) && (entry != -EINVAL)) 3294 goto dma_map_err; 3295 } 3296 3297 for (i = 0; i < nfrags; i++) { 3298 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3299 int len = skb_frag_size(frag); 3300 bool last_segment = (i == (nfrags - 1)); 3301 3302 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3303 WARN_ON(tx_q->tx_skbuff[entry]); 3304 3305 if (likely(priv->extend_desc)) 3306 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3307 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3308 desc = &tx_q->dma_entx[entry].basic; 3309 else 3310 desc = tx_q->dma_tx + entry; 3311 3312 des = skb_frag_dma_map(priv->device, frag, 0, len, 3313 DMA_TO_DEVICE); 3314 if (dma_mapping_error(priv->device, des)) 3315 goto dma_map_err; /* should reuse desc w/o issues */ 3316 3317 tx_q->tx_skbuff_dma[entry].buf = des; 3318 3319 stmmac_set_desc_addr(priv, desc, des); 3320 3321 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3322 tx_q->tx_skbuff_dma[entry].len = len; 3323 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3324 3325 /* Prepare the descriptor and set the own bit too */ 3326 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3327 priv->mode, 1, last_segment, skb->len); 3328 } 3329 3330 /* Only the last descriptor gets to point to the skb. */ 3331 tx_q->tx_skbuff[entry] = skb; 3332 3333 /* According to the coalesce parameter the IC bit for the latest 3334 * segment is reset and the timer re-started to clean the tx status. 3335 * This approach takes care about the fragments: desc is the first 3336 * element in case of no SG. 3337 */ 3338 tx_packets = (entry + 1) - first_tx; 3339 tx_q->tx_count_frames += tx_packets; 3340 3341 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3342 set_ic = true; 3343 else if (!priv->tx_coal_frames) 3344 set_ic = false; 3345 else if (tx_packets > priv->tx_coal_frames) 3346 set_ic = true; 3347 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3348 set_ic = true; 3349 else 3350 set_ic = false; 3351 3352 if (set_ic) { 3353 if (likely(priv->extend_desc)) 3354 desc = &tx_q->dma_etx[entry].basic; 3355 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3356 desc = &tx_q->dma_entx[entry].basic; 3357 else 3358 desc = &tx_q->dma_tx[entry]; 3359 3360 tx_q->tx_count_frames = 0; 3361 stmmac_set_tx_ic(priv, desc); 3362 priv->xstats.tx_set_ic_bit++; 3363 } 3364 3365 /* We've used all descriptors we need for this skb, however, 3366 * advance cur_tx so that it references a fresh descriptor. 3367 * ndo_start_xmit will fill this descriptor the next time it's 3368 * called and stmmac_tx_clean may clean up to this descriptor. 3369 */ 3370 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3371 tx_q->cur_tx = entry; 3372 3373 if (netif_msg_pktdata(priv)) { 3374 netdev_dbg(priv->dev, 3375 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3376 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3377 entry, first, nfrags); 3378 3379 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3380 print_pkt(skb->data, skb->len); 3381 } 3382 3383 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3384 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3385 __func__); 3386 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3387 } 3388 3389 dev->stats.tx_bytes += skb->len; 3390 3391 if (priv->sarc_type) 3392 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3393 3394 skb_tx_timestamp(skb); 3395 3396 /* Ready to fill the first descriptor and set the OWN bit w/o any 3397 * problems because all the descriptors are actually ready to be 3398 * passed to the DMA engine. 3399 */ 3400 if (likely(!is_jumbo)) { 3401 bool last_segment = (nfrags == 0); 3402 3403 des = dma_map_single(priv->device, skb->data, 3404 nopaged_len, DMA_TO_DEVICE); 3405 if (dma_mapping_error(priv->device, des)) 3406 goto dma_map_err; 3407 3408 tx_q->tx_skbuff_dma[first_entry].buf = des; 3409 3410 stmmac_set_desc_addr(priv, first, des); 3411 3412 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3413 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3414 3415 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3416 priv->hwts_tx_en)) { 3417 /* declare that device is doing timestamping */ 3418 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3419 stmmac_enable_tx_timestamp(priv, first); 3420 } 3421 3422 /* Prepare the first descriptor setting the OWN bit too */ 3423 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3424 csum_insertion, priv->mode, 0, last_segment, 3425 skb->len); 3426 } 3427 3428 if (tx_q->tbs & STMMAC_TBS_EN) { 3429 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3430 3431 tbs_desc = &tx_q->dma_entx[first_entry]; 3432 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3433 } 3434 3435 stmmac_set_tx_owner(priv, first); 3436 3437 /* The own bit must be the latest setting done when prepare the 3438 * descriptor and then barrier is needed to make sure that 3439 * all is coherent before granting the DMA engine. 3440 */ 3441 wmb(); 3442 3443 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3444 3445 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3446 3447 if (likely(priv->extend_desc)) 3448 desc_size = sizeof(struct dma_extended_desc); 3449 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3450 desc_size = sizeof(struct dma_edesc); 3451 else 3452 desc_size = sizeof(struct dma_desc); 3453 3454 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3455 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3456 stmmac_tx_timer_arm(priv, queue); 3457 3458 return NETDEV_TX_OK; 3459 3460 dma_map_err: 3461 netdev_err(priv->dev, "Tx DMA map failed\n"); 3462 dev_kfree_skb(skb); 3463 priv->dev->stats.tx_dropped++; 3464 return NETDEV_TX_OK; 3465 } 3466 3467 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3468 { 3469 struct vlan_ethhdr *veth; 3470 __be16 vlan_proto; 3471 u16 vlanid; 3472 3473 veth = (struct vlan_ethhdr *)skb->data; 3474 vlan_proto = veth->h_vlan_proto; 3475 3476 if ((vlan_proto == htons(ETH_P_8021Q) && 3477 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3478 (vlan_proto == htons(ETH_P_8021AD) && 3479 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3480 /* pop the vlan tag */ 3481 vlanid = ntohs(veth->h_vlan_TCI); 3482 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3483 skb_pull(skb, VLAN_HLEN); 3484 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3485 } 3486 } 3487 3488 3489 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3490 { 3491 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3492 return 0; 3493 3494 return 1; 3495 } 3496 3497 /** 3498 * stmmac_rx_refill - refill used skb preallocated buffers 3499 * @priv: driver private structure 3500 * @queue: RX queue index 3501 * Description : this is to reallocate the skb for the reception process 3502 * that is based on zero-copy. 3503 */ 3504 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3505 { 3506 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3507 int len, dirty = stmmac_rx_dirty(priv, queue); 3508 unsigned int entry = rx_q->dirty_rx; 3509 3510 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3511 3512 while (dirty-- > 0) { 3513 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3514 struct dma_desc *p; 3515 bool use_rx_wd; 3516 3517 if (priv->extend_desc) 3518 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3519 else 3520 p = rx_q->dma_rx + entry; 3521 3522 if (!buf->page) { 3523 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3524 if (!buf->page) 3525 break; 3526 } 3527 3528 if (priv->sph && !buf->sec_page) { 3529 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3530 if (!buf->sec_page) 3531 break; 3532 3533 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3534 3535 dma_sync_single_for_device(priv->device, buf->sec_addr, 3536 len, DMA_FROM_DEVICE); 3537 } 3538 3539 buf->addr = page_pool_get_dma_addr(buf->page); 3540 3541 /* Sync whole allocation to device. This will invalidate old 3542 * data. 3543 */ 3544 dma_sync_single_for_device(priv->device, buf->addr, len, 3545 DMA_FROM_DEVICE); 3546 3547 stmmac_set_desc_addr(priv, p, buf->addr); 3548 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3549 stmmac_refill_desc3(priv, rx_q, p); 3550 3551 rx_q->rx_count_frames++; 3552 rx_q->rx_count_frames += priv->rx_coal_frames; 3553 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3554 rx_q->rx_count_frames = 0; 3555 3556 use_rx_wd = !priv->rx_coal_frames; 3557 use_rx_wd |= rx_q->rx_count_frames > 0; 3558 if (!priv->use_riwt) 3559 use_rx_wd = false; 3560 3561 dma_wmb(); 3562 stmmac_set_rx_owner(priv, p, use_rx_wd); 3563 3564 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3565 } 3566 rx_q->dirty_rx = entry; 3567 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3568 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3569 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3570 } 3571 3572 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3573 struct dma_desc *p, 3574 int status, unsigned int len) 3575 { 3576 int ret, coe = priv->hw->rx_csum; 3577 unsigned int plen = 0, hlen = 0; 3578 3579 /* Not first descriptor, buffer is always zero */ 3580 if (priv->sph && len) 3581 return 0; 3582 3583 /* First descriptor, get split header length */ 3584 ret = stmmac_get_rx_header_len(priv, p, &hlen); 3585 if (priv->sph && hlen) { 3586 priv->xstats.rx_split_hdr_pkt_n++; 3587 return hlen; 3588 } 3589 3590 /* First descriptor, not last descriptor and not split header */ 3591 if (status & rx_not_ls) 3592 return priv->dma_buf_sz; 3593 3594 plen = stmmac_get_rx_frame_len(priv, p, coe); 3595 3596 /* First descriptor and last descriptor and not split header */ 3597 return min_t(unsigned int, priv->dma_buf_sz, plen); 3598 } 3599 3600 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3601 struct dma_desc *p, 3602 int status, unsigned int len) 3603 { 3604 int coe = priv->hw->rx_csum; 3605 unsigned int plen = 0; 3606 3607 /* Not split header, buffer is not available */ 3608 if (!priv->sph) 3609 return 0; 3610 3611 /* Not last descriptor */ 3612 if (status & rx_not_ls) 3613 return priv->dma_buf_sz; 3614 3615 plen = stmmac_get_rx_frame_len(priv, p, coe); 3616 3617 /* Last descriptor */ 3618 return plen - len; 3619 } 3620 3621 /** 3622 * stmmac_rx - manage the receive process 3623 * @priv: driver private structure 3624 * @limit: napi bugget 3625 * @queue: RX queue index. 3626 * Description : this the function called by the napi poll method. 3627 * It gets all the frames inside the ring. 3628 */ 3629 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3630 { 3631 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3632 struct stmmac_channel *ch = &priv->channel[queue]; 3633 unsigned int count = 0, error = 0, len = 0; 3634 int status = 0, coe = priv->hw->rx_csum; 3635 unsigned int next_entry = rx_q->cur_rx; 3636 struct sk_buff *skb = NULL; 3637 3638 if (netif_msg_rx_status(priv)) { 3639 void *rx_head; 3640 3641 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3642 if (priv->extend_desc) 3643 rx_head = (void *)rx_q->dma_erx; 3644 else 3645 rx_head = (void *)rx_q->dma_rx; 3646 3647 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3648 } 3649 while (count < limit) { 3650 unsigned int buf1_len = 0, buf2_len = 0; 3651 enum pkt_hash_types hash_type; 3652 struct stmmac_rx_buffer *buf; 3653 struct dma_desc *np, *p; 3654 int entry; 3655 u32 hash; 3656 3657 if (!count && rx_q->state_saved) { 3658 skb = rx_q->state.skb; 3659 error = rx_q->state.error; 3660 len = rx_q->state.len; 3661 } else { 3662 rx_q->state_saved = false; 3663 skb = NULL; 3664 error = 0; 3665 len = 0; 3666 } 3667 3668 if (count >= limit) 3669 break; 3670 3671 read_again: 3672 buf1_len = 0; 3673 buf2_len = 0; 3674 entry = next_entry; 3675 buf = &rx_q->buf_pool[entry]; 3676 3677 if (priv->extend_desc) 3678 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3679 else 3680 p = rx_q->dma_rx + entry; 3681 3682 /* read the status of the incoming frame */ 3683 status = stmmac_rx_status(priv, &priv->dev->stats, 3684 &priv->xstats, p); 3685 /* check if managed by the DMA otherwise go ahead */ 3686 if (unlikely(status & dma_own)) 3687 break; 3688 3689 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3690 next_entry = rx_q->cur_rx; 3691 3692 if (priv->extend_desc) 3693 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3694 else 3695 np = rx_q->dma_rx + next_entry; 3696 3697 prefetch(np); 3698 3699 if (priv->extend_desc) 3700 stmmac_rx_extended_status(priv, &priv->dev->stats, 3701 &priv->xstats, rx_q->dma_erx + entry); 3702 if (unlikely(status == discard_frame)) { 3703 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3704 buf->page = NULL; 3705 error = 1; 3706 if (!priv->hwts_rx_en) 3707 priv->dev->stats.rx_errors++; 3708 } 3709 3710 if (unlikely(error && (status & rx_not_ls))) 3711 goto read_again; 3712 if (unlikely(error)) { 3713 dev_kfree_skb(skb); 3714 skb = NULL; 3715 count++; 3716 continue; 3717 } 3718 3719 /* Buffer is good. Go on. */ 3720 3721 prefetch(page_address(buf->page)); 3722 if (buf->sec_page) 3723 prefetch(page_address(buf->sec_page)); 3724 3725 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3726 len += buf1_len; 3727 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3728 len += buf2_len; 3729 3730 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3731 * Type frames (LLC/LLC-SNAP) 3732 * 3733 * llc_snap is never checked in GMAC >= 4, so this ACS 3734 * feature is always disabled and packets need to be 3735 * stripped manually. 3736 */ 3737 if (likely(!(status & rx_not_ls)) && 3738 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3739 unlikely(status != llc_snap))) { 3740 if (buf2_len) 3741 buf2_len -= ETH_FCS_LEN; 3742 else 3743 buf1_len -= ETH_FCS_LEN; 3744 3745 len -= ETH_FCS_LEN; 3746 } 3747 3748 if (!skb) { 3749 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3750 if (!skb) { 3751 priv->dev->stats.rx_dropped++; 3752 count++; 3753 goto drain_data; 3754 } 3755 3756 dma_sync_single_for_cpu(priv->device, buf->addr, 3757 buf1_len, DMA_FROM_DEVICE); 3758 skb_copy_to_linear_data(skb, page_address(buf->page), 3759 buf1_len); 3760 skb_put(skb, buf1_len); 3761 3762 /* Data payload copied into SKB, page ready for recycle */ 3763 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3764 buf->page = NULL; 3765 } else if (buf1_len) { 3766 dma_sync_single_for_cpu(priv->device, buf->addr, 3767 buf1_len, DMA_FROM_DEVICE); 3768 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3769 buf->page, 0, buf1_len, 3770 priv->dma_buf_sz); 3771 3772 /* Data payload appended into SKB */ 3773 page_pool_release_page(rx_q->page_pool, buf->page); 3774 buf->page = NULL; 3775 } 3776 3777 if (buf2_len) { 3778 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3779 buf2_len, DMA_FROM_DEVICE); 3780 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3781 buf->sec_page, 0, buf2_len, 3782 priv->dma_buf_sz); 3783 3784 /* Data payload appended into SKB */ 3785 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3786 buf->sec_page = NULL; 3787 } 3788 3789 drain_data: 3790 if (likely(status & rx_not_ls)) 3791 goto read_again; 3792 if (!skb) 3793 continue; 3794 3795 /* Got entire packet into SKB. Finish it. */ 3796 3797 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3798 stmmac_rx_vlan(priv->dev, skb); 3799 skb->protocol = eth_type_trans(skb, priv->dev); 3800 3801 if (unlikely(!coe)) 3802 skb_checksum_none_assert(skb); 3803 else 3804 skb->ip_summed = CHECKSUM_UNNECESSARY; 3805 3806 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3807 skb_set_hash(skb, hash, hash_type); 3808 3809 skb_record_rx_queue(skb, queue); 3810 napi_gro_receive(&ch->rx_napi, skb); 3811 skb = NULL; 3812 3813 priv->dev->stats.rx_packets++; 3814 priv->dev->stats.rx_bytes += len; 3815 count++; 3816 } 3817 3818 if (status & rx_not_ls || skb) { 3819 rx_q->state_saved = true; 3820 rx_q->state.skb = skb; 3821 rx_q->state.error = error; 3822 rx_q->state.len = len; 3823 } 3824 3825 stmmac_rx_refill(priv, queue); 3826 3827 priv->xstats.rx_pkt_n += count; 3828 3829 return count; 3830 } 3831 3832 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3833 { 3834 struct stmmac_channel *ch = 3835 container_of(napi, struct stmmac_channel, rx_napi); 3836 struct stmmac_priv *priv = ch->priv_data; 3837 u32 chan = ch->index; 3838 int work_done; 3839 3840 priv->xstats.napi_poll++; 3841 3842 work_done = stmmac_rx(priv, budget, chan); 3843 if (work_done < budget && napi_complete_done(napi, work_done)) { 3844 unsigned long flags; 3845 3846 spin_lock_irqsave(&ch->lock, flags); 3847 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3848 spin_unlock_irqrestore(&ch->lock, flags); 3849 } 3850 3851 return work_done; 3852 } 3853 3854 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3855 { 3856 struct stmmac_channel *ch = 3857 container_of(napi, struct stmmac_channel, tx_napi); 3858 struct stmmac_priv *priv = ch->priv_data; 3859 u32 chan = ch->index; 3860 int work_done; 3861 3862 priv->xstats.napi_poll++; 3863 3864 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3865 work_done = min(work_done, budget); 3866 3867 if (work_done < budget && napi_complete_done(napi, work_done)) { 3868 unsigned long flags; 3869 3870 spin_lock_irqsave(&ch->lock, flags); 3871 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3872 spin_unlock_irqrestore(&ch->lock, flags); 3873 } 3874 3875 return work_done; 3876 } 3877 3878 /** 3879 * stmmac_tx_timeout 3880 * @dev : Pointer to net device structure 3881 * Description: this function is called when a packet transmission fails to 3882 * complete within a reasonable time. The driver will mark the error in the 3883 * netdev structure and arrange for the device to be reset to a sane state 3884 * in order to transmit a new packet. 3885 */ 3886 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3887 { 3888 struct stmmac_priv *priv = netdev_priv(dev); 3889 3890 stmmac_global_err(priv); 3891 } 3892 3893 /** 3894 * stmmac_set_rx_mode - entry point for multicast addressing 3895 * @dev : pointer to the device structure 3896 * Description: 3897 * This function is a driver entry point which gets called by the kernel 3898 * whenever multicast addresses must be enabled/disabled. 3899 * Return value: 3900 * void. 3901 */ 3902 static void stmmac_set_rx_mode(struct net_device *dev) 3903 { 3904 struct stmmac_priv *priv = netdev_priv(dev); 3905 3906 stmmac_set_filter(priv, priv->hw, dev); 3907 } 3908 3909 /** 3910 * stmmac_change_mtu - entry point to change MTU size for the device. 3911 * @dev : device pointer. 3912 * @new_mtu : the new MTU size for the device. 3913 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3914 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3915 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3916 * Return value: 3917 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3918 * file on failure. 3919 */ 3920 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3921 { 3922 struct stmmac_priv *priv = netdev_priv(dev); 3923 int txfifosz = priv->plat->tx_fifo_size; 3924 3925 if (txfifosz == 0) 3926 txfifosz = priv->dma_cap.tx_fifo_size; 3927 3928 txfifosz /= priv->plat->tx_queues_to_use; 3929 3930 if (netif_running(dev)) { 3931 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3932 return -EBUSY; 3933 } 3934 3935 new_mtu = STMMAC_ALIGN(new_mtu); 3936 3937 /* If condition true, FIFO is too small or MTU too large */ 3938 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 3939 return -EINVAL; 3940 3941 dev->mtu = new_mtu; 3942 3943 netdev_update_features(dev); 3944 3945 return 0; 3946 } 3947 3948 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3949 netdev_features_t features) 3950 { 3951 struct stmmac_priv *priv = netdev_priv(dev); 3952 3953 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3954 features &= ~NETIF_F_RXCSUM; 3955 3956 if (!priv->plat->tx_coe) 3957 features &= ~NETIF_F_CSUM_MASK; 3958 3959 /* Some GMAC devices have a bugged Jumbo frame support that 3960 * needs to have the Tx COE disabled for oversized frames 3961 * (due to limited buffer sizes). In this case we disable 3962 * the TX csum insertion in the TDES and not use SF. 3963 */ 3964 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3965 features &= ~NETIF_F_CSUM_MASK; 3966 3967 /* Disable tso if asked by ethtool */ 3968 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3969 if (features & NETIF_F_TSO) 3970 priv->tso = true; 3971 else 3972 priv->tso = false; 3973 } 3974 3975 return features; 3976 } 3977 3978 static int stmmac_set_features(struct net_device *netdev, 3979 netdev_features_t features) 3980 { 3981 struct stmmac_priv *priv = netdev_priv(netdev); 3982 bool sph_en; 3983 u32 chan; 3984 3985 /* Keep the COE Type in case of csum is supporting */ 3986 if (features & NETIF_F_RXCSUM) 3987 priv->hw->rx_csum = priv->plat->rx_coe; 3988 else 3989 priv->hw->rx_csum = 0; 3990 /* No check needed because rx_coe has been set before and it will be 3991 * fixed in case of issue. 3992 */ 3993 stmmac_rx_ipc(priv, priv->hw); 3994 3995 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3996 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 3997 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3998 3999 return 0; 4000 } 4001 4002 /** 4003 * stmmac_interrupt - main ISR 4004 * @irq: interrupt number. 4005 * @dev_id: to pass the net device pointer. 4006 * Description: this is the main driver interrupt service routine. 4007 * It can call: 4008 * o DMA service routine (to manage incoming frame reception and transmission 4009 * status) 4010 * o Core interrupts to manage: remote wake-up, management counter, LPI 4011 * interrupts. 4012 */ 4013 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4014 { 4015 struct net_device *dev = (struct net_device *)dev_id; 4016 struct stmmac_priv *priv = netdev_priv(dev); 4017 u32 rx_cnt = priv->plat->rx_queues_to_use; 4018 u32 tx_cnt = priv->plat->tx_queues_to_use; 4019 u32 queues_count; 4020 u32 queue; 4021 bool xmac; 4022 4023 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4024 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4025 4026 if (priv->irq_wake) 4027 pm_wakeup_event(priv->device, 0); 4028 4029 if (unlikely(!dev)) { 4030 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 4031 return IRQ_NONE; 4032 } 4033 4034 /* Check if adapter is up */ 4035 if (test_bit(STMMAC_DOWN, &priv->state)) 4036 return IRQ_HANDLED; 4037 /* Check if a fatal error happened */ 4038 if (stmmac_safety_feat_interrupt(priv)) 4039 return IRQ_HANDLED; 4040 4041 /* To handle GMAC own interrupts */ 4042 if ((priv->plat->has_gmac) || xmac) { 4043 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4044 int mtl_status; 4045 4046 if (unlikely(status)) { 4047 /* For LPI we need to save the tx status */ 4048 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4049 priv->tx_path_in_lpi_mode = true; 4050 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4051 priv->tx_path_in_lpi_mode = false; 4052 } 4053 4054 for (queue = 0; queue < queues_count; queue++) { 4055 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4056 4057 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4058 queue); 4059 if (mtl_status != -EINVAL) 4060 status |= mtl_status; 4061 4062 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4063 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4064 rx_q->rx_tail_addr, 4065 queue); 4066 } 4067 4068 /* PCS link status */ 4069 if (priv->hw->pcs) { 4070 if (priv->xstats.pcs_link) 4071 netif_carrier_on(dev); 4072 else 4073 netif_carrier_off(dev); 4074 } 4075 } 4076 4077 /* To handle DMA interrupts */ 4078 stmmac_dma_interrupt(priv); 4079 4080 return IRQ_HANDLED; 4081 } 4082 4083 #ifdef CONFIG_NET_POLL_CONTROLLER 4084 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4085 * to allow network I/O with interrupts disabled. 4086 */ 4087 static void stmmac_poll_controller(struct net_device *dev) 4088 { 4089 disable_irq(dev->irq); 4090 stmmac_interrupt(dev->irq, dev); 4091 enable_irq(dev->irq); 4092 } 4093 #endif 4094 4095 /** 4096 * stmmac_ioctl - Entry point for the Ioctl 4097 * @dev: Device pointer. 4098 * @rq: An IOCTL specefic structure, that can contain a pointer to 4099 * a proprietary structure used to pass information to the driver. 4100 * @cmd: IOCTL command 4101 * Description: 4102 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4103 */ 4104 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4105 { 4106 struct stmmac_priv *priv = netdev_priv (dev); 4107 int ret = -EOPNOTSUPP; 4108 4109 if (!netif_running(dev)) 4110 return -EINVAL; 4111 4112 switch (cmd) { 4113 case SIOCGMIIPHY: 4114 case SIOCGMIIREG: 4115 case SIOCSMIIREG: 4116 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4117 break; 4118 case SIOCSHWTSTAMP: 4119 ret = stmmac_hwtstamp_set(dev, rq); 4120 break; 4121 case SIOCGHWTSTAMP: 4122 ret = stmmac_hwtstamp_get(dev, rq); 4123 break; 4124 default: 4125 break; 4126 } 4127 4128 return ret; 4129 } 4130 4131 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4132 void *cb_priv) 4133 { 4134 struct stmmac_priv *priv = cb_priv; 4135 int ret = -EOPNOTSUPP; 4136 4137 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4138 return ret; 4139 4140 stmmac_disable_all_queues(priv); 4141 4142 switch (type) { 4143 case TC_SETUP_CLSU32: 4144 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4145 break; 4146 case TC_SETUP_CLSFLOWER: 4147 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4148 break; 4149 default: 4150 break; 4151 } 4152 4153 stmmac_enable_all_queues(priv); 4154 return ret; 4155 } 4156 4157 static LIST_HEAD(stmmac_block_cb_list); 4158 4159 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4160 void *type_data) 4161 { 4162 struct stmmac_priv *priv = netdev_priv(ndev); 4163 4164 switch (type) { 4165 case TC_SETUP_BLOCK: 4166 return flow_block_cb_setup_simple(type_data, 4167 &stmmac_block_cb_list, 4168 stmmac_setup_tc_block_cb, 4169 priv, priv, true); 4170 case TC_SETUP_QDISC_CBS: 4171 return stmmac_tc_setup_cbs(priv, priv, type_data); 4172 case TC_SETUP_QDISC_TAPRIO: 4173 return stmmac_tc_setup_taprio(priv, priv, type_data); 4174 case TC_SETUP_QDISC_ETF: 4175 return stmmac_tc_setup_etf(priv, priv, type_data); 4176 default: 4177 return -EOPNOTSUPP; 4178 } 4179 } 4180 4181 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4182 struct net_device *sb_dev) 4183 { 4184 int gso = skb_shinfo(skb)->gso_type; 4185 4186 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4187 /* 4188 * There is no way to determine the number of TSO/USO 4189 * capable Queues. Let's use always the Queue 0 4190 * because if TSO/USO is supported then at least this 4191 * one will be capable. 4192 */ 4193 return 0; 4194 } 4195 4196 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4197 } 4198 4199 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4200 { 4201 struct stmmac_priv *priv = netdev_priv(ndev); 4202 int ret = 0; 4203 4204 ret = eth_mac_addr(ndev, addr); 4205 if (ret) 4206 return ret; 4207 4208 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4209 4210 return ret; 4211 } 4212 4213 #ifdef CONFIG_DEBUG_FS 4214 static struct dentry *stmmac_fs_dir; 4215 4216 static void sysfs_display_ring(void *head, int size, int extend_desc, 4217 struct seq_file *seq) 4218 { 4219 int i; 4220 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4221 struct dma_desc *p = (struct dma_desc *)head; 4222 4223 for (i = 0; i < size; i++) { 4224 if (extend_desc) { 4225 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4226 i, (unsigned int)virt_to_phys(ep), 4227 le32_to_cpu(ep->basic.des0), 4228 le32_to_cpu(ep->basic.des1), 4229 le32_to_cpu(ep->basic.des2), 4230 le32_to_cpu(ep->basic.des3)); 4231 ep++; 4232 } else { 4233 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4234 i, (unsigned int)virt_to_phys(p), 4235 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4236 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4237 p++; 4238 } 4239 seq_printf(seq, "\n"); 4240 } 4241 } 4242 4243 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4244 { 4245 struct net_device *dev = seq->private; 4246 struct stmmac_priv *priv = netdev_priv(dev); 4247 u32 rx_count = priv->plat->rx_queues_to_use; 4248 u32 tx_count = priv->plat->tx_queues_to_use; 4249 u32 queue; 4250 4251 if ((dev->flags & IFF_UP) == 0) 4252 return 0; 4253 4254 for (queue = 0; queue < rx_count; queue++) { 4255 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4256 4257 seq_printf(seq, "RX Queue %d:\n", queue); 4258 4259 if (priv->extend_desc) { 4260 seq_printf(seq, "Extended descriptor ring:\n"); 4261 sysfs_display_ring((void *)rx_q->dma_erx, 4262 DMA_RX_SIZE, 1, seq); 4263 } else { 4264 seq_printf(seq, "Descriptor ring:\n"); 4265 sysfs_display_ring((void *)rx_q->dma_rx, 4266 DMA_RX_SIZE, 0, seq); 4267 } 4268 } 4269 4270 for (queue = 0; queue < tx_count; queue++) { 4271 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4272 4273 seq_printf(seq, "TX Queue %d:\n", queue); 4274 4275 if (priv->extend_desc) { 4276 seq_printf(seq, "Extended descriptor ring:\n"); 4277 sysfs_display_ring((void *)tx_q->dma_etx, 4278 DMA_TX_SIZE, 1, seq); 4279 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4280 seq_printf(seq, "Descriptor ring:\n"); 4281 sysfs_display_ring((void *)tx_q->dma_tx, 4282 DMA_TX_SIZE, 0, seq); 4283 } 4284 } 4285 4286 return 0; 4287 } 4288 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4289 4290 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4291 { 4292 struct net_device *dev = seq->private; 4293 struct stmmac_priv *priv = netdev_priv(dev); 4294 4295 if (!priv->hw_cap_support) { 4296 seq_printf(seq, "DMA HW features not supported\n"); 4297 return 0; 4298 } 4299 4300 seq_printf(seq, "==============================\n"); 4301 seq_printf(seq, "\tDMA HW features\n"); 4302 seq_printf(seq, "==============================\n"); 4303 4304 seq_printf(seq, "\t10/100 Mbps: %s\n", 4305 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4306 seq_printf(seq, "\t1000 Mbps: %s\n", 4307 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4308 seq_printf(seq, "\tHalf duplex: %s\n", 4309 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4310 seq_printf(seq, "\tHash Filter: %s\n", 4311 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4312 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4313 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4314 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4315 (priv->dma_cap.pcs) ? "Y" : "N"); 4316 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4317 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4318 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4319 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4320 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4321 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4322 seq_printf(seq, "\tRMON module: %s\n", 4323 (priv->dma_cap.rmon) ? "Y" : "N"); 4324 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4325 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4326 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4327 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4328 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4329 (priv->dma_cap.eee) ? "Y" : "N"); 4330 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4331 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4332 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4333 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4334 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4335 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4336 } else { 4337 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4338 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4339 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4340 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4341 } 4342 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4343 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4344 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4345 priv->dma_cap.number_rx_channel); 4346 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4347 priv->dma_cap.number_tx_channel); 4348 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4349 priv->dma_cap.number_rx_queues); 4350 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4351 priv->dma_cap.number_tx_queues); 4352 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4353 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4354 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4355 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4356 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4357 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4358 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4359 priv->dma_cap.pps_out_num); 4360 seq_printf(seq, "\tSafety Features: %s\n", 4361 priv->dma_cap.asp ? "Y" : "N"); 4362 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4363 priv->dma_cap.frpsel ? "Y" : "N"); 4364 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4365 priv->dma_cap.addr64); 4366 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4367 priv->dma_cap.rssen ? "Y" : "N"); 4368 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4369 priv->dma_cap.vlhash ? "Y" : "N"); 4370 seq_printf(seq, "\tSplit Header: %s\n", 4371 priv->dma_cap.sphen ? "Y" : "N"); 4372 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4373 priv->dma_cap.vlins ? "Y" : "N"); 4374 seq_printf(seq, "\tDouble VLAN: %s\n", 4375 priv->dma_cap.dvlan ? "Y" : "N"); 4376 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4377 priv->dma_cap.l3l4fnum); 4378 seq_printf(seq, "\tARP Offloading: %s\n", 4379 priv->dma_cap.arpoffsel ? "Y" : "N"); 4380 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4381 priv->dma_cap.estsel ? "Y" : "N"); 4382 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4383 priv->dma_cap.fpesel ? "Y" : "N"); 4384 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4385 priv->dma_cap.tbssel ? "Y" : "N"); 4386 return 0; 4387 } 4388 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4389 4390 /* Use network device events to rename debugfs file entries. 4391 */ 4392 static int stmmac_device_event(struct notifier_block *unused, 4393 unsigned long event, void *ptr) 4394 { 4395 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4396 struct stmmac_priv *priv = netdev_priv(dev); 4397 4398 if (dev->netdev_ops != &stmmac_netdev_ops) 4399 goto done; 4400 4401 switch (event) { 4402 case NETDEV_CHANGENAME: 4403 if (priv->dbgfs_dir) 4404 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4405 priv->dbgfs_dir, 4406 stmmac_fs_dir, 4407 dev->name); 4408 break; 4409 } 4410 done: 4411 return NOTIFY_DONE; 4412 } 4413 4414 static struct notifier_block stmmac_notifier = { 4415 .notifier_call = stmmac_device_event, 4416 }; 4417 4418 static void stmmac_init_fs(struct net_device *dev) 4419 { 4420 struct stmmac_priv *priv = netdev_priv(dev); 4421 4422 rtnl_lock(); 4423 4424 /* Create per netdev entries */ 4425 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4426 4427 /* Entry to report DMA RX/TX rings */ 4428 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4429 &stmmac_rings_status_fops); 4430 4431 /* Entry to report the DMA HW features */ 4432 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4433 &stmmac_dma_cap_fops); 4434 4435 rtnl_unlock(); 4436 } 4437 4438 static void stmmac_exit_fs(struct net_device *dev) 4439 { 4440 struct stmmac_priv *priv = netdev_priv(dev); 4441 4442 debugfs_remove_recursive(priv->dbgfs_dir); 4443 } 4444 #endif /* CONFIG_DEBUG_FS */ 4445 4446 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4447 { 4448 unsigned char *data = (unsigned char *)&vid_le; 4449 unsigned char data_byte = 0; 4450 u32 crc = ~0x0; 4451 u32 temp = 0; 4452 int i, bits; 4453 4454 bits = get_bitmask_order(VLAN_VID_MASK); 4455 for (i = 0; i < bits; i++) { 4456 if ((i % 8) == 0) 4457 data_byte = data[i / 8]; 4458 4459 temp = ((crc & 1) ^ data_byte) & 1; 4460 crc >>= 1; 4461 data_byte >>= 1; 4462 4463 if (temp) 4464 crc ^= 0xedb88320; 4465 } 4466 4467 return crc; 4468 } 4469 4470 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4471 { 4472 u32 crc, hash = 0; 4473 __le16 pmatch = 0; 4474 int count = 0; 4475 u16 vid = 0; 4476 4477 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4478 __le16 vid_le = cpu_to_le16(vid); 4479 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4480 hash |= (1 << crc); 4481 count++; 4482 } 4483 4484 if (!priv->dma_cap.vlhash) { 4485 if (count > 2) /* VID = 0 always passes filter */ 4486 return -EOPNOTSUPP; 4487 4488 pmatch = cpu_to_le16(vid); 4489 hash = 0; 4490 } 4491 4492 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4493 } 4494 4495 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4496 { 4497 struct stmmac_priv *priv = netdev_priv(ndev); 4498 bool is_double = false; 4499 int ret; 4500 4501 if (be16_to_cpu(proto) == ETH_P_8021AD) 4502 is_double = true; 4503 4504 set_bit(vid, priv->active_vlans); 4505 ret = stmmac_vlan_update(priv, is_double); 4506 if (ret) { 4507 clear_bit(vid, priv->active_vlans); 4508 return ret; 4509 } 4510 4511 return ret; 4512 } 4513 4514 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4515 { 4516 struct stmmac_priv *priv = netdev_priv(ndev); 4517 bool is_double = false; 4518 4519 if (be16_to_cpu(proto) == ETH_P_8021AD) 4520 is_double = true; 4521 4522 clear_bit(vid, priv->active_vlans); 4523 return stmmac_vlan_update(priv, is_double); 4524 } 4525 4526 static const struct net_device_ops stmmac_netdev_ops = { 4527 .ndo_open = stmmac_open, 4528 .ndo_start_xmit = stmmac_xmit, 4529 .ndo_stop = stmmac_release, 4530 .ndo_change_mtu = stmmac_change_mtu, 4531 .ndo_fix_features = stmmac_fix_features, 4532 .ndo_set_features = stmmac_set_features, 4533 .ndo_set_rx_mode = stmmac_set_rx_mode, 4534 .ndo_tx_timeout = stmmac_tx_timeout, 4535 .ndo_do_ioctl = stmmac_ioctl, 4536 .ndo_setup_tc = stmmac_setup_tc, 4537 .ndo_select_queue = stmmac_select_queue, 4538 #ifdef CONFIG_NET_POLL_CONTROLLER 4539 .ndo_poll_controller = stmmac_poll_controller, 4540 #endif 4541 .ndo_set_mac_address = stmmac_set_mac_address, 4542 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4543 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4544 }; 4545 4546 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4547 { 4548 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4549 return; 4550 if (test_bit(STMMAC_DOWN, &priv->state)) 4551 return; 4552 4553 netdev_err(priv->dev, "Reset adapter.\n"); 4554 4555 rtnl_lock(); 4556 netif_trans_update(priv->dev); 4557 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4558 usleep_range(1000, 2000); 4559 4560 set_bit(STMMAC_DOWN, &priv->state); 4561 dev_close(priv->dev); 4562 dev_open(priv->dev, NULL); 4563 clear_bit(STMMAC_DOWN, &priv->state); 4564 clear_bit(STMMAC_RESETING, &priv->state); 4565 rtnl_unlock(); 4566 } 4567 4568 static void stmmac_service_task(struct work_struct *work) 4569 { 4570 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4571 service_task); 4572 4573 stmmac_reset_subtask(priv); 4574 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4575 } 4576 4577 /** 4578 * stmmac_hw_init - Init the MAC device 4579 * @priv: driver private structure 4580 * Description: this function is to configure the MAC device according to 4581 * some platform parameters or the HW capability register. It prepares the 4582 * driver to use either ring or chain modes and to setup either enhanced or 4583 * normal descriptors. 4584 */ 4585 static int stmmac_hw_init(struct stmmac_priv *priv) 4586 { 4587 int ret; 4588 4589 /* dwmac-sun8i only work in chain mode */ 4590 if (priv->plat->has_sun8i) 4591 chain_mode = 1; 4592 priv->chain_mode = chain_mode; 4593 4594 /* Initialize HW Interface */ 4595 ret = stmmac_hwif_init(priv); 4596 if (ret) 4597 return ret; 4598 4599 /* Get the HW capability (new GMAC newer than 3.50a) */ 4600 priv->hw_cap_support = stmmac_get_hw_features(priv); 4601 if (priv->hw_cap_support) { 4602 dev_info(priv->device, "DMA HW capability register supported\n"); 4603 4604 /* We can override some gmac/dma configuration fields: e.g. 4605 * enh_desc, tx_coe (e.g. that are passed through the 4606 * platform) with the values from the HW capability 4607 * register (if supported). 4608 */ 4609 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4610 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4611 priv->hw->pmt = priv->plat->pmt; 4612 if (priv->dma_cap.hash_tb_sz) { 4613 priv->hw->multicast_filter_bins = 4614 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4615 priv->hw->mcast_bits_log2 = 4616 ilog2(priv->hw->multicast_filter_bins); 4617 } 4618 4619 /* TXCOE doesn't work in thresh DMA mode */ 4620 if (priv->plat->force_thresh_dma_mode) 4621 priv->plat->tx_coe = 0; 4622 else 4623 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4624 4625 /* In case of GMAC4 rx_coe is from HW cap register. */ 4626 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4627 4628 if (priv->dma_cap.rx_coe_type2) 4629 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4630 else if (priv->dma_cap.rx_coe_type1) 4631 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4632 4633 } else { 4634 dev_info(priv->device, "No HW DMA feature register supported\n"); 4635 } 4636 4637 if (priv->plat->rx_coe) { 4638 priv->hw->rx_csum = priv->plat->rx_coe; 4639 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4640 if (priv->synopsys_id < DWMAC_CORE_4_00) 4641 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4642 } 4643 if (priv->plat->tx_coe) 4644 dev_info(priv->device, "TX Checksum insertion supported\n"); 4645 4646 if (priv->plat->pmt) { 4647 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4648 device_set_wakeup_capable(priv->device, 1); 4649 } 4650 4651 if (priv->dma_cap.tsoen) 4652 dev_info(priv->device, "TSO supported\n"); 4653 4654 /* Run HW quirks, if any */ 4655 if (priv->hwif_quirks) { 4656 ret = priv->hwif_quirks(priv); 4657 if (ret) 4658 return ret; 4659 } 4660 4661 /* Rx Watchdog is available in the COREs newer than the 3.40. 4662 * In some case, for example on bugged HW this feature 4663 * has to be disable and this can be done by passing the 4664 * riwt_off field from the platform. 4665 */ 4666 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4667 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4668 priv->use_riwt = 1; 4669 dev_info(priv->device, 4670 "Enable RX Mitigation via HW Watchdog Timer\n"); 4671 } 4672 4673 return 0; 4674 } 4675 4676 /** 4677 * stmmac_dvr_probe 4678 * @device: device pointer 4679 * @plat_dat: platform data pointer 4680 * @res: stmmac resource pointer 4681 * Description: this is the main probe function used to 4682 * call the alloc_etherdev, allocate the priv structure. 4683 * Return: 4684 * returns 0 on success, otherwise errno. 4685 */ 4686 int stmmac_dvr_probe(struct device *device, 4687 struct plat_stmmacenet_data *plat_dat, 4688 struct stmmac_resources *res) 4689 { 4690 struct net_device *ndev = NULL; 4691 struct stmmac_priv *priv; 4692 u32 queue, rxq, maxq; 4693 int i, ret = 0; 4694 4695 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4696 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4697 if (!ndev) 4698 return -ENOMEM; 4699 4700 SET_NETDEV_DEV(ndev, device); 4701 4702 priv = netdev_priv(ndev); 4703 priv->device = device; 4704 priv->dev = ndev; 4705 4706 stmmac_set_ethtool_ops(ndev); 4707 priv->pause = pause; 4708 priv->plat = plat_dat; 4709 priv->ioaddr = res->addr; 4710 priv->dev->base_addr = (unsigned long)res->addr; 4711 4712 priv->dev->irq = res->irq; 4713 priv->wol_irq = res->wol_irq; 4714 priv->lpi_irq = res->lpi_irq; 4715 4716 if (!IS_ERR_OR_NULL(res->mac)) 4717 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4718 4719 dev_set_drvdata(device, priv->dev); 4720 4721 /* Verify driver arguments */ 4722 stmmac_verify_args(); 4723 4724 /* Allocate workqueue */ 4725 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4726 if (!priv->wq) { 4727 dev_err(priv->device, "failed to create workqueue\n"); 4728 return -ENOMEM; 4729 } 4730 4731 INIT_WORK(&priv->service_task, stmmac_service_task); 4732 4733 /* Override with kernel parameters if supplied XXX CRS XXX 4734 * this needs to have multiple instances 4735 */ 4736 if ((phyaddr >= 0) && (phyaddr <= 31)) 4737 priv->plat->phy_addr = phyaddr; 4738 4739 if (priv->plat->stmmac_rst) { 4740 ret = reset_control_assert(priv->plat->stmmac_rst); 4741 reset_control_deassert(priv->plat->stmmac_rst); 4742 /* Some reset controllers have only reset callback instead of 4743 * assert + deassert callbacks pair. 4744 */ 4745 if (ret == -ENOTSUPP) 4746 reset_control_reset(priv->plat->stmmac_rst); 4747 } 4748 4749 /* Init MAC and get the capabilities */ 4750 ret = stmmac_hw_init(priv); 4751 if (ret) 4752 goto error_hw_init; 4753 4754 stmmac_check_ether_addr(priv); 4755 4756 /* Configure real RX and TX queues */ 4757 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4758 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4759 4760 ndev->netdev_ops = &stmmac_netdev_ops; 4761 4762 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4763 NETIF_F_RXCSUM; 4764 4765 ret = stmmac_tc_init(priv, priv); 4766 if (!ret) { 4767 ndev->hw_features |= NETIF_F_HW_TC; 4768 } 4769 4770 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4771 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4772 if (priv->plat->has_gmac4) 4773 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4774 priv->tso = true; 4775 dev_info(priv->device, "TSO feature enabled\n"); 4776 } 4777 4778 if (priv->dma_cap.sphen) { 4779 ndev->hw_features |= NETIF_F_GRO; 4780 priv->sph = true; 4781 dev_info(priv->device, "SPH feature enabled\n"); 4782 } 4783 4784 if (priv->dma_cap.addr64) { 4785 ret = dma_set_mask_and_coherent(device, 4786 DMA_BIT_MASK(priv->dma_cap.addr64)); 4787 if (!ret) { 4788 dev_info(priv->device, "Using %d bits DMA width\n", 4789 priv->dma_cap.addr64); 4790 4791 /* 4792 * If more than 32 bits can be addressed, make sure to 4793 * enable enhanced addressing mode. 4794 */ 4795 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4796 priv->plat->dma_cfg->eame = true; 4797 } else { 4798 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4799 if (ret) { 4800 dev_err(priv->device, "Failed to set DMA Mask\n"); 4801 goto error_hw_init; 4802 } 4803 4804 priv->dma_cap.addr64 = 32; 4805 } 4806 } 4807 4808 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4809 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4810 #ifdef STMMAC_VLAN_TAG_USED 4811 /* Both mac100 and gmac support receive VLAN tag detection */ 4812 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4813 if (priv->dma_cap.vlhash) { 4814 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4815 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4816 } 4817 if (priv->dma_cap.vlins) { 4818 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4819 if (priv->dma_cap.dvlan) 4820 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4821 } 4822 #endif 4823 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4824 4825 /* Initialize RSS */ 4826 rxq = priv->plat->rx_queues_to_use; 4827 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4828 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4829 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4830 4831 if (priv->dma_cap.rssen && priv->plat->rss_en) 4832 ndev->features |= NETIF_F_RXHASH; 4833 4834 /* MTU range: 46 - hw-specific max */ 4835 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4836 if (priv->plat->has_xgmac) 4837 ndev->max_mtu = XGMAC_JUMBO_LEN; 4838 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4839 ndev->max_mtu = JUMBO_LEN; 4840 else 4841 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4842 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4843 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4844 */ 4845 if ((priv->plat->maxmtu < ndev->max_mtu) && 4846 (priv->plat->maxmtu >= ndev->min_mtu)) 4847 ndev->max_mtu = priv->plat->maxmtu; 4848 else if (priv->plat->maxmtu < ndev->min_mtu) 4849 dev_warn(priv->device, 4850 "%s: warning: maxmtu having invalid value (%d)\n", 4851 __func__, priv->plat->maxmtu); 4852 4853 if (flow_ctrl) 4854 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4855 4856 /* Setup channels NAPI */ 4857 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4858 4859 for (queue = 0; queue < maxq; queue++) { 4860 struct stmmac_channel *ch = &priv->channel[queue]; 4861 4862 spin_lock_init(&ch->lock); 4863 ch->priv_data = priv; 4864 ch->index = queue; 4865 4866 if (queue < priv->plat->rx_queues_to_use) { 4867 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4868 NAPI_POLL_WEIGHT); 4869 } 4870 if (queue < priv->plat->tx_queues_to_use) { 4871 netif_tx_napi_add(ndev, &ch->tx_napi, 4872 stmmac_napi_poll_tx, 4873 NAPI_POLL_WEIGHT); 4874 } 4875 } 4876 4877 mutex_init(&priv->lock); 4878 4879 /* If a specific clk_csr value is passed from the platform 4880 * this means that the CSR Clock Range selection cannot be 4881 * changed at run-time and it is fixed. Viceversa the driver'll try to 4882 * set the MDC clock dynamically according to the csr actual 4883 * clock input. 4884 */ 4885 if (priv->plat->clk_csr >= 0) 4886 priv->clk_csr = priv->plat->clk_csr; 4887 else 4888 stmmac_clk_csr_set(priv); 4889 4890 stmmac_check_pcs_mode(priv); 4891 4892 if (priv->hw->pcs != STMMAC_PCS_TBI && 4893 priv->hw->pcs != STMMAC_PCS_RTBI) { 4894 /* MDIO bus Registration */ 4895 ret = stmmac_mdio_register(ndev); 4896 if (ret < 0) { 4897 dev_err(priv->device, 4898 "%s: MDIO bus (id: %d) registration failed", 4899 __func__, priv->plat->bus_id); 4900 goto error_mdio_register; 4901 } 4902 } 4903 4904 ret = stmmac_phy_setup(priv); 4905 if (ret) { 4906 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4907 goto error_phy_setup; 4908 } 4909 4910 ret = register_netdev(ndev); 4911 if (ret) { 4912 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4913 __func__, ret); 4914 goto error_netdev_register; 4915 } 4916 4917 #ifdef CONFIG_DEBUG_FS 4918 stmmac_init_fs(ndev); 4919 #endif 4920 4921 return ret; 4922 4923 error_netdev_register: 4924 phylink_destroy(priv->phylink); 4925 error_phy_setup: 4926 if (priv->hw->pcs != STMMAC_PCS_TBI && 4927 priv->hw->pcs != STMMAC_PCS_RTBI) 4928 stmmac_mdio_unregister(ndev); 4929 error_mdio_register: 4930 for (queue = 0; queue < maxq; queue++) { 4931 struct stmmac_channel *ch = &priv->channel[queue]; 4932 4933 if (queue < priv->plat->rx_queues_to_use) 4934 netif_napi_del(&ch->rx_napi); 4935 if (queue < priv->plat->tx_queues_to_use) 4936 netif_napi_del(&ch->tx_napi); 4937 } 4938 error_hw_init: 4939 destroy_workqueue(priv->wq); 4940 4941 return ret; 4942 } 4943 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4944 4945 /** 4946 * stmmac_dvr_remove 4947 * @dev: device pointer 4948 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4949 * changes the link status, releases the DMA descriptor rings. 4950 */ 4951 int stmmac_dvr_remove(struct device *dev) 4952 { 4953 struct net_device *ndev = dev_get_drvdata(dev); 4954 struct stmmac_priv *priv = netdev_priv(ndev); 4955 4956 netdev_info(priv->dev, "%s: removing driver", __func__); 4957 4958 stmmac_stop_all_dma(priv); 4959 4960 stmmac_mac_set(priv, priv->ioaddr, false); 4961 netif_carrier_off(ndev); 4962 unregister_netdev(ndev); 4963 #ifdef CONFIG_DEBUG_FS 4964 stmmac_exit_fs(ndev); 4965 #endif 4966 phylink_destroy(priv->phylink); 4967 if (priv->plat->stmmac_rst) 4968 reset_control_assert(priv->plat->stmmac_rst); 4969 clk_disable_unprepare(priv->plat->pclk); 4970 clk_disable_unprepare(priv->plat->stmmac_clk); 4971 if (priv->hw->pcs != STMMAC_PCS_TBI && 4972 priv->hw->pcs != STMMAC_PCS_RTBI) 4973 stmmac_mdio_unregister(ndev); 4974 destroy_workqueue(priv->wq); 4975 mutex_destroy(&priv->lock); 4976 4977 return 0; 4978 } 4979 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4980 4981 /** 4982 * stmmac_suspend - suspend callback 4983 * @dev: device pointer 4984 * Description: this is the function to suspend the device and it is called 4985 * by the platform driver to stop the network queue, release the resources, 4986 * program the PMT register (for WoL), clean and release driver resources. 4987 */ 4988 int stmmac_suspend(struct device *dev) 4989 { 4990 struct net_device *ndev = dev_get_drvdata(dev); 4991 struct stmmac_priv *priv = netdev_priv(ndev); 4992 u32 chan; 4993 4994 if (!ndev || !netif_running(ndev)) 4995 return 0; 4996 4997 phylink_mac_change(priv->phylink, false); 4998 4999 mutex_lock(&priv->lock); 5000 5001 netif_device_detach(ndev); 5002 stmmac_stop_all_queues(priv); 5003 5004 stmmac_disable_all_queues(priv); 5005 5006 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5007 del_timer_sync(&priv->tx_queue[chan].txtimer); 5008 5009 /* Stop TX/RX DMA */ 5010 stmmac_stop_all_dma(priv); 5011 5012 /* Enable Power down mode by programming the PMT regs */ 5013 if (device_may_wakeup(priv->device)) { 5014 stmmac_pmt(priv, priv->hw, priv->wolopts); 5015 priv->irq_wake = 1; 5016 } else { 5017 mutex_unlock(&priv->lock); 5018 rtnl_lock(); 5019 phylink_stop(priv->phylink); 5020 rtnl_unlock(); 5021 mutex_lock(&priv->lock); 5022 5023 stmmac_mac_set(priv, priv->ioaddr, false); 5024 pinctrl_pm_select_sleep_state(priv->device); 5025 /* Disable clock in case of PWM is off */ 5026 if (priv->plat->clk_ptp_ref) 5027 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5028 clk_disable_unprepare(priv->plat->pclk); 5029 clk_disable_unprepare(priv->plat->stmmac_clk); 5030 } 5031 mutex_unlock(&priv->lock); 5032 5033 priv->speed = SPEED_UNKNOWN; 5034 return 0; 5035 } 5036 EXPORT_SYMBOL_GPL(stmmac_suspend); 5037 5038 /** 5039 * stmmac_reset_queues_param - reset queue parameters 5040 * @dev: device pointer 5041 */ 5042 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5043 { 5044 u32 rx_cnt = priv->plat->rx_queues_to_use; 5045 u32 tx_cnt = priv->plat->tx_queues_to_use; 5046 u32 queue; 5047 5048 for (queue = 0; queue < rx_cnt; queue++) { 5049 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5050 5051 rx_q->cur_rx = 0; 5052 rx_q->dirty_rx = 0; 5053 } 5054 5055 for (queue = 0; queue < tx_cnt; queue++) { 5056 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5057 5058 tx_q->cur_tx = 0; 5059 tx_q->dirty_tx = 0; 5060 tx_q->mss = 0; 5061 } 5062 } 5063 5064 /** 5065 * stmmac_resume - resume callback 5066 * @dev: device pointer 5067 * Description: when resume this function is invoked to setup the DMA and CORE 5068 * in a usable state. 5069 */ 5070 int stmmac_resume(struct device *dev) 5071 { 5072 struct net_device *ndev = dev_get_drvdata(dev); 5073 struct stmmac_priv *priv = netdev_priv(ndev); 5074 5075 if (!netif_running(ndev)) 5076 return 0; 5077 5078 /* Power Down bit, into the PM register, is cleared 5079 * automatically as soon as a magic packet or a Wake-up frame 5080 * is received. Anyway, it's better to manually clear 5081 * this bit because it can generate problems while resuming 5082 * from another devices (e.g. serial console). 5083 */ 5084 if (device_may_wakeup(priv->device)) { 5085 mutex_lock(&priv->lock); 5086 stmmac_pmt(priv, priv->hw, 0); 5087 mutex_unlock(&priv->lock); 5088 priv->irq_wake = 0; 5089 } else { 5090 pinctrl_pm_select_default_state(priv->device); 5091 /* enable the clk previously disabled */ 5092 clk_prepare_enable(priv->plat->stmmac_clk); 5093 clk_prepare_enable(priv->plat->pclk); 5094 if (priv->plat->clk_ptp_ref) 5095 clk_prepare_enable(priv->plat->clk_ptp_ref); 5096 /* reset the phy so that it's ready */ 5097 if (priv->mii) 5098 stmmac_mdio_reset(priv->mii); 5099 } 5100 5101 netif_device_attach(ndev); 5102 5103 mutex_lock(&priv->lock); 5104 5105 stmmac_reset_queues_param(priv); 5106 5107 stmmac_clear_descriptors(priv); 5108 5109 stmmac_hw_setup(ndev, false); 5110 stmmac_init_coalesce(priv); 5111 stmmac_set_rx_mode(ndev); 5112 5113 stmmac_enable_all_queues(priv); 5114 5115 stmmac_start_all_queues(priv); 5116 5117 mutex_unlock(&priv->lock); 5118 5119 if (!device_may_wakeup(priv->device)) { 5120 rtnl_lock(); 5121 phylink_start(priv->phylink); 5122 rtnl_unlock(); 5123 } 5124 5125 phylink_mac_change(priv->phylink, true); 5126 5127 return 0; 5128 } 5129 EXPORT_SYMBOL_GPL(stmmac_resume); 5130 5131 #ifndef MODULE 5132 static int __init stmmac_cmdline_opt(char *str) 5133 { 5134 char *opt; 5135 5136 if (!str || !*str) 5137 return -EINVAL; 5138 while ((opt = strsep(&str, ",")) != NULL) { 5139 if (!strncmp(opt, "debug:", 6)) { 5140 if (kstrtoint(opt + 6, 0, &debug)) 5141 goto err; 5142 } else if (!strncmp(opt, "phyaddr:", 8)) { 5143 if (kstrtoint(opt + 8, 0, &phyaddr)) 5144 goto err; 5145 } else if (!strncmp(opt, "buf_sz:", 7)) { 5146 if (kstrtoint(opt + 7, 0, &buf_sz)) 5147 goto err; 5148 } else if (!strncmp(opt, "tc:", 3)) { 5149 if (kstrtoint(opt + 3, 0, &tc)) 5150 goto err; 5151 } else if (!strncmp(opt, "watchdog:", 9)) { 5152 if (kstrtoint(opt + 9, 0, &watchdog)) 5153 goto err; 5154 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5155 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5156 goto err; 5157 } else if (!strncmp(opt, "pause:", 6)) { 5158 if (kstrtoint(opt + 6, 0, &pause)) 5159 goto err; 5160 } else if (!strncmp(opt, "eee_timer:", 10)) { 5161 if (kstrtoint(opt + 10, 0, &eee_timer)) 5162 goto err; 5163 } else if (!strncmp(opt, "chain_mode:", 11)) { 5164 if (kstrtoint(opt + 11, 0, &chain_mode)) 5165 goto err; 5166 } 5167 } 5168 return 0; 5169 5170 err: 5171 pr_err("%s: ERROR broken module parameter conversion", __func__); 5172 return -EINVAL; 5173 } 5174 5175 __setup("stmmaceth=", stmmac_cmdline_opt); 5176 #endif /* MODULE */ 5177 5178 static int __init stmmac_init(void) 5179 { 5180 #ifdef CONFIG_DEBUG_FS 5181 /* Create debugfs main directory if it doesn't exist yet */ 5182 if (!stmmac_fs_dir) 5183 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5184 register_netdevice_notifier(&stmmac_notifier); 5185 #endif 5186 5187 return 0; 5188 } 5189 5190 static void __exit stmmac_exit(void) 5191 { 5192 #ifdef CONFIG_DEBUG_FS 5193 unregister_netdevice_notifier(&stmmac_notifier); 5194 debugfs_remove_recursive(stmmac_fs_dir); 5195 #endif 5196 } 5197 5198 module_init(stmmac_init) 5199 module_exit(stmmac_exit) 5200 5201 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5202 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5203 MODULE_LICENSE("GPL"); 5204