1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLOCKGATING); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (priv->hw->xpcs) 941 return &priv->hw->xpcs->pcs; 942 943 if (priv->hw->lynx_pcs) 944 return priv->hw->lynx_pcs; 945 946 return NULL; 947 } 948 949 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 950 const struct phylink_link_state *state) 951 { 952 /* Nothing to do, xpcs_config() handles everything */ 953 } 954 955 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 956 { 957 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 958 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 959 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 960 bool *hs_enable = &fpe_cfg->hs_enable; 961 962 if (is_up && *hs_enable) { 963 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 964 } else { 965 *lo_state = FPE_STATE_OFF; 966 *lp_state = FPE_STATE_OFF; 967 } 968 } 969 970 static void stmmac_mac_link_down(struct phylink_config *config, 971 unsigned int mode, phy_interface_t interface) 972 { 973 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 974 975 stmmac_mac_set(priv, priv->ioaddr, false); 976 priv->eee_active = false; 977 priv->tx_lpi_enabled = false; 978 priv->eee_enabled = stmmac_eee_init(priv); 979 stmmac_set_eee_pls(priv, priv->hw, false); 980 981 if (priv->dma_cap.fpesel) 982 stmmac_fpe_link_state_handle(priv, false); 983 } 984 985 static void stmmac_mac_link_up(struct phylink_config *config, 986 struct phy_device *phy, 987 unsigned int mode, phy_interface_t interface, 988 int speed, int duplex, 989 bool tx_pause, bool rx_pause) 990 { 991 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 992 u32 old_ctrl, ctrl; 993 994 if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 995 priv->plat->serdes_powerup) 996 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 997 998 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 999 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 1000 1001 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1002 switch (speed) { 1003 case SPEED_10000: 1004 ctrl |= priv->hw->link.xgmii.speed10000; 1005 break; 1006 case SPEED_5000: 1007 ctrl |= priv->hw->link.xgmii.speed5000; 1008 break; 1009 case SPEED_2500: 1010 ctrl |= priv->hw->link.xgmii.speed2500; 1011 break; 1012 default: 1013 return; 1014 } 1015 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1016 switch (speed) { 1017 case SPEED_100000: 1018 ctrl |= priv->hw->link.xlgmii.speed100000; 1019 break; 1020 case SPEED_50000: 1021 ctrl |= priv->hw->link.xlgmii.speed50000; 1022 break; 1023 case SPEED_40000: 1024 ctrl |= priv->hw->link.xlgmii.speed40000; 1025 break; 1026 case SPEED_25000: 1027 ctrl |= priv->hw->link.xlgmii.speed25000; 1028 break; 1029 case SPEED_10000: 1030 ctrl |= priv->hw->link.xgmii.speed10000; 1031 break; 1032 case SPEED_2500: 1033 ctrl |= priv->hw->link.speed2500; 1034 break; 1035 case SPEED_1000: 1036 ctrl |= priv->hw->link.speed1000; 1037 break; 1038 default: 1039 return; 1040 } 1041 } else { 1042 switch (speed) { 1043 case SPEED_2500: 1044 ctrl |= priv->hw->link.speed2500; 1045 break; 1046 case SPEED_1000: 1047 ctrl |= priv->hw->link.speed1000; 1048 break; 1049 case SPEED_100: 1050 ctrl |= priv->hw->link.speed100; 1051 break; 1052 case SPEED_10: 1053 ctrl |= priv->hw->link.speed10; 1054 break; 1055 default: 1056 return; 1057 } 1058 } 1059 1060 priv->speed = speed; 1061 1062 if (priv->plat->fix_mac_speed) 1063 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1064 1065 if (!duplex) 1066 ctrl &= ~priv->hw->link.duplex; 1067 else 1068 ctrl |= priv->hw->link.duplex; 1069 1070 /* Flow Control operation */ 1071 if (rx_pause && tx_pause) 1072 priv->flow_ctrl = FLOW_AUTO; 1073 else if (rx_pause && !tx_pause) 1074 priv->flow_ctrl = FLOW_RX; 1075 else if (!rx_pause && tx_pause) 1076 priv->flow_ctrl = FLOW_TX; 1077 else 1078 priv->flow_ctrl = FLOW_OFF; 1079 1080 stmmac_mac_flow_ctrl(priv, duplex); 1081 1082 if (ctrl != old_ctrl) 1083 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1084 1085 stmmac_mac_set(priv, priv->ioaddr, true); 1086 if (phy && priv->dma_cap.eee) { 1087 priv->eee_active = 1088 phy_init_eee(phy, !(priv->plat->flags & 1089 STMMAC_FLAG_RX_CLK_RUNS_IN_LPI)) >= 0; 1090 priv->eee_enabled = stmmac_eee_init(priv); 1091 priv->tx_lpi_enabled = priv->eee_enabled; 1092 stmmac_set_eee_pls(priv, priv->hw, true); 1093 } 1094 1095 if (priv->dma_cap.fpesel) 1096 stmmac_fpe_link_state_handle(priv, true); 1097 } 1098 1099 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1100 .mac_select_pcs = stmmac_mac_select_pcs, 1101 .mac_config = stmmac_mac_config, 1102 .mac_link_down = stmmac_mac_link_down, 1103 .mac_link_up = stmmac_mac_link_up, 1104 }; 1105 1106 /** 1107 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1108 * @priv: driver private structure 1109 * Description: this is to verify if the HW supports the PCS. 1110 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1111 * configured for the TBI, RTBI, or SGMII PHY interface. 1112 */ 1113 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1114 { 1115 int interface = priv->plat->interface; 1116 1117 if (priv->dma_cap.pcs) { 1118 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1119 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1120 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1121 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1122 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1123 priv->hw->pcs = STMMAC_PCS_RGMII; 1124 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1125 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1126 priv->hw->pcs = STMMAC_PCS_SGMII; 1127 } 1128 } 1129 } 1130 1131 /** 1132 * stmmac_init_phy - PHY initialization 1133 * @dev: net device structure 1134 * Description: it initializes the driver's PHY state, and attaches the PHY 1135 * to the mac driver. 1136 * Return value: 1137 * 0 on success 1138 */ 1139 static int stmmac_init_phy(struct net_device *dev) 1140 { 1141 struct stmmac_priv *priv = netdev_priv(dev); 1142 struct fwnode_handle *phy_fwnode; 1143 struct fwnode_handle *fwnode; 1144 int ret; 1145 1146 if (!phylink_expects_phy(priv->phylink)) 1147 return 0; 1148 1149 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1150 if (!fwnode) 1151 fwnode = dev_fwnode(priv->device); 1152 1153 if (fwnode) 1154 phy_fwnode = fwnode_get_phy_node(fwnode); 1155 else 1156 phy_fwnode = NULL; 1157 1158 /* Some DT bindings do not set-up the PHY handle. Let's try to 1159 * manually parse it 1160 */ 1161 if (!phy_fwnode || IS_ERR(phy_fwnode)) { 1162 int addr = priv->plat->phy_addr; 1163 struct phy_device *phydev; 1164 1165 if (addr < 0) { 1166 netdev_err(priv->dev, "no phy found\n"); 1167 return -ENODEV; 1168 } 1169 1170 phydev = mdiobus_get_phy(priv->mii, addr); 1171 if (!phydev) { 1172 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1173 return -ENODEV; 1174 } 1175 1176 ret = phylink_connect_phy(priv->phylink, phydev); 1177 } else { 1178 fwnode_handle_put(phy_fwnode); 1179 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1180 } 1181 1182 if (!priv->plat->pmt) { 1183 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1184 1185 phylink_ethtool_get_wol(priv->phylink, &wol); 1186 device_set_wakeup_capable(priv->device, !!wol.supported); 1187 device_set_wakeup_enable(priv->device, !!wol.wolopts); 1188 } 1189 1190 return ret; 1191 } 1192 1193 static int stmmac_phy_setup(struct stmmac_priv *priv) 1194 { 1195 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1196 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1197 int max_speed = priv->plat->max_speed; 1198 int mode = priv->plat->phy_interface; 1199 struct phylink *phylink; 1200 1201 priv->phylink_config.dev = &priv->dev->dev; 1202 priv->phylink_config.type = PHYLINK_NETDEV; 1203 if (priv->plat->mdio_bus_data) 1204 priv->phylink_config.ovr_an_inband = 1205 mdio_bus_data->xpcs_an_inband; 1206 1207 if (!fwnode) 1208 fwnode = dev_fwnode(priv->device); 1209 1210 /* Set the platform/firmware specified interface mode */ 1211 __set_bit(mode, priv->phylink_config.supported_interfaces); 1212 1213 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1214 if (priv->hw->xpcs) 1215 xpcs_get_interfaces(priv->hw->xpcs, 1216 priv->phylink_config.supported_interfaces); 1217 1218 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1219 MAC_10 | MAC_100; 1220 1221 if (!max_speed || max_speed >= 1000) 1222 priv->phylink_config.mac_capabilities |= MAC_1000; 1223 1224 if (priv->plat->has_gmac4) { 1225 if (!max_speed || max_speed >= 2500) 1226 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1227 } else if (priv->plat->has_xgmac) { 1228 if (!max_speed || max_speed >= 2500) 1229 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1230 if (!max_speed || max_speed >= 5000) 1231 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1232 if (!max_speed || max_speed >= 10000) 1233 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1234 if (!max_speed || max_speed >= 25000) 1235 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1236 if (!max_speed || max_speed >= 40000) 1237 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1238 if (!max_speed || max_speed >= 50000) 1239 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1240 if (!max_speed || max_speed >= 100000) 1241 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1242 } 1243 1244 /* Half-Duplex can only work with single queue */ 1245 if (priv->plat->tx_queues_to_use > 1) 1246 priv->phylink_config.mac_capabilities &= 1247 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1248 priv->phylink_config.mac_managed_pm = true; 1249 1250 phylink = phylink_create(&priv->phylink_config, fwnode, 1251 mode, &stmmac_phylink_mac_ops); 1252 if (IS_ERR(phylink)) 1253 return PTR_ERR(phylink); 1254 1255 priv->phylink = phylink; 1256 return 0; 1257 } 1258 1259 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1260 struct stmmac_dma_conf *dma_conf) 1261 { 1262 u32 rx_cnt = priv->plat->rx_queues_to_use; 1263 unsigned int desc_size; 1264 void *head_rx; 1265 u32 queue; 1266 1267 /* Display RX rings */ 1268 for (queue = 0; queue < rx_cnt; queue++) { 1269 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1270 1271 pr_info("\tRX Queue %u rings\n", queue); 1272 1273 if (priv->extend_desc) { 1274 head_rx = (void *)rx_q->dma_erx; 1275 desc_size = sizeof(struct dma_extended_desc); 1276 } else { 1277 head_rx = (void *)rx_q->dma_rx; 1278 desc_size = sizeof(struct dma_desc); 1279 } 1280 1281 /* Display RX ring */ 1282 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1283 rx_q->dma_rx_phy, desc_size); 1284 } 1285 } 1286 1287 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1288 struct stmmac_dma_conf *dma_conf) 1289 { 1290 u32 tx_cnt = priv->plat->tx_queues_to_use; 1291 unsigned int desc_size; 1292 void *head_tx; 1293 u32 queue; 1294 1295 /* Display TX rings */ 1296 for (queue = 0; queue < tx_cnt; queue++) { 1297 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1298 1299 pr_info("\tTX Queue %d rings\n", queue); 1300 1301 if (priv->extend_desc) { 1302 head_tx = (void *)tx_q->dma_etx; 1303 desc_size = sizeof(struct dma_extended_desc); 1304 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1305 head_tx = (void *)tx_q->dma_entx; 1306 desc_size = sizeof(struct dma_edesc); 1307 } else { 1308 head_tx = (void *)tx_q->dma_tx; 1309 desc_size = sizeof(struct dma_desc); 1310 } 1311 1312 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1313 tx_q->dma_tx_phy, desc_size); 1314 } 1315 } 1316 1317 static void stmmac_display_rings(struct stmmac_priv *priv, 1318 struct stmmac_dma_conf *dma_conf) 1319 { 1320 /* Display RX ring */ 1321 stmmac_display_rx_rings(priv, dma_conf); 1322 1323 /* Display TX ring */ 1324 stmmac_display_tx_rings(priv, dma_conf); 1325 } 1326 1327 static int stmmac_set_bfsize(int mtu, int bufsize) 1328 { 1329 int ret = bufsize; 1330 1331 if (mtu >= BUF_SIZE_8KiB) 1332 ret = BUF_SIZE_16KiB; 1333 else if (mtu >= BUF_SIZE_4KiB) 1334 ret = BUF_SIZE_8KiB; 1335 else if (mtu >= BUF_SIZE_2KiB) 1336 ret = BUF_SIZE_4KiB; 1337 else if (mtu > DEFAULT_BUFSIZE) 1338 ret = BUF_SIZE_2KiB; 1339 else 1340 ret = DEFAULT_BUFSIZE; 1341 1342 return ret; 1343 } 1344 1345 /** 1346 * stmmac_clear_rx_descriptors - clear RX descriptors 1347 * @priv: driver private structure 1348 * @dma_conf: structure to take the dma data 1349 * @queue: RX queue index 1350 * Description: this function is called to clear the RX descriptors 1351 * in case of both basic and extended descriptors are used. 1352 */ 1353 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1354 struct stmmac_dma_conf *dma_conf, 1355 u32 queue) 1356 { 1357 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1358 int i; 1359 1360 /* Clear the RX descriptors */ 1361 for (i = 0; i < dma_conf->dma_rx_size; i++) 1362 if (priv->extend_desc) 1363 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1364 priv->use_riwt, priv->mode, 1365 (i == dma_conf->dma_rx_size - 1), 1366 dma_conf->dma_buf_sz); 1367 else 1368 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1369 priv->use_riwt, priv->mode, 1370 (i == dma_conf->dma_rx_size - 1), 1371 dma_conf->dma_buf_sz); 1372 } 1373 1374 /** 1375 * stmmac_clear_tx_descriptors - clear tx descriptors 1376 * @priv: driver private structure 1377 * @dma_conf: structure to take the dma data 1378 * @queue: TX queue index. 1379 * Description: this function is called to clear the TX descriptors 1380 * in case of both basic and extended descriptors are used. 1381 */ 1382 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1383 struct stmmac_dma_conf *dma_conf, 1384 u32 queue) 1385 { 1386 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1387 int i; 1388 1389 /* Clear the TX descriptors */ 1390 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1391 int last = (i == (dma_conf->dma_tx_size - 1)); 1392 struct dma_desc *p; 1393 1394 if (priv->extend_desc) 1395 p = &tx_q->dma_etx[i].basic; 1396 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1397 p = &tx_q->dma_entx[i].basic; 1398 else 1399 p = &tx_q->dma_tx[i]; 1400 1401 stmmac_init_tx_desc(priv, p, priv->mode, last); 1402 } 1403 } 1404 1405 /** 1406 * stmmac_clear_descriptors - clear descriptors 1407 * @priv: driver private structure 1408 * @dma_conf: structure to take the dma data 1409 * Description: this function is called to clear the TX and RX descriptors 1410 * in case of both basic and extended descriptors are used. 1411 */ 1412 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1413 struct stmmac_dma_conf *dma_conf) 1414 { 1415 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1416 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1417 u32 queue; 1418 1419 /* Clear the RX descriptors */ 1420 for (queue = 0; queue < rx_queue_cnt; queue++) 1421 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1422 1423 /* Clear the TX descriptors */ 1424 for (queue = 0; queue < tx_queue_cnt; queue++) 1425 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1426 } 1427 1428 /** 1429 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1430 * @priv: driver private structure 1431 * @dma_conf: structure to take the dma data 1432 * @p: descriptor pointer 1433 * @i: descriptor index 1434 * @flags: gfp flag 1435 * @queue: RX queue index 1436 * Description: this function is called to allocate a receive buffer, perform 1437 * the DMA mapping and init the descriptor. 1438 */ 1439 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1440 struct stmmac_dma_conf *dma_conf, 1441 struct dma_desc *p, 1442 int i, gfp_t flags, u32 queue) 1443 { 1444 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1445 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1446 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1447 1448 if (priv->dma_cap.host_dma_width <= 32) 1449 gfp |= GFP_DMA32; 1450 1451 if (!buf->page) { 1452 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1453 if (!buf->page) 1454 return -ENOMEM; 1455 buf->page_offset = stmmac_rx_offset(priv); 1456 } 1457 1458 if (priv->sph && !buf->sec_page) { 1459 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1460 if (!buf->sec_page) 1461 return -ENOMEM; 1462 1463 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1464 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1465 } else { 1466 buf->sec_page = NULL; 1467 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1468 } 1469 1470 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1471 1472 stmmac_set_desc_addr(priv, p, buf->addr); 1473 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1474 stmmac_init_desc3(priv, p); 1475 1476 return 0; 1477 } 1478 1479 /** 1480 * stmmac_free_rx_buffer - free RX dma buffers 1481 * @priv: private structure 1482 * @rx_q: RX queue 1483 * @i: buffer index. 1484 */ 1485 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1486 struct stmmac_rx_queue *rx_q, 1487 int i) 1488 { 1489 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1490 1491 if (buf->page) 1492 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1493 buf->page = NULL; 1494 1495 if (buf->sec_page) 1496 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1497 buf->sec_page = NULL; 1498 } 1499 1500 /** 1501 * stmmac_free_tx_buffer - free RX dma buffers 1502 * @priv: private structure 1503 * @dma_conf: structure to take the dma data 1504 * @queue: RX queue index 1505 * @i: buffer index. 1506 */ 1507 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1508 struct stmmac_dma_conf *dma_conf, 1509 u32 queue, int i) 1510 { 1511 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1512 1513 if (tx_q->tx_skbuff_dma[i].buf && 1514 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1515 if (tx_q->tx_skbuff_dma[i].map_as_page) 1516 dma_unmap_page(priv->device, 1517 tx_q->tx_skbuff_dma[i].buf, 1518 tx_q->tx_skbuff_dma[i].len, 1519 DMA_TO_DEVICE); 1520 else 1521 dma_unmap_single(priv->device, 1522 tx_q->tx_skbuff_dma[i].buf, 1523 tx_q->tx_skbuff_dma[i].len, 1524 DMA_TO_DEVICE); 1525 } 1526 1527 if (tx_q->xdpf[i] && 1528 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1529 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1530 xdp_return_frame(tx_q->xdpf[i]); 1531 tx_q->xdpf[i] = NULL; 1532 } 1533 1534 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1535 tx_q->xsk_frames_done++; 1536 1537 if (tx_q->tx_skbuff[i] && 1538 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1539 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1540 tx_q->tx_skbuff[i] = NULL; 1541 } 1542 1543 tx_q->tx_skbuff_dma[i].buf = 0; 1544 tx_q->tx_skbuff_dma[i].map_as_page = false; 1545 } 1546 1547 /** 1548 * dma_free_rx_skbufs - free RX dma buffers 1549 * @priv: private structure 1550 * @dma_conf: structure to take the dma data 1551 * @queue: RX queue index 1552 */ 1553 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1554 struct stmmac_dma_conf *dma_conf, 1555 u32 queue) 1556 { 1557 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1558 int i; 1559 1560 for (i = 0; i < dma_conf->dma_rx_size; i++) 1561 stmmac_free_rx_buffer(priv, rx_q, i); 1562 } 1563 1564 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1565 struct stmmac_dma_conf *dma_conf, 1566 u32 queue, gfp_t flags) 1567 { 1568 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1569 int i; 1570 1571 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1572 struct dma_desc *p; 1573 int ret; 1574 1575 if (priv->extend_desc) 1576 p = &((rx_q->dma_erx + i)->basic); 1577 else 1578 p = rx_q->dma_rx + i; 1579 1580 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1581 queue); 1582 if (ret) 1583 return ret; 1584 1585 rx_q->buf_alloc_num++; 1586 } 1587 1588 return 0; 1589 } 1590 1591 /** 1592 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1593 * @priv: private structure 1594 * @dma_conf: structure to take the dma data 1595 * @queue: RX queue index 1596 */ 1597 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1598 struct stmmac_dma_conf *dma_conf, 1599 u32 queue) 1600 { 1601 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1602 int i; 1603 1604 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1605 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1606 1607 if (!buf->xdp) 1608 continue; 1609 1610 xsk_buff_free(buf->xdp); 1611 buf->xdp = NULL; 1612 } 1613 } 1614 1615 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1616 struct stmmac_dma_conf *dma_conf, 1617 u32 queue) 1618 { 1619 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1620 int i; 1621 1622 /* struct stmmac_xdp_buff is using cb field (maximum size of 24 bytes) 1623 * in struct xdp_buff_xsk to stash driver specific information. Thus, 1624 * use this macro to make sure no size violations. 1625 */ 1626 XSK_CHECK_PRIV_TYPE(struct stmmac_xdp_buff); 1627 1628 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1629 struct stmmac_rx_buffer *buf; 1630 dma_addr_t dma_addr; 1631 struct dma_desc *p; 1632 1633 if (priv->extend_desc) 1634 p = (struct dma_desc *)(rx_q->dma_erx + i); 1635 else 1636 p = rx_q->dma_rx + i; 1637 1638 buf = &rx_q->buf_pool[i]; 1639 1640 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1641 if (!buf->xdp) 1642 return -ENOMEM; 1643 1644 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1645 stmmac_set_desc_addr(priv, p, dma_addr); 1646 rx_q->buf_alloc_num++; 1647 } 1648 1649 return 0; 1650 } 1651 1652 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1653 { 1654 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1655 return NULL; 1656 1657 return xsk_get_pool_from_qid(priv->dev, queue); 1658 } 1659 1660 /** 1661 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1662 * @priv: driver private structure 1663 * @dma_conf: structure to take the dma data 1664 * @queue: RX queue index 1665 * @flags: gfp flag. 1666 * Description: this function initializes the DMA RX descriptors 1667 * and allocates the socket buffers. It supports the chained and ring 1668 * modes. 1669 */ 1670 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1671 struct stmmac_dma_conf *dma_conf, 1672 u32 queue, gfp_t flags) 1673 { 1674 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1675 int ret; 1676 1677 netif_dbg(priv, probe, priv->dev, 1678 "(%s) dma_rx_phy=0x%08x\n", __func__, 1679 (u32)rx_q->dma_rx_phy); 1680 1681 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1682 1683 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1684 1685 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1686 1687 if (rx_q->xsk_pool) { 1688 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1689 MEM_TYPE_XSK_BUFF_POOL, 1690 NULL)); 1691 netdev_info(priv->dev, 1692 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1693 rx_q->queue_index); 1694 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1695 } else { 1696 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1697 MEM_TYPE_PAGE_POOL, 1698 rx_q->page_pool)); 1699 netdev_info(priv->dev, 1700 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1701 rx_q->queue_index); 1702 } 1703 1704 if (rx_q->xsk_pool) { 1705 /* RX XDP ZC buffer pool may not be populated, e.g. 1706 * xdpsock TX-only. 1707 */ 1708 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1709 } else { 1710 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1711 if (ret < 0) 1712 return -ENOMEM; 1713 } 1714 1715 /* Setup the chained descriptor addresses */ 1716 if (priv->mode == STMMAC_CHAIN_MODE) { 1717 if (priv->extend_desc) 1718 stmmac_mode_init(priv, rx_q->dma_erx, 1719 rx_q->dma_rx_phy, 1720 dma_conf->dma_rx_size, 1); 1721 else 1722 stmmac_mode_init(priv, rx_q->dma_rx, 1723 rx_q->dma_rx_phy, 1724 dma_conf->dma_rx_size, 0); 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int init_dma_rx_desc_rings(struct net_device *dev, 1731 struct stmmac_dma_conf *dma_conf, 1732 gfp_t flags) 1733 { 1734 struct stmmac_priv *priv = netdev_priv(dev); 1735 u32 rx_count = priv->plat->rx_queues_to_use; 1736 int queue; 1737 int ret; 1738 1739 /* RX INITIALIZATION */ 1740 netif_dbg(priv, probe, priv->dev, 1741 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1742 1743 for (queue = 0; queue < rx_count; queue++) { 1744 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1745 if (ret) 1746 goto err_init_rx_buffers; 1747 } 1748 1749 return 0; 1750 1751 err_init_rx_buffers: 1752 while (queue >= 0) { 1753 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1754 1755 if (rx_q->xsk_pool) 1756 dma_free_rx_xskbufs(priv, dma_conf, queue); 1757 else 1758 dma_free_rx_skbufs(priv, dma_conf, queue); 1759 1760 rx_q->buf_alloc_num = 0; 1761 rx_q->xsk_pool = NULL; 1762 1763 queue--; 1764 } 1765 1766 return ret; 1767 } 1768 1769 /** 1770 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1771 * @priv: driver private structure 1772 * @dma_conf: structure to take the dma data 1773 * @queue: TX queue index 1774 * Description: this function initializes the DMA TX descriptors 1775 * and allocates the socket buffers. It supports the chained and ring 1776 * modes. 1777 */ 1778 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1779 struct stmmac_dma_conf *dma_conf, 1780 u32 queue) 1781 { 1782 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1783 int i; 1784 1785 netif_dbg(priv, probe, priv->dev, 1786 "(%s) dma_tx_phy=0x%08x\n", __func__, 1787 (u32)tx_q->dma_tx_phy); 1788 1789 /* Setup the chained descriptor addresses */ 1790 if (priv->mode == STMMAC_CHAIN_MODE) { 1791 if (priv->extend_desc) 1792 stmmac_mode_init(priv, tx_q->dma_etx, 1793 tx_q->dma_tx_phy, 1794 dma_conf->dma_tx_size, 1); 1795 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1796 stmmac_mode_init(priv, tx_q->dma_tx, 1797 tx_q->dma_tx_phy, 1798 dma_conf->dma_tx_size, 0); 1799 } 1800 1801 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1802 1803 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1804 struct dma_desc *p; 1805 1806 if (priv->extend_desc) 1807 p = &((tx_q->dma_etx + i)->basic); 1808 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1809 p = &((tx_q->dma_entx + i)->basic); 1810 else 1811 p = tx_q->dma_tx + i; 1812 1813 stmmac_clear_desc(priv, p); 1814 1815 tx_q->tx_skbuff_dma[i].buf = 0; 1816 tx_q->tx_skbuff_dma[i].map_as_page = false; 1817 tx_q->tx_skbuff_dma[i].len = 0; 1818 tx_q->tx_skbuff_dma[i].last_segment = false; 1819 tx_q->tx_skbuff[i] = NULL; 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int init_dma_tx_desc_rings(struct net_device *dev, 1826 struct stmmac_dma_conf *dma_conf) 1827 { 1828 struct stmmac_priv *priv = netdev_priv(dev); 1829 u32 tx_queue_cnt; 1830 u32 queue; 1831 1832 tx_queue_cnt = priv->plat->tx_queues_to_use; 1833 1834 for (queue = 0; queue < tx_queue_cnt; queue++) 1835 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1836 1837 return 0; 1838 } 1839 1840 /** 1841 * init_dma_desc_rings - init the RX/TX descriptor rings 1842 * @dev: net device structure 1843 * @dma_conf: structure to take the dma data 1844 * @flags: gfp flag. 1845 * Description: this function initializes the DMA RX/TX descriptors 1846 * and allocates the socket buffers. It supports the chained and ring 1847 * modes. 1848 */ 1849 static int init_dma_desc_rings(struct net_device *dev, 1850 struct stmmac_dma_conf *dma_conf, 1851 gfp_t flags) 1852 { 1853 struct stmmac_priv *priv = netdev_priv(dev); 1854 int ret; 1855 1856 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1857 if (ret) 1858 return ret; 1859 1860 ret = init_dma_tx_desc_rings(dev, dma_conf); 1861 1862 stmmac_clear_descriptors(priv, dma_conf); 1863 1864 if (netif_msg_hw(priv)) 1865 stmmac_display_rings(priv, dma_conf); 1866 1867 return ret; 1868 } 1869 1870 /** 1871 * dma_free_tx_skbufs - free TX dma buffers 1872 * @priv: private structure 1873 * @dma_conf: structure to take the dma data 1874 * @queue: TX queue index 1875 */ 1876 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1877 struct stmmac_dma_conf *dma_conf, 1878 u32 queue) 1879 { 1880 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1881 int i; 1882 1883 tx_q->xsk_frames_done = 0; 1884 1885 for (i = 0; i < dma_conf->dma_tx_size; i++) 1886 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1887 1888 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1889 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1890 tx_q->xsk_frames_done = 0; 1891 tx_q->xsk_pool = NULL; 1892 } 1893 } 1894 1895 /** 1896 * stmmac_free_tx_skbufs - free TX skb buffers 1897 * @priv: private structure 1898 */ 1899 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1900 { 1901 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1902 u32 queue; 1903 1904 for (queue = 0; queue < tx_queue_cnt; queue++) 1905 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1906 } 1907 1908 /** 1909 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1910 * @priv: private structure 1911 * @dma_conf: structure to take the dma data 1912 * @queue: RX queue index 1913 */ 1914 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1915 struct stmmac_dma_conf *dma_conf, 1916 u32 queue) 1917 { 1918 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1919 1920 /* Release the DMA RX socket buffers */ 1921 if (rx_q->xsk_pool) 1922 dma_free_rx_xskbufs(priv, dma_conf, queue); 1923 else 1924 dma_free_rx_skbufs(priv, dma_conf, queue); 1925 1926 rx_q->buf_alloc_num = 0; 1927 rx_q->xsk_pool = NULL; 1928 1929 /* Free DMA regions of consistent memory previously allocated */ 1930 if (!priv->extend_desc) 1931 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1932 sizeof(struct dma_desc), 1933 rx_q->dma_rx, rx_q->dma_rx_phy); 1934 else 1935 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1936 sizeof(struct dma_extended_desc), 1937 rx_q->dma_erx, rx_q->dma_rx_phy); 1938 1939 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1940 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1941 1942 kfree(rx_q->buf_pool); 1943 if (rx_q->page_pool) 1944 page_pool_destroy(rx_q->page_pool); 1945 } 1946 1947 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1948 struct stmmac_dma_conf *dma_conf) 1949 { 1950 u32 rx_count = priv->plat->rx_queues_to_use; 1951 u32 queue; 1952 1953 /* Free RX queue resources */ 1954 for (queue = 0; queue < rx_count; queue++) 1955 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1956 } 1957 1958 /** 1959 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1960 * @priv: private structure 1961 * @dma_conf: structure to take the dma data 1962 * @queue: TX queue index 1963 */ 1964 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1965 struct stmmac_dma_conf *dma_conf, 1966 u32 queue) 1967 { 1968 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1969 size_t size; 1970 void *addr; 1971 1972 /* Release the DMA TX socket buffers */ 1973 dma_free_tx_skbufs(priv, dma_conf, queue); 1974 1975 if (priv->extend_desc) { 1976 size = sizeof(struct dma_extended_desc); 1977 addr = tx_q->dma_etx; 1978 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1979 size = sizeof(struct dma_edesc); 1980 addr = tx_q->dma_entx; 1981 } else { 1982 size = sizeof(struct dma_desc); 1983 addr = tx_q->dma_tx; 1984 } 1985 1986 size *= dma_conf->dma_tx_size; 1987 1988 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1989 1990 kfree(tx_q->tx_skbuff_dma); 1991 kfree(tx_q->tx_skbuff); 1992 } 1993 1994 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1995 struct stmmac_dma_conf *dma_conf) 1996 { 1997 u32 tx_count = priv->plat->tx_queues_to_use; 1998 u32 queue; 1999 2000 /* Free TX queue resources */ 2001 for (queue = 0; queue < tx_count; queue++) 2002 __free_dma_tx_desc_resources(priv, dma_conf, queue); 2003 } 2004 2005 /** 2006 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 2007 * @priv: private structure 2008 * @dma_conf: structure to take the dma data 2009 * @queue: RX queue index 2010 * Description: according to which descriptor can be used (extend or basic) 2011 * this function allocates the resources for TX and RX paths. In case of 2012 * reception, for example, it pre-allocated the RX socket buffer in order to 2013 * allow zero-copy mechanism. 2014 */ 2015 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2016 struct stmmac_dma_conf *dma_conf, 2017 u32 queue) 2018 { 2019 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 2020 struct stmmac_channel *ch = &priv->channel[queue]; 2021 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2022 struct page_pool_params pp_params = { 0 }; 2023 unsigned int num_pages; 2024 unsigned int napi_id; 2025 int ret; 2026 2027 rx_q->queue_index = queue; 2028 rx_q->priv_data = priv; 2029 2030 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2031 pp_params.pool_size = dma_conf->dma_rx_size; 2032 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2033 pp_params.order = ilog2(num_pages); 2034 pp_params.nid = dev_to_node(priv->device); 2035 pp_params.dev = priv->device; 2036 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2037 pp_params.offset = stmmac_rx_offset(priv); 2038 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2039 2040 rx_q->page_pool = page_pool_create(&pp_params); 2041 if (IS_ERR(rx_q->page_pool)) { 2042 ret = PTR_ERR(rx_q->page_pool); 2043 rx_q->page_pool = NULL; 2044 return ret; 2045 } 2046 2047 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2048 sizeof(*rx_q->buf_pool), 2049 GFP_KERNEL); 2050 if (!rx_q->buf_pool) 2051 return -ENOMEM; 2052 2053 if (priv->extend_desc) { 2054 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2055 dma_conf->dma_rx_size * 2056 sizeof(struct dma_extended_desc), 2057 &rx_q->dma_rx_phy, 2058 GFP_KERNEL); 2059 if (!rx_q->dma_erx) 2060 return -ENOMEM; 2061 2062 } else { 2063 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2064 dma_conf->dma_rx_size * 2065 sizeof(struct dma_desc), 2066 &rx_q->dma_rx_phy, 2067 GFP_KERNEL); 2068 if (!rx_q->dma_rx) 2069 return -ENOMEM; 2070 } 2071 2072 if (stmmac_xdp_is_enabled(priv) && 2073 test_bit(queue, priv->af_xdp_zc_qps)) 2074 napi_id = ch->rxtx_napi.napi_id; 2075 else 2076 napi_id = ch->rx_napi.napi_id; 2077 2078 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2079 rx_q->queue_index, 2080 napi_id); 2081 if (ret) { 2082 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2083 return -EINVAL; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2090 struct stmmac_dma_conf *dma_conf) 2091 { 2092 u32 rx_count = priv->plat->rx_queues_to_use; 2093 u32 queue; 2094 int ret; 2095 2096 /* RX queues buffers and DMA */ 2097 for (queue = 0; queue < rx_count; queue++) { 2098 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2099 if (ret) 2100 goto err_dma; 2101 } 2102 2103 return 0; 2104 2105 err_dma: 2106 free_dma_rx_desc_resources(priv, dma_conf); 2107 2108 return ret; 2109 } 2110 2111 /** 2112 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2113 * @priv: private structure 2114 * @dma_conf: structure to take the dma data 2115 * @queue: TX queue index 2116 * Description: according to which descriptor can be used (extend or basic) 2117 * this function allocates the resources for TX and RX paths. In case of 2118 * reception, for example, it pre-allocated the RX socket buffer in order to 2119 * allow zero-copy mechanism. 2120 */ 2121 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2122 struct stmmac_dma_conf *dma_conf, 2123 u32 queue) 2124 { 2125 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2126 size_t size; 2127 void *addr; 2128 2129 tx_q->queue_index = queue; 2130 tx_q->priv_data = priv; 2131 2132 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2133 sizeof(*tx_q->tx_skbuff_dma), 2134 GFP_KERNEL); 2135 if (!tx_q->tx_skbuff_dma) 2136 return -ENOMEM; 2137 2138 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2139 sizeof(struct sk_buff *), 2140 GFP_KERNEL); 2141 if (!tx_q->tx_skbuff) 2142 return -ENOMEM; 2143 2144 if (priv->extend_desc) 2145 size = sizeof(struct dma_extended_desc); 2146 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2147 size = sizeof(struct dma_edesc); 2148 else 2149 size = sizeof(struct dma_desc); 2150 2151 size *= dma_conf->dma_tx_size; 2152 2153 addr = dma_alloc_coherent(priv->device, size, 2154 &tx_q->dma_tx_phy, GFP_KERNEL); 2155 if (!addr) 2156 return -ENOMEM; 2157 2158 if (priv->extend_desc) 2159 tx_q->dma_etx = addr; 2160 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2161 tx_q->dma_entx = addr; 2162 else 2163 tx_q->dma_tx = addr; 2164 2165 return 0; 2166 } 2167 2168 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2169 struct stmmac_dma_conf *dma_conf) 2170 { 2171 u32 tx_count = priv->plat->tx_queues_to_use; 2172 u32 queue; 2173 int ret; 2174 2175 /* TX queues buffers and DMA */ 2176 for (queue = 0; queue < tx_count; queue++) { 2177 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2178 if (ret) 2179 goto err_dma; 2180 } 2181 2182 return 0; 2183 2184 err_dma: 2185 free_dma_tx_desc_resources(priv, dma_conf); 2186 return ret; 2187 } 2188 2189 /** 2190 * alloc_dma_desc_resources - alloc TX/RX resources. 2191 * @priv: private structure 2192 * @dma_conf: structure to take the dma data 2193 * Description: according to which descriptor can be used (extend or basic) 2194 * this function allocates the resources for TX and RX paths. In case of 2195 * reception, for example, it pre-allocated the RX socket buffer in order to 2196 * allow zero-copy mechanism. 2197 */ 2198 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2199 struct stmmac_dma_conf *dma_conf) 2200 { 2201 /* RX Allocation */ 2202 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2203 2204 if (ret) 2205 return ret; 2206 2207 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2208 2209 return ret; 2210 } 2211 2212 /** 2213 * free_dma_desc_resources - free dma desc resources 2214 * @priv: private structure 2215 * @dma_conf: structure to take the dma data 2216 */ 2217 static void free_dma_desc_resources(struct stmmac_priv *priv, 2218 struct stmmac_dma_conf *dma_conf) 2219 { 2220 /* Release the DMA TX socket buffers */ 2221 free_dma_tx_desc_resources(priv, dma_conf); 2222 2223 /* Release the DMA RX socket buffers later 2224 * to ensure all pending XDP_TX buffers are returned. 2225 */ 2226 free_dma_rx_desc_resources(priv, dma_conf); 2227 } 2228 2229 /** 2230 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2231 * @priv: driver private structure 2232 * Description: It is used for enabling the rx queues in the MAC 2233 */ 2234 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2235 { 2236 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2237 int queue; 2238 u8 mode; 2239 2240 for (queue = 0; queue < rx_queues_count; queue++) { 2241 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2242 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2243 } 2244 } 2245 2246 /** 2247 * stmmac_start_rx_dma - start RX DMA channel 2248 * @priv: driver private structure 2249 * @chan: RX channel index 2250 * Description: 2251 * This starts a RX DMA channel 2252 */ 2253 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2254 { 2255 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2256 stmmac_start_rx(priv, priv->ioaddr, chan); 2257 } 2258 2259 /** 2260 * stmmac_start_tx_dma - start TX DMA channel 2261 * @priv: driver private structure 2262 * @chan: TX channel index 2263 * Description: 2264 * This starts a TX DMA channel 2265 */ 2266 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2267 { 2268 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2269 stmmac_start_tx(priv, priv->ioaddr, chan); 2270 } 2271 2272 /** 2273 * stmmac_stop_rx_dma - stop RX DMA channel 2274 * @priv: driver private structure 2275 * @chan: RX channel index 2276 * Description: 2277 * This stops a RX DMA channel 2278 */ 2279 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2280 { 2281 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2282 stmmac_stop_rx(priv, priv->ioaddr, chan); 2283 } 2284 2285 /** 2286 * stmmac_stop_tx_dma - stop TX DMA channel 2287 * @priv: driver private structure 2288 * @chan: TX channel index 2289 * Description: 2290 * This stops a TX DMA channel 2291 */ 2292 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2293 { 2294 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2295 stmmac_stop_tx(priv, priv->ioaddr, chan); 2296 } 2297 2298 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2299 { 2300 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2301 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2302 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2303 u32 chan; 2304 2305 for (chan = 0; chan < dma_csr_ch; chan++) { 2306 struct stmmac_channel *ch = &priv->channel[chan]; 2307 unsigned long flags; 2308 2309 spin_lock_irqsave(&ch->lock, flags); 2310 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2311 spin_unlock_irqrestore(&ch->lock, flags); 2312 } 2313 } 2314 2315 /** 2316 * stmmac_start_all_dma - start all RX and TX DMA channels 2317 * @priv: driver private structure 2318 * Description: 2319 * This starts all the RX and TX DMA channels 2320 */ 2321 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2322 { 2323 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2324 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2325 u32 chan = 0; 2326 2327 for (chan = 0; chan < rx_channels_count; chan++) 2328 stmmac_start_rx_dma(priv, chan); 2329 2330 for (chan = 0; chan < tx_channels_count; chan++) 2331 stmmac_start_tx_dma(priv, chan); 2332 } 2333 2334 /** 2335 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2336 * @priv: driver private structure 2337 * Description: 2338 * This stops the RX and TX DMA channels 2339 */ 2340 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2341 { 2342 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2343 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2344 u32 chan = 0; 2345 2346 for (chan = 0; chan < rx_channels_count; chan++) 2347 stmmac_stop_rx_dma(priv, chan); 2348 2349 for (chan = 0; chan < tx_channels_count; chan++) 2350 stmmac_stop_tx_dma(priv, chan); 2351 } 2352 2353 /** 2354 * stmmac_dma_operation_mode - HW DMA operation mode 2355 * @priv: driver private structure 2356 * Description: it is used for configuring the DMA operation mode register in 2357 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2358 */ 2359 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2360 { 2361 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2362 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2363 int rxfifosz = priv->plat->rx_fifo_size; 2364 int txfifosz = priv->plat->tx_fifo_size; 2365 u32 txmode = 0; 2366 u32 rxmode = 0; 2367 u32 chan = 0; 2368 u8 qmode = 0; 2369 2370 if (rxfifosz == 0) 2371 rxfifosz = priv->dma_cap.rx_fifo_size; 2372 if (txfifosz == 0) 2373 txfifosz = priv->dma_cap.tx_fifo_size; 2374 2375 /* Adjust for real per queue fifo size */ 2376 rxfifosz /= rx_channels_count; 2377 txfifosz /= tx_channels_count; 2378 2379 if (priv->plat->force_thresh_dma_mode) { 2380 txmode = tc; 2381 rxmode = tc; 2382 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2383 /* 2384 * In case of GMAC, SF mode can be enabled 2385 * to perform the TX COE in HW. This depends on: 2386 * 1) TX COE if actually supported 2387 * 2) There is no bugged Jumbo frame support 2388 * that needs to not insert csum in the TDES. 2389 */ 2390 txmode = SF_DMA_MODE; 2391 rxmode = SF_DMA_MODE; 2392 priv->xstats.threshold = SF_DMA_MODE; 2393 } else { 2394 txmode = tc; 2395 rxmode = SF_DMA_MODE; 2396 } 2397 2398 /* configure all channels */ 2399 for (chan = 0; chan < rx_channels_count; chan++) { 2400 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2401 u32 buf_size; 2402 2403 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2404 2405 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2406 rxfifosz, qmode); 2407 2408 if (rx_q->xsk_pool) { 2409 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2410 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2411 buf_size, 2412 chan); 2413 } else { 2414 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2415 priv->dma_conf.dma_buf_sz, 2416 chan); 2417 } 2418 } 2419 2420 for (chan = 0; chan < tx_channels_count; chan++) { 2421 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2422 2423 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2424 txfifosz, qmode); 2425 } 2426 } 2427 2428 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2429 { 2430 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2431 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2432 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2433 unsigned int entry = tx_q->cur_tx; 2434 struct dma_desc *tx_desc = NULL; 2435 struct xdp_desc xdp_desc; 2436 bool work_done = true; 2437 u32 tx_set_ic_bit = 0; 2438 unsigned long flags; 2439 2440 /* Avoids TX time-out as we are sharing with slow path */ 2441 txq_trans_cond_update(nq); 2442 2443 budget = min(budget, stmmac_tx_avail(priv, queue)); 2444 2445 while (budget-- > 0) { 2446 dma_addr_t dma_addr; 2447 bool set_ic; 2448 2449 /* We are sharing with slow path and stop XSK TX desc submission when 2450 * available TX ring is less than threshold. 2451 */ 2452 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2453 !netif_carrier_ok(priv->dev)) { 2454 work_done = false; 2455 break; 2456 } 2457 2458 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2459 break; 2460 2461 if (likely(priv->extend_desc)) 2462 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2463 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2464 tx_desc = &tx_q->dma_entx[entry].basic; 2465 else 2466 tx_desc = tx_q->dma_tx + entry; 2467 2468 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2469 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2470 2471 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2472 2473 /* To return XDP buffer to XSK pool, we simple call 2474 * xsk_tx_completed(), so we don't need to fill up 2475 * 'buf' and 'xdpf'. 2476 */ 2477 tx_q->tx_skbuff_dma[entry].buf = 0; 2478 tx_q->xdpf[entry] = NULL; 2479 2480 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2481 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2482 tx_q->tx_skbuff_dma[entry].last_segment = true; 2483 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2484 2485 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2486 2487 tx_q->tx_count_frames++; 2488 2489 if (!priv->tx_coal_frames[queue]) 2490 set_ic = false; 2491 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2492 set_ic = true; 2493 else 2494 set_ic = false; 2495 2496 if (set_ic) { 2497 tx_q->tx_count_frames = 0; 2498 stmmac_set_tx_ic(priv, tx_desc); 2499 tx_set_ic_bit++; 2500 } 2501 2502 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2503 true, priv->mode, true, true, 2504 xdp_desc.len); 2505 2506 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2507 2508 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2509 entry = tx_q->cur_tx; 2510 } 2511 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 2512 tx_q->txq_stats.tx_set_ic_bit += tx_set_ic_bit; 2513 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 2514 2515 if (tx_desc) { 2516 stmmac_flush_tx_descriptors(priv, queue); 2517 xsk_tx_release(pool); 2518 } 2519 2520 /* Return true if all of the 3 conditions are met 2521 * a) TX Budget is still available 2522 * b) work_done = true when XSK TX desc peek is empty (no more 2523 * pending XSK TX for transmission) 2524 */ 2525 return !!budget && work_done; 2526 } 2527 2528 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2529 { 2530 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2531 tc += 64; 2532 2533 if (priv->plat->force_thresh_dma_mode) 2534 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2535 else 2536 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2537 chan); 2538 2539 priv->xstats.threshold = tc; 2540 } 2541 } 2542 2543 /** 2544 * stmmac_tx_clean - to manage the transmission completion 2545 * @priv: driver private structure 2546 * @budget: napi budget limiting this functions packet handling 2547 * @queue: TX queue index 2548 * Description: it reclaims the transmit resources after transmission completes. 2549 */ 2550 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2551 { 2552 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2553 unsigned int bytes_compl = 0, pkts_compl = 0; 2554 unsigned int entry, xmits = 0, count = 0; 2555 u32 tx_packets = 0, tx_errors = 0; 2556 unsigned long flags; 2557 2558 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2559 2560 tx_q->xsk_frames_done = 0; 2561 2562 entry = tx_q->dirty_tx; 2563 2564 /* Try to clean all TX complete frame in 1 shot */ 2565 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2566 struct xdp_frame *xdpf; 2567 struct sk_buff *skb; 2568 struct dma_desc *p; 2569 int status; 2570 2571 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2572 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2573 xdpf = tx_q->xdpf[entry]; 2574 skb = NULL; 2575 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2576 xdpf = NULL; 2577 skb = tx_q->tx_skbuff[entry]; 2578 } else { 2579 xdpf = NULL; 2580 skb = NULL; 2581 } 2582 2583 if (priv->extend_desc) 2584 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2585 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2586 p = &tx_q->dma_entx[entry].basic; 2587 else 2588 p = tx_q->dma_tx + entry; 2589 2590 status = stmmac_tx_status(priv, &priv->xstats, p, priv->ioaddr); 2591 /* Check if the descriptor is owned by the DMA */ 2592 if (unlikely(status & tx_dma_own)) 2593 break; 2594 2595 count++; 2596 2597 /* Make sure descriptor fields are read after reading 2598 * the own bit. 2599 */ 2600 dma_rmb(); 2601 2602 /* Just consider the last segment and ...*/ 2603 if (likely(!(status & tx_not_ls))) { 2604 /* ... verify the status error condition */ 2605 if (unlikely(status & tx_err)) { 2606 tx_errors++; 2607 if (unlikely(status & tx_err_bump_tc)) 2608 stmmac_bump_dma_threshold(priv, queue); 2609 } else { 2610 tx_packets++; 2611 } 2612 if (skb) 2613 stmmac_get_tx_hwtstamp(priv, p, skb); 2614 } 2615 2616 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2617 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2618 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2619 dma_unmap_page(priv->device, 2620 tx_q->tx_skbuff_dma[entry].buf, 2621 tx_q->tx_skbuff_dma[entry].len, 2622 DMA_TO_DEVICE); 2623 else 2624 dma_unmap_single(priv->device, 2625 tx_q->tx_skbuff_dma[entry].buf, 2626 tx_q->tx_skbuff_dma[entry].len, 2627 DMA_TO_DEVICE); 2628 tx_q->tx_skbuff_dma[entry].buf = 0; 2629 tx_q->tx_skbuff_dma[entry].len = 0; 2630 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2631 } 2632 2633 stmmac_clean_desc3(priv, tx_q, p); 2634 2635 tx_q->tx_skbuff_dma[entry].last_segment = false; 2636 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2637 2638 if (xdpf && 2639 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2640 xdp_return_frame_rx_napi(xdpf); 2641 tx_q->xdpf[entry] = NULL; 2642 } 2643 2644 if (xdpf && 2645 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2646 xdp_return_frame(xdpf); 2647 tx_q->xdpf[entry] = NULL; 2648 } 2649 2650 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2651 tx_q->xsk_frames_done++; 2652 2653 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2654 if (likely(skb)) { 2655 pkts_compl++; 2656 bytes_compl += skb->len; 2657 dev_consume_skb_any(skb); 2658 tx_q->tx_skbuff[entry] = NULL; 2659 } 2660 } 2661 2662 stmmac_release_tx_desc(priv, p, priv->mode); 2663 2664 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2665 } 2666 tx_q->dirty_tx = entry; 2667 2668 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2669 pkts_compl, bytes_compl); 2670 2671 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2672 queue))) && 2673 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2674 2675 netif_dbg(priv, tx_done, priv->dev, 2676 "%s: restart transmit\n", __func__); 2677 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2678 } 2679 2680 if (tx_q->xsk_pool) { 2681 bool work_done; 2682 2683 if (tx_q->xsk_frames_done) 2684 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2685 2686 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2687 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2688 2689 /* For XSK TX, we try to send as many as possible. 2690 * If XSK work done (XSK TX desc empty and budget still 2691 * available), return "budget - 1" to reenable TX IRQ. 2692 * Else, return "budget" to make NAPI continue polling. 2693 */ 2694 work_done = stmmac_xdp_xmit_zc(priv, queue, 2695 STMMAC_XSK_TX_BUDGET_MAX); 2696 if (work_done) 2697 xmits = budget - 1; 2698 else 2699 xmits = budget; 2700 } 2701 2702 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2703 priv->eee_sw_timer_en) { 2704 if (stmmac_enable_eee_mode(priv)) 2705 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2706 } 2707 2708 /* We still have pending packets, let's call for a new scheduling */ 2709 if (tx_q->dirty_tx != tx_q->cur_tx) 2710 hrtimer_start(&tx_q->txtimer, 2711 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2712 HRTIMER_MODE_REL); 2713 2714 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 2715 tx_q->txq_stats.tx_packets += tx_packets; 2716 tx_q->txq_stats.tx_pkt_n += tx_packets; 2717 tx_q->txq_stats.tx_clean++; 2718 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 2719 2720 priv->xstats.tx_errors += tx_errors; 2721 2722 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2723 2724 /* Combine decisions from TX clean and XSK TX */ 2725 return max(count, xmits); 2726 } 2727 2728 /** 2729 * stmmac_tx_err - to manage the tx error 2730 * @priv: driver private structure 2731 * @chan: channel index 2732 * Description: it cleans the descriptors and restarts the transmission 2733 * in case of transmission errors. 2734 */ 2735 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2736 { 2737 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2738 2739 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2740 2741 stmmac_stop_tx_dma(priv, chan); 2742 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2743 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2744 stmmac_reset_tx_queue(priv, chan); 2745 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2746 tx_q->dma_tx_phy, chan); 2747 stmmac_start_tx_dma(priv, chan); 2748 2749 priv->xstats.tx_errors++; 2750 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2751 } 2752 2753 /** 2754 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2755 * @priv: driver private structure 2756 * @txmode: TX operating mode 2757 * @rxmode: RX operating mode 2758 * @chan: channel index 2759 * Description: it is used for configuring of the DMA operation mode in 2760 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2761 * mode. 2762 */ 2763 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2764 u32 rxmode, u32 chan) 2765 { 2766 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2767 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2768 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2769 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2770 int rxfifosz = priv->plat->rx_fifo_size; 2771 int txfifosz = priv->plat->tx_fifo_size; 2772 2773 if (rxfifosz == 0) 2774 rxfifosz = priv->dma_cap.rx_fifo_size; 2775 if (txfifosz == 0) 2776 txfifosz = priv->dma_cap.tx_fifo_size; 2777 2778 /* Adjust for real per queue fifo size */ 2779 rxfifosz /= rx_channels_count; 2780 txfifosz /= tx_channels_count; 2781 2782 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2783 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2784 } 2785 2786 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2787 { 2788 int ret; 2789 2790 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2791 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2792 if (ret && (ret != -EINVAL)) { 2793 stmmac_global_err(priv); 2794 return true; 2795 } 2796 2797 return false; 2798 } 2799 2800 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2801 { 2802 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2803 &priv->xstats, chan, dir); 2804 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2805 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2806 struct stmmac_channel *ch = &priv->channel[chan]; 2807 struct napi_struct *rx_napi; 2808 struct napi_struct *tx_napi; 2809 unsigned long flags; 2810 2811 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2812 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2813 2814 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2815 if (napi_schedule_prep(rx_napi)) { 2816 spin_lock_irqsave(&ch->lock, flags); 2817 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2818 spin_unlock_irqrestore(&ch->lock, flags); 2819 __napi_schedule(rx_napi); 2820 } 2821 } 2822 2823 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2824 if (napi_schedule_prep(tx_napi)) { 2825 spin_lock_irqsave(&ch->lock, flags); 2826 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2827 spin_unlock_irqrestore(&ch->lock, flags); 2828 __napi_schedule(tx_napi); 2829 } 2830 } 2831 2832 return status; 2833 } 2834 2835 /** 2836 * stmmac_dma_interrupt - DMA ISR 2837 * @priv: driver private structure 2838 * Description: this is the DMA ISR. It is called by the main ISR. 2839 * It calls the dwmac dma routine and schedule poll method in case of some 2840 * work can be done. 2841 */ 2842 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2843 { 2844 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2845 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2846 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2847 tx_channel_count : rx_channel_count; 2848 u32 chan; 2849 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2850 2851 /* Make sure we never check beyond our status buffer. */ 2852 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2853 channels_to_check = ARRAY_SIZE(status); 2854 2855 for (chan = 0; chan < channels_to_check; chan++) 2856 status[chan] = stmmac_napi_check(priv, chan, 2857 DMA_DIR_RXTX); 2858 2859 for (chan = 0; chan < tx_channel_count; chan++) { 2860 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2861 /* Try to bump up the dma threshold on this failure */ 2862 stmmac_bump_dma_threshold(priv, chan); 2863 } else if (unlikely(status[chan] == tx_hard_error)) { 2864 stmmac_tx_err(priv, chan); 2865 } 2866 } 2867 } 2868 2869 /** 2870 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2871 * @priv: driver private structure 2872 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2873 */ 2874 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2875 { 2876 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2877 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2878 2879 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2880 2881 if (priv->dma_cap.rmon) { 2882 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2883 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2884 } else 2885 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2886 } 2887 2888 /** 2889 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2890 * @priv: driver private structure 2891 * Description: 2892 * new GMAC chip generations have a new register to indicate the 2893 * presence of the optional feature/functions. 2894 * This can be also used to override the value passed through the 2895 * platform and necessary for old MAC10/100 and GMAC chips. 2896 */ 2897 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2898 { 2899 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2900 } 2901 2902 /** 2903 * stmmac_check_ether_addr - check if the MAC addr is valid 2904 * @priv: driver private structure 2905 * Description: 2906 * it is to verify if the MAC address is valid, in case of failures it 2907 * generates a random MAC address 2908 */ 2909 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2910 { 2911 u8 addr[ETH_ALEN]; 2912 2913 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2914 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2915 if (is_valid_ether_addr(addr)) 2916 eth_hw_addr_set(priv->dev, addr); 2917 else 2918 eth_hw_addr_random(priv->dev); 2919 dev_info(priv->device, "device MAC address %pM\n", 2920 priv->dev->dev_addr); 2921 } 2922 } 2923 2924 /** 2925 * stmmac_init_dma_engine - DMA init. 2926 * @priv: driver private structure 2927 * Description: 2928 * It inits the DMA invoking the specific MAC/GMAC callback. 2929 * Some DMA parameters can be passed from the platform; 2930 * in case of these are not passed a default is kept for the MAC or GMAC. 2931 */ 2932 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2933 { 2934 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2935 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2936 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2937 struct stmmac_rx_queue *rx_q; 2938 struct stmmac_tx_queue *tx_q; 2939 u32 chan = 0; 2940 int atds = 0; 2941 int ret = 0; 2942 2943 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2944 dev_err(priv->device, "Invalid DMA configuration\n"); 2945 return -EINVAL; 2946 } 2947 2948 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2949 atds = 1; 2950 2951 ret = stmmac_reset(priv, priv->ioaddr); 2952 if (ret) { 2953 dev_err(priv->device, "Failed to reset the dma\n"); 2954 return ret; 2955 } 2956 2957 /* DMA Configuration */ 2958 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2959 2960 if (priv->plat->axi) 2961 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2962 2963 /* DMA CSR Channel configuration */ 2964 for (chan = 0; chan < dma_csr_ch; chan++) { 2965 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2966 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2967 } 2968 2969 /* DMA RX Channel Configuration */ 2970 for (chan = 0; chan < rx_channels_count; chan++) { 2971 rx_q = &priv->dma_conf.rx_queue[chan]; 2972 2973 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2974 rx_q->dma_rx_phy, chan); 2975 2976 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2977 (rx_q->buf_alloc_num * 2978 sizeof(struct dma_desc)); 2979 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2980 rx_q->rx_tail_addr, chan); 2981 } 2982 2983 /* DMA TX Channel Configuration */ 2984 for (chan = 0; chan < tx_channels_count; chan++) { 2985 tx_q = &priv->dma_conf.tx_queue[chan]; 2986 2987 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2988 tx_q->dma_tx_phy, chan); 2989 2990 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2991 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2992 tx_q->tx_tail_addr, chan); 2993 } 2994 2995 return ret; 2996 } 2997 2998 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2999 { 3000 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3001 3002 hrtimer_start(&tx_q->txtimer, 3003 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 3004 HRTIMER_MODE_REL); 3005 } 3006 3007 /** 3008 * stmmac_tx_timer - mitigation sw timer for tx. 3009 * @t: data pointer 3010 * Description: 3011 * This is the timer handler to directly invoke the stmmac_tx_clean. 3012 */ 3013 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 3014 { 3015 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 3016 struct stmmac_priv *priv = tx_q->priv_data; 3017 struct stmmac_channel *ch; 3018 struct napi_struct *napi; 3019 3020 ch = &priv->channel[tx_q->queue_index]; 3021 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 3022 3023 if (likely(napi_schedule_prep(napi))) { 3024 unsigned long flags; 3025 3026 spin_lock_irqsave(&ch->lock, flags); 3027 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 3028 spin_unlock_irqrestore(&ch->lock, flags); 3029 __napi_schedule(napi); 3030 } 3031 3032 return HRTIMER_NORESTART; 3033 } 3034 3035 /** 3036 * stmmac_init_coalesce - init mitigation options. 3037 * @priv: driver private structure 3038 * Description: 3039 * This inits the coalesce parameters: i.e. timer rate, 3040 * timer handler and default threshold used for enabling the 3041 * interrupt on completion bit. 3042 */ 3043 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3044 { 3045 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3046 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3047 u32 chan; 3048 3049 for (chan = 0; chan < tx_channel_count; chan++) { 3050 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3051 3052 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3053 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3054 3055 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3056 tx_q->txtimer.function = stmmac_tx_timer; 3057 } 3058 3059 for (chan = 0; chan < rx_channel_count; chan++) 3060 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3061 } 3062 3063 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3064 { 3065 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3066 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3067 u32 chan; 3068 3069 /* set TX ring length */ 3070 for (chan = 0; chan < tx_channels_count; chan++) 3071 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3072 (priv->dma_conf.dma_tx_size - 1), chan); 3073 3074 /* set RX ring length */ 3075 for (chan = 0; chan < rx_channels_count; chan++) 3076 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3077 (priv->dma_conf.dma_rx_size - 1), chan); 3078 } 3079 3080 /** 3081 * stmmac_set_tx_queue_weight - Set TX queue weight 3082 * @priv: driver private structure 3083 * Description: It is used for setting TX queues weight 3084 */ 3085 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3086 { 3087 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3088 u32 weight; 3089 u32 queue; 3090 3091 for (queue = 0; queue < tx_queues_count; queue++) { 3092 weight = priv->plat->tx_queues_cfg[queue].weight; 3093 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3094 } 3095 } 3096 3097 /** 3098 * stmmac_configure_cbs - Configure CBS in TX queue 3099 * @priv: driver private structure 3100 * Description: It is used for configuring CBS in AVB TX queues 3101 */ 3102 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3103 { 3104 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3105 u32 mode_to_use; 3106 u32 queue; 3107 3108 /* queue 0 is reserved for legacy traffic */ 3109 for (queue = 1; queue < tx_queues_count; queue++) { 3110 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3111 if (mode_to_use == MTL_QUEUE_DCB) 3112 continue; 3113 3114 stmmac_config_cbs(priv, priv->hw, 3115 priv->plat->tx_queues_cfg[queue].send_slope, 3116 priv->plat->tx_queues_cfg[queue].idle_slope, 3117 priv->plat->tx_queues_cfg[queue].high_credit, 3118 priv->plat->tx_queues_cfg[queue].low_credit, 3119 queue); 3120 } 3121 } 3122 3123 /** 3124 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3125 * @priv: driver private structure 3126 * Description: It is used for mapping RX queues to RX dma channels 3127 */ 3128 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3129 { 3130 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3131 u32 queue; 3132 u32 chan; 3133 3134 for (queue = 0; queue < rx_queues_count; queue++) { 3135 chan = priv->plat->rx_queues_cfg[queue].chan; 3136 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3137 } 3138 } 3139 3140 /** 3141 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3142 * @priv: driver private structure 3143 * Description: It is used for configuring the RX Queue Priority 3144 */ 3145 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3146 { 3147 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3148 u32 queue; 3149 u32 prio; 3150 3151 for (queue = 0; queue < rx_queues_count; queue++) { 3152 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3153 continue; 3154 3155 prio = priv->plat->rx_queues_cfg[queue].prio; 3156 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3157 } 3158 } 3159 3160 /** 3161 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3162 * @priv: driver private structure 3163 * Description: It is used for configuring the TX Queue Priority 3164 */ 3165 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3166 { 3167 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3168 u32 queue; 3169 u32 prio; 3170 3171 for (queue = 0; queue < tx_queues_count; queue++) { 3172 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3173 continue; 3174 3175 prio = priv->plat->tx_queues_cfg[queue].prio; 3176 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3177 } 3178 } 3179 3180 /** 3181 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3182 * @priv: driver private structure 3183 * Description: It is used for configuring the RX queue routing 3184 */ 3185 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3186 { 3187 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3188 u32 queue; 3189 u8 packet; 3190 3191 for (queue = 0; queue < rx_queues_count; queue++) { 3192 /* no specific packet type routing specified for the queue */ 3193 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3194 continue; 3195 3196 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3197 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3198 } 3199 } 3200 3201 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3202 { 3203 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3204 priv->rss.enable = false; 3205 return; 3206 } 3207 3208 if (priv->dev->features & NETIF_F_RXHASH) 3209 priv->rss.enable = true; 3210 else 3211 priv->rss.enable = false; 3212 3213 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3214 priv->plat->rx_queues_to_use); 3215 } 3216 3217 /** 3218 * stmmac_mtl_configuration - Configure MTL 3219 * @priv: driver private structure 3220 * Description: It is used for configurring MTL 3221 */ 3222 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3223 { 3224 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3225 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3226 3227 if (tx_queues_count > 1) 3228 stmmac_set_tx_queue_weight(priv); 3229 3230 /* Configure MTL RX algorithms */ 3231 if (rx_queues_count > 1) 3232 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3233 priv->plat->rx_sched_algorithm); 3234 3235 /* Configure MTL TX algorithms */ 3236 if (tx_queues_count > 1) 3237 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3238 priv->plat->tx_sched_algorithm); 3239 3240 /* Configure CBS in AVB TX queues */ 3241 if (tx_queues_count > 1) 3242 stmmac_configure_cbs(priv); 3243 3244 /* Map RX MTL to DMA channels */ 3245 stmmac_rx_queue_dma_chan_map(priv); 3246 3247 /* Enable MAC RX Queues */ 3248 stmmac_mac_enable_rx_queues(priv); 3249 3250 /* Set RX priorities */ 3251 if (rx_queues_count > 1) 3252 stmmac_mac_config_rx_queues_prio(priv); 3253 3254 /* Set TX priorities */ 3255 if (tx_queues_count > 1) 3256 stmmac_mac_config_tx_queues_prio(priv); 3257 3258 /* Set RX routing */ 3259 if (rx_queues_count > 1) 3260 stmmac_mac_config_rx_queues_routing(priv); 3261 3262 /* Receive Side Scaling */ 3263 if (rx_queues_count > 1) 3264 stmmac_mac_config_rss(priv); 3265 } 3266 3267 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3268 { 3269 if (priv->dma_cap.asp) { 3270 netdev_info(priv->dev, "Enabling Safety Features\n"); 3271 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3272 priv->plat->safety_feat_cfg); 3273 } else { 3274 netdev_info(priv->dev, "No Safety Features support found\n"); 3275 } 3276 } 3277 3278 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3279 { 3280 char *name; 3281 3282 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3283 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3284 3285 name = priv->wq_name; 3286 sprintf(name, "%s-fpe", priv->dev->name); 3287 3288 priv->fpe_wq = create_singlethread_workqueue(name); 3289 if (!priv->fpe_wq) { 3290 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3291 3292 return -ENOMEM; 3293 } 3294 netdev_info(priv->dev, "FPE workqueue start"); 3295 3296 return 0; 3297 } 3298 3299 /** 3300 * stmmac_hw_setup - setup mac in a usable state. 3301 * @dev : pointer to the device structure. 3302 * @ptp_register: register PTP if set 3303 * Description: 3304 * this is the main function to setup the HW in a usable state because the 3305 * dma engine is reset, the core registers are configured (e.g. AXI, 3306 * Checksum features, timers). The DMA is ready to start receiving and 3307 * transmitting. 3308 * Return value: 3309 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3310 * file on failure. 3311 */ 3312 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3313 { 3314 struct stmmac_priv *priv = netdev_priv(dev); 3315 u32 rx_cnt = priv->plat->rx_queues_to_use; 3316 u32 tx_cnt = priv->plat->tx_queues_to_use; 3317 bool sph_en; 3318 u32 chan; 3319 int ret; 3320 3321 /* DMA initialization and SW reset */ 3322 ret = stmmac_init_dma_engine(priv); 3323 if (ret < 0) { 3324 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3325 __func__); 3326 return ret; 3327 } 3328 3329 /* Copy the MAC addr into the HW */ 3330 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3331 3332 /* PS and related bits will be programmed according to the speed */ 3333 if (priv->hw->pcs) { 3334 int speed = priv->plat->mac_port_sel_speed; 3335 3336 if ((speed == SPEED_10) || (speed == SPEED_100) || 3337 (speed == SPEED_1000)) { 3338 priv->hw->ps = speed; 3339 } else { 3340 dev_warn(priv->device, "invalid port speed\n"); 3341 priv->hw->ps = 0; 3342 } 3343 } 3344 3345 /* Initialize the MAC Core */ 3346 stmmac_core_init(priv, priv->hw, dev); 3347 3348 /* Initialize MTL*/ 3349 stmmac_mtl_configuration(priv); 3350 3351 /* Initialize Safety Features */ 3352 stmmac_safety_feat_configuration(priv); 3353 3354 ret = stmmac_rx_ipc(priv, priv->hw); 3355 if (!ret) { 3356 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3357 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3358 priv->hw->rx_csum = 0; 3359 } 3360 3361 /* Enable the MAC Rx/Tx */ 3362 stmmac_mac_set(priv, priv->ioaddr, true); 3363 3364 /* Set the HW DMA mode and the COE */ 3365 stmmac_dma_operation_mode(priv); 3366 3367 stmmac_mmc_setup(priv); 3368 3369 if (ptp_register) { 3370 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3371 if (ret < 0) 3372 netdev_warn(priv->dev, 3373 "failed to enable PTP reference clock: %pe\n", 3374 ERR_PTR(ret)); 3375 } 3376 3377 ret = stmmac_init_ptp(priv); 3378 if (ret == -EOPNOTSUPP) 3379 netdev_info(priv->dev, "PTP not supported by HW\n"); 3380 else if (ret) 3381 netdev_warn(priv->dev, "PTP init failed\n"); 3382 else if (ptp_register) 3383 stmmac_ptp_register(priv); 3384 3385 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3386 3387 /* Convert the timer from msec to usec */ 3388 if (!priv->tx_lpi_timer) 3389 priv->tx_lpi_timer = eee_timer * 1000; 3390 3391 if (priv->use_riwt) { 3392 u32 queue; 3393 3394 for (queue = 0; queue < rx_cnt; queue++) { 3395 if (!priv->rx_riwt[queue]) 3396 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3397 3398 stmmac_rx_watchdog(priv, priv->ioaddr, 3399 priv->rx_riwt[queue], queue); 3400 } 3401 } 3402 3403 if (priv->hw->pcs) 3404 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3405 3406 /* set TX and RX rings length */ 3407 stmmac_set_rings_length(priv); 3408 3409 /* Enable TSO */ 3410 if (priv->tso) { 3411 for (chan = 0; chan < tx_cnt; chan++) { 3412 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3413 3414 /* TSO and TBS cannot co-exist */ 3415 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3416 continue; 3417 3418 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3419 } 3420 } 3421 3422 /* Enable Split Header */ 3423 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3424 for (chan = 0; chan < rx_cnt; chan++) 3425 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3426 3427 3428 /* VLAN Tag Insertion */ 3429 if (priv->dma_cap.vlins) 3430 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3431 3432 /* TBS */ 3433 for (chan = 0; chan < tx_cnt; chan++) { 3434 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3435 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3436 3437 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3438 } 3439 3440 /* Configure real RX and TX queues */ 3441 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3442 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3443 3444 /* Start the ball rolling... */ 3445 stmmac_start_all_dma(priv); 3446 3447 if (priv->dma_cap.fpesel) { 3448 stmmac_fpe_start_wq(priv); 3449 3450 if (priv->plat->fpe_cfg->enable) 3451 stmmac_fpe_handshake(priv, true); 3452 } 3453 3454 return 0; 3455 } 3456 3457 static void stmmac_hw_teardown(struct net_device *dev) 3458 { 3459 struct stmmac_priv *priv = netdev_priv(dev); 3460 3461 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3462 } 3463 3464 static void stmmac_free_irq(struct net_device *dev, 3465 enum request_irq_err irq_err, int irq_idx) 3466 { 3467 struct stmmac_priv *priv = netdev_priv(dev); 3468 int j; 3469 3470 switch (irq_err) { 3471 case REQ_IRQ_ERR_ALL: 3472 irq_idx = priv->plat->tx_queues_to_use; 3473 fallthrough; 3474 case REQ_IRQ_ERR_TX: 3475 for (j = irq_idx - 1; j >= 0; j--) { 3476 if (priv->tx_irq[j] > 0) { 3477 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3478 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3479 } 3480 } 3481 irq_idx = priv->plat->rx_queues_to_use; 3482 fallthrough; 3483 case REQ_IRQ_ERR_RX: 3484 for (j = irq_idx - 1; j >= 0; j--) { 3485 if (priv->rx_irq[j] > 0) { 3486 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3487 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3488 } 3489 } 3490 3491 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3492 free_irq(priv->sfty_ue_irq, dev); 3493 fallthrough; 3494 case REQ_IRQ_ERR_SFTY_UE: 3495 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3496 free_irq(priv->sfty_ce_irq, dev); 3497 fallthrough; 3498 case REQ_IRQ_ERR_SFTY_CE: 3499 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3500 free_irq(priv->lpi_irq, dev); 3501 fallthrough; 3502 case REQ_IRQ_ERR_LPI: 3503 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3504 free_irq(priv->wol_irq, dev); 3505 fallthrough; 3506 case REQ_IRQ_ERR_WOL: 3507 free_irq(dev->irq, dev); 3508 fallthrough; 3509 case REQ_IRQ_ERR_MAC: 3510 case REQ_IRQ_ERR_NO: 3511 /* If MAC IRQ request error, no more IRQ to free */ 3512 break; 3513 } 3514 } 3515 3516 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3517 { 3518 struct stmmac_priv *priv = netdev_priv(dev); 3519 enum request_irq_err irq_err; 3520 cpumask_t cpu_mask; 3521 int irq_idx = 0; 3522 char *int_name; 3523 int ret; 3524 int i; 3525 3526 /* For common interrupt */ 3527 int_name = priv->int_name_mac; 3528 sprintf(int_name, "%s:%s", dev->name, "mac"); 3529 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3530 0, int_name, dev); 3531 if (unlikely(ret < 0)) { 3532 netdev_err(priv->dev, 3533 "%s: alloc mac MSI %d (error: %d)\n", 3534 __func__, dev->irq, ret); 3535 irq_err = REQ_IRQ_ERR_MAC; 3536 goto irq_error; 3537 } 3538 3539 /* Request the Wake IRQ in case of another line 3540 * is used for WoL 3541 */ 3542 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3543 int_name = priv->int_name_wol; 3544 sprintf(int_name, "%s:%s", dev->name, "wol"); 3545 ret = request_irq(priv->wol_irq, 3546 stmmac_mac_interrupt, 3547 0, int_name, dev); 3548 if (unlikely(ret < 0)) { 3549 netdev_err(priv->dev, 3550 "%s: alloc wol MSI %d (error: %d)\n", 3551 __func__, priv->wol_irq, ret); 3552 irq_err = REQ_IRQ_ERR_WOL; 3553 goto irq_error; 3554 } 3555 } 3556 3557 /* Request the LPI IRQ in case of another line 3558 * is used for LPI 3559 */ 3560 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3561 int_name = priv->int_name_lpi; 3562 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3563 ret = request_irq(priv->lpi_irq, 3564 stmmac_mac_interrupt, 3565 0, int_name, dev); 3566 if (unlikely(ret < 0)) { 3567 netdev_err(priv->dev, 3568 "%s: alloc lpi MSI %d (error: %d)\n", 3569 __func__, priv->lpi_irq, ret); 3570 irq_err = REQ_IRQ_ERR_LPI; 3571 goto irq_error; 3572 } 3573 } 3574 3575 /* Request the Safety Feature Correctible Error line in 3576 * case of another line is used 3577 */ 3578 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3579 int_name = priv->int_name_sfty_ce; 3580 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3581 ret = request_irq(priv->sfty_ce_irq, 3582 stmmac_safety_interrupt, 3583 0, int_name, dev); 3584 if (unlikely(ret < 0)) { 3585 netdev_err(priv->dev, 3586 "%s: alloc sfty ce MSI %d (error: %d)\n", 3587 __func__, priv->sfty_ce_irq, ret); 3588 irq_err = REQ_IRQ_ERR_SFTY_CE; 3589 goto irq_error; 3590 } 3591 } 3592 3593 /* Request the Safety Feature Uncorrectible Error line in 3594 * case of another line is used 3595 */ 3596 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3597 int_name = priv->int_name_sfty_ue; 3598 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3599 ret = request_irq(priv->sfty_ue_irq, 3600 stmmac_safety_interrupt, 3601 0, int_name, dev); 3602 if (unlikely(ret < 0)) { 3603 netdev_err(priv->dev, 3604 "%s: alloc sfty ue MSI %d (error: %d)\n", 3605 __func__, priv->sfty_ue_irq, ret); 3606 irq_err = REQ_IRQ_ERR_SFTY_UE; 3607 goto irq_error; 3608 } 3609 } 3610 3611 /* Request Rx MSI irq */ 3612 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3613 if (i >= MTL_MAX_RX_QUEUES) 3614 break; 3615 if (priv->rx_irq[i] == 0) 3616 continue; 3617 3618 int_name = priv->int_name_rx_irq[i]; 3619 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3620 ret = request_irq(priv->rx_irq[i], 3621 stmmac_msi_intr_rx, 3622 0, int_name, &priv->dma_conf.rx_queue[i]); 3623 if (unlikely(ret < 0)) { 3624 netdev_err(priv->dev, 3625 "%s: alloc rx-%d MSI %d (error: %d)\n", 3626 __func__, i, priv->rx_irq[i], ret); 3627 irq_err = REQ_IRQ_ERR_RX; 3628 irq_idx = i; 3629 goto irq_error; 3630 } 3631 cpumask_clear(&cpu_mask); 3632 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3633 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3634 } 3635 3636 /* Request Tx MSI irq */ 3637 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3638 if (i >= MTL_MAX_TX_QUEUES) 3639 break; 3640 if (priv->tx_irq[i] == 0) 3641 continue; 3642 3643 int_name = priv->int_name_tx_irq[i]; 3644 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3645 ret = request_irq(priv->tx_irq[i], 3646 stmmac_msi_intr_tx, 3647 0, int_name, &priv->dma_conf.tx_queue[i]); 3648 if (unlikely(ret < 0)) { 3649 netdev_err(priv->dev, 3650 "%s: alloc tx-%d MSI %d (error: %d)\n", 3651 __func__, i, priv->tx_irq[i], ret); 3652 irq_err = REQ_IRQ_ERR_TX; 3653 irq_idx = i; 3654 goto irq_error; 3655 } 3656 cpumask_clear(&cpu_mask); 3657 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3658 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3659 } 3660 3661 return 0; 3662 3663 irq_error: 3664 stmmac_free_irq(dev, irq_err, irq_idx); 3665 return ret; 3666 } 3667 3668 static int stmmac_request_irq_single(struct net_device *dev) 3669 { 3670 struct stmmac_priv *priv = netdev_priv(dev); 3671 enum request_irq_err irq_err; 3672 int ret; 3673 3674 ret = request_irq(dev->irq, stmmac_interrupt, 3675 IRQF_SHARED, dev->name, dev); 3676 if (unlikely(ret < 0)) { 3677 netdev_err(priv->dev, 3678 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3679 __func__, dev->irq, ret); 3680 irq_err = REQ_IRQ_ERR_MAC; 3681 goto irq_error; 3682 } 3683 3684 /* Request the Wake IRQ in case of another line 3685 * is used for WoL 3686 */ 3687 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3688 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3689 IRQF_SHARED, dev->name, dev); 3690 if (unlikely(ret < 0)) { 3691 netdev_err(priv->dev, 3692 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3693 __func__, priv->wol_irq, ret); 3694 irq_err = REQ_IRQ_ERR_WOL; 3695 goto irq_error; 3696 } 3697 } 3698 3699 /* Request the IRQ lines */ 3700 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3701 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3702 IRQF_SHARED, dev->name, dev); 3703 if (unlikely(ret < 0)) { 3704 netdev_err(priv->dev, 3705 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3706 __func__, priv->lpi_irq, ret); 3707 irq_err = REQ_IRQ_ERR_LPI; 3708 goto irq_error; 3709 } 3710 } 3711 3712 return 0; 3713 3714 irq_error: 3715 stmmac_free_irq(dev, irq_err, 0); 3716 return ret; 3717 } 3718 3719 static int stmmac_request_irq(struct net_device *dev) 3720 { 3721 struct stmmac_priv *priv = netdev_priv(dev); 3722 int ret; 3723 3724 /* Request the IRQ lines */ 3725 if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN) 3726 ret = stmmac_request_irq_multi_msi(dev); 3727 else 3728 ret = stmmac_request_irq_single(dev); 3729 3730 return ret; 3731 } 3732 3733 /** 3734 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3735 * @priv: driver private structure 3736 * @mtu: MTU to setup the dma queue and buf with 3737 * Description: Allocate and generate a dma_conf based on the provided MTU. 3738 * Allocate the Tx/Rx DMA queue and init them. 3739 * Return value: 3740 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3741 */ 3742 static struct stmmac_dma_conf * 3743 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3744 { 3745 struct stmmac_dma_conf *dma_conf; 3746 int chan, bfsize, ret; 3747 3748 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3749 if (!dma_conf) { 3750 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3751 __func__); 3752 return ERR_PTR(-ENOMEM); 3753 } 3754 3755 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3756 if (bfsize < 0) 3757 bfsize = 0; 3758 3759 if (bfsize < BUF_SIZE_16KiB) 3760 bfsize = stmmac_set_bfsize(mtu, 0); 3761 3762 dma_conf->dma_buf_sz = bfsize; 3763 /* Chose the tx/rx size from the already defined one in the 3764 * priv struct. (if defined) 3765 */ 3766 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3767 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3768 3769 if (!dma_conf->dma_tx_size) 3770 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3771 if (!dma_conf->dma_rx_size) 3772 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3773 3774 /* Earlier check for TBS */ 3775 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3776 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3777 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3778 3779 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3780 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3781 } 3782 3783 ret = alloc_dma_desc_resources(priv, dma_conf); 3784 if (ret < 0) { 3785 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3786 __func__); 3787 goto alloc_error; 3788 } 3789 3790 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3791 if (ret < 0) { 3792 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3793 __func__); 3794 goto init_error; 3795 } 3796 3797 return dma_conf; 3798 3799 init_error: 3800 free_dma_desc_resources(priv, dma_conf); 3801 alloc_error: 3802 kfree(dma_conf); 3803 return ERR_PTR(ret); 3804 } 3805 3806 /** 3807 * __stmmac_open - open entry point of the driver 3808 * @dev : pointer to the device structure. 3809 * @dma_conf : structure to take the dma data 3810 * Description: 3811 * This function is the open entry point of the driver. 3812 * Return value: 3813 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3814 * file on failure. 3815 */ 3816 static int __stmmac_open(struct net_device *dev, 3817 struct stmmac_dma_conf *dma_conf) 3818 { 3819 struct stmmac_priv *priv = netdev_priv(dev); 3820 int mode = priv->plat->phy_interface; 3821 u32 chan; 3822 int ret; 3823 3824 ret = pm_runtime_resume_and_get(priv->device); 3825 if (ret < 0) 3826 return ret; 3827 3828 if (priv->hw->pcs != STMMAC_PCS_TBI && 3829 priv->hw->pcs != STMMAC_PCS_RTBI && 3830 (!priv->hw->xpcs || 3831 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) && 3832 !priv->hw->lynx_pcs) { 3833 ret = stmmac_init_phy(dev); 3834 if (ret) { 3835 netdev_err(priv->dev, 3836 "%s: Cannot attach to PHY (error: %d)\n", 3837 __func__, ret); 3838 goto init_phy_error; 3839 } 3840 } 3841 3842 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3843 3844 buf_sz = dma_conf->dma_buf_sz; 3845 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3846 3847 stmmac_reset_queues_param(priv); 3848 3849 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 3850 priv->plat->serdes_powerup) { 3851 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3852 if (ret < 0) { 3853 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3854 __func__); 3855 goto init_error; 3856 } 3857 } 3858 3859 ret = stmmac_hw_setup(dev, true); 3860 if (ret < 0) { 3861 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3862 goto init_error; 3863 } 3864 3865 stmmac_init_coalesce(priv); 3866 3867 phylink_start(priv->phylink); 3868 /* We may have called phylink_speed_down before */ 3869 phylink_speed_up(priv->phylink); 3870 3871 ret = stmmac_request_irq(dev); 3872 if (ret) 3873 goto irq_error; 3874 3875 stmmac_enable_all_queues(priv); 3876 netif_tx_start_all_queues(priv->dev); 3877 stmmac_enable_all_dma_irq(priv); 3878 3879 return 0; 3880 3881 irq_error: 3882 phylink_stop(priv->phylink); 3883 3884 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3885 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3886 3887 stmmac_hw_teardown(dev); 3888 init_error: 3889 phylink_disconnect_phy(priv->phylink); 3890 init_phy_error: 3891 pm_runtime_put(priv->device); 3892 return ret; 3893 } 3894 3895 static int stmmac_open(struct net_device *dev) 3896 { 3897 struct stmmac_priv *priv = netdev_priv(dev); 3898 struct stmmac_dma_conf *dma_conf; 3899 int ret; 3900 3901 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3902 if (IS_ERR(dma_conf)) 3903 return PTR_ERR(dma_conf); 3904 3905 ret = __stmmac_open(dev, dma_conf); 3906 if (ret) 3907 free_dma_desc_resources(priv, dma_conf); 3908 3909 kfree(dma_conf); 3910 return ret; 3911 } 3912 3913 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3914 { 3915 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3916 3917 if (priv->fpe_wq) 3918 destroy_workqueue(priv->fpe_wq); 3919 3920 netdev_info(priv->dev, "FPE workqueue stop"); 3921 } 3922 3923 /** 3924 * stmmac_release - close entry point of the driver 3925 * @dev : device pointer. 3926 * Description: 3927 * This is the stop entry point of the driver. 3928 */ 3929 static int stmmac_release(struct net_device *dev) 3930 { 3931 struct stmmac_priv *priv = netdev_priv(dev); 3932 u32 chan; 3933 3934 if (device_may_wakeup(priv->device)) 3935 phylink_speed_down(priv->phylink, false); 3936 /* Stop and disconnect the PHY */ 3937 phylink_stop(priv->phylink); 3938 phylink_disconnect_phy(priv->phylink); 3939 3940 stmmac_disable_all_queues(priv); 3941 3942 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3943 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3944 3945 netif_tx_disable(dev); 3946 3947 /* Free the IRQ lines */ 3948 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3949 3950 if (priv->eee_enabled) { 3951 priv->tx_path_in_lpi_mode = false; 3952 del_timer_sync(&priv->eee_ctrl_timer); 3953 } 3954 3955 /* Stop TX/RX DMA and clear the descriptors */ 3956 stmmac_stop_all_dma(priv); 3957 3958 /* Release and free the Rx/Tx resources */ 3959 free_dma_desc_resources(priv, &priv->dma_conf); 3960 3961 /* Disable the MAC Rx/Tx */ 3962 stmmac_mac_set(priv, priv->ioaddr, false); 3963 3964 /* Powerdown Serdes if there is */ 3965 if (priv->plat->serdes_powerdown) 3966 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3967 3968 netif_carrier_off(dev); 3969 3970 stmmac_release_ptp(priv); 3971 3972 pm_runtime_put(priv->device); 3973 3974 if (priv->dma_cap.fpesel) 3975 stmmac_fpe_stop_wq(priv); 3976 3977 return 0; 3978 } 3979 3980 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3981 struct stmmac_tx_queue *tx_q) 3982 { 3983 u16 tag = 0x0, inner_tag = 0x0; 3984 u32 inner_type = 0x0; 3985 struct dma_desc *p; 3986 3987 if (!priv->dma_cap.vlins) 3988 return false; 3989 if (!skb_vlan_tag_present(skb)) 3990 return false; 3991 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3992 inner_tag = skb_vlan_tag_get(skb); 3993 inner_type = STMMAC_VLAN_INSERT; 3994 } 3995 3996 tag = skb_vlan_tag_get(skb); 3997 3998 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3999 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 4000 else 4001 p = &tx_q->dma_tx[tx_q->cur_tx]; 4002 4003 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 4004 return false; 4005 4006 stmmac_set_tx_owner(priv, p); 4007 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4008 return true; 4009 } 4010 4011 /** 4012 * stmmac_tso_allocator - close entry point of the driver 4013 * @priv: driver private structure 4014 * @des: buffer start address 4015 * @total_len: total length to fill in descriptors 4016 * @last_segment: condition for the last descriptor 4017 * @queue: TX queue index 4018 * Description: 4019 * This function fills descriptor and request new descriptors according to 4020 * buffer length to fill 4021 */ 4022 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 4023 int total_len, bool last_segment, u32 queue) 4024 { 4025 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4026 struct dma_desc *desc; 4027 u32 buff_size; 4028 int tmp_len; 4029 4030 tmp_len = total_len; 4031 4032 while (tmp_len > 0) { 4033 dma_addr_t curr_addr; 4034 4035 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4036 priv->dma_conf.dma_tx_size); 4037 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4038 4039 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4040 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4041 else 4042 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4043 4044 curr_addr = des + (total_len - tmp_len); 4045 if (priv->dma_cap.addr64 <= 32) 4046 desc->des0 = cpu_to_le32(curr_addr); 4047 else 4048 stmmac_set_desc_addr(priv, desc, curr_addr); 4049 4050 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4051 TSO_MAX_BUFF_SIZE : tmp_len; 4052 4053 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4054 0, 1, 4055 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4056 0, 0); 4057 4058 tmp_len -= TSO_MAX_BUFF_SIZE; 4059 } 4060 } 4061 4062 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4063 { 4064 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4065 int desc_size; 4066 4067 if (likely(priv->extend_desc)) 4068 desc_size = sizeof(struct dma_extended_desc); 4069 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4070 desc_size = sizeof(struct dma_edesc); 4071 else 4072 desc_size = sizeof(struct dma_desc); 4073 4074 /* The own bit must be the latest setting done when prepare the 4075 * descriptor and then barrier is needed to make sure that 4076 * all is coherent before granting the DMA engine. 4077 */ 4078 wmb(); 4079 4080 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4081 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4082 } 4083 4084 /** 4085 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4086 * @skb : the socket buffer 4087 * @dev : device pointer 4088 * Description: this is the transmit function that is called on TSO frames 4089 * (support available on GMAC4 and newer chips). 4090 * Diagram below show the ring programming in case of TSO frames: 4091 * 4092 * First Descriptor 4093 * -------- 4094 * | DES0 |---> buffer1 = L2/L3/L4 header 4095 * | DES1 |---> TCP Payload (can continue on next descr...) 4096 * | DES2 |---> buffer 1 and 2 len 4097 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4098 * -------- 4099 * | 4100 * ... 4101 * | 4102 * -------- 4103 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4104 * | DES1 | --| 4105 * | DES2 | --> buffer 1 and 2 len 4106 * | DES3 | 4107 * -------- 4108 * 4109 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4110 */ 4111 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4112 { 4113 struct dma_desc *desc, *first, *mss_desc = NULL; 4114 struct stmmac_priv *priv = netdev_priv(dev); 4115 int nfrags = skb_shinfo(skb)->nr_frags; 4116 u32 queue = skb_get_queue_mapping(skb); 4117 unsigned int first_entry, tx_packets; 4118 int tmp_pay_len = 0, first_tx; 4119 struct stmmac_tx_queue *tx_q; 4120 bool has_vlan, set_ic; 4121 u8 proto_hdr_len, hdr; 4122 unsigned long flags; 4123 u32 pay_len, mss; 4124 dma_addr_t des; 4125 int i; 4126 4127 tx_q = &priv->dma_conf.tx_queue[queue]; 4128 first_tx = tx_q->cur_tx; 4129 4130 /* Compute header lengths */ 4131 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4132 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4133 hdr = sizeof(struct udphdr); 4134 } else { 4135 proto_hdr_len = skb_tcp_all_headers(skb); 4136 hdr = tcp_hdrlen(skb); 4137 } 4138 4139 /* Desc availability based on threshold should be enough safe */ 4140 if (unlikely(stmmac_tx_avail(priv, queue) < 4141 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4142 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4143 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4144 queue)); 4145 /* This is a hard error, log it. */ 4146 netdev_err(priv->dev, 4147 "%s: Tx Ring full when queue awake\n", 4148 __func__); 4149 } 4150 return NETDEV_TX_BUSY; 4151 } 4152 4153 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4154 4155 mss = skb_shinfo(skb)->gso_size; 4156 4157 /* set new MSS value if needed */ 4158 if (mss != tx_q->mss) { 4159 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4160 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4161 else 4162 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4163 4164 stmmac_set_mss(priv, mss_desc, mss); 4165 tx_q->mss = mss; 4166 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4167 priv->dma_conf.dma_tx_size); 4168 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4169 } 4170 4171 if (netif_msg_tx_queued(priv)) { 4172 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4173 __func__, hdr, proto_hdr_len, pay_len, mss); 4174 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4175 skb->data_len); 4176 } 4177 4178 /* Check if VLAN can be inserted by HW */ 4179 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4180 4181 first_entry = tx_q->cur_tx; 4182 WARN_ON(tx_q->tx_skbuff[first_entry]); 4183 4184 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4185 desc = &tx_q->dma_entx[first_entry].basic; 4186 else 4187 desc = &tx_q->dma_tx[first_entry]; 4188 first = desc; 4189 4190 if (has_vlan) 4191 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4192 4193 /* first descriptor: fill Headers on Buf1 */ 4194 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4195 DMA_TO_DEVICE); 4196 if (dma_mapping_error(priv->device, des)) 4197 goto dma_map_err; 4198 4199 tx_q->tx_skbuff_dma[first_entry].buf = des; 4200 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4201 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4202 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4203 4204 if (priv->dma_cap.addr64 <= 32) { 4205 first->des0 = cpu_to_le32(des); 4206 4207 /* Fill start of payload in buff2 of first descriptor */ 4208 if (pay_len) 4209 first->des1 = cpu_to_le32(des + proto_hdr_len); 4210 4211 /* If needed take extra descriptors to fill the remaining payload */ 4212 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4213 } else { 4214 stmmac_set_desc_addr(priv, first, des); 4215 tmp_pay_len = pay_len; 4216 des += proto_hdr_len; 4217 pay_len = 0; 4218 } 4219 4220 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4221 4222 /* Prepare fragments */ 4223 for (i = 0; i < nfrags; i++) { 4224 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4225 4226 des = skb_frag_dma_map(priv->device, frag, 0, 4227 skb_frag_size(frag), 4228 DMA_TO_DEVICE); 4229 if (dma_mapping_error(priv->device, des)) 4230 goto dma_map_err; 4231 4232 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4233 (i == nfrags - 1), queue); 4234 4235 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4236 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4237 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4238 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4239 } 4240 4241 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4242 4243 /* Only the last descriptor gets to point to the skb. */ 4244 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4245 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4246 4247 /* Manage tx mitigation */ 4248 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4249 tx_q->tx_count_frames += tx_packets; 4250 4251 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4252 set_ic = true; 4253 else if (!priv->tx_coal_frames[queue]) 4254 set_ic = false; 4255 else if (tx_packets > priv->tx_coal_frames[queue]) 4256 set_ic = true; 4257 else if ((tx_q->tx_count_frames % 4258 priv->tx_coal_frames[queue]) < tx_packets) 4259 set_ic = true; 4260 else 4261 set_ic = false; 4262 4263 if (set_ic) { 4264 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4265 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4266 else 4267 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4268 4269 tx_q->tx_count_frames = 0; 4270 stmmac_set_tx_ic(priv, desc); 4271 } 4272 4273 /* We've used all descriptors we need for this skb, however, 4274 * advance cur_tx so that it references a fresh descriptor. 4275 * ndo_start_xmit will fill this descriptor the next time it's 4276 * called and stmmac_tx_clean may clean up to this descriptor. 4277 */ 4278 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4279 4280 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4281 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4282 __func__); 4283 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4284 } 4285 4286 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4287 tx_q->txq_stats.tx_bytes += skb->len; 4288 tx_q->txq_stats.tx_tso_frames++; 4289 tx_q->txq_stats.tx_tso_nfrags += nfrags; 4290 if (set_ic) 4291 tx_q->txq_stats.tx_set_ic_bit++; 4292 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4293 4294 if (priv->sarc_type) 4295 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4296 4297 skb_tx_timestamp(skb); 4298 4299 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4300 priv->hwts_tx_en)) { 4301 /* declare that device is doing timestamping */ 4302 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4303 stmmac_enable_tx_timestamp(priv, first); 4304 } 4305 4306 /* Complete the first descriptor before granting the DMA */ 4307 stmmac_prepare_tso_tx_desc(priv, first, 1, 4308 proto_hdr_len, 4309 pay_len, 4310 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4311 hdr / 4, (skb->len - proto_hdr_len)); 4312 4313 /* If context desc is used to change MSS */ 4314 if (mss_desc) { 4315 /* Make sure that first descriptor has been completely 4316 * written, including its own bit. This is because MSS is 4317 * actually before first descriptor, so we need to make 4318 * sure that MSS's own bit is the last thing written. 4319 */ 4320 dma_wmb(); 4321 stmmac_set_tx_owner(priv, mss_desc); 4322 } 4323 4324 if (netif_msg_pktdata(priv)) { 4325 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4326 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4327 tx_q->cur_tx, first, nfrags); 4328 pr_info(">>> frame to be transmitted: "); 4329 print_pkt(skb->data, skb_headlen(skb)); 4330 } 4331 4332 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4333 4334 stmmac_flush_tx_descriptors(priv, queue); 4335 stmmac_tx_timer_arm(priv, queue); 4336 4337 return NETDEV_TX_OK; 4338 4339 dma_map_err: 4340 dev_err(priv->device, "Tx dma map failed\n"); 4341 dev_kfree_skb(skb); 4342 priv->xstats.tx_dropped++; 4343 return NETDEV_TX_OK; 4344 } 4345 4346 /** 4347 * stmmac_xmit - Tx entry point of the driver 4348 * @skb : the socket buffer 4349 * @dev : device pointer 4350 * Description : this is the tx entry point of the driver. 4351 * It programs the chain or the ring and supports oversized frames 4352 * and SG feature. 4353 */ 4354 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4355 { 4356 unsigned int first_entry, tx_packets, enh_desc; 4357 struct stmmac_priv *priv = netdev_priv(dev); 4358 unsigned int nopaged_len = skb_headlen(skb); 4359 int i, csum_insertion = 0, is_jumbo = 0; 4360 u32 queue = skb_get_queue_mapping(skb); 4361 int nfrags = skb_shinfo(skb)->nr_frags; 4362 int gso = skb_shinfo(skb)->gso_type; 4363 struct dma_edesc *tbs_desc = NULL; 4364 struct dma_desc *desc, *first; 4365 struct stmmac_tx_queue *tx_q; 4366 bool has_vlan, set_ic; 4367 int entry, first_tx; 4368 unsigned long flags; 4369 dma_addr_t des; 4370 4371 tx_q = &priv->dma_conf.tx_queue[queue]; 4372 first_tx = tx_q->cur_tx; 4373 4374 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4375 stmmac_disable_eee_mode(priv); 4376 4377 /* Manage oversized TCP frames for GMAC4 device */ 4378 if (skb_is_gso(skb) && priv->tso) { 4379 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4380 return stmmac_tso_xmit(skb, dev); 4381 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4382 return stmmac_tso_xmit(skb, dev); 4383 } 4384 4385 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4386 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4387 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4388 queue)); 4389 /* This is a hard error, log it. */ 4390 netdev_err(priv->dev, 4391 "%s: Tx Ring full when queue awake\n", 4392 __func__); 4393 } 4394 return NETDEV_TX_BUSY; 4395 } 4396 4397 /* Check if VLAN can be inserted by HW */ 4398 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4399 4400 entry = tx_q->cur_tx; 4401 first_entry = entry; 4402 WARN_ON(tx_q->tx_skbuff[first_entry]); 4403 4404 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4405 4406 if (likely(priv->extend_desc)) 4407 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4408 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4409 desc = &tx_q->dma_entx[entry].basic; 4410 else 4411 desc = tx_q->dma_tx + entry; 4412 4413 first = desc; 4414 4415 if (has_vlan) 4416 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4417 4418 enh_desc = priv->plat->enh_desc; 4419 /* To program the descriptors according to the size of the frame */ 4420 if (enh_desc) 4421 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4422 4423 if (unlikely(is_jumbo)) { 4424 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4425 if (unlikely(entry < 0) && (entry != -EINVAL)) 4426 goto dma_map_err; 4427 } 4428 4429 for (i = 0; i < nfrags; i++) { 4430 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4431 int len = skb_frag_size(frag); 4432 bool last_segment = (i == (nfrags - 1)); 4433 4434 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4435 WARN_ON(tx_q->tx_skbuff[entry]); 4436 4437 if (likely(priv->extend_desc)) 4438 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4439 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4440 desc = &tx_q->dma_entx[entry].basic; 4441 else 4442 desc = tx_q->dma_tx + entry; 4443 4444 des = skb_frag_dma_map(priv->device, frag, 0, len, 4445 DMA_TO_DEVICE); 4446 if (dma_mapping_error(priv->device, des)) 4447 goto dma_map_err; /* should reuse desc w/o issues */ 4448 4449 tx_q->tx_skbuff_dma[entry].buf = des; 4450 4451 stmmac_set_desc_addr(priv, desc, des); 4452 4453 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4454 tx_q->tx_skbuff_dma[entry].len = len; 4455 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4456 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4457 4458 /* Prepare the descriptor and set the own bit too */ 4459 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4460 priv->mode, 1, last_segment, skb->len); 4461 } 4462 4463 /* Only the last descriptor gets to point to the skb. */ 4464 tx_q->tx_skbuff[entry] = skb; 4465 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4466 4467 /* According to the coalesce parameter the IC bit for the latest 4468 * segment is reset and the timer re-started to clean the tx status. 4469 * This approach takes care about the fragments: desc is the first 4470 * element in case of no SG. 4471 */ 4472 tx_packets = (entry + 1) - first_tx; 4473 tx_q->tx_count_frames += tx_packets; 4474 4475 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4476 set_ic = true; 4477 else if (!priv->tx_coal_frames[queue]) 4478 set_ic = false; 4479 else if (tx_packets > priv->tx_coal_frames[queue]) 4480 set_ic = true; 4481 else if ((tx_q->tx_count_frames % 4482 priv->tx_coal_frames[queue]) < tx_packets) 4483 set_ic = true; 4484 else 4485 set_ic = false; 4486 4487 if (set_ic) { 4488 if (likely(priv->extend_desc)) 4489 desc = &tx_q->dma_etx[entry].basic; 4490 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4491 desc = &tx_q->dma_entx[entry].basic; 4492 else 4493 desc = &tx_q->dma_tx[entry]; 4494 4495 tx_q->tx_count_frames = 0; 4496 stmmac_set_tx_ic(priv, desc); 4497 } 4498 4499 /* We've used all descriptors we need for this skb, however, 4500 * advance cur_tx so that it references a fresh descriptor. 4501 * ndo_start_xmit will fill this descriptor the next time it's 4502 * called and stmmac_tx_clean may clean up to this descriptor. 4503 */ 4504 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4505 tx_q->cur_tx = entry; 4506 4507 if (netif_msg_pktdata(priv)) { 4508 netdev_dbg(priv->dev, 4509 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4510 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4511 entry, first, nfrags); 4512 4513 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4514 print_pkt(skb->data, skb->len); 4515 } 4516 4517 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4518 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4519 __func__); 4520 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4521 } 4522 4523 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4524 tx_q->txq_stats.tx_bytes += skb->len; 4525 if (set_ic) 4526 tx_q->txq_stats.tx_set_ic_bit++; 4527 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4528 4529 if (priv->sarc_type) 4530 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4531 4532 skb_tx_timestamp(skb); 4533 4534 /* Ready to fill the first descriptor and set the OWN bit w/o any 4535 * problems because all the descriptors are actually ready to be 4536 * passed to the DMA engine. 4537 */ 4538 if (likely(!is_jumbo)) { 4539 bool last_segment = (nfrags == 0); 4540 4541 des = dma_map_single(priv->device, skb->data, 4542 nopaged_len, DMA_TO_DEVICE); 4543 if (dma_mapping_error(priv->device, des)) 4544 goto dma_map_err; 4545 4546 tx_q->tx_skbuff_dma[first_entry].buf = des; 4547 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4548 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4549 4550 stmmac_set_desc_addr(priv, first, des); 4551 4552 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4553 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4554 4555 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4556 priv->hwts_tx_en)) { 4557 /* declare that device is doing timestamping */ 4558 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4559 stmmac_enable_tx_timestamp(priv, first); 4560 } 4561 4562 /* Prepare the first descriptor setting the OWN bit too */ 4563 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4564 csum_insertion, priv->mode, 0, last_segment, 4565 skb->len); 4566 } 4567 4568 if (tx_q->tbs & STMMAC_TBS_EN) { 4569 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4570 4571 tbs_desc = &tx_q->dma_entx[first_entry]; 4572 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4573 } 4574 4575 stmmac_set_tx_owner(priv, first); 4576 4577 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4578 4579 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4580 4581 stmmac_flush_tx_descriptors(priv, queue); 4582 stmmac_tx_timer_arm(priv, queue); 4583 4584 return NETDEV_TX_OK; 4585 4586 dma_map_err: 4587 netdev_err(priv->dev, "Tx DMA map failed\n"); 4588 dev_kfree_skb(skb); 4589 priv->xstats.tx_dropped++; 4590 return NETDEV_TX_OK; 4591 } 4592 4593 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4594 { 4595 struct vlan_ethhdr *veth = skb_vlan_eth_hdr(skb); 4596 __be16 vlan_proto = veth->h_vlan_proto; 4597 u16 vlanid; 4598 4599 if ((vlan_proto == htons(ETH_P_8021Q) && 4600 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4601 (vlan_proto == htons(ETH_P_8021AD) && 4602 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4603 /* pop the vlan tag */ 4604 vlanid = ntohs(veth->h_vlan_TCI); 4605 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4606 skb_pull(skb, VLAN_HLEN); 4607 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4608 } 4609 } 4610 4611 /** 4612 * stmmac_rx_refill - refill used skb preallocated buffers 4613 * @priv: driver private structure 4614 * @queue: RX queue index 4615 * Description : this is to reallocate the skb for the reception process 4616 * that is based on zero-copy. 4617 */ 4618 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4619 { 4620 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4621 int dirty = stmmac_rx_dirty(priv, queue); 4622 unsigned int entry = rx_q->dirty_rx; 4623 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4624 4625 if (priv->dma_cap.host_dma_width <= 32) 4626 gfp |= GFP_DMA32; 4627 4628 while (dirty-- > 0) { 4629 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4630 struct dma_desc *p; 4631 bool use_rx_wd; 4632 4633 if (priv->extend_desc) 4634 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4635 else 4636 p = rx_q->dma_rx + entry; 4637 4638 if (!buf->page) { 4639 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4640 if (!buf->page) 4641 break; 4642 } 4643 4644 if (priv->sph && !buf->sec_page) { 4645 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4646 if (!buf->sec_page) 4647 break; 4648 4649 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4650 } 4651 4652 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4653 4654 stmmac_set_desc_addr(priv, p, buf->addr); 4655 if (priv->sph) 4656 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4657 else 4658 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4659 stmmac_refill_desc3(priv, rx_q, p); 4660 4661 rx_q->rx_count_frames++; 4662 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4663 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4664 rx_q->rx_count_frames = 0; 4665 4666 use_rx_wd = !priv->rx_coal_frames[queue]; 4667 use_rx_wd |= rx_q->rx_count_frames > 0; 4668 if (!priv->use_riwt) 4669 use_rx_wd = false; 4670 4671 dma_wmb(); 4672 stmmac_set_rx_owner(priv, p, use_rx_wd); 4673 4674 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4675 } 4676 rx_q->dirty_rx = entry; 4677 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4678 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4679 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4680 } 4681 4682 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4683 struct dma_desc *p, 4684 int status, unsigned int len) 4685 { 4686 unsigned int plen = 0, hlen = 0; 4687 int coe = priv->hw->rx_csum; 4688 4689 /* Not first descriptor, buffer is always zero */ 4690 if (priv->sph && len) 4691 return 0; 4692 4693 /* First descriptor, get split header length */ 4694 stmmac_get_rx_header_len(priv, p, &hlen); 4695 if (priv->sph && hlen) { 4696 priv->xstats.rx_split_hdr_pkt_n++; 4697 return hlen; 4698 } 4699 4700 /* First descriptor, not last descriptor and not split header */ 4701 if (status & rx_not_ls) 4702 return priv->dma_conf.dma_buf_sz; 4703 4704 plen = stmmac_get_rx_frame_len(priv, p, coe); 4705 4706 /* First descriptor and last descriptor and not split header */ 4707 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4708 } 4709 4710 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4711 struct dma_desc *p, 4712 int status, unsigned int len) 4713 { 4714 int coe = priv->hw->rx_csum; 4715 unsigned int plen = 0; 4716 4717 /* Not split header, buffer is not available */ 4718 if (!priv->sph) 4719 return 0; 4720 4721 /* Not last descriptor */ 4722 if (status & rx_not_ls) 4723 return priv->dma_conf.dma_buf_sz; 4724 4725 plen = stmmac_get_rx_frame_len(priv, p, coe); 4726 4727 /* Last descriptor */ 4728 return plen - len; 4729 } 4730 4731 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4732 struct xdp_frame *xdpf, bool dma_map) 4733 { 4734 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4735 unsigned int entry = tx_q->cur_tx; 4736 struct dma_desc *tx_desc; 4737 dma_addr_t dma_addr; 4738 bool set_ic; 4739 4740 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4741 return STMMAC_XDP_CONSUMED; 4742 4743 if (likely(priv->extend_desc)) 4744 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4745 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4746 tx_desc = &tx_q->dma_entx[entry].basic; 4747 else 4748 tx_desc = tx_q->dma_tx + entry; 4749 4750 if (dma_map) { 4751 dma_addr = dma_map_single(priv->device, xdpf->data, 4752 xdpf->len, DMA_TO_DEVICE); 4753 if (dma_mapping_error(priv->device, dma_addr)) 4754 return STMMAC_XDP_CONSUMED; 4755 4756 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4757 } else { 4758 struct page *page = virt_to_page(xdpf->data); 4759 4760 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4761 xdpf->headroom; 4762 dma_sync_single_for_device(priv->device, dma_addr, 4763 xdpf->len, DMA_BIDIRECTIONAL); 4764 4765 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4766 } 4767 4768 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4769 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4770 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4771 tx_q->tx_skbuff_dma[entry].last_segment = true; 4772 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4773 4774 tx_q->xdpf[entry] = xdpf; 4775 4776 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4777 4778 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4779 true, priv->mode, true, true, 4780 xdpf->len); 4781 4782 tx_q->tx_count_frames++; 4783 4784 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4785 set_ic = true; 4786 else 4787 set_ic = false; 4788 4789 if (set_ic) { 4790 unsigned long flags; 4791 tx_q->tx_count_frames = 0; 4792 stmmac_set_tx_ic(priv, tx_desc); 4793 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4794 tx_q->txq_stats.tx_set_ic_bit++; 4795 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4796 } 4797 4798 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4799 4800 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4801 tx_q->cur_tx = entry; 4802 4803 return STMMAC_XDP_TX; 4804 } 4805 4806 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4807 int cpu) 4808 { 4809 int index = cpu; 4810 4811 if (unlikely(index < 0)) 4812 index = 0; 4813 4814 while (index >= priv->plat->tx_queues_to_use) 4815 index -= priv->plat->tx_queues_to_use; 4816 4817 return index; 4818 } 4819 4820 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4821 struct xdp_buff *xdp) 4822 { 4823 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4824 int cpu = smp_processor_id(); 4825 struct netdev_queue *nq; 4826 int queue; 4827 int res; 4828 4829 if (unlikely(!xdpf)) 4830 return STMMAC_XDP_CONSUMED; 4831 4832 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4833 nq = netdev_get_tx_queue(priv->dev, queue); 4834 4835 __netif_tx_lock(nq, cpu); 4836 /* Avoids TX time-out as we are sharing with slow path */ 4837 txq_trans_cond_update(nq); 4838 4839 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4840 if (res == STMMAC_XDP_TX) 4841 stmmac_flush_tx_descriptors(priv, queue); 4842 4843 __netif_tx_unlock(nq); 4844 4845 return res; 4846 } 4847 4848 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4849 struct bpf_prog *prog, 4850 struct xdp_buff *xdp) 4851 { 4852 u32 act; 4853 int res; 4854 4855 act = bpf_prog_run_xdp(prog, xdp); 4856 switch (act) { 4857 case XDP_PASS: 4858 res = STMMAC_XDP_PASS; 4859 break; 4860 case XDP_TX: 4861 res = stmmac_xdp_xmit_back(priv, xdp); 4862 break; 4863 case XDP_REDIRECT: 4864 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4865 res = STMMAC_XDP_CONSUMED; 4866 else 4867 res = STMMAC_XDP_REDIRECT; 4868 break; 4869 default: 4870 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4871 fallthrough; 4872 case XDP_ABORTED: 4873 trace_xdp_exception(priv->dev, prog, act); 4874 fallthrough; 4875 case XDP_DROP: 4876 res = STMMAC_XDP_CONSUMED; 4877 break; 4878 } 4879 4880 return res; 4881 } 4882 4883 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4884 struct xdp_buff *xdp) 4885 { 4886 struct bpf_prog *prog; 4887 int res; 4888 4889 prog = READ_ONCE(priv->xdp_prog); 4890 if (!prog) { 4891 res = STMMAC_XDP_PASS; 4892 goto out; 4893 } 4894 4895 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4896 out: 4897 return ERR_PTR(-res); 4898 } 4899 4900 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4901 int xdp_status) 4902 { 4903 int cpu = smp_processor_id(); 4904 int queue; 4905 4906 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4907 4908 if (xdp_status & STMMAC_XDP_TX) 4909 stmmac_tx_timer_arm(priv, queue); 4910 4911 if (xdp_status & STMMAC_XDP_REDIRECT) 4912 xdp_do_flush(); 4913 } 4914 4915 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4916 struct xdp_buff *xdp) 4917 { 4918 unsigned int metasize = xdp->data - xdp->data_meta; 4919 unsigned int datasize = xdp->data_end - xdp->data; 4920 struct sk_buff *skb; 4921 4922 skb = __napi_alloc_skb(&ch->rxtx_napi, 4923 xdp->data_end - xdp->data_hard_start, 4924 GFP_ATOMIC | __GFP_NOWARN); 4925 if (unlikely(!skb)) 4926 return NULL; 4927 4928 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4929 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4930 if (metasize) 4931 skb_metadata_set(skb, metasize); 4932 4933 return skb; 4934 } 4935 4936 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4937 struct dma_desc *p, struct dma_desc *np, 4938 struct xdp_buff *xdp) 4939 { 4940 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4941 struct stmmac_channel *ch = &priv->channel[queue]; 4942 unsigned int len = xdp->data_end - xdp->data; 4943 enum pkt_hash_types hash_type; 4944 int coe = priv->hw->rx_csum; 4945 unsigned long flags; 4946 struct sk_buff *skb; 4947 u32 hash; 4948 4949 skb = stmmac_construct_skb_zc(ch, xdp); 4950 if (!skb) { 4951 priv->xstats.rx_dropped++; 4952 return; 4953 } 4954 4955 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4956 stmmac_rx_vlan(priv->dev, skb); 4957 skb->protocol = eth_type_trans(skb, priv->dev); 4958 4959 if (unlikely(!coe)) 4960 skb_checksum_none_assert(skb); 4961 else 4962 skb->ip_summed = CHECKSUM_UNNECESSARY; 4963 4964 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4965 skb_set_hash(skb, hash, hash_type); 4966 4967 skb_record_rx_queue(skb, queue); 4968 napi_gro_receive(&ch->rxtx_napi, skb); 4969 4970 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 4971 rx_q->rxq_stats.rx_pkt_n++; 4972 rx_q->rxq_stats.rx_bytes += len; 4973 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 4974 } 4975 4976 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4977 { 4978 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4979 unsigned int entry = rx_q->dirty_rx; 4980 struct dma_desc *rx_desc = NULL; 4981 bool ret = true; 4982 4983 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4984 4985 while (budget-- > 0 && entry != rx_q->cur_rx) { 4986 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4987 dma_addr_t dma_addr; 4988 bool use_rx_wd; 4989 4990 if (!buf->xdp) { 4991 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4992 if (!buf->xdp) { 4993 ret = false; 4994 break; 4995 } 4996 } 4997 4998 if (priv->extend_desc) 4999 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 5000 else 5001 rx_desc = rx_q->dma_rx + entry; 5002 5003 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 5004 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 5005 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 5006 stmmac_refill_desc3(priv, rx_q, rx_desc); 5007 5008 rx_q->rx_count_frames++; 5009 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 5010 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 5011 rx_q->rx_count_frames = 0; 5012 5013 use_rx_wd = !priv->rx_coal_frames[queue]; 5014 use_rx_wd |= rx_q->rx_count_frames > 0; 5015 if (!priv->use_riwt) 5016 use_rx_wd = false; 5017 5018 dma_wmb(); 5019 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 5020 5021 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 5022 } 5023 5024 if (rx_desc) { 5025 rx_q->dirty_rx = entry; 5026 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 5027 (rx_q->dirty_rx * sizeof(struct dma_desc)); 5028 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 5029 } 5030 5031 return ret; 5032 } 5033 5034 static struct stmmac_xdp_buff *xsk_buff_to_stmmac_ctx(struct xdp_buff *xdp) 5035 { 5036 /* In XDP zero copy data path, xdp field in struct xdp_buff_xsk is used 5037 * to represent incoming packet, whereas cb field in the same structure 5038 * is used to store driver specific info. Thus, struct stmmac_xdp_buff 5039 * is laid on top of xdp and cb fields of struct xdp_buff_xsk. 5040 */ 5041 return (struct stmmac_xdp_buff *)xdp; 5042 } 5043 5044 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 5045 { 5046 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5047 unsigned int count = 0, error = 0, len = 0; 5048 int dirty = stmmac_rx_dirty(priv, queue); 5049 unsigned int next_entry = rx_q->cur_rx; 5050 u32 rx_errors = 0, rx_dropped = 0; 5051 unsigned int desc_size; 5052 struct bpf_prog *prog; 5053 bool failure = false; 5054 unsigned long flags; 5055 int xdp_status = 0; 5056 int status = 0; 5057 5058 if (netif_msg_rx_status(priv)) { 5059 void *rx_head; 5060 5061 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5062 if (priv->extend_desc) { 5063 rx_head = (void *)rx_q->dma_erx; 5064 desc_size = sizeof(struct dma_extended_desc); 5065 } else { 5066 rx_head = (void *)rx_q->dma_rx; 5067 desc_size = sizeof(struct dma_desc); 5068 } 5069 5070 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5071 rx_q->dma_rx_phy, desc_size); 5072 } 5073 while (count < limit) { 5074 struct stmmac_rx_buffer *buf; 5075 struct stmmac_xdp_buff *ctx; 5076 unsigned int buf1_len = 0; 5077 struct dma_desc *np, *p; 5078 int entry; 5079 int res; 5080 5081 if (!count && rx_q->state_saved) { 5082 error = rx_q->state.error; 5083 len = rx_q->state.len; 5084 } else { 5085 rx_q->state_saved = false; 5086 error = 0; 5087 len = 0; 5088 } 5089 5090 if (count >= limit) 5091 break; 5092 5093 read_again: 5094 buf1_len = 0; 5095 entry = next_entry; 5096 buf = &rx_q->buf_pool[entry]; 5097 5098 if (dirty >= STMMAC_RX_FILL_BATCH) { 5099 failure = failure || 5100 !stmmac_rx_refill_zc(priv, queue, dirty); 5101 dirty = 0; 5102 } 5103 5104 if (priv->extend_desc) 5105 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5106 else 5107 p = rx_q->dma_rx + entry; 5108 5109 /* read the status of the incoming frame */ 5110 status = stmmac_rx_status(priv, &priv->xstats, p); 5111 /* check if managed by the DMA otherwise go ahead */ 5112 if (unlikely(status & dma_own)) 5113 break; 5114 5115 /* Prefetch the next RX descriptor */ 5116 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5117 priv->dma_conf.dma_rx_size); 5118 next_entry = rx_q->cur_rx; 5119 5120 if (priv->extend_desc) 5121 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5122 else 5123 np = rx_q->dma_rx + next_entry; 5124 5125 prefetch(np); 5126 5127 /* Ensure a valid XSK buffer before proceed */ 5128 if (!buf->xdp) 5129 break; 5130 5131 if (priv->extend_desc) 5132 stmmac_rx_extended_status(priv, &priv->xstats, 5133 rx_q->dma_erx + entry); 5134 if (unlikely(status == discard_frame)) { 5135 xsk_buff_free(buf->xdp); 5136 buf->xdp = NULL; 5137 dirty++; 5138 error = 1; 5139 if (!priv->hwts_rx_en) 5140 rx_errors++; 5141 } 5142 5143 if (unlikely(error && (status & rx_not_ls))) 5144 goto read_again; 5145 if (unlikely(error)) { 5146 count++; 5147 continue; 5148 } 5149 5150 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5151 if (likely(status & rx_not_ls)) { 5152 xsk_buff_free(buf->xdp); 5153 buf->xdp = NULL; 5154 dirty++; 5155 count++; 5156 goto read_again; 5157 } 5158 5159 ctx = xsk_buff_to_stmmac_ctx(buf->xdp); 5160 ctx->priv = priv; 5161 ctx->desc = p; 5162 ctx->ndesc = np; 5163 5164 /* XDP ZC Frame only support primary buffers for now */ 5165 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5166 len += buf1_len; 5167 5168 /* ACS is disabled; strip manually. */ 5169 if (likely(!(status & rx_not_ls))) { 5170 buf1_len -= ETH_FCS_LEN; 5171 len -= ETH_FCS_LEN; 5172 } 5173 5174 /* RX buffer is good and fit into a XSK pool buffer */ 5175 buf->xdp->data_end = buf->xdp->data + buf1_len; 5176 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5177 5178 prog = READ_ONCE(priv->xdp_prog); 5179 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5180 5181 switch (res) { 5182 case STMMAC_XDP_PASS: 5183 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5184 xsk_buff_free(buf->xdp); 5185 break; 5186 case STMMAC_XDP_CONSUMED: 5187 xsk_buff_free(buf->xdp); 5188 rx_dropped++; 5189 break; 5190 case STMMAC_XDP_TX: 5191 case STMMAC_XDP_REDIRECT: 5192 xdp_status |= res; 5193 break; 5194 } 5195 5196 buf->xdp = NULL; 5197 dirty++; 5198 count++; 5199 } 5200 5201 if (status & rx_not_ls) { 5202 rx_q->state_saved = true; 5203 rx_q->state.error = error; 5204 rx_q->state.len = len; 5205 } 5206 5207 stmmac_finalize_xdp_rx(priv, xdp_status); 5208 5209 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5210 rx_q->rxq_stats.rx_pkt_n += count; 5211 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5212 5213 priv->xstats.rx_dropped += rx_dropped; 5214 priv->xstats.rx_errors += rx_errors; 5215 5216 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5217 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5218 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5219 else 5220 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5221 5222 return (int)count; 5223 } 5224 5225 return failure ? limit : (int)count; 5226 } 5227 5228 /** 5229 * stmmac_rx - manage the receive process 5230 * @priv: driver private structure 5231 * @limit: napi bugget 5232 * @queue: RX queue index. 5233 * Description : this the function called by the napi poll method. 5234 * It gets all the frames inside the ring. 5235 */ 5236 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5237 { 5238 u32 rx_errors = 0, rx_dropped = 0, rx_bytes = 0, rx_packets = 0; 5239 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5240 struct stmmac_channel *ch = &priv->channel[queue]; 5241 unsigned int count = 0, error = 0, len = 0; 5242 int status = 0, coe = priv->hw->rx_csum; 5243 unsigned int next_entry = rx_q->cur_rx; 5244 enum dma_data_direction dma_dir; 5245 unsigned int desc_size; 5246 struct sk_buff *skb = NULL; 5247 struct stmmac_xdp_buff ctx; 5248 unsigned long flags; 5249 int xdp_status = 0; 5250 int buf_sz; 5251 5252 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5253 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5254 5255 if (netif_msg_rx_status(priv)) { 5256 void *rx_head; 5257 5258 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5259 if (priv->extend_desc) { 5260 rx_head = (void *)rx_q->dma_erx; 5261 desc_size = sizeof(struct dma_extended_desc); 5262 } else { 5263 rx_head = (void *)rx_q->dma_rx; 5264 desc_size = sizeof(struct dma_desc); 5265 } 5266 5267 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5268 rx_q->dma_rx_phy, desc_size); 5269 } 5270 while (count < limit) { 5271 unsigned int buf1_len = 0, buf2_len = 0; 5272 enum pkt_hash_types hash_type; 5273 struct stmmac_rx_buffer *buf; 5274 struct dma_desc *np, *p; 5275 int entry; 5276 u32 hash; 5277 5278 if (!count && rx_q->state_saved) { 5279 skb = rx_q->state.skb; 5280 error = rx_q->state.error; 5281 len = rx_q->state.len; 5282 } else { 5283 rx_q->state_saved = false; 5284 skb = NULL; 5285 error = 0; 5286 len = 0; 5287 } 5288 5289 if (count >= limit) 5290 break; 5291 5292 read_again: 5293 buf1_len = 0; 5294 buf2_len = 0; 5295 entry = next_entry; 5296 buf = &rx_q->buf_pool[entry]; 5297 5298 if (priv->extend_desc) 5299 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5300 else 5301 p = rx_q->dma_rx + entry; 5302 5303 /* read the status of the incoming frame */ 5304 status = stmmac_rx_status(priv, &priv->xstats, p); 5305 /* check if managed by the DMA otherwise go ahead */ 5306 if (unlikely(status & dma_own)) 5307 break; 5308 5309 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5310 priv->dma_conf.dma_rx_size); 5311 next_entry = rx_q->cur_rx; 5312 5313 if (priv->extend_desc) 5314 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5315 else 5316 np = rx_q->dma_rx + next_entry; 5317 5318 prefetch(np); 5319 5320 if (priv->extend_desc) 5321 stmmac_rx_extended_status(priv, &priv->xstats, rx_q->dma_erx + entry); 5322 if (unlikely(status == discard_frame)) { 5323 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5324 buf->page = NULL; 5325 error = 1; 5326 if (!priv->hwts_rx_en) 5327 rx_errors++; 5328 } 5329 5330 if (unlikely(error && (status & rx_not_ls))) 5331 goto read_again; 5332 if (unlikely(error)) { 5333 dev_kfree_skb(skb); 5334 skb = NULL; 5335 count++; 5336 continue; 5337 } 5338 5339 /* Buffer is good. Go on. */ 5340 5341 prefetch(page_address(buf->page) + buf->page_offset); 5342 if (buf->sec_page) 5343 prefetch(page_address(buf->sec_page)); 5344 5345 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5346 len += buf1_len; 5347 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5348 len += buf2_len; 5349 5350 /* ACS is disabled; strip manually. */ 5351 if (likely(!(status & rx_not_ls))) { 5352 if (buf2_len) { 5353 buf2_len -= ETH_FCS_LEN; 5354 len -= ETH_FCS_LEN; 5355 } else if (buf1_len) { 5356 buf1_len -= ETH_FCS_LEN; 5357 len -= ETH_FCS_LEN; 5358 } 5359 } 5360 5361 if (!skb) { 5362 unsigned int pre_len, sync_len; 5363 5364 dma_sync_single_for_cpu(priv->device, buf->addr, 5365 buf1_len, dma_dir); 5366 5367 xdp_init_buff(&ctx.xdp, buf_sz, &rx_q->xdp_rxq); 5368 xdp_prepare_buff(&ctx.xdp, page_address(buf->page), 5369 buf->page_offset, buf1_len, true); 5370 5371 pre_len = ctx.xdp.data_end - ctx.xdp.data_hard_start - 5372 buf->page_offset; 5373 5374 ctx.priv = priv; 5375 ctx.desc = p; 5376 ctx.ndesc = np; 5377 5378 skb = stmmac_xdp_run_prog(priv, &ctx.xdp); 5379 /* Due xdp_adjust_tail: DMA sync for_device 5380 * cover max len CPU touch 5381 */ 5382 sync_len = ctx.xdp.data_end - ctx.xdp.data_hard_start - 5383 buf->page_offset; 5384 sync_len = max(sync_len, pre_len); 5385 5386 /* For Not XDP_PASS verdict */ 5387 if (IS_ERR(skb)) { 5388 unsigned int xdp_res = -PTR_ERR(skb); 5389 5390 if (xdp_res & STMMAC_XDP_CONSUMED) { 5391 page_pool_put_page(rx_q->page_pool, 5392 virt_to_head_page(ctx.xdp.data), 5393 sync_len, true); 5394 buf->page = NULL; 5395 rx_dropped++; 5396 5397 /* Clear skb as it was set as 5398 * status by XDP program. 5399 */ 5400 skb = NULL; 5401 5402 if (unlikely((status & rx_not_ls))) 5403 goto read_again; 5404 5405 count++; 5406 continue; 5407 } else if (xdp_res & (STMMAC_XDP_TX | 5408 STMMAC_XDP_REDIRECT)) { 5409 xdp_status |= xdp_res; 5410 buf->page = NULL; 5411 skb = NULL; 5412 count++; 5413 continue; 5414 } 5415 } 5416 } 5417 5418 if (!skb) { 5419 /* XDP program may expand or reduce tail */ 5420 buf1_len = ctx.xdp.data_end - ctx.xdp.data; 5421 5422 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5423 if (!skb) { 5424 rx_dropped++; 5425 count++; 5426 goto drain_data; 5427 } 5428 5429 /* XDP program may adjust header */ 5430 skb_copy_to_linear_data(skb, ctx.xdp.data, buf1_len); 5431 skb_put(skb, buf1_len); 5432 5433 /* Data payload copied into SKB, page ready for recycle */ 5434 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5435 buf->page = NULL; 5436 } else if (buf1_len) { 5437 dma_sync_single_for_cpu(priv->device, buf->addr, 5438 buf1_len, dma_dir); 5439 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5440 buf->page, buf->page_offset, buf1_len, 5441 priv->dma_conf.dma_buf_sz); 5442 5443 /* Data payload appended into SKB */ 5444 skb_mark_for_recycle(skb); 5445 buf->page = NULL; 5446 } 5447 5448 if (buf2_len) { 5449 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5450 buf2_len, dma_dir); 5451 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5452 buf->sec_page, 0, buf2_len, 5453 priv->dma_conf.dma_buf_sz); 5454 5455 /* Data payload appended into SKB */ 5456 skb_mark_for_recycle(skb); 5457 buf->sec_page = NULL; 5458 } 5459 5460 drain_data: 5461 if (likely(status & rx_not_ls)) 5462 goto read_again; 5463 if (!skb) 5464 continue; 5465 5466 /* Got entire packet into SKB. Finish it. */ 5467 5468 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5469 stmmac_rx_vlan(priv->dev, skb); 5470 skb->protocol = eth_type_trans(skb, priv->dev); 5471 5472 if (unlikely(!coe)) 5473 skb_checksum_none_assert(skb); 5474 else 5475 skb->ip_summed = CHECKSUM_UNNECESSARY; 5476 5477 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5478 skb_set_hash(skb, hash, hash_type); 5479 5480 skb_record_rx_queue(skb, queue); 5481 napi_gro_receive(&ch->rx_napi, skb); 5482 skb = NULL; 5483 5484 rx_packets++; 5485 rx_bytes += len; 5486 count++; 5487 } 5488 5489 if (status & rx_not_ls || skb) { 5490 rx_q->state_saved = true; 5491 rx_q->state.skb = skb; 5492 rx_q->state.error = error; 5493 rx_q->state.len = len; 5494 } 5495 5496 stmmac_finalize_xdp_rx(priv, xdp_status); 5497 5498 stmmac_rx_refill(priv, queue); 5499 5500 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5501 rx_q->rxq_stats.rx_packets += rx_packets; 5502 rx_q->rxq_stats.rx_bytes += rx_bytes; 5503 rx_q->rxq_stats.rx_pkt_n += count; 5504 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5505 5506 priv->xstats.rx_dropped += rx_dropped; 5507 priv->xstats.rx_errors += rx_errors; 5508 5509 return count; 5510 } 5511 5512 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5513 { 5514 struct stmmac_channel *ch = 5515 container_of(napi, struct stmmac_channel, rx_napi); 5516 struct stmmac_priv *priv = ch->priv_data; 5517 struct stmmac_rx_queue *rx_q; 5518 u32 chan = ch->index; 5519 unsigned long flags; 5520 int work_done; 5521 5522 rx_q = &priv->dma_conf.rx_queue[chan]; 5523 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5524 rx_q->rxq_stats.napi_poll++; 5525 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5526 5527 work_done = stmmac_rx(priv, budget, chan); 5528 if (work_done < budget && napi_complete_done(napi, work_done)) { 5529 unsigned long flags; 5530 5531 spin_lock_irqsave(&ch->lock, flags); 5532 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5533 spin_unlock_irqrestore(&ch->lock, flags); 5534 } 5535 5536 return work_done; 5537 } 5538 5539 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5540 { 5541 struct stmmac_channel *ch = 5542 container_of(napi, struct stmmac_channel, tx_napi); 5543 struct stmmac_priv *priv = ch->priv_data; 5544 struct stmmac_tx_queue *tx_q; 5545 u32 chan = ch->index; 5546 unsigned long flags; 5547 int work_done; 5548 5549 tx_q = &priv->dma_conf.tx_queue[chan]; 5550 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 5551 tx_q->txq_stats.napi_poll++; 5552 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 5553 5554 work_done = stmmac_tx_clean(priv, budget, chan); 5555 work_done = min(work_done, budget); 5556 5557 if (work_done < budget && napi_complete_done(napi, work_done)) { 5558 unsigned long flags; 5559 5560 spin_lock_irqsave(&ch->lock, flags); 5561 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5562 spin_unlock_irqrestore(&ch->lock, flags); 5563 } 5564 5565 return work_done; 5566 } 5567 5568 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5569 { 5570 struct stmmac_channel *ch = 5571 container_of(napi, struct stmmac_channel, rxtx_napi); 5572 struct stmmac_priv *priv = ch->priv_data; 5573 int rx_done, tx_done, rxtx_done; 5574 struct stmmac_rx_queue *rx_q; 5575 struct stmmac_tx_queue *tx_q; 5576 u32 chan = ch->index; 5577 unsigned long flags; 5578 5579 rx_q = &priv->dma_conf.rx_queue[chan]; 5580 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5581 rx_q->rxq_stats.napi_poll++; 5582 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5583 5584 tx_q = &priv->dma_conf.tx_queue[chan]; 5585 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 5586 tx_q->txq_stats.napi_poll++; 5587 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 5588 5589 tx_done = stmmac_tx_clean(priv, budget, chan); 5590 tx_done = min(tx_done, budget); 5591 5592 rx_done = stmmac_rx_zc(priv, budget, chan); 5593 5594 rxtx_done = max(tx_done, rx_done); 5595 5596 /* If either TX or RX work is not complete, return budget 5597 * and keep pooling 5598 */ 5599 if (rxtx_done >= budget) 5600 return budget; 5601 5602 /* all work done, exit the polling mode */ 5603 if (napi_complete_done(napi, rxtx_done)) { 5604 unsigned long flags; 5605 5606 spin_lock_irqsave(&ch->lock, flags); 5607 /* Both RX and TX work done are compelte, 5608 * so enable both RX & TX IRQs. 5609 */ 5610 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5611 spin_unlock_irqrestore(&ch->lock, flags); 5612 } 5613 5614 return min(rxtx_done, budget - 1); 5615 } 5616 5617 /** 5618 * stmmac_tx_timeout 5619 * @dev : Pointer to net device structure 5620 * @txqueue: the index of the hanging transmit queue 5621 * Description: this function is called when a packet transmission fails to 5622 * complete within a reasonable time. The driver will mark the error in the 5623 * netdev structure and arrange for the device to be reset to a sane state 5624 * in order to transmit a new packet. 5625 */ 5626 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5627 { 5628 struct stmmac_priv *priv = netdev_priv(dev); 5629 5630 stmmac_global_err(priv); 5631 } 5632 5633 /** 5634 * stmmac_set_rx_mode - entry point for multicast addressing 5635 * @dev : pointer to the device structure 5636 * Description: 5637 * This function is a driver entry point which gets called by the kernel 5638 * whenever multicast addresses must be enabled/disabled. 5639 * Return value: 5640 * void. 5641 */ 5642 static void stmmac_set_rx_mode(struct net_device *dev) 5643 { 5644 struct stmmac_priv *priv = netdev_priv(dev); 5645 5646 stmmac_set_filter(priv, priv->hw, dev); 5647 } 5648 5649 /** 5650 * stmmac_change_mtu - entry point to change MTU size for the device. 5651 * @dev : device pointer. 5652 * @new_mtu : the new MTU size for the device. 5653 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5654 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5655 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5656 * Return value: 5657 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5658 * file on failure. 5659 */ 5660 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5661 { 5662 struct stmmac_priv *priv = netdev_priv(dev); 5663 int txfifosz = priv->plat->tx_fifo_size; 5664 struct stmmac_dma_conf *dma_conf; 5665 const int mtu = new_mtu; 5666 int ret; 5667 5668 if (txfifosz == 0) 5669 txfifosz = priv->dma_cap.tx_fifo_size; 5670 5671 txfifosz /= priv->plat->tx_queues_to_use; 5672 5673 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5674 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5675 return -EINVAL; 5676 } 5677 5678 new_mtu = STMMAC_ALIGN(new_mtu); 5679 5680 /* If condition true, FIFO is too small or MTU too large */ 5681 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5682 return -EINVAL; 5683 5684 if (netif_running(dev)) { 5685 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5686 /* Try to allocate the new DMA conf with the new mtu */ 5687 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5688 if (IS_ERR(dma_conf)) { 5689 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5690 mtu); 5691 return PTR_ERR(dma_conf); 5692 } 5693 5694 stmmac_release(dev); 5695 5696 ret = __stmmac_open(dev, dma_conf); 5697 if (ret) { 5698 free_dma_desc_resources(priv, dma_conf); 5699 kfree(dma_conf); 5700 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5701 return ret; 5702 } 5703 5704 kfree(dma_conf); 5705 5706 stmmac_set_rx_mode(dev); 5707 } 5708 5709 dev->mtu = mtu; 5710 netdev_update_features(dev); 5711 5712 return 0; 5713 } 5714 5715 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5716 netdev_features_t features) 5717 { 5718 struct stmmac_priv *priv = netdev_priv(dev); 5719 5720 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5721 features &= ~NETIF_F_RXCSUM; 5722 5723 if (!priv->plat->tx_coe) 5724 features &= ~NETIF_F_CSUM_MASK; 5725 5726 /* Some GMAC devices have a bugged Jumbo frame support that 5727 * needs to have the Tx COE disabled for oversized frames 5728 * (due to limited buffer sizes). In this case we disable 5729 * the TX csum insertion in the TDES and not use SF. 5730 */ 5731 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5732 features &= ~NETIF_F_CSUM_MASK; 5733 5734 /* Disable tso if asked by ethtool */ 5735 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) { 5736 if (features & NETIF_F_TSO) 5737 priv->tso = true; 5738 else 5739 priv->tso = false; 5740 } 5741 5742 return features; 5743 } 5744 5745 static int stmmac_set_features(struct net_device *netdev, 5746 netdev_features_t features) 5747 { 5748 struct stmmac_priv *priv = netdev_priv(netdev); 5749 5750 /* Keep the COE Type in case of csum is supporting */ 5751 if (features & NETIF_F_RXCSUM) 5752 priv->hw->rx_csum = priv->plat->rx_coe; 5753 else 5754 priv->hw->rx_csum = 0; 5755 /* No check needed because rx_coe has been set before and it will be 5756 * fixed in case of issue. 5757 */ 5758 stmmac_rx_ipc(priv, priv->hw); 5759 5760 if (priv->sph_cap) { 5761 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5762 u32 chan; 5763 5764 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5765 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5766 } 5767 5768 return 0; 5769 } 5770 5771 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5772 { 5773 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5774 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5775 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5776 bool *hs_enable = &fpe_cfg->hs_enable; 5777 5778 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5779 return; 5780 5781 /* If LP has sent verify mPacket, LP is FPE capable */ 5782 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5783 if (*lp_state < FPE_STATE_CAPABLE) 5784 *lp_state = FPE_STATE_CAPABLE; 5785 5786 /* If user has requested FPE enable, quickly response */ 5787 if (*hs_enable) 5788 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5789 MPACKET_RESPONSE); 5790 } 5791 5792 /* If Local has sent verify mPacket, Local is FPE capable */ 5793 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5794 if (*lo_state < FPE_STATE_CAPABLE) 5795 *lo_state = FPE_STATE_CAPABLE; 5796 } 5797 5798 /* If LP has sent response mPacket, LP is entering FPE ON */ 5799 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5800 *lp_state = FPE_STATE_ENTERING_ON; 5801 5802 /* If Local has sent response mPacket, Local is entering FPE ON */ 5803 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5804 *lo_state = FPE_STATE_ENTERING_ON; 5805 5806 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5807 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5808 priv->fpe_wq) { 5809 queue_work(priv->fpe_wq, &priv->fpe_task); 5810 } 5811 } 5812 5813 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5814 { 5815 u32 rx_cnt = priv->plat->rx_queues_to_use; 5816 u32 tx_cnt = priv->plat->tx_queues_to_use; 5817 u32 queues_count; 5818 u32 queue; 5819 bool xmac; 5820 5821 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5822 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5823 5824 if (priv->irq_wake) 5825 pm_wakeup_event(priv->device, 0); 5826 5827 if (priv->dma_cap.estsel) 5828 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5829 &priv->xstats, tx_cnt); 5830 5831 if (priv->dma_cap.fpesel) { 5832 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5833 priv->dev); 5834 5835 stmmac_fpe_event_status(priv, status); 5836 } 5837 5838 /* To handle GMAC own interrupts */ 5839 if ((priv->plat->has_gmac) || xmac) { 5840 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5841 5842 if (unlikely(status)) { 5843 /* For LPI we need to save the tx status */ 5844 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5845 priv->tx_path_in_lpi_mode = true; 5846 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5847 priv->tx_path_in_lpi_mode = false; 5848 } 5849 5850 for (queue = 0; queue < queues_count; queue++) { 5851 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5852 queue); 5853 } 5854 5855 /* PCS link status */ 5856 if (priv->hw->pcs && 5857 !(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS)) { 5858 if (priv->xstats.pcs_link) 5859 netif_carrier_on(priv->dev); 5860 else 5861 netif_carrier_off(priv->dev); 5862 } 5863 5864 stmmac_timestamp_interrupt(priv, priv); 5865 } 5866 } 5867 5868 /** 5869 * stmmac_interrupt - main ISR 5870 * @irq: interrupt number. 5871 * @dev_id: to pass the net device pointer. 5872 * Description: this is the main driver interrupt service routine. 5873 * It can call: 5874 * o DMA service routine (to manage incoming frame reception and transmission 5875 * status) 5876 * o Core interrupts to manage: remote wake-up, management counter, LPI 5877 * interrupts. 5878 */ 5879 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5880 { 5881 struct net_device *dev = (struct net_device *)dev_id; 5882 struct stmmac_priv *priv = netdev_priv(dev); 5883 5884 /* Check if adapter is up */ 5885 if (test_bit(STMMAC_DOWN, &priv->state)) 5886 return IRQ_HANDLED; 5887 5888 /* Check if a fatal error happened */ 5889 if (stmmac_safety_feat_interrupt(priv)) 5890 return IRQ_HANDLED; 5891 5892 /* To handle Common interrupts */ 5893 stmmac_common_interrupt(priv); 5894 5895 /* To handle DMA interrupts */ 5896 stmmac_dma_interrupt(priv); 5897 5898 return IRQ_HANDLED; 5899 } 5900 5901 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5902 { 5903 struct net_device *dev = (struct net_device *)dev_id; 5904 struct stmmac_priv *priv = netdev_priv(dev); 5905 5906 if (unlikely(!dev)) { 5907 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5908 return IRQ_NONE; 5909 } 5910 5911 /* Check if adapter is up */ 5912 if (test_bit(STMMAC_DOWN, &priv->state)) 5913 return IRQ_HANDLED; 5914 5915 /* To handle Common interrupts */ 5916 stmmac_common_interrupt(priv); 5917 5918 return IRQ_HANDLED; 5919 } 5920 5921 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5922 { 5923 struct net_device *dev = (struct net_device *)dev_id; 5924 struct stmmac_priv *priv = netdev_priv(dev); 5925 5926 if (unlikely(!dev)) { 5927 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5928 return IRQ_NONE; 5929 } 5930 5931 /* Check if adapter is up */ 5932 if (test_bit(STMMAC_DOWN, &priv->state)) 5933 return IRQ_HANDLED; 5934 5935 /* Check if a fatal error happened */ 5936 stmmac_safety_feat_interrupt(priv); 5937 5938 return IRQ_HANDLED; 5939 } 5940 5941 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5942 { 5943 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5944 struct stmmac_dma_conf *dma_conf; 5945 int chan = tx_q->queue_index; 5946 struct stmmac_priv *priv; 5947 int status; 5948 5949 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5950 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5951 5952 if (unlikely(!data)) { 5953 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5954 return IRQ_NONE; 5955 } 5956 5957 /* Check if adapter is up */ 5958 if (test_bit(STMMAC_DOWN, &priv->state)) 5959 return IRQ_HANDLED; 5960 5961 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5962 5963 if (unlikely(status & tx_hard_error_bump_tc)) { 5964 /* Try to bump up the dma threshold on this failure */ 5965 stmmac_bump_dma_threshold(priv, chan); 5966 } else if (unlikely(status == tx_hard_error)) { 5967 stmmac_tx_err(priv, chan); 5968 } 5969 5970 return IRQ_HANDLED; 5971 } 5972 5973 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5974 { 5975 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5976 struct stmmac_dma_conf *dma_conf; 5977 int chan = rx_q->queue_index; 5978 struct stmmac_priv *priv; 5979 5980 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5981 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5982 5983 if (unlikely(!data)) { 5984 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5985 return IRQ_NONE; 5986 } 5987 5988 /* Check if adapter is up */ 5989 if (test_bit(STMMAC_DOWN, &priv->state)) 5990 return IRQ_HANDLED; 5991 5992 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5993 5994 return IRQ_HANDLED; 5995 } 5996 5997 #ifdef CONFIG_NET_POLL_CONTROLLER 5998 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5999 * to allow network I/O with interrupts disabled. 6000 */ 6001 static void stmmac_poll_controller(struct net_device *dev) 6002 { 6003 struct stmmac_priv *priv = netdev_priv(dev); 6004 int i; 6005 6006 /* If adapter is down, do nothing */ 6007 if (test_bit(STMMAC_DOWN, &priv->state)) 6008 return; 6009 6010 if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN) { 6011 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 6012 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 6013 6014 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 6015 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 6016 } else { 6017 disable_irq(dev->irq); 6018 stmmac_interrupt(dev->irq, dev); 6019 enable_irq(dev->irq); 6020 } 6021 } 6022 #endif 6023 6024 /** 6025 * stmmac_ioctl - Entry point for the Ioctl 6026 * @dev: Device pointer. 6027 * @rq: An IOCTL specefic structure, that can contain a pointer to 6028 * a proprietary structure used to pass information to the driver. 6029 * @cmd: IOCTL command 6030 * Description: 6031 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 6032 */ 6033 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 6034 { 6035 struct stmmac_priv *priv = netdev_priv (dev); 6036 int ret = -EOPNOTSUPP; 6037 6038 if (!netif_running(dev)) 6039 return -EINVAL; 6040 6041 switch (cmd) { 6042 case SIOCGMIIPHY: 6043 case SIOCGMIIREG: 6044 case SIOCSMIIREG: 6045 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 6046 break; 6047 case SIOCSHWTSTAMP: 6048 ret = stmmac_hwtstamp_set(dev, rq); 6049 break; 6050 case SIOCGHWTSTAMP: 6051 ret = stmmac_hwtstamp_get(dev, rq); 6052 break; 6053 default: 6054 break; 6055 } 6056 6057 return ret; 6058 } 6059 6060 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 6061 void *cb_priv) 6062 { 6063 struct stmmac_priv *priv = cb_priv; 6064 int ret = -EOPNOTSUPP; 6065 6066 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 6067 return ret; 6068 6069 __stmmac_disable_all_queues(priv); 6070 6071 switch (type) { 6072 case TC_SETUP_CLSU32: 6073 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 6074 break; 6075 case TC_SETUP_CLSFLOWER: 6076 ret = stmmac_tc_setup_cls(priv, priv, type_data); 6077 break; 6078 default: 6079 break; 6080 } 6081 6082 stmmac_enable_all_queues(priv); 6083 return ret; 6084 } 6085 6086 static LIST_HEAD(stmmac_block_cb_list); 6087 6088 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 6089 void *type_data) 6090 { 6091 struct stmmac_priv *priv = netdev_priv(ndev); 6092 6093 switch (type) { 6094 case TC_QUERY_CAPS: 6095 return stmmac_tc_query_caps(priv, priv, type_data); 6096 case TC_SETUP_BLOCK: 6097 return flow_block_cb_setup_simple(type_data, 6098 &stmmac_block_cb_list, 6099 stmmac_setup_tc_block_cb, 6100 priv, priv, true); 6101 case TC_SETUP_QDISC_CBS: 6102 return stmmac_tc_setup_cbs(priv, priv, type_data); 6103 case TC_SETUP_QDISC_TAPRIO: 6104 return stmmac_tc_setup_taprio(priv, priv, type_data); 6105 case TC_SETUP_QDISC_ETF: 6106 return stmmac_tc_setup_etf(priv, priv, type_data); 6107 default: 6108 return -EOPNOTSUPP; 6109 } 6110 } 6111 6112 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6113 struct net_device *sb_dev) 6114 { 6115 int gso = skb_shinfo(skb)->gso_type; 6116 6117 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6118 /* 6119 * There is no way to determine the number of TSO/USO 6120 * capable Queues. Let's use always the Queue 0 6121 * because if TSO/USO is supported then at least this 6122 * one will be capable. 6123 */ 6124 return 0; 6125 } 6126 6127 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6128 } 6129 6130 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6131 { 6132 struct stmmac_priv *priv = netdev_priv(ndev); 6133 int ret = 0; 6134 6135 ret = pm_runtime_resume_and_get(priv->device); 6136 if (ret < 0) 6137 return ret; 6138 6139 ret = eth_mac_addr(ndev, addr); 6140 if (ret) 6141 goto set_mac_error; 6142 6143 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6144 6145 set_mac_error: 6146 pm_runtime_put(priv->device); 6147 6148 return ret; 6149 } 6150 6151 #ifdef CONFIG_DEBUG_FS 6152 static struct dentry *stmmac_fs_dir; 6153 6154 static void sysfs_display_ring(void *head, int size, int extend_desc, 6155 struct seq_file *seq, dma_addr_t dma_phy_addr) 6156 { 6157 int i; 6158 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6159 struct dma_desc *p = (struct dma_desc *)head; 6160 dma_addr_t dma_addr; 6161 6162 for (i = 0; i < size; i++) { 6163 if (extend_desc) { 6164 dma_addr = dma_phy_addr + i * sizeof(*ep); 6165 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6166 i, &dma_addr, 6167 le32_to_cpu(ep->basic.des0), 6168 le32_to_cpu(ep->basic.des1), 6169 le32_to_cpu(ep->basic.des2), 6170 le32_to_cpu(ep->basic.des3)); 6171 ep++; 6172 } else { 6173 dma_addr = dma_phy_addr + i * sizeof(*p); 6174 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6175 i, &dma_addr, 6176 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6177 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6178 p++; 6179 } 6180 seq_printf(seq, "\n"); 6181 } 6182 } 6183 6184 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6185 { 6186 struct net_device *dev = seq->private; 6187 struct stmmac_priv *priv = netdev_priv(dev); 6188 u32 rx_count = priv->plat->rx_queues_to_use; 6189 u32 tx_count = priv->plat->tx_queues_to_use; 6190 u32 queue; 6191 6192 if ((dev->flags & IFF_UP) == 0) 6193 return 0; 6194 6195 for (queue = 0; queue < rx_count; queue++) { 6196 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6197 6198 seq_printf(seq, "RX Queue %d:\n", queue); 6199 6200 if (priv->extend_desc) { 6201 seq_printf(seq, "Extended descriptor ring:\n"); 6202 sysfs_display_ring((void *)rx_q->dma_erx, 6203 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6204 } else { 6205 seq_printf(seq, "Descriptor ring:\n"); 6206 sysfs_display_ring((void *)rx_q->dma_rx, 6207 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6208 } 6209 } 6210 6211 for (queue = 0; queue < tx_count; queue++) { 6212 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6213 6214 seq_printf(seq, "TX Queue %d:\n", queue); 6215 6216 if (priv->extend_desc) { 6217 seq_printf(seq, "Extended descriptor ring:\n"); 6218 sysfs_display_ring((void *)tx_q->dma_etx, 6219 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6220 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6221 seq_printf(seq, "Descriptor ring:\n"); 6222 sysfs_display_ring((void *)tx_q->dma_tx, 6223 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6224 } 6225 } 6226 6227 return 0; 6228 } 6229 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6230 6231 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6232 { 6233 struct net_device *dev = seq->private; 6234 struct stmmac_priv *priv = netdev_priv(dev); 6235 6236 if (!priv->hw_cap_support) { 6237 seq_printf(seq, "DMA HW features not supported\n"); 6238 return 0; 6239 } 6240 6241 seq_printf(seq, "==============================\n"); 6242 seq_printf(seq, "\tDMA HW features\n"); 6243 seq_printf(seq, "==============================\n"); 6244 6245 seq_printf(seq, "\t10/100 Mbps: %s\n", 6246 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6247 seq_printf(seq, "\t1000 Mbps: %s\n", 6248 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6249 seq_printf(seq, "\tHalf duplex: %s\n", 6250 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6251 seq_printf(seq, "\tHash Filter: %s\n", 6252 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6253 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6254 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6255 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6256 (priv->dma_cap.pcs) ? "Y" : "N"); 6257 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6258 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6259 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6260 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6261 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6262 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6263 seq_printf(seq, "\tRMON module: %s\n", 6264 (priv->dma_cap.rmon) ? "Y" : "N"); 6265 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6266 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6267 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6268 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6269 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6270 (priv->dma_cap.eee) ? "Y" : "N"); 6271 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6272 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6273 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6274 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6275 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6276 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6277 } else { 6278 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6279 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6280 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6281 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6282 } 6283 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6284 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6285 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6286 priv->dma_cap.number_rx_channel); 6287 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6288 priv->dma_cap.number_tx_channel); 6289 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6290 priv->dma_cap.number_rx_queues); 6291 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6292 priv->dma_cap.number_tx_queues); 6293 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6294 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6295 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6296 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6297 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6298 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6299 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6300 priv->dma_cap.pps_out_num); 6301 seq_printf(seq, "\tSafety Features: %s\n", 6302 priv->dma_cap.asp ? "Y" : "N"); 6303 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6304 priv->dma_cap.frpsel ? "Y" : "N"); 6305 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6306 priv->dma_cap.host_dma_width); 6307 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6308 priv->dma_cap.rssen ? "Y" : "N"); 6309 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6310 priv->dma_cap.vlhash ? "Y" : "N"); 6311 seq_printf(seq, "\tSplit Header: %s\n", 6312 priv->dma_cap.sphen ? "Y" : "N"); 6313 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6314 priv->dma_cap.vlins ? "Y" : "N"); 6315 seq_printf(seq, "\tDouble VLAN: %s\n", 6316 priv->dma_cap.dvlan ? "Y" : "N"); 6317 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6318 priv->dma_cap.l3l4fnum); 6319 seq_printf(seq, "\tARP Offloading: %s\n", 6320 priv->dma_cap.arpoffsel ? "Y" : "N"); 6321 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6322 priv->dma_cap.estsel ? "Y" : "N"); 6323 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6324 priv->dma_cap.fpesel ? "Y" : "N"); 6325 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6326 priv->dma_cap.tbssel ? "Y" : "N"); 6327 return 0; 6328 } 6329 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6330 6331 /* Use network device events to rename debugfs file entries. 6332 */ 6333 static int stmmac_device_event(struct notifier_block *unused, 6334 unsigned long event, void *ptr) 6335 { 6336 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6337 struct stmmac_priv *priv = netdev_priv(dev); 6338 6339 if (dev->netdev_ops != &stmmac_netdev_ops) 6340 goto done; 6341 6342 switch (event) { 6343 case NETDEV_CHANGENAME: 6344 if (priv->dbgfs_dir) 6345 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6346 priv->dbgfs_dir, 6347 stmmac_fs_dir, 6348 dev->name); 6349 break; 6350 } 6351 done: 6352 return NOTIFY_DONE; 6353 } 6354 6355 static struct notifier_block stmmac_notifier = { 6356 .notifier_call = stmmac_device_event, 6357 }; 6358 6359 static void stmmac_init_fs(struct net_device *dev) 6360 { 6361 struct stmmac_priv *priv = netdev_priv(dev); 6362 6363 rtnl_lock(); 6364 6365 /* Create per netdev entries */ 6366 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6367 6368 /* Entry to report DMA RX/TX rings */ 6369 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6370 &stmmac_rings_status_fops); 6371 6372 /* Entry to report the DMA HW features */ 6373 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6374 &stmmac_dma_cap_fops); 6375 6376 rtnl_unlock(); 6377 } 6378 6379 static void stmmac_exit_fs(struct net_device *dev) 6380 { 6381 struct stmmac_priv *priv = netdev_priv(dev); 6382 6383 debugfs_remove_recursive(priv->dbgfs_dir); 6384 } 6385 #endif /* CONFIG_DEBUG_FS */ 6386 6387 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6388 { 6389 unsigned char *data = (unsigned char *)&vid_le; 6390 unsigned char data_byte = 0; 6391 u32 crc = ~0x0; 6392 u32 temp = 0; 6393 int i, bits; 6394 6395 bits = get_bitmask_order(VLAN_VID_MASK); 6396 for (i = 0; i < bits; i++) { 6397 if ((i % 8) == 0) 6398 data_byte = data[i / 8]; 6399 6400 temp = ((crc & 1) ^ data_byte) & 1; 6401 crc >>= 1; 6402 data_byte >>= 1; 6403 6404 if (temp) 6405 crc ^= 0xedb88320; 6406 } 6407 6408 return crc; 6409 } 6410 6411 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6412 { 6413 u32 crc, hash = 0; 6414 __le16 pmatch = 0; 6415 int count = 0; 6416 u16 vid = 0; 6417 6418 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6419 __le16 vid_le = cpu_to_le16(vid); 6420 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6421 hash |= (1 << crc); 6422 count++; 6423 } 6424 6425 if (!priv->dma_cap.vlhash) { 6426 if (count > 2) /* VID = 0 always passes filter */ 6427 return -EOPNOTSUPP; 6428 6429 pmatch = cpu_to_le16(vid); 6430 hash = 0; 6431 } 6432 6433 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6434 } 6435 6436 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6437 { 6438 struct stmmac_priv *priv = netdev_priv(ndev); 6439 bool is_double = false; 6440 int ret; 6441 6442 ret = pm_runtime_resume_and_get(priv->device); 6443 if (ret < 0) 6444 return ret; 6445 6446 if (be16_to_cpu(proto) == ETH_P_8021AD) 6447 is_double = true; 6448 6449 set_bit(vid, priv->active_vlans); 6450 ret = stmmac_vlan_update(priv, is_double); 6451 if (ret) { 6452 clear_bit(vid, priv->active_vlans); 6453 goto err_pm_put; 6454 } 6455 6456 if (priv->hw->num_vlan) { 6457 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6458 if (ret) 6459 goto err_pm_put; 6460 } 6461 err_pm_put: 6462 pm_runtime_put(priv->device); 6463 6464 return ret; 6465 } 6466 6467 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6468 { 6469 struct stmmac_priv *priv = netdev_priv(ndev); 6470 bool is_double = false; 6471 int ret; 6472 6473 ret = pm_runtime_resume_and_get(priv->device); 6474 if (ret < 0) 6475 return ret; 6476 6477 if (be16_to_cpu(proto) == ETH_P_8021AD) 6478 is_double = true; 6479 6480 clear_bit(vid, priv->active_vlans); 6481 6482 if (priv->hw->num_vlan) { 6483 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6484 if (ret) 6485 goto del_vlan_error; 6486 } 6487 6488 ret = stmmac_vlan_update(priv, is_double); 6489 6490 del_vlan_error: 6491 pm_runtime_put(priv->device); 6492 6493 return ret; 6494 } 6495 6496 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6497 { 6498 struct stmmac_priv *priv = netdev_priv(dev); 6499 6500 switch (bpf->command) { 6501 case XDP_SETUP_PROG: 6502 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6503 case XDP_SETUP_XSK_POOL: 6504 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6505 bpf->xsk.queue_id); 6506 default: 6507 return -EOPNOTSUPP; 6508 } 6509 } 6510 6511 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6512 struct xdp_frame **frames, u32 flags) 6513 { 6514 struct stmmac_priv *priv = netdev_priv(dev); 6515 int cpu = smp_processor_id(); 6516 struct netdev_queue *nq; 6517 int i, nxmit = 0; 6518 int queue; 6519 6520 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6521 return -ENETDOWN; 6522 6523 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6524 return -EINVAL; 6525 6526 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6527 nq = netdev_get_tx_queue(priv->dev, queue); 6528 6529 __netif_tx_lock(nq, cpu); 6530 /* Avoids TX time-out as we are sharing with slow path */ 6531 txq_trans_cond_update(nq); 6532 6533 for (i = 0; i < num_frames; i++) { 6534 int res; 6535 6536 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6537 if (res == STMMAC_XDP_CONSUMED) 6538 break; 6539 6540 nxmit++; 6541 } 6542 6543 if (flags & XDP_XMIT_FLUSH) { 6544 stmmac_flush_tx_descriptors(priv, queue); 6545 stmmac_tx_timer_arm(priv, queue); 6546 } 6547 6548 __netif_tx_unlock(nq); 6549 6550 return nxmit; 6551 } 6552 6553 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6554 { 6555 struct stmmac_channel *ch = &priv->channel[queue]; 6556 unsigned long flags; 6557 6558 spin_lock_irqsave(&ch->lock, flags); 6559 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6560 spin_unlock_irqrestore(&ch->lock, flags); 6561 6562 stmmac_stop_rx_dma(priv, queue); 6563 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6564 } 6565 6566 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6567 { 6568 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6569 struct stmmac_channel *ch = &priv->channel[queue]; 6570 unsigned long flags; 6571 u32 buf_size; 6572 int ret; 6573 6574 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6575 if (ret) { 6576 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6577 return; 6578 } 6579 6580 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6581 if (ret) { 6582 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6583 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6584 return; 6585 } 6586 6587 stmmac_reset_rx_queue(priv, queue); 6588 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6589 6590 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6591 rx_q->dma_rx_phy, rx_q->queue_index); 6592 6593 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6594 sizeof(struct dma_desc)); 6595 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6596 rx_q->rx_tail_addr, rx_q->queue_index); 6597 6598 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6599 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6600 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6601 buf_size, 6602 rx_q->queue_index); 6603 } else { 6604 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6605 priv->dma_conf.dma_buf_sz, 6606 rx_q->queue_index); 6607 } 6608 6609 stmmac_start_rx_dma(priv, queue); 6610 6611 spin_lock_irqsave(&ch->lock, flags); 6612 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6613 spin_unlock_irqrestore(&ch->lock, flags); 6614 } 6615 6616 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6617 { 6618 struct stmmac_channel *ch = &priv->channel[queue]; 6619 unsigned long flags; 6620 6621 spin_lock_irqsave(&ch->lock, flags); 6622 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6623 spin_unlock_irqrestore(&ch->lock, flags); 6624 6625 stmmac_stop_tx_dma(priv, queue); 6626 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6627 } 6628 6629 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6630 { 6631 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6632 struct stmmac_channel *ch = &priv->channel[queue]; 6633 unsigned long flags; 6634 int ret; 6635 6636 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6637 if (ret) { 6638 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6639 return; 6640 } 6641 6642 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6643 if (ret) { 6644 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6645 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6646 return; 6647 } 6648 6649 stmmac_reset_tx_queue(priv, queue); 6650 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6651 6652 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6653 tx_q->dma_tx_phy, tx_q->queue_index); 6654 6655 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6656 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6657 6658 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6659 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6660 tx_q->tx_tail_addr, tx_q->queue_index); 6661 6662 stmmac_start_tx_dma(priv, queue); 6663 6664 spin_lock_irqsave(&ch->lock, flags); 6665 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6666 spin_unlock_irqrestore(&ch->lock, flags); 6667 } 6668 6669 void stmmac_xdp_release(struct net_device *dev) 6670 { 6671 struct stmmac_priv *priv = netdev_priv(dev); 6672 u32 chan; 6673 6674 /* Ensure tx function is not running */ 6675 netif_tx_disable(dev); 6676 6677 /* Disable NAPI process */ 6678 stmmac_disable_all_queues(priv); 6679 6680 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6681 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6682 6683 /* Free the IRQ lines */ 6684 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6685 6686 /* Stop TX/RX DMA channels */ 6687 stmmac_stop_all_dma(priv); 6688 6689 /* Release and free the Rx/Tx resources */ 6690 free_dma_desc_resources(priv, &priv->dma_conf); 6691 6692 /* Disable the MAC Rx/Tx */ 6693 stmmac_mac_set(priv, priv->ioaddr, false); 6694 6695 /* set trans_start so we don't get spurious 6696 * watchdogs during reset 6697 */ 6698 netif_trans_update(dev); 6699 netif_carrier_off(dev); 6700 } 6701 6702 int stmmac_xdp_open(struct net_device *dev) 6703 { 6704 struct stmmac_priv *priv = netdev_priv(dev); 6705 u32 rx_cnt = priv->plat->rx_queues_to_use; 6706 u32 tx_cnt = priv->plat->tx_queues_to_use; 6707 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6708 struct stmmac_rx_queue *rx_q; 6709 struct stmmac_tx_queue *tx_q; 6710 u32 buf_size; 6711 bool sph_en; 6712 u32 chan; 6713 int ret; 6714 6715 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6716 if (ret < 0) { 6717 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6718 __func__); 6719 goto dma_desc_error; 6720 } 6721 6722 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6723 if (ret < 0) { 6724 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6725 __func__); 6726 goto init_error; 6727 } 6728 6729 stmmac_reset_queues_param(priv); 6730 6731 /* DMA CSR Channel configuration */ 6732 for (chan = 0; chan < dma_csr_ch; chan++) { 6733 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6734 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6735 } 6736 6737 /* Adjust Split header */ 6738 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6739 6740 /* DMA RX Channel Configuration */ 6741 for (chan = 0; chan < rx_cnt; chan++) { 6742 rx_q = &priv->dma_conf.rx_queue[chan]; 6743 6744 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6745 rx_q->dma_rx_phy, chan); 6746 6747 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6748 (rx_q->buf_alloc_num * 6749 sizeof(struct dma_desc)); 6750 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6751 rx_q->rx_tail_addr, chan); 6752 6753 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6754 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6755 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6756 buf_size, 6757 rx_q->queue_index); 6758 } else { 6759 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6760 priv->dma_conf.dma_buf_sz, 6761 rx_q->queue_index); 6762 } 6763 6764 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6765 } 6766 6767 /* DMA TX Channel Configuration */ 6768 for (chan = 0; chan < tx_cnt; chan++) { 6769 tx_q = &priv->dma_conf.tx_queue[chan]; 6770 6771 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6772 tx_q->dma_tx_phy, chan); 6773 6774 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6775 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6776 tx_q->tx_tail_addr, chan); 6777 6778 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6779 tx_q->txtimer.function = stmmac_tx_timer; 6780 } 6781 6782 /* Enable the MAC Rx/Tx */ 6783 stmmac_mac_set(priv, priv->ioaddr, true); 6784 6785 /* Start Rx & Tx DMA Channels */ 6786 stmmac_start_all_dma(priv); 6787 6788 ret = stmmac_request_irq(dev); 6789 if (ret) 6790 goto irq_error; 6791 6792 /* Enable NAPI process*/ 6793 stmmac_enable_all_queues(priv); 6794 netif_carrier_on(dev); 6795 netif_tx_start_all_queues(dev); 6796 stmmac_enable_all_dma_irq(priv); 6797 6798 return 0; 6799 6800 irq_error: 6801 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6802 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6803 6804 stmmac_hw_teardown(dev); 6805 init_error: 6806 free_dma_desc_resources(priv, &priv->dma_conf); 6807 dma_desc_error: 6808 return ret; 6809 } 6810 6811 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6812 { 6813 struct stmmac_priv *priv = netdev_priv(dev); 6814 struct stmmac_rx_queue *rx_q; 6815 struct stmmac_tx_queue *tx_q; 6816 struct stmmac_channel *ch; 6817 6818 if (test_bit(STMMAC_DOWN, &priv->state) || 6819 !netif_carrier_ok(priv->dev)) 6820 return -ENETDOWN; 6821 6822 if (!stmmac_xdp_is_enabled(priv)) 6823 return -EINVAL; 6824 6825 if (queue >= priv->plat->rx_queues_to_use || 6826 queue >= priv->plat->tx_queues_to_use) 6827 return -EINVAL; 6828 6829 rx_q = &priv->dma_conf.rx_queue[queue]; 6830 tx_q = &priv->dma_conf.tx_queue[queue]; 6831 ch = &priv->channel[queue]; 6832 6833 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6834 return -EINVAL; 6835 6836 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6837 /* EQoS does not have per-DMA channel SW interrupt, 6838 * so we schedule RX Napi straight-away. 6839 */ 6840 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6841 __napi_schedule(&ch->rxtx_napi); 6842 } 6843 6844 return 0; 6845 } 6846 6847 static void stmmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6848 { 6849 struct stmmac_priv *priv = netdev_priv(dev); 6850 u32 tx_cnt = priv->plat->tx_queues_to_use; 6851 u32 rx_cnt = priv->plat->rx_queues_to_use; 6852 unsigned int start; 6853 int q; 6854 6855 for (q = 0; q < tx_cnt; q++) { 6856 struct stmmac_txq_stats *txq_stats = &priv->dma_conf.tx_queue[q].txq_stats; 6857 u64 tx_packets; 6858 u64 tx_bytes; 6859 6860 do { 6861 start = u64_stats_fetch_begin(&txq_stats->syncp); 6862 tx_packets = txq_stats->tx_packets; 6863 tx_bytes = txq_stats->tx_bytes; 6864 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 6865 6866 stats->tx_packets += tx_packets; 6867 stats->tx_bytes += tx_bytes; 6868 } 6869 6870 for (q = 0; q < rx_cnt; q++) { 6871 struct stmmac_rxq_stats *rxq_stats = &priv->dma_conf.rx_queue[q].rxq_stats; 6872 u64 rx_packets; 6873 u64 rx_bytes; 6874 6875 do { 6876 start = u64_stats_fetch_begin(&rxq_stats->syncp); 6877 rx_packets = rxq_stats->rx_packets; 6878 rx_bytes = rxq_stats->rx_bytes; 6879 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 6880 6881 stats->rx_packets += rx_packets; 6882 stats->rx_bytes += rx_bytes; 6883 } 6884 6885 stats->rx_dropped = priv->xstats.rx_dropped; 6886 stats->rx_errors = priv->xstats.rx_errors; 6887 stats->tx_dropped = priv->xstats.tx_dropped; 6888 stats->tx_errors = priv->xstats.tx_errors; 6889 stats->tx_carrier_errors = priv->xstats.tx_losscarrier + priv->xstats.tx_carrier; 6890 stats->collisions = priv->xstats.tx_collision + priv->xstats.rx_collision; 6891 stats->rx_length_errors = priv->xstats.rx_length; 6892 stats->rx_crc_errors = priv->xstats.rx_crc_errors; 6893 stats->rx_over_errors = priv->xstats.rx_overflow_cntr; 6894 stats->rx_missed_errors = priv->xstats.rx_missed_cntr; 6895 } 6896 6897 static const struct net_device_ops stmmac_netdev_ops = { 6898 .ndo_open = stmmac_open, 6899 .ndo_start_xmit = stmmac_xmit, 6900 .ndo_stop = stmmac_release, 6901 .ndo_change_mtu = stmmac_change_mtu, 6902 .ndo_fix_features = stmmac_fix_features, 6903 .ndo_set_features = stmmac_set_features, 6904 .ndo_set_rx_mode = stmmac_set_rx_mode, 6905 .ndo_tx_timeout = stmmac_tx_timeout, 6906 .ndo_eth_ioctl = stmmac_ioctl, 6907 .ndo_get_stats64 = stmmac_get_stats64, 6908 .ndo_setup_tc = stmmac_setup_tc, 6909 .ndo_select_queue = stmmac_select_queue, 6910 #ifdef CONFIG_NET_POLL_CONTROLLER 6911 .ndo_poll_controller = stmmac_poll_controller, 6912 #endif 6913 .ndo_set_mac_address = stmmac_set_mac_address, 6914 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6915 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6916 .ndo_bpf = stmmac_bpf, 6917 .ndo_xdp_xmit = stmmac_xdp_xmit, 6918 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6919 }; 6920 6921 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6922 { 6923 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6924 return; 6925 if (test_bit(STMMAC_DOWN, &priv->state)) 6926 return; 6927 6928 netdev_err(priv->dev, "Reset adapter.\n"); 6929 6930 rtnl_lock(); 6931 netif_trans_update(priv->dev); 6932 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6933 usleep_range(1000, 2000); 6934 6935 set_bit(STMMAC_DOWN, &priv->state); 6936 dev_close(priv->dev); 6937 dev_open(priv->dev, NULL); 6938 clear_bit(STMMAC_DOWN, &priv->state); 6939 clear_bit(STMMAC_RESETING, &priv->state); 6940 rtnl_unlock(); 6941 } 6942 6943 static void stmmac_service_task(struct work_struct *work) 6944 { 6945 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6946 service_task); 6947 6948 stmmac_reset_subtask(priv); 6949 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6950 } 6951 6952 /** 6953 * stmmac_hw_init - Init the MAC device 6954 * @priv: driver private structure 6955 * Description: this function is to configure the MAC device according to 6956 * some platform parameters or the HW capability register. It prepares the 6957 * driver to use either ring or chain modes and to setup either enhanced or 6958 * normal descriptors. 6959 */ 6960 static int stmmac_hw_init(struct stmmac_priv *priv) 6961 { 6962 int ret; 6963 6964 /* dwmac-sun8i only work in chain mode */ 6965 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) 6966 chain_mode = 1; 6967 priv->chain_mode = chain_mode; 6968 6969 /* Initialize HW Interface */ 6970 ret = stmmac_hwif_init(priv); 6971 if (ret) 6972 return ret; 6973 6974 /* Get the HW capability (new GMAC newer than 3.50a) */ 6975 priv->hw_cap_support = stmmac_get_hw_features(priv); 6976 if (priv->hw_cap_support) { 6977 dev_info(priv->device, "DMA HW capability register supported\n"); 6978 6979 /* We can override some gmac/dma configuration fields: e.g. 6980 * enh_desc, tx_coe (e.g. that are passed through the 6981 * platform) with the values from the HW capability 6982 * register (if supported). 6983 */ 6984 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6985 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6986 !(priv->plat->flags & STMMAC_FLAG_USE_PHY_WOL); 6987 priv->hw->pmt = priv->plat->pmt; 6988 if (priv->dma_cap.hash_tb_sz) { 6989 priv->hw->multicast_filter_bins = 6990 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6991 priv->hw->mcast_bits_log2 = 6992 ilog2(priv->hw->multicast_filter_bins); 6993 } 6994 6995 /* TXCOE doesn't work in thresh DMA mode */ 6996 if (priv->plat->force_thresh_dma_mode) 6997 priv->plat->tx_coe = 0; 6998 else 6999 priv->plat->tx_coe = priv->dma_cap.tx_coe; 7000 7001 /* In case of GMAC4 rx_coe is from HW cap register. */ 7002 priv->plat->rx_coe = priv->dma_cap.rx_coe; 7003 7004 if (priv->dma_cap.rx_coe_type2) 7005 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 7006 else if (priv->dma_cap.rx_coe_type1) 7007 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 7008 7009 } else { 7010 dev_info(priv->device, "No HW DMA feature register supported\n"); 7011 } 7012 7013 if (priv->plat->rx_coe) { 7014 priv->hw->rx_csum = priv->plat->rx_coe; 7015 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 7016 if (priv->synopsys_id < DWMAC_CORE_4_00) 7017 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 7018 } 7019 if (priv->plat->tx_coe) 7020 dev_info(priv->device, "TX Checksum insertion supported\n"); 7021 7022 if (priv->plat->pmt) { 7023 dev_info(priv->device, "Wake-Up On Lan supported\n"); 7024 device_set_wakeup_capable(priv->device, 1); 7025 } 7026 7027 if (priv->dma_cap.tsoen) 7028 dev_info(priv->device, "TSO supported\n"); 7029 7030 priv->hw->vlan_fail_q_en = 7031 (priv->plat->flags & STMMAC_FLAG_VLAN_FAIL_Q_EN); 7032 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 7033 7034 /* Run HW quirks, if any */ 7035 if (priv->hwif_quirks) { 7036 ret = priv->hwif_quirks(priv); 7037 if (ret) 7038 return ret; 7039 } 7040 7041 /* Rx Watchdog is available in the COREs newer than the 3.40. 7042 * In some case, for example on bugged HW this feature 7043 * has to be disable and this can be done by passing the 7044 * riwt_off field from the platform. 7045 */ 7046 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 7047 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 7048 priv->use_riwt = 1; 7049 dev_info(priv->device, 7050 "Enable RX Mitigation via HW Watchdog Timer\n"); 7051 } 7052 7053 return 0; 7054 } 7055 7056 static void stmmac_napi_add(struct net_device *dev) 7057 { 7058 struct stmmac_priv *priv = netdev_priv(dev); 7059 u32 queue, maxq; 7060 7061 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 7062 7063 for (queue = 0; queue < maxq; queue++) { 7064 struct stmmac_channel *ch = &priv->channel[queue]; 7065 7066 ch->priv_data = priv; 7067 ch->index = queue; 7068 spin_lock_init(&ch->lock); 7069 7070 if (queue < priv->plat->rx_queues_to_use) { 7071 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 7072 } 7073 if (queue < priv->plat->tx_queues_to_use) { 7074 netif_napi_add_tx(dev, &ch->tx_napi, 7075 stmmac_napi_poll_tx); 7076 } 7077 if (queue < priv->plat->rx_queues_to_use && 7078 queue < priv->plat->tx_queues_to_use) { 7079 netif_napi_add(dev, &ch->rxtx_napi, 7080 stmmac_napi_poll_rxtx); 7081 } 7082 } 7083 } 7084 7085 static void stmmac_napi_del(struct net_device *dev) 7086 { 7087 struct stmmac_priv *priv = netdev_priv(dev); 7088 u32 queue, maxq; 7089 7090 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 7091 7092 for (queue = 0; queue < maxq; queue++) { 7093 struct stmmac_channel *ch = &priv->channel[queue]; 7094 7095 if (queue < priv->plat->rx_queues_to_use) 7096 netif_napi_del(&ch->rx_napi); 7097 if (queue < priv->plat->tx_queues_to_use) 7098 netif_napi_del(&ch->tx_napi); 7099 if (queue < priv->plat->rx_queues_to_use && 7100 queue < priv->plat->tx_queues_to_use) { 7101 netif_napi_del(&ch->rxtx_napi); 7102 } 7103 } 7104 } 7105 7106 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 7107 { 7108 struct stmmac_priv *priv = netdev_priv(dev); 7109 int ret = 0, i; 7110 7111 if (netif_running(dev)) 7112 stmmac_release(dev); 7113 7114 stmmac_napi_del(dev); 7115 7116 priv->plat->rx_queues_to_use = rx_cnt; 7117 priv->plat->tx_queues_to_use = tx_cnt; 7118 if (!netif_is_rxfh_configured(dev)) 7119 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7120 priv->rss.table[i] = ethtool_rxfh_indir_default(i, 7121 rx_cnt); 7122 7123 stmmac_napi_add(dev); 7124 7125 if (netif_running(dev)) 7126 ret = stmmac_open(dev); 7127 7128 return ret; 7129 } 7130 7131 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 7132 { 7133 struct stmmac_priv *priv = netdev_priv(dev); 7134 int ret = 0; 7135 7136 if (netif_running(dev)) 7137 stmmac_release(dev); 7138 7139 priv->dma_conf.dma_rx_size = rx_size; 7140 priv->dma_conf.dma_tx_size = tx_size; 7141 7142 if (netif_running(dev)) 7143 ret = stmmac_open(dev); 7144 7145 return ret; 7146 } 7147 7148 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 7149 static void stmmac_fpe_lp_task(struct work_struct *work) 7150 { 7151 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 7152 fpe_task); 7153 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 7154 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 7155 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 7156 bool *hs_enable = &fpe_cfg->hs_enable; 7157 bool *enable = &fpe_cfg->enable; 7158 int retries = 20; 7159 7160 while (retries-- > 0) { 7161 /* Bail out immediately if FPE handshake is OFF */ 7162 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 7163 break; 7164 7165 if (*lo_state == FPE_STATE_ENTERING_ON && 7166 *lp_state == FPE_STATE_ENTERING_ON) { 7167 stmmac_fpe_configure(priv, priv->ioaddr, 7168 priv->plat->tx_queues_to_use, 7169 priv->plat->rx_queues_to_use, 7170 *enable); 7171 7172 netdev_info(priv->dev, "configured FPE\n"); 7173 7174 *lo_state = FPE_STATE_ON; 7175 *lp_state = FPE_STATE_ON; 7176 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7177 break; 7178 } 7179 7180 if ((*lo_state == FPE_STATE_CAPABLE || 7181 *lo_state == FPE_STATE_ENTERING_ON) && 7182 *lp_state != FPE_STATE_ON) { 7183 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7184 *lo_state, *lp_state); 7185 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7186 MPACKET_VERIFY); 7187 } 7188 /* Sleep then retry */ 7189 msleep(500); 7190 } 7191 7192 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7193 } 7194 7195 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7196 { 7197 if (priv->plat->fpe_cfg->hs_enable != enable) { 7198 if (enable) { 7199 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7200 MPACKET_VERIFY); 7201 } else { 7202 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7203 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7204 } 7205 7206 priv->plat->fpe_cfg->hs_enable = enable; 7207 } 7208 } 7209 7210 static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp) 7211 { 7212 const struct stmmac_xdp_buff *ctx = (void *)_ctx; 7213 struct dma_desc *desc_contains_ts = ctx->desc; 7214 struct stmmac_priv *priv = ctx->priv; 7215 struct dma_desc *ndesc = ctx->ndesc; 7216 struct dma_desc *desc = ctx->desc; 7217 u64 ns = 0; 7218 7219 if (!priv->hwts_rx_en) 7220 return -ENODATA; 7221 7222 /* For GMAC4, the valid timestamp is from CTX next desc. */ 7223 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 7224 desc_contains_ts = ndesc; 7225 7226 /* Check if timestamp is available */ 7227 if (stmmac_get_rx_timestamp_status(priv, desc, ndesc, priv->adv_ts)) { 7228 stmmac_get_timestamp(priv, desc_contains_ts, priv->adv_ts, &ns); 7229 ns -= priv->plat->cdc_error_adj; 7230 *timestamp = ns_to_ktime(ns); 7231 return 0; 7232 } 7233 7234 return -ENODATA; 7235 } 7236 7237 static const struct xdp_metadata_ops stmmac_xdp_metadata_ops = { 7238 .xmo_rx_timestamp = stmmac_xdp_rx_timestamp, 7239 }; 7240 7241 /** 7242 * stmmac_dvr_probe 7243 * @device: device pointer 7244 * @plat_dat: platform data pointer 7245 * @res: stmmac resource pointer 7246 * Description: this is the main probe function used to 7247 * call the alloc_etherdev, allocate the priv structure. 7248 * Return: 7249 * returns 0 on success, otherwise errno. 7250 */ 7251 int stmmac_dvr_probe(struct device *device, 7252 struct plat_stmmacenet_data *plat_dat, 7253 struct stmmac_resources *res) 7254 { 7255 struct net_device *ndev = NULL; 7256 struct stmmac_priv *priv; 7257 u32 rxq; 7258 int i, ret = 0; 7259 7260 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7261 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7262 if (!ndev) 7263 return -ENOMEM; 7264 7265 SET_NETDEV_DEV(ndev, device); 7266 7267 priv = netdev_priv(ndev); 7268 priv->device = device; 7269 priv->dev = ndev; 7270 7271 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7272 u64_stats_init(&priv->dma_conf.rx_queue[i].rxq_stats.syncp); 7273 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7274 u64_stats_init(&priv->dma_conf.tx_queue[i].txq_stats.syncp); 7275 7276 stmmac_set_ethtool_ops(ndev); 7277 priv->pause = pause; 7278 priv->plat = plat_dat; 7279 priv->ioaddr = res->addr; 7280 priv->dev->base_addr = (unsigned long)res->addr; 7281 priv->plat->dma_cfg->multi_msi_en = 7282 (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN); 7283 7284 priv->dev->irq = res->irq; 7285 priv->wol_irq = res->wol_irq; 7286 priv->lpi_irq = res->lpi_irq; 7287 priv->sfty_ce_irq = res->sfty_ce_irq; 7288 priv->sfty_ue_irq = res->sfty_ue_irq; 7289 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7290 priv->rx_irq[i] = res->rx_irq[i]; 7291 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7292 priv->tx_irq[i] = res->tx_irq[i]; 7293 7294 if (!is_zero_ether_addr(res->mac)) 7295 eth_hw_addr_set(priv->dev, res->mac); 7296 7297 dev_set_drvdata(device, priv->dev); 7298 7299 /* Verify driver arguments */ 7300 stmmac_verify_args(); 7301 7302 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7303 if (!priv->af_xdp_zc_qps) 7304 return -ENOMEM; 7305 7306 /* Allocate workqueue */ 7307 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7308 if (!priv->wq) { 7309 dev_err(priv->device, "failed to create workqueue\n"); 7310 ret = -ENOMEM; 7311 goto error_wq_init; 7312 } 7313 7314 INIT_WORK(&priv->service_task, stmmac_service_task); 7315 7316 /* Initialize Link Partner FPE workqueue */ 7317 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7318 7319 /* Override with kernel parameters if supplied XXX CRS XXX 7320 * this needs to have multiple instances 7321 */ 7322 if ((phyaddr >= 0) && (phyaddr <= 31)) 7323 priv->plat->phy_addr = phyaddr; 7324 7325 if (priv->plat->stmmac_rst) { 7326 ret = reset_control_assert(priv->plat->stmmac_rst); 7327 reset_control_deassert(priv->plat->stmmac_rst); 7328 /* Some reset controllers have only reset callback instead of 7329 * assert + deassert callbacks pair. 7330 */ 7331 if (ret == -ENOTSUPP) 7332 reset_control_reset(priv->plat->stmmac_rst); 7333 } 7334 7335 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7336 if (ret == -ENOTSUPP) 7337 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7338 ERR_PTR(ret)); 7339 7340 /* Init MAC and get the capabilities */ 7341 ret = stmmac_hw_init(priv); 7342 if (ret) 7343 goto error_hw_init; 7344 7345 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7346 */ 7347 if (priv->synopsys_id < DWMAC_CORE_5_20) 7348 priv->plat->dma_cfg->dche = false; 7349 7350 stmmac_check_ether_addr(priv); 7351 7352 ndev->netdev_ops = &stmmac_netdev_ops; 7353 7354 ndev->xdp_metadata_ops = &stmmac_xdp_metadata_ops; 7355 7356 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7357 NETIF_F_RXCSUM; 7358 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7359 NETDEV_XDP_ACT_XSK_ZEROCOPY; 7360 7361 ret = stmmac_tc_init(priv, priv); 7362 if (!ret) { 7363 ndev->hw_features |= NETIF_F_HW_TC; 7364 } 7365 7366 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) { 7367 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7368 if (priv->plat->has_gmac4) 7369 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7370 priv->tso = true; 7371 dev_info(priv->device, "TSO feature enabled\n"); 7372 } 7373 7374 if (priv->dma_cap.sphen && 7375 !(priv->plat->flags & STMMAC_FLAG_SPH_DISABLE)) { 7376 ndev->hw_features |= NETIF_F_GRO; 7377 priv->sph_cap = true; 7378 priv->sph = priv->sph_cap; 7379 dev_info(priv->device, "SPH feature enabled\n"); 7380 } 7381 7382 /* Ideally our host DMA address width is the same as for the 7383 * device. However, it may differ and then we have to use our 7384 * host DMA width for allocation and the device DMA width for 7385 * register handling. 7386 */ 7387 if (priv->plat->host_dma_width) 7388 priv->dma_cap.host_dma_width = priv->plat->host_dma_width; 7389 else 7390 priv->dma_cap.host_dma_width = priv->dma_cap.addr64; 7391 7392 if (priv->dma_cap.host_dma_width) { 7393 ret = dma_set_mask_and_coherent(device, 7394 DMA_BIT_MASK(priv->dma_cap.host_dma_width)); 7395 if (!ret) { 7396 dev_info(priv->device, "Using %d/%d bits DMA host/device width\n", 7397 priv->dma_cap.host_dma_width, priv->dma_cap.addr64); 7398 7399 /* 7400 * If more than 32 bits can be addressed, make sure to 7401 * enable enhanced addressing mode. 7402 */ 7403 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7404 priv->plat->dma_cfg->eame = true; 7405 } else { 7406 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7407 if (ret) { 7408 dev_err(priv->device, "Failed to set DMA Mask\n"); 7409 goto error_hw_init; 7410 } 7411 7412 priv->dma_cap.host_dma_width = 32; 7413 } 7414 } 7415 7416 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7417 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7418 #ifdef STMMAC_VLAN_TAG_USED 7419 /* Both mac100 and gmac support receive VLAN tag detection */ 7420 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7421 if (priv->dma_cap.vlhash) { 7422 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7423 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7424 } 7425 if (priv->dma_cap.vlins) { 7426 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7427 if (priv->dma_cap.dvlan) 7428 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7429 } 7430 #endif 7431 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7432 7433 priv->xstats.threshold = tc; 7434 7435 /* Initialize RSS */ 7436 rxq = priv->plat->rx_queues_to_use; 7437 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7438 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7439 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7440 7441 if (priv->dma_cap.rssen && priv->plat->rss_en) 7442 ndev->features |= NETIF_F_RXHASH; 7443 7444 ndev->vlan_features |= ndev->features; 7445 /* TSO doesn't work on VLANs yet */ 7446 ndev->vlan_features &= ~NETIF_F_TSO; 7447 7448 /* MTU range: 46 - hw-specific max */ 7449 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7450 if (priv->plat->has_xgmac) 7451 ndev->max_mtu = XGMAC_JUMBO_LEN; 7452 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7453 ndev->max_mtu = JUMBO_LEN; 7454 else 7455 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7456 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7457 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7458 */ 7459 if ((priv->plat->maxmtu < ndev->max_mtu) && 7460 (priv->plat->maxmtu >= ndev->min_mtu)) 7461 ndev->max_mtu = priv->plat->maxmtu; 7462 else if (priv->plat->maxmtu < ndev->min_mtu) 7463 dev_warn(priv->device, 7464 "%s: warning: maxmtu having invalid value (%d)\n", 7465 __func__, priv->plat->maxmtu); 7466 7467 if (flow_ctrl) 7468 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7469 7470 ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7471 7472 /* Setup channels NAPI */ 7473 stmmac_napi_add(ndev); 7474 7475 mutex_init(&priv->lock); 7476 7477 /* If a specific clk_csr value is passed from the platform 7478 * this means that the CSR Clock Range selection cannot be 7479 * changed at run-time and it is fixed. Viceversa the driver'll try to 7480 * set the MDC clock dynamically according to the csr actual 7481 * clock input. 7482 */ 7483 if (priv->plat->clk_csr >= 0) 7484 priv->clk_csr = priv->plat->clk_csr; 7485 else 7486 stmmac_clk_csr_set(priv); 7487 7488 stmmac_check_pcs_mode(priv); 7489 7490 pm_runtime_get_noresume(device); 7491 pm_runtime_set_active(device); 7492 if (!pm_runtime_enabled(device)) 7493 pm_runtime_enable(device); 7494 7495 if (priv->hw->pcs != STMMAC_PCS_TBI && 7496 priv->hw->pcs != STMMAC_PCS_RTBI) { 7497 /* MDIO bus Registration */ 7498 ret = stmmac_mdio_register(ndev); 7499 if (ret < 0) { 7500 dev_err_probe(priv->device, ret, 7501 "%s: MDIO bus (id: %d) registration failed\n", 7502 __func__, priv->plat->bus_id); 7503 goto error_mdio_register; 7504 } 7505 } 7506 7507 if (priv->plat->speed_mode_2500) 7508 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7509 7510 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7511 ret = stmmac_xpcs_setup(priv->mii); 7512 if (ret) 7513 goto error_xpcs_setup; 7514 } 7515 7516 ret = stmmac_phy_setup(priv); 7517 if (ret) { 7518 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7519 goto error_phy_setup; 7520 } 7521 7522 ret = register_netdev(ndev); 7523 if (ret) { 7524 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7525 __func__, ret); 7526 goto error_netdev_register; 7527 } 7528 7529 #ifdef CONFIG_DEBUG_FS 7530 stmmac_init_fs(ndev); 7531 #endif 7532 7533 if (priv->plat->dump_debug_regs) 7534 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7535 7536 /* Let pm_runtime_put() disable the clocks. 7537 * If CONFIG_PM is not enabled, the clocks will stay powered. 7538 */ 7539 pm_runtime_put(device); 7540 7541 return ret; 7542 7543 error_netdev_register: 7544 phylink_destroy(priv->phylink); 7545 error_xpcs_setup: 7546 error_phy_setup: 7547 if (priv->hw->pcs != STMMAC_PCS_TBI && 7548 priv->hw->pcs != STMMAC_PCS_RTBI) 7549 stmmac_mdio_unregister(ndev); 7550 error_mdio_register: 7551 stmmac_napi_del(ndev); 7552 error_hw_init: 7553 destroy_workqueue(priv->wq); 7554 error_wq_init: 7555 bitmap_free(priv->af_xdp_zc_qps); 7556 7557 return ret; 7558 } 7559 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7560 7561 /** 7562 * stmmac_dvr_remove 7563 * @dev: device pointer 7564 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7565 * changes the link status, releases the DMA descriptor rings. 7566 */ 7567 void stmmac_dvr_remove(struct device *dev) 7568 { 7569 struct net_device *ndev = dev_get_drvdata(dev); 7570 struct stmmac_priv *priv = netdev_priv(ndev); 7571 7572 netdev_info(priv->dev, "%s: removing driver", __func__); 7573 7574 pm_runtime_get_sync(dev); 7575 7576 stmmac_stop_all_dma(priv); 7577 stmmac_mac_set(priv, priv->ioaddr, false); 7578 netif_carrier_off(ndev); 7579 unregister_netdev(ndev); 7580 7581 #ifdef CONFIG_DEBUG_FS 7582 stmmac_exit_fs(ndev); 7583 #endif 7584 phylink_destroy(priv->phylink); 7585 if (priv->plat->stmmac_rst) 7586 reset_control_assert(priv->plat->stmmac_rst); 7587 reset_control_assert(priv->plat->stmmac_ahb_rst); 7588 if (priv->hw->pcs != STMMAC_PCS_TBI && 7589 priv->hw->pcs != STMMAC_PCS_RTBI) 7590 stmmac_mdio_unregister(ndev); 7591 destroy_workqueue(priv->wq); 7592 mutex_destroy(&priv->lock); 7593 bitmap_free(priv->af_xdp_zc_qps); 7594 7595 pm_runtime_disable(dev); 7596 pm_runtime_put_noidle(dev); 7597 } 7598 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7599 7600 /** 7601 * stmmac_suspend - suspend callback 7602 * @dev: device pointer 7603 * Description: this is the function to suspend the device and it is called 7604 * by the platform driver to stop the network queue, release the resources, 7605 * program the PMT register (for WoL), clean and release driver resources. 7606 */ 7607 int stmmac_suspend(struct device *dev) 7608 { 7609 struct net_device *ndev = dev_get_drvdata(dev); 7610 struct stmmac_priv *priv = netdev_priv(ndev); 7611 u32 chan; 7612 7613 if (!ndev || !netif_running(ndev)) 7614 return 0; 7615 7616 mutex_lock(&priv->lock); 7617 7618 netif_device_detach(ndev); 7619 7620 stmmac_disable_all_queues(priv); 7621 7622 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7623 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7624 7625 if (priv->eee_enabled) { 7626 priv->tx_path_in_lpi_mode = false; 7627 del_timer_sync(&priv->eee_ctrl_timer); 7628 } 7629 7630 /* Stop TX/RX DMA */ 7631 stmmac_stop_all_dma(priv); 7632 7633 if (priv->plat->serdes_powerdown) 7634 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7635 7636 /* Enable Power down mode by programming the PMT regs */ 7637 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7638 stmmac_pmt(priv, priv->hw, priv->wolopts); 7639 priv->irq_wake = 1; 7640 } else { 7641 stmmac_mac_set(priv, priv->ioaddr, false); 7642 pinctrl_pm_select_sleep_state(priv->device); 7643 } 7644 7645 mutex_unlock(&priv->lock); 7646 7647 rtnl_lock(); 7648 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7649 phylink_suspend(priv->phylink, true); 7650 } else { 7651 if (device_may_wakeup(priv->device)) 7652 phylink_speed_down(priv->phylink, false); 7653 phylink_suspend(priv->phylink, false); 7654 } 7655 rtnl_unlock(); 7656 7657 if (priv->dma_cap.fpesel) { 7658 /* Disable FPE */ 7659 stmmac_fpe_configure(priv, priv->ioaddr, 7660 priv->plat->tx_queues_to_use, 7661 priv->plat->rx_queues_to_use, false); 7662 7663 stmmac_fpe_handshake(priv, false); 7664 stmmac_fpe_stop_wq(priv); 7665 } 7666 7667 priv->speed = SPEED_UNKNOWN; 7668 return 0; 7669 } 7670 EXPORT_SYMBOL_GPL(stmmac_suspend); 7671 7672 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7673 { 7674 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7675 7676 rx_q->cur_rx = 0; 7677 rx_q->dirty_rx = 0; 7678 } 7679 7680 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7681 { 7682 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7683 7684 tx_q->cur_tx = 0; 7685 tx_q->dirty_tx = 0; 7686 tx_q->mss = 0; 7687 7688 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7689 } 7690 7691 /** 7692 * stmmac_reset_queues_param - reset queue parameters 7693 * @priv: device pointer 7694 */ 7695 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7696 { 7697 u32 rx_cnt = priv->plat->rx_queues_to_use; 7698 u32 tx_cnt = priv->plat->tx_queues_to_use; 7699 u32 queue; 7700 7701 for (queue = 0; queue < rx_cnt; queue++) 7702 stmmac_reset_rx_queue(priv, queue); 7703 7704 for (queue = 0; queue < tx_cnt; queue++) 7705 stmmac_reset_tx_queue(priv, queue); 7706 } 7707 7708 /** 7709 * stmmac_resume - resume callback 7710 * @dev: device pointer 7711 * Description: when resume this function is invoked to setup the DMA and CORE 7712 * in a usable state. 7713 */ 7714 int stmmac_resume(struct device *dev) 7715 { 7716 struct net_device *ndev = dev_get_drvdata(dev); 7717 struct stmmac_priv *priv = netdev_priv(ndev); 7718 int ret; 7719 7720 if (!netif_running(ndev)) 7721 return 0; 7722 7723 /* Power Down bit, into the PM register, is cleared 7724 * automatically as soon as a magic packet or a Wake-up frame 7725 * is received. Anyway, it's better to manually clear 7726 * this bit because it can generate problems while resuming 7727 * from another devices (e.g. serial console). 7728 */ 7729 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7730 mutex_lock(&priv->lock); 7731 stmmac_pmt(priv, priv->hw, 0); 7732 mutex_unlock(&priv->lock); 7733 priv->irq_wake = 0; 7734 } else { 7735 pinctrl_pm_select_default_state(priv->device); 7736 /* reset the phy so that it's ready */ 7737 if (priv->mii) 7738 stmmac_mdio_reset(priv->mii); 7739 } 7740 7741 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 7742 priv->plat->serdes_powerup) { 7743 ret = priv->plat->serdes_powerup(ndev, 7744 priv->plat->bsp_priv); 7745 7746 if (ret < 0) 7747 return ret; 7748 } 7749 7750 rtnl_lock(); 7751 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7752 phylink_resume(priv->phylink); 7753 } else { 7754 phylink_resume(priv->phylink); 7755 if (device_may_wakeup(priv->device)) 7756 phylink_speed_up(priv->phylink); 7757 } 7758 rtnl_unlock(); 7759 7760 rtnl_lock(); 7761 mutex_lock(&priv->lock); 7762 7763 stmmac_reset_queues_param(priv); 7764 7765 stmmac_free_tx_skbufs(priv); 7766 stmmac_clear_descriptors(priv, &priv->dma_conf); 7767 7768 stmmac_hw_setup(ndev, false); 7769 stmmac_init_coalesce(priv); 7770 stmmac_set_rx_mode(ndev); 7771 7772 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7773 7774 stmmac_enable_all_queues(priv); 7775 stmmac_enable_all_dma_irq(priv); 7776 7777 mutex_unlock(&priv->lock); 7778 rtnl_unlock(); 7779 7780 netif_device_attach(ndev); 7781 7782 return 0; 7783 } 7784 EXPORT_SYMBOL_GPL(stmmac_resume); 7785 7786 #ifndef MODULE 7787 static int __init stmmac_cmdline_opt(char *str) 7788 { 7789 char *opt; 7790 7791 if (!str || !*str) 7792 return 1; 7793 while ((opt = strsep(&str, ",")) != NULL) { 7794 if (!strncmp(opt, "debug:", 6)) { 7795 if (kstrtoint(opt + 6, 0, &debug)) 7796 goto err; 7797 } else if (!strncmp(opt, "phyaddr:", 8)) { 7798 if (kstrtoint(opt + 8, 0, &phyaddr)) 7799 goto err; 7800 } else if (!strncmp(opt, "buf_sz:", 7)) { 7801 if (kstrtoint(opt + 7, 0, &buf_sz)) 7802 goto err; 7803 } else if (!strncmp(opt, "tc:", 3)) { 7804 if (kstrtoint(opt + 3, 0, &tc)) 7805 goto err; 7806 } else if (!strncmp(opt, "watchdog:", 9)) { 7807 if (kstrtoint(opt + 9, 0, &watchdog)) 7808 goto err; 7809 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7810 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7811 goto err; 7812 } else if (!strncmp(opt, "pause:", 6)) { 7813 if (kstrtoint(opt + 6, 0, &pause)) 7814 goto err; 7815 } else if (!strncmp(opt, "eee_timer:", 10)) { 7816 if (kstrtoint(opt + 10, 0, &eee_timer)) 7817 goto err; 7818 } else if (!strncmp(opt, "chain_mode:", 11)) { 7819 if (kstrtoint(opt + 11, 0, &chain_mode)) 7820 goto err; 7821 } 7822 } 7823 return 1; 7824 7825 err: 7826 pr_err("%s: ERROR broken module parameter conversion", __func__); 7827 return 1; 7828 } 7829 7830 __setup("stmmaceth=", stmmac_cmdline_opt); 7831 #endif /* MODULE */ 7832 7833 static int __init stmmac_init(void) 7834 { 7835 #ifdef CONFIG_DEBUG_FS 7836 /* Create debugfs main directory if it doesn't exist yet */ 7837 if (!stmmac_fs_dir) 7838 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7839 register_netdevice_notifier(&stmmac_notifier); 7840 #endif 7841 7842 return 0; 7843 } 7844 7845 static void __exit stmmac_exit(void) 7846 { 7847 #ifdef CONFIG_DEBUG_FS 7848 unregister_netdevice_notifier(&stmmac_notifier); 7849 debugfs_remove_recursive(stmmac_fs_dir); 7850 #endif 7851 } 7852 7853 module_init(stmmac_init) 7854 module_exit(stmmac_exit) 7855 7856 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7857 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7858 MODULE_LICENSE("GPL"); 7859