1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <net/pkt_cls.h> 40 #include "stmmac_ptp.h" 41 #include "stmmac.h" 42 #include <linux/reset.h> 43 #include <linux/of_mdio.h> 44 #include "dwmac1000.h" 45 #include "dwxgmac2.h" 46 #include "hwif.h" 47 48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) 49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 50 51 /* Module parameters */ 52 #define TX_TIMEO 5000 53 static int watchdog = TX_TIMEO; 54 module_param(watchdog, int, 0644); 55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 56 57 static int debug = -1; 58 module_param(debug, int, 0644); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static int phyaddr = -1; 62 module_param(phyaddr, int, 0444); 63 MODULE_PARM_DESC(phyaddr, "Physical device address"); 64 65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 67 68 static int flow_ctrl = FLOW_AUTO; 69 module_param(flow_ctrl, int, 0644); 70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 71 72 static int pause = PAUSE_TIME; 73 module_param(pause, int, 0644); 74 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 75 76 #define TC_DEFAULT 64 77 static int tc = TC_DEFAULT; 78 module_param(tc, int, 0644); 79 MODULE_PARM_DESC(tc, "DMA threshold control value"); 80 81 #define DEFAULT_BUFSIZE 1536 82 static int buf_sz = DEFAULT_BUFSIZE; 83 module_param(buf_sz, int, 0644); 84 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 85 86 #define STMMAC_RX_COPYBREAK 256 87 88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | 90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 91 92 #define STMMAC_DEFAULT_LPI_TIMER 1000 93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 94 module_param(eee_timer, int, 0644); 95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 97 98 /* By default the driver will use the ring mode to manage tx and rx descriptors, 99 * but allow user to force to use the chain instead of the ring 100 */ 101 static unsigned int chain_mode; 102 module_param(chain_mode, int, 0444); 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 104 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 106 107 #ifdef CONFIG_DEBUG_FS 108 static void stmmac_init_fs(struct net_device *dev); 109 static void stmmac_exit_fs(struct net_device *dev); 110 #endif 111 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 113 114 /** 115 * stmmac_verify_args - verify the driver parameters. 116 * Description: it checks the driver parameters and set a default in case of 117 * errors. 118 */ 119 static void stmmac_verify_args(void) 120 { 121 if (unlikely(watchdog < 0)) 122 watchdog = TX_TIMEO; 123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 124 buf_sz = DEFAULT_BUFSIZE; 125 if (unlikely(flow_ctrl > 1)) 126 flow_ctrl = FLOW_AUTO; 127 else if (likely(flow_ctrl < 0)) 128 flow_ctrl = FLOW_OFF; 129 if (unlikely((pause < 0) || (pause > 0xffff))) 130 pause = PAUSE_TIME; 131 if (eee_timer < 0) 132 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 133 } 134 135 /** 136 * stmmac_disable_all_queues - Disable all queues 137 * @priv: driver private structure 138 */ 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 140 { 141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 144 u32 queue; 145 146 for (queue = 0; queue < maxq; queue++) { 147 struct stmmac_channel *ch = &priv->channel[queue]; 148 149 if (queue < rx_queues_cnt) 150 napi_disable(&ch->rx_napi); 151 if (queue < tx_queues_cnt) 152 napi_disable(&ch->tx_napi); 153 } 154 } 155 156 /** 157 * stmmac_enable_all_queues - Enable all queues 158 * @priv: driver private structure 159 */ 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 161 { 162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 165 u32 queue; 166 167 for (queue = 0; queue < maxq; queue++) { 168 struct stmmac_channel *ch = &priv->channel[queue]; 169 170 if (queue < rx_queues_cnt) 171 napi_enable(&ch->rx_napi); 172 if (queue < tx_queues_cnt) 173 napi_enable(&ch->tx_napi); 174 } 175 } 176 177 /** 178 * stmmac_stop_all_queues - Stop all queues 179 * @priv: driver private structure 180 */ 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 182 { 183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 184 u32 queue; 185 186 for (queue = 0; queue < tx_queues_cnt; queue++) 187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 188 } 189 190 /** 191 * stmmac_start_all_queues - Start all queues 192 * @priv: driver private structure 193 */ 194 static void stmmac_start_all_queues(struct stmmac_priv *priv) 195 { 196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 197 u32 queue; 198 199 for (queue = 0; queue < tx_queues_cnt; queue++) 200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 201 } 202 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 204 { 205 if (!test_bit(STMMAC_DOWN, &priv->state) && 206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 207 queue_work(priv->wq, &priv->service_task); 208 } 209 210 static void stmmac_global_err(struct stmmac_priv *priv) 211 { 212 netif_carrier_off(priv->dev); 213 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 214 stmmac_service_event_schedule(priv); 215 } 216 217 /** 218 * stmmac_clk_csr_set - dynamically set the MDC clock 219 * @priv: driver private structure 220 * Description: this is to dynamically set the MDC clock according to the csr 221 * clock input. 222 * Note: 223 * If a specific clk_csr value is passed from the platform 224 * this means that the CSR Clock Range selection cannot be 225 * changed at run-time and it is fixed (as reported in the driver 226 * documentation). Viceversa the driver will try to set the MDC 227 * clock dynamically according to the actual clock input. 228 */ 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 230 { 231 u32 clk_rate; 232 233 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 234 235 /* Platform provided default clk_csr would be assumed valid 236 * for all other cases except for the below mentioned ones. 237 * For values higher than the IEEE 802.3 specified frequency 238 * we can not estimate the proper divider as it is not known 239 * the frequency of clk_csr_i. So we do not change the default 240 * divider. 241 */ 242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 243 if (clk_rate < CSR_F_35M) 244 priv->clk_csr = STMMAC_CSR_20_35M; 245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 246 priv->clk_csr = STMMAC_CSR_35_60M; 247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 248 priv->clk_csr = STMMAC_CSR_60_100M; 249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 250 priv->clk_csr = STMMAC_CSR_100_150M; 251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 252 priv->clk_csr = STMMAC_CSR_150_250M; 253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 254 priv->clk_csr = STMMAC_CSR_250_300M; 255 } 256 257 if (priv->plat->has_sun8i) { 258 if (clk_rate > 160000000) 259 priv->clk_csr = 0x03; 260 else if (clk_rate > 80000000) 261 priv->clk_csr = 0x02; 262 else if (clk_rate > 40000000) 263 priv->clk_csr = 0x01; 264 else 265 priv->clk_csr = 0; 266 } 267 268 if (priv->plat->has_xgmac) { 269 if (clk_rate > 400000000) 270 priv->clk_csr = 0x5; 271 else if (clk_rate > 350000000) 272 priv->clk_csr = 0x4; 273 else if (clk_rate > 300000000) 274 priv->clk_csr = 0x3; 275 else if (clk_rate > 250000000) 276 priv->clk_csr = 0x2; 277 else if (clk_rate > 150000000) 278 priv->clk_csr = 0x1; 279 else 280 priv->clk_csr = 0x0; 281 } 282 } 283 284 static void print_pkt(unsigned char *buf, int len) 285 { 286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 288 } 289 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 291 { 292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 293 u32 avail; 294 295 if (tx_q->dirty_tx > tx_q->cur_tx) 296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 297 else 298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 299 300 return avail; 301 } 302 303 /** 304 * stmmac_rx_dirty - Get RX queue dirty 305 * @priv: driver private structure 306 * @queue: RX queue index 307 */ 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 309 { 310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 311 u32 dirty; 312 313 if (rx_q->dirty_rx <= rx_q->cur_rx) 314 dirty = rx_q->cur_rx - rx_q->dirty_rx; 315 else 316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 317 318 return dirty; 319 } 320 321 /** 322 * stmmac_enable_eee_mode - check and enter in LPI mode 323 * @priv: driver private structure 324 * Description: this function is to verify and enter in LPI mode in case of 325 * EEE. 326 */ 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 328 { 329 u32 tx_cnt = priv->plat->tx_queues_to_use; 330 u32 queue; 331 332 /* check if all TX queues have the work finished */ 333 for (queue = 0; queue < tx_cnt; queue++) { 334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 335 336 if (tx_q->dirty_tx != tx_q->cur_tx) 337 return; /* still unfinished work */ 338 } 339 340 /* Check and enter in LPI mode */ 341 if (!priv->tx_path_in_lpi_mode) 342 stmmac_set_eee_mode(priv, priv->hw, 343 priv->plat->en_tx_lpi_clockgating); 344 } 345 346 /** 347 * stmmac_disable_eee_mode - disable and exit from LPI mode 348 * @priv: driver private structure 349 * Description: this function is to exit and disable EEE in case of 350 * LPI state is true. This is called by the xmit. 351 */ 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 353 { 354 stmmac_reset_eee_mode(priv, priv->hw); 355 del_timer_sync(&priv->eee_ctrl_timer); 356 priv->tx_path_in_lpi_mode = false; 357 } 358 359 /** 360 * stmmac_eee_ctrl_timer - EEE TX SW timer. 361 * @arg : data hook 362 * Description: 363 * if there is no data transfer and if we are not in LPI state, 364 * then MAC Transmitter can be moved to LPI state. 365 */ 366 static void stmmac_eee_ctrl_timer(struct timer_list *t) 367 { 368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 369 370 stmmac_enable_eee_mode(priv); 371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 372 } 373 374 /** 375 * stmmac_eee_init - init EEE 376 * @priv: driver private structure 377 * Description: 378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 379 * can also manage EEE, this function enable the LPI state and start related 380 * timer. 381 */ 382 bool stmmac_eee_init(struct stmmac_priv *priv) 383 { 384 int tx_lpi_timer = priv->tx_lpi_timer; 385 386 /* Using PCS we cannot dial with the phy registers at this stage 387 * so we do not support extra feature like EEE. 388 */ 389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 390 (priv->hw->pcs == STMMAC_PCS_TBI) || 391 (priv->hw->pcs == STMMAC_PCS_RTBI)) 392 return false; 393 394 /* Check if MAC core supports the EEE feature. */ 395 if (!priv->dma_cap.eee) 396 return false; 397 398 mutex_lock(&priv->lock); 399 400 /* Check if it needs to be deactivated */ 401 if (!priv->eee_active) { 402 if (priv->eee_enabled) { 403 netdev_dbg(priv->dev, "disable EEE\n"); 404 del_timer_sync(&priv->eee_ctrl_timer); 405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 406 } 407 mutex_unlock(&priv->lock); 408 return false; 409 } 410 411 if (priv->eee_active && !priv->eee_enabled) { 412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 415 tx_lpi_timer); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 633 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 634 ptp_over_ethernet = PTP_TCR_TSIPENA; 635 break; 636 637 case HWTSTAMP_FILTER_PTP_V2_SYNC: 638 /* PTP v2/802.AS1, any layer, Sync packet */ 639 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 640 ptp_v2 = PTP_TCR_TSVER2ENA; 641 /* take time stamp for SYNC messages only */ 642 ts_event_en = PTP_TCR_TSEVNTENA; 643 644 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 645 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 646 ptp_over_ethernet = PTP_TCR_TSIPENA; 647 break; 648 649 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 650 /* PTP v2/802.AS1, any layer, Delay_req packet */ 651 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 652 ptp_v2 = PTP_TCR_TSVER2ENA; 653 /* take time stamp for Delay_Req messages only */ 654 ts_master_en = PTP_TCR_TSMSTRENA; 655 ts_event_en = PTP_TCR_TSEVNTENA; 656 657 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 658 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 659 ptp_over_ethernet = PTP_TCR_TSIPENA; 660 break; 661 662 case HWTSTAMP_FILTER_NTP_ALL: 663 case HWTSTAMP_FILTER_ALL: 664 /* time stamp any incoming packet */ 665 config.rx_filter = HWTSTAMP_FILTER_ALL; 666 tstamp_all = PTP_TCR_TSENALL; 667 break; 668 669 default: 670 return -ERANGE; 671 } 672 } else { 673 switch (config.rx_filter) { 674 case HWTSTAMP_FILTER_NONE: 675 config.rx_filter = HWTSTAMP_FILTER_NONE; 676 break; 677 default: 678 /* PTP v1, UDP, any kind of event packet */ 679 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 680 break; 681 } 682 } 683 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 684 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 685 686 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 687 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 688 else { 689 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 690 tstamp_all | ptp_v2 | ptp_over_ethernet | 691 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 692 ts_master_en | snap_type_sel); 693 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 694 695 /* program Sub Second Increment reg */ 696 stmmac_config_sub_second_increment(priv, 697 priv->ptpaddr, priv->plat->clk_ptp_rate, 698 xmac, &sec_inc); 699 temp = div_u64(1000000000ULL, sec_inc); 700 701 /* Store sub second increment and flags for later use */ 702 priv->sub_second_inc = sec_inc; 703 priv->systime_flags = value; 704 705 /* calculate default added value: 706 * formula is : 707 * addend = (2^32)/freq_div_ratio; 708 * where, freq_div_ratio = 1e9ns/sec_inc 709 */ 710 temp = (u64)(temp << 32); 711 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 712 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 713 714 /* initialize system time */ 715 ktime_get_real_ts64(&now); 716 717 /* lower 32 bits of tv_sec are safe until y2106 */ 718 stmmac_init_systime(priv, priv->ptpaddr, 719 (u32)now.tv_sec, now.tv_nsec); 720 } 721 722 memcpy(&priv->tstamp_config, &config, sizeof(config)); 723 724 return copy_to_user(ifr->ifr_data, &config, 725 sizeof(config)) ? -EFAULT : 0; 726 } 727 728 /** 729 * stmmac_hwtstamp_get - read hardware timestamping. 730 * @dev: device pointer. 731 * @ifr: An IOCTL specific structure, that can contain a pointer to 732 * a proprietary structure used to pass information to the driver. 733 * Description: 734 * This function obtain the current hardware timestamping settings 735 as requested. 736 */ 737 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 738 { 739 struct stmmac_priv *priv = netdev_priv(dev); 740 struct hwtstamp_config *config = &priv->tstamp_config; 741 742 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 743 return -EOPNOTSUPP; 744 745 return copy_to_user(ifr->ifr_data, config, 746 sizeof(*config)) ? -EFAULT : 0; 747 } 748 749 /** 750 * stmmac_init_ptp - init PTP 751 * @priv: driver private structure 752 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 753 * This is done by looking at the HW cap. register. 754 * This function also registers the ptp driver. 755 */ 756 static int stmmac_init_ptp(struct stmmac_priv *priv) 757 { 758 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 759 760 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 761 return -EOPNOTSUPP; 762 763 priv->adv_ts = 0; 764 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 765 if (xmac && priv->dma_cap.atime_stamp) 766 priv->adv_ts = 1; 767 /* Dwmac 3.x core with extend_desc can support adv_ts */ 768 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 769 priv->adv_ts = 1; 770 771 if (priv->dma_cap.time_stamp) 772 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 773 774 if (priv->adv_ts) 775 netdev_info(priv->dev, 776 "IEEE 1588-2008 Advanced Timestamp supported\n"); 777 778 priv->hwts_tx_en = 0; 779 priv->hwts_rx_en = 0; 780 781 stmmac_ptp_register(priv); 782 783 return 0; 784 } 785 786 static void stmmac_release_ptp(struct stmmac_priv *priv) 787 { 788 if (priv->plat->clk_ptp_ref) 789 clk_disable_unprepare(priv->plat->clk_ptp_ref); 790 stmmac_ptp_unregister(priv); 791 } 792 793 /** 794 * stmmac_mac_flow_ctrl - Configure flow control in all queues 795 * @priv: driver private structure 796 * Description: It is used for configuring the flow control in all queues 797 */ 798 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 799 { 800 u32 tx_cnt = priv->plat->tx_queues_to_use; 801 802 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 803 priv->pause, tx_cnt); 804 } 805 806 static void stmmac_validate(struct phylink_config *config, 807 unsigned long *supported, 808 struct phylink_link_state *state) 809 { 810 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 811 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 812 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 813 int tx_cnt = priv->plat->tx_queues_to_use; 814 int max_speed = priv->plat->max_speed; 815 816 phylink_set(mac_supported, 10baseT_Half); 817 phylink_set(mac_supported, 10baseT_Full); 818 phylink_set(mac_supported, 100baseT_Half); 819 phylink_set(mac_supported, 100baseT_Full); 820 phylink_set(mac_supported, 1000baseT_Half); 821 phylink_set(mac_supported, 1000baseT_Full); 822 phylink_set(mac_supported, 1000baseKX_Full); 823 824 phylink_set(mac_supported, Autoneg); 825 phylink_set(mac_supported, Pause); 826 phylink_set(mac_supported, Asym_Pause); 827 phylink_set_port_modes(mac_supported); 828 829 /* Cut down 1G if asked to */ 830 if ((max_speed > 0) && (max_speed < 1000)) { 831 phylink_set(mask, 1000baseT_Full); 832 phylink_set(mask, 1000baseX_Full); 833 } else if (priv->plat->has_xgmac) { 834 phylink_set(mac_supported, 2500baseT_Full); 835 phylink_set(mac_supported, 5000baseT_Full); 836 phylink_set(mac_supported, 10000baseSR_Full); 837 phylink_set(mac_supported, 10000baseLR_Full); 838 phylink_set(mac_supported, 10000baseER_Full); 839 phylink_set(mac_supported, 10000baseLRM_Full); 840 phylink_set(mac_supported, 10000baseT_Full); 841 phylink_set(mac_supported, 10000baseKX4_Full); 842 phylink_set(mac_supported, 10000baseKR_Full); 843 } 844 845 /* Half-Duplex can only work with single queue */ 846 if (tx_cnt > 1) { 847 phylink_set(mask, 10baseT_Half); 848 phylink_set(mask, 100baseT_Half); 849 phylink_set(mask, 1000baseT_Half); 850 } 851 852 bitmap_and(supported, supported, mac_supported, 853 __ETHTOOL_LINK_MODE_MASK_NBITS); 854 bitmap_andnot(supported, supported, mask, 855 __ETHTOOL_LINK_MODE_MASK_NBITS); 856 bitmap_and(state->advertising, state->advertising, mac_supported, 857 __ETHTOOL_LINK_MODE_MASK_NBITS); 858 bitmap_andnot(state->advertising, state->advertising, mask, 859 __ETHTOOL_LINK_MODE_MASK_NBITS); 860 } 861 862 static int stmmac_mac_link_state(struct phylink_config *config, 863 struct phylink_link_state *state) 864 { 865 return -EOPNOTSUPP; 866 } 867 868 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 869 const struct phylink_link_state *state) 870 { 871 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 872 u32 ctrl; 873 874 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 875 ctrl &= ~priv->hw->link.speed_mask; 876 877 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 878 switch (state->speed) { 879 case SPEED_10000: 880 ctrl |= priv->hw->link.xgmii.speed10000; 881 break; 882 case SPEED_5000: 883 ctrl |= priv->hw->link.xgmii.speed5000; 884 break; 885 case SPEED_2500: 886 ctrl |= priv->hw->link.xgmii.speed2500; 887 break; 888 default: 889 return; 890 } 891 } else { 892 switch (state->speed) { 893 case SPEED_2500: 894 ctrl |= priv->hw->link.speed2500; 895 break; 896 case SPEED_1000: 897 ctrl |= priv->hw->link.speed1000; 898 break; 899 case SPEED_100: 900 ctrl |= priv->hw->link.speed100; 901 break; 902 case SPEED_10: 903 ctrl |= priv->hw->link.speed10; 904 break; 905 default: 906 return; 907 } 908 } 909 910 priv->speed = state->speed; 911 912 if (priv->plat->fix_mac_speed) 913 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 914 915 if (!state->duplex) 916 ctrl &= ~priv->hw->link.duplex; 917 else 918 ctrl |= priv->hw->link.duplex; 919 920 /* Flow Control operation */ 921 if (state->pause) 922 stmmac_mac_flow_ctrl(priv, state->duplex); 923 924 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 925 } 926 927 static void stmmac_mac_an_restart(struct phylink_config *config) 928 { 929 /* Not Supported */ 930 } 931 932 static void stmmac_mac_link_down(struct phylink_config *config, 933 unsigned int mode, phy_interface_t interface) 934 { 935 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 936 937 stmmac_mac_set(priv, priv->ioaddr, false); 938 priv->eee_active = false; 939 stmmac_eee_init(priv); 940 stmmac_set_eee_pls(priv, priv->hw, false); 941 } 942 943 static void stmmac_mac_link_up(struct phylink_config *config, 944 unsigned int mode, phy_interface_t interface, 945 struct phy_device *phy) 946 { 947 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 948 949 stmmac_mac_set(priv, priv->ioaddr, true); 950 if (phy && priv->dma_cap.eee) { 951 priv->eee_active = phy_init_eee(phy, 1) >= 0; 952 priv->eee_enabled = stmmac_eee_init(priv); 953 stmmac_set_eee_pls(priv, priv->hw, true); 954 } 955 } 956 957 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 958 .validate = stmmac_validate, 959 .mac_link_state = stmmac_mac_link_state, 960 .mac_config = stmmac_mac_config, 961 .mac_an_restart = stmmac_mac_an_restart, 962 .mac_link_down = stmmac_mac_link_down, 963 .mac_link_up = stmmac_mac_link_up, 964 }; 965 966 /** 967 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 968 * @priv: driver private structure 969 * Description: this is to verify if the HW supports the PCS. 970 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 971 * configured for the TBI, RTBI, or SGMII PHY interface. 972 */ 973 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 974 { 975 int interface = priv->plat->interface; 976 977 if (priv->dma_cap.pcs) { 978 if ((interface == PHY_INTERFACE_MODE_RGMII) || 979 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 980 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 981 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 982 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 983 priv->hw->pcs = STMMAC_PCS_RGMII; 984 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 985 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 986 priv->hw->pcs = STMMAC_PCS_SGMII; 987 } 988 } 989 } 990 991 /** 992 * stmmac_init_phy - PHY initialization 993 * @dev: net device structure 994 * Description: it initializes the driver's PHY state, and attaches the PHY 995 * to the mac driver. 996 * Return value: 997 * 0 on success 998 */ 999 static int stmmac_init_phy(struct net_device *dev) 1000 { 1001 struct stmmac_priv *priv = netdev_priv(dev); 1002 struct device_node *node; 1003 int ret; 1004 1005 node = priv->plat->phylink_node; 1006 1007 if (node) 1008 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1009 1010 /* Some DT bindings do not set-up the PHY handle. Let's try to 1011 * manually parse it 1012 */ 1013 if (!node || ret) { 1014 int addr = priv->plat->phy_addr; 1015 struct phy_device *phydev; 1016 1017 phydev = mdiobus_get_phy(priv->mii, addr); 1018 if (!phydev) { 1019 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1020 return -ENODEV; 1021 } 1022 1023 ret = phylink_connect_phy(priv->phylink, phydev); 1024 } 1025 1026 return ret; 1027 } 1028 1029 static int stmmac_phy_setup(struct stmmac_priv *priv) 1030 { 1031 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1032 int mode = priv->plat->interface; 1033 struct phylink *phylink; 1034 1035 priv->phylink_config.dev = &priv->dev->dev; 1036 priv->phylink_config.type = PHYLINK_NETDEV; 1037 1038 phylink = phylink_create(&priv->phylink_config, fwnode, 1039 mode, &stmmac_phylink_mac_ops); 1040 if (IS_ERR(phylink)) 1041 return PTR_ERR(phylink); 1042 1043 priv->phylink = phylink; 1044 return 0; 1045 } 1046 1047 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1048 { 1049 u32 rx_cnt = priv->plat->rx_queues_to_use; 1050 void *head_rx; 1051 u32 queue; 1052 1053 /* Display RX rings */ 1054 for (queue = 0; queue < rx_cnt; queue++) { 1055 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1056 1057 pr_info("\tRX Queue %u rings\n", queue); 1058 1059 if (priv->extend_desc) 1060 head_rx = (void *)rx_q->dma_erx; 1061 else 1062 head_rx = (void *)rx_q->dma_rx; 1063 1064 /* Display RX ring */ 1065 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1066 } 1067 } 1068 1069 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1070 { 1071 u32 tx_cnt = priv->plat->tx_queues_to_use; 1072 void *head_tx; 1073 u32 queue; 1074 1075 /* Display TX rings */ 1076 for (queue = 0; queue < tx_cnt; queue++) { 1077 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1078 1079 pr_info("\tTX Queue %d rings\n", queue); 1080 1081 if (priv->extend_desc) 1082 head_tx = (void *)tx_q->dma_etx; 1083 else 1084 head_tx = (void *)tx_q->dma_tx; 1085 1086 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1087 } 1088 } 1089 1090 static void stmmac_display_rings(struct stmmac_priv *priv) 1091 { 1092 /* Display RX ring */ 1093 stmmac_display_rx_rings(priv); 1094 1095 /* Display TX ring */ 1096 stmmac_display_tx_rings(priv); 1097 } 1098 1099 static int stmmac_set_bfsize(int mtu, int bufsize) 1100 { 1101 int ret = bufsize; 1102 1103 if (mtu >= BUF_SIZE_4KiB) 1104 ret = BUF_SIZE_8KiB; 1105 else if (mtu >= BUF_SIZE_2KiB) 1106 ret = BUF_SIZE_4KiB; 1107 else if (mtu > DEFAULT_BUFSIZE) 1108 ret = BUF_SIZE_2KiB; 1109 else 1110 ret = DEFAULT_BUFSIZE; 1111 1112 return ret; 1113 } 1114 1115 /** 1116 * stmmac_clear_rx_descriptors - clear RX descriptors 1117 * @priv: driver private structure 1118 * @queue: RX queue index 1119 * Description: this function is called to clear the RX descriptors 1120 * in case of both basic and extended descriptors are used. 1121 */ 1122 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1123 { 1124 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1125 int i; 1126 1127 /* Clear the RX descriptors */ 1128 for (i = 0; i < DMA_RX_SIZE; i++) 1129 if (priv->extend_desc) 1130 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1131 priv->use_riwt, priv->mode, 1132 (i == DMA_RX_SIZE - 1), 1133 priv->dma_buf_sz); 1134 else 1135 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1136 priv->use_riwt, priv->mode, 1137 (i == DMA_RX_SIZE - 1), 1138 priv->dma_buf_sz); 1139 } 1140 1141 /** 1142 * stmmac_clear_tx_descriptors - clear tx descriptors 1143 * @priv: driver private structure 1144 * @queue: TX queue index. 1145 * Description: this function is called to clear the TX descriptors 1146 * in case of both basic and extended descriptors are used. 1147 */ 1148 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1149 { 1150 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1151 int i; 1152 1153 /* Clear the TX descriptors */ 1154 for (i = 0; i < DMA_TX_SIZE; i++) 1155 if (priv->extend_desc) 1156 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1157 priv->mode, (i == DMA_TX_SIZE - 1)); 1158 else 1159 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1160 priv->mode, (i == DMA_TX_SIZE - 1)); 1161 } 1162 1163 /** 1164 * stmmac_clear_descriptors - clear descriptors 1165 * @priv: driver private structure 1166 * Description: this function is called to clear the TX and RX descriptors 1167 * in case of both basic and extended descriptors are used. 1168 */ 1169 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1170 { 1171 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1172 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1173 u32 queue; 1174 1175 /* Clear the RX descriptors */ 1176 for (queue = 0; queue < rx_queue_cnt; queue++) 1177 stmmac_clear_rx_descriptors(priv, queue); 1178 1179 /* Clear the TX descriptors */ 1180 for (queue = 0; queue < tx_queue_cnt; queue++) 1181 stmmac_clear_tx_descriptors(priv, queue); 1182 } 1183 1184 /** 1185 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1186 * @priv: driver private structure 1187 * @p: descriptor pointer 1188 * @i: descriptor index 1189 * @flags: gfp flag 1190 * @queue: RX queue index 1191 * Description: this function is called to allocate a receive buffer, perform 1192 * the DMA mapping and init the descriptor. 1193 */ 1194 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1195 int i, gfp_t flags, u32 queue) 1196 { 1197 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1198 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1199 1200 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1201 if (!buf->page) 1202 return -ENOMEM; 1203 1204 if (priv->sph) { 1205 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1206 if (!buf->sec_page) 1207 return -ENOMEM; 1208 1209 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1210 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1211 } else { 1212 buf->sec_page = NULL; 1213 } 1214 1215 buf->addr = page_pool_get_dma_addr(buf->page); 1216 stmmac_set_desc_addr(priv, p, buf->addr); 1217 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1218 stmmac_init_desc3(priv, p); 1219 1220 return 0; 1221 } 1222 1223 /** 1224 * stmmac_free_rx_buffer - free RX dma buffers 1225 * @priv: private structure 1226 * @queue: RX queue index 1227 * @i: buffer index. 1228 */ 1229 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1230 { 1231 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1232 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1233 1234 if (buf->page) 1235 page_pool_put_page(rx_q->page_pool, buf->page, false); 1236 buf->page = NULL; 1237 1238 if (buf->sec_page) 1239 page_pool_put_page(rx_q->page_pool, buf->sec_page, false); 1240 buf->sec_page = NULL; 1241 } 1242 1243 /** 1244 * stmmac_free_tx_buffer - free RX dma buffers 1245 * @priv: private structure 1246 * @queue: RX queue index 1247 * @i: buffer index. 1248 */ 1249 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1250 { 1251 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1252 1253 if (tx_q->tx_skbuff_dma[i].buf) { 1254 if (tx_q->tx_skbuff_dma[i].map_as_page) 1255 dma_unmap_page(priv->device, 1256 tx_q->tx_skbuff_dma[i].buf, 1257 tx_q->tx_skbuff_dma[i].len, 1258 DMA_TO_DEVICE); 1259 else 1260 dma_unmap_single(priv->device, 1261 tx_q->tx_skbuff_dma[i].buf, 1262 tx_q->tx_skbuff_dma[i].len, 1263 DMA_TO_DEVICE); 1264 } 1265 1266 if (tx_q->tx_skbuff[i]) { 1267 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1268 tx_q->tx_skbuff[i] = NULL; 1269 tx_q->tx_skbuff_dma[i].buf = 0; 1270 tx_q->tx_skbuff_dma[i].map_as_page = false; 1271 } 1272 } 1273 1274 /** 1275 * init_dma_rx_desc_rings - init the RX descriptor rings 1276 * @dev: net device structure 1277 * @flags: gfp flag. 1278 * Description: this function initializes the DMA RX descriptors 1279 * and allocates the socket buffers. It supports the chained and ring 1280 * modes. 1281 */ 1282 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1283 { 1284 struct stmmac_priv *priv = netdev_priv(dev); 1285 u32 rx_count = priv->plat->rx_queues_to_use; 1286 int ret = -ENOMEM; 1287 int bfsize = 0; 1288 int queue; 1289 int i; 1290 1291 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 1292 if (bfsize < 0) 1293 bfsize = 0; 1294 1295 if (bfsize < BUF_SIZE_16KiB) 1296 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1297 1298 priv->dma_buf_sz = bfsize; 1299 1300 /* RX INITIALIZATION */ 1301 netif_dbg(priv, probe, priv->dev, 1302 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1303 1304 for (queue = 0; queue < rx_count; queue++) { 1305 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1306 1307 netif_dbg(priv, probe, priv->dev, 1308 "(%s) dma_rx_phy=0x%08x\n", __func__, 1309 (u32)rx_q->dma_rx_phy); 1310 1311 stmmac_clear_rx_descriptors(priv, queue); 1312 1313 for (i = 0; i < DMA_RX_SIZE; i++) { 1314 struct dma_desc *p; 1315 1316 if (priv->extend_desc) 1317 p = &((rx_q->dma_erx + i)->basic); 1318 else 1319 p = rx_q->dma_rx + i; 1320 1321 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1322 queue); 1323 if (ret) 1324 goto err_init_rx_buffers; 1325 } 1326 1327 rx_q->cur_rx = 0; 1328 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1329 1330 /* Setup the chained descriptor addresses */ 1331 if (priv->mode == STMMAC_CHAIN_MODE) { 1332 if (priv->extend_desc) 1333 stmmac_mode_init(priv, rx_q->dma_erx, 1334 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1335 else 1336 stmmac_mode_init(priv, rx_q->dma_rx, 1337 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1338 } 1339 } 1340 1341 buf_sz = bfsize; 1342 1343 return 0; 1344 1345 err_init_rx_buffers: 1346 while (queue >= 0) { 1347 while (--i >= 0) 1348 stmmac_free_rx_buffer(priv, queue, i); 1349 1350 if (queue == 0) 1351 break; 1352 1353 i = DMA_RX_SIZE; 1354 queue--; 1355 } 1356 1357 return ret; 1358 } 1359 1360 /** 1361 * init_dma_tx_desc_rings - init the TX descriptor rings 1362 * @dev: net device structure. 1363 * Description: this function initializes the DMA TX descriptors 1364 * and allocates the socket buffers. It supports the chained and ring 1365 * modes. 1366 */ 1367 static int init_dma_tx_desc_rings(struct net_device *dev) 1368 { 1369 struct stmmac_priv *priv = netdev_priv(dev); 1370 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1371 u32 queue; 1372 int i; 1373 1374 for (queue = 0; queue < tx_queue_cnt; queue++) { 1375 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1376 1377 netif_dbg(priv, probe, priv->dev, 1378 "(%s) dma_tx_phy=0x%08x\n", __func__, 1379 (u32)tx_q->dma_tx_phy); 1380 1381 /* Setup the chained descriptor addresses */ 1382 if (priv->mode == STMMAC_CHAIN_MODE) { 1383 if (priv->extend_desc) 1384 stmmac_mode_init(priv, tx_q->dma_etx, 1385 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1386 else 1387 stmmac_mode_init(priv, tx_q->dma_tx, 1388 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1389 } 1390 1391 for (i = 0; i < DMA_TX_SIZE; i++) { 1392 struct dma_desc *p; 1393 if (priv->extend_desc) 1394 p = &((tx_q->dma_etx + i)->basic); 1395 else 1396 p = tx_q->dma_tx + i; 1397 1398 stmmac_clear_desc(priv, p); 1399 1400 tx_q->tx_skbuff_dma[i].buf = 0; 1401 tx_q->tx_skbuff_dma[i].map_as_page = false; 1402 tx_q->tx_skbuff_dma[i].len = 0; 1403 tx_q->tx_skbuff_dma[i].last_segment = false; 1404 tx_q->tx_skbuff[i] = NULL; 1405 } 1406 1407 tx_q->dirty_tx = 0; 1408 tx_q->cur_tx = 0; 1409 tx_q->mss = 0; 1410 1411 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1412 } 1413 1414 return 0; 1415 } 1416 1417 /** 1418 * init_dma_desc_rings - init the RX/TX descriptor rings 1419 * @dev: net device structure 1420 * @flags: gfp flag. 1421 * Description: this function initializes the DMA RX/TX descriptors 1422 * and allocates the socket buffers. It supports the chained and ring 1423 * modes. 1424 */ 1425 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1426 { 1427 struct stmmac_priv *priv = netdev_priv(dev); 1428 int ret; 1429 1430 ret = init_dma_rx_desc_rings(dev, flags); 1431 if (ret) 1432 return ret; 1433 1434 ret = init_dma_tx_desc_rings(dev); 1435 1436 stmmac_clear_descriptors(priv); 1437 1438 if (netif_msg_hw(priv)) 1439 stmmac_display_rings(priv); 1440 1441 return ret; 1442 } 1443 1444 /** 1445 * dma_free_rx_skbufs - free RX dma buffers 1446 * @priv: private structure 1447 * @queue: RX queue index 1448 */ 1449 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1450 { 1451 int i; 1452 1453 for (i = 0; i < DMA_RX_SIZE; i++) 1454 stmmac_free_rx_buffer(priv, queue, i); 1455 } 1456 1457 /** 1458 * dma_free_tx_skbufs - free TX dma buffers 1459 * @priv: private structure 1460 * @queue: TX queue index 1461 */ 1462 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1463 { 1464 int i; 1465 1466 for (i = 0; i < DMA_TX_SIZE; i++) 1467 stmmac_free_tx_buffer(priv, queue, i); 1468 } 1469 1470 /** 1471 * free_dma_rx_desc_resources - free RX dma desc resources 1472 * @priv: private structure 1473 */ 1474 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1475 { 1476 u32 rx_count = priv->plat->rx_queues_to_use; 1477 u32 queue; 1478 1479 /* Free RX queue resources */ 1480 for (queue = 0; queue < rx_count; queue++) { 1481 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1482 1483 /* Release the DMA RX socket buffers */ 1484 dma_free_rx_skbufs(priv, queue); 1485 1486 /* Free DMA regions of consistent memory previously allocated */ 1487 if (!priv->extend_desc) 1488 dma_free_coherent(priv->device, 1489 DMA_RX_SIZE * sizeof(struct dma_desc), 1490 rx_q->dma_rx, rx_q->dma_rx_phy); 1491 else 1492 dma_free_coherent(priv->device, DMA_RX_SIZE * 1493 sizeof(struct dma_extended_desc), 1494 rx_q->dma_erx, rx_q->dma_rx_phy); 1495 1496 kfree(rx_q->buf_pool); 1497 if (rx_q->page_pool) { 1498 page_pool_request_shutdown(rx_q->page_pool); 1499 page_pool_destroy(rx_q->page_pool); 1500 } 1501 } 1502 } 1503 1504 /** 1505 * free_dma_tx_desc_resources - free TX dma desc resources 1506 * @priv: private structure 1507 */ 1508 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1509 { 1510 u32 tx_count = priv->plat->tx_queues_to_use; 1511 u32 queue; 1512 1513 /* Free TX queue resources */ 1514 for (queue = 0; queue < tx_count; queue++) { 1515 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1516 1517 /* Release the DMA TX socket buffers */ 1518 dma_free_tx_skbufs(priv, queue); 1519 1520 /* Free DMA regions of consistent memory previously allocated */ 1521 if (!priv->extend_desc) 1522 dma_free_coherent(priv->device, 1523 DMA_TX_SIZE * sizeof(struct dma_desc), 1524 tx_q->dma_tx, tx_q->dma_tx_phy); 1525 else 1526 dma_free_coherent(priv->device, DMA_TX_SIZE * 1527 sizeof(struct dma_extended_desc), 1528 tx_q->dma_etx, tx_q->dma_tx_phy); 1529 1530 kfree(tx_q->tx_skbuff_dma); 1531 kfree(tx_q->tx_skbuff); 1532 } 1533 } 1534 1535 /** 1536 * alloc_dma_rx_desc_resources - alloc RX resources. 1537 * @priv: private structure 1538 * Description: according to which descriptor can be used (extend or basic) 1539 * this function allocates the resources for TX and RX paths. In case of 1540 * reception, for example, it pre-allocated the RX socket buffer in order to 1541 * allow zero-copy mechanism. 1542 */ 1543 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1544 { 1545 u32 rx_count = priv->plat->rx_queues_to_use; 1546 int ret = -ENOMEM; 1547 u32 queue; 1548 1549 /* RX queues buffers and DMA */ 1550 for (queue = 0; queue < rx_count; queue++) { 1551 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1552 struct page_pool_params pp_params = { 0 }; 1553 1554 rx_q->queue_index = queue; 1555 rx_q->priv_data = priv; 1556 1557 pp_params.flags = PP_FLAG_DMA_MAP; 1558 pp_params.pool_size = DMA_RX_SIZE; 1559 pp_params.order = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1560 pp_params.nid = dev_to_node(priv->device); 1561 pp_params.dev = priv->device; 1562 pp_params.dma_dir = DMA_FROM_DEVICE; 1563 1564 rx_q->page_pool = page_pool_create(&pp_params); 1565 if (IS_ERR(rx_q->page_pool)) { 1566 ret = PTR_ERR(rx_q->page_pool); 1567 rx_q->page_pool = NULL; 1568 goto err_dma; 1569 } 1570 1571 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1572 GFP_KERNEL); 1573 if (!rx_q->buf_pool) 1574 goto err_dma; 1575 1576 if (priv->extend_desc) { 1577 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1578 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1579 &rx_q->dma_rx_phy, 1580 GFP_KERNEL); 1581 if (!rx_q->dma_erx) 1582 goto err_dma; 1583 1584 } else { 1585 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1586 DMA_RX_SIZE * sizeof(struct dma_desc), 1587 &rx_q->dma_rx_phy, 1588 GFP_KERNEL); 1589 if (!rx_q->dma_rx) 1590 goto err_dma; 1591 } 1592 } 1593 1594 return 0; 1595 1596 err_dma: 1597 free_dma_rx_desc_resources(priv); 1598 1599 return ret; 1600 } 1601 1602 /** 1603 * alloc_dma_tx_desc_resources - alloc TX resources. 1604 * @priv: private structure 1605 * Description: according to which descriptor can be used (extend or basic) 1606 * this function allocates the resources for TX and RX paths. In case of 1607 * reception, for example, it pre-allocated the RX socket buffer in order to 1608 * allow zero-copy mechanism. 1609 */ 1610 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1611 { 1612 u32 tx_count = priv->plat->tx_queues_to_use; 1613 int ret = -ENOMEM; 1614 u32 queue; 1615 1616 /* TX queues buffers and DMA */ 1617 for (queue = 0; queue < tx_count; queue++) { 1618 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1619 1620 tx_q->queue_index = queue; 1621 tx_q->priv_data = priv; 1622 1623 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1624 sizeof(*tx_q->tx_skbuff_dma), 1625 GFP_KERNEL); 1626 if (!tx_q->tx_skbuff_dma) 1627 goto err_dma; 1628 1629 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1630 sizeof(struct sk_buff *), 1631 GFP_KERNEL); 1632 if (!tx_q->tx_skbuff) 1633 goto err_dma; 1634 1635 if (priv->extend_desc) { 1636 tx_q->dma_etx = dma_alloc_coherent(priv->device, 1637 DMA_TX_SIZE * sizeof(struct dma_extended_desc), 1638 &tx_q->dma_tx_phy, 1639 GFP_KERNEL); 1640 if (!tx_q->dma_etx) 1641 goto err_dma; 1642 } else { 1643 tx_q->dma_tx = dma_alloc_coherent(priv->device, 1644 DMA_TX_SIZE * sizeof(struct dma_desc), 1645 &tx_q->dma_tx_phy, 1646 GFP_KERNEL); 1647 if (!tx_q->dma_tx) 1648 goto err_dma; 1649 } 1650 } 1651 1652 return 0; 1653 1654 err_dma: 1655 free_dma_tx_desc_resources(priv); 1656 1657 return ret; 1658 } 1659 1660 /** 1661 * alloc_dma_desc_resources - alloc TX/RX resources. 1662 * @priv: private structure 1663 * Description: according to which descriptor can be used (extend or basic) 1664 * this function allocates the resources for TX and RX paths. In case of 1665 * reception, for example, it pre-allocated the RX socket buffer in order to 1666 * allow zero-copy mechanism. 1667 */ 1668 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1669 { 1670 /* RX Allocation */ 1671 int ret = alloc_dma_rx_desc_resources(priv); 1672 1673 if (ret) 1674 return ret; 1675 1676 ret = alloc_dma_tx_desc_resources(priv); 1677 1678 return ret; 1679 } 1680 1681 /** 1682 * free_dma_desc_resources - free dma desc resources 1683 * @priv: private structure 1684 */ 1685 static void free_dma_desc_resources(struct stmmac_priv *priv) 1686 { 1687 /* Release the DMA RX socket buffers */ 1688 free_dma_rx_desc_resources(priv); 1689 1690 /* Release the DMA TX socket buffers */ 1691 free_dma_tx_desc_resources(priv); 1692 } 1693 1694 /** 1695 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1696 * @priv: driver private structure 1697 * Description: It is used for enabling the rx queues in the MAC 1698 */ 1699 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1700 { 1701 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1702 int queue; 1703 u8 mode; 1704 1705 for (queue = 0; queue < rx_queues_count; queue++) { 1706 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1707 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1708 } 1709 } 1710 1711 /** 1712 * stmmac_start_rx_dma - start RX DMA channel 1713 * @priv: driver private structure 1714 * @chan: RX channel index 1715 * Description: 1716 * This starts a RX DMA channel 1717 */ 1718 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1719 { 1720 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1721 stmmac_start_rx(priv, priv->ioaddr, chan); 1722 } 1723 1724 /** 1725 * stmmac_start_tx_dma - start TX DMA channel 1726 * @priv: driver private structure 1727 * @chan: TX channel index 1728 * Description: 1729 * This starts a TX DMA channel 1730 */ 1731 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1732 { 1733 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1734 stmmac_start_tx(priv, priv->ioaddr, chan); 1735 } 1736 1737 /** 1738 * stmmac_stop_rx_dma - stop RX DMA channel 1739 * @priv: driver private structure 1740 * @chan: RX channel index 1741 * Description: 1742 * This stops a RX DMA channel 1743 */ 1744 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1745 { 1746 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1747 stmmac_stop_rx(priv, priv->ioaddr, chan); 1748 } 1749 1750 /** 1751 * stmmac_stop_tx_dma - stop TX DMA channel 1752 * @priv: driver private structure 1753 * @chan: TX channel index 1754 * Description: 1755 * This stops a TX DMA channel 1756 */ 1757 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1758 { 1759 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1760 stmmac_stop_tx(priv, priv->ioaddr, chan); 1761 } 1762 1763 /** 1764 * stmmac_start_all_dma - start all RX and TX DMA channels 1765 * @priv: driver private structure 1766 * Description: 1767 * This starts all the RX and TX DMA channels 1768 */ 1769 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1770 { 1771 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1772 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1773 u32 chan = 0; 1774 1775 for (chan = 0; chan < rx_channels_count; chan++) 1776 stmmac_start_rx_dma(priv, chan); 1777 1778 for (chan = 0; chan < tx_channels_count; chan++) 1779 stmmac_start_tx_dma(priv, chan); 1780 } 1781 1782 /** 1783 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1784 * @priv: driver private structure 1785 * Description: 1786 * This stops the RX and TX DMA channels 1787 */ 1788 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1789 { 1790 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1791 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1792 u32 chan = 0; 1793 1794 for (chan = 0; chan < rx_channels_count; chan++) 1795 stmmac_stop_rx_dma(priv, chan); 1796 1797 for (chan = 0; chan < tx_channels_count; chan++) 1798 stmmac_stop_tx_dma(priv, chan); 1799 } 1800 1801 /** 1802 * stmmac_dma_operation_mode - HW DMA operation mode 1803 * @priv: driver private structure 1804 * Description: it is used for configuring the DMA operation mode register in 1805 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1806 */ 1807 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1808 { 1809 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1810 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1811 int rxfifosz = priv->plat->rx_fifo_size; 1812 int txfifosz = priv->plat->tx_fifo_size; 1813 u32 txmode = 0; 1814 u32 rxmode = 0; 1815 u32 chan = 0; 1816 u8 qmode = 0; 1817 1818 if (rxfifosz == 0) 1819 rxfifosz = priv->dma_cap.rx_fifo_size; 1820 if (txfifosz == 0) 1821 txfifosz = priv->dma_cap.tx_fifo_size; 1822 1823 /* Adjust for real per queue fifo size */ 1824 rxfifosz /= rx_channels_count; 1825 txfifosz /= tx_channels_count; 1826 1827 if (priv->plat->force_thresh_dma_mode) { 1828 txmode = tc; 1829 rxmode = tc; 1830 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1831 /* 1832 * In case of GMAC, SF mode can be enabled 1833 * to perform the TX COE in HW. This depends on: 1834 * 1) TX COE if actually supported 1835 * 2) There is no bugged Jumbo frame support 1836 * that needs to not insert csum in the TDES. 1837 */ 1838 txmode = SF_DMA_MODE; 1839 rxmode = SF_DMA_MODE; 1840 priv->xstats.threshold = SF_DMA_MODE; 1841 } else { 1842 txmode = tc; 1843 rxmode = SF_DMA_MODE; 1844 } 1845 1846 /* configure all channels */ 1847 for (chan = 0; chan < rx_channels_count; chan++) { 1848 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1849 1850 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1851 rxfifosz, qmode); 1852 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1853 chan); 1854 } 1855 1856 for (chan = 0; chan < tx_channels_count; chan++) { 1857 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1858 1859 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1860 txfifosz, qmode); 1861 } 1862 } 1863 1864 /** 1865 * stmmac_tx_clean - to manage the transmission completion 1866 * @priv: driver private structure 1867 * @queue: TX queue index 1868 * Description: it reclaims the transmit resources after transmission completes. 1869 */ 1870 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1871 { 1872 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1873 unsigned int bytes_compl = 0, pkts_compl = 0; 1874 unsigned int entry, count = 0; 1875 1876 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1877 1878 priv->xstats.tx_clean++; 1879 1880 entry = tx_q->dirty_tx; 1881 while ((entry != tx_q->cur_tx) && (count < budget)) { 1882 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1883 struct dma_desc *p; 1884 int status; 1885 1886 if (priv->extend_desc) 1887 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1888 else 1889 p = tx_q->dma_tx + entry; 1890 1891 status = stmmac_tx_status(priv, &priv->dev->stats, 1892 &priv->xstats, p, priv->ioaddr); 1893 /* Check if the descriptor is owned by the DMA */ 1894 if (unlikely(status & tx_dma_own)) 1895 break; 1896 1897 count++; 1898 1899 /* Make sure descriptor fields are read after reading 1900 * the own bit. 1901 */ 1902 dma_rmb(); 1903 1904 /* Just consider the last segment and ...*/ 1905 if (likely(!(status & tx_not_ls))) { 1906 /* ... verify the status error condition */ 1907 if (unlikely(status & tx_err)) { 1908 priv->dev->stats.tx_errors++; 1909 } else { 1910 priv->dev->stats.tx_packets++; 1911 priv->xstats.tx_pkt_n++; 1912 } 1913 stmmac_get_tx_hwtstamp(priv, p, skb); 1914 } 1915 1916 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1917 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1918 dma_unmap_page(priv->device, 1919 tx_q->tx_skbuff_dma[entry].buf, 1920 tx_q->tx_skbuff_dma[entry].len, 1921 DMA_TO_DEVICE); 1922 else 1923 dma_unmap_single(priv->device, 1924 tx_q->tx_skbuff_dma[entry].buf, 1925 tx_q->tx_skbuff_dma[entry].len, 1926 DMA_TO_DEVICE); 1927 tx_q->tx_skbuff_dma[entry].buf = 0; 1928 tx_q->tx_skbuff_dma[entry].len = 0; 1929 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1930 } 1931 1932 stmmac_clean_desc3(priv, tx_q, p); 1933 1934 tx_q->tx_skbuff_dma[entry].last_segment = false; 1935 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1936 1937 if (likely(skb != NULL)) { 1938 pkts_compl++; 1939 bytes_compl += skb->len; 1940 dev_consume_skb_any(skb); 1941 tx_q->tx_skbuff[entry] = NULL; 1942 } 1943 1944 stmmac_release_tx_desc(priv, p, priv->mode); 1945 1946 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1947 } 1948 tx_q->dirty_tx = entry; 1949 1950 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1951 pkts_compl, bytes_compl); 1952 1953 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1954 queue))) && 1955 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1956 1957 netif_dbg(priv, tx_done, priv->dev, 1958 "%s: restart transmit\n", __func__); 1959 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1960 } 1961 1962 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1963 stmmac_enable_eee_mode(priv); 1964 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1965 } 1966 1967 /* We still have pending packets, let's call for a new scheduling */ 1968 if (tx_q->dirty_tx != tx_q->cur_tx) 1969 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 1970 1971 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1972 1973 return count; 1974 } 1975 1976 /** 1977 * stmmac_tx_err - to manage the tx error 1978 * @priv: driver private structure 1979 * @chan: channel index 1980 * Description: it cleans the descriptors and restarts the transmission 1981 * in case of transmission errors. 1982 */ 1983 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 1984 { 1985 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 1986 int i; 1987 1988 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 1989 1990 stmmac_stop_tx_dma(priv, chan); 1991 dma_free_tx_skbufs(priv, chan); 1992 for (i = 0; i < DMA_TX_SIZE; i++) 1993 if (priv->extend_desc) 1994 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1995 priv->mode, (i == DMA_TX_SIZE - 1)); 1996 else 1997 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1998 priv->mode, (i == DMA_TX_SIZE - 1)); 1999 tx_q->dirty_tx = 0; 2000 tx_q->cur_tx = 0; 2001 tx_q->mss = 0; 2002 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2003 stmmac_start_tx_dma(priv, chan); 2004 2005 priv->dev->stats.tx_errors++; 2006 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2007 } 2008 2009 /** 2010 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2011 * @priv: driver private structure 2012 * @txmode: TX operating mode 2013 * @rxmode: RX operating mode 2014 * @chan: channel index 2015 * Description: it is used for configuring of the DMA operation mode in 2016 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2017 * mode. 2018 */ 2019 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2020 u32 rxmode, u32 chan) 2021 { 2022 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2023 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2024 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2025 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2026 int rxfifosz = priv->plat->rx_fifo_size; 2027 int txfifosz = priv->plat->tx_fifo_size; 2028 2029 if (rxfifosz == 0) 2030 rxfifosz = priv->dma_cap.rx_fifo_size; 2031 if (txfifosz == 0) 2032 txfifosz = priv->dma_cap.tx_fifo_size; 2033 2034 /* Adjust for real per queue fifo size */ 2035 rxfifosz /= rx_channels_count; 2036 txfifosz /= tx_channels_count; 2037 2038 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2039 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2040 } 2041 2042 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2043 { 2044 int ret; 2045 2046 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2047 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2048 if (ret && (ret != -EINVAL)) { 2049 stmmac_global_err(priv); 2050 return true; 2051 } 2052 2053 return false; 2054 } 2055 2056 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2057 { 2058 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2059 &priv->xstats, chan); 2060 struct stmmac_channel *ch = &priv->channel[chan]; 2061 2062 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2063 if (napi_schedule_prep(&ch->rx_napi)) { 2064 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2065 __napi_schedule_irqoff(&ch->rx_napi); 2066 status |= handle_tx; 2067 } 2068 } 2069 2070 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) 2071 napi_schedule_irqoff(&ch->tx_napi); 2072 2073 return status; 2074 } 2075 2076 /** 2077 * stmmac_dma_interrupt - DMA ISR 2078 * @priv: driver private structure 2079 * Description: this is the DMA ISR. It is called by the main ISR. 2080 * It calls the dwmac dma routine and schedule poll method in case of some 2081 * work can be done. 2082 */ 2083 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2084 { 2085 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2086 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2087 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2088 tx_channel_count : rx_channel_count; 2089 u32 chan; 2090 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2091 2092 /* Make sure we never check beyond our status buffer. */ 2093 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2094 channels_to_check = ARRAY_SIZE(status); 2095 2096 for (chan = 0; chan < channels_to_check; chan++) 2097 status[chan] = stmmac_napi_check(priv, chan); 2098 2099 for (chan = 0; chan < tx_channel_count; chan++) { 2100 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2101 /* Try to bump up the dma threshold on this failure */ 2102 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2103 (tc <= 256)) { 2104 tc += 64; 2105 if (priv->plat->force_thresh_dma_mode) 2106 stmmac_set_dma_operation_mode(priv, 2107 tc, 2108 tc, 2109 chan); 2110 else 2111 stmmac_set_dma_operation_mode(priv, 2112 tc, 2113 SF_DMA_MODE, 2114 chan); 2115 priv->xstats.threshold = tc; 2116 } 2117 } else if (unlikely(status[chan] == tx_hard_error)) { 2118 stmmac_tx_err(priv, chan); 2119 } 2120 } 2121 } 2122 2123 /** 2124 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2125 * @priv: driver private structure 2126 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2127 */ 2128 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2129 { 2130 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2131 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2132 2133 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2134 2135 if (priv->dma_cap.rmon) { 2136 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2137 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2138 } else 2139 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2140 } 2141 2142 /** 2143 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2144 * @priv: driver private structure 2145 * Description: 2146 * new GMAC chip generations have a new register to indicate the 2147 * presence of the optional feature/functions. 2148 * This can be also used to override the value passed through the 2149 * platform and necessary for old MAC10/100 and GMAC chips. 2150 */ 2151 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2152 { 2153 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2154 } 2155 2156 /** 2157 * stmmac_check_ether_addr - check if the MAC addr is valid 2158 * @priv: driver private structure 2159 * Description: 2160 * it is to verify if the MAC address is valid, in case of failures it 2161 * generates a random MAC address 2162 */ 2163 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2164 { 2165 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2166 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2167 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2168 eth_hw_addr_random(priv->dev); 2169 dev_info(priv->device, "device MAC address %pM\n", 2170 priv->dev->dev_addr); 2171 } 2172 } 2173 2174 /** 2175 * stmmac_init_dma_engine - DMA init. 2176 * @priv: driver private structure 2177 * Description: 2178 * It inits the DMA invoking the specific MAC/GMAC callback. 2179 * Some DMA parameters can be passed from the platform; 2180 * in case of these are not passed a default is kept for the MAC or GMAC. 2181 */ 2182 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2183 { 2184 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2185 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2186 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2187 struct stmmac_rx_queue *rx_q; 2188 struct stmmac_tx_queue *tx_q; 2189 u32 chan = 0; 2190 int atds = 0; 2191 int ret = 0; 2192 2193 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2194 dev_err(priv->device, "Invalid DMA configuration\n"); 2195 return -EINVAL; 2196 } 2197 2198 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2199 atds = 1; 2200 2201 ret = stmmac_reset(priv, priv->ioaddr); 2202 if (ret) { 2203 dev_err(priv->device, "Failed to reset the dma\n"); 2204 return ret; 2205 } 2206 2207 /* DMA Configuration */ 2208 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2209 2210 if (priv->plat->axi) 2211 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2212 2213 /* DMA CSR Channel configuration */ 2214 for (chan = 0; chan < dma_csr_ch; chan++) 2215 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2216 2217 /* DMA RX Channel Configuration */ 2218 for (chan = 0; chan < rx_channels_count; chan++) { 2219 rx_q = &priv->rx_queue[chan]; 2220 2221 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2222 rx_q->dma_rx_phy, chan); 2223 2224 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2225 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2226 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2227 rx_q->rx_tail_addr, chan); 2228 } 2229 2230 /* DMA TX Channel Configuration */ 2231 for (chan = 0; chan < tx_channels_count; chan++) { 2232 tx_q = &priv->tx_queue[chan]; 2233 2234 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2235 tx_q->dma_tx_phy, chan); 2236 2237 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2238 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2239 tx_q->tx_tail_addr, chan); 2240 } 2241 2242 return ret; 2243 } 2244 2245 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2246 { 2247 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2248 2249 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2250 } 2251 2252 /** 2253 * stmmac_tx_timer - mitigation sw timer for tx. 2254 * @data: data pointer 2255 * Description: 2256 * This is the timer handler to directly invoke the stmmac_tx_clean. 2257 */ 2258 static void stmmac_tx_timer(struct timer_list *t) 2259 { 2260 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2261 struct stmmac_priv *priv = tx_q->priv_data; 2262 struct stmmac_channel *ch; 2263 2264 ch = &priv->channel[tx_q->queue_index]; 2265 2266 /* 2267 * If NAPI is already running we can miss some events. Let's rearm 2268 * the timer and try again. 2269 */ 2270 if (likely(napi_schedule_prep(&ch->tx_napi))) 2271 __napi_schedule(&ch->tx_napi); 2272 else 2273 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 2274 } 2275 2276 /** 2277 * stmmac_init_coalesce - init mitigation options. 2278 * @priv: driver private structure 2279 * Description: 2280 * This inits the coalesce parameters: i.e. timer rate, 2281 * timer handler and default threshold used for enabling the 2282 * interrupt on completion bit. 2283 */ 2284 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2285 { 2286 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2287 u32 chan; 2288 2289 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2290 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2291 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2292 2293 for (chan = 0; chan < tx_channel_count; chan++) { 2294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2295 2296 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2297 } 2298 } 2299 2300 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2301 { 2302 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2303 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2304 u32 chan; 2305 2306 /* set TX ring length */ 2307 for (chan = 0; chan < tx_channels_count; chan++) 2308 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2309 (DMA_TX_SIZE - 1), chan); 2310 2311 /* set RX ring length */ 2312 for (chan = 0; chan < rx_channels_count; chan++) 2313 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2314 (DMA_RX_SIZE - 1), chan); 2315 } 2316 2317 /** 2318 * stmmac_set_tx_queue_weight - Set TX queue weight 2319 * @priv: driver private structure 2320 * Description: It is used for setting TX queues weight 2321 */ 2322 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2323 { 2324 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2325 u32 weight; 2326 u32 queue; 2327 2328 for (queue = 0; queue < tx_queues_count; queue++) { 2329 weight = priv->plat->tx_queues_cfg[queue].weight; 2330 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2331 } 2332 } 2333 2334 /** 2335 * stmmac_configure_cbs - Configure CBS in TX queue 2336 * @priv: driver private structure 2337 * Description: It is used for configuring CBS in AVB TX queues 2338 */ 2339 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2340 { 2341 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2342 u32 mode_to_use; 2343 u32 queue; 2344 2345 /* queue 0 is reserved for legacy traffic */ 2346 for (queue = 1; queue < tx_queues_count; queue++) { 2347 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2348 if (mode_to_use == MTL_QUEUE_DCB) 2349 continue; 2350 2351 stmmac_config_cbs(priv, priv->hw, 2352 priv->plat->tx_queues_cfg[queue].send_slope, 2353 priv->plat->tx_queues_cfg[queue].idle_slope, 2354 priv->plat->tx_queues_cfg[queue].high_credit, 2355 priv->plat->tx_queues_cfg[queue].low_credit, 2356 queue); 2357 } 2358 } 2359 2360 /** 2361 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2362 * @priv: driver private structure 2363 * Description: It is used for mapping RX queues to RX dma channels 2364 */ 2365 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2366 { 2367 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2368 u32 queue; 2369 u32 chan; 2370 2371 for (queue = 0; queue < rx_queues_count; queue++) { 2372 chan = priv->plat->rx_queues_cfg[queue].chan; 2373 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2374 } 2375 } 2376 2377 /** 2378 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2379 * @priv: driver private structure 2380 * Description: It is used for configuring the RX Queue Priority 2381 */ 2382 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2383 { 2384 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2385 u32 queue; 2386 u32 prio; 2387 2388 for (queue = 0; queue < rx_queues_count; queue++) { 2389 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2390 continue; 2391 2392 prio = priv->plat->rx_queues_cfg[queue].prio; 2393 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2394 } 2395 } 2396 2397 /** 2398 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2399 * @priv: driver private structure 2400 * Description: It is used for configuring the TX Queue Priority 2401 */ 2402 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2403 { 2404 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2405 u32 queue; 2406 u32 prio; 2407 2408 for (queue = 0; queue < tx_queues_count; queue++) { 2409 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2410 continue; 2411 2412 prio = priv->plat->tx_queues_cfg[queue].prio; 2413 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2414 } 2415 } 2416 2417 /** 2418 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2419 * @priv: driver private structure 2420 * Description: It is used for configuring the RX queue routing 2421 */ 2422 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2423 { 2424 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2425 u32 queue; 2426 u8 packet; 2427 2428 for (queue = 0; queue < rx_queues_count; queue++) { 2429 /* no specific packet type routing specified for the queue */ 2430 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2431 continue; 2432 2433 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2434 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2435 } 2436 } 2437 2438 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2439 { 2440 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2441 priv->rss.enable = false; 2442 return; 2443 } 2444 2445 if (priv->dev->features & NETIF_F_RXHASH) 2446 priv->rss.enable = true; 2447 else 2448 priv->rss.enable = false; 2449 2450 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2451 priv->plat->rx_queues_to_use); 2452 } 2453 2454 /** 2455 * stmmac_mtl_configuration - Configure MTL 2456 * @priv: driver private structure 2457 * Description: It is used for configurring MTL 2458 */ 2459 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2460 { 2461 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2462 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2463 2464 if (tx_queues_count > 1) 2465 stmmac_set_tx_queue_weight(priv); 2466 2467 /* Configure MTL RX algorithms */ 2468 if (rx_queues_count > 1) 2469 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2470 priv->plat->rx_sched_algorithm); 2471 2472 /* Configure MTL TX algorithms */ 2473 if (tx_queues_count > 1) 2474 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2475 priv->plat->tx_sched_algorithm); 2476 2477 /* Configure CBS in AVB TX queues */ 2478 if (tx_queues_count > 1) 2479 stmmac_configure_cbs(priv); 2480 2481 /* Map RX MTL to DMA channels */ 2482 stmmac_rx_queue_dma_chan_map(priv); 2483 2484 /* Enable MAC RX Queues */ 2485 stmmac_mac_enable_rx_queues(priv); 2486 2487 /* Set RX priorities */ 2488 if (rx_queues_count > 1) 2489 stmmac_mac_config_rx_queues_prio(priv); 2490 2491 /* Set TX priorities */ 2492 if (tx_queues_count > 1) 2493 stmmac_mac_config_tx_queues_prio(priv); 2494 2495 /* Set RX routing */ 2496 if (rx_queues_count > 1) 2497 stmmac_mac_config_rx_queues_routing(priv); 2498 2499 /* Receive Side Scaling */ 2500 if (rx_queues_count > 1) 2501 stmmac_mac_config_rss(priv); 2502 } 2503 2504 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2505 { 2506 if (priv->dma_cap.asp) { 2507 netdev_info(priv->dev, "Enabling Safety Features\n"); 2508 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2509 } else { 2510 netdev_info(priv->dev, "No Safety Features support found\n"); 2511 } 2512 } 2513 2514 /** 2515 * stmmac_hw_setup - setup mac in a usable state. 2516 * @dev : pointer to the device structure. 2517 * Description: 2518 * this is the main function to setup the HW in a usable state because the 2519 * dma engine is reset, the core registers are configured (e.g. AXI, 2520 * Checksum features, timers). The DMA is ready to start receiving and 2521 * transmitting. 2522 * Return value: 2523 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2524 * file on failure. 2525 */ 2526 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2527 { 2528 struct stmmac_priv *priv = netdev_priv(dev); 2529 u32 rx_cnt = priv->plat->rx_queues_to_use; 2530 u32 tx_cnt = priv->plat->tx_queues_to_use; 2531 u32 chan; 2532 int ret; 2533 2534 /* DMA initialization and SW reset */ 2535 ret = stmmac_init_dma_engine(priv); 2536 if (ret < 0) { 2537 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2538 __func__); 2539 return ret; 2540 } 2541 2542 /* Copy the MAC addr into the HW */ 2543 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2544 2545 /* PS and related bits will be programmed according to the speed */ 2546 if (priv->hw->pcs) { 2547 int speed = priv->plat->mac_port_sel_speed; 2548 2549 if ((speed == SPEED_10) || (speed == SPEED_100) || 2550 (speed == SPEED_1000)) { 2551 priv->hw->ps = speed; 2552 } else { 2553 dev_warn(priv->device, "invalid port speed\n"); 2554 priv->hw->ps = 0; 2555 } 2556 } 2557 2558 /* Initialize the MAC Core */ 2559 stmmac_core_init(priv, priv->hw, dev); 2560 2561 /* Initialize MTL*/ 2562 stmmac_mtl_configuration(priv); 2563 2564 /* Initialize Safety Features */ 2565 stmmac_safety_feat_configuration(priv); 2566 2567 ret = stmmac_rx_ipc(priv, priv->hw); 2568 if (!ret) { 2569 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2570 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2571 priv->hw->rx_csum = 0; 2572 } 2573 2574 /* Enable the MAC Rx/Tx */ 2575 stmmac_mac_set(priv, priv->ioaddr, true); 2576 2577 /* Set the HW DMA mode and the COE */ 2578 stmmac_dma_operation_mode(priv); 2579 2580 stmmac_mmc_setup(priv); 2581 2582 if (init_ptp) { 2583 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2584 if (ret < 0) 2585 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2586 2587 ret = stmmac_init_ptp(priv); 2588 if (ret == -EOPNOTSUPP) 2589 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2590 else if (ret) 2591 netdev_warn(priv->dev, "PTP init failed\n"); 2592 } 2593 2594 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2595 2596 if (priv->use_riwt) { 2597 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt); 2598 if (!ret) 2599 priv->rx_riwt = MIN_DMA_RIWT; 2600 } 2601 2602 if (priv->hw->pcs) 2603 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0); 2604 2605 /* set TX and RX rings length */ 2606 stmmac_set_rings_length(priv); 2607 2608 /* Enable TSO */ 2609 if (priv->tso) { 2610 for (chan = 0; chan < tx_cnt; chan++) 2611 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2612 } 2613 2614 /* Enable Split Header */ 2615 if (priv->sph && priv->hw->rx_csum) { 2616 for (chan = 0; chan < rx_cnt; chan++) 2617 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2618 } 2619 2620 /* VLAN Tag Insertion */ 2621 if (priv->dma_cap.vlins) 2622 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2623 2624 /* Start the ball rolling... */ 2625 stmmac_start_all_dma(priv); 2626 2627 return 0; 2628 } 2629 2630 static void stmmac_hw_teardown(struct net_device *dev) 2631 { 2632 struct stmmac_priv *priv = netdev_priv(dev); 2633 2634 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2635 } 2636 2637 /** 2638 * stmmac_open - open entry point of the driver 2639 * @dev : pointer to the device structure. 2640 * Description: 2641 * This function is the open entry point of the driver. 2642 * Return value: 2643 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2644 * file on failure. 2645 */ 2646 static int stmmac_open(struct net_device *dev) 2647 { 2648 struct stmmac_priv *priv = netdev_priv(dev); 2649 u32 chan; 2650 int ret; 2651 2652 if (priv->hw->pcs != STMMAC_PCS_RGMII && 2653 priv->hw->pcs != STMMAC_PCS_TBI && 2654 priv->hw->pcs != STMMAC_PCS_RTBI) { 2655 ret = stmmac_init_phy(dev); 2656 if (ret) { 2657 netdev_err(priv->dev, 2658 "%s: Cannot attach to PHY (error: %d)\n", 2659 __func__, ret); 2660 return ret; 2661 } 2662 } 2663 2664 /* Extra statistics */ 2665 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2666 priv->xstats.threshold = tc; 2667 2668 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 2669 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2670 2671 ret = alloc_dma_desc_resources(priv); 2672 if (ret < 0) { 2673 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2674 __func__); 2675 goto dma_desc_error; 2676 } 2677 2678 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2679 if (ret < 0) { 2680 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2681 __func__); 2682 goto init_error; 2683 } 2684 2685 ret = stmmac_hw_setup(dev, true); 2686 if (ret < 0) { 2687 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2688 goto init_error; 2689 } 2690 2691 stmmac_init_coalesce(priv); 2692 2693 phylink_start(priv->phylink); 2694 2695 /* Request the IRQ lines */ 2696 ret = request_irq(dev->irq, stmmac_interrupt, 2697 IRQF_SHARED, dev->name, dev); 2698 if (unlikely(ret < 0)) { 2699 netdev_err(priv->dev, 2700 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2701 __func__, dev->irq, ret); 2702 goto irq_error; 2703 } 2704 2705 /* Request the Wake IRQ in case of another line is used for WoL */ 2706 if (priv->wol_irq != dev->irq) { 2707 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2708 IRQF_SHARED, dev->name, dev); 2709 if (unlikely(ret < 0)) { 2710 netdev_err(priv->dev, 2711 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2712 __func__, priv->wol_irq, ret); 2713 goto wolirq_error; 2714 } 2715 } 2716 2717 /* Request the IRQ lines */ 2718 if (priv->lpi_irq > 0) { 2719 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2720 dev->name, dev); 2721 if (unlikely(ret < 0)) { 2722 netdev_err(priv->dev, 2723 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2724 __func__, priv->lpi_irq, ret); 2725 goto lpiirq_error; 2726 } 2727 } 2728 2729 stmmac_enable_all_queues(priv); 2730 stmmac_start_all_queues(priv); 2731 2732 return 0; 2733 2734 lpiirq_error: 2735 if (priv->wol_irq != dev->irq) 2736 free_irq(priv->wol_irq, dev); 2737 wolirq_error: 2738 free_irq(dev->irq, dev); 2739 irq_error: 2740 phylink_stop(priv->phylink); 2741 2742 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2743 del_timer_sync(&priv->tx_queue[chan].txtimer); 2744 2745 stmmac_hw_teardown(dev); 2746 init_error: 2747 free_dma_desc_resources(priv); 2748 dma_desc_error: 2749 phylink_disconnect_phy(priv->phylink); 2750 return ret; 2751 } 2752 2753 /** 2754 * stmmac_release - close entry point of the driver 2755 * @dev : device pointer. 2756 * Description: 2757 * This is the stop entry point of the driver. 2758 */ 2759 static int stmmac_release(struct net_device *dev) 2760 { 2761 struct stmmac_priv *priv = netdev_priv(dev); 2762 u32 chan; 2763 2764 if (priv->eee_enabled) 2765 del_timer_sync(&priv->eee_ctrl_timer); 2766 2767 /* Stop and disconnect the PHY */ 2768 phylink_stop(priv->phylink); 2769 phylink_disconnect_phy(priv->phylink); 2770 2771 stmmac_stop_all_queues(priv); 2772 2773 stmmac_disable_all_queues(priv); 2774 2775 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2776 del_timer_sync(&priv->tx_queue[chan].txtimer); 2777 2778 /* Free the IRQ lines */ 2779 free_irq(dev->irq, dev); 2780 if (priv->wol_irq != dev->irq) 2781 free_irq(priv->wol_irq, dev); 2782 if (priv->lpi_irq > 0) 2783 free_irq(priv->lpi_irq, dev); 2784 2785 /* Stop TX/RX DMA and clear the descriptors */ 2786 stmmac_stop_all_dma(priv); 2787 2788 /* Release and free the Rx/Tx resources */ 2789 free_dma_desc_resources(priv); 2790 2791 /* Disable the MAC Rx/Tx */ 2792 stmmac_mac_set(priv, priv->ioaddr, false); 2793 2794 netif_carrier_off(dev); 2795 2796 stmmac_release_ptp(priv); 2797 2798 return 0; 2799 } 2800 2801 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2802 struct stmmac_tx_queue *tx_q) 2803 { 2804 u16 tag = 0x0, inner_tag = 0x0; 2805 u32 inner_type = 0x0; 2806 struct dma_desc *p; 2807 2808 if (!priv->dma_cap.vlins) 2809 return false; 2810 if (!skb_vlan_tag_present(skb)) 2811 return false; 2812 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2813 inner_tag = skb_vlan_tag_get(skb); 2814 inner_type = STMMAC_VLAN_INSERT; 2815 } 2816 2817 tag = skb_vlan_tag_get(skb); 2818 2819 p = tx_q->dma_tx + tx_q->cur_tx; 2820 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2821 return false; 2822 2823 stmmac_set_tx_owner(priv, p); 2824 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2825 return true; 2826 } 2827 2828 /** 2829 * stmmac_tso_allocator - close entry point of the driver 2830 * @priv: driver private structure 2831 * @des: buffer start address 2832 * @total_len: total length to fill in descriptors 2833 * @last_segmant: condition for the last descriptor 2834 * @queue: TX queue index 2835 * Description: 2836 * This function fills descriptor and request new descriptors according to 2837 * buffer length to fill 2838 */ 2839 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2840 int total_len, bool last_segment, u32 queue) 2841 { 2842 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2843 struct dma_desc *desc; 2844 u32 buff_size; 2845 int tmp_len; 2846 2847 tmp_len = total_len; 2848 2849 while (tmp_len > 0) { 2850 dma_addr_t curr_addr; 2851 2852 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2853 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2854 desc = tx_q->dma_tx + tx_q->cur_tx; 2855 2856 curr_addr = des + (total_len - tmp_len); 2857 if (priv->dma_cap.addr64 <= 32) 2858 desc->des0 = cpu_to_le32(curr_addr); 2859 else 2860 stmmac_set_desc_addr(priv, desc, curr_addr); 2861 2862 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2863 TSO_MAX_BUFF_SIZE : tmp_len; 2864 2865 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2866 0, 1, 2867 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2868 0, 0); 2869 2870 tmp_len -= TSO_MAX_BUFF_SIZE; 2871 } 2872 } 2873 2874 /** 2875 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2876 * @skb : the socket buffer 2877 * @dev : device pointer 2878 * Description: this is the transmit function that is called on TSO frames 2879 * (support available on GMAC4 and newer chips). 2880 * Diagram below show the ring programming in case of TSO frames: 2881 * 2882 * First Descriptor 2883 * -------- 2884 * | DES0 |---> buffer1 = L2/L3/L4 header 2885 * | DES1 |---> TCP Payload (can continue on next descr...) 2886 * | DES2 |---> buffer 1 and 2 len 2887 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2888 * -------- 2889 * | 2890 * ... 2891 * | 2892 * -------- 2893 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2894 * | DES1 | --| 2895 * | DES2 | --> buffer 1 and 2 len 2896 * | DES3 | 2897 * -------- 2898 * 2899 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2900 */ 2901 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2902 { 2903 struct dma_desc *desc, *first, *mss_desc = NULL; 2904 struct stmmac_priv *priv = netdev_priv(dev); 2905 int nfrags = skb_shinfo(skb)->nr_frags; 2906 u32 queue = skb_get_queue_mapping(skb); 2907 struct stmmac_tx_queue *tx_q; 2908 unsigned int first_entry; 2909 int tmp_pay_len = 0; 2910 u32 pay_len, mss; 2911 u8 proto_hdr_len; 2912 dma_addr_t des; 2913 bool has_vlan; 2914 int i; 2915 2916 tx_q = &priv->tx_queue[queue]; 2917 2918 /* Compute header lengths */ 2919 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2920 2921 /* Desc availability based on threshold should be enough safe */ 2922 if (unlikely(stmmac_tx_avail(priv, queue) < 2923 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2924 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2925 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2926 queue)); 2927 /* This is a hard error, log it. */ 2928 netdev_err(priv->dev, 2929 "%s: Tx Ring full when queue awake\n", 2930 __func__); 2931 } 2932 return NETDEV_TX_BUSY; 2933 } 2934 2935 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2936 2937 mss = skb_shinfo(skb)->gso_size; 2938 2939 /* set new MSS value if needed */ 2940 if (mss != tx_q->mss) { 2941 mss_desc = tx_q->dma_tx + tx_q->cur_tx; 2942 stmmac_set_mss(priv, mss_desc, mss); 2943 tx_q->mss = mss; 2944 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2945 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2946 } 2947 2948 if (netif_msg_tx_queued(priv)) { 2949 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2950 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2951 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2952 skb->data_len); 2953 } 2954 2955 /* Check if VLAN can be inserted by HW */ 2956 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 2957 2958 first_entry = tx_q->cur_tx; 2959 WARN_ON(tx_q->tx_skbuff[first_entry]); 2960 2961 desc = tx_q->dma_tx + first_entry; 2962 first = desc; 2963 2964 if (has_vlan) 2965 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 2966 2967 /* first descriptor: fill Headers on Buf1 */ 2968 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2969 DMA_TO_DEVICE); 2970 if (dma_mapping_error(priv->device, des)) 2971 goto dma_map_err; 2972 2973 tx_q->tx_skbuff_dma[first_entry].buf = des; 2974 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2975 2976 if (priv->dma_cap.addr64 <= 32) { 2977 first->des0 = cpu_to_le32(des); 2978 2979 /* Fill start of payload in buff2 of first descriptor */ 2980 if (pay_len) 2981 first->des1 = cpu_to_le32(des + proto_hdr_len); 2982 2983 /* If needed take extra descriptors to fill the remaining payload */ 2984 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2985 } else { 2986 stmmac_set_desc_addr(priv, first, des); 2987 tmp_pay_len = pay_len; 2988 } 2989 2990 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 2991 2992 /* Prepare fragments */ 2993 for (i = 0; i < nfrags; i++) { 2994 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2995 2996 des = skb_frag_dma_map(priv->device, frag, 0, 2997 skb_frag_size(frag), 2998 DMA_TO_DEVICE); 2999 if (dma_mapping_error(priv->device, des)) 3000 goto dma_map_err; 3001 3002 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3003 (i == nfrags - 1), queue); 3004 3005 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3006 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3007 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3008 } 3009 3010 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3011 3012 /* Only the last descriptor gets to point to the skb. */ 3013 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3014 3015 /* We've used all descriptors we need for this skb, however, 3016 * advance cur_tx so that it references a fresh descriptor. 3017 * ndo_start_xmit will fill this descriptor the next time it's 3018 * called and stmmac_tx_clean may clean up to this descriptor. 3019 */ 3020 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3021 3022 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3023 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3024 __func__); 3025 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3026 } 3027 3028 dev->stats.tx_bytes += skb->len; 3029 priv->xstats.tx_tso_frames++; 3030 priv->xstats.tx_tso_nfrags += nfrags; 3031 3032 /* Manage tx mitigation */ 3033 tx_q->tx_count_frames += nfrags + 1; 3034 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3035 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 3036 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3037 priv->hwts_tx_en)) { 3038 stmmac_tx_timer_arm(priv, queue); 3039 } else { 3040 tx_q->tx_count_frames = 0; 3041 stmmac_set_tx_ic(priv, desc); 3042 priv->xstats.tx_set_ic_bit++; 3043 } 3044 3045 if (priv->sarc_type) 3046 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3047 3048 skb_tx_timestamp(skb); 3049 3050 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3051 priv->hwts_tx_en)) { 3052 /* declare that device is doing timestamping */ 3053 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3054 stmmac_enable_tx_timestamp(priv, first); 3055 } 3056 3057 /* Complete the first descriptor before granting the DMA */ 3058 stmmac_prepare_tso_tx_desc(priv, first, 1, 3059 proto_hdr_len, 3060 pay_len, 3061 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3062 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 3063 3064 /* If context desc is used to change MSS */ 3065 if (mss_desc) { 3066 /* Make sure that first descriptor has been completely 3067 * written, including its own bit. This is because MSS is 3068 * actually before first descriptor, so we need to make 3069 * sure that MSS's own bit is the last thing written. 3070 */ 3071 dma_wmb(); 3072 stmmac_set_tx_owner(priv, mss_desc); 3073 } 3074 3075 /* The own bit must be the latest setting done when prepare the 3076 * descriptor and then barrier is needed to make sure that 3077 * all is coherent before granting the DMA engine. 3078 */ 3079 wmb(); 3080 3081 if (netif_msg_pktdata(priv)) { 3082 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3083 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3084 tx_q->cur_tx, first, nfrags); 3085 3086 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0); 3087 3088 pr_info(">>> frame to be transmitted: "); 3089 print_pkt(skb->data, skb_headlen(skb)); 3090 } 3091 3092 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3093 3094 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3095 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3096 3097 return NETDEV_TX_OK; 3098 3099 dma_map_err: 3100 dev_err(priv->device, "Tx dma map failed\n"); 3101 dev_kfree_skb(skb); 3102 priv->dev->stats.tx_dropped++; 3103 return NETDEV_TX_OK; 3104 } 3105 3106 /** 3107 * stmmac_xmit - Tx entry point of the driver 3108 * @skb : the socket buffer 3109 * @dev : device pointer 3110 * Description : this is the tx entry point of the driver. 3111 * It programs the chain or the ring and supports oversized frames 3112 * and SG feature. 3113 */ 3114 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3115 { 3116 struct stmmac_priv *priv = netdev_priv(dev); 3117 unsigned int nopaged_len = skb_headlen(skb); 3118 int i, csum_insertion = 0, is_jumbo = 0; 3119 u32 queue = skb_get_queue_mapping(skb); 3120 int nfrags = skb_shinfo(skb)->nr_frags; 3121 struct dma_desc *desc, *first; 3122 struct stmmac_tx_queue *tx_q; 3123 unsigned int first_entry; 3124 unsigned int enh_desc; 3125 dma_addr_t des; 3126 bool has_vlan; 3127 int entry; 3128 3129 tx_q = &priv->tx_queue[queue]; 3130 3131 if (priv->tx_path_in_lpi_mode) 3132 stmmac_disable_eee_mode(priv); 3133 3134 /* Manage oversized TCP frames for GMAC4 device */ 3135 if (skb_is_gso(skb) && priv->tso) { 3136 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3137 return stmmac_tso_xmit(skb, dev); 3138 } 3139 3140 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3141 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3142 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3143 queue)); 3144 /* This is a hard error, log it. */ 3145 netdev_err(priv->dev, 3146 "%s: Tx Ring full when queue awake\n", 3147 __func__); 3148 } 3149 return NETDEV_TX_BUSY; 3150 } 3151 3152 /* Check if VLAN can be inserted by HW */ 3153 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3154 3155 entry = tx_q->cur_tx; 3156 first_entry = entry; 3157 WARN_ON(tx_q->tx_skbuff[first_entry]); 3158 3159 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3160 3161 if (likely(priv->extend_desc)) 3162 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3163 else 3164 desc = tx_q->dma_tx + entry; 3165 3166 first = desc; 3167 3168 if (has_vlan) 3169 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3170 3171 enh_desc = priv->plat->enh_desc; 3172 /* To program the descriptors according to the size of the frame */ 3173 if (enh_desc) 3174 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3175 3176 if (unlikely(is_jumbo)) { 3177 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3178 if (unlikely(entry < 0) && (entry != -EINVAL)) 3179 goto dma_map_err; 3180 } 3181 3182 for (i = 0; i < nfrags; i++) { 3183 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3184 int len = skb_frag_size(frag); 3185 bool last_segment = (i == (nfrags - 1)); 3186 3187 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3188 WARN_ON(tx_q->tx_skbuff[entry]); 3189 3190 if (likely(priv->extend_desc)) 3191 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3192 else 3193 desc = tx_q->dma_tx + entry; 3194 3195 des = skb_frag_dma_map(priv->device, frag, 0, len, 3196 DMA_TO_DEVICE); 3197 if (dma_mapping_error(priv->device, des)) 3198 goto dma_map_err; /* should reuse desc w/o issues */ 3199 3200 tx_q->tx_skbuff_dma[entry].buf = des; 3201 3202 stmmac_set_desc_addr(priv, desc, des); 3203 3204 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3205 tx_q->tx_skbuff_dma[entry].len = len; 3206 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3207 3208 /* Prepare the descriptor and set the own bit too */ 3209 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3210 priv->mode, 1, last_segment, skb->len); 3211 } 3212 3213 /* Only the last descriptor gets to point to the skb. */ 3214 tx_q->tx_skbuff[entry] = skb; 3215 3216 /* We've used all descriptors we need for this skb, however, 3217 * advance cur_tx so that it references a fresh descriptor. 3218 * ndo_start_xmit will fill this descriptor the next time it's 3219 * called and stmmac_tx_clean may clean up to this descriptor. 3220 */ 3221 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3222 tx_q->cur_tx = entry; 3223 3224 if (netif_msg_pktdata(priv)) { 3225 void *tx_head; 3226 3227 netdev_dbg(priv->dev, 3228 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3229 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3230 entry, first, nfrags); 3231 3232 if (priv->extend_desc) 3233 tx_head = (void *)tx_q->dma_etx; 3234 else 3235 tx_head = (void *)tx_q->dma_tx; 3236 3237 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false); 3238 3239 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3240 print_pkt(skb->data, skb->len); 3241 } 3242 3243 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3244 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3245 __func__); 3246 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3247 } 3248 3249 dev->stats.tx_bytes += skb->len; 3250 3251 /* According to the coalesce parameter the IC bit for the latest 3252 * segment is reset and the timer re-started to clean the tx status. 3253 * This approach takes care about the fragments: desc is the first 3254 * element in case of no SG. 3255 */ 3256 tx_q->tx_count_frames += nfrags + 1; 3257 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3258 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 3259 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3260 priv->hwts_tx_en)) { 3261 stmmac_tx_timer_arm(priv, queue); 3262 } else { 3263 tx_q->tx_count_frames = 0; 3264 stmmac_set_tx_ic(priv, desc); 3265 priv->xstats.tx_set_ic_bit++; 3266 } 3267 3268 if (priv->sarc_type) 3269 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3270 3271 skb_tx_timestamp(skb); 3272 3273 /* Ready to fill the first descriptor and set the OWN bit w/o any 3274 * problems because all the descriptors are actually ready to be 3275 * passed to the DMA engine. 3276 */ 3277 if (likely(!is_jumbo)) { 3278 bool last_segment = (nfrags == 0); 3279 3280 des = dma_map_single(priv->device, skb->data, 3281 nopaged_len, DMA_TO_DEVICE); 3282 if (dma_mapping_error(priv->device, des)) 3283 goto dma_map_err; 3284 3285 tx_q->tx_skbuff_dma[first_entry].buf = des; 3286 3287 stmmac_set_desc_addr(priv, first, des); 3288 3289 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3290 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3291 3292 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3293 priv->hwts_tx_en)) { 3294 /* declare that device is doing timestamping */ 3295 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3296 stmmac_enable_tx_timestamp(priv, first); 3297 } 3298 3299 /* Prepare the first descriptor setting the OWN bit too */ 3300 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3301 csum_insertion, priv->mode, 1, last_segment, 3302 skb->len); 3303 } else { 3304 stmmac_set_tx_owner(priv, first); 3305 } 3306 3307 /* The own bit must be the latest setting done when prepare the 3308 * descriptor and then barrier is needed to make sure that 3309 * all is coherent before granting the DMA engine. 3310 */ 3311 wmb(); 3312 3313 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3314 3315 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3316 3317 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3318 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3319 3320 return NETDEV_TX_OK; 3321 3322 dma_map_err: 3323 netdev_err(priv->dev, "Tx DMA map failed\n"); 3324 dev_kfree_skb(skb); 3325 priv->dev->stats.tx_dropped++; 3326 return NETDEV_TX_OK; 3327 } 3328 3329 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3330 { 3331 struct vlan_ethhdr *veth; 3332 __be16 vlan_proto; 3333 u16 vlanid; 3334 3335 veth = (struct vlan_ethhdr *)skb->data; 3336 vlan_proto = veth->h_vlan_proto; 3337 3338 if ((vlan_proto == htons(ETH_P_8021Q) && 3339 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3340 (vlan_proto == htons(ETH_P_8021AD) && 3341 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3342 /* pop the vlan tag */ 3343 vlanid = ntohs(veth->h_vlan_TCI); 3344 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3345 skb_pull(skb, VLAN_HLEN); 3346 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3347 } 3348 } 3349 3350 3351 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3352 { 3353 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3354 return 0; 3355 3356 return 1; 3357 } 3358 3359 /** 3360 * stmmac_rx_refill - refill used skb preallocated buffers 3361 * @priv: driver private structure 3362 * @queue: RX queue index 3363 * Description : this is to reallocate the skb for the reception process 3364 * that is based on zero-copy. 3365 */ 3366 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3367 { 3368 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3369 int len, dirty = stmmac_rx_dirty(priv, queue); 3370 unsigned int entry = rx_q->dirty_rx; 3371 3372 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3373 3374 while (dirty-- > 0) { 3375 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3376 struct dma_desc *p; 3377 bool use_rx_wd; 3378 3379 if (priv->extend_desc) 3380 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3381 else 3382 p = rx_q->dma_rx + entry; 3383 3384 if (!buf->page) { 3385 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3386 if (!buf->page) 3387 break; 3388 } 3389 3390 if (priv->sph && !buf->sec_page) { 3391 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3392 if (!buf->sec_page) 3393 break; 3394 3395 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3396 3397 dma_sync_single_for_device(priv->device, buf->sec_addr, 3398 len, DMA_FROM_DEVICE); 3399 } 3400 3401 buf->addr = page_pool_get_dma_addr(buf->page); 3402 3403 /* Sync whole allocation to device. This will invalidate old 3404 * data. 3405 */ 3406 dma_sync_single_for_device(priv->device, buf->addr, len, 3407 DMA_FROM_DEVICE); 3408 3409 stmmac_set_desc_addr(priv, p, buf->addr); 3410 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3411 stmmac_refill_desc3(priv, rx_q, p); 3412 3413 rx_q->rx_count_frames++; 3414 rx_q->rx_count_frames %= priv->rx_coal_frames; 3415 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames; 3416 3417 dma_wmb(); 3418 stmmac_set_rx_owner(priv, p, use_rx_wd); 3419 3420 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3421 } 3422 rx_q->dirty_rx = entry; 3423 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3424 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3425 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3426 } 3427 3428 /** 3429 * stmmac_rx - manage the receive process 3430 * @priv: driver private structure 3431 * @limit: napi bugget 3432 * @queue: RX queue index. 3433 * Description : this the function called by the napi poll method. 3434 * It gets all the frames inside the ring. 3435 */ 3436 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3437 { 3438 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3439 struct stmmac_channel *ch = &priv->channel[queue]; 3440 unsigned int count = 0, error = 0, len = 0; 3441 int status = 0, coe = priv->hw->rx_csum; 3442 unsigned int next_entry = rx_q->cur_rx; 3443 struct sk_buff *skb = NULL; 3444 3445 if (netif_msg_rx_status(priv)) { 3446 void *rx_head; 3447 3448 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3449 if (priv->extend_desc) 3450 rx_head = (void *)rx_q->dma_erx; 3451 else 3452 rx_head = (void *)rx_q->dma_rx; 3453 3454 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3455 } 3456 while (count < limit) { 3457 unsigned int hlen = 0, prev_len = 0; 3458 enum pkt_hash_types hash_type; 3459 struct stmmac_rx_buffer *buf; 3460 struct dma_desc *np, *p; 3461 unsigned int sec_len; 3462 int entry; 3463 u32 hash; 3464 3465 if (!count && rx_q->state_saved) { 3466 skb = rx_q->state.skb; 3467 error = rx_q->state.error; 3468 len = rx_q->state.len; 3469 } else { 3470 rx_q->state_saved = false; 3471 skb = NULL; 3472 error = 0; 3473 len = 0; 3474 } 3475 3476 if (count >= limit) 3477 break; 3478 3479 read_again: 3480 sec_len = 0; 3481 entry = next_entry; 3482 buf = &rx_q->buf_pool[entry]; 3483 3484 if (priv->extend_desc) 3485 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3486 else 3487 p = rx_q->dma_rx + entry; 3488 3489 /* read the status of the incoming frame */ 3490 status = stmmac_rx_status(priv, &priv->dev->stats, 3491 &priv->xstats, p); 3492 /* check if managed by the DMA otherwise go ahead */ 3493 if (unlikely(status & dma_own)) 3494 break; 3495 3496 count++; 3497 3498 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3499 next_entry = rx_q->cur_rx; 3500 3501 if (priv->extend_desc) 3502 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3503 else 3504 np = rx_q->dma_rx + next_entry; 3505 3506 prefetch(np); 3507 prefetch(page_address(buf->page)); 3508 3509 if (priv->extend_desc) 3510 stmmac_rx_extended_status(priv, &priv->dev->stats, 3511 &priv->xstats, rx_q->dma_erx + entry); 3512 if (unlikely(status == discard_frame)) { 3513 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3514 priv->dev->stats.rx_errors++; 3515 buf->page = NULL; 3516 error = 1; 3517 } 3518 3519 if (unlikely(error && (status & rx_not_ls))) 3520 goto read_again; 3521 if (unlikely(error)) { 3522 dev_kfree_skb(skb); 3523 continue; 3524 } 3525 3526 /* Buffer is good. Go on. */ 3527 3528 if (likely(status & rx_not_ls)) { 3529 len += priv->dma_buf_sz; 3530 } else { 3531 prev_len = len; 3532 len = stmmac_get_rx_frame_len(priv, p, coe); 3533 3534 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3535 * Type frames (LLC/LLC-SNAP) 3536 * 3537 * llc_snap is never checked in GMAC >= 4, so this ACS 3538 * feature is always disabled and packets need to be 3539 * stripped manually. 3540 */ 3541 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3542 unlikely(status != llc_snap)) 3543 len -= ETH_FCS_LEN; 3544 } 3545 3546 if (!skb) { 3547 int ret = stmmac_get_rx_header_len(priv, p, &hlen); 3548 3549 if (priv->sph && !ret && (hlen > 0)) { 3550 sec_len = len; 3551 if (!(status & rx_not_ls)) 3552 sec_len = sec_len - hlen; 3553 len = hlen; 3554 3555 prefetch(page_address(buf->sec_page)); 3556 priv->xstats.rx_split_hdr_pkt_n++; 3557 } 3558 3559 skb = napi_alloc_skb(&ch->rx_napi, len); 3560 if (!skb) { 3561 priv->dev->stats.rx_dropped++; 3562 continue; 3563 } 3564 3565 dma_sync_single_for_cpu(priv->device, buf->addr, len, 3566 DMA_FROM_DEVICE); 3567 skb_copy_to_linear_data(skb, page_address(buf->page), 3568 len); 3569 skb_put(skb, len); 3570 3571 /* Data payload copied into SKB, page ready for recycle */ 3572 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3573 buf->page = NULL; 3574 } else { 3575 unsigned int buf_len = len - prev_len; 3576 3577 if (likely(status & rx_not_ls)) 3578 buf_len = priv->dma_buf_sz; 3579 3580 dma_sync_single_for_cpu(priv->device, buf->addr, 3581 buf_len, DMA_FROM_DEVICE); 3582 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3583 buf->page, 0, buf_len, 3584 priv->dma_buf_sz); 3585 3586 /* Data payload appended into SKB */ 3587 page_pool_release_page(rx_q->page_pool, buf->page); 3588 buf->page = NULL; 3589 } 3590 3591 if (sec_len > 0) { 3592 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3593 sec_len, DMA_FROM_DEVICE); 3594 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3595 buf->sec_page, 0, sec_len, 3596 priv->dma_buf_sz); 3597 3598 len += sec_len; 3599 3600 /* Data payload appended into SKB */ 3601 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3602 buf->sec_page = NULL; 3603 } 3604 3605 if (likely(status & rx_not_ls)) 3606 goto read_again; 3607 3608 /* Got entire packet into SKB. Finish it. */ 3609 3610 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3611 stmmac_rx_vlan(priv->dev, skb); 3612 skb->protocol = eth_type_trans(skb, priv->dev); 3613 3614 if (unlikely(!coe)) 3615 skb_checksum_none_assert(skb); 3616 else 3617 skb->ip_summed = CHECKSUM_UNNECESSARY; 3618 3619 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3620 skb_set_hash(skb, hash, hash_type); 3621 3622 skb_record_rx_queue(skb, queue); 3623 napi_gro_receive(&ch->rx_napi, skb); 3624 3625 priv->dev->stats.rx_packets++; 3626 priv->dev->stats.rx_bytes += len; 3627 } 3628 3629 if (status & rx_not_ls) { 3630 rx_q->state_saved = true; 3631 rx_q->state.skb = skb; 3632 rx_q->state.error = error; 3633 rx_q->state.len = len; 3634 } 3635 3636 stmmac_rx_refill(priv, queue); 3637 3638 priv->xstats.rx_pkt_n += count; 3639 3640 return count; 3641 } 3642 3643 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3644 { 3645 struct stmmac_channel *ch = 3646 container_of(napi, struct stmmac_channel, rx_napi); 3647 struct stmmac_priv *priv = ch->priv_data; 3648 u32 chan = ch->index; 3649 int work_done; 3650 3651 priv->xstats.napi_poll++; 3652 3653 work_done = stmmac_rx(priv, budget, chan); 3654 if (work_done < budget && napi_complete_done(napi, work_done)) 3655 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3656 return work_done; 3657 } 3658 3659 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3660 { 3661 struct stmmac_channel *ch = 3662 container_of(napi, struct stmmac_channel, tx_napi); 3663 struct stmmac_priv *priv = ch->priv_data; 3664 struct stmmac_tx_queue *tx_q; 3665 u32 chan = ch->index; 3666 int work_done; 3667 3668 priv->xstats.napi_poll++; 3669 3670 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3671 work_done = min(work_done, budget); 3672 3673 if (work_done < budget) 3674 napi_complete_done(napi, work_done); 3675 3676 /* Force transmission restart */ 3677 tx_q = &priv->tx_queue[chan]; 3678 if (tx_q->cur_tx != tx_q->dirty_tx) { 3679 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3680 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, 3681 chan); 3682 } 3683 3684 return work_done; 3685 } 3686 3687 /** 3688 * stmmac_tx_timeout 3689 * @dev : Pointer to net device structure 3690 * Description: this function is called when a packet transmission fails to 3691 * complete within a reasonable time. The driver will mark the error in the 3692 * netdev structure and arrange for the device to be reset to a sane state 3693 * in order to transmit a new packet. 3694 */ 3695 static void stmmac_tx_timeout(struct net_device *dev) 3696 { 3697 struct stmmac_priv *priv = netdev_priv(dev); 3698 3699 stmmac_global_err(priv); 3700 } 3701 3702 /** 3703 * stmmac_set_rx_mode - entry point for multicast addressing 3704 * @dev : pointer to the device structure 3705 * Description: 3706 * This function is a driver entry point which gets called by the kernel 3707 * whenever multicast addresses must be enabled/disabled. 3708 * Return value: 3709 * void. 3710 */ 3711 static void stmmac_set_rx_mode(struct net_device *dev) 3712 { 3713 struct stmmac_priv *priv = netdev_priv(dev); 3714 3715 stmmac_set_filter(priv, priv->hw, dev); 3716 } 3717 3718 /** 3719 * stmmac_change_mtu - entry point to change MTU size for the device. 3720 * @dev : device pointer. 3721 * @new_mtu : the new MTU size for the device. 3722 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3723 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3724 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3725 * Return value: 3726 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3727 * file on failure. 3728 */ 3729 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3730 { 3731 struct stmmac_priv *priv = netdev_priv(dev); 3732 3733 if (netif_running(dev)) { 3734 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3735 return -EBUSY; 3736 } 3737 3738 dev->mtu = new_mtu; 3739 3740 netdev_update_features(dev); 3741 3742 return 0; 3743 } 3744 3745 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3746 netdev_features_t features) 3747 { 3748 struct stmmac_priv *priv = netdev_priv(dev); 3749 3750 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3751 features &= ~NETIF_F_RXCSUM; 3752 3753 if (!priv->plat->tx_coe) 3754 features &= ~NETIF_F_CSUM_MASK; 3755 3756 /* Some GMAC devices have a bugged Jumbo frame support that 3757 * needs to have the Tx COE disabled for oversized frames 3758 * (due to limited buffer sizes). In this case we disable 3759 * the TX csum insertion in the TDES and not use SF. 3760 */ 3761 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3762 features &= ~NETIF_F_CSUM_MASK; 3763 3764 /* Disable tso if asked by ethtool */ 3765 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3766 if (features & NETIF_F_TSO) 3767 priv->tso = true; 3768 else 3769 priv->tso = false; 3770 } 3771 3772 return features; 3773 } 3774 3775 static int stmmac_set_features(struct net_device *netdev, 3776 netdev_features_t features) 3777 { 3778 struct stmmac_priv *priv = netdev_priv(netdev); 3779 bool sph_en; 3780 u32 chan; 3781 3782 /* Keep the COE Type in case of csum is supporting */ 3783 if (features & NETIF_F_RXCSUM) 3784 priv->hw->rx_csum = priv->plat->rx_coe; 3785 else 3786 priv->hw->rx_csum = 0; 3787 /* No check needed because rx_coe has been set before and it will be 3788 * fixed in case of issue. 3789 */ 3790 stmmac_rx_ipc(priv, priv->hw); 3791 3792 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3793 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 3794 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3795 3796 return 0; 3797 } 3798 3799 /** 3800 * stmmac_interrupt - main ISR 3801 * @irq: interrupt number. 3802 * @dev_id: to pass the net device pointer. 3803 * Description: this is the main driver interrupt service routine. 3804 * It can call: 3805 * o DMA service routine (to manage incoming frame reception and transmission 3806 * status) 3807 * o Core interrupts to manage: remote wake-up, management counter, LPI 3808 * interrupts. 3809 */ 3810 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 3811 { 3812 struct net_device *dev = (struct net_device *)dev_id; 3813 struct stmmac_priv *priv = netdev_priv(dev); 3814 u32 rx_cnt = priv->plat->rx_queues_to_use; 3815 u32 tx_cnt = priv->plat->tx_queues_to_use; 3816 u32 queues_count; 3817 u32 queue; 3818 bool xmac; 3819 3820 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3821 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 3822 3823 if (priv->irq_wake) 3824 pm_wakeup_event(priv->device, 0); 3825 3826 if (unlikely(!dev)) { 3827 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 3828 return IRQ_NONE; 3829 } 3830 3831 /* Check if adapter is up */ 3832 if (test_bit(STMMAC_DOWN, &priv->state)) 3833 return IRQ_HANDLED; 3834 /* Check if a fatal error happened */ 3835 if (stmmac_safety_feat_interrupt(priv)) 3836 return IRQ_HANDLED; 3837 3838 /* To handle GMAC own interrupts */ 3839 if ((priv->plat->has_gmac) || xmac) { 3840 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 3841 int mtl_status; 3842 3843 if (unlikely(status)) { 3844 /* For LPI we need to save the tx status */ 3845 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 3846 priv->tx_path_in_lpi_mode = true; 3847 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 3848 priv->tx_path_in_lpi_mode = false; 3849 } 3850 3851 for (queue = 0; queue < queues_count; queue++) { 3852 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3853 3854 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 3855 queue); 3856 if (mtl_status != -EINVAL) 3857 status |= mtl_status; 3858 3859 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 3860 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3861 rx_q->rx_tail_addr, 3862 queue); 3863 } 3864 3865 /* PCS link status */ 3866 if (priv->hw->pcs) { 3867 if (priv->xstats.pcs_link) 3868 netif_carrier_on(dev); 3869 else 3870 netif_carrier_off(dev); 3871 } 3872 } 3873 3874 /* To handle DMA interrupts */ 3875 stmmac_dma_interrupt(priv); 3876 3877 return IRQ_HANDLED; 3878 } 3879 3880 #ifdef CONFIG_NET_POLL_CONTROLLER 3881 /* Polling receive - used by NETCONSOLE and other diagnostic tools 3882 * to allow network I/O with interrupts disabled. 3883 */ 3884 static void stmmac_poll_controller(struct net_device *dev) 3885 { 3886 disable_irq(dev->irq); 3887 stmmac_interrupt(dev->irq, dev); 3888 enable_irq(dev->irq); 3889 } 3890 #endif 3891 3892 /** 3893 * stmmac_ioctl - Entry point for the Ioctl 3894 * @dev: Device pointer. 3895 * @rq: An IOCTL specefic structure, that can contain a pointer to 3896 * a proprietary structure used to pass information to the driver. 3897 * @cmd: IOCTL command 3898 * Description: 3899 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 3900 */ 3901 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3902 { 3903 struct stmmac_priv *priv = netdev_priv (dev); 3904 int ret = -EOPNOTSUPP; 3905 3906 if (!netif_running(dev)) 3907 return -EINVAL; 3908 3909 switch (cmd) { 3910 case SIOCGMIIPHY: 3911 case SIOCGMIIREG: 3912 case SIOCSMIIREG: 3913 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 3914 break; 3915 case SIOCSHWTSTAMP: 3916 ret = stmmac_hwtstamp_set(dev, rq); 3917 break; 3918 case SIOCGHWTSTAMP: 3919 ret = stmmac_hwtstamp_get(dev, rq); 3920 break; 3921 default: 3922 break; 3923 } 3924 3925 return ret; 3926 } 3927 3928 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3929 void *cb_priv) 3930 { 3931 struct stmmac_priv *priv = cb_priv; 3932 int ret = -EOPNOTSUPP; 3933 3934 stmmac_disable_all_queues(priv); 3935 3936 switch (type) { 3937 case TC_SETUP_CLSU32: 3938 if (tc_cls_can_offload_and_chain0(priv->dev, type_data)) 3939 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 3940 break; 3941 default: 3942 break; 3943 } 3944 3945 stmmac_enable_all_queues(priv); 3946 return ret; 3947 } 3948 3949 static LIST_HEAD(stmmac_block_cb_list); 3950 3951 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 3952 void *type_data) 3953 { 3954 struct stmmac_priv *priv = netdev_priv(ndev); 3955 3956 switch (type) { 3957 case TC_SETUP_BLOCK: 3958 return flow_block_cb_setup_simple(type_data, 3959 &stmmac_block_cb_list, 3960 stmmac_setup_tc_block_cb, 3961 priv, priv, true); 3962 case TC_SETUP_QDISC_CBS: 3963 return stmmac_tc_setup_cbs(priv, priv, type_data); 3964 default: 3965 return -EOPNOTSUPP; 3966 } 3967 } 3968 3969 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 3970 struct net_device *sb_dev) 3971 { 3972 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 3973 /* 3974 * There is no way to determine the number of TSO 3975 * capable Queues. Let's use always the Queue 0 3976 * because if TSO is supported then at least this 3977 * one will be capable. 3978 */ 3979 return 0; 3980 } 3981 3982 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 3983 } 3984 3985 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 3986 { 3987 struct stmmac_priv *priv = netdev_priv(ndev); 3988 int ret = 0; 3989 3990 ret = eth_mac_addr(ndev, addr); 3991 if (ret) 3992 return ret; 3993 3994 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 3995 3996 return ret; 3997 } 3998 3999 #ifdef CONFIG_DEBUG_FS 4000 static struct dentry *stmmac_fs_dir; 4001 4002 static void sysfs_display_ring(void *head, int size, int extend_desc, 4003 struct seq_file *seq) 4004 { 4005 int i; 4006 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4007 struct dma_desc *p = (struct dma_desc *)head; 4008 4009 for (i = 0; i < size; i++) { 4010 if (extend_desc) { 4011 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4012 i, (unsigned int)virt_to_phys(ep), 4013 le32_to_cpu(ep->basic.des0), 4014 le32_to_cpu(ep->basic.des1), 4015 le32_to_cpu(ep->basic.des2), 4016 le32_to_cpu(ep->basic.des3)); 4017 ep++; 4018 } else { 4019 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4020 i, (unsigned int)virt_to_phys(p), 4021 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4022 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4023 p++; 4024 } 4025 seq_printf(seq, "\n"); 4026 } 4027 } 4028 4029 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4030 { 4031 struct net_device *dev = seq->private; 4032 struct stmmac_priv *priv = netdev_priv(dev); 4033 u32 rx_count = priv->plat->rx_queues_to_use; 4034 u32 tx_count = priv->plat->tx_queues_to_use; 4035 u32 queue; 4036 4037 if ((dev->flags & IFF_UP) == 0) 4038 return 0; 4039 4040 for (queue = 0; queue < rx_count; queue++) { 4041 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4042 4043 seq_printf(seq, "RX Queue %d:\n", queue); 4044 4045 if (priv->extend_desc) { 4046 seq_printf(seq, "Extended descriptor ring:\n"); 4047 sysfs_display_ring((void *)rx_q->dma_erx, 4048 DMA_RX_SIZE, 1, seq); 4049 } else { 4050 seq_printf(seq, "Descriptor ring:\n"); 4051 sysfs_display_ring((void *)rx_q->dma_rx, 4052 DMA_RX_SIZE, 0, seq); 4053 } 4054 } 4055 4056 for (queue = 0; queue < tx_count; queue++) { 4057 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4058 4059 seq_printf(seq, "TX Queue %d:\n", queue); 4060 4061 if (priv->extend_desc) { 4062 seq_printf(seq, "Extended descriptor ring:\n"); 4063 sysfs_display_ring((void *)tx_q->dma_etx, 4064 DMA_TX_SIZE, 1, seq); 4065 } else { 4066 seq_printf(seq, "Descriptor ring:\n"); 4067 sysfs_display_ring((void *)tx_q->dma_tx, 4068 DMA_TX_SIZE, 0, seq); 4069 } 4070 } 4071 4072 return 0; 4073 } 4074 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4075 4076 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4077 { 4078 struct net_device *dev = seq->private; 4079 struct stmmac_priv *priv = netdev_priv(dev); 4080 4081 if (!priv->hw_cap_support) { 4082 seq_printf(seq, "DMA HW features not supported\n"); 4083 return 0; 4084 } 4085 4086 seq_printf(seq, "==============================\n"); 4087 seq_printf(seq, "\tDMA HW features\n"); 4088 seq_printf(seq, "==============================\n"); 4089 4090 seq_printf(seq, "\t10/100 Mbps: %s\n", 4091 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4092 seq_printf(seq, "\t1000 Mbps: %s\n", 4093 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4094 seq_printf(seq, "\tHalf duplex: %s\n", 4095 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4096 seq_printf(seq, "\tHash Filter: %s\n", 4097 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4098 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4099 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4100 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4101 (priv->dma_cap.pcs) ? "Y" : "N"); 4102 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4103 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4104 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4105 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4106 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4107 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4108 seq_printf(seq, "\tRMON module: %s\n", 4109 (priv->dma_cap.rmon) ? "Y" : "N"); 4110 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4111 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4112 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4113 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4114 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4115 (priv->dma_cap.eee) ? "Y" : "N"); 4116 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4117 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4118 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4119 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4120 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4121 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4122 } else { 4123 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4124 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4125 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4126 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4127 } 4128 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4129 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4130 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4131 priv->dma_cap.number_rx_channel); 4132 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4133 priv->dma_cap.number_tx_channel); 4134 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4135 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4136 4137 return 0; 4138 } 4139 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4140 4141 static void stmmac_init_fs(struct net_device *dev) 4142 { 4143 struct stmmac_priv *priv = netdev_priv(dev); 4144 4145 /* Create per netdev entries */ 4146 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4147 4148 /* Entry to report DMA RX/TX rings */ 4149 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4150 &stmmac_rings_status_fops); 4151 4152 /* Entry to report the DMA HW features */ 4153 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4154 &stmmac_dma_cap_fops); 4155 } 4156 4157 static void stmmac_exit_fs(struct net_device *dev) 4158 { 4159 struct stmmac_priv *priv = netdev_priv(dev); 4160 4161 debugfs_remove_recursive(priv->dbgfs_dir); 4162 } 4163 #endif /* CONFIG_DEBUG_FS */ 4164 4165 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4166 { 4167 unsigned char *data = (unsigned char *)&vid_le; 4168 unsigned char data_byte = 0; 4169 u32 crc = ~0x0; 4170 u32 temp = 0; 4171 int i, bits; 4172 4173 bits = get_bitmask_order(VLAN_VID_MASK); 4174 for (i = 0; i < bits; i++) { 4175 if ((i % 8) == 0) 4176 data_byte = data[i / 8]; 4177 4178 temp = ((crc & 1) ^ data_byte) & 1; 4179 crc >>= 1; 4180 data_byte >>= 1; 4181 4182 if (temp) 4183 crc ^= 0xedb88320; 4184 } 4185 4186 return crc; 4187 } 4188 4189 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4190 { 4191 u32 crc, hash = 0; 4192 u16 vid; 4193 4194 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4195 __le16 vid_le = cpu_to_le16(vid); 4196 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4197 hash |= (1 << crc); 4198 } 4199 4200 return stmmac_update_vlan_hash(priv, priv->hw, hash, is_double); 4201 } 4202 4203 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4204 { 4205 struct stmmac_priv *priv = netdev_priv(ndev); 4206 bool is_double = false; 4207 int ret; 4208 4209 if (!priv->dma_cap.vlhash) 4210 return -EOPNOTSUPP; 4211 if (be16_to_cpu(proto) == ETH_P_8021AD) 4212 is_double = true; 4213 4214 set_bit(vid, priv->active_vlans); 4215 ret = stmmac_vlan_update(priv, is_double); 4216 if (ret) { 4217 clear_bit(vid, priv->active_vlans); 4218 return ret; 4219 } 4220 4221 return ret; 4222 } 4223 4224 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4225 { 4226 struct stmmac_priv *priv = netdev_priv(ndev); 4227 bool is_double = false; 4228 4229 if (!priv->dma_cap.vlhash) 4230 return -EOPNOTSUPP; 4231 if (be16_to_cpu(proto) == ETH_P_8021AD) 4232 is_double = true; 4233 4234 clear_bit(vid, priv->active_vlans); 4235 return stmmac_vlan_update(priv, is_double); 4236 } 4237 4238 static const struct net_device_ops stmmac_netdev_ops = { 4239 .ndo_open = stmmac_open, 4240 .ndo_start_xmit = stmmac_xmit, 4241 .ndo_stop = stmmac_release, 4242 .ndo_change_mtu = stmmac_change_mtu, 4243 .ndo_fix_features = stmmac_fix_features, 4244 .ndo_set_features = stmmac_set_features, 4245 .ndo_set_rx_mode = stmmac_set_rx_mode, 4246 .ndo_tx_timeout = stmmac_tx_timeout, 4247 .ndo_do_ioctl = stmmac_ioctl, 4248 .ndo_setup_tc = stmmac_setup_tc, 4249 .ndo_select_queue = stmmac_select_queue, 4250 #ifdef CONFIG_NET_POLL_CONTROLLER 4251 .ndo_poll_controller = stmmac_poll_controller, 4252 #endif 4253 .ndo_set_mac_address = stmmac_set_mac_address, 4254 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4255 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4256 }; 4257 4258 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4259 { 4260 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4261 return; 4262 if (test_bit(STMMAC_DOWN, &priv->state)) 4263 return; 4264 4265 netdev_err(priv->dev, "Reset adapter.\n"); 4266 4267 rtnl_lock(); 4268 netif_trans_update(priv->dev); 4269 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4270 usleep_range(1000, 2000); 4271 4272 set_bit(STMMAC_DOWN, &priv->state); 4273 dev_close(priv->dev); 4274 dev_open(priv->dev, NULL); 4275 clear_bit(STMMAC_DOWN, &priv->state); 4276 clear_bit(STMMAC_RESETING, &priv->state); 4277 rtnl_unlock(); 4278 } 4279 4280 static void stmmac_service_task(struct work_struct *work) 4281 { 4282 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4283 service_task); 4284 4285 stmmac_reset_subtask(priv); 4286 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4287 } 4288 4289 /** 4290 * stmmac_hw_init - Init the MAC device 4291 * @priv: driver private structure 4292 * Description: this function is to configure the MAC device according to 4293 * some platform parameters or the HW capability register. It prepares the 4294 * driver to use either ring or chain modes and to setup either enhanced or 4295 * normal descriptors. 4296 */ 4297 static int stmmac_hw_init(struct stmmac_priv *priv) 4298 { 4299 int ret; 4300 4301 /* dwmac-sun8i only work in chain mode */ 4302 if (priv->plat->has_sun8i) 4303 chain_mode = 1; 4304 priv->chain_mode = chain_mode; 4305 4306 /* Initialize HW Interface */ 4307 ret = stmmac_hwif_init(priv); 4308 if (ret) 4309 return ret; 4310 4311 /* Get the HW capability (new GMAC newer than 3.50a) */ 4312 priv->hw_cap_support = stmmac_get_hw_features(priv); 4313 if (priv->hw_cap_support) { 4314 dev_info(priv->device, "DMA HW capability register supported\n"); 4315 4316 /* We can override some gmac/dma configuration fields: e.g. 4317 * enh_desc, tx_coe (e.g. that are passed through the 4318 * platform) with the values from the HW capability 4319 * register (if supported). 4320 */ 4321 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4322 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4323 priv->hw->pmt = priv->plat->pmt; 4324 if (priv->dma_cap.hash_tb_sz) { 4325 priv->hw->multicast_filter_bins = 4326 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4327 priv->hw->mcast_bits_log2 = 4328 ilog2(priv->hw->multicast_filter_bins); 4329 } 4330 4331 /* TXCOE doesn't work in thresh DMA mode */ 4332 if (priv->plat->force_thresh_dma_mode) 4333 priv->plat->tx_coe = 0; 4334 else 4335 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4336 4337 /* In case of GMAC4 rx_coe is from HW cap register. */ 4338 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4339 4340 if (priv->dma_cap.rx_coe_type2) 4341 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4342 else if (priv->dma_cap.rx_coe_type1) 4343 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4344 4345 } else { 4346 dev_info(priv->device, "No HW DMA feature register supported\n"); 4347 } 4348 4349 if (priv->plat->rx_coe) { 4350 priv->hw->rx_csum = priv->plat->rx_coe; 4351 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4352 if (priv->synopsys_id < DWMAC_CORE_4_00) 4353 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4354 } 4355 if (priv->plat->tx_coe) 4356 dev_info(priv->device, "TX Checksum insertion supported\n"); 4357 4358 if (priv->plat->pmt) { 4359 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4360 device_set_wakeup_capable(priv->device, 1); 4361 } 4362 4363 if (priv->dma_cap.tsoen) 4364 dev_info(priv->device, "TSO supported\n"); 4365 4366 /* Run HW quirks, if any */ 4367 if (priv->hwif_quirks) { 4368 ret = priv->hwif_quirks(priv); 4369 if (ret) 4370 return ret; 4371 } 4372 4373 /* Rx Watchdog is available in the COREs newer than the 3.40. 4374 * In some case, for example on bugged HW this feature 4375 * has to be disable and this can be done by passing the 4376 * riwt_off field from the platform. 4377 */ 4378 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4379 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4380 priv->use_riwt = 1; 4381 dev_info(priv->device, 4382 "Enable RX Mitigation via HW Watchdog Timer\n"); 4383 } 4384 4385 return 0; 4386 } 4387 4388 /** 4389 * stmmac_dvr_probe 4390 * @device: device pointer 4391 * @plat_dat: platform data pointer 4392 * @res: stmmac resource pointer 4393 * Description: this is the main probe function used to 4394 * call the alloc_etherdev, allocate the priv structure. 4395 * Return: 4396 * returns 0 on success, otherwise errno. 4397 */ 4398 int stmmac_dvr_probe(struct device *device, 4399 struct plat_stmmacenet_data *plat_dat, 4400 struct stmmac_resources *res) 4401 { 4402 struct net_device *ndev = NULL; 4403 struct stmmac_priv *priv; 4404 u32 queue, rxq, maxq; 4405 int i, ret = 0; 4406 4407 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4408 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4409 if (!ndev) 4410 return -ENOMEM; 4411 4412 SET_NETDEV_DEV(ndev, device); 4413 4414 priv = netdev_priv(ndev); 4415 priv->device = device; 4416 priv->dev = ndev; 4417 4418 stmmac_set_ethtool_ops(ndev); 4419 priv->pause = pause; 4420 priv->plat = plat_dat; 4421 priv->ioaddr = res->addr; 4422 priv->dev->base_addr = (unsigned long)res->addr; 4423 4424 priv->dev->irq = res->irq; 4425 priv->wol_irq = res->wol_irq; 4426 priv->lpi_irq = res->lpi_irq; 4427 4428 if (!IS_ERR_OR_NULL(res->mac)) 4429 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4430 4431 dev_set_drvdata(device, priv->dev); 4432 4433 /* Verify driver arguments */ 4434 stmmac_verify_args(); 4435 4436 /* Allocate workqueue */ 4437 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4438 if (!priv->wq) { 4439 dev_err(priv->device, "failed to create workqueue\n"); 4440 return -ENOMEM; 4441 } 4442 4443 INIT_WORK(&priv->service_task, stmmac_service_task); 4444 4445 /* Override with kernel parameters if supplied XXX CRS XXX 4446 * this needs to have multiple instances 4447 */ 4448 if ((phyaddr >= 0) && (phyaddr <= 31)) 4449 priv->plat->phy_addr = phyaddr; 4450 4451 if (priv->plat->stmmac_rst) { 4452 ret = reset_control_assert(priv->plat->stmmac_rst); 4453 reset_control_deassert(priv->plat->stmmac_rst); 4454 /* Some reset controllers have only reset callback instead of 4455 * assert + deassert callbacks pair. 4456 */ 4457 if (ret == -ENOTSUPP) 4458 reset_control_reset(priv->plat->stmmac_rst); 4459 } 4460 4461 /* Init MAC and get the capabilities */ 4462 ret = stmmac_hw_init(priv); 4463 if (ret) 4464 goto error_hw_init; 4465 4466 stmmac_check_ether_addr(priv); 4467 4468 /* Configure real RX and TX queues */ 4469 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4470 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4471 4472 ndev->netdev_ops = &stmmac_netdev_ops; 4473 4474 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4475 NETIF_F_RXCSUM; 4476 4477 ret = stmmac_tc_init(priv, priv); 4478 if (!ret) { 4479 ndev->hw_features |= NETIF_F_HW_TC; 4480 } 4481 4482 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4483 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4484 priv->tso = true; 4485 dev_info(priv->device, "TSO feature enabled\n"); 4486 } 4487 4488 if (priv->dma_cap.sphen) { 4489 ndev->hw_features |= NETIF_F_GRO; 4490 priv->sph = true; 4491 dev_info(priv->device, "SPH feature enabled\n"); 4492 } 4493 4494 if (priv->dma_cap.addr64) { 4495 ret = dma_set_mask_and_coherent(device, 4496 DMA_BIT_MASK(priv->dma_cap.addr64)); 4497 if (!ret) { 4498 dev_info(priv->device, "Using %d bits DMA width\n", 4499 priv->dma_cap.addr64); 4500 } else { 4501 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4502 if (ret) { 4503 dev_err(priv->device, "Failed to set DMA Mask\n"); 4504 goto error_hw_init; 4505 } 4506 4507 priv->dma_cap.addr64 = 32; 4508 } 4509 } 4510 4511 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4512 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4513 #ifdef STMMAC_VLAN_TAG_USED 4514 /* Both mac100 and gmac support receive VLAN tag detection */ 4515 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4516 if (priv->dma_cap.vlhash) { 4517 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4518 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4519 } 4520 if (priv->dma_cap.vlins) { 4521 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4522 if (priv->dma_cap.dvlan) 4523 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4524 } 4525 #endif 4526 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4527 4528 /* Initialize RSS */ 4529 rxq = priv->plat->rx_queues_to_use; 4530 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4531 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4532 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4533 4534 if (priv->dma_cap.rssen && priv->plat->rss_en) 4535 ndev->features |= NETIF_F_RXHASH; 4536 4537 /* MTU range: 46 - hw-specific max */ 4538 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4539 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4540 ndev->max_mtu = JUMBO_LEN; 4541 else if (priv->plat->has_xgmac) 4542 ndev->max_mtu = XGMAC_JUMBO_LEN; 4543 else 4544 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4545 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4546 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4547 */ 4548 if ((priv->plat->maxmtu < ndev->max_mtu) && 4549 (priv->plat->maxmtu >= ndev->min_mtu)) 4550 ndev->max_mtu = priv->plat->maxmtu; 4551 else if (priv->plat->maxmtu < ndev->min_mtu) 4552 dev_warn(priv->device, 4553 "%s: warning: maxmtu having invalid value (%d)\n", 4554 __func__, priv->plat->maxmtu); 4555 4556 if (flow_ctrl) 4557 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4558 4559 /* Setup channels NAPI */ 4560 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4561 4562 for (queue = 0; queue < maxq; queue++) { 4563 struct stmmac_channel *ch = &priv->channel[queue]; 4564 4565 ch->priv_data = priv; 4566 ch->index = queue; 4567 4568 if (queue < priv->plat->rx_queues_to_use) { 4569 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4570 NAPI_POLL_WEIGHT); 4571 } 4572 if (queue < priv->plat->tx_queues_to_use) { 4573 netif_tx_napi_add(ndev, &ch->tx_napi, 4574 stmmac_napi_poll_tx, 4575 NAPI_POLL_WEIGHT); 4576 } 4577 } 4578 4579 mutex_init(&priv->lock); 4580 4581 /* If a specific clk_csr value is passed from the platform 4582 * this means that the CSR Clock Range selection cannot be 4583 * changed at run-time and it is fixed. Viceversa the driver'll try to 4584 * set the MDC clock dynamically according to the csr actual 4585 * clock input. 4586 */ 4587 if (priv->plat->clk_csr >= 0) 4588 priv->clk_csr = priv->plat->clk_csr; 4589 else 4590 stmmac_clk_csr_set(priv); 4591 4592 stmmac_check_pcs_mode(priv); 4593 4594 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4595 priv->hw->pcs != STMMAC_PCS_TBI && 4596 priv->hw->pcs != STMMAC_PCS_RTBI) { 4597 /* MDIO bus Registration */ 4598 ret = stmmac_mdio_register(ndev); 4599 if (ret < 0) { 4600 dev_err(priv->device, 4601 "%s: MDIO bus (id: %d) registration failed", 4602 __func__, priv->plat->bus_id); 4603 goto error_mdio_register; 4604 } 4605 } 4606 4607 ret = stmmac_phy_setup(priv); 4608 if (ret) { 4609 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4610 goto error_phy_setup; 4611 } 4612 4613 ret = register_netdev(ndev); 4614 if (ret) { 4615 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4616 __func__, ret); 4617 goto error_netdev_register; 4618 } 4619 4620 #ifdef CONFIG_DEBUG_FS 4621 stmmac_init_fs(ndev); 4622 #endif 4623 4624 return ret; 4625 4626 error_netdev_register: 4627 phylink_destroy(priv->phylink); 4628 error_phy_setup: 4629 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4630 priv->hw->pcs != STMMAC_PCS_TBI && 4631 priv->hw->pcs != STMMAC_PCS_RTBI) 4632 stmmac_mdio_unregister(ndev); 4633 error_mdio_register: 4634 for (queue = 0; queue < maxq; queue++) { 4635 struct stmmac_channel *ch = &priv->channel[queue]; 4636 4637 if (queue < priv->plat->rx_queues_to_use) 4638 netif_napi_del(&ch->rx_napi); 4639 if (queue < priv->plat->tx_queues_to_use) 4640 netif_napi_del(&ch->tx_napi); 4641 } 4642 error_hw_init: 4643 destroy_workqueue(priv->wq); 4644 4645 return ret; 4646 } 4647 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4648 4649 /** 4650 * stmmac_dvr_remove 4651 * @dev: device pointer 4652 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4653 * changes the link status, releases the DMA descriptor rings. 4654 */ 4655 int stmmac_dvr_remove(struct device *dev) 4656 { 4657 struct net_device *ndev = dev_get_drvdata(dev); 4658 struct stmmac_priv *priv = netdev_priv(ndev); 4659 4660 netdev_info(priv->dev, "%s: removing driver", __func__); 4661 4662 #ifdef CONFIG_DEBUG_FS 4663 stmmac_exit_fs(ndev); 4664 #endif 4665 stmmac_stop_all_dma(priv); 4666 4667 stmmac_mac_set(priv, priv->ioaddr, false); 4668 netif_carrier_off(ndev); 4669 unregister_netdev(ndev); 4670 phylink_destroy(priv->phylink); 4671 if (priv->plat->stmmac_rst) 4672 reset_control_assert(priv->plat->stmmac_rst); 4673 clk_disable_unprepare(priv->plat->pclk); 4674 clk_disable_unprepare(priv->plat->stmmac_clk); 4675 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4676 priv->hw->pcs != STMMAC_PCS_TBI && 4677 priv->hw->pcs != STMMAC_PCS_RTBI) 4678 stmmac_mdio_unregister(ndev); 4679 destroy_workqueue(priv->wq); 4680 mutex_destroy(&priv->lock); 4681 4682 return 0; 4683 } 4684 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4685 4686 /** 4687 * stmmac_suspend - suspend callback 4688 * @dev: device pointer 4689 * Description: this is the function to suspend the device and it is called 4690 * by the platform driver to stop the network queue, release the resources, 4691 * program the PMT register (for WoL), clean and release driver resources. 4692 */ 4693 int stmmac_suspend(struct device *dev) 4694 { 4695 struct net_device *ndev = dev_get_drvdata(dev); 4696 struct stmmac_priv *priv = netdev_priv(ndev); 4697 4698 if (!ndev || !netif_running(ndev)) 4699 return 0; 4700 4701 phylink_stop(priv->phylink); 4702 4703 mutex_lock(&priv->lock); 4704 4705 netif_device_detach(ndev); 4706 stmmac_stop_all_queues(priv); 4707 4708 stmmac_disable_all_queues(priv); 4709 4710 /* Stop TX/RX DMA */ 4711 stmmac_stop_all_dma(priv); 4712 4713 /* Enable Power down mode by programming the PMT regs */ 4714 if (device_may_wakeup(priv->device)) { 4715 stmmac_pmt(priv, priv->hw, priv->wolopts); 4716 priv->irq_wake = 1; 4717 } else { 4718 stmmac_mac_set(priv, priv->ioaddr, false); 4719 pinctrl_pm_select_sleep_state(priv->device); 4720 /* Disable clock in case of PWM is off */ 4721 clk_disable(priv->plat->pclk); 4722 clk_disable(priv->plat->stmmac_clk); 4723 } 4724 mutex_unlock(&priv->lock); 4725 4726 priv->speed = SPEED_UNKNOWN; 4727 return 0; 4728 } 4729 EXPORT_SYMBOL_GPL(stmmac_suspend); 4730 4731 /** 4732 * stmmac_reset_queues_param - reset queue parameters 4733 * @dev: device pointer 4734 */ 4735 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 4736 { 4737 u32 rx_cnt = priv->plat->rx_queues_to_use; 4738 u32 tx_cnt = priv->plat->tx_queues_to_use; 4739 u32 queue; 4740 4741 for (queue = 0; queue < rx_cnt; queue++) { 4742 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4743 4744 rx_q->cur_rx = 0; 4745 rx_q->dirty_rx = 0; 4746 } 4747 4748 for (queue = 0; queue < tx_cnt; queue++) { 4749 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4750 4751 tx_q->cur_tx = 0; 4752 tx_q->dirty_tx = 0; 4753 tx_q->mss = 0; 4754 } 4755 } 4756 4757 /** 4758 * stmmac_resume - resume callback 4759 * @dev: device pointer 4760 * Description: when resume this function is invoked to setup the DMA and CORE 4761 * in a usable state. 4762 */ 4763 int stmmac_resume(struct device *dev) 4764 { 4765 struct net_device *ndev = dev_get_drvdata(dev); 4766 struct stmmac_priv *priv = netdev_priv(ndev); 4767 4768 if (!netif_running(ndev)) 4769 return 0; 4770 4771 /* Power Down bit, into the PM register, is cleared 4772 * automatically as soon as a magic packet or a Wake-up frame 4773 * is received. Anyway, it's better to manually clear 4774 * this bit because it can generate problems while resuming 4775 * from another devices (e.g. serial console). 4776 */ 4777 if (device_may_wakeup(priv->device)) { 4778 mutex_lock(&priv->lock); 4779 stmmac_pmt(priv, priv->hw, 0); 4780 mutex_unlock(&priv->lock); 4781 priv->irq_wake = 0; 4782 } else { 4783 pinctrl_pm_select_default_state(priv->device); 4784 /* enable the clk previously disabled */ 4785 clk_enable(priv->plat->stmmac_clk); 4786 clk_enable(priv->plat->pclk); 4787 /* reset the phy so that it's ready */ 4788 if (priv->mii) 4789 stmmac_mdio_reset(priv->mii); 4790 } 4791 4792 netif_device_attach(ndev); 4793 4794 mutex_lock(&priv->lock); 4795 4796 stmmac_reset_queues_param(priv); 4797 4798 stmmac_clear_descriptors(priv); 4799 4800 stmmac_hw_setup(ndev, false); 4801 stmmac_init_coalesce(priv); 4802 stmmac_set_rx_mode(ndev); 4803 4804 stmmac_enable_all_queues(priv); 4805 4806 stmmac_start_all_queues(priv); 4807 4808 mutex_unlock(&priv->lock); 4809 4810 phylink_start(priv->phylink); 4811 4812 return 0; 4813 } 4814 EXPORT_SYMBOL_GPL(stmmac_resume); 4815 4816 #ifndef MODULE 4817 static int __init stmmac_cmdline_opt(char *str) 4818 { 4819 char *opt; 4820 4821 if (!str || !*str) 4822 return -EINVAL; 4823 while ((opt = strsep(&str, ",")) != NULL) { 4824 if (!strncmp(opt, "debug:", 6)) { 4825 if (kstrtoint(opt + 6, 0, &debug)) 4826 goto err; 4827 } else if (!strncmp(opt, "phyaddr:", 8)) { 4828 if (kstrtoint(opt + 8, 0, &phyaddr)) 4829 goto err; 4830 } else if (!strncmp(opt, "buf_sz:", 7)) { 4831 if (kstrtoint(opt + 7, 0, &buf_sz)) 4832 goto err; 4833 } else if (!strncmp(opt, "tc:", 3)) { 4834 if (kstrtoint(opt + 3, 0, &tc)) 4835 goto err; 4836 } else if (!strncmp(opt, "watchdog:", 9)) { 4837 if (kstrtoint(opt + 9, 0, &watchdog)) 4838 goto err; 4839 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 4840 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 4841 goto err; 4842 } else if (!strncmp(opt, "pause:", 6)) { 4843 if (kstrtoint(opt + 6, 0, &pause)) 4844 goto err; 4845 } else if (!strncmp(opt, "eee_timer:", 10)) { 4846 if (kstrtoint(opt + 10, 0, &eee_timer)) 4847 goto err; 4848 } else if (!strncmp(opt, "chain_mode:", 11)) { 4849 if (kstrtoint(opt + 11, 0, &chain_mode)) 4850 goto err; 4851 } 4852 } 4853 return 0; 4854 4855 err: 4856 pr_err("%s: ERROR broken module parameter conversion", __func__); 4857 return -EINVAL; 4858 } 4859 4860 __setup("stmmaceth=", stmmac_cmdline_opt); 4861 #endif /* MODULE */ 4862 4863 static int __init stmmac_init(void) 4864 { 4865 #ifdef CONFIG_DEBUG_FS 4866 /* Create debugfs main directory if it doesn't exist yet */ 4867 if (!stmmac_fs_dir) 4868 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 4869 #endif 4870 4871 return 0; 4872 } 4873 4874 static void __exit stmmac_exit(void) 4875 { 4876 #ifdef CONFIG_DEBUG_FS 4877 debugfs_remove_recursive(stmmac_fs_dir); 4878 #endif 4879 } 4880 4881 module_init(stmmac_init) 4882 module_exit(stmmac_exit) 4883 4884 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 4885 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 4886 MODULE_LICENSE("GPL"); 4887