1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 992 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 993 994 if (interface == PHY_INTERFACE_MODE_USXGMII) { 995 switch (speed) { 996 case SPEED_10000: 997 ctrl |= priv->hw->link.xgmii.speed10000; 998 break; 999 case SPEED_5000: 1000 ctrl |= priv->hw->link.xgmii.speed5000; 1001 break; 1002 case SPEED_2500: 1003 ctrl |= priv->hw->link.xgmii.speed2500; 1004 break; 1005 default: 1006 return; 1007 } 1008 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1009 switch (speed) { 1010 case SPEED_100000: 1011 ctrl |= priv->hw->link.xlgmii.speed100000; 1012 break; 1013 case SPEED_50000: 1014 ctrl |= priv->hw->link.xlgmii.speed50000; 1015 break; 1016 case SPEED_40000: 1017 ctrl |= priv->hw->link.xlgmii.speed40000; 1018 break; 1019 case SPEED_25000: 1020 ctrl |= priv->hw->link.xlgmii.speed25000; 1021 break; 1022 case SPEED_10000: 1023 ctrl |= priv->hw->link.xgmii.speed10000; 1024 break; 1025 case SPEED_2500: 1026 ctrl |= priv->hw->link.speed2500; 1027 break; 1028 case SPEED_1000: 1029 ctrl |= priv->hw->link.speed1000; 1030 break; 1031 default: 1032 return; 1033 } 1034 } else { 1035 switch (speed) { 1036 case SPEED_2500: 1037 ctrl |= priv->hw->link.speed2500; 1038 break; 1039 case SPEED_1000: 1040 ctrl |= priv->hw->link.speed1000; 1041 break; 1042 case SPEED_100: 1043 ctrl |= priv->hw->link.speed100; 1044 break; 1045 case SPEED_10: 1046 ctrl |= priv->hw->link.speed10; 1047 break; 1048 default: 1049 return; 1050 } 1051 } 1052 1053 priv->speed = speed; 1054 1055 if (priv->plat->fix_mac_speed) 1056 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1057 1058 if (!duplex) 1059 ctrl &= ~priv->hw->link.duplex; 1060 else 1061 ctrl |= priv->hw->link.duplex; 1062 1063 /* Flow Control operation */ 1064 if (tx_pause && rx_pause) 1065 stmmac_mac_flow_ctrl(priv, duplex); 1066 1067 if (ctrl != old_ctrl) 1068 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1069 1070 stmmac_mac_set(priv, priv->ioaddr, true); 1071 if (phy && priv->dma_cap.eee) { 1072 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1073 priv->eee_enabled = stmmac_eee_init(priv); 1074 priv->tx_lpi_enabled = priv->eee_enabled; 1075 stmmac_set_eee_pls(priv, priv->hw, true); 1076 } 1077 1078 if (priv->dma_cap.fpesel) 1079 stmmac_fpe_link_state_handle(priv, true); 1080 } 1081 1082 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1083 .validate = phylink_generic_validate, 1084 .mac_select_pcs = stmmac_mac_select_pcs, 1085 .mac_config = stmmac_mac_config, 1086 .mac_link_down = stmmac_mac_link_down, 1087 .mac_link_up = stmmac_mac_link_up, 1088 }; 1089 1090 /** 1091 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1092 * @priv: driver private structure 1093 * Description: this is to verify if the HW supports the PCS. 1094 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1095 * configured for the TBI, RTBI, or SGMII PHY interface. 1096 */ 1097 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1098 { 1099 int interface = priv->plat->interface; 1100 1101 if (priv->dma_cap.pcs) { 1102 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1103 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1104 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1105 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1106 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1107 priv->hw->pcs = STMMAC_PCS_RGMII; 1108 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1109 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1110 priv->hw->pcs = STMMAC_PCS_SGMII; 1111 } 1112 } 1113 } 1114 1115 /** 1116 * stmmac_init_phy - PHY initialization 1117 * @dev: net device structure 1118 * Description: it initializes the driver's PHY state, and attaches the PHY 1119 * to the mac driver. 1120 * Return value: 1121 * 0 on success 1122 */ 1123 static int stmmac_init_phy(struct net_device *dev) 1124 { 1125 struct stmmac_priv *priv = netdev_priv(dev); 1126 struct fwnode_handle *fwnode; 1127 int ret; 1128 1129 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1130 if (!fwnode) 1131 fwnode = dev_fwnode(priv->device); 1132 1133 if (fwnode) 1134 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1135 1136 /* Some DT bindings do not set-up the PHY handle. Let's try to 1137 * manually parse it 1138 */ 1139 if (!fwnode || ret) { 1140 int addr = priv->plat->phy_addr; 1141 struct phy_device *phydev; 1142 1143 phydev = mdiobus_get_phy(priv->mii, addr); 1144 if (!phydev) { 1145 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1146 return -ENODEV; 1147 } 1148 1149 ret = phylink_connect_phy(priv->phylink, phydev); 1150 } 1151 1152 if (!priv->plat->pmt) { 1153 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1154 1155 phylink_ethtool_get_wol(priv->phylink, &wol); 1156 device_set_wakeup_capable(priv->device, !!wol.supported); 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int stmmac_phy_setup(struct stmmac_priv *priv) 1163 { 1164 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1165 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1166 int max_speed = priv->plat->max_speed; 1167 int mode = priv->plat->phy_interface; 1168 struct phylink *phylink; 1169 1170 priv->phylink_config.dev = &priv->dev->dev; 1171 priv->phylink_config.type = PHYLINK_NETDEV; 1172 if (priv->plat->mdio_bus_data) 1173 priv->phylink_config.ovr_an_inband = 1174 mdio_bus_data->xpcs_an_inband; 1175 1176 if (!fwnode) 1177 fwnode = dev_fwnode(priv->device); 1178 1179 /* Set the platform/firmware specified interface mode */ 1180 __set_bit(mode, priv->phylink_config.supported_interfaces); 1181 1182 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1183 if (priv->hw->xpcs) 1184 xpcs_get_interfaces(priv->hw->xpcs, 1185 priv->phylink_config.supported_interfaces); 1186 1187 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1188 MAC_10 | MAC_100; 1189 1190 if (!max_speed || max_speed >= 1000) 1191 priv->phylink_config.mac_capabilities |= MAC_1000; 1192 1193 if (priv->plat->has_gmac4) { 1194 if (!max_speed || max_speed >= 2500) 1195 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1196 } else if (priv->plat->has_xgmac) { 1197 if (!max_speed || max_speed >= 2500) 1198 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1199 if (!max_speed || max_speed >= 5000) 1200 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1201 if (!max_speed || max_speed >= 10000) 1202 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1203 if (!max_speed || max_speed >= 25000) 1204 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1205 if (!max_speed || max_speed >= 40000) 1206 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1207 if (!max_speed || max_speed >= 50000) 1208 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1209 if (!max_speed || max_speed >= 100000) 1210 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1211 } 1212 1213 /* Half-Duplex can only work with single queue */ 1214 if (priv->plat->tx_queues_to_use > 1) 1215 priv->phylink_config.mac_capabilities &= 1216 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1217 priv->phylink_config.mac_managed_pm = true; 1218 1219 phylink = phylink_create(&priv->phylink_config, fwnode, 1220 mode, &stmmac_phylink_mac_ops); 1221 if (IS_ERR(phylink)) 1222 return PTR_ERR(phylink); 1223 1224 priv->phylink = phylink; 1225 return 0; 1226 } 1227 1228 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1229 struct stmmac_dma_conf *dma_conf) 1230 { 1231 u32 rx_cnt = priv->plat->rx_queues_to_use; 1232 unsigned int desc_size; 1233 void *head_rx; 1234 u32 queue; 1235 1236 /* Display RX rings */ 1237 for (queue = 0; queue < rx_cnt; queue++) { 1238 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1239 1240 pr_info("\tRX Queue %u rings\n", queue); 1241 1242 if (priv->extend_desc) { 1243 head_rx = (void *)rx_q->dma_erx; 1244 desc_size = sizeof(struct dma_extended_desc); 1245 } else { 1246 head_rx = (void *)rx_q->dma_rx; 1247 desc_size = sizeof(struct dma_desc); 1248 } 1249 1250 /* Display RX ring */ 1251 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1252 rx_q->dma_rx_phy, desc_size); 1253 } 1254 } 1255 1256 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1257 struct stmmac_dma_conf *dma_conf) 1258 { 1259 u32 tx_cnt = priv->plat->tx_queues_to_use; 1260 unsigned int desc_size; 1261 void *head_tx; 1262 u32 queue; 1263 1264 /* Display TX rings */ 1265 for (queue = 0; queue < tx_cnt; queue++) { 1266 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1267 1268 pr_info("\tTX Queue %d rings\n", queue); 1269 1270 if (priv->extend_desc) { 1271 head_tx = (void *)tx_q->dma_etx; 1272 desc_size = sizeof(struct dma_extended_desc); 1273 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1274 head_tx = (void *)tx_q->dma_entx; 1275 desc_size = sizeof(struct dma_edesc); 1276 } else { 1277 head_tx = (void *)tx_q->dma_tx; 1278 desc_size = sizeof(struct dma_desc); 1279 } 1280 1281 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1282 tx_q->dma_tx_phy, desc_size); 1283 } 1284 } 1285 1286 static void stmmac_display_rings(struct stmmac_priv *priv, 1287 struct stmmac_dma_conf *dma_conf) 1288 { 1289 /* Display RX ring */ 1290 stmmac_display_rx_rings(priv, dma_conf); 1291 1292 /* Display TX ring */ 1293 stmmac_display_tx_rings(priv, dma_conf); 1294 } 1295 1296 static int stmmac_set_bfsize(int mtu, int bufsize) 1297 { 1298 int ret = bufsize; 1299 1300 if (mtu >= BUF_SIZE_8KiB) 1301 ret = BUF_SIZE_16KiB; 1302 else if (mtu >= BUF_SIZE_4KiB) 1303 ret = BUF_SIZE_8KiB; 1304 else if (mtu >= BUF_SIZE_2KiB) 1305 ret = BUF_SIZE_4KiB; 1306 else if (mtu > DEFAULT_BUFSIZE) 1307 ret = BUF_SIZE_2KiB; 1308 else 1309 ret = DEFAULT_BUFSIZE; 1310 1311 return ret; 1312 } 1313 1314 /** 1315 * stmmac_clear_rx_descriptors - clear RX descriptors 1316 * @priv: driver private structure 1317 * @dma_conf: structure to take the dma data 1318 * @queue: RX queue index 1319 * Description: this function is called to clear the RX descriptors 1320 * in case of both basic and extended descriptors are used. 1321 */ 1322 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1323 struct stmmac_dma_conf *dma_conf, 1324 u32 queue) 1325 { 1326 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1327 int i; 1328 1329 /* Clear the RX descriptors */ 1330 for (i = 0; i < dma_conf->dma_rx_size; i++) 1331 if (priv->extend_desc) 1332 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1333 priv->use_riwt, priv->mode, 1334 (i == dma_conf->dma_rx_size - 1), 1335 dma_conf->dma_buf_sz); 1336 else 1337 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1338 priv->use_riwt, priv->mode, 1339 (i == dma_conf->dma_rx_size - 1), 1340 dma_conf->dma_buf_sz); 1341 } 1342 1343 /** 1344 * stmmac_clear_tx_descriptors - clear tx descriptors 1345 * @priv: driver private structure 1346 * @dma_conf: structure to take the dma data 1347 * @queue: TX queue index. 1348 * Description: this function is called to clear the TX descriptors 1349 * in case of both basic and extended descriptors are used. 1350 */ 1351 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1352 struct stmmac_dma_conf *dma_conf, 1353 u32 queue) 1354 { 1355 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1356 int i; 1357 1358 /* Clear the TX descriptors */ 1359 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1360 int last = (i == (dma_conf->dma_tx_size - 1)); 1361 struct dma_desc *p; 1362 1363 if (priv->extend_desc) 1364 p = &tx_q->dma_etx[i].basic; 1365 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1366 p = &tx_q->dma_entx[i].basic; 1367 else 1368 p = &tx_q->dma_tx[i]; 1369 1370 stmmac_init_tx_desc(priv, p, priv->mode, last); 1371 } 1372 } 1373 1374 /** 1375 * stmmac_clear_descriptors - clear descriptors 1376 * @priv: driver private structure 1377 * @dma_conf: structure to take the dma data 1378 * Description: this function is called to clear the TX and RX descriptors 1379 * in case of both basic and extended descriptors are used. 1380 */ 1381 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1382 struct stmmac_dma_conf *dma_conf) 1383 { 1384 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1385 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1386 u32 queue; 1387 1388 /* Clear the RX descriptors */ 1389 for (queue = 0; queue < rx_queue_cnt; queue++) 1390 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1391 1392 /* Clear the TX descriptors */ 1393 for (queue = 0; queue < tx_queue_cnt; queue++) 1394 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1395 } 1396 1397 /** 1398 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1399 * @priv: driver private structure 1400 * @dma_conf: structure to take the dma data 1401 * @p: descriptor pointer 1402 * @i: descriptor index 1403 * @flags: gfp flag 1404 * @queue: RX queue index 1405 * Description: this function is called to allocate a receive buffer, perform 1406 * the DMA mapping and init the descriptor. 1407 */ 1408 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1409 struct stmmac_dma_conf *dma_conf, 1410 struct dma_desc *p, 1411 int i, gfp_t flags, u32 queue) 1412 { 1413 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1414 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1415 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1416 1417 if (priv->dma_cap.addr64 <= 32) 1418 gfp |= GFP_DMA32; 1419 1420 if (!buf->page) { 1421 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1422 if (!buf->page) 1423 return -ENOMEM; 1424 buf->page_offset = stmmac_rx_offset(priv); 1425 } 1426 1427 if (priv->sph && !buf->sec_page) { 1428 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1429 if (!buf->sec_page) 1430 return -ENOMEM; 1431 1432 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1433 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1434 } else { 1435 buf->sec_page = NULL; 1436 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1437 } 1438 1439 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1440 1441 stmmac_set_desc_addr(priv, p, buf->addr); 1442 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1443 stmmac_init_desc3(priv, p); 1444 1445 return 0; 1446 } 1447 1448 /** 1449 * stmmac_free_rx_buffer - free RX dma buffers 1450 * @priv: private structure 1451 * @rx_q: RX queue 1452 * @i: buffer index. 1453 */ 1454 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1455 struct stmmac_rx_queue *rx_q, 1456 int i) 1457 { 1458 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1459 1460 if (buf->page) 1461 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1462 buf->page = NULL; 1463 1464 if (buf->sec_page) 1465 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1466 buf->sec_page = NULL; 1467 } 1468 1469 /** 1470 * stmmac_free_tx_buffer - free RX dma buffers 1471 * @priv: private structure 1472 * @dma_conf: structure to take the dma data 1473 * @queue: RX queue index 1474 * @i: buffer index. 1475 */ 1476 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1477 struct stmmac_dma_conf *dma_conf, 1478 u32 queue, int i) 1479 { 1480 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1481 1482 if (tx_q->tx_skbuff_dma[i].buf && 1483 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1484 if (tx_q->tx_skbuff_dma[i].map_as_page) 1485 dma_unmap_page(priv->device, 1486 tx_q->tx_skbuff_dma[i].buf, 1487 tx_q->tx_skbuff_dma[i].len, 1488 DMA_TO_DEVICE); 1489 else 1490 dma_unmap_single(priv->device, 1491 tx_q->tx_skbuff_dma[i].buf, 1492 tx_q->tx_skbuff_dma[i].len, 1493 DMA_TO_DEVICE); 1494 } 1495 1496 if (tx_q->xdpf[i] && 1497 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1498 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1499 xdp_return_frame(tx_q->xdpf[i]); 1500 tx_q->xdpf[i] = NULL; 1501 } 1502 1503 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1504 tx_q->xsk_frames_done++; 1505 1506 if (tx_q->tx_skbuff[i] && 1507 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1508 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1509 tx_q->tx_skbuff[i] = NULL; 1510 } 1511 1512 tx_q->tx_skbuff_dma[i].buf = 0; 1513 tx_q->tx_skbuff_dma[i].map_as_page = false; 1514 } 1515 1516 /** 1517 * dma_free_rx_skbufs - free RX dma buffers 1518 * @priv: private structure 1519 * @dma_conf: structure to take the dma data 1520 * @queue: RX queue index 1521 */ 1522 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1523 struct stmmac_dma_conf *dma_conf, 1524 u32 queue) 1525 { 1526 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1527 int i; 1528 1529 for (i = 0; i < dma_conf->dma_rx_size; i++) 1530 stmmac_free_rx_buffer(priv, rx_q, i); 1531 } 1532 1533 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1534 struct stmmac_dma_conf *dma_conf, 1535 u32 queue, gfp_t flags) 1536 { 1537 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1538 int i; 1539 1540 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1541 struct dma_desc *p; 1542 int ret; 1543 1544 if (priv->extend_desc) 1545 p = &((rx_q->dma_erx + i)->basic); 1546 else 1547 p = rx_q->dma_rx + i; 1548 1549 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1550 queue); 1551 if (ret) 1552 return ret; 1553 1554 rx_q->buf_alloc_num++; 1555 } 1556 1557 return 0; 1558 } 1559 1560 /** 1561 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1562 * @priv: private structure 1563 * @dma_conf: structure to take the dma data 1564 * @queue: RX queue index 1565 */ 1566 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1567 struct stmmac_dma_conf *dma_conf, 1568 u32 queue) 1569 { 1570 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1571 int i; 1572 1573 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1574 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1575 1576 if (!buf->xdp) 1577 continue; 1578 1579 xsk_buff_free(buf->xdp); 1580 buf->xdp = NULL; 1581 } 1582 } 1583 1584 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1585 struct stmmac_dma_conf *dma_conf, 1586 u32 queue) 1587 { 1588 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1589 int i; 1590 1591 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1592 struct stmmac_rx_buffer *buf; 1593 dma_addr_t dma_addr; 1594 struct dma_desc *p; 1595 1596 if (priv->extend_desc) 1597 p = (struct dma_desc *)(rx_q->dma_erx + i); 1598 else 1599 p = rx_q->dma_rx + i; 1600 1601 buf = &rx_q->buf_pool[i]; 1602 1603 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1604 if (!buf->xdp) 1605 return -ENOMEM; 1606 1607 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1608 stmmac_set_desc_addr(priv, p, dma_addr); 1609 rx_q->buf_alloc_num++; 1610 } 1611 1612 return 0; 1613 } 1614 1615 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1616 { 1617 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1618 return NULL; 1619 1620 return xsk_get_pool_from_qid(priv->dev, queue); 1621 } 1622 1623 /** 1624 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1625 * @priv: driver private structure 1626 * @dma_conf: structure to take the dma data 1627 * @queue: RX queue index 1628 * @flags: gfp flag. 1629 * Description: this function initializes the DMA RX descriptors 1630 * and allocates the socket buffers. It supports the chained and ring 1631 * modes. 1632 */ 1633 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1634 struct stmmac_dma_conf *dma_conf, 1635 u32 queue, gfp_t flags) 1636 { 1637 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1638 int ret; 1639 1640 netif_dbg(priv, probe, priv->dev, 1641 "(%s) dma_rx_phy=0x%08x\n", __func__, 1642 (u32)rx_q->dma_rx_phy); 1643 1644 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1645 1646 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1647 1648 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1649 1650 if (rx_q->xsk_pool) { 1651 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1652 MEM_TYPE_XSK_BUFF_POOL, 1653 NULL)); 1654 netdev_info(priv->dev, 1655 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1656 rx_q->queue_index); 1657 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1658 } else { 1659 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1660 MEM_TYPE_PAGE_POOL, 1661 rx_q->page_pool)); 1662 netdev_info(priv->dev, 1663 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1664 rx_q->queue_index); 1665 } 1666 1667 if (rx_q->xsk_pool) { 1668 /* RX XDP ZC buffer pool may not be populated, e.g. 1669 * xdpsock TX-only. 1670 */ 1671 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1672 } else { 1673 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1674 if (ret < 0) 1675 return -ENOMEM; 1676 } 1677 1678 /* Setup the chained descriptor addresses */ 1679 if (priv->mode == STMMAC_CHAIN_MODE) { 1680 if (priv->extend_desc) 1681 stmmac_mode_init(priv, rx_q->dma_erx, 1682 rx_q->dma_rx_phy, 1683 dma_conf->dma_rx_size, 1); 1684 else 1685 stmmac_mode_init(priv, rx_q->dma_rx, 1686 rx_q->dma_rx_phy, 1687 dma_conf->dma_rx_size, 0); 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int init_dma_rx_desc_rings(struct net_device *dev, 1694 struct stmmac_dma_conf *dma_conf, 1695 gfp_t flags) 1696 { 1697 struct stmmac_priv *priv = netdev_priv(dev); 1698 u32 rx_count = priv->plat->rx_queues_to_use; 1699 int queue; 1700 int ret; 1701 1702 /* RX INITIALIZATION */ 1703 netif_dbg(priv, probe, priv->dev, 1704 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1705 1706 for (queue = 0; queue < rx_count; queue++) { 1707 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1708 if (ret) 1709 goto err_init_rx_buffers; 1710 } 1711 1712 return 0; 1713 1714 err_init_rx_buffers: 1715 while (queue >= 0) { 1716 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1717 1718 if (rx_q->xsk_pool) 1719 dma_free_rx_xskbufs(priv, dma_conf, queue); 1720 else 1721 dma_free_rx_skbufs(priv, dma_conf, queue); 1722 1723 rx_q->buf_alloc_num = 0; 1724 rx_q->xsk_pool = NULL; 1725 1726 queue--; 1727 } 1728 1729 return ret; 1730 } 1731 1732 /** 1733 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1734 * @priv: driver private structure 1735 * @dma_conf: structure to take the dma data 1736 * @queue: TX queue index 1737 * Description: this function initializes the DMA TX descriptors 1738 * and allocates the socket buffers. It supports the chained and ring 1739 * modes. 1740 */ 1741 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1742 struct stmmac_dma_conf *dma_conf, 1743 u32 queue) 1744 { 1745 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1746 int i; 1747 1748 netif_dbg(priv, probe, priv->dev, 1749 "(%s) dma_tx_phy=0x%08x\n", __func__, 1750 (u32)tx_q->dma_tx_phy); 1751 1752 /* Setup the chained descriptor addresses */ 1753 if (priv->mode == STMMAC_CHAIN_MODE) { 1754 if (priv->extend_desc) 1755 stmmac_mode_init(priv, tx_q->dma_etx, 1756 tx_q->dma_tx_phy, 1757 dma_conf->dma_tx_size, 1); 1758 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1759 stmmac_mode_init(priv, tx_q->dma_tx, 1760 tx_q->dma_tx_phy, 1761 dma_conf->dma_tx_size, 0); 1762 } 1763 1764 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1765 1766 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1767 struct dma_desc *p; 1768 1769 if (priv->extend_desc) 1770 p = &((tx_q->dma_etx + i)->basic); 1771 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1772 p = &((tx_q->dma_entx + i)->basic); 1773 else 1774 p = tx_q->dma_tx + i; 1775 1776 stmmac_clear_desc(priv, p); 1777 1778 tx_q->tx_skbuff_dma[i].buf = 0; 1779 tx_q->tx_skbuff_dma[i].map_as_page = false; 1780 tx_q->tx_skbuff_dma[i].len = 0; 1781 tx_q->tx_skbuff_dma[i].last_segment = false; 1782 tx_q->tx_skbuff[i] = NULL; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static int init_dma_tx_desc_rings(struct net_device *dev, 1789 struct stmmac_dma_conf *dma_conf) 1790 { 1791 struct stmmac_priv *priv = netdev_priv(dev); 1792 u32 tx_queue_cnt; 1793 u32 queue; 1794 1795 tx_queue_cnt = priv->plat->tx_queues_to_use; 1796 1797 for (queue = 0; queue < tx_queue_cnt; queue++) 1798 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1799 1800 return 0; 1801 } 1802 1803 /** 1804 * init_dma_desc_rings - init the RX/TX descriptor rings 1805 * @dev: net device structure 1806 * @dma_conf: structure to take the dma data 1807 * @flags: gfp flag. 1808 * Description: this function initializes the DMA RX/TX descriptors 1809 * and allocates the socket buffers. It supports the chained and ring 1810 * modes. 1811 */ 1812 static int init_dma_desc_rings(struct net_device *dev, 1813 struct stmmac_dma_conf *dma_conf, 1814 gfp_t flags) 1815 { 1816 struct stmmac_priv *priv = netdev_priv(dev); 1817 int ret; 1818 1819 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1820 if (ret) 1821 return ret; 1822 1823 ret = init_dma_tx_desc_rings(dev, dma_conf); 1824 1825 stmmac_clear_descriptors(priv, dma_conf); 1826 1827 if (netif_msg_hw(priv)) 1828 stmmac_display_rings(priv, dma_conf); 1829 1830 return ret; 1831 } 1832 1833 /** 1834 * dma_free_tx_skbufs - free TX dma buffers 1835 * @priv: private structure 1836 * @dma_conf: structure to take the dma data 1837 * @queue: TX queue index 1838 */ 1839 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1840 struct stmmac_dma_conf *dma_conf, 1841 u32 queue) 1842 { 1843 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1844 int i; 1845 1846 tx_q->xsk_frames_done = 0; 1847 1848 for (i = 0; i < dma_conf->dma_tx_size; i++) 1849 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1850 1851 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1852 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1853 tx_q->xsk_frames_done = 0; 1854 tx_q->xsk_pool = NULL; 1855 } 1856 } 1857 1858 /** 1859 * stmmac_free_tx_skbufs - free TX skb buffers 1860 * @priv: private structure 1861 */ 1862 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1863 { 1864 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1865 u32 queue; 1866 1867 for (queue = 0; queue < tx_queue_cnt; queue++) 1868 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1869 } 1870 1871 /** 1872 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1873 * @priv: private structure 1874 * @dma_conf: structure to take the dma data 1875 * @queue: RX queue index 1876 */ 1877 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1878 struct stmmac_dma_conf *dma_conf, 1879 u32 queue) 1880 { 1881 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1882 1883 /* Release the DMA RX socket buffers */ 1884 if (rx_q->xsk_pool) 1885 dma_free_rx_xskbufs(priv, dma_conf, queue); 1886 else 1887 dma_free_rx_skbufs(priv, dma_conf, queue); 1888 1889 rx_q->buf_alloc_num = 0; 1890 rx_q->xsk_pool = NULL; 1891 1892 /* Free DMA regions of consistent memory previously allocated */ 1893 if (!priv->extend_desc) 1894 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1895 sizeof(struct dma_desc), 1896 rx_q->dma_rx, rx_q->dma_rx_phy); 1897 else 1898 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1899 sizeof(struct dma_extended_desc), 1900 rx_q->dma_erx, rx_q->dma_rx_phy); 1901 1902 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1903 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1904 1905 kfree(rx_q->buf_pool); 1906 if (rx_q->page_pool) 1907 page_pool_destroy(rx_q->page_pool); 1908 } 1909 1910 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1911 struct stmmac_dma_conf *dma_conf) 1912 { 1913 u32 rx_count = priv->plat->rx_queues_to_use; 1914 u32 queue; 1915 1916 /* Free RX queue resources */ 1917 for (queue = 0; queue < rx_count; queue++) 1918 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1919 } 1920 1921 /** 1922 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1923 * @priv: private structure 1924 * @dma_conf: structure to take the dma data 1925 * @queue: TX queue index 1926 */ 1927 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1928 struct stmmac_dma_conf *dma_conf, 1929 u32 queue) 1930 { 1931 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1932 size_t size; 1933 void *addr; 1934 1935 /* Release the DMA TX socket buffers */ 1936 dma_free_tx_skbufs(priv, dma_conf, queue); 1937 1938 if (priv->extend_desc) { 1939 size = sizeof(struct dma_extended_desc); 1940 addr = tx_q->dma_etx; 1941 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1942 size = sizeof(struct dma_edesc); 1943 addr = tx_q->dma_entx; 1944 } else { 1945 size = sizeof(struct dma_desc); 1946 addr = tx_q->dma_tx; 1947 } 1948 1949 size *= dma_conf->dma_tx_size; 1950 1951 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1952 1953 kfree(tx_q->tx_skbuff_dma); 1954 kfree(tx_q->tx_skbuff); 1955 } 1956 1957 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1958 struct stmmac_dma_conf *dma_conf) 1959 { 1960 u32 tx_count = priv->plat->tx_queues_to_use; 1961 u32 queue; 1962 1963 /* Free TX queue resources */ 1964 for (queue = 0; queue < tx_count; queue++) 1965 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1966 } 1967 1968 /** 1969 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1970 * @priv: private structure 1971 * @dma_conf: structure to take the dma data 1972 * @queue: RX queue index 1973 * Description: according to which descriptor can be used (extend or basic) 1974 * this function allocates the resources for TX and RX paths. In case of 1975 * reception, for example, it pre-allocated the RX socket buffer in order to 1976 * allow zero-copy mechanism. 1977 */ 1978 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1979 struct stmmac_dma_conf *dma_conf, 1980 u32 queue) 1981 { 1982 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1983 struct stmmac_channel *ch = &priv->channel[queue]; 1984 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1985 struct page_pool_params pp_params = { 0 }; 1986 unsigned int num_pages; 1987 unsigned int napi_id; 1988 int ret; 1989 1990 rx_q->queue_index = queue; 1991 rx_q->priv_data = priv; 1992 1993 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1994 pp_params.pool_size = dma_conf->dma_rx_size; 1995 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 1996 pp_params.order = ilog2(num_pages); 1997 pp_params.nid = dev_to_node(priv->device); 1998 pp_params.dev = priv->device; 1999 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2000 pp_params.offset = stmmac_rx_offset(priv); 2001 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2002 2003 rx_q->page_pool = page_pool_create(&pp_params); 2004 if (IS_ERR(rx_q->page_pool)) { 2005 ret = PTR_ERR(rx_q->page_pool); 2006 rx_q->page_pool = NULL; 2007 return ret; 2008 } 2009 2010 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2011 sizeof(*rx_q->buf_pool), 2012 GFP_KERNEL); 2013 if (!rx_q->buf_pool) 2014 return -ENOMEM; 2015 2016 if (priv->extend_desc) { 2017 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2018 dma_conf->dma_rx_size * 2019 sizeof(struct dma_extended_desc), 2020 &rx_q->dma_rx_phy, 2021 GFP_KERNEL); 2022 if (!rx_q->dma_erx) 2023 return -ENOMEM; 2024 2025 } else { 2026 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2027 dma_conf->dma_rx_size * 2028 sizeof(struct dma_desc), 2029 &rx_q->dma_rx_phy, 2030 GFP_KERNEL); 2031 if (!rx_q->dma_rx) 2032 return -ENOMEM; 2033 } 2034 2035 if (stmmac_xdp_is_enabled(priv) && 2036 test_bit(queue, priv->af_xdp_zc_qps)) 2037 napi_id = ch->rxtx_napi.napi_id; 2038 else 2039 napi_id = ch->rx_napi.napi_id; 2040 2041 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2042 rx_q->queue_index, 2043 napi_id); 2044 if (ret) { 2045 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2046 return -EINVAL; 2047 } 2048 2049 return 0; 2050 } 2051 2052 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2053 struct stmmac_dma_conf *dma_conf) 2054 { 2055 u32 rx_count = priv->plat->rx_queues_to_use; 2056 u32 queue; 2057 int ret; 2058 2059 /* RX queues buffers and DMA */ 2060 for (queue = 0; queue < rx_count; queue++) { 2061 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2062 if (ret) 2063 goto err_dma; 2064 } 2065 2066 return 0; 2067 2068 err_dma: 2069 free_dma_rx_desc_resources(priv, dma_conf); 2070 2071 return ret; 2072 } 2073 2074 /** 2075 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2076 * @priv: private structure 2077 * @dma_conf: structure to take the dma data 2078 * @queue: TX queue index 2079 * Description: according to which descriptor can be used (extend or basic) 2080 * this function allocates the resources for TX and RX paths. In case of 2081 * reception, for example, it pre-allocated the RX socket buffer in order to 2082 * allow zero-copy mechanism. 2083 */ 2084 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2085 struct stmmac_dma_conf *dma_conf, 2086 u32 queue) 2087 { 2088 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2089 size_t size; 2090 void *addr; 2091 2092 tx_q->queue_index = queue; 2093 tx_q->priv_data = priv; 2094 2095 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2096 sizeof(*tx_q->tx_skbuff_dma), 2097 GFP_KERNEL); 2098 if (!tx_q->tx_skbuff_dma) 2099 return -ENOMEM; 2100 2101 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2102 sizeof(struct sk_buff *), 2103 GFP_KERNEL); 2104 if (!tx_q->tx_skbuff) 2105 return -ENOMEM; 2106 2107 if (priv->extend_desc) 2108 size = sizeof(struct dma_extended_desc); 2109 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2110 size = sizeof(struct dma_edesc); 2111 else 2112 size = sizeof(struct dma_desc); 2113 2114 size *= dma_conf->dma_tx_size; 2115 2116 addr = dma_alloc_coherent(priv->device, size, 2117 &tx_q->dma_tx_phy, GFP_KERNEL); 2118 if (!addr) 2119 return -ENOMEM; 2120 2121 if (priv->extend_desc) 2122 tx_q->dma_etx = addr; 2123 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2124 tx_q->dma_entx = addr; 2125 else 2126 tx_q->dma_tx = addr; 2127 2128 return 0; 2129 } 2130 2131 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2132 struct stmmac_dma_conf *dma_conf) 2133 { 2134 u32 tx_count = priv->plat->tx_queues_to_use; 2135 u32 queue; 2136 int ret; 2137 2138 /* TX queues buffers and DMA */ 2139 for (queue = 0; queue < tx_count; queue++) { 2140 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2141 if (ret) 2142 goto err_dma; 2143 } 2144 2145 return 0; 2146 2147 err_dma: 2148 free_dma_tx_desc_resources(priv, dma_conf); 2149 return ret; 2150 } 2151 2152 /** 2153 * alloc_dma_desc_resources - alloc TX/RX resources. 2154 * @priv: private structure 2155 * @dma_conf: structure to take the dma data 2156 * Description: according to which descriptor can be used (extend or basic) 2157 * this function allocates the resources for TX and RX paths. In case of 2158 * reception, for example, it pre-allocated the RX socket buffer in order to 2159 * allow zero-copy mechanism. 2160 */ 2161 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2162 struct stmmac_dma_conf *dma_conf) 2163 { 2164 /* RX Allocation */ 2165 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2166 2167 if (ret) 2168 return ret; 2169 2170 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2171 2172 return ret; 2173 } 2174 2175 /** 2176 * free_dma_desc_resources - free dma desc resources 2177 * @priv: private structure 2178 * @dma_conf: structure to take the dma data 2179 */ 2180 static void free_dma_desc_resources(struct stmmac_priv *priv, 2181 struct stmmac_dma_conf *dma_conf) 2182 { 2183 /* Release the DMA TX socket buffers */ 2184 free_dma_tx_desc_resources(priv, dma_conf); 2185 2186 /* Release the DMA RX socket buffers later 2187 * to ensure all pending XDP_TX buffers are returned. 2188 */ 2189 free_dma_rx_desc_resources(priv, dma_conf); 2190 } 2191 2192 /** 2193 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2194 * @priv: driver private structure 2195 * Description: It is used for enabling the rx queues in the MAC 2196 */ 2197 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2198 { 2199 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2200 int queue; 2201 u8 mode; 2202 2203 for (queue = 0; queue < rx_queues_count; queue++) { 2204 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2205 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2206 } 2207 } 2208 2209 /** 2210 * stmmac_start_rx_dma - start RX DMA channel 2211 * @priv: driver private structure 2212 * @chan: RX channel index 2213 * Description: 2214 * This starts a RX DMA channel 2215 */ 2216 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2217 { 2218 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2219 stmmac_start_rx(priv, priv->ioaddr, chan); 2220 } 2221 2222 /** 2223 * stmmac_start_tx_dma - start TX DMA channel 2224 * @priv: driver private structure 2225 * @chan: TX channel index 2226 * Description: 2227 * This starts a TX DMA channel 2228 */ 2229 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2230 { 2231 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2232 stmmac_start_tx(priv, priv->ioaddr, chan); 2233 } 2234 2235 /** 2236 * stmmac_stop_rx_dma - stop RX DMA channel 2237 * @priv: driver private structure 2238 * @chan: RX channel index 2239 * Description: 2240 * This stops a RX DMA channel 2241 */ 2242 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2243 { 2244 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2245 stmmac_stop_rx(priv, priv->ioaddr, chan); 2246 } 2247 2248 /** 2249 * stmmac_stop_tx_dma - stop TX DMA channel 2250 * @priv: driver private structure 2251 * @chan: TX channel index 2252 * Description: 2253 * This stops a TX DMA channel 2254 */ 2255 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2256 { 2257 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2258 stmmac_stop_tx(priv, priv->ioaddr, chan); 2259 } 2260 2261 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2262 { 2263 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2264 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2265 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2266 u32 chan; 2267 2268 for (chan = 0; chan < dma_csr_ch; chan++) { 2269 struct stmmac_channel *ch = &priv->channel[chan]; 2270 unsigned long flags; 2271 2272 spin_lock_irqsave(&ch->lock, flags); 2273 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2274 spin_unlock_irqrestore(&ch->lock, flags); 2275 } 2276 } 2277 2278 /** 2279 * stmmac_start_all_dma - start all RX and TX DMA channels 2280 * @priv: driver private structure 2281 * Description: 2282 * This starts all the RX and TX DMA channels 2283 */ 2284 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2285 { 2286 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2287 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2288 u32 chan = 0; 2289 2290 for (chan = 0; chan < rx_channels_count; chan++) 2291 stmmac_start_rx_dma(priv, chan); 2292 2293 for (chan = 0; chan < tx_channels_count; chan++) 2294 stmmac_start_tx_dma(priv, chan); 2295 } 2296 2297 /** 2298 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2299 * @priv: driver private structure 2300 * Description: 2301 * This stops the RX and TX DMA channels 2302 */ 2303 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2304 { 2305 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2306 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2307 u32 chan = 0; 2308 2309 for (chan = 0; chan < rx_channels_count; chan++) 2310 stmmac_stop_rx_dma(priv, chan); 2311 2312 for (chan = 0; chan < tx_channels_count; chan++) 2313 stmmac_stop_tx_dma(priv, chan); 2314 } 2315 2316 /** 2317 * stmmac_dma_operation_mode - HW DMA operation mode 2318 * @priv: driver private structure 2319 * Description: it is used for configuring the DMA operation mode register in 2320 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2321 */ 2322 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2323 { 2324 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2325 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2326 int rxfifosz = priv->plat->rx_fifo_size; 2327 int txfifosz = priv->plat->tx_fifo_size; 2328 u32 txmode = 0; 2329 u32 rxmode = 0; 2330 u32 chan = 0; 2331 u8 qmode = 0; 2332 2333 if (rxfifosz == 0) 2334 rxfifosz = priv->dma_cap.rx_fifo_size; 2335 if (txfifosz == 0) 2336 txfifosz = priv->dma_cap.tx_fifo_size; 2337 2338 /* Adjust for real per queue fifo size */ 2339 rxfifosz /= rx_channels_count; 2340 txfifosz /= tx_channels_count; 2341 2342 if (priv->plat->force_thresh_dma_mode) { 2343 txmode = tc; 2344 rxmode = tc; 2345 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2346 /* 2347 * In case of GMAC, SF mode can be enabled 2348 * to perform the TX COE in HW. This depends on: 2349 * 1) TX COE if actually supported 2350 * 2) There is no bugged Jumbo frame support 2351 * that needs to not insert csum in the TDES. 2352 */ 2353 txmode = SF_DMA_MODE; 2354 rxmode = SF_DMA_MODE; 2355 priv->xstats.threshold = SF_DMA_MODE; 2356 } else { 2357 txmode = tc; 2358 rxmode = SF_DMA_MODE; 2359 } 2360 2361 /* configure all channels */ 2362 for (chan = 0; chan < rx_channels_count; chan++) { 2363 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2364 u32 buf_size; 2365 2366 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2367 2368 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2369 rxfifosz, qmode); 2370 2371 if (rx_q->xsk_pool) { 2372 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2373 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2374 buf_size, 2375 chan); 2376 } else { 2377 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2378 priv->dma_conf.dma_buf_sz, 2379 chan); 2380 } 2381 } 2382 2383 for (chan = 0; chan < tx_channels_count; chan++) { 2384 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2385 2386 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2387 txfifosz, qmode); 2388 } 2389 } 2390 2391 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2392 { 2393 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2394 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2395 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2396 unsigned int entry = tx_q->cur_tx; 2397 struct dma_desc *tx_desc = NULL; 2398 struct xdp_desc xdp_desc; 2399 bool work_done = true; 2400 2401 /* Avoids TX time-out as we are sharing with slow path */ 2402 txq_trans_cond_update(nq); 2403 2404 budget = min(budget, stmmac_tx_avail(priv, queue)); 2405 2406 while (budget-- > 0) { 2407 dma_addr_t dma_addr; 2408 bool set_ic; 2409 2410 /* We are sharing with slow path and stop XSK TX desc submission when 2411 * available TX ring is less than threshold. 2412 */ 2413 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2414 !netif_carrier_ok(priv->dev)) { 2415 work_done = false; 2416 break; 2417 } 2418 2419 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2420 break; 2421 2422 if (likely(priv->extend_desc)) 2423 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2424 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2425 tx_desc = &tx_q->dma_entx[entry].basic; 2426 else 2427 tx_desc = tx_q->dma_tx + entry; 2428 2429 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2430 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2431 2432 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2433 2434 /* To return XDP buffer to XSK pool, we simple call 2435 * xsk_tx_completed(), so we don't need to fill up 2436 * 'buf' and 'xdpf'. 2437 */ 2438 tx_q->tx_skbuff_dma[entry].buf = 0; 2439 tx_q->xdpf[entry] = NULL; 2440 2441 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2442 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2443 tx_q->tx_skbuff_dma[entry].last_segment = true; 2444 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2445 2446 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2447 2448 tx_q->tx_count_frames++; 2449 2450 if (!priv->tx_coal_frames[queue]) 2451 set_ic = false; 2452 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2453 set_ic = true; 2454 else 2455 set_ic = false; 2456 2457 if (set_ic) { 2458 tx_q->tx_count_frames = 0; 2459 stmmac_set_tx_ic(priv, tx_desc); 2460 priv->xstats.tx_set_ic_bit++; 2461 } 2462 2463 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2464 true, priv->mode, true, true, 2465 xdp_desc.len); 2466 2467 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2468 2469 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2470 entry = tx_q->cur_tx; 2471 } 2472 2473 if (tx_desc) { 2474 stmmac_flush_tx_descriptors(priv, queue); 2475 xsk_tx_release(pool); 2476 } 2477 2478 /* Return true if all of the 3 conditions are met 2479 * a) TX Budget is still available 2480 * b) work_done = true when XSK TX desc peek is empty (no more 2481 * pending XSK TX for transmission) 2482 */ 2483 return !!budget && work_done; 2484 } 2485 2486 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2487 { 2488 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2489 tc += 64; 2490 2491 if (priv->plat->force_thresh_dma_mode) 2492 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2493 else 2494 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2495 chan); 2496 2497 priv->xstats.threshold = tc; 2498 } 2499 } 2500 2501 /** 2502 * stmmac_tx_clean - to manage the transmission completion 2503 * @priv: driver private structure 2504 * @budget: napi budget limiting this functions packet handling 2505 * @queue: TX queue index 2506 * Description: it reclaims the transmit resources after transmission completes. 2507 */ 2508 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2509 { 2510 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2511 unsigned int bytes_compl = 0, pkts_compl = 0; 2512 unsigned int entry, xmits = 0, count = 0; 2513 2514 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2515 2516 priv->xstats.tx_clean++; 2517 2518 tx_q->xsk_frames_done = 0; 2519 2520 entry = tx_q->dirty_tx; 2521 2522 /* Try to clean all TX complete frame in 1 shot */ 2523 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2524 struct xdp_frame *xdpf; 2525 struct sk_buff *skb; 2526 struct dma_desc *p; 2527 int status; 2528 2529 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2530 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2531 xdpf = tx_q->xdpf[entry]; 2532 skb = NULL; 2533 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2534 xdpf = NULL; 2535 skb = tx_q->tx_skbuff[entry]; 2536 } else { 2537 xdpf = NULL; 2538 skb = NULL; 2539 } 2540 2541 if (priv->extend_desc) 2542 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2543 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2544 p = &tx_q->dma_entx[entry].basic; 2545 else 2546 p = tx_q->dma_tx + entry; 2547 2548 status = stmmac_tx_status(priv, &priv->dev->stats, 2549 &priv->xstats, p, priv->ioaddr); 2550 /* Check if the descriptor is owned by the DMA */ 2551 if (unlikely(status & tx_dma_own)) 2552 break; 2553 2554 count++; 2555 2556 /* Make sure descriptor fields are read after reading 2557 * the own bit. 2558 */ 2559 dma_rmb(); 2560 2561 /* Just consider the last segment and ...*/ 2562 if (likely(!(status & tx_not_ls))) { 2563 /* ... verify the status error condition */ 2564 if (unlikely(status & tx_err)) { 2565 priv->dev->stats.tx_errors++; 2566 if (unlikely(status & tx_err_bump_tc)) 2567 stmmac_bump_dma_threshold(priv, queue); 2568 } else { 2569 priv->dev->stats.tx_packets++; 2570 priv->xstats.tx_pkt_n++; 2571 priv->xstats.txq_stats[queue].tx_pkt_n++; 2572 } 2573 if (skb) 2574 stmmac_get_tx_hwtstamp(priv, p, skb); 2575 } 2576 2577 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2578 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2579 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2580 dma_unmap_page(priv->device, 2581 tx_q->tx_skbuff_dma[entry].buf, 2582 tx_q->tx_skbuff_dma[entry].len, 2583 DMA_TO_DEVICE); 2584 else 2585 dma_unmap_single(priv->device, 2586 tx_q->tx_skbuff_dma[entry].buf, 2587 tx_q->tx_skbuff_dma[entry].len, 2588 DMA_TO_DEVICE); 2589 tx_q->tx_skbuff_dma[entry].buf = 0; 2590 tx_q->tx_skbuff_dma[entry].len = 0; 2591 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2592 } 2593 2594 stmmac_clean_desc3(priv, tx_q, p); 2595 2596 tx_q->tx_skbuff_dma[entry].last_segment = false; 2597 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2598 2599 if (xdpf && 2600 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2601 xdp_return_frame_rx_napi(xdpf); 2602 tx_q->xdpf[entry] = NULL; 2603 } 2604 2605 if (xdpf && 2606 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2607 xdp_return_frame(xdpf); 2608 tx_q->xdpf[entry] = NULL; 2609 } 2610 2611 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2612 tx_q->xsk_frames_done++; 2613 2614 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2615 if (likely(skb)) { 2616 pkts_compl++; 2617 bytes_compl += skb->len; 2618 dev_consume_skb_any(skb); 2619 tx_q->tx_skbuff[entry] = NULL; 2620 } 2621 } 2622 2623 stmmac_release_tx_desc(priv, p, priv->mode); 2624 2625 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2626 } 2627 tx_q->dirty_tx = entry; 2628 2629 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2630 pkts_compl, bytes_compl); 2631 2632 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2633 queue))) && 2634 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2635 2636 netif_dbg(priv, tx_done, priv->dev, 2637 "%s: restart transmit\n", __func__); 2638 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2639 } 2640 2641 if (tx_q->xsk_pool) { 2642 bool work_done; 2643 2644 if (tx_q->xsk_frames_done) 2645 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2646 2647 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2648 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2649 2650 /* For XSK TX, we try to send as many as possible. 2651 * If XSK work done (XSK TX desc empty and budget still 2652 * available), return "budget - 1" to reenable TX IRQ. 2653 * Else, return "budget" to make NAPI continue polling. 2654 */ 2655 work_done = stmmac_xdp_xmit_zc(priv, queue, 2656 STMMAC_XSK_TX_BUDGET_MAX); 2657 if (work_done) 2658 xmits = budget - 1; 2659 else 2660 xmits = budget; 2661 } 2662 2663 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2664 priv->eee_sw_timer_en) { 2665 if (stmmac_enable_eee_mode(priv)) 2666 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2667 } 2668 2669 /* We still have pending packets, let's call for a new scheduling */ 2670 if (tx_q->dirty_tx != tx_q->cur_tx) 2671 hrtimer_start(&tx_q->txtimer, 2672 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2673 HRTIMER_MODE_REL); 2674 2675 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2676 2677 /* Combine decisions from TX clean and XSK TX */ 2678 return max(count, xmits); 2679 } 2680 2681 /** 2682 * stmmac_tx_err - to manage the tx error 2683 * @priv: driver private structure 2684 * @chan: channel index 2685 * Description: it cleans the descriptors and restarts the transmission 2686 * in case of transmission errors. 2687 */ 2688 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2689 { 2690 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2691 2692 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2693 2694 stmmac_stop_tx_dma(priv, chan); 2695 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2696 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2697 stmmac_reset_tx_queue(priv, chan); 2698 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2699 tx_q->dma_tx_phy, chan); 2700 stmmac_start_tx_dma(priv, chan); 2701 2702 priv->dev->stats.tx_errors++; 2703 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2704 } 2705 2706 /** 2707 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2708 * @priv: driver private structure 2709 * @txmode: TX operating mode 2710 * @rxmode: RX operating mode 2711 * @chan: channel index 2712 * Description: it is used for configuring of the DMA operation mode in 2713 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2714 * mode. 2715 */ 2716 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2717 u32 rxmode, u32 chan) 2718 { 2719 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2720 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2721 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2722 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2723 int rxfifosz = priv->plat->rx_fifo_size; 2724 int txfifosz = priv->plat->tx_fifo_size; 2725 2726 if (rxfifosz == 0) 2727 rxfifosz = priv->dma_cap.rx_fifo_size; 2728 if (txfifosz == 0) 2729 txfifosz = priv->dma_cap.tx_fifo_size; 2730 2731 /* Adjust for real per queue fifo size */ 2732 rxfifosz /= rx_channels_count; 2733 txfifosz /= tx_channels_count; 2734 2735 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2736 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2737 } 2738 2739 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2740 { 2741 int ret; 2742 2743 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2744 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2745 if (ret && (ret != -EINVAL)) { 2746 stmmac_global_err(priv); 2747 return true; 2748 } 2749 2750 return false; 2751 } 2752 2753 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2754 { 2755 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2756 &priv->xstats, chan, dir); 2757 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2758 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2759 struct stmmac_channel *ch = &priv->channel[chan]; 2760 struct napi_struct *rx_napi; 2761 struct napi_struct *tx_napi; 2762 unsigned long flags; 2763 2764 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2765 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2766 2767 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2768 if (napi_schedule_prep(rx_napi)) { 2769 spin_lock_irqsave(&ch->lock, flags); 2770 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2771 spin_unlock_irqrestore(&ch->lock, flags); 2772 __napi_schedule(rx_napi); 2773 } 2774 } 2775 2776 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2777 if (napi_schedule_prep(tx_napi)) { 2778 spin_lock_irqsave(&ch->lock, flags); 2779 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2780 spin_unlock_irqrestore(&ch->lock, flags); 2781 __napi_schedule(tx_napi); 2782 } 2783 } 2784 2785 return status; 2786 } 2787 2788 /** 2789 * stmmac_dma_interrupt - DMA ISR 2790 * @priv: driver private structure 2791 * Description: this is the DMA ISR. It is called by the main ISR. 2792 * It calls the dwmac dma routine and schedule poll method in case of some 2793 * work can be done. 2794 */ 2795 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2796 { 2797 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2798 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2799 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2800 tx_channel_count : rx_channel_count; 2801 u32 chan; 2802 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2803 2804 /* Make sure we never check beyond our status buffer. */ 2805 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2806 channels_to_check = ARRAY_SIZE(status); 2807 2808 for (chan = 0; chan < channels_to_check; chan++) 2809 status[chan] = stmmac_napi_check(priv, chan, 2810 DMA_DIR_RXTX); 2811 2812 for (chan = 0; chan < tx_channel_count; chan++) { 2813 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2814 /* Try to bump up the dma threshold on this failure */ 2815 stmmac_bump_dma_threshold(priv, chan); 2816 } else if (unlikely(status[chan] == tx_hard_error)) { 2817 stmmac_tx_err(priv, chan); 2818 } 2819 } 2820 } 2821 2822 /** 2823 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2824 * @priv: driver private structure 2825 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2826 */ 2827 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2828 { 2829 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2830 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2831 2832 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2833 2834 if (priv->dma_cap.rmon) { 2835 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2836 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2837 } else 2838 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2839 } 2840 2841 /** 2842 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2843 * @priv: driver private structure 2844 * Description: 2845 * new GMAC chip generations have a new register to indicate the 2846 * presence of the optional feature/functions. 2847 * This can be also used to override the value passed through the 2848 * platform and necessary for old MAC10/100 and GMAC chips. 2849 */ 2850 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2851 { 2852 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2853 } 2854 2855 /** 2856 * stmmac_check_ether_addr - check if the MAC addr is valid 2857 * @priv: driver private structure 2858 * Description: 2859 * it is to verify if the MAC address is valid, in case of failures it 2860 * generates a random MAC address 2861 */ 2862 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2863 { 2864 u8 addr[ETH_ALEN]; 2865 2866 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2867 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2868 if (is_valid_ether_addr(addr)) 2869 eth_hw_addr_set(priv->dev, addr); 2870 else 2871 eth_hw_addr_random(priv->dev); 2872 dev_info(priv->device, "device MAC address %pM\n", 2873 priv->dev->dev_addr); 2874 } 2875 } 2876 2877 /** 2878 * stmmac_init_dma_engine - DMA init. 2879 * @priv: driver private structure 2880 * Description: 2881 * It inits the DMA invoking the specific MAC/GMAC callback. 2882 * Some DMA parameters can be passed from the platform; 2883 * in case of these are not passed a default is kept for the MAC or GMAC. 2884 */ 2885 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2886 { 2887 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2888 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2889 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2890 struct stmmac_rx_queue *rx_q; 2891 struct stmmac_tx_queue *tx_q; 2892 u32 chan = 0; 2893 int atds = 0; 2894 int ret = 0; 2895 2896 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2897 dev_err(priv->device, "Invalid DMA configuration\n"); 2898 return -EINVAL; 2899 } 2900 2901 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2902 atds = 1; 2903 2904 ret = stmmac_reset(priv, priv->ioaddr); 2905 if (ret) { 2906 dev_err(priv->device, "Failed to reset the dma\n"); 2907 return ret; 2908 } 2909 2910 /* DMA Configuration */ 2911 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2912 2913 if (priv->plat->axi) 2914 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2915 2916 /* DMA CSR Channel configuration */ 2917 for (chan = 0; chan < dma_csr_ch; chan++) { 2918 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2919 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2920 } 2921 2922 /* DMA RX Channel Configuration */ 2923 for (chan = 0; chan < rx_channels_count; chan++) { 2924 rx_q = &priv->dma_conf.rx_queue[chan]; 2925 2926 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2927 rx_q->dma_rx_phy, chan); 2928 2929 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2930 (rx_q->buf_alloc_num * 2931 sizeof(struct dma_desc)); 2932 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2933 rx_q->rx_tail_addr, chan); 2934 } 2935 2936 /* DMA TX Channel Configuration */ 2937 for (chan = 0; chan < tx_channels_count; chan++) { 2938 tx_q = &priv->dma_conf.tx_queue[chan]; 2939 2940 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2941 tx_q->dma_tx_phy, chan); 2942 2943 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2944 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2945 tx_q->tx_tail_addr, chan); 2946 } 2947 2948 return ret; 2949 } 2950 2951 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2952 { 2953 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2954 2955 hrtimer_start(&tx_q->txtimer, 2956 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2957 HRTIMER_MODE_REL); 2958 } 2959 2960 /** 2961 * stmmac_tx_timer - mitigation sw timer for tx. 2962 * @t: data pointer 2963 * Description: 2964 * This is the timer handler to directly invoke the stmmac_tx_clean. 2965 */ 2966 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2967 { 2968 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2969 struct stmmac_priv *priv = tx_q->priv_data; 2970 struct stmmac_channel *ch; 2971 struct napi_struct *napi; 2972 2973 ch = &priv->channel[tx_q->queue_index]; 2974 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2975 2976 if (likely(napi_schedule_prep(napi))) { 2977 unsigned long flags; 2978 2979 spin_lock_irqsave(&ch->lock, flags); 2980 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2981 spin_unlock_irqrestore(&ch->lock, flags); 2982 __napi_schedule(napi); 2983 } 2984 2985 return HRTIMER_NORESTART; 2986 } 2987 2988 /** 2989 * stmmac_init_coalesce - init mitigation options. 2990 * @priv: driver private structure 2991 * Description: 2992 * This inits the coalesce parameters: i.e. timer rate, 2993 * timer handler and default threshold used for enabling the 2994 * interrupt on completion bit. 2995 */ 2996 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2997 { 2998 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2999 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3000 u32 chan; 3001 3002 for (chan = 0; chan < tx_channel_count; chan++) { 3003 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3004 3005 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3006 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3007 3008 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3009 tx_q->txtimer.function = stmmac_tx_timer; 3010 } 3011 3012 for (chan = 0; chan < rx_channel_count; chan++) 3013 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3014 } 3015 3016 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3017 { 3018 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3019 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3020 u32 chan; 3021 3022 /* set TX ring length */ 3023 for (chan = 0; chan < tx_channels_count; chan++) 3024 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3025 (priv->dma_conf.dma_tx_size - 1), chan); 3026 3027 /* set RX ring length */ 3028 for (chan = 0; chan < rx_channels_count; chan++) 3029 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3030 (priv->dma_conf.dma_rx_size - 1), chan); 3031 } 3032 3033 /** 3034 * stmmac_set_tx_queue_weight - Set TX queue weight 3035 * @priv: driver private structure 3036 * Description: It is used for setting TX queues weight 3037 */ 3038 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3039 { 3040 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3041 u32 weight; 3042 u32 queue; 3043 3044 for (queue = 0; queue < tx_queues_count; queue++) { 3045 weight = priv->plat->tx_queues_cfg[queue].weight; 3046 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3047 } 3048 } 3049 3050 /** 3051 * stmmac_configure_cbs - Configure CBS in TX queue 3052 * @priv: driver private structure 3053 * Description: It is used for configuring CBS in AVB TX queues 3054 */ 3055 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3056 { 3057 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3058 u32 mode_to_use; 3059 u32 queue; 3060 3061 /* queue 0 is reserved for legacy traffic */ 3062 for (queue = 1; queue < tx_queues_count; queue++) { 3063 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3064 if (mode_to_use == MTL_QUEUE_DCB) 3065 continue; 3066 3067 stmmac_config_cbs(priv, priv->hw, 3068 priv->plat->tx_queues_cfg[queue].send_slope, 3069 priv->plat->tx_queues_cfg[queue].idle_slope, 3070 priv->plat->tx_queues_cfg[queue].high_credit, 3071 priv->plat->tx_queues_cfg[queue].low_credit, 3072 queue); 3073 } 3074 } 3075 3076 /** 3077 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3078 * @priv: driver private structure 3079 * Description: It is used for mapping RX queues to RX dma channels 3080 */ 3081 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3082 { 3083 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3084 u32 queue; 3085 u32 chan; 3086 3087 for (queue = 0; queue < rx_queues_count; queue++) { 3088 chan = priv->plat->rx_queues_cfg[queue].chan; 3089 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3090 } 3091 } 3092 3093 /** 3094 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3095 * @priv: driver private structure 3096 * Description: It is used for configuring the RX Queue Priority 3097 */ 3098 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3099 { 3100 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3101 u32 queue; 3102 u32 prio; 3103 3104 for (queue = 0; queue < rx_queues_count; queue++) { 3105 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3106 continue; 3107 3108 prio = priv->plat->rx_queues_cfg[queue].prio; 3109 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3110 } 3111 } 3112 3113 /** 3114 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3115 * @priv: driver private structure 3116 * Description: It is used for configuring the TX Queue Priority 3117 */ 3118 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3119 { 3120 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3121 u32 queue; 3122 u32 prio; 3123 3124 for (queue = 0; queue < tx_queues_count; queue++) { 3125 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3126 continue; 3127 3128 prio = priv->plat->tx_queues_cfg[queue].prio; 3129 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3130 } 3131 } 3132 3133 /** 3134 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3135 * @priv: driver private structure 3136 * Description: It is used for configuring the RX queue routing 3137 */ 3138 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3139 { 3140 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3141 u32 queue; 3142 u8 packet; 3143 3144 for (queue = 0; queue < rx_queues_count; queue++) { 3145 /* no specific packet type routing specified for the queue */ 3146 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3147 continue; 3148 3149 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3150 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3151 } 3152 } 3153 3154 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3155 { 3156 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3157 priv->rss.enable = false; 3158 return; 3159 } 3160 3161 if (priv->dev->features & NETIF_F_RXHASH) 3162 priv->rss.enable = true; 3163 else 3164 priv->rss.enable = false; 3165 3166 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3167 priv->plat->rx_queues_to_use); 3168 } 3169 3170 /** 3171 * stmmac_mtl_configuration - Configure MTL 3172 * @priv: driver private structure 3173 * Description: It is used for configurring MTL 3174 */ 3175 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3176 { 3177 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3178 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3179 3180 if (tx_queues_count > 1) 3181 stmmac_set_tx_queue_weight(priv); 3182 3183 /* Configure MTL RX algorithms */ 3184 if (rx_queues_count > 1) 3185 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3186 priv->plat->rx_sched_algorithm); 3187 3188 /* Configure MTL TX algorithms */ 3189 if (tx_queues_count > 1) 3190 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3191 priv->plat->tx_sched_algorithm); 3192 3193 /* Configure CBS in AVB TX queues */ 3194 if (tx_queues_count > 1) 3195 stmmac_configure_cbs(priv); 3196 3197 /* Map RX MTL to DMA channels */ 3198 stmmac_rx_queue_dma_chan_map(priv); 3199 3200 /* Enable MAC RX Queues */ 3201 stmmac_mac_enable_rx_queues(priv); 3202 3203 /* Set RX priorities */ 3204 if (rx_queues_count > 1) 3205 stmmac_mac_config_rx_queues_prio(priv); 3206 3207 /* Set TX priorities */ 3208 if (tx_queues_count > 1) 3209 stmmac_mac_config_tx_queues_prio(priv); 3210 3211 /* Set RX routing */ 3212 if (rx_queues_count > 1) 3213 stmmac_mac_config_rx_queues_routing(priv); 3214 3215 /* Receive Side Scaling */ 3216 if (rx_queues_count > 1) 3217 stmmac_mac_config_rss(priv); 3218 } 3219 3220 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3221 { 3222 if (priv->dma_cap.asp) { 3223 netdev_info(priv->dev, "Enabling Safety Features\n"); 3224 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3225 priv->plat->safety_feat_cfg); 3226 } else { 3227 netdev_info(priv->dev, "No Safety Features support found\n"); 3228 } 3229 } 3230 3231 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3232 { 3233 char *name; 3234 3235 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3236 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3237 3238 name = priv->wq_name; 3239 sprintf(name, "%s-fpe", priv->dev->name); 3240 3241 priv->fpe_wq = create_singlethread_workqueue(name); 3242 if (!priv->fpe_wq) { 3243 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3244 3245 return -ENOMEM; 3246 } 3247 netdev_info(priv->dev, "FPE workqueue start"); 3248 3249 return 0; 3250 } 3251 3252 /** 3253 * stmmac_hw_setup - setup mac in a usable state. 3254 * @dev : pointer to the device structure. 3255 * @ptp_register: register PTP if set 3256 * Description: 3257 * this is the main function to setup the HW in a usable state because the 3258 * dma engine is reset, the core registers are configured (e.g. AXI, 3259 * Checksum features, timers). The DMA is ready to start receiving and 3260 * transmitting. 3261 * Return value: 3262 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3263 * file on failure. 3264 */ 3265 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3266 { 3267 struct stmmac_priv *priv = netdev_priv(dev); 3268 u32 rx_cnt = priv->plat->rx_queues_to_use; 3269 u32 tx_cnt = priv->plat->tx_queues_to_use; 3270 bool sph_en; 3271 u32 chan; 3272 int ret; 3273 3274 /* DMA initialization and SW reset */ 3275 ret = stmmac_init_dma_engine(priv); 3276 if (ret < 0) { 3277 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3278 __func__); 3279 return ret; 3280 } 3281 3282 /* Copy the MAC addr into the HW */ 3283 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3284 3285 /* PS and related bits will be programmed according to the speed */ 3286 if (priv->hw->pcs) { 3287 int speed = priv->plat->mac_port_sel_speed; 3288 3289 if ((speed == SPEED_10) || (speed == SPEED_100) || 3290 (speed == SPEED_1000)) { 3291 priv->hw->ps = speed; 3292 } else { 3293 dev_warn(priv->device, "invalid port speed\n"); 3294 priv->hw->ps = 0; 3295 } 3296 } 3297 3298 /* Initialize the MAC Core */ 3299 stmmac_core_init(priv, priv->hw, dev); 3300 3301 /* Initialize MTL*/ 3302 stmmac_mtl_configuration(priv); 3303 3304 /* Initialize Safety Features */ 3305 stmmac_safety_feat_configuration(priv); 3306 3307 ret = stmmac_rx_ipc(priv, priv->hw); 3308 if (!ret) { 3309 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3310 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3311 priv->hw->rx_csum = 0; 3312 } 3313 3314 /* Enable the MAC Rx/Tx */ 3315 stmmac_mac_set(priv, priv->ioaddr, true); 3316 3317 /* Set the HW DMA mode and the COE */ 3318 stmmac_dma_operation_mode(priv); 3319 3320 stmmac_mmc_setup(priv); 3321 3322 if (ptp_register) { 3323 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3324 if (ret < 0) 3325 netdev_warn(priv->dev, 3326 "failed to enable PTP reference clock: %pe\n", 3327 ERR_PTR(ret)); 3328 } 3329 3330 ret = stmmac_init_ptp(priv); 3331 if (ret == -EOPNOTSUPP) 3332 netdev_info(priv->dev, "PTP not supported by HW\n"); 3333 else if (ret) 3334 netdev_warn(priv->dev, "PTP init failed\n"); 3335 else if (ptp_register) 3336 stmmac_ptp_register(priv); 3337 3338 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3339 3340 /* Convert the timer from msec to usec */ 3341 if (!priv->tx_lpi_timer) 3342 priv->tx_lpi_timer = eee_timer * 1000; 3343 3344 if (priv->use_riwt) { 3345 u32 queue; 3346 3347 for (queue = 0; queue < rx_cnt; queue++) { 3348 if (!priv->rx_riwt[queue]) 3349 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3350 3351 stmmac_rx_watchdog(priv, priv->ioaddr, 3352 priv->rx_riwt[queue], queue); 3353 } 3354 } 3355 3356 if (priv->hw->pcs) 3357 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3358 3359 /* set TX and RX rings length */ 3360 stmmac_set_rings_length(priv); 3361 3362 /* Enable TSO */ 3363 if (priv->tso) { 3364 for (chan = 0; chan < tx_cnt; chan++) { 3365 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3366 3367 /* TSO and TBS cannot co-exist */ 3368 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3369 continue; 3370 3371 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3372 } 3373 } 3374 3375 /* Enable Split Header */ 3376 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3377 for (chan = 0; chan < rx_cnt; chan++) 3378 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3379 3380 3381 /* VLAN Tag Insertion */ 3382 if (priv->dma_cap.vlins) 3383 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3384 3385 /* TBS */ 3386 for (chan = 0; chan < tx_cnt; chan++) { 3387 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3388 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3389 3390 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3391 } 3392 3393 /* Configure real RX and TX queues */ 3394 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3395 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3396 3397 /* Start the ball rolling... */ 3398 stmmac_start_all_dma(priv); 3399 3400 if (priv->dma_cap.fpesel) { 3401 stmmac_fpe_start_wq(priv); 3402 3403 if (priv->plat->fpe_cfg->enable) 3404 stmmac_fpe_handshake(priv, true); 3405 } 3406 3407 return 0; 3408 } 3409 3410 static void stmmac_hw_teardown(struct net_device *dev) 3411 { 3412 struct stmmac_priv *priv = netdev_priv(dev); 3413 3414 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3415 } 3416 3417 static void stmmac_free_irq(struct net_device *dev, 3418 enum request_irq_err irq_err, int irq_idx) 3419 { 3420 struct stmmac_priv *priv = netdev_priv(dev); 3421 int j; 3422 3423 switch (irq_err) { 3424 case REQ_IRQ_ERR_ALL: 3425 irq_idx = priv->plat->tx_queues_to_use; 3426 fallthrough; 3427 case REQ_IRQ_ERR_TX: 3428 for (j = irq_idx - 1; j >= 0; j--) { 3429 if (priv->tx_irq[j] > 0) { 3430 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3431 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3432 } 3433 } 3434 irq_idx = priv->plat->rx_queues_to_use; 3435 fallthrough; 3436 case REQ_IRQ_ERR_RX: 3437 for (j = irq_idx - 1; j >= 0; j--) { 3438 if (priv->rx_irq[j] > 0) { 3439 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3440 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3441 } 3442 } 3443 3444 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3445 free_irq(priv->sfty_ue_irq, dev); 3446 fallthrough; 3447 case REQ_IRQ_ERR_SFTY_UE: 3448 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3449 free_irq(priv->sfty_ce_irq, dev); 3450 fallthrough; 3451 case REQ_IRQ_ERR_SFTY_CE: 3452 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3453 free_irq(priv->lpi_irq, dev); 3454 fallthrough; 3455 case REQ_IRQ_ERR_LPI: 3456 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3457 free_irq(priv->wol_irq, dev); 3458 fallthrough; 3459 case REQ_IRQ_ERR_WOL: 3460 free_irq(dev->irq, dev); 3461 fallthrough; 3462 case REQ_IRQ_ERR_MAC: 3463 case REQ_IRQ_ERR_NO: 3464 /* If MAC IRQ request error, no more IRQ to free */ 3465 break; 3466 } 3467 } 3468 3469 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3470 { 3471 struct stmmac_priv *priv = netdev_priv(dev); 3472 enum request_irq_err irq_err; 3473 cpumask_t cpu_mask; 3474 int irq_idx = 0; 3475 char *int_name; 3476 int ret; 3477 int i; 3478 3479 /* For common interrupt */ 3480 int_name = priv->int_name_mac; 3481 sprintf(int_name, "%s:%s", dev->name, "mac"); 3482 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3483 0, int_name, dev); 3484 if (unlikely(ret < 0)) { 3485 netdev_err(priv->dev, 3486 "%s: alloc mac MSI %d (error: %d)\n", 3487 __func__, dev->irq, ret); 3488 irq_err = REQ_IRQ_ERR_MAC; 3489 goto irq_error; 3490 } 3491 3492 /* Request the Wake IRQ in case of another line 3493 * is used for WoL 3494 */ 3495 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3496 int_name = priv->int_name_wol; 3497 sprintf(int_name, "%s:%s", dev->name, "wol"); 3498 ret = request_irq(priv->wol_irq, 3499 stmmac_mac_interrupt, 3500 0, int_name, dev); 3501 if (unlikely(ret < 0)) { 3502 netdev_err(priv->dev, 3503 "%s: alloc wol MSI %d (error: %d)\n", 3504 __func__, priv->wol_irq, ret); 3505 irq_err = REQ_IRQ_ERR_WOL; 3506 goto irq_error; 3507 } 3508 } 3509 3510 /* Request the LPI IRQ in case of another line 3511 * is used for LPI 3512 */ 3513 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3514 int_name = priv->int_name_lpi; 3515 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3516 ret = request_irq(priv->lpi_irq, 3517 stmmac_mac_interrupt, 3518 0, int_name, dev); 3519 if (unlikely(ret < 0)) { 3520 netdev_err(priv->dev, 3521 "%s: alloc lpi MSI %d (error: %d)\n", 3522 __func__, priv->lpi_irq, ret); 3523 irq_err = REQ_IRQ_ERR_LPI; 3524 goto irq_error; 3525 } 3526 } 3527 3528 /* Request the Safety Feature Correctible Error line in 3529 * case of another line is used 3530 */ 3531 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3532 int_name = priv->int_name_sfty_ce; 3533 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3534 ret = request_irq(priv->sfty_ce_irq, 3535 stmmac_safety_interrupt, 3536 0, int_name, dev); 3537 if (unlikely(ret < 0)) { 3538 netdev_err(priv->dev, 3539 "%s: alloc sfty ce MSI %d (error: %d)\n", 3540 __func__, priv->sfty_ce_irq, ret); 3541 irq_err = REQ_IRQ_ERR_SFTY_CE; 3542 goto irq_error; 3543 } 3544 } 3545 3546 /* Request the Safety Feature Uncorrectible Error line in 3547 * case of another line is used 3548 */ 3549 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3550 int_name = priv->int_name_sfty_ue; 3551 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3552 ret = request_irq(priv->sfty_ue_irq, 3553 stmmac_safety_interrupt, 3554 0, int_name, dev); 3555 if (unlikely(ret < 0)) { 3556 netdev_err(priv->dev, 3557 "%s: alloc sfty ue MSI %d (error: %d)\n", 3558 __func__, priv->sfty_ue_irq, ret); 3559 irq_err = REQ_IRQ_ERR_SFTY_UE; 3560 goto irq_error; 3561 } 3562 } 3563 3564 /* Request Rx MSI irq */ 3565 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3566 if (i >= MTL_MAX_RX_QUEUES) 3567 break; 3568 if (priv->rx_irq[i] == 0) 3569 continue; 3570 3571 int_name = priv->int_name_rx_irq[i]; 3572 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3573 ret = request_irq(priv->rx_irq[i], 3574 stmmac_msi_intr_rx, 3575 0, int_name, &priv->dma_conf.rx_queue[i]); 3576 if (unlikely(ret < 0)) { 3577 netdev_err(priv->dev, 3578 "%s: alloc rx-%d MSI %d (error: %d)\n", 3579 __func__, i, priv->rx_irq[i], ret); 3580 irq_err = REQ_IRQ_ERR_RX; 3581 irq_idx = i; 3582 goto irq_error; 3583 } 3584 cpumask_clear(&cpu_mask); 3585 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3586 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3587 } 3588 3589 /* Request Tx MSI irq */ 3590 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3591 if (i >= MTL_MAX_TX_QUEUES) 3592 break; 3593 if (priv->tx_irq[i] == 0) 3594 continue; 3595 3596 int_name = priv->int_name_tx_irq[i]; 3597 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3598 ret = request_irq(priv->tx_irq[i], 3599 stmmac_msi_intr_tx, 3600 0, int_name, &priv->dma_conf.tx_queue[i]); 3601 if (unlikely(ret < 0)) { 3602 netdev_err(priv->dev, 3603 "%s: alloc tx-%d MSI %d (error: %d)\n", 3604 __func__, i, priv->tx_irq[i], ret); 3605 irq_err = REQ_IRQ_ERR_TX; 3606 irq_idx = i; 3607 goto irq_error; 3608 } 3609 cpumask_clear(&cpu_mask); 3610 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3611 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3612 } 3613 3614 return 0; 3615 3616 irq_error: 3617 stmmac_free_irq(dev, irq_err, irq_idx); 3618 return ret; 3619 } 3620 3621 static int stmmac_request_irq_single(struct net_device *dev) 3622 { 3623 struct stmmac_priv *priv = netdev_priv(dev); 3624 enum request_irq_err irq_err; 3625 int ret; 3626 3627 ret = request_irq(dev->irq, stmmac_interrupt, 3628 IRQF_SHARED, dev->name, dev); 3629 if (unlikely(ret < 0)) { 3630 netdev_err(priv->dev, 3631 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3632 __func__, dev->irq, ret); 3633 irq_err = REQ_IRQ_ERR_MAC; 3634 goto irq_error; 3635 } 3636 3637 /* Request the Wake IRQ in case of another line 3638 * is used for WoL 3639 */ 3640 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3641 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3642 IRQF_SHARED, dev->name, dev); 3643 if (unlikely(ret < 0)) { 3644 netdev_err(priv->dev, 3645 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3646 __func__, priv->wol_irq, ret); 3647 irq_err = REQ_IRQ_ERR_WOL; 3648 goto irq_error; 3649 } 3650 } 3651 3652 /* Request the IRQ lines */ 3653 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3654 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3655 IRQF_SHARED, dev->name, dev); 3656 if (unlikely(ret < 0)) { 3657 netdev_err(priv->dev, 3658 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3659 __func__, priv->lpi_irq, ret); 3660 irq_err = REQ_IRQ_ERR_LPI; 3661 goto irq_error; 3662 } 3663 } 3664 3665 return 0; 3666 3667 irq_error: 3668 stmmac_free_irq(dev, irq_err, 0); 3669 return ret; 3670 } 3671 3672 static int stmmac_request_irq(struct net_device *dev) 3673 { 3674 struct stmmac_priv *priv = netdev_priv(dev); 3675 int ret; 3676 3677 /* Request the IRQ lines */ 3678 if (priv->plat->multi_msi_en) 3679 ret = stmmac_request_irq_multi_msi(dev); 3680 else 3681 ret = stmmac_request_irq_single(dev); 3682 3683 return ret; 3684 } 3685 3686 /** 3687 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3688 * @priv: driver private structure 3689 * @mtu: MTU to setup the dma queue and buf with 3690 * Description: Allocate and generate a dma_conf based on the provided MTU. 3691 * Allocate the Tx/Rx DMA queue and init them. 3692 * Return value: 3693 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3694 */ 3695 static struct stmmac_dma_conf * 3696 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3697 { 3698 struct stmmac_dma_conf *dma_conf; 3699 int chan, bfsize, ret; 3700 3701 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3702 if (!dma_conf) { 3703 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3704 __func__); 3705 return ERR_PTR(-ENOMEM); 3706 } 3707 3708 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3709 if (bfsize < 0) 3710 bfsize = 0; 3711 3712 if (bfsize < BUF_SIZE_16KiB) 3713 bfsize = stmmac_set_bfsize(mtu, 0); 3714 3715 dma_conf->dma_buf_sz = bfsize; 3716 /* Chose the tx/rx size from the already defined one in the 3717 * priv struct. (if defined) 3718 */ 3719 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3720 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3721 3722 if (!dma_conf->dma_tx_size) 3723 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3724 if (!dma_conf->dma_rx_size) 3725 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3726 3727 /* Earlier check for TBS */ 3728 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3729 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3730 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3731 3732 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3733 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3734 } 3735 3736 ret = alloc_dma_desc_resources(priv, dma_conf); 3737 if (ret < 0) { 3738 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3739 __func__); 3740 goto alloc_error; 3741 } 3742 3743 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3744 if (ret < 0) { 3745 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3746 __func__); 3747 goto init_error; 3748 } 3749 3750 return dma_conf; 3751 3752 init_error: 3753 free_dma_desc_resources(priv, dma_conf); 3754 alloc_error: 3755 kfree(dma_conf); 3756 return ERR_PTR(ret); 3757 } 3758 3759 /** 3760 * __stmmac_open - open entry point of the driver 3761 * @dev : pointer to the device structure. 3762 * @dma_conf : structure to take the dma data 3763 * Description: 3764 * This function is the open entry point of the driver. 3765 * Return value: 3766 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3767 * file on failure. 3768 */ 3769 static int __stmmac_open(struct net_device *dev, 3770 struct stmmac_dma_conf *dma_conf) 3771 { 3772 struct stmmac_priv *priv = netdev_priv(dev); 3773 int mode = priv->plat->phy_interface; 3774 u32 chan; 3775 int ret; 3776 3777 ret = pm_runtime_resume_and_get(priv->device); 3778 if (ret < 0) 3779 return ret; 3780 3781 if (priv->hw->pcs != STMMAC_PCS_TBI && 3782 priv->hw->pcs != STMMAC_PCS_RTBI && 3783 (!priv->hw->xpcs || 3784 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3785 ret = stmmac_init_phy(dev); 3786 if (ret) { 3787 netdev_err(priv->dev, 3788 "%s: Cannot attach to PHY (error: %d)\n", 3789 __func__, ret); 3790 goto init_phy_error; 3791 } 3792 } 3793 3794 /* Extra statistics */ 3795 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3796 priv->xstats.threshold = tc; 3797 3798 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3799 3800 buf_sz = dma_conf->dma_buf_sz; 3801 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3802 3803 stmmac_reset_queues_param(priv); 3804 3805 if (priv->plat->serdes_powerup) { 3806 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3807 if (ret < 0) { 3808 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3809 __func__); 3810 goto init_error; 3811 } 3812 } 3813 3814 ret = stmmac_hw_setup(dev, true); 3815 if (ret < 0) { 3816 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3817 goto init_error; 3818 } 3819 3820 stmmac_init_coalesce(priv); 3821 3822 phylink_start(priv->phylink); 3823 /* We may have called phylink_speed_down before */ 3824 phylink_speed_up(priv->phylink); 3825 3826 ret = stmmac_request_irq(dev); 3827 if (ret) 3828 goto irq_error; 3829 3830 stmmac_enable_all_queues(priv); 3831 netif_tx_start_all_queues(priv->dev); 3832 stmmac_enable_all_dma_irq(priv); 3833 3834 return 0; 3835 3836 irq_error: 3837 phylink_stop(priv->phylink); 3838 3839 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3840 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3841 3842 stmmac_hw_teardown(dev); 3843 init_error: 3844 free_dma_desc_resources(priv, &priv->dma_conf); 3845 phylink_disconnect_phy(priv->phylink); 3846 init_phy_error: 3847 pm_runtime_put(priv->device); 3848 return ret; 3849 } 3850 3851 static int stmmac_open(struct net_device *dev) 3852 { 3853 struct stmmac_priv *priv = netdev_priv(dev); 3854 struct stmmac_dma_conf *dma_conf; 3855 int ret; 3856 3857 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3858 if (IS_ERR(dma_conf)) 3859 return PTR_ERR(dma_conf); 3860 3861 ret = __stmmac_open(dev, dma_conf); 3862 kfree(dma_conf); 3863 return ret; 3864 } 3865 3866 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3867 { 3868 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3869 3870 if (priv->fpe_wq) 3871 destroy_workqueue(priv->fpe_wq); 3872 3873 netdev_info(priv->dev, "FPE workqueue stop"); 3874 } 3875 3876 /** 3877 * stmmac_release - close entry point of the driver 3878 * @dev : device pointer. 3879 * Description: 3880 * This is the stop entry point of the driver. 3881 */ 3882 static int stmmac_release(struct net_device *dev) 3883 { 3884 struct stmmac_priv *priv = netdev_priv(dev); 3885 u32 chan; 3886 3887 if (device_may_wakeup(priv->device)) 3888 phylink_speed_down(priv->phylink, false); 3889 /* Stop and disconnect the PHY */ 3890 phylink_stop(priv->phylink); 3891 phylink_disconnect_phy(priv->phylink); 3892 3893 stmmac_disable_all_queues(priv); 3894 3895 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3896 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3897 3898 netif_tx_disable(dev); 3899 3900 /* Free the IRQ lines */ 3901 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3902 3903 if (priv->eee_enabled) { 3904 priv->tx_path_in_lpi_mode = false; 3905 del_timer_sync(&priv->eee_ctrl_timer); 3906 } 3907 3908 /* Stop TX/RX DMA and clear the descriptors */ 3909 stmmac_stop_all_dma(priv); 3910 3911 /* Release and free the Rx/Tx resources */ 3912 free_dma_desc_resources(priv, &priv->dma_conf); 3913 3914 /* Disable the MAC Rx/Tx */ 3915 stmmac_mac_set(priv, priv->ioaddr, false); 3916 3917 /* Powerdown Serdes if there is */ 3918 if (priv->plat->serdes_powerdown) 3919 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3920 3921 netif_carrier_off(dev); 3922 3923 stmmac_release_ptp(priv); 3924 3925 pm_runtime_put(priv->device); 3926 3927 if (priv->dma_cap.fpesel) 3928 stmmac_fpe_stop_wq(priv); 3929 3930 return 0; 3931 } 3932 3933 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3934 struct stmmac_tx_queue *tx_q) 3935 { 3936 u16 tag = 0x0, inner_tag = 0x0; 3937 u32 inner_type = 0x0; 3938 struct dma_desc *p; 3939 3940 if (!priv->dma_cap.vlins) 3941 return false; 3942 if (!skb_vlan_tag_present(skb)) 3943 return false; 3944 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3945 inner_tag = skb_vlan_tag_get(skb); 3946 inner_type = STMMAC_VLAN_INSERT; 3947 } 3948 3949 tag = skb_vlan_tag_get(skb); 3950 3951 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3952 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3953 else 3954 p = &tx_q->dma_tx[tx_q->cur_tx]; 3955 3956 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3957 return false; 3958 3959 stmmac_set_tx_owner(priv, p); 3960 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3961 return true; 3962 } 3963 3964 /** 3965 * stmmac_tso_allocator - close entry point of the driver 3966 * @priv: driver private structure 3967 * @des: buffer start address 3968 * @total_len: total length to fill in descriptors 3969 * @last_segment: condition for the last descriptor 3970 * @queue: TX queue index 3971 * Description: 3972 * This function fills descriptor and request new descriptors according to 3973 * buffer length to fill 3974 */ 3975 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3976 int total_len, bool last_segment, u32 queue) 3977 { 3978 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3979 struct dma_desc *desc; 3980 u32 buff_size; 3981 int tmp_len; 3982 3983 tmp_len = total_len; 3984 3985 while (tmp_len > 0) { 3986 dma_addr_t curr_addr; 3987 3988 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3989 priv->dma_conf.dma_tx_size); 3990 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3991 3992 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3993 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3994 else 3995 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3996 3997 curr_addr = des + (total_len - tmp_len); 3998 if (priv->dma_cap.addr64 <= 32) 3999 desc->des0 = cpu_to_le32(curr_addr); 4000 else 4001 stmmac_set_desc_addr(priv, desc, curr_addr); 4002 4003 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4004 TSO_MAX_BUFF_SIZE : tmp_len; 4005 4006 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4007 0, 1, 4008 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4009 0, 0); 4010 4011 tmp_len -= TSO_MAX_BUFF_SIZE; 4012 } 4013 } 4014 4015 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4016 { 4017 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4018 int desc_size; 4019 4020 if (likely(priv->extend_desc)) 4021 desc_size = sizeof(struct dma_extended_desc); 4022 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4023 desc_size = sizeof(struct dma_edesc); 4024 else 4025 desc_size = sizeof(struct dma_desc); 4026 4027 /* The own bit must be the latest setting done when prepare the 4028 * descriptor and then barrier is needed to make sure that 4029 * all is coherent before granting the DMA engine. 4030 */ 4031 wmb(); 4032 4033 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4034 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4035 } 4036 4037 /** 4038 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4039 * @skb : the socket buffer 4040 * @dev : device pointer 4041 * Description: this is the transmit function that is called on TSO frames 4042 * (support available on GMAC4 and newer chips). 4043 * Diagram below show the ring programming in case of TSO frames: 4044 * 4045 * First Descriptor 4046 * -------- 4047 * | DES0 |---> buffer1 = L2/L3/L4 header 4048 * | DES1 |---> TCP Payload (can continue on next descr...) 4049 * | DES2 |---> buffer 1 and 2 len 4050 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4051 * -------- 4052 * | 4053 * ... 4054 * | 4055 * -------- 4056 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4057 * | DES1 | --| 4058 * | DES2 | --> buffer 1 and 2 len 4059 * | DES3 | 4060 * -------- 4061 * 4062 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4063 */ 4064 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4065 { 4066 struct dma_desc *desc, *first, *mss_desc = NULL; 4067 struct stmmac_priv *priv = netdev_priv(dev); 4068 int nfrags = skb_shinfo(skb)->nr_frags; 4069 u32 queue = skb_get_queue_mapping(skb); 4070 unsigned int first_entry, tx_packets; 4071 int tmp_pay_len = 0, first_tx; 4072 struct stmmac_tx_queue *tx_q; 4073 bool has_vlan, set_ic; 4074 u8 proto_hdr_len, hdr; 4075 u32 pay_len, mss; 4076 dma_addr_t des; 4077 int i; 4078 4079 tx_q = &priv->dma_conf.tx_queue[queue]; 4080 first_tx = tx_q->cur_tx; 4081 4082 /* Compute header lengths */ 4083 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4084 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4085 hdr = sizeof(struct udphdr); 4086 } else { 4087 proto_hdr_len = skb_tcp_all_headers(skb); 4088 hdr = tcp_hdrlen(skb); 4089 } 4090 4091 /* Desc availability based on threshold should be enough safe */ 4092 if (unlikely(stmmac_tx_avail(priv, queue) < 4093 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4094 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4095 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4096 queue)); 4097 /* This is a hard error, log it. */ 4098 netdev_err(priv->dev, 4099 "%s: Tx Ring full when queue awake\n", 4100 __func__); 4101 } 4102 return NETDEV_TX_BUSY; 4103 } 4104 4105 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4106 4107 mss = skb_shinfo(skb)->gso_size; 4108 4109 /* set new MSS value if needed */ 4110 if (mss != tx_q->mss) { 4111 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4112 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4113 else 4114 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4115 4116 stmmac_set_mss(priv, mss_desc, mss); 4117 tx_q->mss = mss; 4118 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4119 priv->dma_conf.dma_tx_size); 4120 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4121 } 4122 4123 if (netif_msg_tx_queued(priv)) { 4124 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4125 __func__, hdr, proto_hdr_len, pay_len, mss); 4126 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4127 skb->data_len); 4128 } 4129 4130 /* Check if VLAN can be inserted by HW */ 4131 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4132 4133 first_entry = tx_q->cur_tx; 4134 WARN_ON(tx_q->tx_skbuff[first_entry]); 4135 4136 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4137 desc = &tx_q->dma_entx[first_entry].basic; 4138 else 4139 desc = &tx_q->dma_tx[first_entry]; 4140 first = desc; 4141 4142 if (has_vlan) 4143 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4144 4145 /* first descriptor: fill Headers on Buf1 */ 4146 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4147 DMA_TO_DEVICE); 4148 if (dma_mapping_error(priv->device, des)) 4149 goto dma_map_err; 4150 4151 tx_q->tx_skbuff_dma[first_entry].buf = des; 4152 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4153 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4154 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4155 4156 if (priv->dma_cap.addr64 <= 32) { 4157 first->des0 = cpu_to_le32(des); 4158 4159 /* Fill start of payload in buff2 of first descriptor */ 4160 if (pay_len) 4161 first->des1 = cpu_to_le32(des + proto_hdr_len); 4162 4163 /* If needed take extra descriptors to fill the remaining payload */ 4164 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4165 } else { 4166 stmmac_set_desc_addr(priv, first, des); 4167 tmp_pay_len = pay_len; 4168 des += proto_hdr_len; 4169 pay_len = 0; 4170 } 4171 4172 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4173 4174 /* Prepare fragments */ 4175 for (i = 0; i < nfrags; i++) { 4176 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4177 4178 des = skb_frag_dma_map(priv->device, frag, 0, 4179 skb_frag_size(frag), 4180 DMA_TO_DEVICE); 4181 if (dma_mapping_error(priv->device, des)) 4182 goto dma_map_err; 4183 4184 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4185 (i == nfrags - 1), queue); 4186 4187 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4188 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4189 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4190 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4191 } 4192 4193 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4194 4195 /* Only the last descriptor gets to point to the skb. */ 4196 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4197 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4198 4199 /* Manage tx mitigation */ 4200 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4201 tx_q->tx_count_frames += tx_packets; 4202 4203 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4204 set_ic = true; 4205 else if (!priv->tx_coal_frames[queue]) 4206 set_ic = false; 4207 else if (tx_packets > priv->tx_coal_frames[queue]) 4208 set_ic = true; 4209 else if ((tx_q->tx_count_frames % 4210 priv->tx_coal_frames[queue]) < tx_packets) 4211 set_ic = true; 4212 else 4213 set_ic = false; 4214 4215 if (set_ic) { 4216 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4217 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4218 else 4219 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4220 4221 tx_q->tx_count_frames = 0; 4222 stmmac_set_tx_ic(priv, desc); 4223 priv->xstats.tx_set_ic_bit++; 4224 } 4225 4226 /* We've used all descriptors we need for this skb, however, 4227 * advance cur_tx so that it references a fresh descriptor. 4228 * ndo_start_xmit will fill this descriptor the next time it's 4229 * called and stmmac_tx_clean may clean up to this descriptor. 4230 */ 4231 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4232 4233 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4234 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4235 __func__); 4236 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4237 } 4238 4239 dev->stats.tx_bytes += skb->len; 4240 priv->xstats.tx_tso_frames++; 4241 priv->xstats.tx_tso_nfrags += nfrags; 4242 4243 if (priv->sarc_type) 4244 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4245 4246 skb_tx_timestamp(skb); 4247 4248 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4249 priv->hwts_tx_en)) { 4250 /* declare that device is doing timestamping */ 4251 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4252 stmmac_enable_tx_timestamp(priv, first); 4253 } 4254 4255 /* Complete the first descriptor before granting the DMA */ 4256 stmmac_prepare_tso_tx_desc(priv, first, 1, 4257 proto_hdr_len, 4258 pay_len, 4259 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4260 hdr / 4, (skb->len - proto_hdr_len)); 4261 4262 /* If context desc is used to change MSS */ 4263 if (mss_desc) { 4264 /* Make sure that first descriptor has been completely 4265 * written, including its own bit. This is because MSS is 4266 * actually before first descriptor, so we need to make 4267 * sure that MSS's own bit is the last thing written. 4268 */ 4269 dma_wmb(); 4270 stmmac_set_tx_owner(priv, mss_desc); 4271 } 4272 4273 if (netif_msg_pktdata(priv)) { 4274 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4275 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4276 tx_q->cur_tx, first, nfrags); 4277 pr_info(">>> frame to be transmitted: "); 4278 print_pkt(skb->data, skb_headlen(skb)); 4279 } 4280 4281 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4282 4283 stmmac_flush_tx_descriptors(priv, queue); 4284 stmmac_tx_timer_arm(priv, queue); 4285 4286 return NETDEV_TX_OK; 4287 4288 dma_map_err: 4289 dev_err(priv->device, "Tx dma map failed\n"); 4290 dev_kfree_skb(skb); 4291 priv->dev->stats.tx_dropped++; 4292 return NETDEV_TX_OK; 4293 } 4294 4295 /** 4296 * stmmac_xmit - Tx entry point of the driver 4297 * @skb : the socket buffer 4298 * @dev : device pointer 4299 * Description : this is the tx entry point of the driver. 4300 * It programs the chain or the ring and supports oversized frames 4301 * and SG feature. 4302 */ 4303 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4304 { 4305 unsigned int first_entry, tx_packets, enh_desc; 4306 struct stmmac_priv *priv = netdev_priv(dev); 4307 unsigned int nopaged_len = skb_headlen(skb); 4308 int i, csum_insertion = 0, is_jumbo = 0; 4309 u32 queue = skb_get_queue_mapping(skb); 4310 int nfrags = skb_shinfo(skb)->nr_frags; 4311 int gso = skb_shinfo(skb)->gso_type; 4312 struct dma_edesc *tbs_desc = NULL; 4313 struct dma_desc *desc, *first; 4314 struct stmmac_tx_queue *tx_q; 4315 bool has_vlan, set_ic; 4316 int entry, first_tx; 4317 dma_addr_t des; 4318 4319 tx_q = &priv->dma_conf.tx_queue[queue]; 4320 first_tx = tx_q->cur_tx; 4321 4322 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4323 stmmac_disable_eee_mode(priv); 4324 4325 /* Manage oversized TCP frames for GMAC4 device */ 4326 if (skb_is_gso(skb) && priv->tso) { 4327 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4328 return stmmac_tso_xmit(skb, dev); 4329 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4330 return stmmac_tso_xmit(skb, dev); 4331 } 4332 4333 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4334 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4335 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4336 queue)); 4337 /* This is a hard error, log it. */ 4338 netdev_err(priv->dev, 4339 "%s: Tx Ring full when queue awake\n", 4340 __func__); 4341 } 4342 return NETDEV_TX_BUSY; 4343 } 4344 4345 /* Check if VLAN can be inserted by HW */ 4346 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4347 4348 entry = tx_q->cur_tx; 4349 first_entry = entry; 4350 WARN_ON(tx_q->tx_skbuff[first_entry]); 4351 4352 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4353 4354 if (likely(priv->extend_desc)) 4355 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4356 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4357 desc = &tx_q->dma_entx[entry].basic; 4358 else 4359 desc = tx_q->dma_tx + entry; 4360 4361 first = desc; 4362 4363 if (has_vlan) 4364 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4365 4366 enh_desc = priv->plat->enh_desc; 4367 /* To program the descriptors according to the size of the frame */ 4368 if (enh_desc) 4369 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4370 4371 if (unlikely(is_jumbo)) { 4372 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4373 if (unlikely(entry < 0) && (entry != -EINVAL)) 4374 goto dma_map_err; 4375 } 4376 4377 for (i = 0; i < nfrags; i++) { 4378 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4379 int len = skb_frag_size(frag); 4380 bool last_segment = (i == (nfrags - 1)); 4381 4382 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4383 WARN_ON(tx_q->tx_skbuff[entry]); 4384 4385 if (likely(priv->extend_desc)) 4386 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4387 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4388 desc = &tx_q->dma_entx[entry].basic; 4389 else 4390 desc = tx_q->dma_tx + entry; 4391 4392 des = skb_frag_dma_map(priv->device, frag, 0, len, 4393 DMA_TO_DEVICE); 4394 if (dma_mapping_error(priv->device, des)) 4395 goto dma_map_err; /* should reuse desc w/o issues */ 4396 4397 tx_q->tx_skbuff_dma[entry].buf = des; 4398 4399 stmmac_set_desc_addr(priv, desc, des); 4400 4401 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4402 tx_q->tx_skbuff_dma[entry].len = len; 4403 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4404 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4405 4406 /* Prepare the descriptor and set the own bit too */ 4407 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4408 priv->mode, 1, last_segment, skb->len); 4409 } 4410 4411 /* Only the last descriptor gets to point to the skb. */ 4412 tx_q->tx_skbuff[entry] = skb; 4413 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4414 4415 /* According to the coalesce parameter the IC bit for the latest 4416 * segment is reset and the timer re-started to clean the tx status. 4417 * This approach takes care about the fragments: desc is the first 4418 * element in case of no SG. 4419 */ 4420 tx_packets = (entry + 1) - first_tx; 4421 tx_q->tx_count_frames += tx_packets; 4422 4423 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4424 set_ic = true; 4425 else if (!priv->tx_coal_frames[queue]) 4426 set_ic = false; 4427 else if (tx_packets > priv->tx_coal_frames[queue]) 4428 set_ic = true; 4429 else if ((tx_q->tx_count_frames % 4430 priv->tx_coal_frames[queue]) < tx_packets) 4431 set_ic = true; 4432 else 4433 set_ic = false; 4434 4435 if (set_ic) { 4436 if (likely(priv->extend_desc)) 4437 desc = &tx_q->dma_etx[entry].basic; 4438 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4439 desc = &tx_q->dma_entx[entry].basic; 4440 else 4441 desc = &tx_q->dma_tx[entry]; 4442 4443 tx_q->tx_count_frames = 0; 4444 stmmac_set_tx_ic(priv, desc); 4445 priv->xstats.tx_set_ic_bit++; 4446 } 4447 4448 /* We've used all descriptors we need for this skb, however, 4449 * advance cur_tx so that it references a fresh descriptor. 4450 * ndo_start_xmit will fill this descriptor the next time it's 4451 * called and stmmac_tx_clean may clean up to this descriptor. 4452 */ 4453 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4454 tx_q->cur_tx = entry; 4455 4456 if (netif_msg_pktdata(priv)) { 4457 netdev_dbg(priv->dev, 4458 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4459 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4460 entry, first, nfrags); 4461 4462 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4463 print_pkt(skb->data, skb->len); 4464 } 4465 4466 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4467 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4468 __func__); 4469 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4470 } 4471 4472 dev->stats.tx_bytes += skb->len; 4473 4474 if (priv->sarc_type) 4475 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4476 4477 skb_tx_timestamp(skb); 4478 4479 /* Ready to fill the first descriptor and set the OWN bit w/o any 4480 * problems because all the descriptors are actually ready to be 4481 * passed to the DMA engine. 4482 */ 4483 if (likely(!is_jumbo)) { 4484 bool last_segment = (nfrags == 0); 4485 4486 des = dma_map_single(priv->device, skb->data, 4487 nopaged_len, DMA_TO_DEVICE); 4488 if (dma_mapping_error(priv->device, des)) 4489 goto dma_map_err; 4490 4491 tx_q->tx_skbuff_dma[first_entry].buf = des; 4492 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4493 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4494 4495 stmmac_set_desc_addr(priv, first, des); 4496 4497 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4498 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4499 4500 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4501 priv->hwts_tx_en)) { 4502 /* declare that device is doing timestamping */ 4503 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4504 stmmac_enable_tx_timestamp(priv, first); 4505 } 4506 4507 /* Prepare the first descriptor setting the OWN bit too */ 4508 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4509 csum_insertion, priv->mode, 0, last_segment, 4510 skb->len); 4511 } 4512 4513 if (tx_q->tbs & STMMAC_TBS_EN) { 4514 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4515 4516 tbs_desc = &tx_q->dma_entx[first_entry]; 4517 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4518 } 4519 4520 stmmac_set_tx_owner(priv, first); 4521 4522 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4523 4524 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4525 4526 stmmac_flush_tx_descriptors(priv, queue); 4527 stmmac_tx_timer_arm(priv, queue); 4528 4529 return NETDEV_TX_OK; 4530 4531 dma_map_err: 4532 netdev_err(priv->dev, "Tx DMA map failed\n"); 4533 dev_kfree_skb(skb); 4534 priv->dev->stats.tx_dropped++; 4535 return NETDEV_TX_OK; 4536 } 4537 4538 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4539 { 4540 struct vlan_ethhdr *veth; 4541 __be16 vlan_proto; 4542 u16 vlanid; 4543 4544 veth = (struct vlan_ethhdr *)skb->data; 4545 vlan_proto = veth->h_vlan_proto; 4546 4547 if ((vlan_proto == htons(ETH_P_8021Q) && 4548 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4549 (vlan_proto == htons(ETH_P_8021AD) && 4550 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4551 /* pop the vlan tag */ 4552 vlanid = ntohs(veth->h_vlan_TCI); 4553 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4554 skb_pull(skb, VLAN_HLEN); 4555 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4556 } 4557 } 4558 4559 /** 4560 * stmmac_rx_refill - refill used skb preallocated buffers 4561 * @priv: driver private structure 4562 * @queue: RX queue index 4563 * Description : this is to reallocate the skb for the reception process 4564 * that is based on zero-copy. 4565 */ 4566 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4567 { 4568 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4569 int dirty = stmmac_rx_dirty(priv, queue); 4570 unsigned int entry = rx_q->dirty_rx; 4571 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4572 4573 if (priv->dma_cap.addr64 <= 32) 4574 gfp |= GFP_DMA32; 4575 4576 while (dirty-- > 0) { 4577 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4578 struct dma_desc *p; 4579 bool use_rx_wd; 4580 4581 if (priv->extend_desc) 4582 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4583 else 4584 p = rx_q->dma_rx + entry; 4585 4586 if (!buf->page) { 4587 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4588 if (!buf->page) 4589 break; 4590 } 4591 4592 if (priv->sph && !buf->sec_page) { 4593 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4594 if (!buf->sec_page) 4595 break; 4596 4597 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4598 } 4599 4600 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4601 4602 stmmac_set_desc_addr(priv, p, buf->addr); 4603 if (priv->sph) 4604 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4605 else 4606 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4607 stmmac_refill_desc3(priv, rx_q, p); 4608 4609 rx_q->rx_count_frames++; 4610 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4611 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4612 rx_q->rx_count_frames = 0; 4613 4614 use_rx_wd = !priv->rx_coal_frames[queue]; 4615 use_rx_wd |= rx_q->rx_count_frames > 0; 4616 if (!priv->use_riwt) 4617 use_rx_wd = false; 4618 4619 dma_wmb(); 4620 stmmac_set_rx_owner(priv, p, use_rx_wd); 4621 4622 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4623 } 4624 rx_q->dirty_rx = entry; 4625 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4626 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4627 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4628 } 4629 4630 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4631 struct dma_desc *p, 4632 int status, unsigned int len) 4633 { 4634 unsigned int plen = 0, hlen = 0; 4635 int coe = priv->hw->rx_csum; 4636 4637 /* Not first descriptor, buffer is always zero */ 4638 if (priv->sph && len) 4639 return 0; 4640 4641 /* First descriptor, get split header length */ 4642 stmmac_get_rx_header_len(priv, p, &hlen); 4643 if (priv->sph && hlen) { 4644 priv->xstats.rx_split_hdr_pkt_n++; 4645 return hlen; 4646 } 4647 4648 /* First descriptor, not last descriptor and not split header */ 4649 if (status & rx_not_ls) 4650 return priv->dma_conf.dma_buf_sz; 4651 4652 plen = stmmac_get_rx_frame_len(priv, p, coe); 4653 4654 /* First descriptor and last descriptor and not split header */ 4655 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4656 } 4657 4658 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4659 struct dma_desc *p, 4660 int status, unsigned int len) 4661 { 4662 int coe = priv->hw->rx_csum; 4663 unsigned int plen = 0; 4664 4665 /* Not split header, buffer is not available */ 4666 if (!priv->sph) 4667 return 0; 4668 4669 /* Not last descriptor */ 4670 if (status & rx_not_ls) 4671 return priv->dma_conf.dma_buf_sz; 4672 4673 plen = stmmac_get_rx_frame_len(priv, p, coe); 4674 4675 /* Last descriptor */ 4676 return plen - len; 4677 } 4678 4679 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4680 struct xdp_frame *xdpf, bool dma_map) 4681 { 4682 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4683 unsigned int entry = tx_q->cur_tx; 4684 struct dma_desc *tx_desc; 4685 dma_addr_t dma_addr; 4686 bool set_ic; 4687 4688 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4689 return STMMAC_XDP_CONSUMED; 4690 4691 if (likely(priv->extend_desc)) 4692 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4693 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4694 tx_desc = &tx_q->dma_entx[entry].basic; 4695 else 4696 tx_desc = tx_q->dma_tx + entry; 4697 4698 if (dma_map) { 4699 dma_addr = dma_map_single(priv->device, xdpf->data, 4700 xdpf->len, DMA_TO_DEVICE); 4701 if (dma_mapping_error(priv->device, dma_addr)) 4702 return STMMAC_XDP_CONSUMED; 4703 4704 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4705 } else { 4706 struct page *page = virt_to_page(xdpf->data); 4707 4708 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4709 xdpf->headroom; 4710 dma_sync_single_for_device(priv->device, dma_addr, 4711 xdpf->len, DMA_BIDIRECTIONAL); 4712 4713 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4714 } 4715 4716 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4717 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4718 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4719 tx_q->tx_skbuff_dma[entry].last_segment = true; 4720 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4721 4722 tx_q->xdpf[entry] = xdpf; 4723 4724 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4725 4726 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4727 true, priv->mode, true, true, 4728 xdpf->len); 4729 4730 tx_q->tx_count_frames++; 4731 4732 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4733 set_ic = true; 4734 else 4735 set_ic = false; 4736 4737 if (set_ic) { 4738 tx_q->tx_count_frames = 0; 4739 stmmac_set_tx_ic(priv, tx_desc); 4740 priv->xstats.tx_set_ic_bit++; 4741 } 4742 4743 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4744 4745 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4746 tx_q->cur_tx = entry; 4747 4748 return STMMAC_XDP_TX; 4749 } 4750 4751 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4752 int cpu) 4753 { 4754 int index = cpu; 4755 4756 if (unlikely(index < 0)) 4757 index = 0; 4758 4759 while (index >= priv->plat->tx_queues_to_use) 4760 index -= priv->plat->tx_queues_to_use; 4761 4762 return index; 4763 } 4764 4765 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4766 struct xdp_buff *xdp) 4767 { 4768 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4769 int cpu = smp_processor_id(); 4770 struct netdev_queue *nq; 4771 int queue; 4772 int res; 4773 4774 if (unlikely(!xdpf)) 4775 return STMMAC_XDP_CONSUMED; 4776 4777 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4778 nq = netdev_get_tx_queue(priv->dev, queue); 4779 4780 __netif_tx_lock(nq, cpu); 4781 /* Avoids TX time-out as we are sharing with slow path */ 4782 txq_trans_cond_update(nq); 4783 4784 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4785 if (res == STMMAC_XDP_TX) 4786 stmmac_flush_tx_descriptors(priv, queue); 4787 4788 __netif_tx_unlock(nq); 4789 4790 return res; 4791 } 4792 4793 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4794 struct bpf_prog *prog, 4795 struct xdp_buff *xdp) 4796 { 4797 u32 act; 4798 int res; 4799 4800 act = bpf_prog_run_xdp(prog, xdp); 4801 switch (act) { 4802 case XDP_PASS: 4803 res = STMMAC_XDP_PASS; 4804 break; 4805 case XDP_TX: 4806 res = stmmac_xdp_xmit_back(priv, xdp); 4807 break; 4808 case XDP_REDIRECT: 4809 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4810 res = STMMAC_XDP_CONSUMED; 4811 else 4812 res = STMMAC_XDP_REDIRECT; 4813 break; 4814 default: 4815 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4816 fallthrough; 4817 case XDP_ABORTED: 4818 trace_xdp_exception(priv->dev, prog, act); 4819 fallthrough; 4820 case XDP_DROP: 4821 res = STMMAC_XDP_CONSUMED; 4822 break; 4823 } 4824 4825 return res; 4826 } 4827 4828 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4829 struct xdp_buff *xdp) 4830 { 4831 struct bpf_prog *prog; 4832 int res; 4833 4834 prog = READ_ONCE(priv->xdp_prog); 4835 if (!prog) { 4836 res = STMMAC_XDP_PASS; 4837 goto out; 4838 } 4839 4840 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4841 out: 4842 return ERR_PTR(-res); 4843 } 4844 4845 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4846 int xdp_status) 4847 { 4848 int cpu = smp_processor_id(); 4849 int queue; 4850 4851 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4852 4853 if (xdp_status & STMMAC_XDP_TX) 4854 stmmac_tx_timer_arm(priv, queue); 4855 4856 if (xdp_status & STMMAC_XDP_REDIRECT) 4857 xdp_do_flush(); 4858 } 4859 4860 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4861 struct xdp_buff *xdp) 4862 { 4863 unsigned int metasize = xdp->data - xdp->data_meta; 4864 unsigned int datasize = xdp->data_end - xdp->data; 4865 struct sk_buff *skb; 4866 4867 skb = __napi_alloc_skb(&ch->rxtx_napi, 4868 xdp->data_end - xdp->data_hard_start, 4869 GFP_ATOMIC | __GFP_NOWARN); 4870 if (unlikely(!skb)) 4871 return NULL; 4872 4873 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4874 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4875 if (metasize) 4876 skb_metadata_set(skb, metasize); 4877 4878 return skb; 4879 } 4880 4881 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4882 struct dma_desc *p, struct dma_desc *np, 4883 struct xdp_buff *xdp) 4884 { 4885 struct stmmac_channel *ch = &priv->channel[queue]; 4886 unsigned int len = xdp->data_end - xdp->data; 4887 enum pkt_hash_types hash_type; 4888 int coe = priv->hw->rx_csum; 4889 struct sk_buff *skb; 4890 u32 hash; 4891 4892 skb = stmmac_construct_skb_zc(ch, xdp); 4893 if (!skb) { 4894 priv->dev->stats.rx_dropped++; 4895 return; 4896 } 4897 4898 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4899 stmmac_rx_vlan(priv->dev, skb); 4900 skb->protocol = eth_type_trans(skb, priv->dev); 4901 4902 if (unlikely(!coe)) 4903 skb_checksum_none_assert(skb); 4904 else 4905 skb->ip_summed = CHECKSUM_UNNECESSARY; 4906 4907 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4908 skb_set_hash(skb, hash, hash_type); 4909 4910 skb_record_rx_queue(skb, queue); 4911 napi_gro_receive(&ch->rxtx_napi, skb); 4912 4913 priv->dev->stats.rx_packets++; 4914 priv->dev->stats.rx_bytes += len; 4915 } 4916 4917 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4918 { 4919 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4920 unsigned int entry = rx_q->dirty_rx; 4921 struct dma_desc *rx_desc = NULL; 4922 bool ret = true; 4923 4924 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4925 4926 while (budget-- > 0 && entry != rx_q->cur_rx) { 4927 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4928 dma_addr_t dma_addr; 4929 bool use_rx_wd; 4930 4931 if (!buf->xdp) { 4932 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4933 if (!buf->xdp) { 4934 ret = false; 4935 break; 4936 } 4937 } 4938 4939 if (priv->extend_desc) 4940 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4941 else 4942 rx_desc = rx_q->dma_rx + entry; 4943 4944 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4945 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4946 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4947 stmmac_refill_desc3(priv, rx_q, rx_desc); 4948 4949 rx_q->rx_count_frames++; 4950 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4951 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4952 rx_q->rx_count_frames = 0; 4953 4954 use_rx_wd = !priv->rx_coal_frames[queue]; 4955 use_rx_wd |= rx_q->rx_count_frames > 0; 4956 if (!priv->use_riwt) 4957 use_rx_wd = false; 4958 4959 dma_wmb(); 4960 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4961 4962 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4963 } 4964 4965 if (rx_desc) { 4966 rx_q->dirty_rx = entry; 4967 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4968 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4969 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4970 } 4971 4972 return ret; 4973 } 4974 4975 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4976 { 4977 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4978 unsigned int count = 0, error = 0, len = 0; 4979 int dirty = stmmac_rx_dirty(priv, queue); 4980 unsigned int next_entry = rx_q->cur_rx; 4981 unsigned int desc_size; 4982 struct bpf_prog *prog; 4983 bool failure = false; 4984 int xdp_status = 0; 4985 int status = 0; 4986 4987 if (netif_msg_rx_status(priv)) { 4988 void *rx_head; 4989 4990 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4991 if (priv->extend_desc) { 4992 rx_head = (void *)rx_q->dma_erx; 4993 desc_size = sizeof(struct dma_extended_desc); 4994 } else { 4995 rx_head = (void *)rx_q->dma_rx; 4996 desc_size = sizeof(struct dma_desc); 4997 } 4998 4999 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5000 rx_q->dma_rx_phy, desc_size); 5001 } 5002 while (count < limit) { 5003 struct stmmac_rx_buffer *buf; 5004 unsigned int buf1_len = 0; 5005 struct dma_desc *np, *p; 5006 int entry; 5007 int res; 5008 5009 if (!count && rx_q->state_saved) { 5010 error = rx_q->state.error; 5011 len = rx_q->state.len; 5012 } else { 5013 rx_q->state_saved = false; 5014 error = 0; 5015 len = 0; 5016 } 5017 5018 if (count >= limit) 5019 break; 5020 5021 read_again: 5022 buf1_len = 0; 5023 entry = next_entry; 5024 buf = &rx_q->buf_pool[entry]; 5025 5026 if (dirty >= STMMAC_RX_FILL_BATCH) { 5027 failure = failure || 5028 !stmmac_rx_refill_zc(priv, queue, dirty); 5029 dirty = 0; 5030 } 5031 5032 if (priv->extend_desc) 5033 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5034 else 5035 p = rx_q->dma_rx + entry; 5036 5037 /* read the status of the incoming frame */ 5038 status = stmmac_rx_status(priv, &priv->dev->stats, 5039 &priv->xstats, p); 5040 /* check if managed by the DMA otherwise go ahead */ 5041 if (unlikely(status & dma_own)) 5042 break; 5043 5044 /* Prefetch the next RX descriptor */ 5045 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5046 priv->dma_conf.dma_rx_size); 5047 next_entry = rx_q->cur_rx; 5048 5049 if (priv->extend_desc) 5050 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5051 else 5052 np = rx_q->dma_rx + next_entry; 5053 5054 prefetch(np); 5055 5056 /* Ensure a valid XSK buffer before proceed */ 5057 if (!buf->xdp) 5058 break; 5059 5060 if (priv->extend_desc) 5061 stmmac_rx_extended_status(priv, &priv->dev->stats, 5062 &priv->xstats, 5063 rx_q->dma_erx + entry); 5064 if (unlikely(status == discard_frame)) { 5065 xsk_buff_free(buf->xdp); 5066 buf->xdp = NULL; 5067 dirty++; 5068 error = 1; 5069 if (!priv->hwts_rx_en) 5070 priv->dev->stats.rx_errors++; 5071 } 5072 5073 if (unlikely(error && (status & rx_not_ls))) 5074 goto read_again; 5075 if (unlikely(error)) { 5076 count++; 5077 continue; 5078 } 5079 5080 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5081 if (likely(status & rx_not_ls)) { 5082 xsk_buff_free(buf->xdp); 5083 buf->xdp = NULL; 5084 dirty++; 5085 count++; 5086 goto read_again; 5087 } 5088 5089 /* XDP ZC Frame only support primary buffers for now */ 5090 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5091 len += buf1_len; 5092 5093 /* ACS is disabled; strip manually. */ 5094 if (likely(!(status & rx_not_ls))) { 5095 buf1_len -= ETH_FCS_LEN; 5096 len -= ETH_FCS_LEN; 5097 } 5098 5099 /* RX buffer is good and fit into a XSK pool buffer */ 5100 buf->xdp->data_end = buf->xdp->data + buf1_len; 5101 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5102 5103 prog = READ_ONCE(priv->xdp_prog); 5104 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5105 5106 switch (res) { 5107 case STMMAC_XDP_PASS: 5108 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5109 xsk_buff_free(buf->xdp); 5110 break; 5111 case STMMAC_XDP_CONSUMED: 5112 xsk_buff_free(buf->xdp); 5113 priv->dev->stats.rx_dropped++; 5114 break; 5115 case STMMAC_XDP_TX: 5116 case STMMAC_XDP_REDIRECT: 5117 xdp_status |= res; 5118 break; 5119 } 5120 5121 buf->xdp = NULL; 5122 dirty++; 5123 count++; 5124 } 5125 5126 if (status & rx_not_ls) { 5127 rx_q->state_saved = true; 5128 rx_q->state.error = error; 5129 rx_q->state.len = len; 5130 } 5131 5132 stmmac_finalize_xdp_rx(priv, xdp_status); 5133 5134 priv->xstats.rx_pkt_n += count; 5135 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5136 5137 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5138 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5139 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5140 else 5141 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5142 5143 return (int)count; 5144 } 5145 5146 return failure ? limit : (int)count; 5147 } 5148 5149 /** 5150 * stmmac_rx - manage the receive process 5151 * @priv: driver private structure 5152 * @limit: napi bugget 5153 * @queue: RX queue index. 5154 * Description : this the function called by the napi poll method. 5155 * It gets all the frames inside the ring. 5156 */ 5157 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5158 { 5159 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5160 struct stmmac_channel *ch = &priv->channel[queue]; 5161 unsigned int count = 0, error = 0, len = 0; 5162 int status = 0, coe = priv->hw->rx_csum; 5163 unsigned int next_entry = rx_q->cur_rx; 5164 enum dma_data_direction dma_dir; 5165 unsigned int desc_size; 5166 struct sk_buff *skb = NULL; 5167 struct xdp_buff xdp; 5168 int xdp_status = 0; 5169 int buf_sz; 5170 5171 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5172 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5173 5174 if (netif_msg_rx_status(priv)) { 5175 void *rx_head; 5176 5177 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5178 if (priv->extend_desc) { 5179 rx_head = (void *)rx_q->dma_erx; 5180 desc_size = sizeof(struct dma_extended_desc); 5181 } else { 5182 rx_head = (void *)rx_q->dma_rx; 5183 desc_size = sizeof(struct dma_desc); 5184 } 5185 5186 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5187 rx_q->dma_rx_phy, desc_size); 5188 } 5189 while (count < limit) { 5190 unsigned int buf1_len = 0, buf2_len = 0; 5191 enum pkt_hash_types hash_type; 5192 struct stmmac_rx_buffer *buf; 5193 struct dma_desc *np, *p; 5194 int entry; 5195 u32 hash; 5196 5197 if (!count && rx_q->state_saved) { 5198 skb = rx_q->state.skb; 5199 error = rx_q->state.error; 5200 len = rx_q->state.len; 5201 } else { 5202 rx_q->state_saved = false; 5203 skb = NULL; 5204 error = 0; 5205 len = 0; 5206 } 5207 5208 if (count >= limit) 5209 break; 5210 5211 read_again: 5212 buf1_len = 0; 5213 buf2_len = 0; 5214 entry = next_entry; 5215 buf = &rx_q->buf_pool[entry]; 5216 5217 if (priv->extend_desc) 5218 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5219 else 5220 p = rx_q->dma_rx + entry; 5221 5222 /* read the status of the incoming frame */ 5223 status = stmmac_rx_status(priv, &priv->dev->stats, 5224 &priv->xstats, p); 5225 /* check if managed by the DMA otherwise go ahead */ 5226 if (unlikely(status & dma_own)) 5227 break; 5228 5229 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5230 priv->dma_conf.dma_rx_size); 5231 next_entry = rx_q->cur_rx; 5232 5233 if (priv->extend_desc) 5234 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5235 else 5236 np = rx_q->dma_rx + next_entry; 5237 5238 prefetch(np); 5239 5240 if (priv->extend_desc) 5241 stmmac_rx_extended_status(priv, &priv->dev->stats, 5242 &priv->xstats, rx_q->dma_erx + entry); 5243 if (unlikely(status == discard_frame)) { 5244 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5245 buf->page = NULL; 5246 error = 1; 5247 if (!priv->hwts_rx_en) 5248 priv->dev->stats.rx_errors++; 5249 } 5250 5251 if (unlikely(error && (status & rx_not_ls))) 5252 goto read_again; 5253 if (unlikely(error)) { 5254 dev_kfree_skb(skb); 5255 skb = NULL; 5256 count++; 5257 continue; 5258 } 5259 5260 /* Buffer is good. Go on. */ 5261 5262 prefetch(page_address(buf->page) + buf->page_offset); 5263 if (buf->sec_page) 5264 prefetch(page_address(buf->sec_page)); 5265 5266 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5267 len += buf1_len; 5268 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5269 len += buf2_len; 5270 5271 /* ACS is disabled; strip manually. */ 5272 if (likely(!(status & rx_not_ls))) { 5273 if (buf2_len) { 5274 buf2_len -= ETH_FCS_LEN; 5275 len -= ETH_FCS_LEN; 5276 } else if (buf1_len) { 5277 buf1_len -= ETH_FCS_LEN; 5278 len -= ETH_FCS_LEN; 5279 } 5280 } 5281 5282 if (!skb) { 5283 unsigned int pre_len, sync_len; 5284 5285 dma_sync_single_for_cpu(priv->device, buf->addr, 5286 buf1_len, dma_dir); 5287 5288 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5289 xdp_prepare_buff(&xdp, page_address(buf->page), 5290 buf->page_offset, buf1_len, false); 5291 5292 pre_len = xdp.data_end - xdp.data_hard_start - 5293 buf->page_offset; 5294 skb = stmmac_xdp_run_prog(priv, &xdp); 5295 /* Due xdp_adjust_tail: DMA sync for_device 5296 * cover max len CPU touch 5297 */ 5298 sync_len = xdp.data_end - xdp.data_hard_start - 5299 buf->page_offset; 5300 sync_len = max(sync_len, pre_len); 5301 5302 /* For Not XDP_PASS verdict */ 5303 if (IS_ERR(skb)) { 5304 unsigned int xdp_res = -PTR_ERR(skb); 5305 5306 if (xdp_res & STMMAC_XDP_CONSUMED) { 5307 page_pool_put_page(rx_q->page_pool, 5308 virt_to_head_page(xdp.data), 5309 sync_len, true); 5310 buf->page = NULL; 5311 priv->dev->stats.rx_dropped++; 5312 5313 /* Clear skb as it was set as 5314 * status by XDP program. 5315 */ 5316 skb = NULL; 5317 5318 if (unlikely((status & rx_not_ls))) 5319 goto read_again; 5320 5321 count++; 5322 continue; 5323 } else if (xdp_res & (STMMAC_XDP_TX | 5324 STMMAC_XDP_REDIRECT)) { 5325 xdp_status |= xdp_res; 5326 buf->page = NULL; 5327 skb = NULL; 5328 count++; 5329 continue; 5330 } 5331 } 5332 } 5333 5334 if (!skb) { 5335 /* XDP program may expand or reduce tail */ 5336 buf1_len = xdp.data_end - xdp.data; 5337 5338 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5339 if (!skb) { 5340 priv->dev->stats.rx_dropped++; 5341 count++; 5342 goto drain_data; 5343 } 5344 5345 /* XDP program may adjust header */ 5346 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5347 skb_put(skb, buf1_len); 5348 5349 /* Data payload copied into SKB, page ready for recycle */ 5350 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5351 buf->page = NULL; 5352 } else if (buf1_len) { 5353 dma_sync_single_for_cpu(priv->device, buf->addr, 5354 buf1_len, dma_dir); 5355 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5356 buf->page, buf->page_offset, buf1_len, 5357 priv->dma_conf.dma_buf_sz); 5358 5359 /* Data payload appended into SKB */ 5360 page_pool_release_page(rx_q->page_pool, buf->page); 5361 buf->page = NULL; 5362 } 5363 5364 if (buf2_len) { 5365 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5366 buf2_len, dma_dir); 5367 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5368 buf->sec_page, 0, buf2_len, 5369 priv->dma_conf.dma_buf_sz); 5370 5371 /* Data payload appended into SKB */ 5372 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5373 buf->sec_page = NULL; 5374 } 5375 5376 drain_data: 5377 if (likely(status & rx_not_ls)) 5378 goto read_again; 5379 if (!skb) 5380 continue; 5381 5382 /* Got entire packet into SKB. Finish it. */ 5383 5384 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5385 stmmac_rx_vlan(priv->dev, skb); 5386 skb->protocol = eth_type_trans(skb, priv->dev); 5387 5388 if (unlikely(!coe)) 5389 skb_checksum_none_assert(skb); 5390 else 5391 skb->ip_summed = CHECKSUM_UNNECESSARY; 5392 5393 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5394 skb_set_hash(skb, hash, hash_type); 5395 5396 skb_record_rx_queue(skb, queue); 5397 napi_gro_receive(&ch->rx_napi, skb); 5398 skb = NULL; 5399 5400 priv->dev->stats.rx_packets++; 5401 priv->dev->stats.rx_bytes += len; 5402 count++; 5403 } 5404 5405 if (status & rx_not_ls || skb) { 5406 rx_q->state_saved = true; 5407 rx_q->state.skb = skb; 5408 rx_q->state.error = error; 5409 rx_q->state.len = len; 5410 } 5411 5412 stmmac_finalize_xdp_rx(priv, xdp_status); 5413 5414 stmmac_rx_refill(priv, queue); 5415 5416 priv->xstats.rx_pkt_n += count; 5417 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5418 5419 return count; 5420 } 5421 5422 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5423 { 5424 struct stmmac_channel *ch = 5425 container_of(napi, struct stmmac_channel, rx_napi); 5426 struct stmmac_priv *priv = ch->priv_data; 5427 u32 chan = ch->index; 5428 int work_done; 5429 5430 priv->xstats.napi_poll++; 5431 5432 work_done = stmmac_rx(priv, budget, chan); 5433 if (work_done < budget && napi_complete_done(napi, work_done)) { 5434 unsigned long flags; 5435 5436 spin_lock_irqsave(&ch->lock, flags); 5437 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5438 spin_unlock_irqrestore(&ch->lock, flags); 5439 } 5440 5441 return work_done; 5442 } 5443 5444 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5445 { 5446 struct stmmac_channel *ch = 5447 container_of(napi, struct stmmac_channel, tx_napi); 5448 struct stmmac_priv *priv = ch->priv_data; 5449 u32 chan = ch->index; 5450 int work_done; 5451 5452 priv->xstats.napi_poll++; 5453 5454 work_done = stmmac_tx_clean(priv, budget, chan); 5455 work_done = min(work_done, budget); 5456 5457 if (work_done < budget && napi_complete_done(napi, work_done)) { 5458 unsigned long flags; 5459 5460 spin_lock_irqsave(&ch->lock, flags); 5461 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5462 spin_unlock_irqrestore(&ch->lock, flags); 5463 } 5464 5465 return work_done; 5466 } 5467 5468 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5469 { 5470 struct stmmac_channel *ch = 5471 container_of(napi, struct stmmac_channel, rxtx_napi); 5472 struct stmmac_priv *priv = ch->priv_data; 5473 int rx_done, tx_done, rxtx_done; 5474 u32 chan = ch->index; 5475 5476 priv->xstats.napi_poll++; 5477 5478 tx_done = stmmac_tx_clean(priv, budget, chan); 5479 tx_done = min(tx_done, budget); 5480 5481 rx_done = stmmac_rx_zc(priv, budget, chan); 5482 5483 rxtx_done = max(tx_done, rx_done); 5484 5485 /* If either TX or RX work is not complete, return budget 5486 * and keep pooling 5487 */ 5488 if (rxtx_done >= budget) 5489 return budget; 5490 5491 /* all work done, exit the polling mode */ 5492 if (napi_complete_done(napi, rxtx_done)) { 5493 unsigned long flags; 5494 5495 spin_lock_irqsave(&ch->lock, flags); 5496 /* Both RX and TX work done are compelte, 5497 * so enable both RX & TX IRQs. 5498 */ 5499 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5500 spin_unlock_irqrestore(&ch->lock, flags); 5501 } 5502 5503 return min(rxtx_done, budget - 1); 5504 } 5505 5506 /** 5507 * stmmac_tx_timeout 5508 * @dev : Pointer to net device structure 5509 * @txqueue: the index of the hanging transmit queue 5510 * Description: this function is called when a packet transmission fails to 5511 * complete within a reasonable time. The driver will mark the error in the 5512 * netdev structure and arrange for the device to be reset to a sane state 5513 * in order to transmit a new packet. 5514 */ 5515 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5516 { 5517 struct stmmac_priv *priv = netdev_priv(dev); 5518 5519 stmmac_global_err(priv); 5520 } 5521 5522 /** 5523 * stmmac_set_rx_mode - entry point for multicast addressing 5524 * @dev : pointer to the device structure 5525 * Description: 5526 * This function is a driver entry point which gets called by the kernel 5527 * whenever multicast addresses must be enabled/disabled. 5528 * Return value: 5529 * void. 5530 */ 5531 static void stmmac_set_rx_mode(struct net_device *dev) 5532 { 5533 struct stmmac_priv *priv = netdev_priv(dev); 5534 5535 stmmac_set_filter(priv, priv->hw, dev); 5536 } 5537 5538 /** 5539 * stmmac_change_mtu - entry point to change MTU size for the device. 5540 * @dev : device pointer. 5541 * @new_mtu : the new MTU size for the device. 5542 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5543 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5544 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5545 * Return value: 5546 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5547 * file on failure. 5548 */ 5549 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5550 { 5551 struct stmmac_priv *priv = netdev_priv(dev); 5552 int txfifosz = priv->plat->tx_fifo_size; 5553 struct stmmac_dma_conf *dma_conf; 5554 const int mtu = new_mtu; 5555 int ret; 5556 5557 if (txfifosz == 0) 5558 txfifosz = priv->dma_cap.tx_fifo_size; 5559 5560 txfifosz /= priv->plat->tx_queues_to_use; 5561 5562 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5563 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5564 return -EINVAL; 5565 } 5566 5567 new_mtu = STMMAC_ALIGN(new_mtu); 5568 5569 /* If condition true, FIFO is too small or MTU too large */ 5570 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5571 return -EINVAL; 5572 5573 if (netif_running(dev)) { 5574 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5575 /* Try to allocate the new DMA conf with the new mtu */ 5576 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5577 if (IS_ERR(dma_conf)) { 5578 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5579 mtu); 5580 return PTR_ERR(dma_conf); 5581 } 5582 5583 stmmac_release(dev); 5584 5585 ret = __stmmac_open(dev, dma_conf); 5586 kfree(dma_conf); 5587 if (ret) { 5588 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5589 return ret; 5590 } 5591 5592 stmmac_set_rx_mode(dev); 5593 } 5594 5595 dev->mtu = mtu; 5596 netdev_update_features(dev); 5597 5598 return 0; 5599 } 5600 5601 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5602 netdev_features_t features) 5603 { 5604 struct stmmac_priv *priv = netdev_priv(dev); 5605 5606 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5607 features &= ~NETIF_F_RXCSUM; 5608 5609 if (!priv->plat->tx_coe) 5610 features &= ~NETIF_F_CSUM_MASK; 5611 5612 /* Some GMAC devices have a bugged Jumbo frame support that 5613 * needs to have the Tx COE disabled for oversized frames 5614 * (due to limited buffer sizes). In this case we disable 5615 * the TX csum insertion in the TDES and not use SF. 5616 */ 5617 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5618 features &= ~NETIF_F_CSUM_MASK; 5619 5620 /* Disable tso if asked by ethtool */ 5621 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5622 if (features & NETIF_F_TSO) 5623 priv->tso = true; 5624 else 5625 priv->tso = false; 5626 } 5627 5628 return features; 5629 } 5630 5631 static int stmmac_set_features(struct net_device *netdev, 5632 netdev_features_t features) 5633 { 5634 struct stmmac_priv *priv = netdev_priv(netdev); 5635 5636 /* Keep the COE Type in case of csum is supporting */ 5637 if (features & NETIF_F_RXCSUM) 5638 priv->hw->rx_csum = priv->plat->rx_coe; 5639 else 5640 priv->hw->rx_csum = 0; 5641 /* No check needed because rx_coe has been set before and it will be 5642 * fixed in case of issue. 5643 */ 5644 stmmac_rx_ipc(priv, priv->hw); 5645 5646 if (priv->sph_cap) { 5647 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5648 u32 chan; 5649 5650 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5651 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5652 } 5653 5654 return 0; 5655 } 5656 5657 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5658 { 5659 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5660 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5661 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5662 bool *hs_enable = &fpe_cfg->hs_enable; 5663 5664 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5665 return; 5666 5667 /* If LP has sent verify mPacket, LP is FPE capable */ 5668 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5669 if (*lp_state < FPE_STATE_CAPABLE) 5670 *lp_state = FPE_STATE_CAPABLE; 5671 5672 /* If user has requested FPE enable, quickly response */ 5673 if (*hs_enable) 5674 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5675 MPACKET_RESPONSE); 5676 } 5677 5678 /* If Local has sent verify mPacket, Local is FPE capable */ 5679 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5680 if (*lo_state < FPE_STATE_CAPABLE) 5681 *lo_state = FPE_STATE_CAPABLE; 5682 } 5683 5684 /* If LP has sent response mPacket, LP is entering FPE ON */ 5685 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5686 *lp_state = FPE_STATE_ENTERING_ON; 5687 5688 /* If Local has sent response mPacket, Local is entering FPE ON */ 5689 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5690 *lo_state = FPE_STATE_ENTERING_ON; 5691 5692 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5693 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5694 priv->fpe_wq) { 5695 queue_work(priv->fpe_wq, &priv->fpe_task); 5696 } 5697 } 5698 5699 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5700 { 5701 u32 rx_cnt = priv->plat->rx_queues_to_use; 5702 u32 tx_cnt = priv->plat->tx_queues_to_use; 5703 u32 queues_count; 5704 u32 queue; 5705 bool xmac; 5706 5707 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5708 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5709 5710 if (priv->irq_wake) 5711 pm_wakeup_event(priv->device, 0); 5712 5713 if (priv->dma_cap.estsel) 5714 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5715 &priv->xstats, tx_cnt); 5716 5717 if (priv->dma_cap.fpesel) { 5718 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5719 priv->dev); 5720 5721 stmmac_fpe_event_status(priv, status); 5722 } 5723 5724 /* To handle GMAC own interrupts */ 5725 if ((priv->plat->has_gmac) || xmac) { 5726 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5727 5728 if (unlikely(status)) { 5729 /* For LPI we need to save the tx status */ 5730 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5731 priv->tx_path_in_lpi_mode = true; 5732 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5733 priv->tx_path_in_lpi_mode = false; 5734 } 5735 5736 for (queue = 0; queue < queues_count; queue++) { 5737 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5738 queue); 5739 } 5740 5741 /* PCS link status */ 5742 if (priv->hw->pcs) { 5743 if (priv->xstats.pcs_link) 5744 netif_carrier_on(priv->dev); 5745 else 5746 netif_carrier_off(priv->dev); 5747 } 5748 5749 stmmac_timestamp_interrupt(priv, priv); 5750 } 5751 } 5752 5753 /** 5754 * stmmac_interrupt - main ISR 5755 * @irq: interrupt number. 5756 * @dev_id: to pass the net device pointer. 5757 * Description: this is the main driver interrupt service routine. 5758 * It can call: 5759 * o DMA service routine (to manage incoming frame reception and transmission 5760 * status) 5761 * o Core interrupts to manage: remote wake-up, management counter, LPI 5762 * interrupts. 5763 */ 5764 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5765 { 5766 struct net_device *dev = (struct net_device *)dev_id; 5767 struct stmmac_priv *priv = netdev_priv(dev); 5768 5769 /* Check if adapter is up */ 5770 if (test_bit(STMMAC_DOWN, &priv->state)) 5771 return IRQ_HANDLED; 5772 5773 /* Check if a fatal error happened */ 5774 if (stmmac_safety_feat_interrupt(priv)) 5775 return IRQ_HANDLED; 5776 5777 /* To handle Common interrupts */ 5778 stmmac_common_interrupt(priv); 5779 5780 /* To handle DMA interrupts */ 5781 stmmac_dma_interrupt(priv); 5782 5783 return IRQ_HANDLED; 5784 } 5785 5786 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5787 { 5788 struct net_device *dev = (struct net_device *)dev_id; 5789 struct stmmac_priv *priv = netdev_priv(dev); 5790 5791 if (unlikely(!dev)) { 5792 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5793 return IRQ_NONE; 5794 } 5795 5796 /* Check if adapter is up */ 5797 if (test_bit(STMMAC_DOWN, &priv->state)) 5798 return IRQ_HANDLED; 5799 5800 /* To handle Common interrupts */ 5801 stmmac_common_interrupt(priv); 5802 5803 return IRQ_HANDLED; 5804 } 5805 5806 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5807 { 5808 struct net_device *dev = (struct net_device *)dev_id; 5809 struct stmmac_priv *priv = netdev_priv(dev); 5810 5811 if (unlikely(!dev)) { 5812 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5813 return IRQ_NONE; 5814 } 5815 5816 /* Check if adapter is up */ 5817 if (test_bit(STMMAC_DOWN, &priv->state)) 5818 return IRQ_HANDLED; 5819 5820 /* Check if a fatal error happened */ 5821 stmmac_safety_feat_interrupt(priv); 5822 5823 return IRQ_HANDLED; 5824 } 5825 5826 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5827 { 5828 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5829 struct stmmac_dma_conf *dma_conf; 5830 int chan = tx_q->queue_index; 5831 struct stmmac_priv *priv; 5832 int status; 5833 5834 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5835 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5836 5837 if (unlikely(!data)) { 5838 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5839 return IRQ_NONE; 5840 } 5841 5842 /* Check if adapter is up */ 5843 if (test_bit(STMMAC_DOWN, &priv->state)) 5844 return IRQ_HANDLED; 5845 5846 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5847 5848 if (unlikely(status & tx_hard_error_bump_tc)) { 5849 /* Try to bump up the dma threshold on this failure */ 5850 stmmac_bump_dma_threshold(priv, chan); 5851 } else if (unlikely(status == tx_hard_error)) { 5852 stmmac_tx_err(priv, chan); 5853 } 5854 5855 return IRQ_HANDLED; 5856 } 5857 5858 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5859 { 5860 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5861 struct stmmac_dma_conf *dma_conf; 5862 int chan = rx_q->queue_index; 5863 struct stmmac_priv *priv; 5864 5865 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5866 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5867 5868 if (unlikely(!data)) { 5869 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5870 return IRQ_NONE; 5871 } 5872 5873 /* Check if adapter is up */ 5874 if (test_bit(STMMAC_DOWN, &priv->state)) 5875 return IRQ_HANDLED; 5876 5877 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5878 5879 return IRQ_HANDLED; 5880 } 5881 5882 #ifdef CONFIG_NET_POLL_CONTROLLER 5883 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5884 * to allow network I/O with interrupts disabled. 5885 */ 5886 static void stmmac_poll_controller(struct net_device *dev) 5887 { 5888 struct stmmac_priv *priv = netdev_priv(dev); 5889 int i; 5890 5891 /* If adapter is down, do nothing */ 5892 if (test_bit(STMMAC_DOWN, &priv->state)) 5893 return; 5894 5895 if (priv->plat->multi_msi_en) { 5896 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5897 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5898 5899 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5900 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5901 } else { 5902 disable_irq(dev->irq); 5903 stmmac_interrupt(dev->irq, dev); 5904 enable_irq(dev->irq); 5905 } 5906 } 5907 #endif 5908 5909 /** 5910 * stmmac_ioctl - Entry point for the Ioctl 5911 * @dev: Device pointer. 5912 * @rq: An IOCTL specefic structure, that can contain a pointer to 5913 * a proprietary structure used to pass information to the driver. 5914 * @cmd: IOCTL command 5915 * Description: 5916 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5917 */ 5918 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5919 { 5920 struct stmmac_priv *priv = netdev_priv (dev); 5921 int ret = -EOPNOTSUPP; 5922 5923 if (!netif_running(dev)) 5924 return -EINVAL; 5925 5926 switch (cmd) { 5927 case SIOCGMIIPHY: 5928 case SIOCGMIIREG: 5929 case SIOCSMIIREG: 5930 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5931 break; 5932 case SIOCSHWTSTAMP: 5933 ret = stmmac_hwtstamp_set(dev, rq); 5934 break; 5935 case SIOCGHWTSTAMP: 5936 ret = stmmac_hwtstamp_get(dev, rq); 5937 break; 5938 default: 5939 break; 5940 } 5941 5942 return ret; 5943 } 5944 5945 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5946 void *cb_priv) 5947 { 5948 struct stmmac_priv *priv = cb_priv; 5949 int ret = -EOPNOTSUPP; 5950 5951 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5952 return ret; 5953 5954 __stmmac_disable_all_queues(priv); 5955 5956 switch (type) { 5957 case TC_SETUP_CLSU32: 5958 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5959 break; 5960 case TC_SETUP_CLSFLOWER: 5961 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5962 break; 5963 default: 5964 break; 5965 } 5966 5967 stmmac_enable_all_queues(priv); 5968 return ret; 5969 } 5970 5971 static LIST_HEAD(stmmac_block_cb_list); 5972 5973 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5974 void *type_data) 5975 { 5976 struct stmmac_priv *priv = netdev_priv(ndev); 5977 5978 switch (type) { 5979 case TC_SETUP_BLOCK: 5980 return flow_block_cb_setup_simple(type_data, 5981 &stmmac_block_cb_list, 5982 stmmac_setup_tc_block_cb, 5983 priv, priv, true); 5984 case TC_SETUP_QDISC_CBS: 5985 return stmmac_tc_setup_cbs(priv, priv, type_data); 5986 case TC_SETUP_QDISC_TAPRIO: 5987 return stmmac_tc_setup_taprio(priv, priv, type_data); 5988 case TC_SETUP_QDISC_ETF: 5989 return stmmac_tc_setup_etf(priv, priv, type_data); 5990 default: 5991 return -EOPNOTSUPP; 5992 } 5993 } 5994 5995 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5996 struct net_device *sb_dev) 5997 { 5998 int gso = skb_shinfo(skb)->gso_type; 5999 6000 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6001 /* 6002 * There is no way to determine the number of TSO/USO 6003 * capable Queues. Let's use always the Queue 0 6004 * because if TSO/USO is supported then at least this 6005 * one will be capable. 6006 */ 6007 return 0; 6008 } 6009 6010 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6011 } 6012 6013 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6014 { 6015 struct stmmac_priv *priv = netdev_priv(ndev); 6016 int ret = 0; 6017 6018 ret = pm_runtime_resume_and_get(priv->device); 6019 if (ret < 0) 6020 return ret; 6021 6022 ret = eth_mac_addr(ndev, addr); 6023 if (ret) 6024 goto set_mac_error; 6025 6026 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6027 6028 set_mac_error: 6029 pm_runtime_put(priv->device); 6030 6031 return ret; 6032 } 6033 6034 #ifdef CONFIG_DEBUG_FS 6035 static struct dentry *stmmac_fs_dir; 6036 6037 static void sysfs_display_ring(void *head, int size, int extend_desc, 6038 struct seq_file *seq, dma_addr_t dma_phy_addr) 6039 { 6040 int i; 6041 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6042 struct dma_desc *p = (struct dma_desc *)head; 6043 dma_addr_t dma_addr; 6044 6045 for (i = 0; i < size; i++) { 6046 if (extend_desc) { 6047 dma_addr = dma_phy_addr + i * sizeof(*ep); 6048 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6049 i, &dma_addr, 6050 le32_to_cpu(ep->basic.des0), 6051 le32_to_cpu(ep->basic.des1), 6052 le32_to_cpu(ep->basic.des2), 6053 le32_to_cpu(ep->basic.des3)); 6054 ep++; 6055 } else { 6056 dma_addr = dma_phy_addr + i * sizeof(*p); 6057 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6058 i, &dma_addr, 6059 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6060 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6061 p++; 6062 } 6063 seq_printf(seq, "\n"); 6064 } 6065 } 6066 6067 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6068 { 6069 struct net_device *dev = seq->private; 6070 struct stmmac_priv *priv = netdev_priv(dev); 6071 u32 rx_count = priv->plat->rx_queues_to_use; 6072 u32 tx_count = priv->plat->tx_queues_to_use; 6073 u32 queue; 6074 6075 if ((dev->flags & IFF_UP) == 0) 6076 return 0; 6077 6078 for (queue = 0; queue < rx_count; queue++) { 6079 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6080 6081 seq_printf(seq, "RX Queue %d:\n", queue); 6082 6083 if (priv->extend_desc) { 6084 seq_printf(seq, "Extended descriptor ring:\n"); 6085 sysfs_display_ring((void *)rx_q->dma_erx, 6086 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6087 } else { 6088 seq_printf(seq, "Descriptor ring:\n"); 6089 sysfs_display_ring((void *)rx_q->dma_rx, 6090 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6091 } 6092 } 6093 6094 for (queue = 0; queue < tx_count; queue++) { 6095 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6096 6097 seq_printf(seq, "TX Queue %d:\n", queue); 6098 6099 if (priv->extend_desc) { 6100 seq_printf(seq, "Extended descriptor ring:\n"); 6101 sysfs_display_ring((void *)tx_q->dma_etx, 6102 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6103 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6104 seq_printf(seq, "Descriptor ring:\n"); 6105 sysfs_display_ring((void *)tx_q->dma_tx, 6106 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6107 } 6108 } 6109 6110 return 0; 6111 } 6112 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6113 6114 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6115 { 6116 struct net_device *dev = seq->private; 6117 struct stmmac_priv *priv = netdev_priv(dev); 6118 6119 if (!priv->hw_cap_support) { 6120 seq_printf(seq, "DMA HW features not supported\n"); 6121 return 0; 6122 } 6123 6124 seq_printf(seq, "==============================\n"); 6125 seq_printf(seq, "\tDMA HW features\n"); 6126 seq_printf(seq, "==============================\n"); 6127 6128 seq_printf(seq, "\t10/100 Mbps: %s\n", 6129 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6130 seq_printf(seq, "\t1000 Mbps: %s\n", 6131 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6132 seq_printf(seq, "\tHalf duplex: %s\n", 6133 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6134 seq_printf(seq, "\tHash Filter: %s\n", 6135 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6136 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6137 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6138 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6139 (priv->dma_cap.pcs) ? "Y" : "N"); 6140 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6141 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6142 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6143 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6144 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6145 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6146 seq_printf(seq, "\tRMON module: %s\n", 6147 (priv->dma_cap.rmon) ? "Y" : "N"); 6148 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6149 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6150 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6151 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6152 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6153 (priv->dma_cap.eee) ? "Y" : "N"); 6154 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6155 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6156 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6157 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6158 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6159 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6160 } else { 6161 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6162 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6163 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6164 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6165 } 6166 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6167 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6168 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6169 priv->dma_cap.number_rx_channel); 6170 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6171 priv->dma_cap.number_tx_channel); 6172 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6173 priv->dma_cap.number_rx_queues); 6174 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6175 priv->dma_cap.number_tx_queues); 6176 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6177 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6178 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6179 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6180 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6181 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6182 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6183 priv->dma_cap.pps_out_num); 6184 seq_printf(seq, "\tSafety Features: %s\n", 6185 priv->dma_cap.asp ? "Y" : "N"); 6186 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6187 priv->dma_cap.frpsel ? "Y" : "N"); 6188 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6189 priv->dma_cap.addr64); 6190 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6191 priv->dma_cap.rssen ? "Y" : "N"); 6192 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6193 priv->dma_cap.vlhash ? "Y" : "N"); 6194 seq_printf(seq, "\tSplit Header: %s\n", 6195 priv->dma_cap.sphen ? "Y" : "N"); 6196 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6197 priv->dma_cap.vlins ? "Y" : "N"); 6198 seq_printf(seq, "\tDouble VLAN: %s\n", 6199 priv->dma_cap.dvlan ? "Y" : "N"); 6200 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6201 priv->dma_cap.l3l4fnum); 6202 seq_printf(seq, "\tARP Offloading: %s\n", 6203 priv->dma_cap.arpoffsel ? "Y" : "N"); 6204 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6205 priv->dma_cap.estsel ? "Y" : "N"); 6206 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6207 priv->dma_cap.fpesel ? "Y" : "N"); 6208 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6209 priv->dma_cap.tbssel ? "Y" : "N"); 6210 return 0; 6211 } 6212 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6213 6214 /* Use network device events to rename debugfs file entries. 6215 */ 6216 static int stmmac_device_event(struct notifier_block *unused, 6217 unsigned long event, void *ptr) 6218 { 6219 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6220 struct stmmac_priv *priv = netdev_priv(dev); 6221 6222 if (dev->netdev_ops != &stmmac_netdev_ops) 6223 goto done; 6224 6225 switch (event) { 6226 case NETDEV_CHANGENAME: 6227 if (priv->dbgfs_dir) 6228 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6229 priv->dbgfs_dir, 6230 stmmac_fs_dir, 6231 dev->name); 6232 break; 6233 } 6234 done: 6235 return NOTIFY_DONE; 6236 } 6237 6238 static struct notifier_block stmmac_notifier = { 6239 .notifier_call = stmmac_device_event, 6240 }; 6241 6242 static void stmmac_init_fs(struct net_device *dev) 6243 { 6244 struct stmmac_priv *priv = netdev_priv(dev); 6245 6246 rtnl_lock(); 6247 6248 /* Create per netdev entries */ 6249 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6250 6251 /* Entry to report DMA RX/TX rings */ 6252 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6253 &stmmac_rings_status_fops); 6254 6255 /* Entry to report the DMA HW features */ 6256 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6257 &stmmac_dma_cap_fops); 6258 6259 rtnl_unlock(); 6260 } 6261 6262 static void stmmac_exit_fs(struct net_device *dev) 6263 { 6264 struct stmmac_priv *priv = netdev_priv(dev); 6265 6266 debugfs_remove_recursive(priv->dbgfs_dir); 6267 } 6268 #endif /* CONFIG_DEBUG_FS */ 6269 6270 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6271 { 6272 unsigned char *data = (unsigned char *)&vid_le; 6273 unsigned char data_byte = 0; 6274 u32 crc = ~0x0; 6275 u32 temp = 0; 6276 int i, bits; 6277 6278 bits = get_bitmask_order(VLAN_VID_MASK); 6279 for (i = 0; i < bits; i++) { 6280 if ((i % 8) == 0) 6281 data_byte = data[i / 8]; 6282 6283 temp = ((crc & 1) ^ data_byte) & 1; 6284 crc >>= 1; 6285 data_byte >>= 1; 6286 6287 if (temp) 6288 crc ^= 0xedb88320; 6289 } 6290 6291 return crc; 6292 } 6293 6294 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6295 { 6296 u32 crc, hash = 0; 6297 __le16 pmatch = 0; 6298 int count = 0; 6299 u16 vid = 0; 6300 6301 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6302 __le16 vid_le = cpu_to_le16(vid); 6303 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6304 hash |= (1 << crc); 6305 count++; 6306 } 6307 6308 if (!priv->dma_cap.vlhash) { 6309 if (count > 2) /* VID = 0 always passes filter */ 6310 return -EOPNOTSUPP; 6311 6312 pmatch = cpu_to_le16(vid); 6313 hash = 0; 6314 } 6315 6316 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6317 } 6318 6319 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6320 { 6321 struct stmmac_priv *priv = netdev_priv(ndev); 6322 bool is_double = false; 6323 int ret; 6324 6325 if (be16_to_cpu(proto) == ETH_P_8021AD) 6326 is_double = true; 6327 6328 set_bit(vid, priv->active_vlans); 6329 ret = stmmac_vlan_update(priv, is_double); 6330 if (ret) { 6331 clear_bit(vid, priv->active_vlans); 6332 return ret; 6333 } 6334 6335 if (priv->hw->num_vlan) { 6336 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6337 if (ret) 6338 return ret; 6339 } 6340 6341 return 0; 6342 } 6343 6344 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6345 { 6346 struct stmmac_priv *priv = netdev_priv(ndev); 6347 bool is_double = false; 6348 int ret; 6349 6350 ret = pm_runtime_resume_and_get(priv->device); 6351 if (ret < 0) 6352 return ret; 6353 6354 if (be16_to_cpu(proto) == ETH_P_8021AD) 6355 is_double = true; 6356 6357 clear_bit(vid, priv->active_vlans); 6358 6359 if (priv->hw->num_vlan) { 6360 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6361 if (ret) 6362 goto del_vlan_error; 6363 } 6364 6365 ret = stmmac_vlan_update(priv, is_double); 6366 6367 del_vlan_error: 6368 pm_runtime_put(priv->device); 6369 6370 return ret; 6371 } 6372 6373 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6374 { 6375 struct stmmac_priv *priv = netdev_priv(dev); 6376 6377 switch (bpf->command) { 6378 case XDP_SETUP_PROG: 6379 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6380 case XDP_SETUP_XSK_POOL: 6381 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6382 bpf->xsk.queue_id); 6383 default: 6384 return -EOPNOTSUPP; 6385 } 6386 } 6387 6388 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6389 struct xdp_frame **frames, u32 flags) 6390 { 6391 struct stmmac_priv *priv = netdev_priv(dev); 6392 int cpu = smp_processor_id(); 6393 struct netdev_queue *nq; 6394 int i, nxmit = 0; 6395 int queue; 6396 6397 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6398 return -ENETDOWN; 6399 6400 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6401 return -EINVAL; 6402 6403 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6404 nq = netdev_get_tx_queue(priv->dev, queue); 6405 6406 __netif_tx_lock(nq, cpu); 6407 /* Avoids TX time-out as we are sharing with slow path */ 6408 txq_trans_cond_update(nq); 6409 6410 for (i = 0; i < num_frames; i++) { 6411 int res; 6412 6413 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6414 if (res == STMMAC_XDP_CONSUMED) 6415 break; 6416 6417 nxmit++; 6418 } 6419 6420 if (flags & XDP_XMIT_FLUSH) { 6421 stmmac_flush_tx_descriptors(priv, queue); 6422 stmmac_tx_timer_arm(priv, queue); 6423 } 6424 6425 __netif_tx_unlock(nq); 6426 6427 return nxmit; 6428 } 6429 6430 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6431 { 6432 struct stmmac_channel *ch = &priv->channel[queue]; 6433 unsigned long flags; 6434 6435 spin_lock_irqsave(&ch->lock, flags); 6436 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6437 spin_unlock_irqrestore(&ch->lock, flags); 6438 6439 stmmac_stop_rx_dma(priv, queue); 6440 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6441 } 6442 6443 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6444 { 6445 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6446 struct stmmac_channel *ch = &priv->channel[queue]; 6447 unsigned long flags; 6448 u32 buf_size; 6449 int ret; 6450 6451 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6452 if (ret) { 6453 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6454 return; 6455 } 6456 6457 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6458 if (ret) { 6459 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6460 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6461 return; 6462 } 6463 6464 stmmac_reset_rx_queue(priv, queue); 6465 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6466 6467 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6468 rx_q->dma_rx_phy, rx_q->queue_index); 6469 6470 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6471 sizeof(struct dma_desc)); 6472 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6473 rx_q->rx_tail_addr, rx_q->queue_index); 6474 6475 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6476 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6477 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6478 buf_size, 6479 rx_q->queue_index); 6480 } else { 6481 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6482 priv->dma_conf.dma_buf_sz, 6483 rx_q->queue_index); 6484 } 6485 6486 stmmac_start_rx_dma(priv, queue); 6487 6488 spin_lock_irqsave(&ch->lock, flags); 6489 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6490 spin_unlock_irqrestore(&ch->lock, flags); 6491 } 6492 6493 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6494 { 6495 struct stmmac_channel *ch = &priv->channel[queue]; 6496 unsigned long flags; 6497 6498 spin_lock_irqsave(&ch->lock, flags); 6499 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6500 spin_unlock_irqrestore(&ch->lock, flags); 6501 6502 stmmac_stop_tx_dma(priv, queue); 6503 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6504 } 6505 6506 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6507 { 6508 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6509 struct stmmac_channel *ch = &priv->channel[queue]; 6510 unsigned long flags; 6511 int ret; 6512 6513 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6514 if (ret) { 6515 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6516 return; 6517 } 6518 6519 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6520 if (ret) { 6521 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6522 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6523 return; 6524 } 6525 6526 stmmac_reset_tx_queue(priv, queue); 6527 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6528 6529 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6530 tx_q->dma_tx_phy, tx_q->queue_index); 6531 6532 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6533 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6534 6535 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6536 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6537 tx_q->tx_tail_addr, tx_q->queue_index); 6538 6539 stmmac_start_tx_dma(priv, queue); 6540 6541 spin_lock_irqsave(&ch->lock, flags); 6542 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6543 spin_unlock_irqrestore(&ch->lock, flags); 6544 } 6545 6546 void stmmac_xdp_release(struct net_device *dev) 6547 { 6548 struct stmmac_priv *priv = netdev_priv(dev); 6549 u32 chan; 6550 6551 /* Disable NAPI process */ 6552 stmmac_disable_all_queues(priv); 6553 6554 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6555 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6556 6557 /* Free the IRQ lines */ 6558 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6559 6560 /* Stop TX/RX DMA channels */ 6561 stmmac_stop_all_dma(priv); 6562 6563 /* Release and free the Rx/Tx resources */ 6564 free_dma_desc_resources(priv, &priv->dma_conf); 6565 6566 /* Disable the MAC Rx/Tx */ 6567 stmmac_mac_set(priv, priv->ioaddr, false); 6568 6569 /* set trans_start so we don't get spurious 6570 * watchdogs during reset 6571 */ 6572 netif_trans_update(dev); 6573 netif_carrier_off(dev); 6574 } 6575 6576 int stmmac_xdp_open(struct net_device *dev) 6577 { 6578 struct stmmac_priv *priv = netdev_priv(dev); 6579 u32 rx_cnt = priv->plat->rx_queues_to_use; 6580 u32 tx_cnt = priv->plat->tx_queues_to_use; 6581 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6582 struct stmmac_rx_queue *rx_q; 6583 struct stmmac_tx_queue *tx_q; 6584 u32 buf_size; 6585 bool sph_en; 6586 u32 chan; 6587 int ret; 6588 6589 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6590 if (ret < 0) { 6591 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6592 __func__); 6593 goto dma_desc_error; 6594 } 6595 6596 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6597 if (ret < 0) { 6598 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6599 __func__); 6600 goto init_error; 6601 } 6602 6603 /* DMA CSR Channel configuration */ 6604 for (chan = 0; chan < dma_csr_ch; chan++) { 6605 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6606 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6607 } 6608 6609 /* Adjust Split header */ 6610 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6611 6612 /* DMA RX Channel Configuration */ 6613 for (chan = 0; chan < rx_cnt; chan++) { 6614 rx_q = &priv->dma_conf.rx_queue[chan]; 6615 6616 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6617 rx_q->dma_rx_phy, chan); 6618 6619 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6620 (rx_q->buf_alloc_num * 6621 sizeof(struct dma_desc)); 6622 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6623 rx_q->rx_tail_addr, chan); 6624 6625 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6626 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6627 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6628 buf_size, 6629 rx_q->queue_index); 6630 } else { 6631 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6632 priv->dma_conf.dma_buf_sz, 6633 rx_q->queue_index); 6634 } 6635 6636 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6637 } 6638 6639 /* DMA TX Channel Configuration */ 6640 for (chan = 0; chan < tx_cnt; chan++) { 6641 tx_q = &priv->dma_conf.tx_queue[chan]; 6642 6643 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6644 tx_q->dma_tx_phy, chan); 6645 6646 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6647 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6648 tx_q->tx_tail_addr, chan); 6649 6650 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6651 tx_q->txtimer.function = stmmac_tx_timer; 6652 } 6653 6654 /* Enable the MAC Rx/Tx */ 6655 stmmac_mac_set(priv, priv->ioaddr, true); 6656 6657 /* Start Rx & Tx DMA Channels */ 6658 stmmac_start_all_dma(priv); 6659 6660 ret = stmmac_request_irq(dev); 6661 if (ret) 6662 goto irq_error; 6663 6664 /* Enable NAPI process*/ 6665 stmmac_enable_all_queues(priv); 6666 netif_carrier_on(dev); 6667 netif_tx_start_all_queues(dev); 6668 stmmac_enable_all_dma_irq(priv); 6669 6670 return 0; 6671 6672 irq_error: 6673 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6674 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6675 6676 stmmac_hw_teardown(dev); 6677 init_error: 6678 free_dma_desc_resources(priv, &priv->dma_conf); 6679 dma_desc_error: 6680 return ret; 6681 } 6682 6683 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6684 { 6685 struct stmmac_priv *priv = netdev_priv(dev); 6686 struct stmmac_rx_queue *rx_q; 6687 struct stmmac_tx_queue *tx_q; 6688 struct stmmac_channel *ch; 6689 6690 if (test_bit(STMMAC_DOWN, &priv->state) || 6691 !netif_carrier_ok(priv->dev)) 6692 return -ENETDOWN; 6693 6694 if (!stmmac_xdp_is_enabled(priv)) 6695 return -EINVAL; 6696 6697 if (queue >= priv->plat->rx_queues_to_use || 6698 queue >= priv->plat->tx_queues_to_use) 6699 return -EINVAL; 6700 6701 rx_q = &priv->dma_conf.rx_queue[queue]; 6702 tx_q = &priv->dma_conf.tx_queue[queue]; 6703 ch = &priv->channel[queue]; 6704 6705 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6706 return -EINVAL; 6707 6708 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6709 /* EQoS does not have per-DMA channel SW interrupt, 6710 * so we schedule RX Napi straight-away. 6711 */ 6712 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6713 __napi_schedule(&ch->rxtx_napi); 6714 } 6715 6716 return 0; 6717 } 6718 6719 static const struct net_device_ops stmmac_netdev_ops = { 6720 .ndo_open = stmmac_open, 6721 .ndo_start_xmit = stmmac_xmit, 6722 .ndo_stop = stmmac_release, 6723 .ndo_change_mtu = stmmac_change_mtu, 6724 .ndo_fix_features = stmmac_fix_features, 6725 .ndo_set_features = stmmac_set_features, 6726 .ndo_set_rx_mode = stmmac_set_rx_mode, 6727 .ndo_tx_timeout = stmmac_tx_timeout, 6728 .ndo_eth_ioctl = stmmac_ioctl, 6729 .ndo_setup_tc = stmmac_setup_tc, 6730 .ndo_select_queue = stmmac_select_queue, 6731 #ifdef CONFIG_NET_POLL_CONTROLLER 6732 .ndo_poll_controller = stmmac_poll_controller, 6733 #endif 6734 .ndo_set_mac_address = stmmac_set_mac_address, 6735 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6736 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6737 .ndo_bpf = stmmac_bpf, 6738 .ndo_xdp_xmit = stmmac_xdp_xmit, 6739 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6740 }; 6741 6742 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6743 { 6744 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6745 return; 6746 if (test_bit(STMMAC_DOWN, &priv->state)) 6747 return; 6748 6749 netdev_err(priv->dev, "Reset adapter.\n"); 6750 6751 rtnl_lock(); 6752 netif_trans_update(priv->dev); 6753 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6754 usleep_range(1000, 2000); 6755 6756 set_bit(STMMAC_DOWN, &priv->state); 6757 dev_close(priv->dev); 6758 dev_open(priv->dev, NULL); 6759 clear_bit(STMMAC_DOWN, &priv->state); 6760 clear_bit(STMMAC_RESETING, &priv->state); 6761 rtnl_unlock(); 6762 } 6763 6764 static void stmmac_service_task(struct work_struct *work) 6765 { 6766 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6767 service_task); 6768 6769 stmmac_reset_subtask(priv); 6770 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6771 } 6772 6773 /** 6774 * stmmac_hw_init - Init the MAC device 6775 * @priv: driver private structure 6776 * Description: this function is to configure the MAC device according to 6777 * some platform parameters or the HW capability register. It prepares the 6778 * driver to use either ring or chain modes and to setup either enhanced or 6779 * normal descriptors. 6780 */ 6781 static int stmmac_hw_init(struct stmmac_priv *priv) 6782 { 6783 int ret; 6784 6785 /* dwmac-sun8i only work in chain mode */ 6786 if (priv->plat->has_sun8i) 6787 chain_mode = 1; 6788 priv->chain_mode = chain_mode; 6789 6790 /* Initialize HW Interface */ 6791 ret = stmmac_hwif_init(priv); 6792 if (ret) 6793 return ret; 6794 6795 /* Get the HW capability (new GMAC newer than 3.50a) */ 6796 priv->hw_cap_support = stmmac_get_hw_features(priv); 6797 if (priv->hw_cap_support) { 6798 dev_info(priv->device, "DMA HW capability register supported\n"); 6799 6800 /* We can override some gmac/dma configuration fields: e.g. 6801 * enh_desc, tx_coe (e.g. that are passed through the 6802 * platform) with the values from the HW capability 6803 * register (if supported). 6804 */ 6805 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6806 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6807 !priv->plat->use_phy_wol; 6808 priv->hw->pmt = priv->plat->pmt; 6809 if (priv->dma_cap.hash_tb_sz) { 6810 priv->hw->multicast_filter_bins = 6811 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6812 priv->hw->mcast_bits_log2 = 6813 ilog2(priv->hw->multicast_filter_bins); 6814 } 6815 6816 /* TXCOE doesn't work in thresh DMA mode */ 6817 if (priv->plat->force_thresh_dma_mode) 6818 priv->plat->tx_coe = 0; 6819 else 6820 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6821 6822 /* In case of GMAC4 rx_coe is from HW cap register. */ 6823 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6824 6825 if (priv->dma_cap.rx_coe_type2) 6826 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6827 else if (priv->dma_cap.rx_coe_type1) 6828 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6829 6830 } else { 6831 dev_info(priv->device, "No HW DMA feature register supported\n"); 6832 } 6833 6834 if (priv->plat->rx_coe) { 6835 priv->hw->rx_csum = priv->plat->rx_coe; 6836 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6837 if (priv->synopsys_id < DWMAC_CORE_4_00) 6838 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6839 } 6840 if (priv->plat->tx_coe) 6841 dev_info(priv->device, "TX Checksum insertion supported\n"); 6842 6843 if (priv->plat->pmt) { 6844 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6845 device_set_wakeup_capable(priv->device, 1); 6846 } 6847 6848 if (priv->dma_cap.tsoen) 6849 dev_info(priv->device, "TSO supported\n"); 6850 6851 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6852 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6853 6854 /* Run HW quirks, if any */ 6855 if (priv->hwif_quirks) { 6856 ret = priv->hwif_quirks(priv); 6857 if (ret) 6858 return ret; 6859 } 6860 6861 /* Rx Watchdog is available in the COREs newer than the 3.40. 6862 * In some case, for example on bugged HW this feature 6863 * has to be disable and this can be done by passing the 6864 * riwt_off field from the platform. 6865 */ 6866 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6867 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6868 priv->use_riwt = 1; 6869 dev_info(priv->device, 6870 "Enable RX Mitigation via HW Watchdog Timer\n"); 6871 } 6872 6873 return 0; 6874 } 6875 6876 static void stmmac_napi_add(struct net_device *dev) 6877 { 6878 struct stmmac_priv *priv = netdev_priv(dev); 6879 u32 queue, maxq; 6880 6881 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6882 6883 for (queue = 0; queue < maxq; queue++) { 6884 struct stmmac_channel *ch = &priv->channel[queue]; 6885 6886 ch->priv_data = priv; 6887 ch->index = queue; 6888 spin_lock_init(&ch->lock); 6889 6890 if (queue < priv->plat->rx_queues_to_use) { 6891 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 6892 } 6893 if (queue < priv->plat->tx_queues_to_use) { 6894 netif_napi_add_tx(dev, &ch->tx_napi, 6895 stmmac_napi_poll_tx); 6896 } 6897 if (queue < priv->plat->rx_queues_to_use && 6898 queue < priv->plat->tx_queues_to_use) { 6899 netif_napi_add(dev, &ch->rxtx_napi, 6900 stmmac_napi_poll_rxtx); 6901 } 6902 } 6903 } 6904 6905 static void stmmac_napi_del(struct net_device *dev) 6906 { 6907 struct stmmac_priv *priv = netdev_priv(dev); 6908 u32 queue, maxq; 6909 6910 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6911 6912 for (queue = 0; queue < maxq; queue++) { 6913 struct stmmac_channel *ch = &priv->channel[queue]; 6914 6915 if (queue < priv->plat->rx_queues_to_use) 6916 netif_napi_del(&ch->rx_napi); 6917 if (queue < priv->plat->tx_queues_to_use) 6918 netif_napi_del(&ch->tx_napi); 6919 if (queue < priv->plat->rx_queues_to_use && 6920 queue < priv->plat->tx_queues_to_use) { 6921 netif_napi_del(&ch->rxtx_napi); 6922 } 6923 } 6924 } 6925 6926 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6927 { 6928 struct stmmac_priv *priv = netdev_priv(dev); 6929 int ret = 0; 6930 6931 if (netif_running(dev)) 6932 stmmac_release(dev); 6933 6934 stmmac_napi_del(dev); 6935 6936 priv->plat->rx_queues_to_use = rx_cnt; 6937 priv->plat->tx_queues_to_use = tx_cnt; 6938 6939 stmmac_napi_add(dev); 6940 6941 if (netif_running(dev)) 6942 ret = stmmac_open(dev); 6943 6944 return ret; 6945 } 6946 6947 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6948 { 6949 struct stmmac_priv *priv = netdev_priv(dev); 6950 int ret = 0; 6951 6952 if (netif_running(dev)) 6953 stmmac_release(dev); 6954 6955 priv->dma_conf.dma_rx_size = rx_size; 6956 priv->dma_conf.dma_tx_size = tx_size; 6957 6958 if (netif_running(dev)) 6959 ret = stmmac_open(dev); 6960 6961 return ret; 6962 } 6963 6964 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6965 static void stmmac_fpe_lp_task(struct work_struct *work) 6966 { 6967 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6968 fpe_task); 6969 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6970 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6971 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6972 bool *hs_enable = &fpe_cfg->hs_enable; 6973 bool *enable = &fpe_cfg->enable; 6974 int retries = 20; 6975 6976 while (retries-- > 0) { 6977 /* Bail out immediately if FPE handshake is OFF */ 6978 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6979 break; 6980 6981 if (*lo_state == FPE_STATE_ENTERING_ON && 6982 *lp_state == FPE_STATE_ENTERING_ON) { 6983 stmmac_fpe_configure(priv, priv->ioaddr, 6984 priv->plat->tx_queues_to_use, 6985 priv->plat->rx_queues_to_use, 6986 *enable); 6987 6988 netdev_info(priv->dev, "configured FPE\n"); 6989 6990 *lo_state = FPE_STATE_ON; 6991 *lp_state = FPE_STATE_ON; 6992 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6993 break; 6994 } 6995 6996 if ((*lo_state == FPE_STATE_CAPABLE || 6997 *lo_state == FPE_STATE_ENTERING_ON) && 6998 *lp_state != FPE_STATE_ON) { 6999 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7000 *lo_state, *lp_state); 7001 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7002 MPACKET_VERIFY); 7003 } 7004 /* Sleep then retry */ 7005 msleep(500); 7006 } 7007 7008 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7009 } 7010 7011 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7012 { 7013 if (priv->plat->fpe_cfg->hs_enable != enable) { 7014 if (enable) { 7015 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7016 MPACKET_VERIFY); 7017 } else { 7018 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7019 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7020 } 7021 7022 priv->plat->fpe_cfg->hs_enable = enable; 7023 } 7024 } 7025 7026 /** 7027 * stmmac_dvr_probe 7028 * @device: device pointer 7029 * @plat_dat: platform data pointer 7030 * @res: stmmac resource pointer 7031 * Description: this is the main probe function used to 7032 * call the alloc_etherdev, allocate the priv structure. 7033 * Return: 7034 * returns 0 on success, otherwise errno. 7035 */ 7036 int stmmac_dvr_probe(struct device *device, 7037 struct plat_stmmacenet_data *plat_dat, 7038 struct stmmac_resources *res) 7039 { 7040 struct net_device *ndev = NULL; 7041 struct stmmac_priv *priv; 7042 u32 rxq; 7043 int i, ret = 0; 7044 7045 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7046 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7047 if (!ndev) 7048 return -ENOMEM; 7049 7050 SET_NETDEV_DEV(ndev, device); 7051 7052 priv = netdev_priv(ndev); 7053 priv->device = device; 7054 priv->dev = ndev; 7055 7056 stmmac_set_ethtool_ops(ndev); 7057 priv->pause = pause; 7058 priv->plat = plat_dat; 7059 priv->ioaddr = res->addr; 7060 priv->dev->base_addr = (unsigned long)res->addr; 7061 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7062 7063 priv->dev->irq = res->irq; 7064 priv->wol_irq = res->wol_irq; 7065 priv->lpi_irq = res->lpi_irq; 7066 priv->sfty_ce_irq = res->sfty_ce_irq; 7067 priv->sfty_ue_irq = res->sfty_ue_irq; 7068 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7069 priv->rx_irq[i] = res->rx_irq[i]; 7070 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7071 priv->tx_irq[i] = res->tx_irq[i]; 7072 7073 if (!is_zero_ether_addr(res->mac)) 7074 eth_hw_addr_set(priv->dev, res->mac); 7075 7076 dev_set_drvdata(device, priv->dev); 7077 7078 /* Verify driver arguments */ 7079 stmmac_verify_args(); 7080 7081 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7082 if (!priv->af_xdp_zc_qps) 7083 return -ENOMEM; 7084 7085 /* Allocate workqueue */ 7086 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7087 if (!priv->wq) { 7088 dev_err(priv->device, "failed to create workqueue\n"); 7089 return -ENOMEM; 7090 } 7091 7092 INIT_WORK(&priv->service_task, stmmac_service_task); 7093 7094 /* Initialize Link Partner FPE workqueue */ 7095 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7096 7097 /* Override with kernel parameters if supplied XXX CRS XXX 7098 * this needs to have multiple instances 7099 */ 7100 if ((phyaddr >= 0) && (phyaddr <= 31)) 7101 priv->plat->phy_addr = phyaddr; 7102 7103 if (priv->plat->stmmac_rst) { 7104 ret = reset_control_assert(priv->plat->stmmac_rst); 7105 reset_control_deassert(priv->plat->stmmac_rst); 7106 /* Some reset controllers have only reset callback instead of 7107 * assert + deassert callbacks pair. 7108 */ 7109 if (ret == -ENOTSUPP) 7110 reset_control_reset(priv->plat->stmmac_rst); 7111 } 7112 7113 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7114 if (ret == -ENOTSUPP) 7115 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7116 ERR_PTR(ret)); 7117 7118 /* Init MAC and get the capabilities */ 7119 ret = stmmac_hw_init(priv); 7120 if (ret) 7121 goto error_hw_init; 7122 7123 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7124 */ 7125 if (priv->synopsys_id < DWMAC_CORE_5_20) 7126 priv->plat->dma_cfg->dche = false; 7127 7128 stmmac_check_ether_addr(priv); 7129 7130 ndev->netdev_ops = &stmmac_netdev_ops; 7131 7132 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7133 NETIF_F_RXCSUM; 7134 7135 ret = stmmac_tc_init(priv, priv); 7136 if (!ret) { 7137 ndev->hw_features |= NETIF_F_HW_TC; 7138 } 7139 7140 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7141 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7142 if (priv->plat->has_gmac4) 7143 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7144 priv->tso = true; 7145 dev_info(priv->device, "TSO feature enabled\n"); 7146 } 7147 7148 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7149 ndev->hw_features |= NETIF_F_GRO; 7150 priv->sph_cap = true; 7151 priv->sph = priv->sph_cap; 7152 dev_info(priv->device, "SPH feature enabled\n"); 7153 } 7154 7155 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7156 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7157 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7158 * So overwrite dma_cap.addr64 according to HW real design. 7159 */ 7160 if (priv->plat->addr64) 7161 priv->dma_cap.addr64 = priv->plat->addr64; 7162 7163 if (priv->dma_cap.addr64) { 7164 ret = dma_set_mask_and_coherent(device, 7165 DMA_BIT_MASK(priv->dma_cap.addr64)); 7166 if (!ret) { 7167 dev_info(priv->device, "Using %d bits DMA width\n", 7168 priv->dma_cap.addr64); 7169 7170 /* 7171 * If more than 32 bits can be addressed, make sure to 7172 * enable enhanced addressing mode. 7173 */ 7174 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7175 priv->plat->dma_cfg->eame = true; 7176 } else { 7177 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7178 if (ret) { 7179 dev_err(priv->device, "Failed to set DMA Mask\n"); 7180 goto error_hw_init; 7181 } 7182 7183 priv->dma_cap.addr64 = 32; 7184 } 7185 } 7186 7187 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7188 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7189 #ifdef STMMAC_VLAN_TAG_USED 7190 /* Both mac100 and gmac support receive VLAN tag detection */ 7191 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7192 if (priv->dma_cap.vlhash) { 7193 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7194 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7195 } 7196 if (priv->dma_cap.vlins) { 7197 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7198 if (priv->dma_cap.dvlan) 7199 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7200 } 7201 #endif 7202 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7203 7204 /* Initialize RSS */ 7205 rxq = priv->plat->rx_queues_to_use; 7206 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7207 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7208 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7209 7210 if (priv->dma_cap.rssen && priv->plat->rss_en) 7211 ndev->features |= NETIF_F_RXHASH; 7212 7213 /* MTU range: 46 - hw-specific max */ 7214 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7215 if (priv->plat->has_xgmac) 7216 ndev->max_mtu = XGMAC_JUMBO_LEN; 7217 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7218 ndev->max_mtu = JUMBO_LEN; 7219 else 7220 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7221 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7222 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7223 */ 7224 if ((priv->plat->maxmtu < ndev->max_mtu) && 7225 (priv->plat->maxmtu >= ndev->min_mtu)) 7226 ndev->max_mtu = priv->plat->maxmtu; 7227 else if (priv->plat->maxmtu < ndev->min_mtu) 7228 dev_warn(priv->device, 7229 "%s: warning: maxmtu having invalid value (%d)\n", 7230 __func__, priv->plat->maxmtu); 7231 7232 if (flow_ctrl) 7233 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7234 7235 /* Setup channels NAPI */ 7236 stmmac_napi_add(ndev); 7237 7238 mutex_init(&priv->lock); 7239 7240 /* If a specific clk_csr value is passed from the platform 7241 * this means that the CSR Clock Range selection cannot be 7242 * changed at run-time and it is fixed. Viceversa the driver'll try to 7243 * set the MDC clock dynamically according to the csr actual 7244 * clock input. 7245 */ 7246 if (priv->plat->clk_csr >= 0) 7247 priv->clk_csr = priv->plat->clk_csr; 7248 else 7249 stmmac_clk_csr_set(priv); 7250 7251 stmmac_check_pcs_mode(priv); 7252 7253 pm_runtime_get_noresume(device); 7254 pm_runtime_set_active(device); 7255 if (!pm_runtime_enabled(device)) 7256 pm_runtime_enable(device); 7257 7258 if (priv->hw->pcs != STMMAC_PCS_TBI && 7259 priv->hw->pcs != STMMAC_PCS_RTBI) { 7260 /* MDIO bus Registration */ 7261 ret = stmmac_mdio_register(ndev); 7262 if (ret < 0) { 7263 dev_err_probe(priv->device, ret, 7264 "%s: MDIO bus (id: %d) registration failed\n", 7265 __func__, priv->plat->bus_id); 7266 goto error_mdio_register; 7267 } 7268 } 7269 7270 if (priv->plat->speed_mode_2500) 7271 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7272 7273 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7274 ret = stmmac_xpcs_setup(priv->mii); 7275 if (ret) 7276 goto error_xpcs_setup; 7277 } 7278 7279 ret = stmmac_phy_setup(priv); 7280 if (ret) { 7281 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7282 goto error_phy_setup; 7283 } 7284 7285 ret = register_netdev(ndev); 7286 if (ret) { 7287 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7288 __func__, ret); 7289 goto error_netdev_register; 7290 } 7291 7292 #ifdef CONFIG_DEBUG_FS 7293 stmmac_init_fs(ndev); 7294 #endif 7295 7296 if (priv->plat->dump_debug_regs) 7297 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7298 7299 /* Let pm_runtime_put() disable the clocks. 7300 * If CONFIG_PM is not enabled, the clocks will stay powered. 7301 */ 7302 pm_runtime_put(device); 7303 7304 return ret; 7305 7306 error_netdev_register: 7307 phylink_destroy(priv->phylink); 7308 error_xpcs_setup: 7309 error_phy_setup: 7310 if (priv->hw->pcs != STMMAC_PCS_TBI && 7311 priv->hw->pcs != STMMAC_PCS_RTBI) 7312 stmmac_mdio_unregister(ndev); 7313 error_mdio_register: 7314 stmmac_napi_del(ndev); 7315 error_hw_init: 7316 destroy_workqueue(priv->wq); 7317 bitmap_free(priv->af_xdp_zc_qps); 7318 7319 return ret; 7320 } 7321 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7322 7323 /** 7324 * stmmac_dvr_remove 7325 * @dev: device pointer 7326 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7327 * changes the link status, releases the DMA descriptor rings. 7328 */ 7329 int stmmac_dvr_remove(struct device *dev) 7330 { 7331 struct net_device *ndev = dev_get_drvdata(dev); 7332 struct stmmac_priv *priv = netdev_priv(ndev); 7333 7334 netdev_info(priv->dev, "%s: removing driver", __func__); 7335 7336 pm_runtime_get_sync(dev); 7337 7338 stmmac_stop_all_dma(priv); 7339 stmmac_mac_set(priv, priv->ioaddr, false); 7340 netif_carrier_off(ndev); 7341 unregister_netdev(ndev); 7342 7343 /* Serdes power down needs to happen after VLAN filter 7344 * is deleted that is triggered by unregister_netdev(). 7345 */ 7346 if (priv->plat->serdes_powerdown) 7347 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7348 7349 #ifdef CONFIG_DEBUG_FS 7350 stmmac_exit_fs(ndev); 7351 #endif 7352 phylink_destroy(priv->phylink); 7353 if (priv->plat->stmmac_rst) 7354 reset_control_assert(priv->plat->stmmac_rst); 7355 reset_control_assert(priv->plat->stmmac_ahb_rst); 7356 if (priv->hw->pcs != STMMAC_PCS_TBI && 7357 priv->hw->pcs != STMMAC_PCS_RTBI) 7358 stmmac_mdio_unregister(ndev); 7359 destroy_workqueue(priv->wq); 7360 mutex_destroy(&priv->lock); 7361 bitmap_free(priv->af_xdp_zc_qps); 7362 7363 pm_runtime_disable(dev); 7364 pm_runtime_put_noidle(dev); 7365 7366 return 0; 7367 } 7368 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7369 7370 /** 7371 * stmmac_suspend - suspend callback 7372 * @dev: device pointer 7373 * Description: this is the function to suspend the device and it is called 7374 * by the platform driver to stop the network queue, release the resources, 7375 * program the PMT register (for WoL), clean and release driver resources. 7376 */ 7377 int stmmac_suspend(struct device *dev) 7378 { 7379 struct net_device *ndev = dev_get_drvdata(dev); 7380 struct stmmac_priv *priv = netdev_priv(ndev); 7381 u32 chan; 7382 7383 if (!ndev || !netif_running(ndev)) 7384 return 0; 7385 7386 mutex_lock(&priv->lock); 7387 7388 netif_device_detach(ndev); 7389 7390 stmmac_disable_all_queues(priv); 7391 7392 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7393 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7394 7395 if (priv->eee_enabled) { 7396 priv->tx_path_in_lpi_mode = false; 7397 del_timer_sync(&priv->eee_ctrl_timer); 7398 } 7399 7400 /* Stop TX/RX DMA */ 7401 stmmac_stop_all_dma(priv); 7402 7403 if (priv->plat->serdes_powerdown) 7404 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7405 7406 /* Enable Power down mode by programming the PMT regs */ 7407 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7408 stmmac_pmt(priv, priv->hw, priv->wolopts); 7409 priv->irq_wake = 1; 7410 } else { 7411 stmmac_mac_set(priv, priv->ioaddr, false); 7412 pinctrl_pm_select_sleep_state(priv->device); 7413 } 7414 7415 mutex_unlock(&priv->lock); 7416 7417 rtnl_lock(); 7418 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7419 phylink_suspend(priv->phylink, true); 7420 } else { 7421 if (device_may_wakeup(priv->device)) 7422 phylink_speed_down(priv->phylink, false); 7423 phylink_suspend(priv->phylink, false); 7424 } 7425 rtnl_unlock(); 7426 7427 if (priv->dma_cap.fpesel) { 7428 /* Disable FPE */ 7429 stmmac_fpe_configure(priv, priv->ioaddr, 7430 priv->plat->tx_queues_to_use, 7431 priv->plat->rx_queues_to_use, false); 7432 7433 stmmac_fpe_handshake(priv, false); 7434 stmmac_fpe_stop_wq(priv); 7435 } 7436 7437 priv->speed = SPEED_UNKNOWN; 7438 return 0; 7439 } 7440 EXPORT_SYMBOL_GPL(stmmac_suspend); 7441 7442 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7443 { 7444 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7445 7446 rx_q->cur_rx = 0; 7447 rx_q->dirty_rx = 0; 7448 } 7449 7450 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7451 { 7452 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7453 7454 tx_q->cur_tx = 0; 7455 tx_q->dirty_tx = 0; 7456 tx_q->mss = 0; 7457 7458 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7459 } 7460 7461 /** 7462 * stmmac_reset_queues_param - reset queue parameters 7463 * @priv: device pointer 7464 */ 7465 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7466 { 7467 u32 rx_cnt = priv->plat->rx_queues_to_use; 7468 u32 tx_cnt = priv->plat->tx_queues_to_use; 7469 u32 queue; 7470 7471 for (queue = 0; queue < rx_cnt; queue++) 7472 stmmac_reset_rx_queue(priv, queue); 7473 7474 for (queue = 0; queue < tx_cnt; queue++) 7475 stmmac_reset_tx_queue(priv, queue); 7476 } 7477 7478 /** 7479 * stmmac_resume - resume callback 7480 * @dev: device pointer 7481 * Description: when resume this function is invoked to setup the DMA and CORE 7482 * in a usable state. 7483 */ 7484 int stmmac_resume(struct device *dev) 7485 { 7486 struct net_device *ndev = dev_get_drvdata(dev); 7487 struct stmmac_priv *priv = netdev_priv(ndev); 7488 int ret; 7489 7490 if (!netif_running(ndev)) 7491 return 0; 7492 7493 /* Power Down bit, into the PM register, is cleared 7494 * automatically as soon as a magic packet or a Wake-up frame 7495 * is received. Anyway, it's better to manually clear 7496 * this bit because it can generate problems while resuming 7497 * from another devices (e.g. serial console). 7498 */ 7499 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7500 mutex_lock(&priv->lock); 7501 stmmac_pmt(priv, priv->hw, 0); 7502 mutex_unlock(&priv->lock); 7503 priv->irq_wake = 0; 7504 } else { 7505 pinctrl_pm_select_default_state(priv->device); 7506 /* reset the phy so that it's ready */ 7507 if (priv->mii) 7508 stmmac_mdio_reset(priv->mii); 7509 } 7510 7511 if (priv->plat->serdes_powerup) { 7512 ret = priv->plat->serdes_powerup(ndev, 7513 priv->plat->bsp_priv); 7514 7515 if (ret < 0) 7516 return ret; 7517 } 7518 7519 rtnl_lock(); 7520 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7521 phylink_resume(priv->phylink); 7522 } else { 7523 phylink_resume(priv->phylink); 7524 if (device_may_wakeup(priv->device)) 7525 phylink_speed_up(priv->phylink); 7526 } 7527 rtnl_unlock(); 7528 7529 rtnl_lock(); 7530 mutex_lock(&priv->lock); 7531 7532 stmmac_reset_queues_param(priv); 7533 7534 stmmac_free_tx_skbufs(priv); 7535 stmmac_clear_descriptors(priv, &priv->dma_conf); 7536 7537 stmmac_hw_setup(ndev, false); 7538 stmmac_init_coalesce(priv); 7539 stmmac_set_rx_mode(ndev); 7540 7541 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7542 7543 stmmac_enable_all_queues(priv); 7544 stmmac_enable_all_dma_irq(priv); 7545 7546 mutex_unlock(&priv->lock); 7547 rtnl_unlock(); 7548 7549 netif_device_attach(ndev); 7550 7551 return 0; 7552 } 7553 EXPORT_SYMBOL_GPL(stmmac_resume); 7554 7555 #ifndef MODULE 7556 static int __init stmmac_cmdline_opt(char *str) 7557 { 7558 char *opt; 7559 7560 if (!str || !*str) 7561 return 1; 7562 while ((opt = strsep(&str, ",")) != NULL) { 7563 if (!strncmp(opt, "debug:", 6)) { 7564 if (kstrtoint(opt + 6, 0, &debug)) 7565 goto err; 7566 } else if (!strncmp(opt, "phyaddr:", 8)) { 7567 if (kstrtoint(opt + 8, 0, &phyaddr)) 7568 goto err; 7569 } else if (!strncmp(opt, "buf_sz:", 7)) { 7570 if (kstrtoint(opt + 7, 0, &buf_sz)) 7571 goto err; 7572 } else if (!strncmp(opt, "tc:", 3)) { 7573 if (kstrtoint(opt + 3, 0, &tc)) 7574 goto err; 7575 } else if (!strncmp(opt, "watchdog:", 9)) { 7576 if (kstrtoint(opt + 9, 0, &watchdog)) 7577 goto err; 7578 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7579 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7580 goto err; 7581 } else if (!strncmp(opt, "pause:", 6)) { 7582 if (kstrtoint(opt + 6, 0, &pause)) 7583 goto err; 7584 } else if (!strncmp(opt, "eee_timer:", 10)) { 7585 if (kstrtoint(opt + 10, 0, &eee_timer)) 7586 goto err; 7587 } else if (!strncmp(opt, "chain_mode:", 11)) { 7588 if (kstrtoint(opt + 11, 0, &chain_mode)) 7589 goto err; 7590 } 7591 } 7592 return 1; 7593 7594 err: 7595 pr_err("%s: ERROR broken module parameter conversion", __func__); 7596 return 1; 7597 } 7598 7599 __setup("stmmaceth=", stmmac_cmdline_opt); 7600 #endif /* MODULE */ 7601 7602 static int __init stmmac_init(void) 7603 { 7604 #ifdef CONFIG_DEBUG_FS 7605 /* Create debugfs main directory if it doesn't exist yet */ 7606 if (!stmmac_fs_dir) 7607 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7608 register_netdevice_notifier(&stmmac_notifier); 7609 #endif 7610 7611 return 0; 7612 } 7613 7614 static void __exit stmmac_exit(void) 7615 { 7616 #ifdef CONFIG_DEBUG_FS 7617 unregister_netdevice_notifier(&stmmac_notifier); 7618 debugfs_remove_recursive(stmmac_fs_dir); 7619 #endif 7620 } 7621 7622 module_init(stmmac_init) 7623 module_exit(stmmac_exit) 7624 7625 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7626 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7627 MODULE_LICENSE("GPL"); 7628