1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 67 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 180 { 181 if (!test_bit(STMMAC_DOWN, &priv->state) && 182 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 183 queue_work(priv->wq, &priv->service_task); 184 } 185 186 static void stmmac_global_err(struct stmmac_priv *priv) 187 { 188 netif_carrier_off(priv->dev); 189 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 190 stmmac_service_event_schedule(priv); 191 } 192 193 /** 194 * stmmac_clk_csr_set - dynamically set the MDC clock 195 * @priv: driver private structure 196 * Description: this is to dynamically set the MDC clock according to the csr 197 * clock input. 198 * Note: 199 * If a specific clk_csr value is passed from the platform 200 * this means that the CSR Clock Range selection cannot be 201 * changed at run-time and it is fixed (as reported in the driver 202 * documentation). Viceversa the driver will try to set the MDC 203 * clock dynamically according to the actual clock input. 204 */ 205 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 206 { 207 u32 clk_rate; 208 209 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 210 211 /* Platform provided default clk_csr would be assumed valid 212 * for all other cases except for the below mentioned ones. 213 * For values higher than the IEEE 802.3 specified frequency 214 * we can not estimate the proper divider as it is not known 215 * the frequency of clk_csr_i. So we do not change the default 216 * divider. 217 */ 218 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 219 if (clk_rate < CSR_F_35M) 220 priv->clk_csr = STMMAC_CSR_20_35M; 221 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 222 priv->clk_csr = STMMAC_CSR_35_60M; 223 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 224 priv->clk_csr = STMMAC_CSR_60_100M; 225 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 226 priv->clk_csr = STMMAC_CSR_100_150M; 227 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 228 priv->clk_csr = STMMAC_CSR_150_250M; 229 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 230 priv->clk_csr = STMMAC_CSR_250_300M; 231 } 232 233 if (priv->plat->has_sun8i) { 234 if (clk_rate > 160000000) 235 priv->clk_csr = 0x03; 236 else if (clk_rate > 80000000) 237 priv->clk_csr = 0x02; 238 else if (clk_rate > 40000000) 239 priv->clk_csr = 0x01; 240 else 241 priv->clk_csr = 0; 242 } 243 244 if (priv->plat->has_xgmac) { 245 if (clk_rate > 400000000) 246 priv->clk_csr = 0x5; 247 else if (clk_rate > 350000000) 248 priv->clk_csr = 0x4; 249 else if (clk_rate > 300000000) 250 priv->clk_csr = 0x3; 251 else if (clk_rate > 250000000) 252 priv->clk_csr = 0x2; 253 else if (clk_rate > 150000000) 254 priv->clk_csr = 0x1; 255 else 256 priv->clk_csr = 0x0; 257 } 258 } 259 260 static void print_pkt(unsigned char *buf, int len) 261 { 262 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 263 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 264 } 265 266 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 267 { 268 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 269 u32 avail; 270 271 if (tx_q->dirty_tx > tx_q->cur_tx) 272 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 273 else 274 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 275 276 return avail; 277 } 278 279 /** 280 * stmmac_rx_dirty - Get RX queue dirty 281 * @priv: driver private structure 282 * @queue: RX queue index 283 */ 284 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 285 { 286 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 287 u32 dirty; 288 289 if (rx_q->dirty_rx <= rx_q->cur_rx) 290 dirty = rx_q->cur_rx - rx_q->dirty_rx; 291 else 292 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 293 294 return dirty; 295 } 296 297 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 298 { 299 int tx_lpi_timer; 300 301 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 302 priv->eee_sw_timer_en = en ? 0 : 1; 303 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 304 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 305 } 306 307 /** 308 * stmmac_enable_eee_mode - check and enter in LPI mode 309 * @priv: driver private structure 310 * Description: this function is to verify and enter in LPI mode in case of 311 * EEE. 312 */ 313 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 314 { 315 u32 tx_cnt = priv->plat->tx_queues_to_use; 316 u32 queue; 317 318 /* check if all TX queues have the work finished */ 319 for (queue = 0; queue < tx_cnt; queue++) { 320 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 321 322 if (tx_q->dirty_tx != tx_q->cur_tx) 323 return; /* still unfinished work */ 324 } 325 326 /* Check and enter in LPI mode */ 327 if (!priv->tx_path_in_lpi_mode) 328 stmmac_set_eee_mode(priv, priv->hw, 329 priv->plat->en_tx_lpi_clockgating); 330 } 331 332 /** 333 * stmmac_disable_eee_mode - disable and exit from LPI mode 334 * @priv: driver private structure 335 * Description: this function is to exit and disable EEE in case of 336 * LPI state is true. This is called by the xmit. 337 */ 338 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 339 { 340 if (!priv->eee_sw_timer_en) { 341 stmmac_lpi_entry_timer_config(priv, 0); 342 return; 343 } 344 345 stmmac_reset_eee_mode(priv, priv->hw); 346 del_timer_sync(&priv->eee_ctrl_timer); 347 priv->tx_path_in_lpi_mode = false; 348 } 349 350 /** 351 * stmmac_eee_ctrl_timer - EEE TX SW timer. 352 * @t: timer_list struct containing private info 353 * Description: 354 * if there is no data transfer and if we are not in LPI state, 355 * then MAC Transmitter can be moved to LPI state. 356 */ 357 static void stmmac_eee_ctrl_timer(struct timer_list *t) 358 { 359 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 360 361 stmmac_enable_eee_mode(priv); 362 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 363 } 364 365 /** 366 * stmmac_eee_init - init EEE 367 * @priv: driver private structure 368 * Description: 369 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 370 * can also manage EEE, this function enable the LPI state and start related 371 * timer. 372 */ 373 bool stmmac_eee_init(struct stmmac_priv *priv) 374 { 375 int eee_tw_timer = priv->eee_tw_timer; 376 377 /* Using PCS we cannot dial with the phy registers at this stage 378 * so we do not support extra feature like EEE. 379 */ 380 if (priv->hw->pcs == STMMAC_PCS_TBI || 381 priv->hw->pcs == STMMAC_PCS_RTBI) 382 return false; 383 384 /* Check if MAC core supports the EEE feature. */ 385 if (!priv->dma_cap.eee) 386 return false; 387 388 mutex_lock(&priv->lock); 389 390 /* Check if it needs to be deactivated */ 391 if (!priv->eee_active) { 392 if (priv->eee_enabled) { 393 netdev_dbg(priv->dev, "disable EEE\n"); 394 stmmac_lpi_entry_timer_config(priv, 0); 395 del_timer_sync(&priv->eee_ctrl_timer); 396 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 397 } 398 mutex_unlock(&priv->lock); 399 return false; 400 } 401 402 if (priv->eee_active && !priv->eee_enabled) { 403 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 404 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 405 eee_tw_timer); 406 } 407 408 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 409 del_timer_sync(&priv->eee_ctrl_timer); 410 priv->tx_path_in_lpi_mode = false; 411 stmmac_lpi_entry_timer_config(priv, 1); 412 } else { 413 stmmac_lpi_entry_timer_config(priv, 0); 414 mod_timer(&priv->eee_ctrl_timer, 415 STMMAC_LPI_T(priv->tx_lpi_timer)); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 if (priv->synopsys_id != DWMAC_CORE_5_10) 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 * as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 clk_disable_unprepare(priv->plat->clk_ptp_ref); 791 stmmac_ptp_unregister(priv); 792 } 793 794 /** 795 * stmmac_mac_flow_ctrl - Configure flow control in all queues 796 * @priv: driver private structure 797 * @duplex: duplex passed to the next function 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 if (!max_speed || (max_speed >= 25000)) { 853 phylink_set(mac_supported, 25000baseCR_Full); 854 phylink_set(mac_supported, 25000baseKR_Full); 855 phylink_set(mac_supported, 25000baseSR_Full); 856 } 857 if (!max_speed || (max_speed >= 40000)) { 858 phylink_set(mac_supported, 40000baseKR4_Full); 859 phylink_set(mac_supported, 40000baseCR4_Full); 860 phylink_set(mac_supported, 40000baseSR4_Full); 861 phylink_set(mac_supported, 40000baseLR4_Full); 862 } 863 if (!max_speed || (max_speed >= 50000)) { 864 phylink_set(mac_supported, 50000baseCR2_Full); 865 phylink_set(mac_supported, 50000baseKR2_Full); 866 phylink_set(mac_supported, 50000baseSR2_Full); 867 phylink_set(mac_supported, 50000baseKR_Full); 868 phylink_set(mac_supported, 50000baseSR_Full); 869 phylink_set(mac_supported, 50000baseCR_Full); 870 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 871 phylink_set(mac_supported, 50000baseDR_Full); 872 } 873 if (!max_speed || (max_speed >= 100000)) { 874 phylink_set(mac_supported, 100000baseKR4_Full); 875 phylink_set(mac_supported, 100000baseSR4_Full); 876 phylink_set(mac_supported, 100000baseCR4_Full); 877 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 878 phylink_set(mac_supported, 100000baseKR2_Full); 879 phylink_set(mac_supported, 100000baseSR2_Full); 880 phylink_set(mac_supported, 100000baseCR2_Full); 881 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 882 phylink_set(mac_supported, 100000baseDR2_Full); 883 } 884 } 885 886 /* Half-Duplex can only work with single queue */ 887 if (tx_cnt > 1) { 888 phylink_set(mask, 10baseT_Half); 889 phylink_set(mask, 100baseT_Half); 890 phylink_set(mask, 1000baseT_Half); 891 } 892 893 linkmode_and(supported, supported, mac_supported); 894 linkmode_andnot(supported, supported, mask); 895 896 linkmode_and(state->advertising, state->advertising, mac_supported); 897 linkmode_andnot(state->advertising, state->advertising, mask); 898 899 /* If PCS is supported, check which modes it supports. */ 900 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 901 } 902 903 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 904 struct phylink_link_state *state) 905 { 906 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 907 908 state->link = 0; 909 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 910 } 911 912 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 913 const struct phylink_link_state *state) 914 { 915 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 916 917 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 918 } 919 920 static void stmmac_mac_an_restart(struct phylink_config *config) 921 { 922 /* Not Supported */ 923 } 924 925 static void stmmac_mac_link_down(struct phylink_config *config, 926 unsigned int mode, phy_interface_t interface) 927 { 928 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 929 930 stmmac_mac_set(priv, priv->ioaddr, false); 931 priv->eee_active = false; 932 priv->tx_lpi_enabled = false; 933 stmmac_eee_init(priv); 934 stmmac_set_eee_pls(priv, priv->hw, false); 935 } 936 937 static void stmmac_mac_link_up(struct phylink_config *config, 938 struct phy_device *phy, 939 unsigned int mode, phy_interface_t interface, 940 int speed, int duplex, 941 bool tx_pause, bool rx_pause) 942 { 943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 944 u32 ctrl; 945 946 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 947 948 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 949 ctrl &= ~priv->hw->link.speed_mask; 950 951 if (interface == PHY_INTERFACE_MODE_USXGMII) { 952 switch (speed) { 953 case SPEED_10000: 954 ctrl |= priv->hw->link.xgmii.speed10000; 955 break; 956 case SPEED_5000: 957 ctrl |= priv->hw->link.xgmii.speed5000; 958 break; 959 case SPEED_2500: 960 ctrl |= priv->hw->link.xgmii.speed2500; 961 break; 962 default: 963 return; 964 } 965 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 966 switch (speed) { 967 case SPEED_100000: 968 ctrl |= priv->hw->link.xlgmii.speed100000; 969 break; 970 case SPEED_50000: 971 ctrl |= priv->hw->link.xlgmii.speed50000; 972 break; 973 case SPEED_40000: 974 ctrl |= priv->hw->link.xlgmii.speed40000; 975 break; 976 case SPEED_25000: 977 ctrl |= priv->hw->link.xlgmii.speed25000; 978 break; 979 case SPEED_10000: 980 ctrl |= priv->hw->link.xgmii.speed10000; 981 break; 982 case SPEED_2500: 983 ctrl |= priv->hw->link.speed2500; 984 break; 985 case SPEED_1000: 986 ctrl |= priv->hw->link.speed1000; 987 break; 988 default: 989 return; 990 } 991 } else { 992 switch (speed) { 993 case SPEED_2500: 994 ctrl |= priv->hw->link.speed2500; 995 break; 996 case SPEED_1000: 997 ctrl |= priv->hw->link.speed1000; 998 break; 999 case SPEED_100: 1000 ctrl |= priv->hw->link.speed100; 1001 break; 1002 case SPEED_10: 1003 ctrl |= priv->hw->link.speed10; 1004 break; 1005 default: 1006 return; 1007 } 1008 } 1009 1010 priv->speed = speed; 1011 1012 if (priv->plat->fix_mac_speed) 1013 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1014 1015 if (!duplex) 1016 ctrl &= ~priv->hw->link.duplex; 1017 else 1018 ctrl |= priv->hw->link.duplex; 1019 1020 /* Flow Control operation */ 1021 if (tx_pause && rx_pause) 1022 stmmac_mac_flow_ctrl(priv, duplex); 1023 1024 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1025 1026 stmmac_mac_set(priv, priv->ioaddr, true); 1027 if (phy && priv->dma_cap.eee) { 1028 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1029 priv->eee_enabled = stmmac_eee_init(priv); 1030 priv->tx_lpi_enabled = priv->eee_enabled; 1031 stmmac_set_eee_pls(priv, priv->hw, true); 1032 } 1033 } 1034 1035 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1036 .validate = stmmac_validate, 1037 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1038 .mac_config = stmmac_mac_config, 1039 .mac_an_restart = stmmac_mac_an_restart, 1040 .mac_link_down = stmmac_mac_link_down, 1041 .mac_link_up = stmmac_mac_link_up, 1042 }; 1043 1044 /** 1045 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1046 * @priv: driver private structure 1047 * Description: this is to verify if the HW supports the PCS. 1048 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1049 * configured for the TBI, RTBI, or SGMII PHY interface. 1050 */ 1051 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1052 { 1053 int interface = priv->plat->interface; 1054 1055 if (priv->dma_cap.pcs) { 1056 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1057 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1058 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1059 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1060 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1061 priv->hw->pcs = STMMAC_PCS_RGMII; 1062 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1063 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1064 priv->hw->pcs = STMMAC_PCS_SGMII; 1065 } 1066 } 1067 } 1068 1069 /** 1070 * stmmac_init_phy - PHY initialization 1071 * @dev: net device structure 1072 * Description: it initializes the driver's PHY state, and attaches the PHY 1073 * to the mac driver. 1074 * Return value: 1075 * 0 on success 1076 */ 1077 static int stmmac_init_phy(struct net_device *dev) 1078 { 1079 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1080 struct stmmac_priv *priv = netdev_priv(dev); 1081 struct device_node *node; 1082 int ret; 1083 1084 node = priv->plat->phylink_node; 1085 1086 if (node) 1087 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1088 1089 /* Some DT bindings do not set-up the PHY handle. Let's try to 1090 * manually parse it 1091 */ 1092 if (!node || ret) { 1093 int addr = priv->plat->phy_addr; 1094 struct phy_device *phydev; 1095 1096 phydev = mdiobus_get_phy(priv->mii, addr); 1097 if (!phydev) { 1098 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1099 return -ENODEV; 1100 } 1101 1102 ret = phylink_connect_phy(priv->phylink, phydev); 1103 } 1104 1105 phylink_ethtool_get_wol(priv->phylink, &wol); 1106 device_set_wakeup_capable(priv->device, !!wol.supported); 1107 1108 return ret; 1109 } 1110 1111 static int stmmac_phy_setup(struct stmmac_priv *priv) 1112 { 1113 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1114 int mode = priv->plat->phy_interface; 1115 struct phylink *phylink; 1116 1117 priv->phylink_config.dev = &priv->dev->dev; 1118 priv->phylink_config.type = PHYLINK_NETDEV; 1119 priv->phylink_config.pcs_poll = true; 1120 1121 if (!fwnode) 1122 fwnode = dev_fwnode(priv->device); 1123 1124 phylink = phylink_create(&priv->phylink_config, fwnode, 1125 mode, &stmmac_phylink_mac_ops); 1126 if (IS_ERR(phylink)) 1127 return PTR_ERR(phylink); 1128 1129 priv->phylink = phylink; 1130 return 0; 1131 } 1132 1133 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1134 { 1135 u32 rx_cnt = priv->plat->rx_queues_to_use; 1136 unsigned int desc_size; 1137 void *head_rx; 1138 u32 queue; 1139 1140 /* Display RX rings */ 1141 for (queue = 0; queue < rx_cnt; queue++) { 1142 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1143 1144 pr_info("\tRX Queue %u rings\n", queue); 1145 1146 if (priv->extend_desc) { 1147 head_rx = (void *)rx_q->dma_erx; 1148 desc_size = sizeof(struct dma_extended_desc); 1149 } else { 1150 head_rx = (void *)rx_q->dma_rx; 1151 desc_size = sizeof(struct dma_desc); 1152 } 1153 1154 /* Display RX ring */ 1155 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1156 rx_q->dma_rx_phy, desc_size); 1157 } 1158 } 1159 1160 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1161 { 1162 u32 tx_cnt = priv->plat->tx_queues_to_use; 1163 unsigned int desc_size; 1164 void *head_tx; 1165 u32 queue; 1166 1167 /* Display TX rings */ 1168 for (queue = 0; queue < tx_cnt; queue++) { 1169 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1170 1171 pr_info("\tTX Queue %d rings\n", queue); 1172 1173 if (priv->extend_desc) { 1174 head_tx = (void *)tx_q->dma_etx; 1175 desc_size = sizeof(struct dma_extended_desc); 1176 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1177 head_tx = (void *)tx_q->dma_entx; 1178 desc_size = sizeof(struct dma_edesc); 1179 } else { 1180 head_tx = (void *)tx_q->dma_tx; 1181 desc_size = sizeof(struct dma_desc); 1182 } 1183 1184 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1185 tx_q->dma_tx_phy, desc_size); 1186 } 1187 } 1188 1189 static void stmmac_display_rings(struct stmmac_priv *priv) 1190 { 1191 /* Display RX ring */ 1192 stmmac_display_rx_rings(priv); 1193 1194 /* Display TX ring */ 1195 stmmac_display_tx_rings(priv); 1196 } 1197 1198 static int stmmac_set_bfsize(int mtu, int bufsize) 1199 { 1200 int ret = bufsize; 1201 1202 if (mtu >= BUF_SIZE_8KiB) 1203 ret = BUF_SIZE_16KiB; 1204 else if (mtu >= BUF_SIZE_4KiB) 1205 ret = BUF_SIZE_8KiB; 1206 else if (mtu >= BUF_SIZE_2KiB) 1207 ret = BUF_SIZE_4KiB; 1208 else if (mtu > DEFAULT_BUFSIZE) 1209 ret = BUF_SIZE_2KiB; 1210 else 1211 ret = DEFAULT_BUFSIZE; 1212 1213 return ret; 1214 } 1215 1216 /** 1217 * stmmac_clear_rx_descriptors - clear RX descriptors 1218 * @priv: driver private structure 1219 * @queue: RX queue index 1220 * Description: this function is called to clear the RX descriptors 1221 * in case of both basic and extended descriptors are used. 1222 */ 1223 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1224 { 1225 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1226 int i; 1227 1228 /* Clear the RX descriptors */ 1229 for (i = 0; i < priv->dma_rx_size; i++) 1230 if (priv->extend_desc) 1231 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1232 priv->use_riwt, priv->mode, 1233 (i == priv->dma_rx_size - 1), 1234 priv->dma_buf_sz); 1235 else 1236 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1237 priv->use_riwt, priv->mode, 1238 (i == priv->dma_rx_size - 1), 1239 priv->dma_buf_sz); 1240 } 1241 1242 /** 1243 * stmmac_clear_tx_descriptors - clear tx descriptors 1244 * @priv: driver private structure 1245 * @queue: TX queue index. 1246 * Description: this function is called to clear the TX descriptors 1247 * in case of both basic and extended descriptors are used. 1248 */ 1249 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1250 { 1251 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1252 int i; 1253 1254 /* Clear the TX descriptors */ 1255 for (i = 0; i < priv->dma_tx_size; i++) { 1256 int last = (i == (priv->dma_tx_size - 1)); 1257 struct dma_desc *p; 1258 1259 if (priv->extend_desc) 1260 p = &tx_q->dma_etx[i].basic; 1261 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1262 p = &tx_q->dma_entx[i].basic; 1263 else 1264 p = &tx_q->dma_tx[i]; 1265 1266 stmmac_init_tx_desc(priv, p, priv->mode, last); 1267 } 1268 } 1269 1270 /** 1271 * stmmac_clear_descriptors - clear descriptors 1272 * @priv: driver private structure 1273 * Description: this function is called to clear the TX and RX descriptors 1274 * in case of both basic and extended descriptors are used. 1275 */ 1276 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1277 { 1278 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1279 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1280 u32 queue; 1281 1282 /* Clear the RX descriptors */ 1283 for (queue = 0; queue < rx_queue_cnt; queue++) 1284 stmmac_clear_rx_descriptors(priv, queue); 1285 1286 /* Clear the TX descriptors */ 1287 for (queue = 0; queue < tx_queue_cnt; queue++) 1288 stmmac_clear_tx_descriptors(priv, queue); 1289 } 1290 1291 /** 1292 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1293 * @priv: driver private structure 1294 * @p: descriptor pointer 1295 * @i: descriptor index 1296 * @flags: gfp flag 1297 * @queue: RX queue index 1298 * Description: this function is called to allocate a receive buffer, perform 1299 * the DMA mapping and init the descriptor. 1300 */ 1301 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1302 int i, gfp_t flags, u32 queue) 1303 { 1304 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1305 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1306 1307 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1308 if (!buf->page) 1309 return -ENOMEM; 1310 1311 if (priv->sph) { 1312 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1313 if (!buf->sec_page) 1314 return -ENOMEM; 1315 1316 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1317 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1318 } else { 1319 buf->sec_page = NULL; 1320 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1321 } 1322 1323 buf->addr = page_pool_get_dma_addr(buf->page); 1324 stmmac_set_desc_addr(priv, p, buf->addr); 1325 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1326 stmmac_init_desc3(priv, p); 1327 1328 return 0; 1329 } 1330 1331 /** 1332 * stmmac_free_rx_buffer - free RX dma buffers 1333 * @priv: private structure 1334 * @queue: RX queue index 1335 * @i: buffer index. 1336 */ 1337 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1338 { 1339 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1340 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1341 1342 if (buf->page) 1343 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1344 buf->page = NULL; 1345 1346 if (buf->sec_page) 1347 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1348 buf->sec_page = NULL; 1349 } 1350 1351 /** 1352 * stmmac_free_tx_buffer - free RX dma buffers 1353 * @priv: private structure 1354 * @queue: RX queue index 1355 * @i: buffer index. 1356 */ 1357 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1358 { 1359 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1360 1361 if (tx_q->tx_skbuff_dma[i].buf) { 1362 if (tx_q->tx_skbuff_dma[i].map_as_page) 1363 dma_unmap_page(priv->device, 1364 tx_q->tx_skbuff_dma[i].buf, 1365 tx_q->tx_skbuff_dma[i].len, 1366 DMA_TO_DEVICE); 1367 else 1368 dma_unmap_single(priv->device, 1369 tx_q->tx_skbuff_dma[i].buf, 1370 tx_q->tx_skbuff_dma[i].len, 1371 DMA_TO_DEVICE); 1372 } 1373 1374 if (tx_q->tx_skbuff[i]) { 1375 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1376 tx_q->tx_skbuff[i] = NULL; 1377 tx_q->tx_skbuff_dma[i].buf = 0; 1378 tx_q->tx_skbuff_dma[i].map_as_page = false; 1379 } 1380 } 1381 1382 /** 1383 * stmmac_reinit_rx_buffers - reinit the RX descriptor buffer. 1384 * @priv: driver private structure 1385 * Description: this function is called to re-allocate a receive buffer, perform 1386 * the DMA mapping and init the descriptor. 1387 */ 1388 static void stmmac_reinit_rx_buffers(struct stmmac_priv *priv) 1389 { 1390 u32 rx_count = priv->plat->rx_queues_to_use; 1391 u32 queue; 1392 int i; 1393 1394 for (queue = 0; queue < rx_count; queue++) { 1395 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1396 1397 for (i = 0; i < priv->dma_rx_size; i++) { 1398 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1399 1400 if (buf->page) { 1401 page_pool_recycle_direct(rx_q->page_pool, buf->page); 1402 buf->page = NULL; 1403 } 1404 1405 if (priv->sph && buf->sec_page) { 1406 page_pool_recycle_direct(rx_q->page_pool, buf->sec_page); 1407 buf->sec_page = NULL; 1408 } 1409 } 1410 } 1411 1412 for (queue = 0; queue < rx_count; queue++) { 1413 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1414 1415 for (i = 0; i < priv->dma_rx_size; i++) { 1416 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1417 struct dma_desc *p; 1418 1419 if (priv->extend_desc) 1420 p = &((rx_q->dma_erx + i)->basic); 1421 else 1422 p = rx_q->dma_rx + i; 1423 1424 if (!buf->page) { 1425 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1426 if (!buf->page) 1427 goto err_reinit_rx_buffers; 1428 1429 buf->addr = page_pool_get_dma_addr(buf->page); 1430 } 1431 1432 if (priv->sph && !buf->sec_page) { 1433 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1434 if (!buf->sec_page) 1435 goto err_reinit_rx_buffers; 1436 1437 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1438 } 1439 1440 stmmac_set_desc_addr(priv, p, buf->addr); 1441 if (priv->sph) 1442 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1443 else 1444 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1445 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1446 stmmac_init_desc3(priv, p); 1447 } 1448 } 1449 1450 return; 1451 1452 err_reinit_rx_buffers: 1453 do { 1454 while (--i >= 0) 1455 stmmac_free_rx_buffer(priv, queue, i); 1456 1457 if (queue == 0) 1458 break; 1459 1460 i = priv->dma_rx_size; 1461 } while (queue-- > 0); 1462 } 1463 1464 /** 1465 * init_dma_rx_desc_rings - init the RX descriptor rings 1466 * @dev: net device structure 1467 * @flags: gfp flag. 1468 * Description: this function initializes the DMA RX descriptors 1469 * and allocates the socket buffers. It supports the chained and ring 1470 * modes. 1471 */ 1472 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1473 { 1474 struct stmmac_priv *priv = netdev_priv(dev); 1475 u32 rx_count = priv->plat->rx_queues_to_use; 1476 int ret = -ENOMEM; 1477 int queue; 1478 int i; 1479 1480 /* RX INITIALIZATION */ 1481 netif_dbg(priv, probe, priv->dev, 1482 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1483 1484 for (queue = 0; queue < rx_count; queue++) { 1485 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1486 1487 netif_dbg(priv, probe, priv->dev, 1488 "(%s) dma_rx_phy=0x%08x\n", __func__, 1489 (u32)rx_q->dma_rx_phy); 1490 1491 stmmac_clear_rx_descriptors(priv, queue); 1492 1493 for (i = 0; i < priv->dma_rx_size; i++) { 1494 struct dma_desc *p; 1495 1496 if (priv->extend_desc) 1497 p = &((rx_q->dma_erx + i)->basic); 1498 else 1499 p = rx_q->dma_rx + i; 1500 1501 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1502 queue); 1503 if (ret) 1504 goto err_init_rx_buffers; 1505 } 1506 1507 rx_q->cur_rx = 0; 1508 rx_q->dirty_rx = (unsigned int)(i - priv->dma_rx_size); 1509 1510 /* Setup the chained descriptor addresses */ 1511 if (priv->mode == STMMAC_CHAIN_MODE) { 1512 if (priv->extend_desc) 1513 stmmac_mode_init(priv, rx_q->dma_erx, 1514 rx_q->dma_rx_phy, 1515 priv->dma_rx_size, 1); 1516 else 1517 stmmac_mode_init(priv, rx_q->dma_rx, 1518 rx_q->dma_rx_phy, 1519 priv->dma_rx_size, 0); 1520 } 1521 } 1522 1523 return 0; 1524 1525 err_init_rx_buffers: 1526 while (queue >= 0) { 1527 while (--i >= 0) 1528 stmmac_free_rx_buffer(priv, queue, i); 1529 1530 if (queue == 0) 1531 break; 1532 1533 i = priv->dma_rx_size; 1534 queue--; 1535 } 1536 1537 return ret; 1538 } 1539 1540 /** 1541 * init_dma_tx_desc_rings - init the TX descriptor rings 1542 * @dev: net device structure. 1543 * Description: this function initializes the DMA TX descriptors 1544 * and allocates the socket buffers. It supports the chained and ring 1545 * modes. 1546 */ 1547 static int init_dma_tx_desc_rings(struct net_device *dev) 1548 { 1549 struct stmmac_priv *priv = netdev_priv(dev); 1550 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1551 u32 queue; 1552 int i; 1553 1554 for (queue = 0; queue < tx_queue_cnt; queue++) { 1555 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1556 1557 netif_dbg(priv, probe, priv->dev, 1558 "(%s) dma_tx_phy=0x%08x\n", __func__, 1559 (u32)tx_q->dma_tx_phy); 1560 1561 /* Setup the chained descriptor addresses */ 1562 if (priv->mode == STMMAC_CHAIN_MODE) { 1563 if (priv->extend_desc) 1564 stmmac_mode_init(priv, tx_q->dma_etx, 1565 tx_q->dma_tx_phy, 1566 priv->dma_tx_size, 1); 1567 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1568 stmmac_mode_init(priv, tx_q->dma_tx, 1569 tx_q->dma_tx_phy, 1570 priv->dma_tx_size, 0); 1571 } 1572 1573 for (i = 0; i < priv->dma_tx_size; i++) { 1574 struct dma_desc *p; 1575 if (priv->extend_desc) 1576 p = &((tx_q->dma_etx + i)->basic); 1577 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1578 p = &((tx_q->dma_entx + i)->basic); 1579 else 1580 p = tx_q->dma_tx + i; 1581 1582 stmmac_clear_desc(priv, p); 1583 1584 tx_q->tx_skbuff_dma[i].buf = 0; 1585 tx_q->tx_skbuff_dma[i].map_as_page = false; 1586 tx_q->tx_skbuff_dma[i].len = 0; 1587 tx_q->tx_skbuff_dma[i].last_segment = false; 1588 tx_q->tx_skbuff[i] = NULL; 1589 } 1590 1591 tx_q->dirty_tx = 0; 1592 tx_q->cur_tx = 0; 1593 tx_q->mss = 0; 1594 1595 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1596 } 1597 1598 return 0; 1599 } 1600 1601 /** 1602 * init_dma_desc_rings - init the RX/TX descriptor rings 1603 * @dev: net device structure 1604 * @flags: gfp flag. 1605 * Description: this function initializes the DMA RX/TX descriptors 1606 * and allocates the socket buffers. It supports the chained and ring 1607 * modes. 1608 */ 1609 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1610 { 1611 struct stmmac_priv *priv = netdev_priv(dev); 1612 int ret; 1613 1614 ret = init_dma_rx_desc_rings(dev, flags); 1615 if (ret) 1616 return ret; 1617 1618 ret = init_dma_tx_desc_rings(dev); 1619 1620 stmmac_clear_descriptors(priv); 1621 1622 if (netif_msg_hw(priv)) 1623 stmmac_display_rings(priv); 1624 1625 return ret; 1626 } 1627 1628 /** 1629 * dma_free_rx_skbufs - free RX dma buffers 1630 * @priv: private structure 1631 * @queue: RX queue index 1632 */ 1633 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1634 { 1635 int i; 1636 1637 for (i = 0; i < priv->dma_rx_size; i++) 1638 stmmac_free_rx_buffer(priv, queue, i); 1639 } 1640 1641 /** 1642 * dma_free_tx_skbufs - free TX dma buffers 1643 * @priv: private structure 1644 * @queue: TX queue index 1645 */ 1646 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1647 { 1648 int i; 1649 1650 for (i = 0; i < priv->dma_tx_size; i++) 1651 stmmac_free_tx_buffer(priv, queue, i); 1652 } 1653 1654 /** 1655 * stmmac_free_tx_skbufs - free TX skb buffers 1656 * @priv: private structure 1657 */ 1658 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1659 { 1660 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1661 u32 queue; 1662 1663 for (queue = 0; queue < tx_queue_cnt; queue++) 1664 dma_free_tx_skbufs(priv, queue); 1665 } 1666 1667 /** 1668 * free_dma_rx_desc_resources - free RX dma desc resources 1669 * @priv: private structure 1670 */ 1671 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1672 { 1673 u32 rx_count = priv->plat->rx_queues_to_use; 1674 u32 queue; 1675 1676 /* Free RX queue resources */ 1677 for (queue = 0; queue < rx_count; queue++) { 1678 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1679 1680 /* Release the DMA RX socket buffers */ 1681 dma_free_rx_skbufs(priv, queue); 1682 1683 /* Free DMA regions of consistent memory previously allocated */ 1684 if (!priv->extend_desc) 1685 dma_free_coherent(priv->device, priv->dma_rx_size * 1686 sizeof(struct dma_desc), 1687 rx_q->dma_rx, rx_q->dma_rx_phy); 1688 else 1689 dma_free_coherent(priv->device, priv->dma_rx_size * 1690 sizeof(struct dma_extended_desc), 1691 rx_q->dma_erx, rx_q->dma_rx_phy); 1692 1693 kfree(rx_q->buf_pool); 1694 if (rx_q->page_pool) 1695 page_pool_destroy(rx_q->page_pool); 1696 } 1697 } 1698 1699 /** 1700 * free_dma_tx_desc_resources - free TX dma desc resources 1701 * @priv: private structure 1702 */ 1703 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1704 { 1705 u32 tx_count = priv->plat->tx_queues_to_use; 1706 u32 queue; 1707 1708 /* Free TX queue resources */ 1709 for (queue = 0; queue < tx_count; queue++) { 1710 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1711 size_t size; 1712 void *addr; 1713 1714 /* Release the DMA TX socket buffers */ 1715 dma_free_tx_skbufs(priv, queue); 1716 1717 if (priv->extend_desc) { 1718 size = sizeof(struct dma_extended_desc); 1719 addr = tx_q->dma_etx; 1720 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1721 size = sizeof(struct dma_edesc); 1722 addr = tx_q->dma_entx; 1723 } else { 1724 size = sizeof(struct dma_desc); 1725 addr = tx_q->dma_tx; 1726 } 1727 1728 size *= priv->dma_tx_size; 1729 1730 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1731 1732 kfree(tx_q->tx_skbuff_dma); 1733 kfree(tx_q->tx_skbuff); 1734 } 1735 } 1736 1737 /** 1738 * alloc_dma_rx_desc_resources - alloc RX resources. 1739 * @priv: private structure 1740 * Description: according to which descriptor can be used (extend or basic) 1741 * this function allocates the resources for TX and RX paths. In case of 1742 * reception, for example, it pre-allocated the RX socket buffer in order to 1743 * allow zero-copy mechanism. 1744 */ 1745 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1746 { 1747 u32 rx_count = priv->plat->rx_queues_to_use; 1748 int ret = -ENOMEM; 1749 u32 queue; 1750 1751 /* RX queues buffers and DMA */ 1752 for (queue = 0; queue < rx_count; queue++) { 1753 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1754 struct page_pool_params pp_params = { 0 }; 1755 unsigned int num_pages; 1756 1757 rx_q->queue_index = queue; 1758 rx_q->priv_data = priv; 1759 1760 pp_params.flags = PP_FLAG_DMA_MAP; 1761 pp_params.pool_size = priv->dma_rx_size; 1762 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1763 pp_params.order = ilog2(num_pages); 1764 pp_params.nid = dev_to_node(priv->device); 1765 pp_params.dev = priv->device; 1766 pp_params.dma_dir = DMA_FROM_DEVICE; 1767 1768 rx_q->page_pool = page_pool_create(&pp_params); 1769 if (IS_ERR(rx_q->page_pool)) { 1770 ret = PTR_ERR(rx_q->page_pool); 1771 rx_q->page_pool = NULL; 1772 goto err_dma; 1773 } 1774 1775 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1776 sizeof(*rx_q->buf_pool), 1777 GFP_KERNEL); 1778 if (!rx_q->buf_pool) 1779 goto err_dma; 1780 1781 if (priv->extend_desc) { 1782 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1783 priv->dma_rx_size * 1784 sizeof(struct dma_extended_desc), 1785 &rx_q->dma_rx_phy, 1786 GFP_KERNEL); 1787 if (!rx_q->dma_erx) 1788 goto err_dma; 1789 1790 } else { 1791 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1792 priv->dma_rx_size * 1793 sizeof(struct dma_desc), 1794 &rx_q->dma_rx_phy, 1795 GFP_KERNEL); 1796 if (!rx_q->dma_rx) 1797 goto err_dma; 1798 } 1799 } 1800 1801 return 0; 1802 1803 err_dma: 1804 free_dma_rx_desc_resources(priv); 1805 1806 return ret; 1807 } 1808 1809 /** 1810 * alloc_dma_tx_desc_resources - alloc TX resources. 1811 * @priv: private structure 1812 * Description: according to which descriptor can be used (extend or basic) 1813 * this function allocates the resources for TX and RX paths. In case of 1814 * reception, for example, it pre-allocated the RX socket buffer in order to 1815 * allow zero-copy mechanism. 1816 */ 1817 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1818 { 1819 u32 tx_count = priv->plat->tx_queues_to_use; 1820 int ret = -ENOMEM; 1821 u32 queue; 1822 1823 /* TX queues buffers and DMA */ 1824 for (queue = 0; queue < tx_count; queue++) { 1825 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1826 size_t size; 1827 void *addr; 1828 1829 tx_q->queue_index = queue; 1830 tx_q->priv_data = priv; 1831 1832 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 1833 sizeof(*tx_q->tx_skbuff_dma), 1834 GFP_KERNEL); 1835 if (!tx_q->tx_skbuff_dma) 1836 goto err_dma; 1837 1838 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 1839 sizeof(struct sk_buff *), 1840 GFP_KERNEL); 1841 if (!tx_q->tx_skbuff) 1842 goto err_dma; 1843 1844 if (priv->extend_desc) 1845 size = sizeof(struct dma_extended_desc); 1846 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1847 size = sizeof(struct dma_edesc); 1848 else 1849 size = sizeof(struct dma_desc); 1850 1851 size *= priv->dma_tx_size; 1852 1853 addr = dma_alloc_coherent(priv->device, size, 1854 &tx_q->dma_tx_phy, GFP_KERNEL); 1855 if (!addr) 1856 goto err_dma; 1857 1858 if (priv->extend_desc) 1859 tx_q->dma_etx = addr; 1860 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1861 tx_q->dma_entx = addr; 1862 else 1863 tx_q->dma_tx = addr; 1864 } 1865 1866 return 0; 1867 1868 err_dma: 1869 free_dma_tx_desc_resources(priv); 1870 return ret; 1871 } 1872 1873 /** 1874 * alloc_dma_desc_resources - alloc TX/RX resources. 1875 * @priv: private structure 1876 * Description: according to which descriptor can be used (extend or basic) 1877 * this function allocates the resources for TX and RX paths. In case of 1878 * reception, for example, it pre-allocated the RX socket buffer in order to 1879 * allow zero-copy mechanism. 1880 */ 1881 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1882 { 1883 /* RX Allocation */ 1884 int ret = alloc_dma_rx_desc_resources(priv); 1885 1886 if (ret) 1887 return ret; 1888 1889 ret = alloc_dma_tx_desc_resources(priv); 1890 1891 return ret; 1892 } 1893 1894 /** 1895 * free_dma_desc_resources - free dma desc resources 1896 * @priv: private structure 1897 */ 1898 static void free_dma_desc_resources(struct stmmac_priv *priv) 1899 { 1900 /* Release the DMA RX socket buffers */ 1901 free_dma_rx_desc_resources(priv); 1902 1903 /* Release the DMA TX socket buffers */ 1904 free_dma_tx_desc_resources(priv); 1905 } 1906 1907 /** 1908 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1909 * @priv: driver private structure 1910 * Description: It is used for enabling the rx queues in the MAC 1911 */ 1912 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1913 { 1914 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1915 int queue; 1916 u8 mode; 1917 1918 for (queue = 0; queue < rx_queues_count; queue++) { 1919 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1920 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1921 } 1922 } 1923 1924 /** 1925 * stmmac_start_rx_dma - start RX DMA channel 1926 * @priv: driver private structure 1927 * @chan: RX channel index 1928 * Description: 1929 * This starts a RX DMA channel 1930 */ 1931 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1932 { 1933 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1934 stmmac_start_rx(priv, priv->ioaddr, chan); 1935 } 1936 1937 /** 1938 * stmmac_start_tx_dma - start TX DMA channel 1939 * @priv: driver private structure 1940 * @chan: TX channel index 1941 * Description: 1942 * This starts a TX DMA channel 1943 */ 1944 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1945 { 1946 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1947 stmmac_start_tx(priv, priv->ioaddr, chan); 1948 } 1949 1950 /** 1951 * stmmac_stop_rx_dma - stop RX DMA channel 1952 * @priv: driver private structure 1953 * @chan: RX channel index 1954 * Description: 1955 * This stops a RX DMA channel 1956 */ 1957 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1958 { 1959 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1960 stmmac_stop_rx(priv, priv->ioaddr, chan); 1961 } 1962 1963 /** 1964 * stmmac_stop_tx_dma - stop TX DMA channel 1965 * @priv: driver private structure 1966 * @chan: TX channel index 1967 * Description: 1968 * This stops a TX DMA channel 1969 */ 1970 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1971 { 1972 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1973 stmmac_stop_tx(priv, priv->ioaddr, chan); 1974 } 1975 1976 /** 1977 * stmmac_start_all_dma - start all RX and TX DMA channels 1978 * @priv: driver private structure 1979 * Description: 1980 * This starts all the RX and TX DMA channels 1981 */ 1982 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1983 { 1984 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1985 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1986 u32 chan = 0; 1987 1988 for (chan = 0; chan < rx_channels_count; chan++) 1989 stmmac_start_rx_dma(priv, chan); 1990 1991 for (chan = 0; chan < tx_channels_count; chan++) 1992 stmmac_start_tx_dma(priv, chan); 1993 } 1994 1995 /** 1996 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1997 * @priv: driver private structure 1998 * Description: 1999 * This stops the RX and TX DMA channels 2000 */ 2001 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2002 { 2003 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2004 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2005 u32 chan = 0; 2006 2007 for (chan = 0; chan < rx_channels_count; chan++) 2008 stmmac_stop_rx_dma(priv, chan); 2009 2010 for (chan = 0; chan < tx_channels_count; chan++) 2011 stmmac_stop_tx_dma(priv, chan); 2012 } 2013 2014 /** 2015 * stmmac_dma_operation_mode - HW DMA operation mode 2016 * @priv: driver private structure 2017 * Description: it is used for configuring the DMA operation mode register in 2018 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2019 */ 2020 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2021 { 2022 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2023 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2024 int rxfifosz = priv->plat->rx_fifo_size; 2025 int txfifosz = priv->plat->tx_fifo_size; 2026 u32 txmode = 0; 2027 u32 rxmode = 0; 2028 u32 chan = 0; 2029 u8 qmode = 0; 2030 2031 if (rxfifosz == 0) 2032 rxfifosz = priv->dma_cap.rx_fifo_size; 2033 if (txfifosz == 0) 2034 txfifosz = priv->dma_cap.tx_fifo_size; 2035 2036 /* Adjust for real per queue fifo size */ 2037 rxfifosz /= rx_channels_count; 2038 txfifosz /= tx_channels_count; 2039 2040 if (priv->plat->force_thresh_dma_mode) { 2041 txmode = tc; 2042 rxmode = tc; 2043 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2044 /* 2045 * In case of GMAC, SF mode can be enabled 2046 * to perform the TX COE in HW. This depends on: 2047 * 1) TX COE if actually supported 2048 * 2) There is no bugged Jumbo frame support 2049 * that needs to not insert csum in the TDES. 2050 */ 2051 txmode = SF_DMA_MODE; 2052 rxmode = SF_DMA_MODE; 2053 priv->xstats.threshold = SF_DMA_MODE; 2054 } else { 2055 txmode = tc; 2056 rxmode = SF_DMA_MODE; 2057 } 2058 2059 /* configure all channels */ 2060 for (chan = 0; chan < rx_channels_count; chan++) { 2061 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2062 2063 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2064 rxfifosz, qmode); 2065 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 2066 chan); 2067 } 2068 2069 for (chan = 0; chan < tx_channels_count; chan++) { 2070 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2071 2072 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2073 txfifosz, qmode); 2074 } 2075 } 2076 2077 /** 2078 * stmmac_tx_clean - to manage the transmission completion 2079 * @priv: driver private structure 2080 * @budget: napi budget limiting this functions packet handling 2081 * @queue: TX queue index 2082 * Description: it reclaims the transmit resources after transmission completes. 2083 */ 2084 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2085 { 2086 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2087 unsigned int bytes_compl = 0, pkts_compl = 0; 2088 unsigned int entry, count = 0; 2089 2090 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2091 2092 priv->xstats.tx_clean++; 2093 2094 entry = tx_q->dirty_tx; 2095 while ((entry != tx_q->cur_tx) && (count < budget)) { 2096 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 2097 struct dma_desc *p; 2098 int status; 2099 2100 if (priv->extend_desc) 2101 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2102 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2103 p = &tx_q->dma_entx[entry].basic; 2104 else 2105 p = tx_q->dma_tx + entry; 2106 2107 status = stmmac_tx_status(priv, &priv->dev->stats, 2108 &priv->xstats, p, priv->ioaddr); 2109 /* Check if the descriptor is owned by the DMA */ 2110 if (unlikely(status & tx_dma_own)) 2111 break; 2112 2113 count++; 2114 2115 /* Make sure descriptor fields are read after reading 2116 * the own bit. 2117 */ 2118 dma_rmb(); 2119 2120 /* Just consider the last segment and ...*/ 2121 if (likely(!(status & tx_not_ls))) { 2122 /* ... verify the status error condition */ 2123 if (unlikely(status & tx_err)) { 2124 priv->dev->stats.tx_errors++; 2125 } else { 2126 priv->dev->stats.tx_packets++; 2127 priv->xstats.tx_pkt_n++; 2128 } 2129 stmmac_get_tx_hwtstamp(priv, p, skb); 2130 } 2131 2132 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2133 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2134 dma_unmap_page(priv->device, 2135 tx_q->tx_skbuff_dma[entry].buf, 2136 tx_q->tx_skbuff_dma[entry].len, 2137 DMA_TO_DEVICE); 2138 else 2139 dma_unmap_single(priv->device, 2140 tx_q->tx_skbuff_dma[entry].buf, 2141 tx_q->tx_skbuff_dma[entry].len, 2142 DMA_TO_DEVICE); 2143 tx_q->tx_skbuff_dma[entry].buf = 0; 2144 tx_q->tx_skbuff_dma[entry].len = 0; 2145 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2146 } 2147 2148 stmmac_clean_desc3(priv, tx_q, p); 2149 2150 tx_q->tx_skbuff_dma[entry].last_segment = false; 2151 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2152 2153 if (likely(skb != NULL)) { 2154 pkts_compl++; 2155 bytes_compl += skb->len; 2156 dev_consume_skb_any(skb); 2157 tx_q->tx_skbuff[entry] = NULL; 2158 } 2159 2160 stmmac_release_tx_desc(priv, p, priv->mode); 2161 2162 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2163 } 2164 tx_q->dirty_tx = entry; 2165 2166 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2167 pkts_compl, bytes_compl); 2168 2169 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2170 queue))) && 2171 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2172 2173 netif_dbg(priv, tx_done, priv->dev, 2174 "%s: restart transmit\n", __func__); 2175 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2176 } 2177 2178 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2179 priv->eee_sw_timer_en) { 2180 stmmac_enable_eee_mode(priv); 2181 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2182 } 2183 2184 /* We still have pending packets, let's call for a new scheduling */ 2185 if (tx_q->dirty_tx != tx_q->cur_tx) 2186 hrtimer_start(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer), 2187 HRTIMER_MODE_REL); 2188 2189 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2190 2191 return count; 2192 } 2193 2194 /** 2195 * stmmac_tx_err - to manage the tx error 2196 * @priv: driver private structure 2197 * @chan: channel index 2198 * Description: it cleans the descriptors and restarts the transmission 2199 * in case of transmission errors. 2200 */ 2201 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2202 { 2203 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2204 2205 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2206 2207 stmmac_stop_tx_dma(priv, chan); 2208 dma_free_tx_skbufs(priv, chan); 2209 stmmac_clear_tx_descriptors(priv, chan); 2210 tx_q->dirty_tx = 0; 2211 tx_q->cur_tx = 0; 2212 tx_q->mss = 0; 2213 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2214 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2215 tx_q->dma_tx_phy, chan); 2216 stmmac_start_tx_dma(priv, chan); 2217 2218 priv->dev->stats.tx_errors++; 2219 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2220 } 2221 2222 /** 2223 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2224 * @priv: driver private structure 2225 * @txmode: TX operating mode 2226 * @rxmode: RX operating mode 2227 * @chan: channel index 2228 * Description: it is used for configuring of the DMA operation mode in 2229 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2230 * mode. 2231 */ 2232 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2233 u32 rxmode, u32 chan) 2234 { 2235 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2236 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2237 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2238 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2239 int rxfifosz = priv->plat->rx_fifo_size; 2240 int txfifosz = priv->plat->tx_fifo_size; 2241 2242 if (rxfifosz == 0) 2243 rxfifosz = priv->dma_cap.rx_fifo_size; 2244 if (txfifosz == 0) 2245 txfifosz = priv->dma_cap.tx_fifo_size; 2246 2247 /* Adjust for real per queue fifo size */ 2248 rxfifosz /= rx_channels_count; 2249 txfifosz /= tx_channels_count; 2250 2251 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2252 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2253 } 2254 2255 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2256 { 2257 int ret; 2258 2259 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2260 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2261 if (ret && (ret != -EINVAL)) { 2262 stmmac_global_err(priv); 2263 return true; 2264 } 2265 2266 return false; 2267 } 2268 2269 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2270 { 2271 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2272 &priv->xstats, chan); 2273 struct stmmac_channel *ch = &priv->channel[chan]; 2274 unsigned long flags; 2275 2276 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2277 if (napi_schedule_prep(&ch->rx_napi)) { 2278 spin_lock_irqsave(&ch->lock, flags); 2279 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2280 spin_unlock_irqrestore(&ch->lock, flags); 2281 __napi_schedule(&ch->rx_napi); 2282 } 2283 } 2284 2285 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2286 if (napi_schedule_prep(&ch->tx_napi)) { 2287 spin_lock_irqsave(&ch->lock, flags); 2288 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2289 spin_unlock_irqrestore(&ch->lock, flags); 2290 __napi_schedule(&ch->tx_napi); 2291 } 2292 } 2293 2294 return status; 2295 } 2296 2297 /** 2298 * stmmac_dma_interrupt - DMA ISR 2299 * @priv: driver private structure 2300 * Description: this is the DMA ISR. It is called by the main ISR. 2301 * It calls the dwmac dma routine and schedule poll method in case of some 2302 * work can be done. 2303 */ 2304 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2305 { 2306 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2307 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2308 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2309 tx_channel_count : rx_channel_count; 2310 u32 chan; 2311 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2312 2313 /* Make sure we never check beyond our status buffer. */ 2314 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2315 channels_to_check = ARRAY_SIZE(status); 2316 2317 for (chan = 0; chan < channels_to_check; chan++) 2318 status[chan] = stmmac_napi_check(priv, chan); 2319 2320 for (chan = 0; chan < tx_channel_count; chan++) { 2321 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2322 /* Try to bump up the dma threshold on this failure */ 2323 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2324 (tc <= 256)) { 2325 tc += 64; 2326 if (priv->plat->force_thresh_dma_mode) 2327 stmmac_set_dma_operation_mode(priv, 2328 tc, 2329 tc, 2330 chan); 2331 else 2332 stmmac_set_dma_operation_mode(priv, 2333 tc, 2334 SF_DMA_MODE, 2335 chan); 2336 priv->xstats.threshold = tc; 2337 } 2338 } else if (unlikely(status[chan] == tx_hard_error)) { 2339 stmmac_tx_err(priv, chan); 2340 } 2341 } 2342 } 2343 2344 /** 2345 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2346 * @priv: driver private structure 2347 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2348 */ 2349 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2350 { 2351 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2352 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2353 2354 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2355 2356 if (priv->dma_cap.rmon) { 2357 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2358 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2359 } else 2360 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2361 } 2362 2363 /** 2364 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2365 * @priv: driver private structure 2366 * Description: 2367 * new GMAC chip generations have a new register to indicate the 2368 * presence of the optional feature/functions. 2369 * This can be also used to override the value passed through the 2370 * platform and necessary for old MAC10/100 and GMAC chips. 2371 */ 2372 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2373 { 2374 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2375 } 2376 2377 /** 2378 * stmmac_check_ether_addr - check if the MAC addr is valid 2379 * @priv: driver private structure 2380 * Description: 2381 * it is to verify if the MAC address is valid, in case of failures it 2382 * generates a random MAC address 2383 */ 2384 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2385 { 2386 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2387 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2388 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2389 eth_hw_addr_random(priv->dev); 2390 dev_info(priv->device, "device MAC address %pM\n", 2391 priv->dev->dev_addr); 2392 } 2393 } 2394 2395 /** 2396 * stmmac_init_dma_engine - DMA init. 2397 * @priv: driver private structure 2398 * Description: 2399 * It inits the DMA invoking the specific MAC/GMAC callback. 2400 * Some DMA parameters can be passed from the platform; 2401 * in case of these are not passed a default is kept for the MAC or GMAC. 2402 */ 2403 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2404 { 2405 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2406 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2407 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2408 struct stmmac_rx_queue *rx_q; 2409 struct stmmac_tx_queue *tx_q; 2410 u32 chan = 0; 2411 int atds = 0; 2412 int ret = 0; 2413 2414 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2415 dev_err(priv->device, "Invalid DMA configuration\n"); 2416 return -EINVAL; 2417 } 2418 2419 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2420 atds = 1; 2421 2422 ret = stmmac_reset(priv, priv->ioaddr); 2423 if (ret) { 2424 dev_err(priv->device, "Failed to reset the dma\n"); 2425 return ret; 2426 } 2427 2428 /* DMA Configuration */ 2429 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2430 2431 if (priv->plat->axi) 2432 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2433 2434 /* DMA CSR Channel configuration */ 2435 for (chan = 0; chan < dma_csr_ch; chan++) 2436 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2437 2438 /* DMA RX Channel Configuration */ 2439 for (chan = 0; chan < rx_channels_count; chan++) { 2440 rx_q = &priv->rx_queue[chan]; 2441 2442 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2443 rx_q->dma_rx_phy, chan); 2444 2445 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2446 (priv->dma_rx_size * 2447 sizeof(struct dma_desc)); 2448 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2449 rx_q->rx_tail_addr, chan); 2450 } 2451 2452 /* DMA TX Channel Configuration */ 2453 for (chan = 0; chan < tx_channels_count; chan++) { 2454 tx_q = &priv->tx_queue[chan]; 2455 2456 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2457 tx_q->dma_tx_phy, chan); 2458 2459 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2460 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2461 tx_q->tx_tail_addr, chan); 2462 } 2463 2464 return ret; 2465 } 2466 2467 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2468 { 2469 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2470 2471 hrtimer_start(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer), 2472 HRTIMER_MODE_REL); 2473 } 2474 2475 /** 2476 * stmmac_tx_timer - mitigation sw timer for tx. 2477 * @t: data pointer 2478 * Description: 2479 * This is the timer handler to directly invoke the stmmac_tx_clean. 2480 */ 2481 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2482 { 2483 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2484 struct stmmac_priv *priv = tx_q->priv_data; 2485 struct stmmac_channel *ch; 2486 2487 ch = &priv->channel[tx_q->queue_index]; 2488 2489 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2490 unsigned long flags; 2491 2492 spin_lock_irqsave(&ch->lock, flags); 2493 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2494 spin_unlock_irqrestore(&ch->lock, flags); 2495 __napi_schedule(&ch->tx_napi); 2496 } 2497 2498 return HRTIMER_NORESTART; 2499 } 2500 2501 /** 2502 * stmmac_init_coalesce - init mitigation options. 2503 * @priv: driver private structure 2504 * Description: 2505 * This inits the coalesce parameters: i.e. timer rate, 2506 * timer handler and default threshold used for enabling the 2507 * interrupt on completion bit. 2508 */ 2509 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2510 { 2511 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2512 u32 chan; 2513 2514 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2515 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2516 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2517 2518 for (chan = 0; chan < tx_channel_count; chan++) { 2519 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2520 2521 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2522 tx_q->txtimer.function = stmmac_tx_timer; 2523 } 2524 } 2525 2526 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2527 { 2528 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2529 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2530 u32 chan; 2531 2532 /* set TX ring length */ 2533 for (chan = 0; chan < tx_channels_count; chan++) 2534 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2535 (priv->dma_tx_size - 1), chan); 2536 2537 /* set RX ring length */ 2538 for (chan = 0; chan < rx_channels_count; chan++) 2539 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2540 (priv->dma_rx_size - 1), chan); 2541 } 2542 2543 /** 2544 * stmmac_set_tx_queue_weight - Set TX queue weight 2545 * @priv: driver private structure 2546 * Description: It is used for setting TX queues weight 2547 */ 2548 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2549 { 2550 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2551 u32 weight; 2552 u32 queue; 2553 2554 for (queue = 0; queue < tx_queues_count; queue++) { 2555 weight = priv->plat->tx_queues_cfg[queue].weight; 2556 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2557 } 2558 } 2559 2560 /** 2561 * stmmac_configure_cbs - Configure CBS in TX queue 2562 * @priv: driver private structure 2563 * Description: It is used for configuring CBS in AVB TX queues 2564 */ 2565 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2566 { 2567 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2568 u32 mode_to_use; 2569 u32 queue; 2570 2571 /* queue 0 is reserved for legacy traffic */ 2572 for (queue = 1; queue < tx_queues_count; queue++) { 2573 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2574 if (mode_to_use == MTL_QUEUE_DCB) 2575 continue; 2576 2577 stmmac_config_cbs(priv, priv->hw, 2578 priv->plat->tx_queues_cfg[queue].send_slope, 2579 priv->plat->tx_queues_cfg[queue].idle_slope, 2580 priv->plat->tx_queues_cfg[queue].high_credit, 2581 priv->plat->tx_queues_cfg[queue].low_credit, 2582 queue); 2583 } 2584 } 2585 2586 /** 2587 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2588 * @priv: driver private structure 2589 * Description: It is used for mapping RX queues to RX dma channels 2590 */ 2591 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2592 { 2593 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2594 u32 queue; 2595 u32 chan; 2596 2597 for (queue = 0; queue < rx_queues_count; queue++) { 2598 chan = priv->plat->rx_queues_cfg[queue].chan; 2599 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2600 } 2601 } 2602 2603 /** 2604 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2605 * @priv: driver private structure 2606 * Description: It is used for configuring the RX Queue Priority 2607 */ 2608 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2609 { 2610 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2611 u32 queue; 2612 u32 prio; 2613 2614 for (queue = 0; queue < rx_queues_count; queue++) { 2615 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2616 continue; 2617 2618 prio = priv->plat->rx_queues_cfg[queue].prio; 2619 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2620 } 2621 } 2622 2623 /** 2624 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2625 * @priv: driver private structure 2626 * Description: It is used for configuring the TX Queue Priority 2627 */ 2628 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2629 { 2630 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2631 u32 queue; 2632 u32 prio; 2633 2634 for (queue = 0; queue < tx_queues_count; queue++) { 2635 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2636 continue; 2637 2638 prio = priv->plat->tx_queues_cfg[queue].prio; 2639 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2640 } 2641 } 2642 2643 /** 2644 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2645 * @priv: driver private structure 2646 * Description: It is used for configuring the RX queue routing 2647 */ 2648 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2649 { 2650 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2651 u32 queue; 2652 u8 packet; 2653 2654 for (queue = 0; queue < rx_queues_count; queue++) { 2655 /* no specific packet type routing specified for the queue */ 2656 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2657 continue; 2658 2659 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2660 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2661 } 2662 } 2663 2664 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2665 { 2666 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2667 priv->rss.enable = false; 2668 return; 2669 } 2670 2671 if (priv->dev->features & NETIF_F_RXHASH) 2672 priv->rss.enable = true; 2673 else 2674 priv->rss.enable = false; 2675 2676 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2677 priv->plat->rx_queues_to_use); 2678 } 2679 2680 /** 2681 * stmmac_mtl_configuration - Configure MTL 2682 * @priv: driver private structure 2683 * Description: It is used for configurring MTL 2684 */ 2685 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2686 { 2687 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2688 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2689 2690 if (tx_queues_count > 1) 2691 stmmac_set_tx_queue_weight(priv); 2692 2693 /* Configure MTL RX algorithms */ 2694 if (rx_queues_count > 1) 2695 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2696 priv->plat->rx_sched_algorithm); 2697 2698 /* Configure MTL TX algorithms */ 2699 if (tx_queues_count > 1) 2700 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2701 priv->plat->tx_sched_algorithm); 2702 2703 /* Configure CBS in AVB TX queues */ 2704 if (tx_queues_count > 1) 2705 stmmac_configure_cbs(priv); 2706 2707 /* Map RX MTL to DMA channels */ 2708 stmmac_rx_queue_dma_chan_map(priv); 2709 2710 /* Enable MAC RX Queues */ 2711 stmmac_mac_enable_rx_queues(priv); 2712 2713 /* Set RX priorities */ 2714 if (rx_queues_count > 1) 2715 stmmac_mac_config_rx_queues_prio(priv); 2716 2717 /* Set TX priorities */ 2718 if (tx_queues_count > 1) 2719 stmmac_mac_config_tx_queues_prio(priv); 2720 2721 /* Set RX routing */ 2722 if (rx_queues_count > 1) 2723 stmmac_mac_config_rx_queues_routing(priv); 2724 2725 /* Receive Side Scaling */ 2726 if (rx_queues_count > 1) 2727 stmmac_mac_config_rss(priv); 2728 } 2729 2730 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2731 { 2732 if (priv->dma_cap.asp) { 2733 netdev_info(priv->dev, "Enabling Safety Features\n"); 2734 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2735 } else { 2736 netdev_info(priv->dev, "No Safety Features support found\n"); 2737 } 2738 } 2739 2740 /** 2741 * stmmac_hw_setup - setup mac in a usable state. 2742 * @dev : pointer to the device structure. 2743 * @init_ptp: initialize PTP if set 2744 * Description: 2745 * this is the main function to setup the HW in a usable state because the 2746 * dma engine is reset, the core registers are configured (e.g. AXI, 2747 * Checksum features, timers). The DMA is ready to start receiving and 2748 * transmitting. 2749 * Return value: 2750 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2751 * file on failure. 2752 */ 2753 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2754 { 2755 struct stmmac_priv *priv = netdev_priv(dev); 2756 u32 rx_cnt = priv->plat->rx_queues_to_use; 2757 u32 tx_cnt = priv->plat->tx_queues_to_use; 2758 u32 chan; 2759 int ret; 2760 2761 /* DMA initialization and SW reset */ 2762 ret = stmmac_init_dma_engine(priv); 2763 if (ret < 0) { 2764 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2765 __func__); 2766 return ret; 2767 } 2768 2769 /* Copy the MAC addr into the HW */ 2770 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2771 2772 /* PS and related bits will be programmed according to the speed */ 2773 if (priv->hw->pcs) { 2774 int speed = priv->plat->mac_port_sel_speed; 2775 2776 if ((speed == SPEED_10) || (speed == SPEED_100) || 2777 (speed == SPEED_1000)) { 2778 priv->hw->ps = speed; 2779 } else { 2780 dev_warn(priv->device, "invalid port speed\n"); 2781 priv->hw->ps = 0; 2782 } 2783 } 2784 2785 /* Initialize the MAC Core */ 2786 stmmac_core_init(priv, priv->hw, dev); 2787 2788 /* Initialize MTL*/ 2789 stmmac_mtl_configuration(priv); 2790 2791 /* Initialize Safety Features */ 2792 stmmac_safety_feat_configuration(priv); 2793 2794 ret = stmmac_rx_ipc(priv, priv->hw); 2795 if (!ret) { 2796 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2797 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2798 priv->hw->rx_csum = 0; 2799 } 2800 2801 /* Enable the MAC Rx/Tx */ 2802 stmmac_mac_set(priv, priv->ioaddr, true); 2803 2804 /* Set the HW DMA mode and the COE */ 2805 stmmac_dma_operation_mode(priv); 2806 2807 stmmac_mmc_setup(priv); 2808 2809 if (init_ptp) { 2810 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2811 if (ret < 0) 2812 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2813 2814 ret = stmmac_init_ptp(priv); 2815 if (ret == -EOPNOTSUPP) 2816 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2817 else if (ret) 2818 netdev_warn(priv->dev, "PTP init failed\n"); 2819 } 2820 2821 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 2822 2823 /* Convert the timer from msec to usec */ 2824 if (!priv->tx_lpi_timer) 2825 priv->tx_lpi_timer = eee_timer * 1000; 2826 2827 if (priv->use_riwt) { 2828 if (!priv->rx_riwt) 2829 priv->rx_riwt = DEF_DMA_RIWT; 2830 2831 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2832 } 2833 2834 if (priv->hw->pcs) 2835 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2836 2837 /* set TX and RX rings length */ 2838 stmmac_set_rings_length(priv); 2839 2840 /* Enable TSO */ 2841 if (priv->tso) { 2842 for (chan = 0; chan < tx_cnt; chan++) 2843 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2844 } 2845 2846 /* Enable Split Header */ 2847 if (priv->sph && priv->hw->rx_csum) { 2848 for (chan = 0; chan < rx_cnt; chan++) 2849 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2850 } 2851 2852 /* VLAN Tag Insertion */ 2853 if (priv->dma_cap.vlins) 2854 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2855 2856 /* TBS */ 2857 for (chan = 0; chan < tx_cnt; chan++) { 2858 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2859 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2860 2861 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2862 } 2863 2864 /* Configure real RX and TX queues */ 2865 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 2866 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 2867 2868 /* Start the ball rolling... */ 2869 stmmac_start_all_dma(priv); 2870 2871 return 0; 2872 } 2873 2874 static void stmmac_hw_teardown(struct net_device *dev) 2875 { 2876 struct stmmac_priv *priv = netdev_priv(dev); 2877 2878 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2879 } 2880 2881 /** 2882 * stmmac_open - open entry point of the driver 2883 * @dev : pointer to the device structure. 2884 * Description: 2885 * This function is the open entry point of the driver. 2886 * Return value: 2887 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2888 * file on failure. 2889 */ 2890 static int stmmac_open(struct net_device *dev) 2891 { 2892 struct stmmac_priv *priv = netdev_priv(dev); 2893 int bfsize = 0; 2894 u32 chan; 2895 int ret; 2896 2897 if (priv->hw->pcs != STMMAC_PCS_TBI && 2898 priv->hw->pcs != STMMAC_PCS_RTBI && 2899 priv->hw->xpcs == NULL) { 2900 ret = stmmac_init_phy(dev); 2901 if (ret) { 2902 netdev_err(priv->dev, 2903 "%s: Cannot attach to PHY (error: %d)\n", 2904 __func__, ret); 2905 return ret; 2906 } 2907 } 2908 2909 /* Extra statistics */ 2910 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2911 priv->xstats.threshold = tc; 2912 2913 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2914 if (bfsize < 0) 2915 bfsize = 0; 2916 2917 if (bfsize < BUF_SIZE_16KiB) 2918 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2919 2920 priv->dma_buf_sz = bfsize; 2921 buf_sz = bfsize; 2922 2923 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2924 2925 if (!priv->dma_tx_size) 2926 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 2927 if (!priv->dma_rx_size) 2928 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 2929 2930 /* Earlier check for TBS */ 2931 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2932 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2933 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2934 2935 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2936 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2937 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2938 } 2939 2940 ret = alloc_dma_desc_resources(priv); 2941 if (ret < 0) { 2942 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2943 __func__); 2944 goto dma_desc_error; 2945 } 2946 2947 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2948 if (ret < 0) { 2949 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2950 __func__); 2951 goto init_error; 2952 } 2953 2954 ret = stmmac_hw_setup(dev, true); 2955 if (ret < 0) { 2956 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2957 goto init_error; 2958 } 2959 2960 stmmac_init_coalesce(priv); 2961 2962 phylink_start(priv->phylink); 2963 /* We may have called phylink_speed_down before */ 2964 phylink_speed_up(priv->phylink); 2965 2966 /* Request the IRQ lines */ 2967 ret = request_irq(dev->irq, stmmac_interrupt, 2968 IRQF_SHARED, dev->name, dev); 2969 if (unlikely(ret < 0)) { 2970 netdev_err(priv->dev, 2971 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2972 __func__, dev->irq, ret); 2973 goto irq_error; 2974 } 2975 2976 /* Request the Wake IRQ in case of another line is used for WoL */ 2977 if (priv->wol_irq != dev->irq) { 2978 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2979 IRQF_SHARED, dev->name, dev); 2980 if (unlikely(ret < 0)) { 2981 netdev_err(priv->dev, 2982 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2983 __func__, priv->wol_irq, ret); 2984 goto wolirq_error; 2985 } 2986 } 2987 2988 /* Request the IRQ lines */ 2989 if (priv->lpi_irq > 0) { 2990 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2991 dev->name, dev); 2992 if (unlikely(ret < 0)) { 2993 netdev_err(priv->dev, 2994 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2995 __func__, priv->lpi_irq, ret); 2996 goto lpiirq_error; 2997 } 2998 } 2999 3000 stmmac_enable_all_queues(priv); 3001 netif_tx_start_all_queues(priv->dev); 3002 3003 return 0; 3004 3005 lpiirq_error: 3006 if (priv->wol_irq != dev->irq) 3007 free_irq(priv->wol_irq, dev); 3008 wolirq_error: 3009 free_irq(dev->irq, dev); 3010 irq_error: 3011 phylink_stop(priv->phylink); 3012 3013 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3014 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3015 3016 stmmac_hw_teardown(dev); 3017 init_error: 3018 free_dma_desc_resources(priv); 3019 dma_desc_error: 3020 phylink_disconnect_phy(priv->phylink); 3021 return ret; 3022 } 3023 3024 /** 3025 * stmmac_release - close entry point of the driver 3026 * @dev : device pointer. 3027 * Description: 3028 * This is the stop entry point of the driver. 3029 */ 3030 static int stmmac_release(struct net_device *dev) 3031 { 3032 struct stmmac_priv *priv = netdev_priv(dev); 3033 u32 chan; 3034 3035 if (device_may_wakeup(priv->device)) 3036 phylink_speed_down(priv->phylink, false); 3037 /* Stop and disconnect the PHY */ 3038 phylink_stop(priv->phylink); 3039 phylink_disconnect_phy(priv->phylink); 3040 3041 stmmac_disable_all_queues(priv); 3042 3043 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3044 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3045 3046 /* Free the IRQ lines */ 3047 free_irq(dev->irq, dev); 3048 if (priv->wol_irq != dev->irq) 3049 free_irq(priv->wol_irq, dev); 3050 if (priv->lpi_irq > 0) 3051 free_irq(priv->lpi_irq, dev); 3052 3053 if (priv->eee_enabled) { 3054 priv->tx_path_in_lpi_mode = false; 3055 del_timer_sync(&priv->eee_ctrl_timer); 3056 } 3057 3058 /* Stop TX/RX DMA and clear the descriptors */ 3059 stmmac_stop_all_dma(priv); 3060 3061 /* Release and free the Rx/Tx resources */ 3062 free_dma_desc_resources(priv); 3063 3064 /* Disable the MAC Rx/Tx */ 3065 stmmac_mac_set(priv, priv->ioaddr, false); 3066 3067 netif_carrier_off(dev); 3068 3069 stmmac_release_ptp(priv); 3070 3071 return 0; 3072 } 3073 3074 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3075 struct stmmac_tx_queue *tx_q) 3076 { 3077 u16 tag = 0x0, inner_tag = 0x0; 3078 u32 inner_type = 0x0; 3079 struct dma_desc *p; 3080 3081 if (!priv->dma_cap.vlins) 3082 return false; 3083 if (!skb_vlan_tag_present(skb)) 3084 return false; 3085 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3086 inner_tag = skb_vlan_tag_get(skb); 3087 inner_type = STMMAC_VLAN_INSERT; 3088 } 3089 3090 tag = skb_vlan_tag_get(skb); 3091 3092 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3093 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3094 else 3095 p = &tx_q->dma_tx[tx_q->cur_tx]; 3096 3097 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3098 return false; 3099 3100 stmmac_set_tx_owner(priv, p); 3101 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3102 return true; 3103 } 3104 3105 /** 3106 * stmmac_tso_allocator - close entry point of the driver 3107 * @priv: driver private structure 3108 * @des: buffer start address 3109 * @total_len: total length to fill in descriptors 3110 * @last_segment: condition for the last descriptor 3111 * @queue: TX queue index 3112 * Description: 3113 * This function fills descriptor and request new descriptors according to 3114 * buffer length to fill 3115 */ 3116 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3117 int total_len, bool last_segment, u32 queue) 3118 { 3119 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3120 struct dma_desc *desc; 3121 u32 buff_size; 3122 int tmp_len; 3123 3124 tmp_len = total_len; 3125 3126 while (tmp_len > 0) { 3127 dma_addr_t curr_addr; 3128 3129 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3130 priv->dma_tx_size); 3131 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3132 3133 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3134 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3135 else 3136 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3137 3138 curr_addr = des + (total_len - tmp_len); 3139 if (priv->dma_cap.addr64 <= 32) 3140 desc->des0 = cpu_to_le32(curr_addr); 3141 else 3142 stmmac_set_desc_addr(priv, desc, curr_addr); 3143 3144 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3145 TSO_MAX_BUFF_SIZE : tmp_len; 3146 3147 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3148 0, 1, 3149 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3150 0, 0); 3151 3152 tmp_len -= TSO_MAX_BUFF_SIZE; 3153 } 3154 } 3155 3156 /** 3157 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3158 * @skb : the socket buffer 3159 * @dev : device pointer 3160 * Description: this is the transmit function that is called on TSO frames 3161 * (support available on GMAC4 and newer chips). 3162 * Diagram below show the ring programming in case of TSO frames: 3163 * 3164 * First Descriptor 3165 * -------- 3166 * | DES0 |---> buffer1 = L2/L3/L4 header 3167 * | DES1 |---> TCP Payload (can continue on next descr...) 3168 * | DES2 |---> buffer 1 and 2 len 3169 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3170 * -------- 3171 * | 3172 * ... 3173 * | 3174 * -------- 3175 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3176 * | DES1 | --| 3177 * | DES2 | --> buffer 1 and 2 len 3178 * | DES3 | 3179 * -------- 3180 * 3181 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3182 */ 3183 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3184 { 3185 struct dma_desc *desc, *first, *mss_desc = NULL; 3186 struct stmmac_priv *priv = netdev_priv(dev); 3187 int desc_size, tmp_pay_len = 0, first_tx; 3188 int nfrags = skb_shinfo(skb)->nr_frags; 3189 u32 queue = skb_get_queue_mapping(skb); 3190 unsigned int first_entry, tx_packets; 3191 struct stmmac_tx_queue *tx_q; 3192 bool has_vlan, set_ic; 3193 u8 proto_hdr_len, hdr; 3194 u32 pay_len, mss; 3195 dma_addr_t des; 3196 int i; 3197 3198 tx_q = &priv->tx_queue[queue]; 3199 first_tx = tx_q->cur_tx; 3200 3201 /* Compute header lengths */ 3202 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3203 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3204 hdr = sizeof(struct udphdr); 3205 } else { 3206 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3207 hdr = tcp_hdrlen(skb); 3208 } 3209 3210 /* Desc availability based on threshold should be enough safe */ 3211 if (unlikely(stmmac_tx_avail(priv, queue) < 3212 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3213 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3214 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3215 queue)); 3216 /* This is a hard error, log it. */ 3217 netdev_err(priv->dev, 3218 "%s: Tx Ring full when queue awake\n", 3219 __func__); 3220 } 3221 return NETDEV_TX_BUSY; 3222 } 3223 3224 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3225 3226 mss = skb_shinfo(skb)->gso_size; 3227 3228 /* set new MSS value if needed */ 3229 if (mss != tx_q->mss) { 3230 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3231 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3232 else 3233 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3234 3235 stmmac_set_mss(priv, mss_desc, mss); 3236 tx_q->mss = mss; 3237 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3238 priv->dma_tx_size); 3239 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3240 } 3241 3242 if (netif_msg_tx_queued(priv)) { 3243 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3244 __func__, hdr, proto_hdr_len, pay_len, mss); 3245 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3246 skb->data_len); 3247 } 3248 3249 /* Check if VLAN can be inserted by HW */ 3250 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3251 3252 first_entry = tx_q->cur_tx; 3253 WARN_ON(tx_q->tx_skbuff[first_entry]); 3254 3255 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3256 desc = &tx_q->dma_entx[first_entry].basic; 3257 else 3258 desc = &tx_q->dma_tx[first_entry]; 3259 first = desc; 3260 3261 if (has_vlan) 3262 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3263 3264 /* first descriptor: fill Headers on Buf1 */ 3265 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3266 DMA_TO_DEVICE); 3267 if (dma_mapping_error(priv->device, des)) 3268 goto dma_map_err; 3269 3270 tx_q->tx_skbuff_dma[first_entry].buf = des; 3271 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3272 3273 if (priv->dma_cap.addr64 <= 32) { 3274 first->des0 = cpu_to_le32(des); 3275 3276 /* Fill start of payload in buff2 of first descriptor */ 3277 if (pay_len) 3278 first->des1 = cpu_to_le32(des + proto_hdr_len); 3279 3280 /* If needed take extra descriptors to fill the remaining payload */ 3281 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3282 } else { 3283 stmmac_set_desc_addr(priv, first, des); 3284 tmp_pay_len = pay_len; 3285 des += proto_hdr_len; 3286 pay_len = 0; 3287 } 3288 3289 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3290 3291 /* Prepare fragments */ 3292 for (i = 0; i < nfrags; i++) { 3293 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3294 3295 des = skb_frag_dma_map(priv->device, frag, 0, 3296 skb_frag_size(frag), 3297 DMA_TO_DEVICE); 3298 if (dma_mapping_error(priv->device, des)) 3299 goto dma_map_err; 3300 3301 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3302 (i == nfrags - 1), queue); 3303 3304 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3305 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3306 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3307 } 3308 3309 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3310 3311 /* Only the last descriptor gets to point to the skb. */ 3312 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3313 3314 /* Manage tx mitigation */ 3315 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3316 tx_q->tx_count_frames += tx_packets; 3317 3318 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3319 set_ic = true; 3320 else if (!priv->tx_coal_frames) 3321 set_ic = false; 3322 else if (tx_packets > priv->tx_coal_frames) 3323 set_ic = true; 3324 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3325 set_ic = true; 3326 else 3327 set_ic = false; 3328 3329 if (set_ic) { 3330 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3331 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3332 else 3333 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3334 3335 tx_q->tx_count_frames = 0; 3336 stmmac_set_tx_ic(priv, desc); 3337 priv->xstats.tx_set_ic_bit++; 3338 } 3339 3340 /* We've used all descriptors we need for this skb, however, 3341 * advance cur_tx so that it references a fresh descriptor. 3342 * ndo_start_xmit will fill this descriptor the next time it's 3343 * called and stmmac_tx_clean may clean up to this descriptor. 3344 */ 3345 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3346 3347 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3348 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3349 __func__); 3350 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3351 } 3352 3353 dev->stats.tx_bytes += skb->len; 3354 priv->xstats.tx_tso_frames++; 3355 priv->xstats.tx_tso_nfrags += nfrags; 3356 3357 if (priv->sarc_type) 3358 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3359 3360 skb_tx_timestamp(skb); 3361 3362 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3363 priv->hwts_tx_en)) { 3364 /* declare that device is doing timestamping */ 3365 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3366 stmmac_enable_tx_timestamp(priv, first); 3367 } 3368 3369 /* Complete the first descriptor before granting the DMA */ 3370 stmmac_prepare_tso_tx_desc(priv, first, 1, 3371 proto_hdr_len, 3372 pay_len, 3373 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3374 hdr / 4, (skb->len - proto_hdr_len)); 3375 3376 /* If context desc is used to change MSS */ 3377 if (mss_desc) { 3378 /* Make sure that first descriptor has been completely 3379 * written, including its own bit. This is because MSS is 3380 * actually before first descriptor, so we need to make 3381 * sure that MSS's own bit is the last thing written. 3382 */ 3383 dma_wmb(); 3384 stmmac_set_tx_owner(priv, mss_desc); 3385 } 3386 3387 /* The own bit must be the latest setting done when prepare the 3388 * descriptor and then barrier is needed to make sure that 3389 * all is coherent before granting the DMA engine. 3390 */ 3391 wmb(); 3392 3393 if (netif_msg_pktdata(priv)) { 3394 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3395 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3396 tx_q->cur_tx, first, nfrags); 3397 pr_info(">>> frame to be transmitted: "); 3398 print_pkt(skb->data, skb_headlen(skb)); 3399 } 3400 3401 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3402 3403 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3404 desc_size = sizeof(struct dma_edesc); 3405 else 3406 desc_size = sizeof(struct dma_desc); 3407 3408 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3409 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3410 stmmac_tx_timer_arm(priv, queue); 3411 3412 return NETDEV_TX_OK; 3413 3414 dma_map_err: 3415 dev_err(priv->device, "Tx dma map failed\n"); 3416 dev_kfree_skb(skb); 3417 priv->dev->stats.tx_dropped++; 3418 return NETDEV_TX_OK; 3419 } 3420 3421 /** 3422 * stmmac_xmit - Tx entry point of the driver 3423 * @skb : the socket buffer 3424 * @dev : device pointer 3425 * Description : this is the tx entry point of the driver. 3426 * It programs the chain or the ring and supports oversized frames 3427 * and SG feature. 3428 */ 3429 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3430 { 3431 unsigned int first_entry, tx_packets, enh_desc; 3432 struct stmmac_priv *priv = netdev_priv(dev); 3433 unsigned int nopaged_len = skb_headlen(skb); 3434 int i, csum_insertion = 0, is_jumbo = 0; 3435 u32 queue = skb_get_queue_mapping(skb); 3436 int nfrags = skb_shinfo(skb)->nr_frags; 3437 int gso = skb_shinfo(skb)->gso_type; 3438 struct dma_edesc *tbs_desc = NULL; 3439 int entry, desc_size, first_tx; 3440 struct dma_desc *desc, *first; 3441 struct stmmac_tx_queue *tx_q; 3442 bool has_vlan, set_ic; 3443 dma_addr_t des; 3444 3445 tx_q = &priv->tx_queue[queue]; 3446 first_tx = tx_q->cur_tx; 3447 3448 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 3449 stmmac_disable_eee_mode(priv); 3450 3451 /* Manage oversized TCP frames for GMAC4 device */ 3452 if (skb_is_gso(skb) && priv->tso) { 3453 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3454 return stmmac_tso_xmit(skb, dev); 3455 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3456 return stmmac_tso_xmit(skb, dev); 3457 } 3458 3459 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3460 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3461 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3462 queue)); 3463 /* This is a hard error, log it. */ 3464 netdev_err(priv->dev, 3465 "%s: Tx Ring full when queue awake\n", 3466 __func__); 3467 } 3468 return NETDEV_TX_BUSY; 3469 } 3470 3471 /* Check if VLAN can be inserted by HW */ 3472 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3473 3474 entry = tx_q->cur_tx; 3475 first_entry = entry; 3476 WARN_ON(tx_q->tx_skbuff[first_entry]); 3477 3478 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3479 3480 if (likely(priv->extend_desc)) 3481 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3482 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3483 desc = &tx_q->dma_entx[entry].basic; 3484 else 3485 desc = tx_q->dma_tx + entry; 3486 3487 first = desc; 3488 3489 if (has_vlan) 3490 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3491 3492 enh_desc = priv->plat->enh_desc; 3493 /* To program the descriptors according to the size of the frame */ 3494 if (enh_desc) 3495 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3496 3497 if (unlikely(is_jumbo)) { 3498 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3499 if (unlikely(entry < 0) && (entry != -EINVAL)) 3500 goto dma_map_err; 3501 } 3502 3503 for (i = 0; i < nfrags; i++) { 3504 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3505 int len = skb_frag_size(frag); 3506 bool last_segment = (i == (nfrags - 1)); 3507 3508 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3509 WARN_ON(tx_q->tx_skbuff[entry]); 3510 3511 if (likely(priv->extend_desc)) 3512 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3513 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3514 desc = &tx_q->dma_entx[entry].basic; 3515 else 3516 desc = tx_q->dma_tx + entry; 3517 3518 des = skb_frag_dma_map(priv->device, frag, 0, len, 3519 DMA_TO_DEVICE); 3520 if (dma_mapping_error(priv->device, des)) 3521 goto dma_map_err; /* should reuse desc w/o issues */ 3522 3523 tx_q->tx_skbuff_dma[entry].buf = des; 3524 3525 stmmac_set_desc_addr(priv, desc, des); 3526 3527 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3528 tx_q->tx_skbuff_dma[entry].len = len; 3529 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3530 3531 /* Prepare the descriptor and set the own bit too */ 3532 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3533 priv->mode, 1, last_segment, skb->len); 3534 } 3535 3536 /* Only the last descriptor gets to point to the skb. */ 3537 tx_q->tx_skbuff[entry] = skb; 3538 3539 /* According to the coalesce parameter the IC bit for the latest 3540 * segment is reset and the timer re-started to clean the tx status. 3541 * This approach takes care about the fragments: desc is the first 3542 * element in case of no SG. 3543 */ 3544 tx_packets = (entry + 1) - first_tx; 3545 tx_q->tx_count_frames += tx_packets; 3546 3547 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3548 set_ic = true; 3549 else if (!priv->tx_coal_frames) 3550 set_ic = false; 3551 else if (tx_packets > priv->tx_coal_frames) 3552 set_ic = true; 3553 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3554 set_ic = true; 3555 else 3556 set_ic = false; 3557 3558 if (set_ic) { 3559 if (likely(priv->extend_desc)) 3560 desc = &tx_q->dma_etx[entry].basic; 3561 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3562 desc = &tx_q->dma_entx[entry].basic; 3563 else 3564 desc = &tx_q->dma_tx[entry]; 3565 3566 tx_q->tx_count_frames = 0; 3567 stmmac_set_tx_ic(priv, desc); 3568 priv->xstats.tx_set_ic_bit++; 3569 } 3570 3571 /* We've used all descriptors we need for this skb, however, 3572 * advance cur_tx so that it references a fresh descriptor. 3573 * ndo_start_xmit will fill this descriptor the next time it's 3574 * called and stmmac_tx_clean may clean up to this descriptor. 3575 */ 3576 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3577 tx_q->cur_tx = entry; 3578 3579 if (netif_msg_pktdata(priv)) { 3580 netdev_dbg(priv->dev, 3581 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3582 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3583 entry, first, nfrags); 3584 3585 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3586 print_pkt(skb->data, skb->len); 3587 } 3588 3589 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3590 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3591 __func__); 3592 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3593 } 3594 3595 dev->stats.tx_bytes += skb->len; 3596 3597 if (priv->sarc_type) 3598 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3599 3600 skb_tx_timestamp(skb); 3601 3602 /* Ready to fill the first descriptor and set the OWN bit w/o any 3603 * problems because all the descriptors are actually ready to be 3604 * passed to the DMA engine. 3605 */ 3606 if (likely(!is_jumbo)) { 3607 bool last_segment = (nfrags == 0); 3608 3609 des = dma_map_single(priv->device, skb->data, 3610 nopaged_len, DMA_TO_DEVICE); 3611 if (dma_mapping_error(priv->device, des)) 3612 goto dma_map_err; 3613 3614 tx_q->tx_skbuff_dma[first_entry].buf = des; 3615 3616 stmmac_set_desc_addr(priv, first, des); 3617 3618 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3619 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3620 3621 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3622 priv->hwts_tx_en)) { 3623 /* declare that device is doing timestamping */ 3624 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3625 stmmac_enable_tx_timestamp(priv, first); 3626 } 3627 3628 /* Prepare the first descriptor setting the OWN bit too */ 3629 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3630 csum_insertion, priv->mode, 0, last_segment, 3631 skb->len); 3632 } 3633 3634 if (tx_q->tbs & STMMAC_TBS_EN) { 3635 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3636 3637 tbs_desc = &tx_q->dma_entx[first_entry]; 3638 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3639 } 3640 3641 stmmac_set_tx_owner(priv, first); 3642 3643 /* The own bit must be the latest setting done when prepare the 3644 * descriptor and then barrier is needed to make sure that 3645 * all is coherent before granting the DMA engine. 3646 */ 3647 wmb(); 3648 3649 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3650 3651 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3652 3653 if (likely(priv->extend_desc)) 3654 desc_size = sizeof(struct dma_extended_desc); 3655 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3656 desc_size = sizeof(struct dma_edesc); 3657 else 3658 desc_size = sizeof(struct dma_desc); 3659 3660 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3661 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3662 stmmac_tx_timer_arm(priv, queue); 3663 3664 return NETDEV_TX_OK; 3665 3666 dma_map_err: 3667 netdev_err(priv->dev, "Tx DMA map failed\n"); 3668 dev_kfree_skb(skb); 3669 priv->dev->stats.tx_dropped++; 3670 return NETDEV_TX_OK; 3671 } 3672 3673 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3674 { 3675 struct vlan_ethhdr *veth; 3676 __be16 vlan_proto; 3677 u16 vlanid; 3678 3679 veth = (struct vlan_ethhdr *)skb->data; 3680 vlan_proto = veth->h_vlan_proto; 3681 3682 if ((vlan_proto == htons(ETH_P_8021Q) && 3683 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3684 (vlan_proto == htons(ETH_P_8021AD) && 3685 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3686 /* pop the vlan tag */ 3687 vlanid = ntohs(veth->h_vlan_TCI); 3688 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3689 skb_pull(skb, VLAN_HLEN); 3690 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3691 } 3692 } 3693 3694 /** 3695 * stmmac_rx_refill - refill used skb preallocated buffers 3696 * @priv: driver private structure 3697 * @queue: RX queue index 3698 * Description : this is to reallocate the skb for the reception process 3699 * that is based on zero-copy. 3700 */ 3701 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3702 { 3703 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3704 int len, dirty = stmmac_rx_dirty(priv, queue); 3705 unsigned int entry = rx_q->dirty_rx; 3706 3707 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3708 3709 while (dirty-- > 0) { 3710 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3711 struct dma_desc *p; 3712 bool use_rx_wd; 3713 3714 if (priv->extend_desc) 3715 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3716 else 3717 p = rx_q->dma_rx + entry; 3718 3719 if (!buf->page) { 3720 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3721 if (!buf->page) 3722 break; 3723 } 3724 3725 if (priv->sph && !buf->sec_page) { 3726 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3727 if (!buf->sec_page) 3728 break; 3729 3730 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3731 3732 dma_sync_single_for_device(priv->device, buf->sec_addr, 3733 len, DMA_FROM_DEVICE); 3734 } 3735 3736 buf->addr = page_pool_get_dma_addr(buf->page); 3737 3738 /* Sync whole allocation to device. This will invalidate old 3739 * data. 3740 */ 3741 dma_sync_single_for_device(priv->device, buf->addr, len, 3742 DMA_FROM_DEVICE); 3743 3744 stmmac_set_desc_addr(priv, p, buf->addr); 3745 if (priv->sph) 3746 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 3747 else 3748 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 3749 stmmac_refill_desc3(priv, rx_q, p); 3750 3751 rx_q->rx_count_frames++; 3752 rx_q->rx_count_frames += priv->rx_coal_frames; 3753 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3754 rx_q->rx_count_frames = 0; 3755 3756 use_rx_wd = !priv->rx_coal_frames; 3757 use_rx_wd |= rx_q->rx_count_frames > 0; 3758 if (!priv->use_riwt) 3759 use_rx_wd = false; 3760 3761 dma_wmb(); 3762 stmmac_set_rx_owner(priv, p, use_rx_wd); 3763 3764 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 3765 } 3766 rx_q->dirty_rx = entry; 3767 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3768 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3769 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3770 } 3771 3772 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3773 struct dma_desc *p, 3774 int status, unsigned int len) 3775 { 3776 unsigned int plen = 0, hlen = 0; 3777 int coe = priv->hw->rx_csum; 3778 3779 /* Not first descriptor, buffer is always zero */ 3780 if (priv->sph && len) 3781 return 0; 3782 3783 /* First descriptor, get split header length */ 3784 stmmac_get_rx_header_len(priv, p, &hlen); 3785 if (priv->sph && hlen) { 3786 priv->xstats.rx_split_hdr_pkt_n++; 3787 return hlen; 3788 } 3789 3790 /* First descriptor, not last descriptor and not split header */ 3791 if (status & rx_not_ls) 3792 return priv->dma_buf_sz; 3793 3794 plen = stmmac_get_rx_frame_len(priv, p, coe); 3795 3796 /* First descriptor and last descriptor and not split header */ 3797 return min_t(unsigned int, priv->dma_buf_sz, plen); 3798 } 3799 3800 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3801 struct dma_desc *p, 3802 int status, unsigned int len) 3803 { 3804 int coe = priv->hw->rx_csum; 3805 unsigned int plen = 0; 3806 3807 /* Not split header, buffer is not available */ 3808 if (!priv->sph) 3809 return 0; 3810 3811 /* Not last descriptor */ 3812 if (status & rx_not_ls) 3813 return priv->dma_buf_sz; 3814 3815 plen = stmmac_get_rx_frame_len(priv, p, coe); 3816 3817 /* Last descriptor */ 3818 return plen - len; 3819 } 3820 3821 /** 3822 * stmmac_rx - manage the receive process 3823 * @priv: driver private structure 3824 * @limit: napi bugget 3825 * @queue: RX queue index. 3826 * Description : this the function called by the napi poll method. 3827 * It gets all the frames inside the ring. 3828 */ 3829 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3830 { 3831 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3832 struct stmmac_channel *ch = &priv->channel[queue]; 3833 unsigned int count = 0, error = 0, len = 0; 3834 int status = 0, coe = priv->hw->rx_csum; 3835 unsigned int next_entry = rx_q->cur_rx; 3836 unsigned int desc_size; 3837 struct sk_buff *skb = NULL; 3838 3839 if (netif_msg_rx_status(priv)) { 3840 void *rx_head; 3841 3842 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3843 if (priv->extend_desc) { 3844 rx_head = (void *)rx_q->dma_erx; 3845 desc_size = sizeof(struct dma_extended_desc); 3846 } else { 3847 rx_head = (void *)rx_q->dma_rx; 3848 desc_size = sizeof(struct dma_desc); 3849 } 3850 3851 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 3852 rx_q->dma_rx_phy, desc_size); 3853 } 3854 while (count < limit) { 3855 unsigned int buf1_len = 0, buf2_len = 0; 3856 enum pkt_hash_types hash_type; 3857 struct stmmac_rx_buffer *buf; 3858 struct dma_desc *np, *p; 3859 int entry; 3860 u32 hash; 3861 3862 if (!count && rx_q->state_saved) { 3863 skb = rx_q->state.skb; 3864 error = rx_q->state.error; 3865 len = rx_q->state.len; 3866 } else { 3867 rx_q->state_saved = false; 3868 skb = NULL; 3869 error = 0; 3870 len = 0; 3871 } 3872 3873 if (count >= limit) 3874 break; 3875 3876 read_again: 3877 buf1_len = 0; 3878 buf2_len = 0; 3879 entry = next_entry; 3880 buf = &rx_q->buf_pool[entry]; 3881 3882 if (priv->extend_desc) 3883 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3884 else 3885 p = rx_q->dma_rx + entry; 3886 3887 /* read the status of the incoming frame */ 3888 status = stmmac_rx_status(priv, &priv->dev->stats, 3889 &priv->xstats, p); 3890 /* check if managed by the DMA otherwise go ahead */ 3891 if (unlikely(status & dma_own)) 3892 break; 3893 3894 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 3895 priv->dma_rx_size); 3896 next_entry = rx_q->cur_rx; 3897 3898 if (priv->extend_desc) 3899 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3900 else 3901 np = rx_q->dma_rx + next_entry; 3902 3903 prefetch(np); 3904 3905 if (priv->extend_desc) 3906 stmmac_rx_extended_status(priv, &priv->dev->stats, 3907 &priv->xstats, rx_q->dma_erx + entry); 3908 if (unlikely(status == discard_frame)) { 3909 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3910 buf->page = NULL; 3911 error = 1; 3912 if (!priv->hwts_rx_en) 3913 priv->dev->stats.rx_errors++; 3914 } 3915 3916 if (unlikely(error && (status & rx_not_ls))) 3917 goto read_again; 3918 if (unlikely(error)) { 3919 dev_kfree_skb(skb); 3920 skb = NULL; 3921 count++; 3922 continue; 3923 } 3924 3925 /* Buffer is good. Go on. */ 3926 3927 prefetch(page_address(buf->page)); 3928 if (buf->sec_page) 3929 prefetch(page_address(buf->sec_page)); 3930 3931 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3932 len += buf1_len; 3933 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3934 len += buf2_len; 3935 3936 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3937 * Type frames (LLC/LLC-SNAP) 3938 * 3939 * llc_snap is never checked in GMAC >= 4, so this ACS 3940 * feature is always disabled and packets need to be 3941 * stripped manually. 3942 */ 3943 if (likely(!(status & rx_not_ls)) && 3944 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3945 unlikely(status != llc_snap))) { 3946 if (buf2_len) 3947 buf2_len -= ETH_FCS_LEN; 3948 else 3949 buf1_len -= ETH_FCS_LEN; 3950 3951 len -= ETH_FCS_LEN; 3952 } 3953 3954 if (!skb) { 3955 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3956 if (!skb) { 3957 priv->dev->stats.rx_dropped++; 3958 count++; 3959 goto drain_data; 3960 } 3961 3962 dma_sync_single_for_cpu(priv->device, buf->addr, 3963 buf1_len, DMA_FROM_DEVICE); 3964 skb_copy_to_linear_data(skb, page_address(buf->page), 3965 buf1_len); 3966 skb_put(skb, buf1_len); 3967 3968 /* Data payload copied into SKB, page ready for recycle */ 3969 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3970 buf->page = NULL; 3971 } else if (buf1_len) { 3972 dma_sync_single_for_cpu(priv->device, buf->addr, 3973 buf1_len, DMA_FROM_DEVICE); 3974 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3975 buf->page, 0, buf1_len, 3976 priv->dma_buf_sz); 3977 3978 /* Data payload appended into SKB */ 3979 page_pool_release_page(rx_q->page_pool, buf->page); 3980 buf->page = NULL; 3981 } 3982 3983 if (buf2_len) { 3984 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3985 buf2_len, DMA_FROM_DEVICE); 3986 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3987 buf->sec_page, 0, buf2_len, 3988 priv->dma_buf_sz); 3989 3990 /* Data payload appended into SKB */ 3991 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3992 buf->sec_page = NULL; 3993 } 3994 3995 drain_data: 3996 if (likely(status & rx_not_ls)) 3997 goto read_again; 3998 if (!skb) 3999 continue; 4000 4001 /* Got entire packet into SKB. Finish it. */ 4002 4003 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4004 stmmac_rx_vlan(priv->dev, skb); 4005 skb->protocol = eth_type_trans(skb, priv->dev); 4006 4007 if (unlikely(!coe)) 4008 skb_checksum_none_assert(skb); 4009 else 4010 skb->ip_summed = CHECKSUM_UNNECESSARY; 4011 4012 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4013 skb_set_hash(skb, hash, hash_type); 4014 4015 skb_record_rx_queue(skb, queue); 4016 napi_gro_receive(&ch->rx_napi, skb); 4017 skb = NULL; 4018 4019 priv->dev->stats.rx_packets++; 4020 priv->dev->stats.rx_bytes += len; 4021 count++; 4022 } 4023 4024 if (status & rx_not_ls || skb) { 4025 rx_q->state_saved = true; 4026 rx_q->state.skb = skb; 4027 rx_q->state.error = error; 4028 rx_q->state.len = len; 4029 } 4030 4031 stmmac_rx_refill(priv, queue); 4032 4033 priv->xstats.rx_pkt_n += count; 4034 4035 return count; 4036 } 4037 4038 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 4039 { 4040 struct stmmac_channel *ch = 4041 container_of(napi, struct stmmac_channel, rx_napi); 4042 struct stmmac_priv *priv = ch->priv_data; 4043 u32 chan = ch->index; 4044 int work_done; 4045 4046 priv->xstats.napi_poll++; 4047 4048 work_done = stmmac_rx(priv, budget, chan); 4049 if (work_done < budget && napi_complete_done(napi, work_done)) { 4050 unsigned long flags; 4051 4052 spin_lock_irqsave(&ch->lock, flags); 4053 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 4054 spin_unlock_irqrestore(&ch->lock, flags); 4055 } 4056 4057 return work_done; 4058 } 4059 4060 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 4061 { 4062 struct stmmac_channel *ch = 4063 container_of(napi, struct stmmac_channel, tx_napi); 4064 struct stmmac_priv *priv = ch->priv_data; 4065 u32 chan = ch->index; 4066 int work_done; 4067 4068 priv->xstats.napi_poll++; 4069 4070 work_done = stmmac_tx_clean(priv, priv->dma_tx_size, chan); 4071 work_done = min(work_done, budget); 4072 4073 if (work_done < budget && napi_complete_done(napi, work_done)) { 4074 unsigned long flags; 4075 4076 spin_lock_irqsave(&ch->lock, flags); 4077 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 4078 spin_unlock_irqrestore(&ch->lock, flags); 4079 } 4080 4081 return work_done; 4082 } 4083 4084 /** 4085 * stmmac_tx_timeout 4086 * @dev : Pointer to net device structure 4087 * @txqueue: the index of the hanging transmit queue 4088 * Description: this function is called when a packet transmission fails to 4089 * complete within a reasonable time. The driver will mark the error in the 4090 * netdev structure and arrange for the device to be reset to a sane state 4091 * in order to transmit a new packet. 4092 */ 4093 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 4094 { 4095 struct stmmac_priv *priv = netdev_priv(dev); 4096 4097 stmmac_global_err(priv); 4098 } 4099 4100 /** 4101 * stmmac_set_rx_mode - entry point for multicast addressing 4102 * @dev : pointer to the device structure 4103 * Description: 4104 * This function is a driver entry point which gets called by the kernel 4105 * whenever multicast addresses must be enabled/disabled. 4106 * Return value: 4107 * void. 4108 */ 4109 static void stmmac_set_rx_mode(struct net_device *dev) 4110 { 4111 struct stmmac_priv *priv = netdev_priv(dev); 4112 4113 stmmac_set_filter(priv, priv->hw, dev); 4114 } 4115 4116 /** 4117 * stmmac_change_mtu - entry point to change MTU size for the device. 4118 * @dev : device pointer. 4119 * @new_mtu : the new MTU size for the device. 4120 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 4121 * to drive packet transmission. Ethernet has an MTU of 1500 octets 4122 * (ETH_DATA_LEN). This value can be changed with ifconfig. 4123 * Return value: 4124 * 0 on success and an appropriate (-)ve integer as defined in errno.h 4125 * file on failure. 4126 */ 4127 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 4128 { 4129 struct stmmac_priv *priv = netdev_priv(dev); 4130 int txfifosz = priv->plat->tx_fifo_size; 4131 const int mtu = new_mtu; 4132 4133 if (txfifosz == 0) 4134 txfifosz = priv->dma_cap.tx_fifo_size; 4135 4136 txfifosz /= priv->plat->tx_queues_to_use; 4137 4138 if (netif_running(dev)) { 4139 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 4140 return -EBUSY; 4141 } 4142 4143 new_mtu = STMMAC_ALIGN(new_mtu); 4144 4145 /* If condition true, FIFO is too small or MTU too large */ 4146 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 4147 return -EINVAL; 4148 4149 dev->mtu = mtu; 4150 4151 netdev_update_features(dev); 4152 4153 return 0; 4154 } 4155 4156 static netdev_features_t stmmac_fix_features(struct net_device *dev, 4157 netdev_features_t features) 4158 { 4159 struct stmmac_priv *priv = netdev_priv(dev); 4160 4161 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4162 features &= ~NETIF_F_RXCSUM; 4163 4164 if (!priv->plat->tx_coe) 4165 features &= ~NETIF_F_CSUM_MASK; 4166 4167 /* Some GMAC devices have a bugged Jumbo frame support that 4168 * needs to have the Tx COE disabled for oversized frames 4169 * (due to limited buffer sizes). In this case we disable 4170 * the TX csum insertion in the TDES and not use SF. 4171 */ 4172 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4173 features &= ~NETIF_F_CSUM_MASK; 4174 4175 /* Disable tso if asked by ethtool */ 4176 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4177 if (features & NETIF_F_TSO) 4178 priv->tso = true; 4179 else 4180 priv->tso = false; 4181 } 4182 4183 return features; 4184 } 4185 4186 static int stmmac_set_features(struct net_device *netdev, 4187 netdev_features_t features) 4188 { 4189 struct stmmac_priv *priv = netdev_priv(netdev); 4190 bool sph_en; 4191 u32 chan; 4192 4193 /* Keep the COE Type in case of csum is supporting */ 4194 if (features & NETIF_F_RXCSUM) 4195 priv->hw->rx_csum = priv->plat->rx_coe; 4196 else 4197 priv->hw->rx_csum = 0; 4198 /* No check needed because rx_coe has been set before and it will be 4199 * fixed in case of issue. 4200 */ 4201 stmmac_rx_ipc(priv, priv->hw); 4202 4203 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4204 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4205 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4206 4207 return 0; 4208 } 4209 4210 /** 4211 * stmmac_interrupt - main ISR 4212 * @irq: interrupt number. 4213 * @dev_id: to pass the net device pointer (must be valid). 4214 * Description: this is the main driver interrupt service routine. 4215 * It can call: 4216 * o DMA service routine (to manage incoming frame reception and transmission 4217 * status) 4218 * o Core interrupts to manage: remote wake-up, management counter, LPI 4219 * interrupts. 4220 */ 4221 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4222 { 4223 struct net_device *dev = (struct net_device *)dev_id; 4224 struct stmmac_priv *priv = netdev_priv(dev); 4225 u32 rx_cnt = priv->plat->rx_queues_to_use; 4226 u32 tx_cnt = priv->plat->tx_queues_to_use; 4227 u32 queues_count; 4228 u32 queue; 4229 bool xmac; 4230 4231 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4232 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4233 4234 if (priv->irq_wake) 4235 pm_wakeup_event(priv->device, 0); 4236 4237 /* Check if adapter is up */ 4238 if (test_bit(STMMAC_DOWN, &priv->state)) 4239 return IRQ_HANDLED; 4240 /* Check if a fatal error happened */ 4241 if (stmmac_safety_feat_interrupt(priv)) 4242 return IRQ_HANDLED; 4243 4244 /* To handle GMAC own interrupts */ 4245 if ((priv->plat->has_gmac) || xmac) { 4246 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4247 int mtl_status; 4248 4249 if (unlikely(status)) { 4250 /* For LPI we need to save the tx status */ 4251 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4252 priv->tx_path_in_lpi_mode = true; 4253 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4254 priv->tx_path_in_lpi_mode = false; 4255 } 4256 4257 for (queue = 0; queue < queues_count; queue++) { 4258 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4259 4260 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4261 queue); 4262 if (mtl_status != -EINVAL) 4263 status |= mtl_status; 4264 4265 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4266 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4267 rx_q->rx_tail_addr, 4268 queue); 4269 } 4270 4271 /* PCS link status */ 4272 if (priv->hw->pcs) { 4273 if (priv->xstats.pcs_link) 4274 netif_carrier_on(dev); 4275 else 4276 netif_carrier_off(dev); 4277 } 4278 } 4279 4280 /* To handle DMA interrupts */ 4281 stmmac_dma_interrupt(priv); 4282 4283 return IRQ_HANDLED; 4284 } 4285 4286 #ifdef CONFIG_NET_POLL_CONTROLLER 4287 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4288 * to allow network I/O with interrupts disabled. 4289 */ 4290 static void stmmac_poll_controller(struct net_device *dev) 4291 { 4292 disable_irq(dev->irq); 4293 stmmac_interrupt(dev->irq, dev); 4294 enable_irq(dev->irq); 4295 } 4296 #endif 4297 4298 /** 4299 * stmmac_ioctl - Entry point for the Ioctl 4300 * @dev: Device pointer. 4301 * @rq: An IOCTL specefic structure, that can contain a pointer to 4302 * a proprietary structure used to pass information to the driver. 4303 * @cmd: IOCTL command 4304 * Description: 4305 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4306 */ 4307 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4308 { 4309 struct stmmac_priv *priv = netdev_priv (dev); 4310 int ret = -EOPNOTSUPP; 4311 4312 if (!netif_running(dev)) 4313 return -EINVAL; 4314 4315 switch (cmd) { 4316 case SIOCGMIIPHY: 4317 case SIOCGMIIREG: 4318 case SIOCSMIIREG: 4319 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4320 break; 4321 case SIOCSHWTSTAMP: 4322 ret = stmmac_hwtstamp_set(dev, rq); 4323 break; 4324 case SIOCGHWTSTAMP: 4325 ret = stmmac_hwtstamp_get(dev, rq); 4326 break; 4327 default: 4328 break; 4329 } 4330 4331 return ret; 4332 } 4333 4334 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4335 void *cb_priv) 4336 { 4337 struct stmmac_priv *priv = cb_priv; 4338 int ret = -EOPNOTSUPP; 4339 4340 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4341 return ret; 4342 4343 stmmac_disable_all_queues(priv); 4344 4345 switch (type) { 4346 case TC_SETUP_CLSU32: 4347 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4348 break; 4349 case TC_SETUP_CLSFLOWER: 4350 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4351 break; 4352 default: 4353 break; 4354 } 4355 4356 stmmac_enable_all_queues(priv); 4357 return ret; 4358 } 4359 4360 static LIST_HEAD(stmmac_block_cb_list); 4361 4362 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4363 void *type_data) 4364 { 4365 struct stmmac_priv *priv = netdev_priv(ndev); 4366 4367 switch (type) { 4368 case TC_SETUP_BLOCK: 4369 return flow_block_cb_setup_simple(type_data, 4370 &stmmac_block_cb_list, 4371 stmmac_setup_tc_block_cb, 4372 priv, priv, true); 4373 case TC_SETUP_QDISC_CBS: 4374 return stmmac_tc_setup_cbs(priv, priv, type_data); 4375 case TC_SETUP_QDISC_TAPRIO: 4376 return stmmac_tc_setup_taprio(priv, priv, type_data); 4377 case TC_SETUP_QDISC_ETF: 4378 return stmmac_tc_setup_etf(priv, priv, type_data); 4379 default: 4380 return -EOPNOTSUPP; 4381 } 4382 } 4383 4384 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4385 struct net_device *sb_dev) 4386 { 4387 int gso = skb_shinfo(skb)->gso_type; 4388 4389 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4390 /* 4391 * There is no way to determine the number of TSO/USO 4392 * capable Queues. Let's use always the Queue 0 4393 * because if TSO/USO is supported then at least this 4394 * one will be capable. 4395 */ 4396 return 0; 4397 } 4398 4399 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4400 } 4401 4402 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4403 { 4404 struct stmmac_priv *priv = netdev_priv(ndev); 4405 int ret = 0; 4406 4407 ret = eth_mac_addr(ndev, addr); 4408 if (ret) 4409 return ret; 4410 4411 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4412 4413 return ret; 4414 } 4415 4416 #ifdef CONFIG_DEBUG_FS 4417 static struct dentry *stmmac_fs_dir; 4418 4419 static void sysfs_display_ring(void *head, int size, int extend_desc, 4420 struct seq_file *seq, dma_addr_t dma_phy_addr) 4421 { 4422 int i; 4423 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4424 struct dma_desc *p = (struct dma_desc *)head; 4425 dma_addr_t dma_addr; 4426 4427 for (i = 0; i < size; i++) { 4428 if (extend_desc) { 4429 dma_addr = dma_phy_addr + i * sizeof(*ep); 4430 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 4431 i, &dma_addr, 4432 le32_to_cpu(ep->basic.des0), 4433 le32_to_cpu(ep->basic.des1), 4434 le32_to_cpu(ep->basic.des2), 4435 le32_to_cpu(ep->basic.des3)); 4436 ep++; 4437 } else { 4438 dma_addr = dma_phy_addr + i * sizeof(*p); 4439 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 4440 i, &dma_addr, 4441 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4442 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4443 p++; 4444 } 4445 seq_printf(seq, "\n"); 4446 } 4447 } 4448 4449 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4450 { 4451 struct net_device *dev = seq->private; 4452 struct stmmac_priv *priv = netdev_priv(dev); 4453 u32 rx_count = priv->plat->rx_queues_to_use; 4454 u32 tx_count = priv->plat->tx_queues_to_use; 4455 u32 queue; 4456 4457 if ((dev->flags & IFF_UP) == 0) 4458 return 0; 4459 4460 for (queue = 0; queue < rx_count; queue++) { 4461 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4462 4463 seq_printf(seq, "RX Queue %d:\n", queue); 4464 4465 if (priv->extend_desc) { 4466 seq_printf(seq, "Extended descriptor ring:\n"); 4467 sysfs_display_ring((void *)rx_q->dma_erx, 4468 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 4469 } else { 4470 seq_printf(seq, "Descriptor ring:\n"); 4471 sysfs_display_ring((void *)rx_q->dma_rx, 4472 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 4473 } 4474 } 4475 4476 for (queue = 0; queue < tx_count; queue++) { 4477 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4478 4479 seq_printf(seq, "TX Queue %d:\n", queue); 4480 4481 if (priv->extend_desc) { 4482 seq_printf(seq, "Extended descriptor ring:\n"); 4483 sysfs_display_ring((void *)tx_q->dma_etx, 4484 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 4485 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4486 seq_printf(seq, "Descriptor ring:\n"); 4487 sysfs_display_ring((void *)tx_q->dma_tx, 4488 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 4489 } 4490 } 4491 4492 return 0; 4493 } 4494 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4495 4496 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4497 { 4498 struct net_device *dev = seq->private; 4499 struct stmmac_priv *priv = netdev_priv(dev); 4500 4501 if (!priv->hw_cap_support) { 4502 seq_printf(seq, "DMA HW features not supported\n"); 4503 return 0; 4504 } 4505 4506 seq_printf(seq, "==============================\n"); 4507 seq_printf(seq, "\tDMA HW features\n"); 4508 seq_printf(seq, "==============================\n"); 4509 4510 seq_printf(seq, "\t10/100 Mbps: %s\n", 4511 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4512 seq_printf(seq, "\t1000 Mbps: %s\n", 4513 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4514 seq_printf(seq, "\tHalf duplex: %s\n", 4515 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4516 seq_printf(seq, "\tHash Filter: %s\n", 4517 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4518 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4519 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4520 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4521 (priv->dma_cap.pcs) ? "Y" : "N"); 4522 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4523 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4524 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4525 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4526 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4527 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4528 seq_printf(seq, "\tRMON module: %s\n", 4529 (priv->dma_cap.rmon) ? "Y" : "N"); 4530 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4531 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4532 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4533 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4534 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4535 (priv->dma_cap.eee) ? "Y" : "N"); 4536 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4537 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4538 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4539 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4540 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4541 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4542 } else { 4543 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4544 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4545 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4546 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4547 } 4548 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4549 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4550 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4551 priv->dma_cap.number_rx_channel); 4552 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4553 priv->dma_cap.number_tx_channel); 4554 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4555 priv->dma_cap.number_rx_queues); 4556 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4557 priv->dma_cap.number_tx_queues); 4558 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4559 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4560 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4561 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4562 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4563 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4564 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4565 priv->dma_cap.pps_out_num); 4566 seq_printf(seq, "\tSafety Features: %s\n", 4567 priv->dma_cap.asp ? "Y" : "N"); 4568 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4569 priv->dma_cap.frpsel ? "Y" : "N"); 4570 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4571 priv->dma_cap.addr64); 4572 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4573 priv->dma_cap.rssen ? "Y" : "N"); 4574 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4575 priv->dma_cap.vlhash ? "Y" : "N"); 4576 seq_printf(seq, "\tSplit Header: %s\n", 4577 priv->dma_cap.sphen ? "Y" : "N"); 4578 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4579 priv->dma_cap.vlins ? "Y" : "N"); 4580 seq_printf(seq, "\tDouble VLAN: %s\n", 4581 priv->dma_cap.dvlan ? "Y" : "N"); 4582 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4583 priv->dma_cap.l3l4fnum); 4584 seq_printf(seq, "\tARP Offloading: %s\n", 4585 priv->dma_cap.arpoffsel ? "Y" : "N"); 4586 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4587 priv->dma_cap.estsel ? "Y" : "N"); 4588 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4589 priv->dma_cap.fpesel ? "Y" : "N"); 4590 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4591 priv->dma_cap.tbssel ? "Y" : "N"); 4592 return 0; 4593 } 4594 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4595 4596 /* Use network device events to rename debugfs file entries. 4597 */ 4598 static int stmmac_device_event(struct notifier_block *unused, 4599 unsigned long event, void *ptr) 4600 { 4601 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4602 struct stmmac_priv *priv = netdev_priv(dev); 4603 4604 if (dev->netdev_ops != &stmmac_netdev_ops) 4605 goto done; 4606 4607 switch (event) { 4608 case NETDEV_CHANGENAME: 4609 if (priv->dbgfs_dir) 4610 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4611 priv->dbgfs_dir, 4612 stmmac_fs_dir, 4613 dev->name); 4614 break; 4615 } 4616 done: 4617 return NOTIFY_DONE; 4618 } 4619 4620 static struct notifier_block stmmac_notifier = { 4621 .notifier_call = stmmac_device_event, 4622 }; 4623 4624 static void stmmac_init_fs(struct net_device *dev) 4625 { 4626 struct stmmac_priv *priv = netdev_priv(dev); 4627 4628 rtnl_lock(); 4629 4630 /* Create per netdev entries */ 4631 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4632 4633 /* Entry to report DMA RX/TX rings */ 4634 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4635 &stmmac_rings_status_fops); 4636 4637 /* Entry to report the DMA HW features */ 4638 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4639 &stmmac_dma_cap_fops); 4640 4641 rtnl_unlock(); 4642 } 4643 4644 static void stmmac_exit_fs(struct net_device *dev) 4645 { 4646 struct stmmac_priv *priv = netdev_priv(dev); 4647 4648 debugfs_remove_recursive(priv->dbgfs_dir); 4649 } 4650 #endif /* CONFIG_DEBUG_FS */ 4651 4652 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4653 { 4654 unsigned char *data = (unsigned char *)&vid_le; 4655 unsigned char data_byte = 0; 4656 u32 crc = ~0x0; 4657 u32 temp = 0; 4658 int i, bits; 4659 4660 bits = get_bitmask_order(VLAN_VID_MASK); 4661 for (i = 0; i < bits; i++) { 4662 if ((i % 8) == 0) 4663 data_byte = data[i / 8]; 4664 4665 temp = ((crc & 1) ^ data_byte) & 1; 4666 crc >>= 1; 4667 data_byte >>= 1; 4668 4669 if (temp) 4670 crc ^= 0xedb88320; 4671 } 4672 4673 return crc; 4674 } 4675 4676 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4677 { 4678 u32 crc, hash = 0; 4679 __le16 pmatch = 0; 4680 int count = 0; 4681 u16 vid = 0; 4682 4683 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4684 __le16 vid_le = cpu_to_le16(vid); 4685 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4686 hash |= (1 << crc); 4687 count++; 4688 } 4689 4690 if (!priv->dma_cap.vlhash) { 4691 if (count > 2) /* VID = 0 always passes filter */ 4692 return -EOPNOTSUPP; 4693 4694 pmatch = cpu_to_le16(vid); 4695 hash = 0; 4696 } 4697 4698 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4699 } 4700 4701 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4702 { 4703 struct stmmac_priv *priv = netdev_priv(ndev); 4704 bool is_double = false; 4705 int ret; 4706 4707 if (be16_to_cpu(proto) == ETH_P_8021AD) 4708 is_double = true; 4709 4710 set_bit(vid, priv->active_vlans); 4711 ret = stmmac_vlan_update(priv, is_double); 4712 if (ret) { 4713 clear_bit(vid, priv->active_vlans); 4714 return ret; 4715 } 4716 4717 if (priv->hw->num_vlan) { 4718 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4719 if (ret) 4720 return ret; 4721 } 4722 4723 return 0; 4724 } 4725 4726 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4727 { 4728 struct stmmac_priv *priv = netdev_priv(ndev); 4729 bool is_double = false; 4730 int ret; 4731 4732 if (be16_to_cpu(proto) == ETH_P_8021AD) 4733 is_double = true; 4734 4735 clear_bit(vid, priv->active_vlans); 4736 4737 if (priv->hw->num_vlan) { 4738 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4739 if (ret) 4740 return ret; 4741 } 4742 4743 return stmmac_vlan_update(priv, is_double); 4744 } 4745 4746 static const struct net_device_ops stmmac_netdev_ops = { 4747 .ndo_open = stmmac_open, 4748 .ndo_start_xmit = stmmac_xmit, 4749 .ndo_stop = stmmac_release, 4750 .ndo_change_mtu = stmmac_change_mtu, 4751 .ndo_fix_features = stmmac_fix_features, 4752 .ndo_set_features = stmmac_set_features, 4753 .ndo_set_rx_mode = stmmac_set_rx_mode, 4754 .ndo_tx_timeout = stmmac_tx_timeout, 4755 .ndo_do_ioctl = stmmac_ioctl, 4756 .ndo_setup_tc = stmmac_setup_tc, 4757 .ndo_select_queue = stmmac_select_queue, 4758 #ifdef CONFIG_NET_POLL_CONTROLLER 4759 .ndo_poll_controller = stmmac_poll_controller, 4760 #endif 4761 .ndo_set_mac_address = stmmac_set_mac_address, 4762 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4763 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4764 }; 4765 4766 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4767 { 4768 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4769 return; 4770 if (test_bit(STMMAC_DOWN, &priv->state)) 4771 return; 4772 4773 netdev_err(priv->dev, "Reset adapter.\n"); 4774 4775 rtnl_lock(); 4776 netif_trans_update(priv->dev); 4777 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4778 usleep_range(1000, 2000); 4779 4780 set_bit(STMMAC_DOWN, &priv->state); 4781 dev_close(priv->dev); 4782 dev_open(priv->dev, NULL); 4783 clear_bit(STMMAC_DOWN, &priv->state); 4784 clear_bit(STMMAC_RESETING, &priv->state); 4785 rtnl_unlock(); 4786 } 4787 4788 static void stmmac_service_task(struct work_struct *work) 4789 { 4790 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4791 service_task); 4792 4793 stmmac_reset_subtask(priv); 4794 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4795 } 4796 4797 /** 4798 * stmmac_hw_init - Init the MAC device 4799 * @priv: driver private structure 4800 * Description: this function is to configure the MAC device according to 4801 * some platform parameters or the HW capability register. It prepares the 4802 * driver to use either ring or chain modes and to setup either enhanced or 4803 * normal descriptors. 4804 */ 4805 static int stmmac_hw_init(struct stmmac_priv *priv) 4806 { 4807 int ret; 4808 4809 /* dwmac-sun8i only work in chain mode */ 4810 if (priv->plat->has_sun8i) 4811 chain_mode = 1; 4812 priv->chain_mode = chain_mode; 4813 4814 /* Initialize HW Interface */ 4815 ret = stmmac_hwif_init(priv); 4816 if (ret) 4817 return ret; 4818 4819 /* Get the HW capability (new GMAC newer than 3.50a) */ 4820 priv->hw_cap_support = stmmac_get_hw_features(priv); 4821 if (priv->hw_cap_support) { 4822 dev_info(priv->device, "DMA HW capability register supported\n"); 4823 4824 /* We can override some gmac/dma configuration fields: e.g. 4825 * enh_desc, tx_coe (e.g. that are passed through the 4826 * platform) with the values from the HW capability 4827 * register (if supported). 4828 */ 4829 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4830 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4831 priv->hw->pmt = priv->plat->pmt; 4832 if (priv->dma_cap.hash_tb_sz) { 4833 priv->hw->multicast_filter_bins = 4834 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4835 priv->hw->mcast_bits_log2 = 4836 ilog2(priv->hw->multicast_filter_bins); 4837 } 4838 4839 /* TXCOE doesn't work in thresh DMA mode */ 4840 if (priv->plat->force_thresh_dma_mode) 4841 priv->plat->tx_coe = 0; 4842 else 4843 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4844 4845 /* In case of GMAC4 rx_coe is from HW cap register. */ 4846 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4847 4848 if (priv->dma_cap.rx_coe_type2) 4849 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4850 else if (priv->dma_cap.rx_coe_type1) 4851 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4852 4853 } else { 4854 dev_info(priv->device, "No HW DMA feature register supported\n"); 4855 } 4856 4857 if (priv->plat->rx_coe) { 4858 priv->hw->rx_csum = priv->plat->rx_coe; 4859 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4860 if (priv->synopsys_id < DWMAC_CORE_4_00) 4861 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4862 } 4863 if (priv->plat->tx_coe) 4864 dev_info(priv->device, "TX Checksum insertion supported\n"); 4865 4866 if (priv->plat->pmt) { 4867 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4868 device_set_wakeup_capable(priv->device, 1); 4869 } 4870 4871 if (priv->dma_cap.tsoen) 4872 dev_info(priv->device, "TSO supported\n"); 4873 4874 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 4875 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 4876 4877 /* Run HW quirks, if any */ 4878 if (priv->hwif_quirks) { 4879 ret = priv->hwif_quirks(priv); 4880 if (ret) 4881 return ret; 4882 } 4883 4884 /* Rx Watchdog is available in the COREs newer than the 3.40. 4885 * In some case, for example on bugged HW this feature 4886 * has to be disable and this can be done by passing the 4887 * riwt_off field from the platform. 4888 */ 4889 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4890 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4891 priv->use_riwt = 1; 4892 dev_info(priv->device, 4893 "Enable RX Mitigation via HW Watchdog Timer\n"); 4894 } 4895 4896 return 0; 4897 } 4898 4899 static void stmmac_napi_add(struct net_device *dev) 4900 { 4901 struct stmmac_priv *priv = netdev_priv(dev); 4902 u32 queue, maxq; 4903 4904 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4905 4906 for (queue = 0; queue < maxq; queue++) { 4907 struct stmmac_channel *ch = &priv->channel[queue]; 4908 4909 ch->priv_data = priv; 4910 ch->index = queue; 4911 spin_lock_init(&ch->lock); 4912 4913 if (queue < priv->plat->rx_queues_to_use) { 4914 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 4915 NAPI_POLL_WEIGHT); 4916 } 4917 if (queue < priv->plat->tx_queues_to_use) { 4918 netif_tx_napi_add(dev, &ch->tx_napi, 4919 stmmac_napi_poll_tx, 4920 NAPI_POLL_WEIGHT); 4921 } 4922 } 4923 } 4924 4925 static void stmmac_napi_del(struct net_device *dev) 4926 { 4927 struct stmmac_priv *priv = netdev_priv(dev); 4928 u32 queue, maxq; 4929 4930 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4931 4932 for (queue = 0; queue < maxq; queue++) { 4933 struct stmmac_channel *ch = &priv->channel[queue]; 4934 4935 if (queue < priv->plat->rx_queues_to_use) 4936 netif_napi_del(&ch->rx_napi); 4937 if (queue < priv->plat->tx_queues_to_use) 4938 netif_napi_del(&ch->tx_napi); 4939 } 4940 } 4941 4942 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 4943 { 4944 struct stmmac_priv *priv = netdev_priv(dev); 4945 int ret = 0; 4946 4947 if (netif_running(dev)) 4948 stmmac_release(dev); 4949 4950 stmmac_napi_del(dev); 4951 4952 priv->plat->rx_queues_to_use = rx_cnt; 4953 priv->plat->tx_queues_to_use = tx_cnt; 4954 4955 stmmac_napi_add(dev); 4956 4957 if (netif_running(dev)) 4958 ret = stmmac_open(dev); 4959 4960 return ret; 4961 } 4962 4963 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 4964 { 4965 struct stmmac_priv *priv = netdev_priv(dev); 4966 int ret = 0; 4967 4968 if (netif_running(dev)) 4969 stmmac_release(dev); 4970 4971 priv->dma_rx_size = rx_size; 4972 priv->dma_tx_size = tx_size; 4973 4974 if (netif_running(dev)) 4975 ret = stmmac_open(dev); 4976 4977 return ret; 4978 } 4979 4980 /** 4981 * stmmac_dvr_probe 4982 * @device: device pointer 4983 * @plat_dat: platform data pointer 4984 * @res: stmmac resource pointer 4985 * Description: this is the main probe function used to 4986 * call the alloc_etherdev, allocate the priv structure. 4987 * Return: 4988 * returns 0 on success, otherwise errno. 4989 */ 4990 int stmmac_dvr_probe(struct device *device, 4991 struct plat_stmmacenet_data *plat_dat, 4992 struct stmmac_resources *res) 4993 { 4994 struct net_device *ndev = NULL; 4995 struct stmmac_priv *priv; 4996 u32 rxq; 4997 int i, ret = 0; 4998 4999 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 5000 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 5001 if (!ndev) 5002 return -ENOMEM; 5003 5004 SET_NETDEV_DEV(ndev, device); 5005 5006 priv = netdev_priv(ndev); 5007 priv->device = device; 5008 priv->dev = ndev; 5009 5010 stmmac_set_ethtool_ops(ndev); 5011 priv->pause = pause; 5012 priv->plat = plat_dat; 5013 priv->ioaddr = res->addr; 5014 priv->dev->base_addr = (unsigned long)res->addr; 5015 5016 priv->dev->irq = res->irq; 5017 priv->wol_irq = res->wol_irq; 5018 priv->lpi_irq = res->lpi_irq; 5019 5020 if (!IS_ERR_OR_NULL(res->mac)) 5021 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 5022 5023 dev_set_drvdata(device, priv->dev); 5024 5025 /* Verify driver arguments */ 5026 stmmac_verify_args(); 5027 5028 /* Allocate workqueue */ 5029 priv->wq = create_singlethread_workqueue("stmmac_wq"); 5030 if (!priv->wq) { 5031 dev_err(priv->device, "failed to create workqueue\n"); 5032 return -ENOMEM; 5033 } 5034 5035 INIT_WORK(&priv->service_task, stmmac_service_task); 5036 5037 /* Override with kernel parameters if supplied XXX CRS XXX 5038 * this needs to have multiple instances 5039 */ 5040 if ((phyaddr >= 0) && (phyaddr <= 31)) 5041 priv->plat->phy_addr = phyaddr; 5042 5043 if (priv->plat->stmmac_rst) { 5044 ret = reset_control_assert(priv->plat->stmmac_rst); 5045 reset_control_deassert(priv->plat->stmmac_rst); 5046 /* Some reset controllers have only reset callback instead of 5047 * assert + deassert callbacks pair. 5048 */ 5049 if (ret == -ENOTSUPP) 5050 reset_control_reset(priv->plat->stmmac_rst); 5051 } 5052 5053 /* Init MAC and get the capabilities */ 5054 ret = stmmac_hw_init(priv); 5055 if (ret) 5056 goto error_hw_init; 5057 5058 stmmac_check_ether_addr(priv); 5059 5060 ndev->netdev_ops = &stmmac_netdev_ops; 5061 5062 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5063 NETIF_F_RXCSUM; 5064 5065 ret = stmmac_tc_init(priv, priv); 5066 if (!ret) { 5067 ndev->hw_features |= NETIF_F_HW_TC; 5068 } 5069 5070 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5071 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 5072 if (priv->plat->has_gmac4) 5073 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 5074 priv->tso = true; 5075 dev_info(priv->device, "TSO feature enabled\n"); 5076 } 5077 5078 if (priv->dma_cap.sphen) { 5079 ndev->hw_features |= NETIF_F_GRO; 5080 priv->sph = true; 5081 dev_info(priv->device, "SPH feature enabled\n"); 5082 } 5083 5084 /* The current IP register MAC_HW_Feature1[ADDR64] only define 5085 * 32/40/64 bit width, but some SOC support others like i.MX8MP 5086 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 5087 * So overwrite dma_cap.addr64 according to HW real design. 5088 */ 5089 if (priv->plat->addr64) 5090 priv->dma_cap.addr64 = priv->plat->addr64; 5091 5092 if (priv->dma_cap.addr64) { 5093 ret = dma_set_mask_and_coherent(device, 5094 DMA_BIT_MASK(priv->dma_cap.addr64)); 5095 if (!ret) { 5096 dev_info(priv->device, "Using %d bits DMA width\n", 5097 priv->dma_cap.addr64); 5098 5099 /* 5100 * If more than 32 bits can be addressed, make sure to 5101 * enable enhanced addressing mode. 5102 */ 5103 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 5104 priv->plat->dma_cfg->eame = true; 5105 } else { 5106 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 5107 if (ret) { 5108 dev_err(priv->device, "Failed to set DMA Mask\n"); 5109 goto error_hw_init; 5110 } 5111 5112 priv->dma_cap.addr64 = 32; 5113 } 5114 } 5115 5116 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 5117 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 5118 #ifdef STMMAC_VLAN_TAG_USED 5119 /* Both mac100 and gmac support receive VLAN tag detection */ 5120 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 5121 if (priv->dma_cap.vlhash) { 5122 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 5123 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 5124 } 5125 if (priv->dma_cap.vlins) { 5126 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 5127 if (priv->dma_cap.dvlan) 5128 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 5129 } 5130 #endif 5131 priv->msg_enable = netif_msg_init(debug, default_msg_level); 5132 5133 /* Initialize RSS */ 5134 rxq = priv->plat->rx_queues_to_use; 5135 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 5136 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 5137 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 5138 5139 if (priv->dma_cap.rssen && priv->plat->rss_en) 5140 ndev->features |= NETIF_F_RXHASH; 5141 5142 /* MTU range: 46 - hw-specific max */ 5143 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 5144 if (priv->plat->has_xgmac) 5145 ndev->max_mtu = XGMAC_JUMBO_LEN; 5146 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 5147 ndev->max_mtu = JUMBO_LEN; 5148 else 5149 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 5150 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 5151 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 5152 */ 5153 if ((priv->plat->maxmtu < ndev->max_mtu) && 5154 (priv->plat->maxmtu >= ndev->min_mtu)) 5155 ndev->max_mtu = priv->plat->maxmtu; 5156 else if (priv->plat->maxmtu < ndev->min_mtu) 5157 dev_warn(priv->device, 5158 "%s: warning: maxmtu having invalid value (%d)\n", 5159 __func__, priv->plat->maxmtu); 5160 5161 if (flow_ctrl) 5162 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 5163 5164 /* Setup channels NAPI */ 5165 stmmac_napi_add(ndev); 5166 5167 mutex_init(&priv->lock); 5168 5169 /* If a specific clk_csr value is passed from the platform 5170 * this means that the CSR Clock Range selection cannot be 5171 * changed at run-time and it is fixed. Viceversa the driver'll try to 5172 * set the MDC clock dynamically according to the csr actual 5173 * clock input. 5174 */ 5175 if (priv->plat->clk_csr >= 0) 5176 priv->clk_csr = priv->plat->clk_csr; 5177 else 5178 stmmac_clk_csr_set(priv); 5179 5180 stmmac_check_pcs_mode(priv); 5181 5182 if (priv->hw->pcs != STMMAC_PCS_TBI && 5183 priv->hw->pcs != STMMAC_PCS_RTBI) { 5184 /* MDIO bus Registration */ 5185 ret = stmmac_mdio_register(ndev); 5186 if (ret < 0) { 5187 dev_err(priv->device, 5188 "%s: MDIO bus (id: %d) registration failed", 5189 __func__, priv->plat->bus_id); 5190 goto error_mdio_register; 5191 } 5192 } 5193 5194 ret = stmmac_phy_setup(priv); 5195 if (ret) { 5196 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 5197 goto error_phy_setup; 5198 } 5199 5200 ret = register_netdev(ndev); 5201 if (ret) { 5202 dev_err(priv->device, "%s: ERROR %i registering the device\n", 5203 __func__, ret); 5204 goto error_netdev_register; 5205 } 5206 5207 if (priv->plat->serdes_powerup) { 5208 ret = priv->plat->serdes_powerup(ndev, 5209 priv->plat->bsp_priv); 5210 5211 if (ret < 0) 5212 goto error_serdes_powerup; 5213 } 5214 5215 #ifdef CONFIG_DEBUG_FS 5216 stmmac_init_fs(ndev); 5217 #endif 5218 5219 return ret; 5220 5221 error_serdes_powerup: 5222 unregister_netdev(ndev); 5223 error_netdev_register: 5224 phylink_destroy(priv->phylink); 5225 error_phy_setup: 5226 if (priv->hw->pcs != STMMAC_PCS_TBI && 5227 priv->hw->pcs != STMMAC_PCS_RTBI) 5228 stmmac_mdio_unregister(ndev); 5229 error_mdio_register: 5230 stmmac_napi_del(ndev); 5231 error_hw_init: 5232 destroy_workqueue(priv->wq); 5233 5234 return ret; 5235 } 5236 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5237 5238 /** 5239 * stmmac_dvr_remove 5240 * @dev: device pointer 5241 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5242 * changes the link status, releases the DMA descriptor rings. 5243 */ 5244 int stmmac_dvr_remove(struct device *dev) 5245 { 5246 struct net_device *ndev = dev_get_drvdata(dev); 5247 struct stmmac_priv *priv = netdev_priv(ndev); 5248 5249 netdev_info(priv->dev, "%s: removing driver", __func__); 5250 5251 stmmac_stop_all_dma(priv); 5252 stmmac_mac_set(priv, priv->ioaddr, false); 5253 netif_carrier_off(ndev); 5254 unregister_netdev(ndev); 5255 5256 /* Serdes power down needs to happen after VLAN filter 5257 * is deleted that is triggered by unregister_netdev(). 5258 */ 5259 if (priv->plat->serdes_powerdown) 5260 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5261 5262 #ifdef CONFIG_DEBUG_FS 5263 stmmac_exit_fs(ndev); 5264 #endif 5265 phylink_destroy(priv->phylink); 5266 if (priv->plat->stmmac_rst) 5267 reset_control_assert(priv->plat->stmmac_rst); 5268 clk_disable_unprepare(priv->plat->pclk); 5269 clk_disable_unprepare(priv->plat->stmmac_clk); 5270 if (priv->hw->pcs != STMMAC_PCS_TBI && 5271 priv->hw->pcs != STMMAC_PCS_RTBI) 5272 stmmac_mdio_unregister(ndev); 5273 destroy_workqueue(priv->wq); 5274 mutex_destroy(&priv->lock); 5275 5276 return 0; 5277 } 5278 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5279 5280 /** 5281 * stmmac_suspend - suspend callback 5282 * @dev: device pointer 5283 * Description: this is the function to suspend the device and it is called 5284 * by the platform driver to stop the network queue, release the resources, 5285 * program the PMT register (for WoL), clean and release driver resources. 5286 */ 5287 int stmmac_suspend(struct device *dev) 5288 { 5289 struct net_device *ndev = dev_get_drvdata(dev); 5290 struct stmmac_priv *priv = netdev_priv(ndev); 5291 u32 chan; 5292 5293 if (!ndev || !netif_running(ndev)) 5294 return 0; 5295 5296 phylink_mac_change(priv->phylink, false); 5297 5298 mutex_lock(&priv->lock); 5299 5300 netif_device_detach(ndev); 5301 5302 stmmac_disable_all_queues(priv); 5303 5304 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5305 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 5306 5307 if (priv->eee_enabled) { 5308 priv->tx_path_in_lpi_mode = false; 5309 del_timer_sync(&priv->eee_ctrl_timer); 5310 } 5311 5312 /* Stop TX/RX DMA */ 5313 stmmac_stop_all_dma(priv); 5314 5315 if (priv->plat->serdes_powerdown) 5316 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5317 5318 /* Enable Power down mode by programming the PMT regs */ 5319 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5320 stmmac_pmt(priv, priv->hw, priv->wolopts); 5321 priv->irq_wake = 1; 5322 } else { 5323 mutex_unlock(&priv->lock); 5324 rtnl_lock(); 5325 if (device_may_wakeup(priv->device)) 5326 phylink_speed_down(priv->phylink, false); 5327 phylink_stop(priv->phylink); 5328 rtnl_unlock(); 5329 mutex_lock(&priv->lock); 5330 5331 stmmac_mac_set(priv, priv->ioaddr, false); 5332 pinctrl_pm_select_sleep_state(priv->device); 5333 /* Disable clock in case of PWM is off */ 5334 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5335 clk_disable_unprepare(priv->plat->pclk); 5336 clk_disable_unprepare(priv->plat->stmmac_clk); 5337 } 5338 mutex_unlock(&priv->lock); 5339 5340 priv->speed = SPEED_UNKNOWN; 5341 return 0; 5342 } 5343 EXPORT_SYMBOL_GPL(stmmac_suspend); 5344 5345 /** 5346 * stmmac_reset_queues_param - reset queue parameters 5347 * @priv: device pointer 5348 */ 5349 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5350 { 5351 u32 rx_cnt = priv->plat->rx_queues_to_use; 5352 u32 tx_cnt = priv->plat->tx_queues_to_use; 5353 u32 queue; 5354 5355 for (queue = 0; queue < rx_cnt; queue++) { 5356 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5357 5358 rx_q->cur_rx = 0; 5359 rx_q->dirty_rx = 0; 5360 } 5361 5362 for (queue = 0; queue < tx_cnt; queue++) { 5363 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5364 5365 tx_q->cur_tx = 0; 5366 tx_q->dirty_tx = 0; 5367 tx_q->mss = 0; 5368 5369 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 5370 } 5371 } 5372 5373 /** 5374 * stmmac_resume - resume callback 5375 * @dev: device pointer 5376 * Description: when resume this function is invoked to setup the DMA and CORE 5377 * in a usable state. 5378 */ 5379 int stmmac_resume(struct device *dev) 5380 { 5381 struct net_device *ndev = dev_get_drvdata(dev); 5382 struct stmmac_priv *priv = netdev_priv(ndev); 5383 int ret; 5384 5385 if (!netif_running(ndev)) 5386 return 0; 5387 5388 /* Power Down bit, into the PM register, is cleared 5389 * automatically as soon as a magic packet or a Wake-up frame 5390 * is received. Anyway, it's better to manually clear 5391 * this bit because it can generate problems while resuming 5392 * from another devices (e.g. serial console). 5393 */ 5394 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5395 mutex_lock(&priv->lock); 5396 stmmac_pmt(priv, priv->hw, 0); 5397 mutex_unlock(&priv->lock); 5398 priv->irq_wake = 0; 5399 } else { 5400 pinctrl_pm_select_default_state(priv->device); 5401 /* enable the clk previously disabled */ 5402 clk_prepare_enable(priv->plat->stmmac_clk); 5403 clk_prepare_enable(priv->plat->pclk); 5404 if (priv->plat->clk_ptp_ref) 5405 clk_prepare_enable(priv->plat->clk_ptp_ref); 5406 /* reset the phy so that it's ready */ 5407 if (priv->mii) 5408 stmmac_mdio_reset(priv->mii); 5409 } 5410 5411 if (priv->plat->serdes_powerup) { 5412 ret = priv->plat->serdes_powerup(ndev, 5413 priv->plat->bsp_priv); 5414 5415 if (ret < 0) 5416 return ret; 5417 } 5418 5419 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 5420 rtnl_lock(); 5421 phylink_start(priv->phylink); 5422 /* We may have called phylink_speed_down before */ 5423 phylink_speed_up(priv->phylink); 5424 rtnl_unlock(); 5425 } 5426 5427 rtnl_lock(); 5428 mutex_lock(&priv->lock); 5429 5430 stmmac_reset_queues_param(priv); 5431 stmmac_reinit_rx_buffers(priv); 5432 stmmac_free_tx_skbufs(priv); 5433 stmmac_clear_descriptors(priv); 5434 5435 stmmac_hw_setup(ndev, false); 5436 stmmac_init_coalesce(priv); 5437 stmmac_set_rx_mode(ndev); 5438 5439 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5440 5441 stmmac_enable_all_queues(priv); 5442 5443 mutex_unlock(&priv->lock); 5444 rtnl_unlock(); 5445 5446 phylink_mac_change(priv->phylink, true); 5447 5448 netif_device_attach(ndev); 5449 5450 return 0; 5451 } 5452 EXPORT_SYMBOL_GPL(stmmac_resume); 5453 5454 #ifndef MODULE 5455 static int __init stmmac_cmdline_opt(char *str) 5456 { 5457 char *opt; 5458 5459 if (!str || !*str) 5460 return -EINVAL; 5461 while ((opt = strsep(&str, ",")) != NULL) { 5462 if (!strncmp(opt, "debug:", 6)) { 5463 if (kstrtoint(opt + 6, 0, &debug)) 5464 goto err; 5465 } else if (!strncmp(opt, "phyaddr:", 8)) { 5466 if (kstrtoint(opt + 8, 0, &phyaddr)) 5467 goto err; 5468 } else if (!strncmp(opt, "buf_sz:", 7)) { 5469 if (kstrtoint(opt + 7, 0, &buf_sz)) 5470 goto err; 5471 } else if (!strncmp(opt, "tc:", 3)) { 5472 if (kstrtoint(opt + 3, 0, &tc)) 5473 goto err; 5474 } else if (!strncmp(opt, "watchdog:", 9)) { 5475 if (kstrtoint(opt + 9, 0, &watchdog)) 5476 goto err; 5477 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5478 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5479 goto err; 5480 } else if (!strncmp(opt, "pause:", 6)) { 5481 if (kstrtoint(opt + 6, 0, &pause)) 5482 goto err; 5483 } else if (!strncmp(opt, "eee_timer:", 10)) { 5484 if (kstrtoint(opt + 10, 0, &eee_timer)) 5485 goto err; 5486 } else if (!strncmp(opt, "chain_mode:", 11)) { 5487 if (kstrtoint(opt + 11, 0, &chain_mode)) 5488 goto err; 5489 } 5490 } 5491 return 0; 5492 5493 err: 5494 pr_err("%s: ERROR broken module parameter conversion", __func__); 5495 return -EINVAL; 5496 } 5497 5498 __setup("stmmaceth=", stmmac_cmdline_opt); 5499 #endif /* MODULE */ 5500 5501 static int __init stmmac_init(void) 5502 { 5503 #ifdef CONFIG_DEBUG_FS 5504 /* Create debugfs main directory if it doesn't exist yet */ 5505 if (!stmmac_fs_dir) 5506 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5507 register_netdevice_notifier(&stmmac_notifier); 5508 #endif 5509 5510 return 0; 5511 } 5512 5513 static void __exit stmmac_exit(void) 5514 { 5515 #ifdef CONFIG_DEBUG_FS 5516 unregister_netdevice_notifier(&stmmac_notifier); 5517 debugfs_remove_recursive(stmmac_fs_dir); 5518 #endif 5519 } 5520 5521 module_init(stmmac_init) 5522 module_exit(stmmac_exit) 5523 5524 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5525 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5526 MODULE_LICENSE("GPL"); 5527