1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_STMMAC_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_STMMAC_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 57 58 /* Module parameters */ 59 #define TX_TIMEO 5000 60 static int watchdog = TX_TIMEO; 61 module_param(watchdog, int, S_IRUGO | S_IWUSR); 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 63 64 static int debug = -1; 65 module_param(debug, int, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 67 68 static int phyaddr = -1; 69 module_param(phyaddr, int, S_IRUGO); 70 MODULE_PARM_DESC(phyaddr, "Physical device address"); 71 72 #define DMA_TX_SIZE 256 73 static int dma_txsize = DMA_TX_SIZE; 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 76 77 #define DMA_RX_SIZE 256 78 static int dma_rxsize = DMA_RX_SIZE; 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 81 82 static int flow_ctrl = FLOW_OFF; 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 85 86 static int pause = PAUSE_TIME; 87 module_param(pause, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 89 90 #define TC_DEFAULT 64 91 static int tc = TC_DEFAULT; 92 module_param(tc, int, S_IRUGO | S_IWUSR); 93 MODULE_PARM_DESC(tc, "DMA threshold control value"); 94 95 #define DEFAULT_BUFSIZE 1536 96 static int buf_sz = DEFAULT_BUFSIZE; 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 99 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 101 NETIF_MSG_LINK | NETIF_MSG_IFUP | 102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 103 104 #define STMMAC_DEFAULT_LPI_TIMER 1000 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 109 110 /* By default the driver will use the ring mode to manage tx and rx descriptors 111 * but passing this value so user can force to use the chain instead of the ring 112 */ 113 static unsigned int chain_mode; 114 module_param(chain_mode, int, S_IRUGO); 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 116 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 118 119 #ifdef CONFIG_STMMAC_DEBUG_FS 120 static int stmmac_init_fs(struct net_device *dev); 121 static void stmmac_exit_fs(void); 122 #endif 123 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 125 126 /** 127 * stmmac_verify_args - verify the driver parameters. 128 * Description: it verifies if some wrong parameter is passed to the driver. 129 * Note that wrong parameters are replaced with the default values. 130 */ 131 static void stmmac_verify_args(void) 132 { 133 if (unlikely(watchdog < 0)) 134 watchdog = TX_TIMEO; 135 if (unlikely(dma_rxsize < 0)) 136 dma_rxsize = DMA_RX_SIZE; 137 if (unlikely(dma_txsize < 0)) 138 dma_txsize = DMA_TX_SIZE; 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 140 buf_sz = DEFAULT_BUFSIZE; 141 if (unlikely(flow_ctrl > 1)) 142 flow_ctrl = FLOW_AUTO; 143 else if (likely(flow_ctrl < 0)) 144 flow_ctrl = FLOW_OFF; 145 if (unlikely((pause < 0) || (pause > 0xffff))) 146 pause = PAUSE_TIME; 147 if (eee_timer < 0) 148 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 149 } 150 151 /** 152 * stmmac_clk_csr_set - dynamically set the MDC clock 153 * @priv: driver private structure 154 * Description: this is to dynamically set the MDC clock according to the csr 155 * clock input. 156 * Note: 157 * If a specific clk_csr value is passed from the platform 158 * this means that the CSR Clock Range selection cannot be 159 * changed at run-time and it is fixed (as reported in the driver 160 * documentation). Viceversa the driver will try to set the MDC 161 * clock dynamically according to the actual clock input. 162 */ 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 164 { 165 u32 clk_rate; 166 167 clk_rate = clk_get_rate(priv->stmmac_clk); 168 169 /* Platform provided default clk_csr would be assumed valid 170 * for all other cases except for the below mentioned ones. 171 * For values higher than the IEEE 802.3 specified frequency 172 * we can not estimate the proper divider as it is not known 173 * the frequency of clk_csr_i. So we do not change the default 174 * divider. 175 */ 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 177 if (clk_rate < CSR_F_35M) 178 priv->clk_csr = STMMAC_CSR_20_35M; 179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 180 priv->clk_csr = STMMAC_CSR_35_60M; 181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 182 priv->clk_csr = STMMAC_CSR_60_100M; 183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 184 priv->clk_csr = STMMAC_CSR_100_150M; 185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 186 priv->clk_csr = STMMAC_CSR_150_250M; 187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 188 priv->clk_csr = STMMAC_CSR_250_300M; 189 } 190 } 191 192 static void print_pkt(unsigned char *buf, int len) 193 { 194 int j; 195 pr_debug("len = %d byte, buf addr: 0x%p", len, buf); 196 for (j = 0; j < len; j++) { 197 if ((j % 16) == 0) 198 pr_debug("\n %03x:", j); 199 pr_debug(" %02x", buf[j]); 200 } 201 pr_debug("\n"); 202 } 203 204 /* minimum number of free TX descriptors required to wake up TX process */ 205 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 206 207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 208 { 209 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 210 } 211 212 /** 213 * stmmac_hw_fix_mac_speed: callback for speed selection 214 * @priv: driver private structure 215 * Description: on some platforms (e.g. ST), some HW system configuraton 216 * registers have to be set according to the link speed negotiated. 217 */ 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 219 { 220 struct phy_device *phydev = priv->phydev; 221 222 if (likely(priv->plat->fix_mac_speed)) 223 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 224 } 225 226 /** 227 * stmmac_enable_eee_mode: Check and enter in LPI mode 228 * @priv: driver private structure 229 * Description: this function is to verify and enter in LPI mode for EEE. 230 */ 231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 232 { 233 /* Check and enter in LPI mode */ 234 if ((priv->dirty_tx == priv->cur_tx) && 235 (priv->tx_path_in_lpi_mode == false)) 236 priv->hw->mac->set_eee_mode(priv->hw); 237 } 238 239 /** 240 * stmmac_disable_eee_mode: disable/exit from EEE 241 * @priv: driver private structure 242 * Description: this function is to exit and disable EEE in case of 243 * LPI state is true. This is called by the xmit. 244 */ 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 246 { 247 priv->hw->mac->reset_eee_mode(priv->hw); 248 del_timer_sync(&priv->eee_ctrl_timer); 249 priv->tx_path_in_lpi_mode = false; 250 } 251 252 /** 253 * stmmac_eee_ctrl_timer: EEE TX SW timer. 254 * @arg : data hook 255 * Description: 256 * if there is no data transfer and if we are not in LPI state, 257 * then MAC Transmitter can be moved to LPI state. 258 */ 259 static void stmmac_eee_ctrl_timer(unsigned long arg) 260 { 261 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 262 263 stmmac_enable_eee_mode(priv); 264 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 265 } 266 267 /** 268 * stmmac_eee_init: init EEE 269 * @priv: driver private structure 270 * Description: 271 * If the EEE support has been enabled while configuring the driver, 272 * if the GMAC actually supports the EEE (from the HW cap reg) and the 273 * phy can also manage EEE, so enable the LPI state and start the timer 274 * to verify if the tx path can enter in LPI state. 275 */ 276 bool stmmac_eee_init(struct stmmac_priv *priv) 277 { 278 bool ret = false; 279 280 /* Using PCS we cannot dial with the phy registers at this stage 281 * so we do not support extra feature like EEE. 282 */ 283 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 284 (priv->pcs == STMMAC_PCS_RTBI)) 285 goto out; 286 287 /* MAC core supports the EEE feature. */ 288 if (priv->dma_cap.eee) { 289 int tx_lpi_timer = priv->tx_lpi_timer; 290 291 /* Check if the PHY supports EEE */ 292 if (phy_init_eee(priv->phydev, 1)) { 293 /* To manage at run-time if the EEE cannot be supported 294 * anymore (for example because the lp caps have been 295 * changed). 296 * In that case the driver disable own timers. 297 */ 298 if (priv->eee_active) { 299 pr_debug("stmmac: disable EEE\n"); 300 del_timer_sync(&priv->eee_ctrl_timer); 301 priv->hw->mac->set_eee_timer(priv->hw, 0, 302 tx_lpi_timer); 303 } 304 priv->eee_active = 0; 305 goto out; 306 } 307 /* Activate the EEE and start timers */ 308 if (!priv->eee_active) { 309 priv->eee_active = 1; 310 init_timer(&priv->eee_ctrl_timer); 311 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 312 priv->eee_ctrl_timer.data = (unsigned long)priv; 313 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 314 add_timer(&priv->eee_ctrl_timer); 315 316 priv->hw->mac->set_eee_timer(priv->hw, 317 STMMAC_DEFAULT_LIT_LS, 318 tx_lpi_timer); 319 } else 320 /* Set HW EEE according to the speed */ 321 priv->hw->mac->set_eee_pls(priv->hw, 322 priv->phydev->link); 323 324 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 325 326 ret = true; 327 } 328 out: 329 return ret; 330 } 331 332 /* stmmac_get_tx_hwtstamp: get HW TX timestamps 333 * @priv: driver private structure 334 * @entry : descriptor index to be used. 335 * @skb : the socket buffer 336 * Description : 337 * This function will read timestamp from the descriptor & pass it to stack. 338 * and also perform some sanity checks. 339 */ 340 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 341 unsigned int entry, struct sk_buff *skb) 342 { 343 struct skb_shared_hwtstamps shhwtstamp; 344 u64 ns; 345 void *desc = NULL; 346 347 if (!priv->hwts_tx_en) 348 return; 349 350 /* exit if skb doesn't support hw tstamp */ 351 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 352 return; 353 354 if (priv->adv_ts) 355 desc = (priv->dma_etx + entry); 356 else 357 desc = (priv->dma_tx + entry); 358 359 /* check tx tstamp status */ 360 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 361 return; 362 363 /* get the valid tstamp */ 364 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 365 366 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 367 shhwtstamp.hwtstamp = ns_to_ktime(ns); 368 /* pass tstamp to stack */ 369 skb_tstamp_tx(skb, &shhwtstamp); 370 371 return; 372 } 373 374 /* stmmac_get_rx_hwtstamp: get HW RX timestamps 375 * @priv: driver private structure 376 * @entry : descriptor index to be used. 377 * @skb : the socket buffer 378 * Description : 379 * This function will read received packet's timestamp from the descriptor 380 * and pass it to stack. It also perform some sanity checks. 381 */ 382 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 383 unsigned int entry, struct sk_buff *skb) 384 { 385 struct skb_shared_hwtstamps *shhwtstamp = NULL; 386 u64 ns; 387 void *desc = NULL; 388 389 if (!priv->hwts_rx_en) 390 return; 391 392 if (priv->adv_ts) 393 desc = (priv->dma_erx + entry); 394 else 395 desc = (priv->dma_rx + entry); 396 397 /* exit if rx tstamp is not valid */ 398 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 399 return; 400 401 /* get valid tstamp */ 402 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 403 shhwtstamp = skb_hwtstamps(skb); 404 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 405 shhwtstamp->hwtstamp = ns_to_ktime(ns); 406 } 407 408 /** 409 * stmmac_hwtstamp_ioctl - control hardware timestamping. 410 * @dev: device pointer. 411 * @ifr: An IOCTL specefic structure, that can contain a pointer to 412 * a proprietary structure used to pass information to the driver. 413 * Description: 414 * This function configures the MAC to enable/disable both outgoing(TX) 415 * and incoming(RX) packets time stamping based on user input. 416 * Return Value: 417 * 0 on success and an appropriate -ve integer on failure. 418 */ 419 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 420 { 421 struct stmmac_priv *priv = netdev_priv(dev); 422 struct hwtstamp_config config; 423 struct timespec now; 424 u64 temp = 0; 425 u32 ptp_v2 = 0; 426 u32 tstamp_all = 0; 427 u32 ptp_over_ipv4_udp = 0; 428 u32 ptp_over_ipv6_udp = 0; 429 u32 ptp_over_ethernet = 0; 430 u32 snap_type_sel = 0; 431 u32 ts_master_en = 0; 432 u32 ts_event_en = 0; 433 u32 value = 0; 434 435 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 436 netdev_alert(priv->dev, "No support for HW time stamping\n"); 437 priv->hwts_tx_en = 0; 438 priv->hwts_rx_en = 0; 439 440 return -EOPNOTSUPP; 441 } 442 443 if (copy_from_user(&config, ifr->ifr_data, 444 sizeof(struct hwtstamp_config))) 445 return -EFAULT; 446 447 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 448 __func__, config.flags, config.tx_type, config.rx_filter); 449 450 /* reserved for future extensions */ 451 if (config.flags) 452 return -EINVAL; 453 454 if (config.tx_type != HWTSTAMP_TX_OFF && 455 config.tx_type != HWTSTAMP_TX_ON) 456 return -ERANGE; 457 458 if (priv->adv_ts) { 459 switch (config.rx_filter) { 460 case HWTSTAMP_FILTER_NONE: 461 /* time stamp no incoming packet at all */ 462 config.rx_filter = HWTSTAMP_FILTER_NONE; 463 break; 464 465 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 466 /* PTP v1, UDP, any kind of event packet */ 467 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 468 /* take time stamp for all event messages */ 469 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 470 471 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 472 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 473 break; 474 475 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 476 /* PTP v1, UDP, Sync packet */ 477 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 478 /* take time stamp for SYNC messages only */ 479 ts_event_en = PTP_TCR_TSEVNTENA; 480 481 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 482 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 483 break; 484 485 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 486 /* PTP v1, UDP, Delay_req packet */ 487 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 488 /* take time stamp for Delay_Req messages only */ 489 ts_master_en = PTP_TCR_TSMSTRENA; 490 ts_event_en = PTP_TCR_TSEVNTENA; 491 492 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 493 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 494 break; 495 496 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 497 /* PTP v2, UDP, any kind of event packet */ 498 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 499 ptp_v2 = PTP_TCR_TSVER2ENA; 500 /* take time stamp for all event messages */ 501 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 502 503 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 504 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 505 break; 506 507 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 508 /* PTP v2, UDP, Sync packet */ 509 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 510 ptp_v2 = PTP_TCR_TSVER2ENA; 511 /* take time stamp for SYNC messages only */ 512 ts_event_en = PTP_TCR_TSEVNTENA; 513 514 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 515 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 516 break; 517 518 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 519 /* PTP v2, UDP, Delay_req packet */ 520 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 521 ptp_v2 = PTP_TCR_TSVER2ENA; 522 /* take time stamp for Delay_Req messages only */ 523 ts_master_en = PTP_TCR_TSMSTRENA; 524 ts_event_en = PTP_TCR_TSEVNTENA; 525 526 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 527 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 528 break; 529 530 case HWTSTAMP_FILTER_PTP_V2_EVENT: 531 /* PTP v2/802.AS1 any layer, any kind of event packet */ 532 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 533 ptp_v2 = PTP_TCR_TSVER2ENA; 534 /* take time stamp for all event messages */ 535 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 536 537 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 538 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 539 ptp_over_ethernet = PTP_TCR_TSIPENA; 540 break; 541 542 case HWTSTAMP_FILTER_PTP_V2_SYNC: 543 /* PTP v2/802.AS1, any layer, Sync packet */ 544 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 545 ptp_v2 = PTP_TCR_TSVER2ENA; 546 /* take time stamp for SYNC messages only */ 547 ts_event_en = PTP_TCR_TSEVNTENA; 548 549 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 550 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 551 ptp_over_ethernet = PTP_TCR_TSIPENA; 552 break; 553 554 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 555 /* PTP v2/802.AS1, any layer, Delay_req packet */ 556 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 557 ptp_v2 = PTP_TCR_TSVER2ENA; 558 /* take time stamp for Delay_Req messages only */ 559 ts_master_en = PTP_TCR_TSMSTRENA; 560 ts_event_en = PTP_TCR_TSEVNTENA; 561 562 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 563 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 564 ptp_over_ethernet = PTP_TCR_TSIPENA; 565 break; 566 567 case HWTSTAMP_FILTER_ALL: 568 /* time stamp any incoming packet */ 569 config.rx_filter = HWTSTAMP_FILTER_ALL; 570 tstamp_all = PTP_TCR_TSENALL; 571 break; 572 573 default: 574 return -ERANGE; 575 } 576 } else { 577 switch (config.rx_filter) { 578 case HWTSTAMP_FILTER_NONE: 579 config.rx_filter = HWTSTAMP_FILTER_NONE; 580 break; 581 default: 582 /* PTP v1, UDP, any kind of event packet */ 583 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 584 break; 585 } 586 } 587 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 588 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 589 590 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 591 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 592 else { 593 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 594 tstamp_all | ptp_v2 | ptp_over_ethernet | 595 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 596 ts_master_en | snap_type_sel); 597 598 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 599 600 /* program Sub Second Increment reg */ 601 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 602 603 /* calculate default added value: 604 * formula is : 605 * addend = (2^32)/freq_div_ratio; 606 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz 607 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK; 608 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to 609 * achive 20ns accuracy. 610 * 611 * 2^x * y == (y << x), hence 612 * 2^32 * 50000000 ==> (50000000 << 32) 613 */ 614 temp = (u64) (50000000ULL << 32); 615 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK); 616 priv->hw->ptp->config_addend(priv->ioaddr, 617 priv->default_addend); 618 619 /* initialize system time */ 620 getnstimeofday(&now); 621 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 622 now.tv_nsec); 623 } 624 625 return copy_to_user(ifr->ifr_data, &config, 626 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 627 } 628 629 /** 630 * stmmac_init_ptp: init PTP 631 * @priv: driver private structure 632 * Description: this is to verify if the HW supports the PTPv1 or v2. 633 * This is done by looking at the HW cap. register. 634 * Also it registers the ptp driver. 635 */ 636 static int stmmac_init_ptp(struct stmmac_priv *priv) 637 { 638 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 639 return -EOPNOTSUPP; 640 641 priv->adv_ts = 0; 642 if (priv->dma_cap.atime_stamp && priv->extend_desc) 643 priv->adv_ts = 1; 644 645 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 646 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 647 648 if (netif_msg_hw(priv) && priv->adv_ts) 649 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 650 651 priv->hw->ptp = &stmmac_ptp; 652 priv->hwts_tx_en = 0; 653 priv->hwts_rx_en = 0; 654 655 return stmmac_ptp_register(priv); 656 } 657 658 static void stmmac_release_ptp(struct stmmac_priv *priv) 659 { 660 stmmac_ptp_unregister(priv); 661 } 662 663 /** 664 * stmmac_adjust_link 665 * @dev: net device structure 666 * Description: it adjusts the link parameters. 667 */ 668 static void stmmac_adjust_link(struct net_device *dev) 669 { 670 struct stmmac_priv *priv = netdev_priv(dev); 671 struct phy_device *phydev = priv->phydev; 672 unsigned long flags; 673 int new_state = 0; 674 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 675 676 if (phydev == NULL) 677 return; 678 679 spin_lock_irqsave(&priv->lock, flags); 680 681 if (phydev->link) { 682 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 683 684 /* Now we make sure that we can be in full duplex mode. 685 * If not, we operate in half-duplex mode. */ 686 if (phydev->duplex != priv->oldduplex) { 687 new_state = 1; 688 if (!(phydev->duplex)) 689 ctrl &= ~priv->hw->link.duplex; 690 else 691 ctrl |= priv->hw->link.duplex; 692 priv->oldduplex = phydev->duplex; 693 } 694 /* Flow Control operation */ 695 if (phydev->pause) 696 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 697 fc, pause_time); 698 699 if (phydev->speed != priv->speed) { 700 new_state = 1; 701 switch (phydev->speed) { 702 case 1000: 703 if (likely(priv->plat->has_gmac)) 704 ctrl &= ~priv->hw->link.port; 705 stmmac_hw_fix_mac_speed(priv); 706 break; 707 case 100: 708 case 10: 709 if (priv->plat->has_gmac) { 710 ctrl |= priv->hw->link.port; 711 if (phydev->speed == SPEED_100) { 712 ctrl |= priv->hw->link.speed; 713 } else { 714 ctrl &= ~(priv->hw->link.speed); 715 } 716 } else { 717 ctrl &= ~priv->hw->link.port; 718 } 719 stmmac_hw_fix_mac_speed(priv); 720 break; 721 default: 722 if (netif_msg_link(priv)) 723 pr_warn("%s: Speed (%d) not 10/100\n", 724 dev->name, phydev->speed); 725 break; 726 } 727 728 priv->speed = phydev->speed; 729 } 730 731 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 732 733 if (!priv->oldlink) { 734 new_state = 1; 735 priv->oldlink = 1; 736 } 737 } else if (priv->oldlink) { 738 new_state = 1; 739 priv->oldlink = 0; 740 priv->speed = 0; 741 priv->oldduplex = -1; 742 } 743 744 if (new_state && netif_msg_link(priv)) 745 phy_print_status(phydev); 746 747 /* At this stage, it could be needed to setup the EEE or adjust some 748 * MAC related HW registers. 749 */ 750 priv->eee_enabled = stmmac_eee_init(priv); 751 752 spin_unlock_irqrestore(&priv->lock, flags); 753 } 754 755 /** 756 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported 757 * @priv: driver private structure 758 * Description: this is to verify if the HW supports the PCS. 759 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 760 * configured for the TBI, RTBI, or SGMII PHY interface. 761 */ 762 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 763 { 764 int interface = priv->plat->interface; 765 766 if (priv->dma_cap.pcs) { 767 if ((interface == PHY_INTERFACE_MODE_RGMII) || 768 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 769 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 770 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 771 pr_debug("STMMAC: PCS RGMII support enable\n"); 772 priv->pcs = STMMAC_PCS_RGMII; 773 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 774 pr_debug("STMMAC: PCS SGMII support enable\n"); 775 priv->pcs = STMMAC_PCS_SGMII; 776 } 777 } 778 } 779 780 /** 781 * stmmac_init_phy - PHY initialization 782 * @dev: net device structure 783 * Description: it initializes the driver's PHY state, and attaches the PHY 784 * to the mac driver. 785 * Return value: 786 * 0 on success 787 */ 788 static int stmmac_init_phy(struct net_device *dev) 789 { 790 struct stmmac_priv *priv = netdev_priv(dev); 791 struct phy_device *phydev; 792 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 793 char bus_id[MII_BUS_ID_SIZE]; 794 int interface = priv->plat->interface; 795 int max_speed = priv->plat->max_speed; 796 priv->oldlink = 0; 797 priv->speed = 0; 798 priv->oldduplex = -1; 799 800 if (priv->plat->phy_bus_name) 801 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 802 priv->plat->phy_bus_name, priv->plat->bus_id); 803 else 804 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 805 priv->plat->bus_id); 806 807 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 808 priv->plat->phy_addr); 809 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 810 811 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 812 813 if (IS_ERR(phydev)) { 814 pr_err("%s: Could not attach to PHY\n", dev->name); 815 return PTR_ERR(phydev); 816 } 817 818 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 819 if ((interface == PHY_INTERFACE_MODE_MII) || 820 (interface == PHY_INTERFACE_MODE_RMII) || 821 (max_speed < 1000 && max_speed > 0)) 822 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 823 SUPPORTED_1000baseT_Full); 824 825 /* 826 * Broken HW is sometimes missing the pull-up resistor on the 827 * MDIO line, which results in reads to non-existent devices returning 828 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 829 * device as well. 830 * Note: phydev->phy_id is the result of reading the UID PHY registers. 831 */ 832 if (phydev->phy_id == 0) { 833 phy_disconnect(phydev); 834 return -ENODEV; 835 } 836 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 837 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 838 839 priv->phydev = phydev; 840 841 return 0; 842 } 843 844 /** 845 * stmmac_display_ring: display ring 846 * @head: pointer to the head of the ring passed. 847 * @size: size of the ring. 848 * @extend_desc: to verify if extended descriptors are used. 849 * Description: display the control/status and buffer descriptors. 850 */ 851 static void stmmac_display_ring(void *head, int size, int extend_desc) 852 { 853 int i; 854 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 855 struct dma_desc *p = (struct dma_desc *)head; 856 857 for (i = 0; i < size; i++) { 858 u64 x; 859 if (extend_desc) { 860 x = *(u64 *) ep; 861 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 862 i, (unsigned int)virt_to_phys(ep), 863 (unsigned int)x, (unsigned int)(x >> 32), 864 ep->basic.des2, ep->basic.des3); 865 ep++; 866 } else { 867 x = *(u64 *) p; 868 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 869 i, (unsigned int)virt_to_phys(p), 870 (unsigned int)x, (unsigned int)(x >> 32), 871 p->des2, p->des3); 872 p++; 873 } 874 pr_info("\n"); 875 } 876 } 877 878 static void stmmac_display_rings(struct stmmac_priv *priv) 879 { 880 unsigned int txsize = priv->dma_tx_size; 881 unsigned int rxsize = priv->dma_rx_size; 882 883 if (priv->extend_desc) { 884 pr_info("Extended RX descriptor ring:\n"); 885 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 886 pr_info("Extended TX descriptor ring:\n"); 887 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 888 } else { 889 pr_info("RX descriptor ring:\n"); 890 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 891 pr_info("TX descriptor ring:\n"); 892 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 893 } 894 } 895 896 static int stmmac_set_bfsize(int mtu, int bufsize) 897 { 898 int ret = bufsize; 899 900 if (mtu >= BUF_SIZE_4KiB) 901 ret = BUF_SIZE_8KiB; 902 else if (mtu >= BUF_SIZE_2KiB) 903 ret = BUF_SIZE_4KiB; 904 else if (mtu > DEFAULT_BUFSIZE) 905 ret = BUF_SIZE_2KiB; 906 else 907 ret = DEFAULT_BUFSIZE; 908 909 return ret; 910 } 911 912 /** 913 * stmmac_clear_descriptors: clear descriptors 914 * @priv: driver private structure 915 * Description: this function is called to clear the tx and rx descriptors 916 * in case of both basic and extended descriptors are used. 917 */ 918 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 919 { 920 int i; 921 unsigned int txsize = priv->dma_tx_size; 922 unsigned int rxsize = priv->dma_rx_size; 923 924 /* Clear the Rx/Tx descriptors */ 925 for (i = 0; i < rxsize; i++) 926 if (priv->extend_desc) 927 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 928 priv->use_riwt, priv->mode, 929 (i == rxsize - 1)); 930 else 931 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 932 priv->use_riwt, priv->mode, 933 (i == rxsize - 1)); 934 for (i = 0; i < txsize; i++) 935 if (priv->extend_desc) 936 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 937 priv->mode, 938 (i == txsize - 1)); 939 else 940 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 941 priv->mode, 942 (i == txsize - 1)); 943 } 944 945 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 946 int i) 947 { 948 struct sk_buff *skb; 949 950 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 951 GFP_KERNEL); 952 if (!skb) { 953 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 954 return -ENOMEM; 955 } 956 skb_reserve(skb, NET_IP_ALIGN); 957 priv->rx_skbuff[i] = skb; 958 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 959 priv->dma_buf_sz, 960 DMA_FROM_DEVICE); 961 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 962 pr_err("%s: DMA mapping error\n", __func__); 963 dev_kfree_skb_any(skb); 964 return -EINVAL; 965 } 966 967 p->des2 = priv->rx_skbuff_dma[i]; 968 969 if ((priv->hw->mode->init_desc3) && 970 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 971 priv->hw->mode->init_desc3(p); 972 973 return 0; 974 } 975 976 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 977 { 978 if (priv->rx_skbuff[i]) { 979 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 980 priv->dma_buf_sz, DMA_FROM_DEVICE); 981 dev_kfree_skb_any(priv->rx_skbuff[i]); 982 } 983 priv->rx_skbuff[i] = NULL; 984 } 985 986 /** 987 * init_dma_desc_rings - init the RX/TX descriptor rings 988 * @dev: net device structure 989 * Description: this function initializes the DMA RX/TX descriptors 990 * and allocates the socket buffers. It suppors the chained and ring 991 * modes. 992 */ 993 static int init_dma_desc_rings(struct net_device *dev) 994 { 995 int i; 996 struct stmmac_priv *priv = netdev_priv(dev); 997 unsigned int txsize = priv->dma_tx_size; 998 unsigned int rxsize = priv->dma_rx_size; 999 unsigned int bfsize = 0; 1000 int ret = -ENOMEM; 1001 1002 if (priv->hw->mode->set_16kib_bfsize) 1003 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1004 1005 if (bfsize < BUF_SIZE_16KiB) 1006 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1007 1008 priv->dma_buf_sz = bfsize; 1009 1010 if (netif_msg_probe(priv)) 1011 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1012 txsize, rxsize, bfsize); 1013 1014 if (netif_msg_probe(priv)) { 1015 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1016 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1017 1018 /* RX INITIALIZATION */ 1019 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1020 } 1021 for (i = 0; i < rxsize; i++) { 1022 struct dma_desc *p; 1023 if (priv->extend_desc) 1024 p = &((priv->dma_erx + i)->basic); 1025 else 1026 p = priv->dma_rx + i; 1027 1028 ret = stmmac_init_rx_buffers(priv, p, i); 1029 if (ret) 1030 goto err_init_rx_buffers; 1031 1032 if (netif_msg_probe(priv)) 1033 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1034 priv->rx_skbuff[i]->data, 1035 (unsigned int)priv->rx_skbuff_dma[i]); 1036 } 1037 priv->cur_rx = 0; 1038 priv->dirty_rx = (unsigned int)(i - rxsize); 1039 buf_sz = bfsize; 1040 1041 /* Setup the chained descriptor addresses */ 1042 if (priv->mode == STMMAC_CHAIN_MODE) { 1043 if (priv->extend_desc) { 1044 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1045 rxsize, 1); 1046 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1047 txsize, 1); 1048 } else { 1049 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1050 rxsize, 0); 1051 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1052 txsize, 0); 1053 } 1054 } 1055 1056 /* TX INITIALIZATION */ 1057 for (i = 0; i < txsize; i++) { 1058 struct dma_desc *p; 1059 if (priv->extend_desc) 1060 p = &((priv->dma_etx + i)->basic); 1061 else 1062 p = priv->dma_tx + i; 1063 p->des2 = 0; 1064 priv->tx_skbuff_dma[i] = 0; 1065 priv->tx_skbuff[i] = NULL; 1066 } 1067 1068 priv->dirty_tx = 0; 1069 priv->cur_tx = 0; 1070 1071 stmmac_clear_descriptors(priv); 1072 1073 if (netif_msg_hw(priv)) 1074 stmmac_display_rings(priv); 1075 1076 return 0; 1077 err_init_rx_buffers: 1078 while (--i >= 0) 1079 stmmac_free_rx_buffers(priv, i); 1080 return ret; 1081 } 1082 1083 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1084 { 1085 int i; 1086 1087 for (i = 0; i < priv->dma_rx_size; i++) 1088 stmmac_free_rx_buffers(priv, i); 1089 } 1090 1091 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1092 { 1093 int i; 1094 1095 for (i = 0; i < priv->dma_tx_size; i++) { 1096 struct dma_desc *p; 1097 1098 if (priv->extend_desc) 1099 p = &((priv->dma_etx + i)->basic); 1100 else 1101 p = priv->dma_tx + i; 1102 1103 if (priv->tx_skbuff_dma[i]) { 1104 dma_unmap_single(priv->device, 1105 priv->tx_skbuff_dma[i], 1106 priv->hw->desc->get_tx_len(p), 1107 DMA_TO_DEVICE); 1108 priv->tx_skbuff_dma[i] = 0; 1109 } 1110 1111 if (priv->tx_skbuff[i] != NULL) { 1112 dev_kfree_skb_any(priv->tx_skbuff[i]); 1113 priv->tx_skbuff[i] = NULL; 1114 } 1115 } 1116 } 1117 1118 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1119 { 1120 unsigned int txsize = priv->dma_tx_size; 1121 unsigned int rxsize = priv->dma_rx_size; 1122 int ret = -ENOMEM; 1123 1124 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1125 GFP_KERNEL); 1126 if (!priv->rx_skbuff_dma) 1127 return -ENOMEM; 1128 1129 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1130 GFP_KERNEL); 1131 if (!priv->rx_skbuff) 1132 goto err_rx_skbuff; 1133 1134 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t), 1135 GFP_KERNEL); 1136 if (!priv->tx_skbuff_dma) 1137 goto err_tx_skbuff_dma; 1138 1139 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1140 GFP_KERNEL); 1141 if (!priv->tx_skbuff) 1142 goto err_tx_skbuff; 1143 1144 if (priv->extend_desc) { 1145 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1146 sizeof(struct 1147 dma_extended_desc), 1148 &priv->dma_rx_phy, 1149 GFP_KERNEL); 1150 if (!priv->dma_erx) 1151 goto err_dma; 1152 1153 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1154 sizeof(struct 1155 dma_extended_desc), 1156 &priv->dma_tx_phy, 1157 GFP_KERNEL); 1158 if (!priv->dma_etx) { 1159 dma_free_coherent(priv->device, priv->dma_rx_size * 1160 sizeof(struct dma_extended_desc), 1161 priv->dma_erx, priv->dma_rx_phy); 1162 goto err_dma; 1163 } 1164 } else { 1165 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1166 sizeof(struct dma_desc), 1167 &priv->dma_rx_phy, 1168 GFP_KERNEL); 1169 if (!priv->dma_rx) 1170 goto err_dma; 1171 1172 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1173 sizeof(struct dma_desc), 1174 &priv->dma_tx_phy, 1175 GFP_KERNEL); 1176 if (!priv->dma_tx) { 1177 dma_free_coherent(priv->device, priv->dma_rx_size * 1178 sizeof(struct dma_desc), 1179 priv->dma_rx, priv->dma_rx_phy); 1180 goto err_dma; 1181 } 1182 } 1183 1184 return 0; 1185 1186 err_dma: 1187 kfree(priv->tx_skbuff); 1188 err_tx_skbuff: 1189 kfree(priv->tx_skbuff_dma); 1190 err_tx_skbuff_dma: 1191 kfree(priv->rx_skbuff); 1192 err_rx_skbuff: 1193 kfree(priv->rx_skbuff_dma); 1194 return ret; 1195 } 1196 1197 static void free_dma_desc_resources(struct stmmac_priv *priv) 1198 { 1199 /* Release the DMA TX/RX socket buffers */ 1200 dma_free_rx_skbufs(priv); 1201 dma_free_tx_skbufs(priv); 1202 1203 /* Free DMA regions of consistent memory previously allocated */ 1204 if (!priv->extend_desc) { 1205 dma_free_coherent(priv->device, 1206 priv->dma_tx_size * sizeof(struct dma_desc), 1207 priv->dma_tx, priv->dma_tx_phy); 1208 dma_free_coherent(priv->device, 1209 priv->dma_rx_size * sizeof(struct dma_desc), 1210 priv->dma_rx, priv->dma_rx_phy); 1211 } else { 1212 dma_free_coherent(priv->device, priv->dma_tx_size * 1213 sizeof(struct dma_extended_desc), 1214 priv->dma_etx, priv->dma_tx_phy); 1215 dma_free_coherent(priv->device, priv->dma_rx_size * 1216 sizeof(struct dma_extended_desc), 1217 priv->dma_erx, priv->dma_rx_phy); 1218 } 1219 kfree(priv->rx_skbuff_dma); 1220 kfree(priv->rx_skbuff); 1221 kfree(priv->tx_skbuff_dma); 1222 kfree(priv->tx_skbuff); 1223 } 1224 1225 /** 1226 * stmmac_dma_operation_mode - HW DMA operation mode 1227 * @priv: driver private structure 1228 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 1229 * or Store-And-Forward capability. 1230 */ 1231 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1232 { 1233 if (priv->plat->force_thresh_dma_mode) 1234 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1235 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1236 /* 1237 * In case of GMAC, SF mode can be enabled 1238 * to perform the TX COE in HW. This depends on: 1239 * 1) TX COE if actually supported 1240 * 2) There is no bugged Jumbo frame support 1241 * that needs to not insert csum in the TDES. 1242 */ 1243 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1244 tc = SF_DMA_MODE; 1245 } else 1246 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1247 } 1248 1249 /** 1250 * stmmac_tx_clean: 1251 * @priv: driver private structure 1252 * Description: it reclaims resources after transmission completes. 1253 */ 1254 static void stmmac_tx_clean(struct stmmac_priv *priv) 1255 { 1256 unsigned int txsize = priv->dma_tx_size; 1257 1258 spin_lock(&priv->tx_lock); 1259 1260 priv->xstats.tx_clean++; 1261 1262 while (priv->dirty_tx != priv->cur_tx) { 1263 int last; 1264 unsigned int entry = priv->dirty_tx % txsize; 1265 struct sk_buff *skb = priv->tx_skbuff[entry]; 1266 struct dma_desc *p; 1267 1268 if (priv->extend_desc) 1269 p = (struct dma_desc *)(priv->dma_etx + entry); 1270 else 1271 p = priv->dma_tx + entry; 1272 1273 /* Check if the descriptor is owned by the DMA. */ 1274 if (priv->hw->desc->get_tx_owner(p)) 1275 break; 1276 1277 /* Verify tx error by looking at the last segment. */ 1278 last = priv->hw->desc->get_tx_ls(p); 1279 if (likely(last)) { 1280 int tx_error = 1281 priv->hw->desc->tx_status(&priv->dev->stats, 1282 &priv->xstats, p, 1283 priv->ioaddr); 1284 if (likely(tx_error == 0)) { 1285 priv->dev->stats.tx_packets++; 1286 priv->xstats.tx_pkt_n++; 1287 } else 1288 priv->dev->stats.tx_errors++; 1289 1290 stmmac_get_tx_hwtstamp(priv, entry, skb); 1291 } 1292 if (netif_msg_tx_done(priv)) 1293 pr_debug("%s: curr %d, dirty %d\n", __func__, 1294 priv->cur_tx, priv->dirty_tx); 1295 1296 if (likely(priv->tx_skbuff_dma[entry])) { 1297 dma_unmap_single(priv->device, 1298 priv->tx_skbuff_dma[entry], 1299 priv->hw->desc->get_tx_len(p), 1300 DMA_TO_DEVICE); 1301 priv->tx_skbuff_dma[entry] = 0; 1302 } 1303 priv->hw->mode->clean_desc3(priv, p); 1304 1305 if (likely(skb != NULL)) { 1306 dev_consume_skb_any(skb); 1307 priv->tx_skbuff[entry] = NULL; 1308 } 1309 1310 priv->hw->desc->release_tx_desc(p, priv->mode); 1311 1312 priv->dirty_tx++; 1313 } 1314 if (unlikely(netif_queue_stopped(priv->dev) && 1315 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1316 netif_tx_lock(priv->dev); 1317 if (netif_queue_stopped(priv->dev) && 1318 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1319 if (netif_msg_tx_done(priv)) 1320 pr_debug("%s: restart transmit\n", __func__); 1321 netif_wake_queue(priv->dev); 1322 } 1323 netif_tx_unlock(priv->dev); 1324 } 1325 1326 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1327 stmmac_enable_eee_mode(priv); 1328 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1329 } 1330 spin_unlock(&priv->tx_lock); 1331 } 1332 1333 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1334 { 1335 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1336 } 1337 1338 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1339 { 1340 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1341 } 1342 1343 /** 1344 * stmmac_tx_err: irq tx error mng function 1345 * @priv: driver private structure 1346 * Description: it cleans the descriptors and restarts the transmission 1347 * in case of errors. 1348 */ 1349 static void stmmac_tx_err(struct stmmac_priv *priv) 1350 { 1351 int i; 1352 int txsize = priv->dma_tx_size; 1353 netif_stop_queue(priv->dev); 1354 1355 priv->hw->dma->stop_tx(priv->ioaddr); 1356 dma_free_tx_skbufs(priv); 1357 for (i = 0; i < txsize; i++) 1358 if (priv->extend_desc) 1359 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1360 priv->mode, 1361 (i == txsize - 1)); 1362 else 1363 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1364 priv->mode, 1365 (i == txsize - 1)); 1366 priv->dirty_tx = 0; 1367 priv->cur_tx = 0; 1368 priv->hw->dma->start_tx(priv->ioaddr); 1369 1370 priv->dev->stats.tx_errors++; 1371 netif_wake_queue(priv->dev); 1372 } 1373 1374 /** 1375 * stmmac_dma_interrupt: DMA ISR 1376 * @priv: driver private structure 1377 * Description: this is the DMA ISR. It is called by the main ISR. 1378 * It calls the dwmac dma routine to understand which type of interrupt 1379 * happened. In case of there is a Normal interrupt and either TX or RX 1380 * interrupt happened so the NAPI is scheduled. 1381 */ 1382 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1383 { 1384 int status; 1385 1386 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1387 if (likely((status & handle_rx)) || (status & handle_tx)) { 1388 if (likely(napi_schedule_prep(&priv->napi))) { 1389 stmmac_disable_dma_irq(priv); 1390 __napi_schedule(&priv->napi); 1391 } 1392 } 1393 if (unlikely(status & tx_hard_error_bump_tc)) { 1394 /* Try to bump up the dma threshold on this failure */ 1395 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1396 tc += 64; 1397 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1398 priv->xstats.threshold = tc; 1399 } 1400 } else if (unlikely(status == tx_hard_error)) 1401 stmmac_tx_err(priv); 1402 } 1403 1404 /** 1405 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1406 * @priv: driver private structure 1407 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1408 */ 1409 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1410 { 1411 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1412 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1413 1414 dwmac_mmc_intr_all_mask(priv->ioaddr); 1415 1416 if (priv->dma_cap.rmon) { 1417 dwmac_mmc_ctrl(priv->ioaddr, mode); 1418 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1419 } else 1420 pr_info(" No MAC Management Counters available\n"); 1421 } 1422 1423 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1424 { 1425 u32 hwid = priv->hw->synopsys_uid; 1426 1427 /* Check Synopsys Id (not available on old chips) */ 1428 if (likely(hwid)) { 1429 u32 uid = ((hwid & 0x0000ff00) >> 8); 1430 u32 synid = (hwid & 0x000000ff); 1431 1432 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1433 uid, synid); 1434 1435 return synid; 1436 } 1437 return 0; 1438 } 1439 1440 /** 1441 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors 1442 * @priv: driver private structure 1443 * Description: select the Enhanced/Alternate or Normal descriptors. 1444 * In case of Enhanced/Alternate, it looks at the extended descriptors are 1445 * supported by the HW cap. register. 1446 */ 1447 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1448 { 1449 if (priv->plat->enh_desc) { 1450 pr_info(" Enhanced/Alternate descriptors\n"); 1451 1452 /* GMAC older than 3.50 has no extended descriptors */ 1453 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1454 pr_info("\tEnabled extended descriptors\n"); 1455 priv->extend_desc = 1; 1456 } else 1457 pr_warn("Extended descriptors not supported\n"); 1458 1459 priv->hw->desc = &enh_desc_ops; 1460 } else { 1461 pr_info(" Normal descriptors\n"); 1462 priv->hw->desc = &ndesc_ops; 1463 } 1464 } 1465 1466 /** 1467 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. 1468 * @priv: driver private structure 1469 * Description: 1470 * new GMAC chip generations have a new register to indicate the 1471 * presence of the optional feature/functions. 1472 * This can be also used to override the value passed through the 1473 * platform and necessary for old MAC10/100 and GMAC chips. 1474 */ 1475 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1476 { 1477 u32 hw_cap = 0; 1478 1479 if (priv->hw->dma->get_hw_feature) { 1480 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1481 1482 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1483 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1484 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1485 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1486 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1487 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1488 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1489 priv->dma_cap.pmt_remote_wake_up = 1490 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1491 priv->dma_cap.pmt_magic_frame = 1492 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1493 /* MMC */ 1494 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1495 /* IEEE 1588-2002 */ 1496 priv->dma_cap.time_stamp = 1497 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1498 /* IEEE 1588-2008 */ 1499 priv->dma_cap.atime_stamp = 1500 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1501 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1502 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1503 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1504 /* TX and RX csum */ 1505 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1506 priv->dma_cap.rx_coe_type1 = 1507 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1508 priv->dma_cap.rx_coe_type2 = 1509 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1510 priv->dma_cap.rxfifo_over_2048 = 1511 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1512 /* TX and RX number of channels */ 1513 priv->dma_cap.number_rx_channel = 1514 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1515 priv->dma_cap.number_tx_channel = 1516 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1517 /* Alternate (enhanced) DESC mode */ 1518 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1519 } 1520 1521 return hw_cap; 1522 } 1523 1524 /** 1525 * stmmac_check_ether_addr: check if the MAC addr is valid 1526 * @priv: driver private structure 1527 * Description: 1528 * it is to verify if the MAC address is valid, in case of failures it 1529 * generates a random MAC address 1530 */ 1531 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1532 { 1533 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1534 priv->hw->mac->get_umac_addr(priv->hw, 1535 priv->dev->dev_addr, 0); 1536 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1537 eth_hw_addr_random(priv->dev); 1538 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1539 priv->dev->dev_addr); 1540 } 1541 } 1542 1543 /** 1544 * stmmac_init_dma_engine: DMA init. 1545 * @priv: driver private structure 1546 * Description: 1547 * It inits the DMA invoking the specific MAC/GMAC callback. 1548 * Some DMA parameters can be passed from the platform; 1549 * in case of these are not passed a default is kept for the MAC or GMAC. 1550 */ 1551 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1552 { 1553 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1554 int mixed_burst = 0; 1555 int atds = 0; 1556 1557 if (priv->plat->dma_cfg) { 1558 pbl = priv->plat->dma_cfg->pbl; 1559 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1560 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1561 burst_len = priv->plat->dma_cfg->burst_len; 1562 } 1563 1564 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1565 atds = 1; 1566 1567 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1568 burst_len, priv->dma_tx_phy, 1569 priv->dma_rx_phy, atds); 1570 } 1571 1572 /** 1573 * stmmac_tx_timer: mitigation sw timer for tx. 1574 * @data: data pointer 1575 * Description: 1576 * This is the timer handler to directly invoke the stmmac_tx_clean. 1577 */ 1578 static void stmmac_tx_timer(unsigned long data) 1579 { 1580 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1581 1582 stmmac_tx_clean(priv); 1583 } 1584 1585 /** 1586 * stmmac_init_tx_coalesce: init tx mitigation options. 1587 * @priv: driver private structure 1588 * Description: 1589 * This inits the transmit coalesce parameters: i.e. timer rate, 1590 * timer handler and default threshold used for enabling the 1591 * interrupt on completion bit. 1592 */ 1593 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1594 { 1595 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1596 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1597 init_timer(&priv->txtimer); 1598 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1599 priv->txtimer.data = (unsigned long)priv; 1600 priv->txtimer.function = stmmac_tx_timer; 1601 add_timer(&priv->txtimer); 1602 } 1603 1604 /** 1605 * stmmac_hw_setup: setup mac in a usable state. 1606 * @dev : pointer to the device structure. 1607 * Description: 1608 * This function sets up the ip in a usable state. 1609 * Return value: 1610 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1611 * file on failure. 1612 */ 1613 static int stmmac_hw_setup(struct net_device *dev) 1614 { 1615 struct stmmac_priv *priv = netdev_priv(dev); 1616 int ret; 1617 1618 ret = init_dma_desc_rings(dev); 1619 if (ret < 0) { 1620 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1621 return ret; 1622 } 1623 /* DMA initialization and SW reset */ 1624 ret = stmmac_init_dma_engine(priv); 1625 if (ret < 0) { 1626 pr_err("%s: DMA engine initialization failed\n", __func__); 1627 return ret; 1628 } 1629 1630 /* Copy the MAC addr into the HW */ 1631 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1632 1633 /* If required, perform hw setup of the bus. */ 1634 if (priv->plat->bus_setup) 1635 priv->plat->bus_setup(priv->ioaddr); 1636 1637 /* Initialize the MAC Core */ 1638 priv->hw->mac->core_init(priv->hw, dev->mtu); 1639 1640 /* Enable the MAC Rx/Tx */ 1641 stmmac_set_mac(priv->ioaddr, true); 1642 1643 /* Set the HW DMA mode and the COE */ 1644 stmmac_dma_operation_mode(priv); 1645 1646 stmmac_mmc_setup(priv); 1647 1648 ret = stmmac_init_ptp(priv); 1649 if (ret && ret != -EOPNOTSUPP) 1650 pr_warn("%s: failed PTP initialisation\n", __func__); 1651 1652 #ifdef CONFIG_STMMAC_DEBUG_FS 1653 ret = stmmac_init_fs(dev); 1654 if (ret < 0) 1655 pr_warn("%s: failed debugFS registration\n", __func__); 1656 #endif 1657 /* Start the ball rolling... */ 1658 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1659 priv->hw->dma->start_tx(priv->ioaddr); 1660 priv->hw->dma->start_rx(priv->ioaddr); 1661 1662 /* Dump DMA/MAC registers */ 1663 if (netif_msg_hw(priv)) { 1664 priv->hw->mac->dump_regs(priv->hw); 1665 priv->hw->dma->dump_regs(priv->ioaddr); 1666 } 1667 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1668 1669 priv->eee_enabled = stmmac_eee_init(priv); 1670 1671 stmmac_init_tx_coalesce(priv); 1672 1673 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1674 priv->rx_riwt = MAX_DMA_RIWT; 1675 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1676 } 1677 1678 if (priv->pcs && priv->hw->mac->ctrl_ane) 1679 priv->hw->mac->ctrl_ane(priv->hw, 0); 1680 1681 return 0; 1682 } 1683 1684 /** 1685 * stmmac_open - open entry point of the driver 1686 * @dev : pointer to the device structure. 1687 * Description: 1688 * This function is the open entry point of the driver. 1689 * Return value: 1690 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1691 * file on failure. 1692 */ 1693 static int stmmac_open(struct net_device *dev) 1694 { 1695 struct stmmac_priv *priv = netdev_priv(dev); 1696 int ret; 1697 1698 stmmac_check_ether_addr(priv); 1699 1700 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1701 priv->pcs != STMMAC_PCS_RTBI) { 1702 ret = stmmac_init_phy(dev); 1703 if (ret) { 1704 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1705 __func__, ret); 1706 return ret; 1707 } 1708 } 1709 1710 /* Extra statistics */ 1711 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1712 priv->xstats.threshold = tc; 1713 1714 /* Create and initialize the TX/RX descriptors chains. */ 1715 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1716 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1717 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1718 1719 ret = alloc_dma_desc_resources(priv); 1720 if (ret < 0) { 1721 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1722 goto dma_desc_error; 1723 } 1724 1725 ret = stmmac_hw_setup(dev); 1726 if (ret < 0) { 1727 pr_err("%s: Hw setup failed\n", __func__); 1728 goto init_error; 1729 } 1730 1731 if (priv->phydev) 1732 phy_start(priv->phydev); 1733 1734 /* Request the IRQ lines */ 1735 ret = request_irq(dev->irq, stmmac_interrupt, 1736 IRQF_SHARED, dev->name, dev); 1737 if (unlikely(ret < 0)) { 1738 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1739 __func__, dev->irq, ret); 1740 goto init_error; 1741 } 1742 1743 /* Request the Wake IRQ in case of another line is used for WoL */ 1744 if (priv->wol_irq != dev->irq) { 1745 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1746 IRQF_SHARED, dev->name, dev); 1747 if (unlikely(ret < 0)) { 1748 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1749 __func__, priv->wol_irq, ret); 1750 goto wolirq_error; 1751 } 1752 } 1753 1754 /* Request the IRQ lines */ 1755 if (priv->lpi_irq > 0) { 1756 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1757 dev->name, dev); 1758 if (unlikely(ret < 0)) { 1759 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1760 __func__, priv->lpi_irq, ret); 1761 goto lpiirq_error; 1762 } 1763 } 1764 1765 napi_enable(&priv->napi); 1766 netif_start_queue(dev); 1767 1768 return 0; 1769 1770 lpiirq_error: 1771 if (priv->wol_irq != dev->irq) 1772 free_irq(priv->wol_irq, dev); 1773 wolirq_error: 1774 free_irq(dev->irq, dev); 1775 1776 init_error: 1777 free_dma_desc_resources(priv); 1778 dma_desc_error: 1779 if (priv->phydev) 1780 phy_disconnect(priv->phydev); 1781 1782 return ret; 1783 } 1784 1785 /** 1786 * stmmac_release - close entry point of the driver 1787 * @dev : device pointer. 1788 * Description: 1789 * This is the stop entry point of the driver. 1790 */ 1791 static int stmmac_release(struct net_device *dev) 1792 { 1793 struct stmmac_priv *priv = netdev_priv(dev); 1794 1795 if (priv->eee_enabled) 1796 del_timer_sync(&priv->eee_ctrl_timer); 1797 1798 /* Stop and disconnect the PHY */ 1799 if (priv->phydev) { 1800 phy_stop(priv->phydev); 1801 phy_disconnect(priv->phydev); 1802 priv->phydev = NULL; 1803 } 1804 1805 netif_stop_queue(dev); 1806 1807 napi_disable(&priv->napi); 1808 1809 del_timer_sync(&priv->txtimer); 1810 1811 /* Free the IRQ lines */ 1812 free_irq(dev->irq, dev); 1813 if (priv->wol_irq != dev->irq) 1814 free_irq(priv->wol_irq, dev); 1815 if (priv->lpi_irq > 0) 1816 free_irq(priv->lpi_irq, dev); 1817 1818 /* Stop TX/RX DMA and clear the descriptors */ 1819 priv->hw->dma->stop_tx(priv->ioaddr); 1820 priv->hw->dma->stop_rx(priv->ioaddr); 1821 1822 /* Release and free the Rx/Tx resources */ 1823 free_dma_desc_resources(priv); 1824 1825 /* Disable the MAC Rx/Tx */ 1826 stmmac_set_mac(priv->ioaddr, false); 1827 1828 netif_carrier_off(dev); 1829 1830 #ifdef CONFIG_STMMAC_DEBUG_FS 1831 stmmac_exit_fs(); 1832 #endif 1833 1834 stmmac_release_ptp(priv); 1835 1836 return 0; 1837 } 1838 1839 /** 1840 * stmmac_xmit: Tx entry point of the driver 1841 * @skb : the socket buffer 1842 * @dev : device pointer 1843 * Description : this is the tx entry point of the driver. 1844 * It programs the chain or the ring and supports oversized frames 1845 * and SG feature. 1846 */ 1847 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1848 { 1849 struct stmmac_priv *priv = netdev_priv(dev); 1850 unsigned int txsize = priv->dma_tx_size; 1851 unsigned int entry; 1852 int i, csum_insertion = 0, is_jumbo = 0; 1853 int nfrags = skb_shinfo(skb)->nr_frags; 1854 struct dma_desc *desc, *first; 1855 unsigned int nopaged_len = skb_headlen(skb); 1856 unsigned int enh_desc = priv->plat->enh_desc; 1857 1858 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1859 if (!netif_queue_stopped(dev)) { 1860 netif_stop_queue(dev); 1861 /* This is a hard error, log it. */ 1862 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1863 } 1864 return NETDEV_TX_BUSY; 1865 } 1866 1867 spin_lock(&priv->tx_lock); 1868 1869 if (priv->tx_path_in_lpi_mode) 1870 stmmac_disable_eee_mode(priv); 1871 1872 entry = priv->cur_tx % txsize; 1873 1874 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1875 1876 if (priv->extend_desc) 1877 desc = (struct dma_desc *)(priv->dma_etx + entry); 1878 else 1879 desc = priv->dma_tx + entry; 1880 1881 first = desc; 1882 1883 /* To program the descriptors according to the size of the frame */ 1884 if (enh_desc) 1885 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 1886 1887 if (likely(!is_jumbo)) { 1888 desc->des2 = dma_map_single(priv->device, skb->data, 1889 nopaged_len, DMA_TO_DEVICE); 1890 priv->tx_skbuff_dma[entry] = desc->des2; 1891 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1892 csum_insertion, priv->mode); 1893 } else { 1894 desc = first; 1895 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 1896 } 1897 1898 for (i = 0; i < nfrags; i++) { 1899 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1900 int len = skb_frag_size(frag); 1901 1902 priv->tx_skbuff[entry] = NULL; 1903 entry = (++priv->cur_tx) % txsize; 1904 if (priv->extend_desc) 1905 desc = (struct dma_desc *)(priv->dma_etx + entry); 1906 else 1907 desc = priv->dma_tx + entry; 1908 1909 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1910 DMA_TO_DEVICE); 1911 priv->tx_skbuff_dma[entry] = desc->des2; 1912 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1913 priv->mode); 1914 wmb(); 1915 priv->hw->desc->set_tx_owner(desc); 1916 wmb(); 1917 } 1918 1919 priv->tx_skbuff[entry] = skb; 1920 1921 /* Finalize the latest segment. */ 1922 priv->hw->desc->close_tx_desc(desc); 1923 1924 wmb(); 1925 /* According to the coalesce parameter the IC bit for the latest 1926 * segment could be reset and the timer re-started to invoke the 1927 * stmmac_tx function. This approach takes care about the fragments. 1928 */ 1929 priv->tx_count_frames += nfrags + 1; 1930 if (priv->tx_coal_frames > priv->tx_count_frames) { 1931 priv->hw->desc->clear_tx_ic(desc); 1932 priv->xstats.tx_reset_ic_bit++; 1933 mod_timer(&priv->txtimer, 1934 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1935 } else 1936 priv->tx_count_frames = 0; 1937 1938 /* To avoid raise condition */ 1939 priv->hw->desc->set_tx_owner(first); 1940 wmb(); 1941 1942 priv->cur_tx++; 1943 1944 if (netif_msg_pktdata(priv)) { 1945 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 1946 __func__, (priv->cur_tx % txsize), 1947 (priv->dirty_tx % txsize), entry, first, nfrags); 1948 1949 if (priv->extend_desc) 1950 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 1951 else 1952 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 1953 1954 pr_debug(">>> frame to be transmitted: "); 1955 print_pkt(skb->data, skb->len); 1956 } 1957 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1958 if (netif_msg_hw(priv)) 1959 pr_debug("%s: stop transmitted packets\n", __func__); 1960 netif_stop_queue(dev); 1961 } 1962 1963 dev->stats.tx_bytes += skb->len; 1964 1965 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1966 priv->hwts_tx_en)) { 1967 /* declare that device is doing timestamping */ 1968 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1969 priv->hw->desc->enable_tx_timestamp(first); 1970 } 1971 1972 if (!priv->hwts_tx_en) 1973 skb_tx_timestamp(skb); 1974 1975 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1976 1977 spin_unlock(&priv->tx_lock); 1978 1979 return NETDEV_TX_OK; 1980 } 1981 1982 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 1983 { 1984 struct ethhdr *ehdr; 1985 u16 vlanid; 1986 1987 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 1988 NETIF_F_HW_VLAN_CTAG_RX && 1989 !__vlan_get_tag(skb, &vlanid)) { 1990 /* pop the vlan tag */ 1991 ehdr = (struct ethhdr *)skb->data; 1992 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 1993 skb_pull(skb, VLAN_HLEN); 1994 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 1995 } 1996 } 1997 1998 1999 /** 2000 * stmmac_rx_refill: refill used skb preallocated buffers 2001 * @priv: driver private structure 2002 * Description : this is to reallocate the skb for the reception process 2003 * that is based on zero-copy. 2004 */ 2005 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2006 { 2007 unsigned int rxsize = priv->dma_rx_size; 2008 int bfsize = priv->dma_buf_sz; 2009 2010 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2011 unsigned int entry = priv->dirty_rx % rxsize; 2012 struct dma_desc *p; 2013 2014 if (priv->extend_desc) 2015 p = (struct dma_desc *)(priv->dma_erx + entry); 2016 else 2017 p = priv->dma_rx + entry; 2018 2019 if (likely(priv->rx_skbuff[entry] == NULL)) { 2020 struct sk_buff *skb; 2021 2022 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2023 2024 if (unlikely(skb == NULL)) 2025 break; 2026 2027 priv->rx_skbuff[entry] = skb; 2028 priv->rx_skbuff_dma[entry] = 2029 dma_map_single(priv->device, skb->data, bfsize, 2030 DMA_FROM_DEVICE); 2031 2032 p->des2 = priv->rx_skbuff_dma[entry]; 2033 2034 priv->hw->mode->refill_desc3(priv, p); 2035 2036 if (netif_msg_rx_status(priv)) 2037 pr_debug("\trefill entry #%d\n", entry); 2038 } 2039 wmb(); 2040 priv->hw->desc->set_rx_owner(p); 2041 wmb(); 2042 } 2043 } 2044 2045 /** 2046 * stmmac_rx_refill: refill used skb preallocated buffers 2047 * @priv: driver private structure 2048 * @limit: napi bugget. 2049 * Description : this the function called by the napi poll method. 2050 * It gets all the frames inside the ring. 2051 */ 2052 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2053 { 2054 unsigned int rxsize = priv->dma_rx_size; 2055 unsigned int entry = priv->cur_rx % rxsize; 2056 unsigned int next_entry; 2057 unsigned int count = 0; 2058 int coe = priv->plat->rx_coe; 2059 2060 if (netif_msg_rx_status(priv)) { 2061 pr_debug("%s: descriptor ring:\n", __func__); 2062 if (priv->extend_desc) 2063 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2064 else 2065 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2066 } 2067 while (count < limit) { 2068 int status; 2069 struct dma_desc *p; 2070 2071 if (priv->extend_desc) 2072 p = (struct dma_desc *)(priv->dma_erx + entry); 2073 else 2074 p = priv->dma_rx + entry; 2075 2076 if (priv->hw->desc->get_rx_owner(p)) 2077 break; 2078 2079 count++; 2080 2081 next_entry = (++priv->cur_rx) % rxsize; 2082 if (priv->extend_desc) 2083 prefetch(priv->dma_erx + next_entry); 2084 else 2085 prefetch(priv->dma_rx + next_entry); 2086 2087 /* read the status of the incoming frame */ 2088 status = priv->hw->desc->rx_status(&priv->dev->stats, 2089 &priv->xstats, p); 2090 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2091 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2092 &priv->xstats, 2093 priv->dma_erx + 2094 entry); 2095 if (unlikely(status == discard_frame)) { 2096 priv->dev->stats.rx_errors++; 2097 if (priv->hwts_rx_en && !priv->extend_desc) { 2098 /* DESC2 & DESC3 will be overwitten by device 2099 * with timestamp value, hence reinitialize 2100 * them in stmmac_rx_refill() function so that 2101 * device can reuse it. 2102 */ 2103 priv->rx_skbuff[entry] = NULL; 2104 dma_unmap_single(priv->device, 2105 priv->rx_skbuff_dma[entry], 2106 priv->dma_buf_sz, 2107 DMA_FROM_DEVICE); 2108 } 2109 } else { 2110 struct sk_buff *skb; 2111 int frame_len; 2112 2113 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2114 2115 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2116 * Type frames (LLC/LLC-SNAP) 2117 */ 2118 if (unlikely(status != llc_snap)) 2119 frame_len -= ETH_FCS_LEN; 2120 2121 if (netif_msg_rx_status(priv)) { 2122 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2123 p, entry, p->des2); 2124 if (frame_len > ETH_FRAME_LEN) 2125 pr_debug("\tframe size %d, COE: %d\n", 2126 frame_len, status); 2127 } 2128 skb = priv->rx_skbuff[entry]; 2129 if (unlikely(!skb)) { 2130 pr_err("%s: Inconsistent Rx descriptor chain\n", 2131 priv->dev->name); 2132 priv->dev->stats.rx_dropped++; 2133 break; 2134 } 2135 prefetch(skb->data - NET_IP_ALIGN); 2136 priv->rx_skbuff[entry] = NULL; 2137 2138 stmmac_get_rx_hwtstamp(priv, entry, skb); 2139 2140 skb_put(skb, frame_len); 2141 dma_unmap_single(priv->device, 2142 priv->rx_skbuff_dma[entry], 2143 priv->dma_buf_sz, DMA_FROM_DEVICE); 2144 2145 if (netif_msg_pktdata(priv)) { 2146 pr_debug("frame received (%dbytes)", frame_len); 2147 print_pkt(skb->data, frame_len); 2148 } 2149 2150 stmmac_rx_vlan(priv->dev, skb); 2151 2152 skb->protocol = eth_type_trans(skb, priv->dev); 2153 2154 if (unlikely(!coe)) 2155 skb_checksum_none_assert(skb); 2156 else 2157 skb->ip_summed = CHECKSUM_UNNECESSARY; 2158 2159 napi_gro_receive(&priv->napi, skb); 2160 2161 priv->dev->stats.rx_packets++; 2162 priv->dev->stats.rx_bytes += frame_len; 2163 } 2164 entry = next_entry; 2165 } 2166 2167 stmmac_rx_refill(priv); 2168 2169 priv->xstats.rx_pkt_n += count; 2170 2171 return count; 2172 } 2173 2174 /** 2175 * stmmac_poll - stmmac poll method (NAPI) 2176 * @napi : pointer to the napi structure. 2177 * @budget : maximum number of packets that the current CPU can receive from 2178 * all interfaces. 2179 * Description : 2180 * To look at the incoming frames and clear the tx resources. 2181 */ 2182 static int stmmac_poll(struct napi_struct *napi, int budget) 2183 { 2184 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2185 int work_done = 0; 2186 2187 priv->xstats.napi_poll++; 2188 stmmac_tx_clean(priv); 2189 2190 work_done = stmmac_rx(priv, budget); 2191 if (work_done < budget) { 2192 napi_complete(napi); 2193 stmmac_enable_dma_irq(priv); 2194 } 2195 return work_done; 2196 } 2197 2198 /** 2199 * stmmac_tx_timeout 2200 * @dev : Pointer to net device structure 2201 * Description: this function is called when a packet transmission fails to 2202 * complete within a reasonable time. The driver will mark the error in the 2203 * netdev structure and arrange for the device to be reset to a sane state 2204 * in order to transmit a new packet. 2205 */ 2206 static void stmmac_tx_timeout(struct net_device *dev) 2207 { 2208 struct stmmac_priv *priv = netdev_priv(dev); 2209 2210 /* Clear Tx resources and restart transmitting again */ 2211 stmmac_tx_err(priv); 2212 } 2213 2214 /** 2215 * stmmac_set_rx_mode - entry point for multicast addressing 2216 * @dev : pointer to the device structure 2217 * Description: 2218 * This function is a driver entry point which gets called by the kernel 2219 * whenever multicast addresses must be enabled/disabled. 2220 * Return value: 2221 * void. 2222 */ 2223 static void stmmac_set_rx_mode(struct net_device *dev) 2224 { 2225 struct stmmac_priv *priv = netdev_priv(dev); 2226 2227 spin_lock(&priv->lock); 2228 priv->hw->mac->set_filter(priv->hw, dev); 2229 spin_unlock(&priv->lock); 2230 } 2231 2232 /** 2233 * stmmac_change_mtu - entry point to change MTU size for the device. 2234 * @dev : device pointer. 2235 * @new_mtu : the new MTU size for the device. 2236 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2237 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2238 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2239 * Return value: 2240 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2241 * file on failure. 2242 */ 2243 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2244 { 2245 struct stmmac_priv *priv = netdev_priv(dev); 2246 int max_mtu; 2247 2248 if (netif_running(dev)) { 2249 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2250 return -EBUSY; 2251 } 2252 2253 if (priv->plat->enh_desc) 2254 max_mtu = JUMBO_LEN; 2255 else 2256 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2257 2258 if (priv->plat->maxmtu < max_mtu) 2259 max_mtu = priv->plat->maxmtu; 2260 2261 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2262 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2263 return -EINVAL; 2264 } 2265 2266 dev->mtu = new_mtu; 2267 netdev_update_features(dev); 2268 2269 return 0; 2270 } 2271 2272 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2273 netdev_features_t features) 2274 { 2275 struct stmmac_priv *priv = netdev_priv(dev); 2276 2277 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2278 features &= ~NETIF_F_RXCSUM; 2279 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 2280 features &= ~NETIF_F_IPV6_CSUM; 2281 if (!priv->plat->tx_coe) 2282 features &= ~NETIF_F_ALL_CSUM; 2283 2284 /* Some GMAC devices have a bugged Jumbo frame support that 2285 * needs to have the Tx COE disabled for oversized frames 2286 * (due to limited buffer sizes). In this case we disable 2287 * the TX csum insertionin the TDES and not use SF. 2288 */ 2289 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2290 features &= ~NETIF_F_ALL_CSUM; 2291 2292 return features; 2293 } 2294 2295 /** 2296 * stmmac_interrupt - main ISR 2297 * @irq: interrupt number. 2298 * @dev_id: to pass the net device pointer. 2299 * Description: this is the main driver interrupt service routine. 2300 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 2301 * interrupts. 2302 */ 2303 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2304 { 2305 struct net_device *dev = (struct net_device *)dev_id; 2306 struct stmmac_priv *priv = netdev_priv(dev); 2307 2308 if (priv->irq_wake) 2309 pm_wakeup_event(priv->device, 0); 2310 2311 if (unlikely(!dev)) { 2312 pr_err("%s: invalid dev pointer\n", __func__); 2313 return IRQ_NONE; 2314 } 2315 2316 /* To handle GMAC own interrupts */ 2317 if (priv->plat->has_gmac) { 2318 int status = priv->hw->mac->host_irq_status(priv->hw, 2319 &priv->xstats); 2320 if (unlikely(status)) { 2321 /* For LPI we need to save the tx status */ 2322 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2323 priv->tx_path_in_lpi_mode = true; 2324 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2325 priv->tx_path_in_lpi_mode = false; 2326 } 2327 } 2328 2329 /* To handle DMA interrupts */ 2330 stmmac_dma_interrupt(priv); 2331 2332 return IRQ_HANDLED; 2333 } 2334 2335 #ifdef CONFIG_NET_POLL_CONTROLLER 2336 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2337 * to allow network I/O with interrupts disabled. 2338 */ 2339 static void stmmac_poll_controller(struct net_device *dev) 2340 { 2341 disable_irq(dev->irq); 2342 stmmac_interrupt(dev->irq, dev); 2343 enable_irq(dev->irq); 2344 } 2345 #endif 2346 2347 /** 2348 * stmmac_ioctl - Entry point for the Ioctl 2349 * @dev: Device pointer. 2350 * @rq: An IOCTL specefic structure, that can contain a pointer to 2351 * a proprietary structure used to pass information to the driver. 2352 * @cmd: IOCTL command 2353 * Description: 2354 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2355 */ 2356 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2357 { 2358 struct stmmac_priv *priv = netdev_priv(dev); 2359 int ret = -EOPNOTSUPP; 2360 2361 if (!netif_running(dev)) 2362 return -EINVAL; 2363 2364 switch (cmd) { 2365 case SIOCGMIIPHY: 2366 case SIOCGMIIREG: 2367 case SIOCSMIIREG: 2368 if (!priv->phydev) 2369 return -EINVAL; 2370 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2371 break; 2372 case SIOCSHWTSTAMP: 2373 ret = stmmac_hwtstamp_ioctl(dev, rq); 2374 break; 2375 default: 2376 break; 2377 } 2378 2379 return ret; 2380 } 2381 2382 #ifdef CONFIG_STMMAC_DEBUG_FS 2383 static struct dentry *stmmac_fs_dir; 2384 static struct dentry *stmmac_rings_status; 2385 static struct dentry *stmmac_dma_cap; 2386 2387 static void sysfs_display_ring(void *head, int size, int extend_desc, 2388 struct seq_file *seq) 2389 { 2390 int i; 2391 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2392 struct dma_desc *p = (struct dma_desc *)head; 2393 2394 for (i = 0; i < size; i++) { 2395 u64 x; 2396 if (extend_desc) { 2397 x = *(u64 *) ep; 2398 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2399 i, (unsigned int)virt_to_phys(ep), 2400 (unsigned int)x, (unsigned int)(x >> 32), 2401 ep->basic.des2, ep->basic.des3); 2402 ep++; 2403 } else { 2404 x = *(u64 *) p; 2405 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2406 i, (unsigned int)virt_to_phys(ep), 2407 (unsigned int)x, (unsigned int)(x >> 32), 2408 p->des2, p->des3); 2409 p++; 2410 } 2411 seq_printf(seq, "\n"); 2412 } 2413 } 2414 2415 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2416 { 2417 struct net_device *dev = seq->private; 2418 struct stmmac_priv *priv = netdev_priv(dev); 2419 unsigned int txsize = priv->dma_tx_size; 2420 unsigned int rxsize = priv->dma_rx_size; 2421 2422 if (priv->extend_desc) { 2423 seq_printf(seq, "Extended RX descriptor ring:\n"); 2424 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2425 seq_printf(seq, "Extended TX descriptor ring:\n"); 2426 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2427 } else { 2428 seq_printf(seq, "RX descriptor ring:\n"); 2429 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2430 seq_printf(seq, "TX descriptor ring:\n"); 2431 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2432 } 2433 2434 return 0; 2435 } 2436 2437 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2438 { 2439 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2440 } 2441 2442 static const struct file_operations stmmac_rings_status_fops = { 2443 .owner = THIS_MODULE, 2444 .open = stmmac_sysfs_ring_open, 2445 .read = seq_read, 2446 .llseek = seq_lseek, 2447 .release = single_release, 2448 }; 2449 2450 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2451 { 2452 struct net_device *dev = seq->private; 2453 struct stmmac_priv *priv = netdev_priv(dev); 2454 2455 if (!priv->hw_cap_support) { 2456 seq_printf(seq, "DMA HW features not supported\n"); 2457 return 0; 2458 } 2459 2460 seq_printf(seq, "==============================\n"); 2461 seq_printf(seq, "\tDMA HW features\n"); 2462 seq_printf(seq, "==============================\n"); 2463 2464 seq_printf(seq, "\t10/100 Mbps %s\n", 2465 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2466 seq_printf(seq, "\t1000 Mbps %s\n", 2467 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2468 seq_printf(seq, "\tHalf duple %s\n", 2469 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2470 seq_printf(seq, "\tHash Filter: %s\n", 2471 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2472 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2473 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2474 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2475 (priv->dma_cap.pcs) ? "Y" : "N"); 2476 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2477 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2478 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2479 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2480 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2481 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2482 seq_printf(seq, "\tRMON module: %s\n", 2483 (priv->dma_cap.rmon) ? "Y" : "N"); 2484 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2485 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2486 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2487 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2488 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2489 (priv->dma_cap.eee) ? "Y" : "N"); 2490 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2491 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2492 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2493 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2494 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2495 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2496 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2497 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2498 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2499 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2500 priv->dma_cap.number_rx_channel); 2501 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2502 priv->dma_cap.number_tx_channel); 2503 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2504 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2505 2506 return 0; 2507 } 2508 2509 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2510 { 2511 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2512 } 2513 2514 static const struct file_operations stmmac_dma_cap_fops = { 2515 .owner = THIS_MODULE, 2516 .open = stmmac_sysfs_dma_cap_open, 2517 .read = seq_read, 2518 .llseek = seq_lseek, 2519 .release = single_release, 2520 }; 2521 2522 static int stmmac_init_fs(struct net_device *dev) 2523 { 2524 /* Create debugfs entries */ 2525 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2526 2527 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2528 pr_err("ERROR %s, debugfs create directory failed\n", 2529 STMMAC_RESOURCE_NAME); 2530 2531 return -ENOMEM; 2532 } 2533 2534 /* Entry to report DMA RX/TX rings */ 2535 stmmac_rings_status = debugfs_create_file("descriptors_status", 2536 S_IRUGO, stmmac_fs_dir, dev, 2537 &stmmac_rings_status_fops); 2538 2539 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2540 pr_info("ERROR creating stmmac ring debugfs file\n"); 2541 debugfs_remove(stmmac_fs_dir); 2542 2543 return -ENOMEM; 2544 } 2545 2546 /* Entry to report the DMA HW features */ 2547 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2548 dev, &stmmac_dma_cap_fops); 2549 2550 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2551 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2552 debugfs_remove(stmmac_rings_status); 2553 debugfs_remove(stmmac_fs_dir); 2554 2555 return -ENOMEM; 2556 } 2557 2558 return 0; 2559 } 2560 2561 static void stmmac_exit_fs(void) 2562 { 2563 debugfs_remove(stmmac_rings_status); 2564 debugfs_remove(stmmac_dma_cap); 2565 debugfs_remove(stmmac_fs_dir); 2566 } 2567 #endif /* CONFIG_STMMAC_DEBUG_FS */ 2568 2569 static const struct net_device_ops stmmac_netdev_ops = { 2570 .ndo_open = stmmac_open, 2571 .ndo_start_xmit = stmmac_xmit, 2572 .ndo_stop = stmmac_release, 2573 .ndo_change_mtu = stmmac_change_mtu, 2574 .ndo_fix_features = stmmac_fix_features, 2575 .ndo_set_rx_mode = stmmac_set_rx_mode, 2576 .ndo_tx_timeout = stmmac_tx_timeout, 2577 .ndo_do_ioctl = stmmac_ioctl, 2578 #ifdef CONFIG_NET_POLL_CONTROLLER 2579 .ndo_poll_controller = stmmac_poll_controller, 2580 #endif 2581 .ndo_set_mac_address = eth_mac_addr, 2582 }; 2583 2584 /** 2585 * stmmac_hw_init - Init the MAC device 2586 * @priv: driver private structure 2587 * Description: this function detects which MAC device 2588 * (GMAC/MAC10-100) has to attached, checks the HW capability 2589 * (if supported) and sets the driver's features (for example 2590 * to use the ring or chaine mode or support the normal/enh 2591 * descriptor structure). 2592 */ 2593 static int stmmac_hw_init(struct stmmac_priv *priv) 2594 { 2595 int ret; 2596 struct mac_device_info *mac; 2597 2598 /* Identify the MAC HW device */ 2599 if (priv->plat->has_gmac) { 2600 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2601 mac = dwmac1000_setup(priv->ioaddr, 2602 priv->plat->multicast_filter_bins, 2603 priv->plat->unicast_filter_entries); 2604 } else { 2605 mac = dwmac100_setup(priv->ioaddr); 2606 } 2607 if (!mac) 2608 return -ENOMEM; 2609 2610 priv->hw = mac; 2611 2612 /* Get and dump the chip ID */ 2613 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2614 2615 /* To use the chained or ring mode */ 2616 if (chain_mode) { 2617 priv->hw->mode = &chain_mode_ops; 2618 pr_info(" Chain mode enabled\n"); 2619 priv->mode = STMMAC_CHAIN_MODE; 2620 } else { 2621 priv->hw->mode = &ring_mode_ops; 2622 pr_info(" Ring mode enabled\n"); 2623 priv->mode = STMMAC_RING_MODE; 2624 } 2625 2626 /* Get the HW capability (new GMAC newer than 3.50a) */ 2627 priv->hw_cap_support = stmmac_get_hw_features(priv); 2628 if (priv->hw_cap_support) { 2629 pr_info(" DMA HW capability register supported"); 2630 2631 /* We can override some gmac/dma configuration fields: e.g. 2632 * enh_desc, tx_coe (e.g. that are passed through the 2633 * platform) with the values from the HW capability 2634 * register (if supported). 2635 */ 2636 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2637 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2638 2639 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2640 2641 if (priv->dma_cap.rx_coe_type2) 2642 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2643 else if (priv->dma_cap.rx_coe_type1) 2644 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2645 2646 } else 2647 pr_info(" No HW DMA feature register supported"); 2648 2649 /* To use alternate (extended) or normal descriptor structures */ 2650 stmmac_selec_desc_mode(priv); 2651 2652 ret = priv->hw->mac->rx_ipc(priv->hw); 2653 if (!ret) { 2654 pr_warn(" RX IPC Checksum Offload not configured.\n"); 2655 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2656 } 2657 2658 if (priv->plat->rx_coe) 2659 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2660 priv->plat->rx_coe); 2661 if (priv->plat->tx_coe) 2662 pr_info(" TX Checksum insertion supported\n"); 2663 2664 if (priv->plat->pmt) { 2665 pr_info(" Wake-Up On Lan supported\n"); 2666 device_set_wakeup_capable(priv->device, 1); 2667 } 2668 2669 return 0; 2670 } 2671 2672 /** 2673 * stmmac_dvr_probe 2674 * @device: device pointer 2675 * @plat_dat: platform data pointer 2676 * @addr: iobase memory address 2677 * Description: this is the main probe function used to 2678 * call the alloc_etherdev, allocate the priv structure. 2679 */ 2680 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2681 struct plat_stmmacenet_data *plat_dat, 2682 void __iomem *addr) 2683 { 2684 int ret = 0; 2685 struct net_device *ndev = NULL; 2686 struct stmmac_priv *priv; 2687 2688 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2689 if (!ndev) 2690 return NULL; 2691 2692 SET_NETDEV_DEV(ndev, device); 2693 2694 priv = netdev_priv(ndev); 2695 priv->device = device; 2696 priv->dev = ndev; 2697 2698 ether_setup(ndev); 2699 2700 stmmac_set_ethtool_ops(ndev); 2701 priv->pause = pause; 2702 priv->plat = plat_dat; 2703 priv->ioaddr = addr; 2704 priv->dev->base_addr = (unsigned long)addr; 2705 2706 /* Verify driver arguments */ 2707 stmmac_verify_args(); 2708 2709 /* Override with kernel parameters if supplied XXX CRS XXX 2710 * this needs to have multiple instances 2711 */ 2712 if ((phyaddr >= 0) && (phyaddr <= 31)) 2713 priv->plat->phy_addr = phyaddr; 2714 2715 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2716 if (IS_ERR(priv->stmmac_clk)) { 2717 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2718 __func__); 2719 ret = PTR_ERR(priv->stmmac_clk); 2720 goto error_clk_get; 2721 } 2722 clk_prepare_enable(priv->stmmac_clk); 2723 2724 priv->stmmac_rst = devm_reset_control_get(priv->device, 2725 STMMAC_RESOURCE_NAME); 2726 if (IS_ERR(priv->stmmac_rst)) { 2727 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2728 ret = -EPROBE_DEFER; 2729 goto error_hw_init; 2730 } 2731 dev_info(priv->device, "no reset control found\n"); 2732 priv->stmmac_rst = NULL; 2733 } 2734 if (priv->stmmac_rst) 2735 reset_control_deassert(priv->stmmac_rst); 2736 2737 /* Init MAC and get the capabilities */ 2738 ret = stmmac_hw_init(priv); 2739 if (ret) 2740 goto error_hw_init; 2741 2742 ndev->netdev_ops = &stmmac_netdev_ops; 2743 2744 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2745 NETIF_F_RXCSUM; 2746 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2747 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2748 #ifdef STMMAC_VLAN_TAG_USED 2749 /* Both mac100 and gmac support receive VLAN tag detection */ 2750 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2751 #endif 2752 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2753 2754 if (flow_ctrl) 2755 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2756 2757 /* Rx Watchdog is available in the COREs newer than the 3.40. 2758 * In some case, for example on bugged HW this feature 2759 * has to be disable and this can be done by passing the 2760 * riwt_off field from the platform. 2761 */ 2762 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2763 priv->use_riwt = 1; 2764 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2765 } 2766 2767 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2768 2769 spin_lock_init(&priv->lock); 2770 spin_lock_init(&priv->tx_lock); 2771 2772 ret = register_netdev(ndev); 2773 if (ret) { 2774 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2775 goto error_netdev_register; 2776 } 2777 2778 /* If a specific clk_csr value is passed from the platform 2779 * this means that the CSR Clock Range selection cannot be 2780 * changed at run-time and it is fixed. Viceversa the driver'll try to 2781 * set the MDC clock dynamically according to the csr actual 2782 * clock input. 2783 */ 2784 if (!priv->plat->clk_csr) 2785 stmmac_clk_csr_set(priv); 2786 else 2787 priv->clk_csr = priv->plat->clk_csr; 2788 2789 stmmac_check_pcs_mode(priv); 2790 2791 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2792 priv->pcs != STMMAC_PCS_RTBI) { 2793 /* MDIO bus Registration */ 2794 ret = stmmac_mdio_register(ndev); 2795 if (ret < 0) { 2796 pr_debug("%s: MDIO bus (id: %d) registration failed", 2797 __func__, priv->plat->bus_id); 2798 goto error_mdio_register; 2799 } 2800 } 2801 2802 return priv; 2803 2804 error_mdio_register: 2805 unregister_netdev(ndev); 2806 error_netdev_register: 2807 netif_napi_del(&priv->napi); 2808 error_hw_init: 2809 clk_disable_unprepare(priv->stmmac_clk); 2810 error_clk_get: 2811 free_netdev(ndev); 2812 2813 return ERR_PTR(ret); 2814 } 2815 2816 /** 2817 * stmmac_dvr_remove 2818 * @ndev: net device pointer 2819 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2820 * changes the link status, releases the DMA descriptor rings. 2821 */ 2822 int stmmac_dvr_remove(struct net_device *ndev) 2823 { 2824 struct stmmac_priv *priv = netdev_priv(ndev); 2825 2826 pr_info("%s:\n\tremoving driver", __func__); 2827 2828 priv->hw->dma->stop_rx(priv->ioaddr); 2829 priv->hw->dma->stop_tx(priv->ioaddr); 2830 2831 stmmac_set_mac(priv->ioaddr, false); 2832 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2833 priv->pcs != STMMAC_PCS_RTBI) 2834 stmmac_mdio_unregister(ndev); 2835 netif_carrier_off(ndev); 2836 unregister_netdev(ndev); 2837 if (priv->stmmac_rst) 2838 reset_control_assert(priv->stmmac_rst); 2839 clk_disable_unprepare(priv->stmmac_clk); 2840 free_netdev(ndev); 2841 2842 return 0; 2843 } 2844 2845 #ifdef CONFIG_PM 2846 int stmmac_suspend(struct net_device *ndev) 2847 { 2848 struct stmmac_priv *priv = netdev_priv(ndev); 2849 unsigned long flags; 2850 2851 if (!ndev || !netif_running(ndev)) 2852 return 0; 2853 2854 if (priv->phydev) 2855 phy_stop(priv->phydev); 2856 2857 spin_lock_irqsave(&priv->lock, flags); 2858 2859 netif_device_detach(ndev); 2860 netif_stop_queue(ndev); 2861 2862 napi_disable(&priv->napi); 2863 2864 /* Stop TX/RX DMA */ 2865 priv->hw->dma->stop_tx(priv->ioaddr); 2866 priv->hw->dma->stop_rx(priv->ioaddr); 2867 2868 stmmac_clear_descriptors(priv); 2869 2870 /* Enable Power down mode by programming the PMT regs */ 2871 if (device_may_wakeup(priv->device)) { 2872 priv->hw->mac->pmt(priv->hw, priv->wolopts); 2873 priv->irq_wake = 1; 2874 } else { 2875 stmmac_set_mac(priv->ioaddr, false); 2876 pinctrl_pm_select_sleep_state(priv->device); 2877 /* Disable clock in case of PWM is off */ 2878 clk_disable_unprepare(priv->stmmac_clk); 2879 } 2880 spin_unlock_irqrestore(&priv->lock, flags); 2881 2882 priv->oldlink = 0; 2883 priv->speed = 0; 2884 priv->oldduplex = -1; 2885 return 0; 2886 } 2887 2888 int stmmac_resume(struct net_device *ndev) 2889 { 2890 struct stmmac_priv *priv = netdev_priv(ndev); 2891 unsigned long flags; 2892 2893 if (!netif_running(ndev)) 2894 return 0; 2895 2896 spin_lock_irqsave(&priv->lock, flags); 2897 2898 /* Power Down bit, into the PM register, is cleared 2899 * automatically as soon as a magic packet or a Wake-up frame 2900 * is received. Anyway, it's better to manually clear 2901 * this bit because it can generate problems while resuming 2902 * from another devices (e.g. serial console). 2903 */ 2904 if (device_may_wakeup(priv->device)) { 2905 priv->hw->mac->pmt(priv->hw, 0); 2906 priv->irq_wake = 0; 2907 } else { 2908 pinctrl_pm_select_default_state(priv->device); 2909 /* enable the clk prevously disabled */ 2910 clk_prepare_enable(priv->stmmac_clk); 2911 /* reset the phy so that it's ready */ 2912 if (priv->mii) 2913 stmmac_mdio_reset(priv->mii); 2914 } 2915 2916 netif_device_attach(ndev); 2917 2918 stmmac_hw_setup(ndev); 2919 2920 napi_enable(&priv->napi); 2921 2922 netif_start_queue(ndev); 2923 2924 spin_unlock_irqrestore(&priv->lock, flags); 2925 2926 if (priv->phydev) 2927 phy_start(priv->phydev); 2928 2929 return 0; 2930 } 2931 #endif /* CONFIG_PM */ 2932 2933 /* Driver can be configured w/ and w/ both PCI and Platf drivers 2934 * depending on the configuration selected. 2935 */ 2936 static int __init stmmac_init(void) 2937 { 2938 int ret; 2939 2940 ret = stmmac_register_platform(); 2941 if (ret) 2942 goto err; 2943 ret = stmmac_register_pci(); 2944 if (ret) 2945 goto err_pci; 2946 return 0; 2947 err_pci: 2948 stmmac_unregister_platform(); 2949 err: 2950 pr_err("stmmac: driver registration failed\n"); 2951 return ret; 2952 } 2953 2954 static void __exit stmmac_exit(void) 2955 { 2956 stmmac_unregister_platform(); 2957 stmmac_unregister_pci(); 2958 } 2959 2960 module_init(stmmac_init); 2961 module_exit(stmmac_exit); 2962 2963 #ifndef MODULE 2964 static int __init stmmac_cmdline_opt(char *str) 2965 { 2966 char *opt; 2967 2968 if (!str || !*str) 2969 return -EINVAL; 2970 while ((opt = strsep(&str, ",")) != NULL) { 2971 if (!strncmp(opt, "debug:", 6)) { 2972 if (kstrtoint(opt + 6, 0, &debug)) 2973 goto err; 2974 } else if (!strncmp(opt, "phyaddr:", 8)) { 2975 if (kstrtoint(opt + 8, 0, &phyaddr)) 2976 goto err; 2977 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2978 if (kstrtoint(opt + 11, 0, &dma_txsize)) 2979 goto err; 2980 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2981 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 2982 goto err; 2983 } else if (!strncmp(opt, "buf_sz:", 7)) { 2984 if (kstrtoint(opt + 7, 0, &buf_sz)) 2985 goto err; 2986 } else if (!strncmp(opt, "tc:", 3)) { 2987 if (kstrtoint(opt + 3, 0, &tc)) 2988 goto err; 2989 } else if (!strncmp(opt, "watchdog:", 9)) { 2990 if (kstrtoint(opt + 9, 0, &watchdog)) 2991 goto err; 2992 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2993 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 2994 goto err; 2995 } else if (!strncmp(opt, "pause:", 6)) { 2996 if (kstrtoint(opt + 6, 0, &pause)) 2997 goto err; 2998 } else if (!strncmp(opt, "eee_timer:", 10)) { 2999 if (kstrtoint(opt + 10, 0, &eee_timer)) 3000 goto err; 3001 } else if (!strncmp(opt, "chain_mode:", 11)) { 3002 if (kstrtoint(opt + 11, 0, &chain_mode)) 3003 goto err; 3004 } 3005 } 3006 return 0; 3007 3008 err: 3009 pr_err("%s: ERROR broken module parameter conversion", __func__); 3010 return -EINVAL; 3011 } 3012 3013 __setup("stmmaceth=", stmmac_cmdline_opt); 3014 #endif /* MODULE */ 3015 3016 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3017 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3018 MODULE_LICENSE("GPL"); 3019