1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #ifdef CONFIG_STMMAC_DEBUG_FS 47 #include <linux/debugfs.h> 48 #include <linux/seq_file.h> 49 #endif /* CONFIG_STMMAC_DEBUG_FS */ 50 #include <linux/net_tstamp.h> 51 #include "stmmac_ptp.h" 52 #include "stmmac.h" 53 54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 55 #define JUMBO_LEN 9000 56 57 /* Module parameters */ 58 #define TX_TIMEO 5000 59 static int watchdog = TX_TIMEO; 60 module_param(watchdog, int, S_IRUGO | S_IWUSR); 61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 62 63 static int debug = -1; 64 module_param(debug, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 66 67 int phyaddr = -1; 68 module_param(phyaddr, int, S_IRUGO); 69 MODULE_PARM_DESC(phyaddr, "Physical device address"); 70 71 #define DMA_TX_SIZE 256 72 static int dma_txsize = DMA_TX_SIZE; 73 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 74 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 75 76 #define DMA_RX_SIZE 256 77 static int dma_rxsize = DMA_RX_SIZE; 78 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 79 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 80 81 static int flow_ctrl = FLOW_OFF; 82 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 83 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 84 85 static int pause = PAUSE_TIME; 86 module_param(pause, int, S_IRUGO | S_IWUSR); 87 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 88 89 #define TC_DEFAULT 64 90 static int tc = TC_DEFAULT; 91 module_param(tc, int, S_IRUGO | S_IWUSR); 92 MODULE_PARM_DESC(tc, "DMA threshold control value"); 93 94 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB 95 static int buf_sz = DMA_BUFFER_SIZE; 96 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 97 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 98 99 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 100 NETIF_MSG_LINK | NETIF_MSG_IFUP | 101 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 102 103 #define STMMAC_DEFAULT_LPI_TIMER 1000 104 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 105 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 106 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 107 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 108 109 /* By default the driver will use the ring mode to manage tx and rx descriptors 110 * but passing this value so user can force to use the chain instead of the ring 111 */ 112 static unsigned int chain_mode; 113 module_param(chain_mode, int, S_IRUGO); 114 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 115 116 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 117 118 #ifdef CONFIG_STMMAC_DEBUG_FS 119 static int stmmac_init_fs(struct net_device *dev); 120 static void stmmac_exit_fs(void); 121 #endif 122 123 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 124 125 /** 126 * stmmac_verify_args - verify the driver parameters. 127 * Description: it verifies if some wrong parameter is passed to the driver. 128 * Note that wrong parameters are replaced with the default values. 129 */ 130 static void stmmac_verify_args(void) 131 { 132 if (unlikely(watchdog < 0)) 133 watchdog = TX_TIMEO; 134 if (unlikely(dma_rxsize < 0)) 135 dma_rxsize = DMA_RX_SIZE; 136 if (unlikely(dma_txsize < 0)) 137 dma_txsize = DMA_TX_SIZE; 138 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 139 buf_sz = DMA_BUFFER_SIZE; 140 if (unlikely(flow_ctrl > 1)) 141 flow_ctrl = FLOW_AUTO; 142 else if (likely(flow_ctrl < 0)) 143 flow_ctrl = FLOW_OFF; 144 if (unlikely((pause < 0) || (pause > 0xffff))) 145 pause = PAUSE_TIME; 146 if (eee_timer < 0) 147 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 148 } 149 150 /** 151 * stmmac_clk_csr_set - dynamically set the MDC clock 152 * @priv: driver private structure 153 * Description: this is to dynamically set the MDC clock according to the csr 154 * clock input. 155 * Note: 156 * If a specific clk_csr value is passed from the platform 157 * this means that the CSR Clock Range selection cannot be 158 * changed at run-time and it is fixed (as reported in the driver 159 * documentation). Viceversa the driver will try to set the MDC 160 * clock dynamically according to the actual clock input. 161 */ 162 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 163 { 164 u32 clk_rate; 165 166 clk_rate = clk_get_rate(priv->stmmac_clk); 167 168 /* Platform provided default clk_csr would be assumed valid 169 * for all other cases except for the below mentioned ones. 170 * For values higher than the IEEE 802.3 specified frequency 171 * we can not estimate the proper divider as it is not known 172 * the frequency of clk_csr_i. So we do not change the default 173 * divider. 174 */ 175 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 176 if (clk_rate < CSR_F_35M) 177 priv->clk_csr = STMMAC_CSR_20_35M; 178 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 179 priv->clk_csr = STMMAC_CSR_35_60M; 180 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 181 priv->clk_csr = STMMAC_CSR_60_100M; 182 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 183 priv->clk_csr = STMMAC_CSR_100_150M; 184 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 185 priv->clk_csr = STMMAC_CSR_150_250M; 186 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 187 priv->clk_csr = STMMAC_CSR_250_300M; 188 } 189 } 190 191 static void print_pkt(unsigned char *buf, int len) 192 { 193 int j; 194 pr_debug("len = %d byte, buf addr: 0x%p", len, buf); 195 for (j = 0; j < len; j++) { 196 if ((j % 16) == 0) 197 pr_debug("\n %03x:", j); 198 pr_debug(" %02x", buf[j]); 199 } 200 pr_debug("\n"); 201 } 202 203 /* minimum number of free TX descriptors required to wake up TX process */ 204 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 205 206 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 207 { 208 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 209 } 210 211 /** 212 * stmmac_hw_fix_mac_speed: callback for speed selection 213 * @priv: driver private structure 214 * Description: on some platforms (e.g. ST), some HW system configuraton 215 * registers have to be set according to the link speed negotiated. 216 */ 217 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 218 { 219 struct phy_device *phydev = priv->phydev; 220 221 if (likely(priv->plat->fix_mac_speed)) 222 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 223 } 224 225 /** 226 * stmmac_enable_eee_mode: Check and enter in LPI mode 227 * @priv: driver private structure 228 * Description: this function is to verify and enter in LPI mode for EEE. 229 */ 230 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 231 { 232 /* Check and enter in LPI mode */ 233 if ((priv->dirty_tx == priv->cur_tx) && 234 (priv->tx_path_in_lpi_mode == false)) 235 priv->hw->mac->set_eee_mode(priv->ioaddr); 236 } 237 238 /** 239 * stmmac_disable_eee_mode: disable/exit from EEE 240 * @priv: driver private structure 241 * Description: this function is to exit and disable EEE in case of 242 * LPI state is true. This is called by the xmit. 243 */ 244 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 245 { 246 priv->hw->mac->reset_eee_mode(priv->ioaddr); 247 del_timer_sync(&priv->eee_ctrl_timer); 248 priv->tx_path_in_lpi_mode = false; 249 } 250 251 /** 252 * stmmac_eee_ctrl_timer: EEE TX SW timer. 253 * @arg : data hook 254 * Description: 255 * if there is no data transfer and if we are not in LPI state, 256 * then MAC Transmitter can be moved to LPI state. 257 */ 258 static void stmmac_eee_ctrl_timer(unsigned long arg) 259 { 260 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 261 262 stmmac_enable_eee_mode(priv); 263 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 264 } 265 266 /** 267 * stmmac_eee_init: init EEE 268 * @priv: driver private structure 269 * Description: 270 * If the EEE support has been enabled while configuring the driver, 271 * if the GMAC actually supports the EEE (from the HW cap reg) and the 272 * phy can also manage EEE, so enable the LPI state and start the timer 273 * to verify if the tx path can enter in LPI state. 274 */ 275 bool stmmac_eee_init(struct stmmac_priv *priv) 276 { 277 bool ret = false; 278 279 /* Using PCS we cannot dial with the phy registers at this stage 280 * so we do not support extra feature like EEE. 281 */ 282 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 283 (priv->pcs == STMMAC_PCS_RTBI)) 284 goto out; 285 286 /* MAC core supports the EEE feature. */ 287 if (priv->dma_cap.eee) { 288 /* Check if the PHY supports EEE */ 289 if (phy_init_eee(priv->phydev, 1)) 290 goto out; 291 292 if (!priv->eee_active) { 293 priv->eee_active = 1; 294 init_timer(&priv->eee_ctrl_timer); 295 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 296 priv->eee_ctrl_timer.data = (unsigned long)priv; 297 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 298 add_timer(&priv->eee_ctrl_timer); 299 300 priv->hw->mac->set_eee_timer(priv->ioaddr, 301 STMMAC_DEFAULT_LIT_LS, 302 priv->tx_lpi_timer); 303 } else 304 /* Set HW EEE according to the speed */ 305 priv->hw->mac->set_eee_pls(priv->ioaddr, 306 priv->phydev->link); 307 308 pr_info("stmmac: Energy-Efficient Ethernet initialized\n"); 309 310 ret = true; 311 } 312 out: 313 return ret; 314 } 315 316 /* stmmac_get_tx_hwtstamp: get HW TX timestamps 317 * @priv: driver private structure 318 * @entry : descriptor index to be used. 319 * @skb : the socket buffer 320 * Description : 321 * This function will read timestamp from the descriptor & pass it to stack. 322 * and also perform some sanity checks. 323 */ 324 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 325 unsigned int entry, struct sk_buff *skb) 326 { 327 struct skb_shared_hwtstamps shhwtstamp; 328 u64 ns; 329 void *desc = NULL; 330 331 if (!priv->hwts_tx_en) 332 return; 333 334 /* exit if skb doesn't support hw tstamp */ 335 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 336 return; 337 338 if (priv->adv_ts) 339 desc = (priv->dma_etx + entry); 340 else 341 desc = (priv->dma_tx + entry); 342 343 /* check tx tstamp status */ 344 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 345 return; 346 347 /* get the valid tstamp */ 348 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 349 350 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 351 shhwtstamp.hwtstamp = ns_to_ktime(ns); 352 /* pass tstamp to stack */ 353 skb_tstamp_tx(skb, &shhwtstamp); 354 355 return; 356 } 357 358 /* stmmac_get_rx_hwtstamp: get HW RX timestamps 359 * @priv: driver private structure 360 * @entry : descriptor index to be used. 361 * @skb : the socket buffer 362 * Description : 363 * This function will read received packet's timestamp from the descriptor 364 * and pass it to stack. It also perform some sanity checks. 365 */ 366 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 367 unsigned int entry, struct sk_buff *skb) 368 { 369 struct skb_shared_hwtstamps *shhwtstamp = NULL; 370 u64 ns; 371 void *desc = NULL; 372 373 if (!priv->hwts_rx_en) 374 return; 375 376 if (priv->adv_ts) 377 desc = (priv->dma_erx + entry); 378 else 379 desc = (priv->dma_rx + entry); 380 381 /* exit if rx tstamp is not valid */ 382 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 383 return; 384 385 /* get valid tstamp */ 386 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 387 shhwtstamp = skb_hwtstamps(skb); 388 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 389 shhwtstamp->hwtstamp = ns_to_ktime(ns); 390 } 391 392 /** 393 * stmmac_hwtstamp_ioctl - control hardware timestamping. 394 * @dev: device pointer. 395 * @ifr: An IOCTL specefic structure, that can contain a pointer to 396 * a proprietary structure used to pass information to the driver. 397 * Description: 398 * This function configures the MAC to enable/disable both outgoing(TX) 399 * and incoming(RX) packets time stamping based on user input. 400 * Return Value: 401 * 0 on success and an appropriate -ve integer on failure. 402 */ 403 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 404 { 405 struct stmmac_priv *priv = netdev_priv(dev); 406 struct hwtstamp_config config; 407 struct timespec now; 408 u64 temp = 0; 409 u32 ptp_v2 = 0; 410 u32 tstamp_all = 0; 411 u32 ptp_over_ipv4_udp = 0; 412 u32 ptp_over_ipv6_udp = 0; 413 u32 ptp_over_ethernet = 0; 414 u32 snap_type_sel = 0; 415 u32 ts_master_en = 0; 416 u32 ts_event_en = 0; 417 u32 value = 0; 418 419 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 420 netdev_alert(priv->dev, "No support for HW time stamping\n"); 421 priv->hwts_tx_en = 0; 422 priv->hwts_rx_en = 0; 423 424 return -EOPNOTSUPP; 425 } 426 427 if (copy_from_user(&config, ifr->ifr_data, 428 sizeof(struct hwtstamp_config))) 429 return -EFAULT; 430 431 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 432 __func__, config.flags, config.tx_type, config.rx_filter); 433 434 /* reserved for future extensions */ 435 if (config.flags) 436 return -EINVAL; 437 438 switch (config.tx_type) { 439 case HWTSTAMP_TX_OFF: 440 priv->hwts_tx_en = 0; 441 break; 442 case HWTSTAMP_TX_ON: 443 priv->hwts_tx_en = 1; 444 break; 445 default: 446 return -ERANGE; 447 } 448 449 if (priv->adv_ts) { 450 switch (config.rx_filter) { 451 case HWTSTAMP_FILTER_NONE: 452 /* time stamp no incoming packet at all */ 453 config.rx_filter = HWTSTAMP_FILTER_NONE; 454 break; 455 456 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 457 /* PTP v1, UDP, any kind of event packet */ 458 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 459 /* take time stamp for all event messages */ 460 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 461 462 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 463 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 464 break; 465 466 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 467 /* PTP v1, UDP, Sync packet */ 468 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 469 /* take time stamp for SYNC messages only */ 470 ts_event_en = PTP_TCR_TSEVNTENA; 471 472 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 473 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 474 break; 475 476 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 477 /* PTP v1, UDP, Delay_req packet */ 478 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 479 /* take time stamp for Delay_Req messages only */ 480 ts_master_en = PTP_TCR_TSMSTRENA; 481 ts_event_en = PTP_TCR_TSEVNTENA; 482 483 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 484 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 485 break; 486 487 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 488 /* PTP v2, UDP, any kind of event packet */ 489 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 490 ptp_v2 = PTP_TCR_TSVER2ENA; 491 /* take time stamp for all event messages */ 492 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 493 494 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 495 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 496 break; 497 498 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 499 /* PTP v2, UDP, Sync packet */ 500 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 501 ptp_v2 = PTP_TCR_TSVER2ENA; 502 /* take time stamp for SYNC messages only */ 503 ts_event_en = PTP_TCR_TSEVNTENA; 504 505 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 506 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 507 break; 508 509 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 510 /* PTP v2, UDP, Delay_req packet */ 511 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 512 ptp_v2 = PTP_TCR_TSVER2ENA; 513 /* take time stamp for Delay_Req messages only */ 514 ts_master_en = PTP_TCR_TSMSTRENA; 515 ts_event_en = PTP_TCR_TSEVNTENA; 516 517 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 518 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 519 break; 520 521 case HWTSTAMP_FILTER_PTP_V2_EVENT: 522 /* PTP v2/802.AS1 any layer, any kind of event packet */ 523 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 524 ptp_v2 = PTP_TCR_TSVER2ENA; 525 /* take time stamp for all event messages */ 526 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 527 528 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 529 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 530 ptp_over_ethernet = PTP_TCR_TSIPENA; 531 break; 532 533 case HWTSTAMP_FILTER_PTP_V2_SYNC: 534 /* PTP v2/802.AS1, any layer, Sync packet */ 535 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 536 ptp_v2 = PTP_TCR_TSVER2ENA; 537 /* take time stamp for SYNC messages only */ 538 ts_event_en = PTP_TCR_TSEVNTENA; 539 540 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 541 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 542 ptp_over_ethernet = PTP_TCR_TSIPENA; 543 break; 544 545 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 546 /* PTP v2/802.AS1, any layer, Delay_req packet */ 547 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 548 ptp_v2 = PTP_TCR_TSVER2ENA; 549 /* take time stamp for Delay_Req messages only */ 550 ts_master_en = PTP_TCR_TSMSTRENA; 551 ts_event_en = PTP_TCR_TSEVNTENA; 552 553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 555 ptp_over_ethernet = PTP_TCR_TSIPENA; 556 break; 557 558 case HWTSTAMP_FILTER_ALL: 559 /* time stamp any incoming packet */ 560 config.rx_filter = HWTSTAMP_FILTER_ALL; 561 tstamp_all = PTP_TCR_TSENALL; 562 break; 563 564 default: 565 return -ERANGE; 566 } 567 } else { 568 switch (config.rx_filter) { 569 case HWTSTAMP_FILTER_NONE: 570 config.rx_filter = HWTSTAMP_FILTER_NONE; 571 break; 572 default: 573 /* PTP v1, UDP, any kind of event packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 575 break; 576 } 577 } 578 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 579 580 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 581 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 582 else { 583 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 584 tstamp_all | ptp_v2 | ptp_over_ethernet | 585 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 586 ts_master_en | snap_type_sel); 587 588 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 589 590 /* program Sub Second Increment reg */ 591 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 592 593 /* calculate default added value: 594 * formula is : 595 * addend = (2^32)/freq_div_ratio; 596 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz 597 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK; 598 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to 599 * achive 20ns accuracy. 600 * 601 * 2^x * y == (y << x), hence 602 * 2^32 * 50000000 ==> (50000000 << 32) 603 */ 604 temp = (u64) (50000000ULL << 32); 605 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK); 606 priv->hw->ptp->config_addend(priv->ioaddr, 607 priv->default_addend); 608 609 /* initialize system time */ 610 getnstimeofday(&now); 611 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 612 now.tv_nsec); 613 } 614 615 return copy_to_user(ifr->ifr_data, &config, 616 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 617 } 618 619 /** 620 * stmmac_init_ptp: init PTP 621 * @priv: driver private structure 622 * Description: this is to verify if the HW supports the PTPv1 or v2. 623 * This is done by looking at the HW cap. register. 624 * Also it registers the ptp driver. 625 */ 626 static int stmmac_init_ptp(struct stmmac_priv *priv) 627 { 628 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 629 return -EOPNOTSUPP; 630 631 if (netif_msg_hw(priv)) { 632 if (priv->dma_cap.time_stamp) { 633 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 634 priv->adv_ts = 0; 635 } 636 if (priv->dma_cap.atime_stamp && priv->extend_desc) { 637 pr_debug 638 ("IEEE 1588-2008 Advanced Time Stamp supported\n"); 639 priv->adv_ts = 1; 640 } 641 } 642 643 priv->hw->ptp = &stmmac_ptp; 644 priv->hwts_tx_en = 0; 645 priv->hwts_rx_en = 0; 646 647 return stmmac_ptp_register(priv); 648 } 649 650 static void stmmac_release_ptp(struct stmmac_priv *priv) 651 { 652 stmmac_ptp_unregister(priv); 653 } 654 655 /** 656 * stmmac_adjust_link 657 * @dev: net device structure 658 * Description: it adjusts the link parameters. 659 */ 660 static void stmmac_adjust_link(struct net_device *dev) 661 { 662 struct stmmac_priv *priv = netdev_priv(dev); 663 struct phy_device *phydev = priv->phydev; 664 unsigned long flags; 665 int new_state = 0; 666 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 667 668 if (phydev == NULL) 669 return; 670 671 spin_lock_irqsave(&priv->lock, flags); 672 673 if (phydev->link) { 674 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 675 676 /* Now we make sure that we can be in full duplex mode. 677 * If not, we operate in half-duplex mode. */ 678 if (phydev->duplex != priv->oldduplex) { 679 new_state = 1; 680 if (!(phydev->duplex)) 681 ctrl &= ~priv->hw->link.duplex; 682 else 683 ctrl |= priv->hw->link.duplex; 684 priv->oldduplex = phydev->duplex; 685 } 686 /* Flow Control operation */ 687 if (phydev->pause) 688 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 689 fc, pause_time); 690 691 if (phydev->speed != priv->speed) { 692 new_state = 1; 693 switch (phydev->speed) { 694 case 1000: 695 if (likely(priv->plat->has_gmac)) 696 ctrl &= ~priv->hw->link.port; 697 stmmac_hw_fix_mac_speed(priv); 698 break; 699 case 100: 700 case 10: 701 if (priv->plat->has_gmac) { 702 ctrl |= priv->hw->link.port; 703 if (phydev->speed == SPEED_100) { 704 ctrl |= priv->hw->link.speed; 705 } else { 706 ctrl &= ~(priv->hw->link.speed); 707 } 708 } else { 709 ctrl &= ~priv->hw->link.port; 710 } 711 stmmac_hw_fix_mac_speed(priv); 712 break; 713 default: 714 if (netif_msg_link(priv)) 715 pr_warn("%s: Speed (%d) not 10/100\n", 716 dev->name, phydev->speed); 717 break; 718 } 719 720 priv->speed = phydev->speed; 721 } 722 723 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 724 725 if (!priv->oldlink) { 726 new_state = 1; 727 priv->oldlink = 1; 728 } 729 } else if (priv->oldlink) { 730 new_state = 1; 731 priv->oldlink = 0; 732 priv->speed = 0; 733 priv->oldduplex = -1; 734 } 735 736 if (new_state && netif_msg_link(priv)) 737 phy_print_status(phydev); 738 739 /* At this stage, it could be needed to setup the EEE or adjust some 740 * MAC related HW registers. 741 */ 742 priv->eee_enabled = stmmac_eee_init(priv); 743 744 spin_unlock_irqrestore(&priv->lock, flags); 745 } 746 747 /** 748 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported 749 * @priv: driver private structure 750 * Description: this is to verify if the HW supports the PCS. 751 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 752 * configured for the TBI, RTBI, or SGMII PHY interface. 753 */ 754 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 755 { 756 int interface = priv->plat->interface; 757 758 if (priv->dma_cap.pcs) { 759 if ((interface == PHY_INTERFACE_MODE_RGMII) || 760 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 761 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 762 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 763 pr_debug("STMMAC: PCS RGMII support enable\n"); 764 priv->pcs = STMMAC_PCS_RGMII; 765 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 766 pr_debug("STMMAC: PCS SGMII support enable\n"); 767 priv->pcs = STMMAC_PCS_SGMII; 768 } 769 } 770 } 771 772 /** 773 * stmmac_init_phy - PHY initialization 774 * @dev: net device structure 775 * Description: it initializes the driver's PHY state, and attaches the PHY 776 * to the mac driver. 777 * Return value: 778 * 0 on success 779 */ 780 static int stmmac_init_phy(struct net_device *dev) 781 { 782 struct stmmac_priv *priv = netdev_priv(dev); 783 struct phy_device *phydev; 784 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 785 char bus_id[MII_BUS_ID_SIZE]; 786 int interface = priv->plat->interface; 787 priv->oldlink = 0; 788 priv->speed = 0; 789 priv->oldduplex = -1; 790 791 if (priv->plat->phy_bus_name) 792 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 793 priv->plat->phy_bus_name, priv->plat->bus_id); 794 else 795 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 796 priv->plat->bus_id); 797 798 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 799 priv->plat->phy_addr); 800 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 801 802 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 803 804 if (IS_ERR(phydev)) { 805 pr_err("%s: Could not attach to PHY\n", dev->name); 806 return PTR_ERR(phydev); 807 } 808 809 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 810 if ((interface == PHY_INTERFACE_MODE_MII) || 811 (interface == PHY_INTERFACE_MODE_RMII)) 812 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 813 SUPPORTED_1000baseT_Full); 814 815 /* 816 * Broken HW is sometimes missing the pull-up resistor on the 817 * MDIO line, which results in reads to non-existent devices returning 818 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 819 * device as well. 820 * Note: phydev->phy_id is the result of reading the UID PHY registers. 821 */ 822 if (phydev->phy_id == 0) { 823 phy_disconnect(phydev); 824 return -ENODEV; 825 } 826 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 827 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 828 829 priv->phydev = phydev; 830 831 return 0; 832 } 833 834 /** 835 * stmmac_display_ring: display ring 836 * @head: pointer to the head of the ring passed. 837 * @size: size of the ring. 838 * @extend_desc: to verify if extended descriptors are used. 839 * Description: display the control/status and buffer descriptors. 840 */ 841 static void stmmac_display_ring(void *head, int size, int extend_desc) 842 { 843 int i; 844 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 845 struct dma_desc *p = (struct dma_desc *)head; 846 847 for (i = 0; i < size; i++) { 848 u64 x; 849 if (extend_desc) { 850 x = *(u64 *) ep; 851 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 852 i, (unsigned int)virt_to_phys(ep), 853 (unsigned int)x, (unsigned int)(x >> 32), 854 ep->basic.des2, ep->basic.des3); 855 ep++; 856 } else { 857 x = *(u64 *) p; 858 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 859 i, (unsigned int)virt_to_phys(p), 860 (unsigned int)x, (unsigned int)(x >> 32), 861 p->des2, p->des3); 862 p++; 863 } 864 pr_info("\n"); 865 } 866 } 867 868 static void stmmac_display_rings(struct stmmac_priv *priv) 869 { 870 unsigned int txsize = priv->dma_tx_size; 871 unsigned int rxsize = priv->dma_rx_size; 872 873 if (priv->extend_desc) { 874 pr_info("Extended RX descriptor ring:\n"); 875 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 876 pr_info("Extended TX descriptor ring:\n"); 877 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 878 } else { 879 pr_info("RX descriptor ring:\n"); 880 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 881 pr_info("TX descriptor ring:\n"); 882 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 883 } 884 } 885 886 static int stmmac_set_bfsize(int mtu, int bufsize) 887 { 888 int ret = bufsize; 889 890 if (mtu >= BUF_SIZE_4KiB) 891 ret = BUF_SIZE_8KiB; 892 else if (mtu >= BUF_SIZE_2KiB) 893 ret = BUF_SIZE_4KiB; 894 else if (mtu >= DMA_BUFFER_SIZE) 895 ret = BUF_SIZE_2KiB; 896 else 897 ret = DMA_BUFFER_SIZE; 898 899 return ret; 900 } 901 902 /** 903 * stmmac_clear_descriptors: clear descriptors 904 * @priv: driver private structure 905 * Description: this function is called to clear the tx and rx descriptors 906 * in case of both basic and extended descriptors are used. 907 */ 908 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 909 { 910 int i; 911 unsigned int txsize = priv->dma_tx_size; 912 unsigned int rxsize = priv->dma_rx_size; 913 914 /* Clear the Rx/Tx descriptors */ 915 for (i = 0; i < rxsize; i++) 916 if (priv->extend_desc) 917 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 918 priv->use_riwt, priv->mode, 919 (i == rxsize - 1)); 920 else 921 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 922 priv->use_riwt, priv->mode, 923 (i == rxsize - 1)); 924 for (i = 0; i < txsize; i++) 925 if (priv->extend_desc) 926 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 927 priv->mode, 928 (i == txsize - 1)); 929 else 930 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 931 priv->mode, 932 (i == txsize - 1)); 933 } 934 935 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 936 int i) 937 { 938 struct sk_buff *skb; 939 940 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 941 GFP_KERNEL); 942 if (unlikely(skb == NULL)) { 943 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 944 return 1; 945 } 946 skb_reserve(skb, NET_IP_ALIGN); 947 priv->rx_skbuff[i] = skb; 948 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 949 priv->dma_buf_sz, 950 DMA_FROM_DEVICE); 951 952 p->des2 = priv->rx_skbuff_dma[i]; 953 954 if ((priv->mode == STMMAC_RING_MODE) && 955 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 956 priv->hw->ring->init_desc3(p); 957 958 return 0; 959 } 960 961 /** 962 * init_dma_desc_rings - init the RX/TX descriptor rings 963 * @dev: net device structure 964 * Description: this function initializes the DMA RX/TX descriptors 965 * and allocates the socket buffers. It suppors the chained and ring 966 * modes. 967 */ 968 static void init_dma_desc_rings(struct net_device *dev) 969 { 970 int i; 971 struct stmmac_priv *priv = netdev_priv(dev); 972 unsigned int txsize = priv->dma_tx_size; 973 unsigned int rxsize = priv->dma_rx_size; 974 unsigned int bfsize = 0; 975 976 /* Set the max buffer size according to the DESC mode 977 * and the MTU. Note that RING mode allows 16KiB bsize. 978 */ 979 if (priv->mode == STMMAC_RING_MODE) 980 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 981 982 if (bfsize < BUF_SIZE_16KiB) 983 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 984 985 if (netif_msg_probe(priv)) 986 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 987 txsize, rxsize, bfsize); 988 989 if (priv->extend_desc) { 990 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 991 sizeof(struct 992 dma_extended_desc), 993 &priv->dma_rx_phy, 994 GFP_KERNEL); 995 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 996 sizeof(struct 997 dma_extended_desc), 998 &priv->dma_tx_phy, 999 GFP_KERNEL); 1000 if ((!priv->dma_erx) || (!priv->dma_etx)) 1001 return; 1002 } else { 1003 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1004 sizeof(struct dma_desc), 1005 &priv->dma_rx_phy, 1006 GFP_KERNEL); 1007 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1008 sizeof(struct dma_desc), 1009 &priv->dma_tx_phy, 1010 GFP_KERNEL); 1011 if ((!priv->dma_rx) || (!priv->dma_tx)) 1012 return; 1013 } 1014 1015 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1016 GFP_KERNEL); 1017 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1018 GFP_KERNEL); 1019 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t), 1020 GFP_KERNEL); 1021 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1022 GFP_KERNEL); 1023 if (netif_msg_probe(priv)) { 1024 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1025 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1026 1027 /* RX INITIALIZATION */ 1028 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1029 } 1030 for (i = 0; i < rxsize; i++) { 1031 struct dma_desc *p; 1032 if (priv->extend_desc) 1033 p = &((priv->dma_erx + i)->basic); 1034 else 1035 p = priv->dma_rx + i; 1036 1037 if (stmmac_init_rx_buffers(priv, p, i)) 1038 break; 1039 1040 if (netif_msg_probe(priv)) 1041 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1042 priv->rx_skbuff[i]->data, 1043 (unsigned int)priv->rx_skbuff_dma[i]); 1044 } 1045 priv->cur_rx = 0; 1046 priv->dirty_rx = (unsigned int)(i - rxsize); 1047 priv->dma_buf_sz = bfsize; 1048 buf_sz = bfsize; 1049 1050 /* Setup the chained descriptor addresses */ 1051 if (priv->mode == STMMAC_CHAIN_MODE) { 1052 if (priv->extend_desc) { 1053 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy, 1054 rxsize, 1); 1055 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy, 1056 txsize, 1); 1057 } else { 1058 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy, 1059 rxsize, 0); 1060 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy, 1061 txsize, 0); 1062 } 1063 } 1064 1065 /* TX INITIALIZATION */ 1066 for (i = 0; i < txsize; i++) { 1067 struct dma_desc *p; 1068 if (priv->extend_desc) 1069 p = &((priv->dma_etx + i)->basic); 1070 else 1071 p = priv->dma_tx + i; 1072 p->des2 = 0; 1073 priv->tx_skbuff_dma[i] = 0; 1074 priv->tx_skbuff[i] = NULL; 1075 } 1076 1077 priv->dirty_tx = 0; 1078 priv->cur_tx = 0; 1079 1080 stmmac_clear_descriptors(priv); 1081 1082 if (netif_msg_hw(priv)) 1083 stmmac_display_rings(priv); 1084 } 1085 1086 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1087 { 1088 int i; 1089 1090 for (i = 0; i < priv->dma_rx_size; i++) { 1091 if (priv->rx_skbuff[i]) { 1092 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1093 priv->dma_buf_sz, DMA_FROM_DEVICE); 1094 dev_kfree_skb_any(priv->rx_skbuff[i]); 1095 } 1096 priv->rx_skbuff[i] = NULL; 1097 } 1098 } 1099 1100 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1101 { 1102 int i; 1103 1104 for (i = 0; i < priv->dma_tx_size; i++) { 1105 if (priv->tx_skbuff[i] != NULL) { 1106 struct dma_desc *p; 1107 if (priv->extend_desc) 1108 p = &((priv->dma_etx + i)->basic); 1109 else 1110 p = priv->dma_tx + i; 1111 1112 if (priv->tx_skbuff_dma[i]) 1113 dma_unmap_single(priv->device, 1114 priv->tx_skbuff_dma[i], 1115 priv->hw->desc->get_tx_len(p), 1116 DMA_TO_DEVICE); 1117 dev_kfree_skb_any(priv->tx_skbuff[i]); 1118 priv->tx_skbuff[i] = NULL; 1119 priv->tx_skbuff_dma[i] = 0; 1120 } 1121 } 1122 } 1123 1124 static void free_dma_desc_resources(struct stmmac_priv *priv) 1125 { 1126 /* Release the DMA TX/RX socket buffers */ 1127 dma_free_rx_skbufs(priv); 1128 dma_free_tx_skbufs(priv); 1129 1130 /* Free DMA regions of consistent memory previously allocated */ 1131 if (!priv->extend_desc) { 1132 dma_free_coherent(priv->device, 1133 priv->dma_tx_size * sizeof(struct dma_desc), 1134 priv->dma_tx, priv->dma_tx_phy); 1135 dma_free_coherent(priv->device, 1136 priv->dma_rx_size * sizeof(struct dma_desc), 1137 priv->dma_rx, priv->dma_rx_phy); 1138 } else { 1139 dma_free_coherent(priv->device, priv->dma_tx_size * 1140 sizeof(struct dma_extended_desc), 1141 priv->dma_etx, priv->dma_tx_phy); 1142 dma_free_coherent(priv->device, priv->dma_rx_size * 1143 sizeof(struct dma_extended_desc), 1144 priv->dma_erx, priv->dma_rx_phy); 1145 } 1146 kfree(priv->rx_skbuff_dma); 1147 kfree(priv->rx_skbuff); 1148 kfree(priv->tx_skbuff_dma); 1149 kfree(priv->tx_skbuff); 1150 } 1151 1152 /** 1153 * stmmac_dma_operation_mode - HW DMA operation mode 1154 * @priv: driver private structure 1155 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 1156 * or Store-And-Forward capability. 1157 */ 1158 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1159 { 1160 if (likely(priv->plat->force_sf_dma_mode || 1161 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { 1162 /* 1163 * In case of GMAC, SF mode can be enabled 1164 * to perform the TX COE in HW. This depends on: 1165 * 1) TX COE if actually supported 1166 * 2) There is no bugged Jumbo frame support 1167 * that needs to not insert csum in the TDES. 1168 */ 1169 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1170 tc = SF_DMA_MODE; 1171 } else 1172 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1173 } 1174 1175 /** 1176 * stmmac_tx_clean: 1177 * @priv: driver private structure 1178 * Description: it reclaims resources after transmission completes. 1179 */ 1180 static void stmmac_tx_clean(struct stmmac_priv *priv) 1181 { 1182 unsigned int txsize = priv->dma_tx_size; 1183 1184 spin_lock(&priv->tx_lock); 1185 1186 priv->xstats.tx_clean++; 1187 1188 while (priv->dirty_tx != priv->cur_tx) { 1189 int last; 1190 unsigned int entry = priv->dirty_tx % txsize; 1191 struct sk_buff *skb = priv->tx_skbuff[entry]; 1192 struct dma_desc *p; 1193 1194 if (priv->extend_desc) 1195 p = (struct dma_desc *)(priv->dma_etx + entry); 1196 else 1197 p = priv->dma_tx + entry; 1198 1199 /* Check if the descriptor is owned by the DMA. */ 1200 if (priv->hw->desc->get_tx_owner(p)) 1201 break; 1202 1203 /* Verify tx error by looking at the last segment. */ 1204 last = priv->hw->desc->get_tx_ls(p); 1205 if (likely(last)) { 1206 int tx_error = 1207 priv->hw->desc->tx_status(&priv->dev->stats, 1208 &priv->xstats, p, 1209 priv->ioaddr); 1210 if (likely(tx_error == 0)) { 1211 priv->dev->stats.tx_packets++; 1212 priv->xstats.tx_pkt_n++; 1213 } else 1214 priv->dev->stats.tx_errors++; 1215 1216 stmmac_get_tx_hwtstamp(priv, entry, skb); 1217 } 1218 if (netif_msg_tx_done(priv)) 1219 pr_debug("%s: curr %d, dirty %d\n", __func__, 1220 priv->cur_tx, priv->dirty_tx); 1221 1222 if (likely(priv->tx_skbuff_dma[entry])) { 1223 dma_unmap_single(priv->device, 1224 priv->tx_skbuff_dma[entry], 1225 priv->hw->desc->get_tx_len(p), 1226 DMA_TO_DEVICE); 1227 priv->tx_skbuff_dma[entry] = 0; 1228 } 1229 priv->hw->ring->clean_desc3(priv, p); 1230 1231 if (likely(skb != NULL)) { 1232 dev_kfree_skb(skb); 1233 priv->tx_skbuff[entry] = NULL; 1234 } 1235 1236 priv->hw->desc->release_tx_desc(p, priv->mode); 1237 1238 priv->dirty_tx++; 1239 } 1240 if (unlikely(netif_queue_stopped(priv->dev) && 1241 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1242 netif_tx_lock(priv->dev); 1243 if (netif_queue_stopped(priv->dev) && 1244 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1245 if (netif_msg_tx_done(priv)) 1246 pr_debug("%s: restart transmit\n", __func__); 1247 netif_wake_queue(priv->dev); 1248 } 1249 netif_tx_unlock(priv->dev); 1250 } 1251 1252 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1253 stmmac_enable_eee_mode(priv); 1254 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1255 } 1256 spin_unlock(&priv->tx_lock); 1257 } 1258 1259 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1260 { 1261 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1262 } 1263 1264 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1265 { 1266 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1267 } 1268 1269 /** 1270 * stmmac_tx_err: irq tx error mng function 1271 * @priv: driver private structure 1272 * Description: it cleans the descriptors and restarts the transmission 1273 * in case of errors. 1274 */ 1275 static void stmmac_tx_err(struct stmmac_priv *priv) 1276 { 1277 int i; 1278 int txsize = priv->dma_tx_size; 1279 netif_stop_queue(priv->dev); 1280 1281 priv->hw->dma->stop_tx(priv->ioaddr); 1282 dma_free_tx_skbufs(priv); 1283 for (i = 0; i < txsize; i++) 1284 if (priv->extend_desc) 1285 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1286 priv->mode, 1287 (i == txsize - 1)); 1288 else 1289 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1290 priv->mode, 1291 (i == txsize - 1)); 1292 priv->dirty_tx = 0; 1293 priv->cur_tx = 0; 1294 priv->hw->dma->start_tx(priv->ioaddr); 1295 1296 priv->dev->stats.tx_errors++; 1297 netif_wake_queue(priv->dev); 1298 } 1299 1300 /** 1301 * stmmac_dma_interrupt: DMA ISR 1302 * @priv: driver private structure 1303 * Description: this is the DMA ISR. It is called by the main ISR. 1304 * It calls the dwmac dma routine to understand which type of interrupt 1305 * happened. In case of there is a Normal interrupt and either TX or RX 1306 * interrupt happened so the NAPI is scheduled. 1307 */ 1308 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1309 { 1310 int status; 1311 1312 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1313 if (likely((status & handle_rx)) || (status & handle_tx)) { 1314 if (likely(napi_schedule_prep(&priv->napi))) { 1315 stmmac_disable_dma_irq(priv); 1316 __napi_schedule(&priv->napi); 1317 } 1318 } 1319 if (unlikely(status & tx_hard_error_bump_tc)) { 1320 /* Try to bump up the dma threshold on this failure */ 1321 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1322 tc += 64; 1323 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1324 priv->xstats.threshold = tc; 1325 } 1326 } else if (unlikely(status == tx_hard_error)) 1327 stmmac_tx_err(priv); 1328 } 1329 1330 /** 1331 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1332 * @priv: driver private structure 1333 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1334 */ 1335 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1336 { 1337 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1338 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1339 1340 dwmac_mmc_intr_all_mask(priv->ioaddr); 1341 1342 if (priv->dma_cap.rmon) { 1343 dwmac_mmc_ctrl(priv->ioaddr, mode); 1344 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1345 } else 1346 pr_info(" No MAC Management Counters available\n"); 1347 } 1348 1349 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1350 { 1351 u32 hwid = priv->hw->synopsys_uid; 1352 1353 /* Check Synopsys Id (not available on old chips) */ 1354 if (likely(hwid)) { 1355 u32 uid = ((hwid & 0x0000ff00) >> 8); 1356 u32 synid = (hwid & 0x000000ff); 1357 1358 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1359 uid, synid); 1360 1361 return synid; 1362 } 1363 return 0; 1364 } 1365 1366 /** 1367 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors 1368 * @priv: driver private structure 1369 * Description: select the Enhanced/Alternate or Normal descriptors. 1370 * In case of Enhanced/Alternate, it looks at the extended descriptors are 1371 * supported by the HW cap. register. 1372 */ 1373 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1374 { 1375 if (priv->plat->enh_desc) { 1376 pr_info(" Enhanced/Alternate descriptors\n"); 1377 1378 /* GMAC older than 3.50 has no extended descriptors */ 1379 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1380 pr_info("\tEnabled extended descriptors\n"); 1381 priv->extend_desc = 1; 1382 } else 1383 pr_warn("Extended descriptors not supported\n"); 1384 1385 priv->hw->desc = &enh_desc_ops; 1386 } else { 1387 pr_info(" Normal descriptors\n"); 1388 priv->hw->desc = &ndesc_ops; 1389 } 1390 } 1391 1392 /** 1393 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. 1394 * @priv: driver private structure 1395 * Description: 1396 * new GMAC chip generations have a new register to indicate the 1397 * presence of the optional feature/functions. 1398 * This can be also used to override the value passed through the 1399 * platform and necessary for old MAC10/100 and GMAC chips. 1400 */ 1401 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1402 { 1403 u32 hw_cap = 0; 1404 1405 if (priv->hw->dma->get_hw_feature) { 1406 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1407 1408 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1409 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1410 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1411 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1412 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1413 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1414 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1415 priv->dma_cap.pmt_remote_wake_up = 1416 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1417 priv->dma_cap.pmt_magic_frame = 1418 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1419 /* MMC */ 1420 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1421 /* IEEE 1588-2002 */ 1422 priv->dma_cap.time_stamp = 1423 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1424 /* IEEE 1588-2008 */ 1425 priv->dma_cap.atime_stamp = 1426 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1427 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1428 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1429 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1430 /* TX and RX csum */ 1431 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1432 priv->dma_cap.rx_coe_type1 = 1433 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1434 priv->dma_cap.rx_coe_type2 = 1435 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1436 priv->dma_cap.rxfifo_over_2048 = 1437 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1438 /* TX and RX number of channels */ 1439 priv->dma_cap.number_rx_channel = 1440 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1441 priv->dma_cap.number_tx_channel = 1442 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1443 /* Alternate (enhanced) DESC mode */ 1444 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1445 } 1446 1447 return hw_cap; 1448 } 1449 1450 /** 1451 * stmmac_check_ether_addr: check if the MAC addr is valid 1452 * @priv: driver private structure 1453 * Description: 1454 * it is to verify if the MAC address is valid, in case of failures it 1455 * generates a random MAC address 1456 */ 1457 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1458 { 1459 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1460 priv->hw->mac->get_umac_addr((void __iomem *) 1461 priv->dev->base_addr, 1462 priv->dev->dev_addr, 0); 1463 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1464 eth_hw_addr_random(priv->dev); 1465 } 1466 pr_warn("%s: device MAC address %pM\n", priv->dev->name, 1467 priv->dev->dev_addr); 1468 } 1469 1470 /** 1471 * stmmac_init_dma_engine: DMA init. 1472 * @priv: driver private structure 1473 * Description: 1474 * It inits the DMA invoking the specific MAC/GMAC callback. 1475 * Some DMA parameters can be passed from the platform; 1476 * in case of these are not passed a default is kept for the MAC or GMAC. 1477 */ 1478 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1479 { 1480 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1481 int mixed_burst = 0; 1482 int atds = 0; 1483 1484 if (priv->plat->dma_cfg) { 1485 pbl = priv->plat->dma_cfg->pbl; 1486 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1487 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1488 burst_len = priv->plat->dma_cfg->burst_len; 1489 } 1490 1491 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1492 atds = 1; 1493 1494 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1495 burst_len, priv->dma_tx_phy, 1496 priv->dma_rx_phy, atds); 1497 } 1498 1499 /** 1500 * stmmac_tx_timer: mitigation sw timer for tx. 1501 * @data: data pointer 1502 * Description: 1503 * This is the timer handler to directly invoke the stmmac_tx_clean. 1504 */ 1505 static void stmmac_tx_timer(unsigned long data) 1506 { 1507 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1508 1509 stmmac_tx_clean(priv); 1510 } 1511 1512 /** 1513 * stmmac_init_tx_coalesce: init tx mitigation options. 1514 * @priv: driver private structure 1515 * Description: 1516 * This inits the transmit coalesce parameters: i.e. timer rate, 1517 * timer handler and default threshold used for enabling the 1518 * interrupt on completion bit. 1519 */ 1520 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1521 { 1522 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1523 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1524 init_timer(&priv->txtimer); 1525 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1526 priv->txtimer.data = (unsigned long)priv; 1527 priv->txtimer.function = stmmac_tx_timer; 1528 add_timer(&priv->txtimer); 1529 } 1530 1531 /** 1532 * stmmac_open - open entry point of the driver 1533 * @dev : pointer to the device structure. 1534 * Description: 1535 * This function is the open entry point of the driver. 1536 * Return value: 1537 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1538 * file on failure. 1539 */ 1540 static int stmmac_open(struct net_device *dev) 1541 { 1542 struct stmmac_priv *priv = netdev_priv(dev); 1543 int ret; 1544 1545 clk_prepare_enable(priv->stmmac_clk); 1546 1547 stmmac_check_ether_addr(priv); 1548 1549 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1550 priv->pcs != STMMAC_PCS_RTBI) { 1551 ret = stmmac_init_phy(dev); 1552 if (ret) { 1553 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1554 __func__, ret); 1555 goto phy_error; 1556 } 1557 } 1558 1559 /* Create and initialize the TX/RX descriptors chains. */ 1560 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1561 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1562 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1563 init_dma_desc_rings(dev); 1564 1565 /* DMA initialization and SW reset */ 1566 ret = stmmac_init_dma_engine(priv); 1567 if (ret < 0) { 1568 pr_err("%s: DMA initialization failed\n", __func__); 1569 goto init_error; 1570 } 1571 1572 /* Copy the MAC addr into the HW */ 1573 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1574 1575 /* If required, perform hw setup of the bus. */ 1576 if (priv->plat->bus_setup) 1577 priv->plat->bus_setup(priv->ioaddr); 1578 1579 /* Initialize the MAC Core */ 1580 priv->hw->mac->core_init(priv->ioaddr); 1581 1582 /* Request the IRQ lines */ 1583 ret = request_irq(dev->irq, stmmac_interrupt, 1584 IRQF_SHARED, dev->name, dev); 1585 if (unlikely(ret < 0)) { 1586 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1587 __func__, dev->irq, ret); 1588 goto init_error; 1589 } 1590 1591 /* Request the Wake IRQ in case of another line is used for WoL */ 1592 if (priv->wol_irq != dev->irq) { 1593 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1594 IRQF_SHARED, dev->name, dev); 1595 if (unlikely(ret < 0)) { 1596 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1597 __func__, priv->wol_irq, ret); 1598 goto wolirq_error; 1599 } 1600 } 1601 1602 /* Request the IRQ lines */ 1603 if (priv->lpi_irq != -ENXIO) { 1604 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1605 dev->name, dev); 1606 if (unlikely(ret < 0)) { 1607 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1608 __func__, priv->lpi_irq, ret); 1609 goto lpiirq_error; 1610 } 1611 } 1612 1613 /* Enable the MAC Rx/Tx */ 1614 stmmac_set_mac(priv->ioaddr, true); 1615 1616 /* Set the HW DMA mode and the COE */ 1617 stmmac_dma_operation_mode(priv); 1618 1619 /* Extra statistics */ 1620 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1621 priv->xstats.threshold = tc; 1622 1623 stmmac_mmc_setup(priv); 1624 1625 ret = stmmac_init_ptp(priv); 1626 if (ret) 1627 pr_warn("%s: failed PTP initialisation\n", __func__); 1628 1629 #ifdef CONFIG_STMMAC_DEBUG_FS 1630 ret = stmmac_init_fs(dev); 1631 if (ret < 0) 1632 pr_warn("%s: failed debugFS registration\n", __func__); 1633 #endif 1634 /* Start the ball rolling... */ 1635 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1636 priv->hw->dma->start_tx(priv->ioaddr); 1637 priv->hw->dma->start_rx(priv->ioaddr); 1638 1639 /* Dump DMA/MAC registers */ 1640 if (netif_msg_hw(priv)) { 1641 priv->hw->mac->dump_regs(priv->ioaddr); 1642 priv->hw->dma->dump_regs(priv->ioaddr); 1643 } 1644 1645 if (priv->phydev) 1646 phy_start(priv->phydev); 1647 1648 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1649 1650 priv->eee_enabled = stmmac_eee_init(priv); 1651 1652 stmmac_init_tx_coalesce(priv); 1653 1654 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1655 priv->rx_riwt = MAX_DMA_RIWT; 1656 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1657 } 1658 1659 if (priv->pcs && priv->hw->mac->ctrl_ane) 1660 priv->hw->mac->ctrl_ane(priv->ioaddr, 0); 1661 1662 napi_enable(&priv->napi); 1663 netif_start_queue(dev); 1664 1665 return 0; 1666 1667 lpiirq_error: 1668 if (priv->wol_irq != dev->irq) 1669 free_irq(priv->wol_irq, dev); 1670 wolirq_error: 1671 free_irq(dev->irq, dev); 1672 1673 init_error: 1674 free_dma_desc_resources(priv); 1675 if (priv->phydev) 1676 phy_disconnect(priv->phydev); 1677 phy_error: 1678 clk_disable_unprepare(priv->stmmac_clk); 1679 1680 return ret; 1681 } 1682 1683 /** 1684 * stmmac_release - close entry point of the driver 1685 * @dev : device pointer. 1686 * Description: 1687 * This is the stop entry point of the driver. 1688 */ 1689 static int stmmac_release(struct net_device *dev) 1690 { 1691 struct stmmac_priv *priv = netdev_priv(dev); 1692 1693 if (priv->eee_enabled) 1694 del_timer_sync(&priv->eee_ctrl_timer); 1695 1696 /* Stop and disconnect the PHY */ 1697 if (priv->phydev) { 1698 phy_stop(priv->phydev); 1699 phy_disconnect(priv->phydev); 1700 priv->phydev = NULL; 1701 } 1702 1703 netif_stop_queue(dev); 1704 1705 napi_disable(&priv->napi); 1706 1707 del_timer_sync(&priv->txtimer); 1708 1709 /* Free the IRQ lines */ 1710 free_irq(dev->irq, dev); 1711 if (priv->wol_irq != dev->irq) 1712 free_irq(priv->wol_irq, dev); 1713 if (priv->lpi_irq != -ENXIO) 1714 free_irq(priv->lpi_irq, dev); 1715 1716 /* Stop TX/RX DMA and clear the descriptors */ 1717 priv->hw->dma->stop_tx(priv->ioaddr); 1718 priv->hw->dma->stop_rx(priv->ioaddr); 1719 1720 /* Release and free the Rx/Tx resources */ 1721 free_dma_desc_resources(priv); 1722 1723 /* Disable the MAC Rx/Tx */ 1724 stmmac_set_mac(priv->ioaddr, false); 1725 1726 netif_carrier_off(dev); 1727 1728 #ifdef CONFIG_STMMAC_DEBUG_FS 1729 stmmac_exit_fs(); 1730 #endif 1731 clk_disable_unprepare(priv->stmmac_clk); 1732 1733 stmmac_release_ptp(priv); 1734 1735 return 0; 1736 } 1737 1738 /** 1739 * stmmac_xmit: Tx entry point of the driver 1740 * @skb : the socket buffer 1741 * @dev : device pointer 1742 * Description : this is the tx entry point of the driver. 1743 * It programs the chain or the ring and supports oversized frames 1744 * and SG feature. 1745 */ 1746 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1747 { 1748 struct stmmac_priv *priv = netdev_priv(dev); 1749 unsigned int txsize = priv->dma_tx_size; 1750 unsigned int entry; 1751 int i, csum_insertion = 0, is_jumbo = 0; 1752 int nfrags = skb_shinfo(skb)->nr_frags; 1753 struct dma_desc *desc, *first; 1754 unsigned int nopaged_len = skb_headlen(skb); 1755 1756 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1757 if (!netif_queue_stopped(dev)) { 1758 netif_stop_queue(dev); 1759 /* This is a hard error, log it. */ 1760 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1761 } 1762 return NETDEV_TX_BUSY; 1763 } 1764 1765 spin_lock(&priv->tx_lock); 1766 1767 if (priv->tx_path_in_lpi_mode) 1768 stmmac_disable_eee_mode(priv); 1769 1770 entry = priv->cur_tx % txsize; 1771 1772 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1773 1774 if (priv->extend_desc) 1775 desc = (struct dma_desc *)(priv->dma_etx + entry); 1776 else 1777 desc = priv->dma_tx + entry; 1778 1779 first = desc; 1780 1781 priv->tx_skbuff[entry] = skb; 1782 1783 /* To program the descriptors according to the size of the frame */ 1784 if (priv->mode == STMMAC_RING_MODE) { 1785 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len, 1786 priv->plat->enh_desc); 1787 if (unlikely(is_jumbo)) 1788 entry = priv->hw->ring->jumbo_frm(priv, skb, 1789 csum_insertion); 1790 } else { 1791 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len, 1792 priv->plat->enh_desc); 1793 if (unlikely(is_jumbo)) 1794 entry = priv->hw->chain->jumbo_frm(priv, skb, 1795 csum_insertion); 1796 } 1797 if (likely(!is_jumbo)) { 1798 desc->des2 = dma_map_single(priv->device, skb->data, 1799 nopaged_len, DMA_TO_DEVICE); 1800 priv->tx_skbuff_dma[entry] = desc->des2; 1801 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1802 csum_insertion, priv->mode); 1803 } else 1804 desc = first; 1805 1806 for (i = 0; i < nfrags; i++) { 1807 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1808 int len = skb_frag_size(frag); 1809 1810 entry = (++priv->cur_tx) % txsize; 1811 if (priv->extend_desc) 1812 desc = (struct dma_desc *)(priv->dma_etx + entry); 1813 else 1814 desc = priv->dma_tx + entry; 1815 1816 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1817 DMA_TO_DEVICE); 1818 priv->tx_skbuff_dma[entry] = desc->des2; 1819 priv->tx_skbuff[entry] = NULL; 1820 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1821 priv->mode); 1822 wmb(); 1823 priv->hw->desc->set_tx_owner(desc); 1824 wmb(); 1825 } 1826 1827 /* Finalize the latest segment. */ 1828 priv->hw->desc->close_tx_desc(desc); 1829 1830 wmb(); 1831 /* According to the coalesce parameter the IC bit for the latest 1832 * segment could be reset and the timer re-started to invoke the 1833 * stmmac_tx function. This approach takes care about the fragments. 1834 */ 1835 priv->tx_count_frames += nfrags + 1; 1836 if (priv->tx_coal_frames > priv->tx_count_frames) { 1837 priv->hw->desc->clear_tx_ic(desc); 1838 priv->xstats.tx_reset_ic_bit++; 1839 mod_timer(&priv->txtimer, 1840 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1841 } else 1842 priv->tx_count_frames = 0; 1843 1844 /* To avoid raise condition */ 1845 priv->hw->desc->set_tx_owner(first); 1846 wmb(); 1847 1848 priv->cur_tx++; 1849 1850 if (netif_msg_pktdata(priv)) { 1851 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 1852 __func__, (priv->cur_tx % txsize), 1853 (priv->dirty_tx % txsize), entry, first, nfrags); 1854 1855 if (priv->extend_desc) 1856 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 1857 else 1858 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 1859 1860 pr_debug(">>> frame to be transmitted: "); 1861 print_pkt(skb->data, skb->len); 1862 } 1863 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1864 if (netif_msg_hw(priv)) 1865 pr_debug("%s: stop transmitted packets\n", __func__); 1866 netif_stop_queue(dev); 1867 } 1868 1869 dev->stats.tx_bytes += skb->len; 1870 1871 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1872 priv->hwts_tx_en)) { 1873 /* declare that device is doing timestamping */ 1874 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1875 priv->hw->desc->enable_tx_timestamp(first); 1876 } 1877 1878 if (!priv->hwts_tx_en) 1879 skb_tx_timestamp(skb); 1880 1881 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1882 1883 spin_unlock(&priv->tx_lock); 1884 1885 return NETDEV_TX_OK; 1886 } 1887 1888 /** 1889 * stmmac_rx_refill: refill used skb preallocated buffers 1890 * @priv: driver private structure 1891 * Description : this is to reallocate the skb for the reception process 1892 * that is based on zero-copy. 1893 */ 1894 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 1895 { 1896 unsigned int rxsize = priv->dma_rx_size; 1897 int bfsize = priv->dma_buf_sz; 1898 1899 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 1900 unsigned int entry = priv->dirty_rx % rxsize; 1901 struct dma_desc *p; 1902 1903 if (priv->extend_desc) 1904 p = (struct dma_desc *)(priv->dma_erx + entry); 1905 else 1906 p = priv->dma_rx + entry; 1907 1908 if (likely(priv->rx_skbuff[entry] == NULL)) { 1909 struct sk_buff *skb; 1910 1911 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 1912 1913 if (unlikely(skb == NULL)) 1914 break; 1915 1916 priv->rx_skbuff[entry] = skb; 1917 priv->rx_skbuff_dma[entry] = 1918 dma_map_single(priv->device, skb->data, bfsize, 1919 DMA_FROM_DEVICE); 1920 1921 p->des2 = priv->rx_skbuff_dma[entry]; 1922 1923 priv->hw->ring->refill_desc3(priv, p); 1924 1925 if (netif_msg_rx_status(priv)) 1926 pr_debug("\trefill entry #%d\n", entry); 1927 } 1928 wmb(); 1929 priv->hw->desc->set_rx_owner(p); 1930 wmb(); 1931 } 1932 } 1933 1934 /** 1935 * stmmac_rx_refill: refill used skb preallocated buffers 1936 * @priv: driver private structure 1937 * @limit: napi bugget. 1938 * Description : this the function called by the napi poll method. 1939 * It gets all the frames inside the ring. 1940 */ 1941 static int stmmac_rx(struct stmmac_priv *priv, int limit) 1942 { 1943 unsigned int rxsize = priv->dma_rx_size; 1944 unsigned int entry = priv->cur_rx % rxsize; 1945 unsigned int next_entry; 1946 unsigned int count = 0; 1947 int coe = priv->plat->rx_coe; 1948 1949 if (netif_msg_rx_status(priv)) { 1950 pr_debug("%s: descriptor ring:\n", __func__); 1951 if (priv->extend_desc) 1952 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 1953 else 1954 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 1955 } 1956 while (count < limit) { 1957 int status; 1958 struct dma_desc *p; 1959 1960 if (priv->extend_desc) 1961 p = (struct dma_desc *)(priv->dma_erx + entry); 1962 else 1963 p = priv->dma_rx + entry; 1964 1965 if (priv->hw->desc->get_rx_owner(p)) 1966 break; 1967 1968 count++; 1969 1970 next_entry = (++priv->cur_rx) % rxsize; 1971 if (priv->extend_desc) 1972 prefetch(priv->dma_erx + next_entry); 1973 else 1974 prefetch(priv->dma_rx + next_entry); 1975 1976 /* read the status of the incoming frame */ 1977 status = priv->hw->desc->rx_status(&priv->dev->stats, 1978 &priv->xstats, p); 1979 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 1980 priv->hw->desc->rx_extended_status(&priv->dev->stats, 1981 &priv->xstats, 1982 priv->dma_erx + 1983 entry); 1984 if (unlikely(status == discard_frame)) { 1985 priv->dev->stats.rx_errors++; 1986 if (priv->hwts_rx_en && !priv->extend_desc) { 1987 /* DESC2 & DESC3 will be overwitten by device 1988 * with timestamp value, hence reinitialize 1989 * them in stmmac_rx_refill() function so that 1990 * device can reuse it. 1991 */ 1992 priv->rx_skbuff[entry] = NULL; 1993 dma_unmap_single(priv->device, 1994 priv->rx_skbuff_dma[entry], 1995 priv->dma_buf_sz, 1996 DMA_FROM_DEVICE); 1997 } 1998 } else { 1999 struct sk_buff *skb; 2000 int frame_len; 2001 2002 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2003 2004 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2005 * Type frames (LLC/LLC-SNAP) 2006 */ 2007 if (unlikely(status != llc_snap)) 2008 frame_len -= ETH_FCS_LEN; 2009 2010 if (netif_msg_rx_status(priv)) { 2011 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2012 p, entry, p->des2); 2013 if (frame_len > ETH_FRAME_LEN) 2014 pr_debug("\tframe size %d, COE: %d\n", 2015 frame_len, status); 2016 } 2017 skb = priv->rx_skbuff[entry]; 2018 if (unlikely(!skb)) { 2019 pr_err("%s: Inconsistent Rx descriptor chain\n", 2020 priv->dev->name); 2021 priv->dev->stats.rx_dropped++; 2022 break; 2023 } 2024 prefetch(skb->data - NET_IP_ALIGN); 2025 priv->rx_skbuff[entry] = NULL; 2026 2027 stmmac_get_rx_hwtstamp(priv, entry, skb); 2028 2029 skb_put(skb, frame_len); 2030 dma_unmap_single(priv->device, 2031 priv->rx_skbuff_dma[entry], 2032 priv->dma_buf_sz, DMA_FROM_DEVICE); 2033 2034 if (netif_msg_pktdata(priv)) { 2035 pr_debug("frame received (%dbytes)", frame_len); 2036 print_pkt(skb->data, frame_len); 2037 } 2038 2039 skb->protocol = eth_type_trans(skb, priv->dev); 2040 2041 if (unlikely(!coe)) 2042 skb_checksum_none_assert(skb); 2043 else 2044 skb->ip_summed = CHECKSUM_UNNECESSARY; 2045 2046 napi_gro_receive(&priv->napi, skb); 2047 2048 priv->dev->stats.rx_packets++; 2049 priv->dev->stats.rx_bytes += frame_len; 2050 } 2051 entry = next_entry; 2052 } 2053 2054 stmmac_rx_refill(priv); 2055 2056 priv->xstats.rx_pkt_n += count; 2057 2058 return count; 2059 } 2060 2061 /** 2062 * stmmac_poll - stmmac poll method (NAPI) 2063 * @napi : pointer to the napi structure. 2064 * @budget : maximum number of packets that the current CPU can receive from 2065 * all interfaces. 2066 * Description : 2067 * To look at the incoming frames and clear the tx resources. 2068 */ 2069 static int stmmac_poll(struct napi_struct *napi, int budget) 2070 { 2071 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2072 int work_done = 0; 2073 2074 priv->xstats.napi_poll++; 2075 stmmac_tx_clean(priv); 2076 2077 work_done = stmmac_rx(priv, budget); 2078 if (work_done < budget) { 2079 napi_complete(napi); 2080 stmmac_enable_dma_irq(priv); 2081 } 2082 return work_done; 2083 } 2084 2085 /** 2086 * stmmac_tx_timeout 2087 * @dev : Pointer to net device structure 2088 * Description: this function is called when a packet transmission fails to 2089 * complete within a reasonable time. The driver will mark the error in the 2090 * netdev structure and arrange for the device to be reset to a sane state 2091 * in order to transmit a new packet. 2092 */ 2093 static void stmmac_tx_timeout(struct net_device *dev) 2094 { 2095 struct stmmac_priv *priv = netdev_priv(dev); 2096 2097 /* Clear Tx resources and restart transmitting again */ 2098 stmmac_tx_err(priv); 2099 } 2100 2101 /* Configuration changes (passed on by ifconfig) */ 2102 static int stmmac_config(struct net_device *dev, struct ifmap *map) 2103 { 2104 if (dev->flags & IFF_UP) /* can't act on a running interface */ 2105 return -EBUSY; 2106 2107 /* Don't allow changing the I/O address */ 2108 if (map->base_addr != dev->base_addr) { 2109 pr_warn("%s: can't change I/O address\n", dev->name); 2110 return -EOPNOTSUPP; 2111 } 2112 2113 /* Don't allow changing the IRQ */ 2114 if (map->irq != dev->irq) { 2115 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq); 2116 return -EOPNOTSUPP; 2117 } 2118 2119 return 0; 2120 } 2121 2122 /** 2123 * stmmac_set_rx_mode - entry point for multicast addressing 2124 * @dev : pointer to the device structure 2125 * Description: 2126 * This function is a driver entry point which gets called by the kernel 2127 * whenever multicast addresses must be enabled/disabled. 2128 * Return value: 2129 * void. 2130 */ 2131 static void stmmac_set_rx_mode(struct net_device *dev) 2132 { 2133 struct stmmac_priv *priv = netdev_priv(dev); 2134 2135 spin_lock(&priv->lock); 2136 priv->hw->mac->set_filter(dev, priv->synopsys_id); 2137 spin_unlock(&priv->lock); 2138 } 2139 2140 /** 2141 * stmmac_change_mtu - entry point to change MTU size for the device. 2142 * @dev : device pointer. 2143 * @new_mtu : the new MTU size for the device. 2144 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2145 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2146 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2147 * Return value: 2148 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2149 * file on failure. 2150 */ 2151 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2152 { 2153 struct stmmac_priv *priv = netdev_priv(dev); 2154 int max_mtu; 2155 2156 if (netif_running(dev)) { 2157 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2158 return -EBUSY; 2159 } 2160 2161 if (priv->plat->enh_desc) 2162 max_mtu = JUMBO_LEN; 2163 else 2164 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2165 2166 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2167 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2168 return -EINVAL; 2169 } 2170 2171 dev->mtu = new_mtu; 2172 netdev_update_features(dev); 2173 2174 return 0; 2175 } 2176 2177 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2178 netdev_features_t features) 2179 { 2180 struct stmmac_priv *priv = netdev_priv(dev); 2181 2182 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2183 features &= ~NETIF_F_RXCSUM; 2184 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 2185 features &= ~NETIF_F_IPV6_CSUM; 2186 if (!priv->plat->tx_coe) 2187 features &= ~NETIF_F_ALL_CSUM; 2188 2189 /* Some GMAC devices have a bugged Jumbo frame support that 2190 * needs to have the Tx COE disabled for oversized frames 2191 * (due to limited buffer sizes). In this case we disable 2192 * the TX csum insertionin the TDES and not use SF. 2193 */ 2194 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2195 features &= ~NETIF_F_ALL_CSUM; 2196 2197 return features; 2198 } 2199 2200 /** 2201 * stmmac_interrupt - main ISR 2202 * @irq: interrupt number. 2203 * @dev_id: to pass the net device pointer. 2204 * Description: this is the main driver interrupt service routine. 2205 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 2206 * interrupts. 2207 */ 2208 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2209 { 2210 struct net_device *dev = (struct net_device *)dev_id; 2211 struct stmmac_priv *priv = netdev_priv(dev); 2212 2213 if (unlikely(!dev)) { 2214 pr_err("%s: invalid dev pointer\n", __func__); 2215 return IRQ_NONE; 2216 } 2217 2218 /* To handle GMAC own interrupts */ 2219 if (priv->plat->has_gmac) { 2220 int status = priv->hw->mac->host_irq_status((void __iomem *) 2221 dev->base_addr, 2222 &priv->xstats); 2223 if (unlikely(status)) { 2224 /* For LPI we need to save the tx status */ 2225 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2226 priv->tx_path_in_lpi_mode = true; 2227 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2228 priv->tx_path_in_lpi_mode = false; 2229 } 2230 } 2231 2232 /* To handle DMA interrupts */ 2233 stmmac_dma_interrupt(priv); 2234 2235 return IRQ_HANDLED; 2236 } 2237 2238 #ifdef CONFIG_NET_POLL_CONTROLLER 2239 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2240 * to allow network I/O with interrupts disabled. 2241 */ 2242 static void stmmac_poll_controller(struct net_device *dev) 2243 { 2244 disable_irq(dev->irq); 2245 stmmac_interrupt(dev->irq, dev); 2246 enable_irq(dev->irq); 2247 } 2248 #endif 2249 2250 /** 2251 * stmmac_ioctl - Entry point for the Ioctl 2252 * @dev: Device pointer. 2253 * @rq: An IOCTL specefic structure, that can contain a pointer to 2254 * a proprietary structure used to pass information to the driver. 2255 * @cmd: IOCTL command 2256 * Description: 2257 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2258 */ 2259 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2260 { 2261 struct stmmac_priv *priv = netdev_priv(dev); 2262 int ret = -EOPNOTSUPP; 2263 2264 if (!netif_running(dev)) 2265 return -EINVAL; 2266 2267 switch (cmd) { 2268 case SIOCGMIIPHY: 2269 case SIOCGMIIREG: 2270 case SIOCSMIIREG: 2271 if (!priv->phydev) 2272 return -EINVAL; 2273 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2274 break; 2275 case SIOCSHWTSTAMP: 2276 ret = stmmac_hwtstamp_ioctl(dev, rq); 2277 break; 2278 default: 2279 break; 2280 } 2281 2282 return ret; 2283 } 2284 2285 #ifdef CONFIG_STMMAC_DEBUG_FS 2286 static struct dentry *stmmac_fs_dir; 2287 static struct dentry *stmmac_rings_status; 2288 static struct dentry *stmmac_dma_cap; 2289 2290 static void sysfs_display_ring(void *head, int size, int extend_desc, 2291 struct seq_file *seq) 2292 { 2293 int i; 2294 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2295 struct dma_desc *p = (struct dma_desc *)head; 2296 2297 for (i = 0; i < size; i++) { 2298 u64 x; 2299 if (extend_desc) { 2300 x = *(u64 *) ep; 2301 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2302 i, (unsigned int)virt_to_phys(ep), 2303 (unsigned int)x, (unsigned int)(x >> 32), 2304 ep->basic.des2, ep->basic.des3); 2305 ep++; 2306 } else { 2307 x = *(u64 *) p; 2308 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2309 i, (unsigned int)virt_to_phys(ep), 2310 (unsigned int)x, (unsigned int)(x >> 32), 2311 p->des2, p->des3); 2312 p++; 2313 } 2314 seq_printf(seq, "\n"); 2315 } 2316 } 2317 2318 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2319 { 2320 struct net_device *dev = seq->private; 2321 struct stmmac_priv *priv = netdev_priv(dev); 2322 unsigned int txsize = priv->dma_tx_size; 2323 unsigned int rxsize = priv->dma_rx_size; 2324 2325 if (priv->extend_desc) { 2326 seq_printf(seq, "Extended RX descriptor ring:\n"); 2327 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2328 seq_printf(seq, "Extended TX descriptor ring:\n"); 2329 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2330 } else { 2331 seq_printf(seq, "RX descriptor ring:\n"); 2332 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2333 seq_printf(seq, "TX descriptor ring:\n"); 2334 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2335 } 2336 2337 return 0; 2338 } 2339 2340 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2341 { 2342 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2343 } 2344 2345 static const struct file_operations stmmac_rings_status_fops = { 2346 .owner = THIS_MODULE, 2347 .open = stmmac_sysfs_ring_open, 2348 .read = seq_read, 2349 .llseek = seq_lseek, 2350 .release = single_release, 2351 }; 2352 2353 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2354 { 2355 struct net_device *dev = seq->private; 2356 struct stmmac_priv *priv = netdev_priv(dev); 2357 2358 if (!priv->hw_cap_support) { 2359 seq_printf(seq, "DMA HW features not supported\n"); 2360 return 0; 2361 } 2362 2363 seq_printf(seq, "==============================\n"); 2364 seq_printf(seq, "\tDMA HW features\n"); 2365 seq_printf(seq, "==============================\n"); 2366 2367 seq_printf(seq, "\t10/100 Mbps %s\n", 2368 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2369 seq_printf(seq, "\t1000 Mbps %s\n", 2370 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2371 seq_printf(seq, "\tHalf duple %s\n", 2372 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2373 seq_printf(seq, "\tHash Filter: %s\n", 2374 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2375 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2376 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2377 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2378 (priv->dma_cap.pcs) ? "Y" : "N"); 2379 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2380 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2381 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2382 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2383 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2384 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2385 seq_printf(seq, "\tRMON module: %s\n", 2386 (priv->dma_cap.rmon) ? "Y" : "N"); 2387 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2388 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2389 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2390 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2391 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2392 (priv->dma_cap.eee) ? "Y" : "N"); 2393 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2394 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2395 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2396 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2397 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2398 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2399 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2400 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2401 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2402 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2403 priv->dma_cap.number_rx_channel); 2404 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2405 priv->dma_cap.number_tx_channel); 2406 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2407 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2408 2409 return 0; 2410 } 2411 2412 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2413 { 2414 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2415 } 2416 2417 static const struct file_operations stmmac_dma_cap_fops = { 2418 .owner = THIS_MODULE, 2419 .open = stmmac_sysfs_dma_cap_open, 2420 .read = seq_read, 2421 .llseek = seq_lseek, 2422 .release = single_release, 2423 }; 2424 2425 static int stmmac_init_fs(struct net_device *dev) 2426 { 2427 /* Create debugfs entries */ 2428 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2429 2430 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2431 pr_err("ERROR %s, debugfs create directory failed\n", 2432 STMMAC_RESOURCE_NAME); 2433 2434 return -ENOMEM; 2435 } 2436 2437 /* Entry to report DMA RX/TX rings */ 2438 stmmac_rings_status = debugfs_create_file("descriptors_status", 2439 S_IRUGO, stmmac_fs_dir, dev, 2440 &stmmac_rings_status_fops); 2441 2442 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2443 pr_info("ERROR creating stmmac ring debugfs file\n"); 2444 debugfs_remove(stmmac_fs_dir); 2445 2446 return -ENOMEM; 2447 } 2448 2449 /* Entry to report the DMA HW features */ 2450 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2451 dev, &stmmac_dma_cap_fops); 2452 2453 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2454 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2455 debugfs_remove(stmmac_rings_status); 2456 debugfs_remove(stmmac_fs_dir); 2457 2458 return -ENOMEM; 2459 } 2460 2461 return 0; 2462 } 2463 2464 static void stmmac_exit_fs(void) 2465 { 2466 debugfs_remove(stmmac_rings_status); 2467 debugfs_remove(stmmac_dma_cap); 2468 debugfs_remove(stmmac_fs_dir); 2469 } 2470 #endif /* CONFIG_STMMAC_DEBUG_FS */ 2471 2472 static const struct net_device_ops stmmac_netdev_ops = { 2473 .ndo_open = stmmac_open, 2474 .ndo_start_xmit = stmmac_xmit, 2475 .ndo_stop = stmmac_release, 2476 .ndo_change_mtu = stmmac_change_mtu, 2477 .ndo_fix_features = stmmac_fix_features, 2478 .ndo_set_rx_mode = stmmac_set_rx_mode, 2479 .ndo_tx_timeout = stmmac_tx_timeout, 2480 .ndo_do_ioctl = stmmac_ioctl, 2481 .ndo_set_config = stmmac_config, 2482 #ifdef CONFIG_NET_POLL_CONTROLLER 2483 .ndo_poll_controller = stmmac_poll_controller, 2484 #endif 2485 .ndo_set_mac_address = eth_mac_addr, 2486 }; 2487 2488 /** 2489 * stmmac_hw_init - Init the MAC device 2490 * @priv: driver private structure 2491 * Description: this function detects which MAC device 2492 * (GMAC/MAC10-100) has to attached, checks the HW capability 2493 * (if supported) and sets the driver's features (for example 2494 * to use the ring or chaine mode or support the normal/enh 2495 * descriptor structure). 2496 */ 2497 static int stmmac_hw_init(struct stmmac_priv *priv) 2498 { 2499 int ret; 2500 struct mac_device_info *mac; 2501 2502 /* Identify the MAC HW device */ 2503 if (priv->plat->has_gmac) { 2504 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2505 mac = dwmac1000_setup(priv->ioaddr); 2506 } else { 2507 mac = dwmac100_setup(priv->ioaddr); 2508 } 2509 if (!mac) 2510 return -ENOMEM; 2511 2512 priv->hw = mac; 2513 2514 /* Get and dump the chip ID */ 2515 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2516 2517 /* To use the chained or ring mode */ 2518 if (chain_mode) { 2519 priv->hw->chain = &chain_mode_ops; 2520 pr_info(" Chain mode enabled\n"); 2521 priv->mode = STMMAC_CHAIN_MODE; 2522 } else { 2523 priv->hw->ring = &ring_mode_ops; 2524 pr_info(" Ring mode enabled\n"); 2525 priv->mode = STMMAC_RING_MODE; 2526 } 2527 2528 /* Get the HW capability (new GMAC newer than 3.50a) */ 2529 priv->hw_cap_support = stmmac_get_hw_features(priv); 2530 if (priv->hw_cap_support) { 2531 pr_info(" DMA HW capability register supported"); 2532 2533 /* We can override some gmac/dma configuration fields: e.g. 2534 * enh_desc, tx_coe (e.g. that are passed through the 2535 * platform) with the values from the HW capability 2536 * register (if supported). 2537 */ 2538 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2539 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2540 2541 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2542 2543 if (priv->dma_cap.rx_coe_type2) 2544 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2545 else if (priv->dma_cap.rx_coe_type1) 2546 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2547 2548 } else 2549 pr_info(" No HW DMA feature register supported"); 2550 2551 /* To use alternate (extended) or normal descriptor structures */ 2552 stmmac_selec_desc_mode(priv); 2553 2554 ret = priv->hw->mac->rx_ipc(priv->ioaddr); 2555 if (!ret) { 2556 pr_warn(" RX IPC Checksum Offload not configured.\n"); 2557 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2558 } 2559 2560 if (priv->plat->rx_coe) 2561 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2562 priv->plat->rx_coe); 2563 if (priv->plat->tx_coe) 2564 pr_info(" TX Checksum insertion supported\n"); 2565 2566 if (priv->plat->pmt) { 2567 pr_info(" Wake-Up On Lan supported\n"); 2568 device_set_wakeup_capable(priv->device, 1); 2569 } 2570 2571 return 0; 2572 } 2573 2574 /** 2575 * stmmac_dvr_probe 2576 * @device: device pointer 2577 * @plat_dat: platform data pointer 2578 * @addr: iobase memory address 2579 * Description: this is the main probe function used to 2580 * call the alloc_etherdev, allocate the priv structure. 2581 */ 2582 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2583 struct plat_stmmacenet_data *plat_dat, 2584 void __iomem *addr) 2585 { 2586 int ret = 0; 2587 struct net_device *ndev = NULL; 2588 struct stmmac_priv *priv; 2589 2590 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2591 if (!ndev) 2592 return NULL; 2593 2594 SET_NETDEV_DEV(ndev, device); 2595 2596 priv = netdev_priv(ndev); 2597 priv->device = device; 2598 priv->dev = ndev; 2599 2600 ether_setup(ndev); 2601 2602 stmmac_set_ethtool_ops(ndev); 2603 priv->pause = pause; 2604 priv->plat = plat_dat; 2605 priv->ioaddr = addr; 2606 priv->dev->base_addr = (unsigned long)addr; 2607 2608 /* Verify driver arguments */ 2609 stmmac_verify_args(); 2610 2611 /* Override with kernel parameters if supplied XXX CRS XXX 2612 * this needs to have multiple instances 2613 */ 2614 if ((phyaddr >= 0) && (phyaddr <= 31)) 2615 priv->plat->phy_addr = phyaddr; 2616 2617 /* Init MAC and get the capabilities */ 2618 ret = stmmac_hw_init(priv); 2619 if (ret) 2620 goto error_free_netdev; 2621 2622 ndev->netdev_ops = &stmmac_netdev_ops; 2623 2624 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2625 NETIF_F_RXCSUM; 2626 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2627 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2628 #ifdef STMMAC_VLAN_TAG_USED 2629 /* Both mac100 and gmac support receive VLAN tag detection */ 2630 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2631 #endif 2632 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2633 2634 if (flow_ctrl) 2635 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2636 2637 /* Rx Watchdog is available in the COREs newer than the 3.40. 2638 * In some case, for example on bugged HW this feature 2639 * has to be disable and this can be done by passing the 2640 * riwt_off field from the platform. 2641 */ 2642 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2643 priv->use_riwt = 1; 2644 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2645 } 2646 2647 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2648 2649 spin_lock_init(&priv->lock); 2650 spin_lock_init(&priv->tx_lock); 2651 2652 ret = register_netdev(ndev); 2653 if (ret) { 2654 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2655 goto error_netdev_register; 2656 } 2657 2658 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME); 2659 if (IS_ERR(priv->stmmac_clk)) { 2660 pr_warn("%s: warning: cannot get CSR clock\n", __func__); 2661 goto error_clk_get; 2662 } 2663 2664 /* If a specific clk_csr value is passed from the platform 2665 * this means that the CSR Clock Range selection cannot be 2666 * changed at run-time and it is fixed. Viceversa the driver'll try to 2667 * set the MDC clock dynamically according to the csr actual 2668 * clock input. 2669 */ 2670 if (!priv->plat->clk_csr) 2671 stmmac_clk_csr_set(priv); 2672 else 2673 priv->clk_csr = priv->plat->clk_csr; 2674 2675 stmmac_check_pcs_mode(priv); 2676 2677 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2678 priv->pcs != STMMAC_PCS_RTBI) { 2679 /* MDIO bus Registration */ 2680 ret = stmmac_mdio_register(ndev); 2681 if (ret < 0) { 2682 pr_debug("%s: MDIO bus (id: %d) registration failed", 2683 __func__, priv->plat->bus_id); 2684 goto error_mdio_register; 2685 } 2686 } 2687 2688 return priv; 2689 2690 error_mdio_register: 2691 clk_put(priv->stmmac_clk); 2692 error_clk_get: 2693 unregister_netdev(ndev); 2694 error_netdev_register: 2695 netif_napi_del(&priv->napi); 2696 error_free_netdev: 2697 free_netdev(ndev); 2698 2699 return NULL; 2700 } 2701 2702 /** 2703 * stmmac_dvr_remove 2704 * @ndev: net device pointer 2705 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2706 * changes the link status, releases the DMA descriptor rings. 2707 */ 2708 int stmmac_dvr_remove(struct net_device *ndev) 2709 { 2710 struct stmmac_priv *priv = netdev_priv(ndev); 2711 2712 pr_info("%s:\n\tremoving driver", __func__); 2713 2714 priv->hw->dma->stop_rx(priv->ioaddr); 2715 priv->hw->dma->stop_tx(priv->ioaddr); 2716 2717 stmmac_set_mac(priv->ioaddr, false); 2718 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2719 priv->pcs != STMMAC_PCS_RTBI) 2720 stmmac_mdio_unregister(ndev); 2721 netif_carrier_off(ndev); 2722 unregister_netdev(ndev); 2723 free_netdev(ndev); 2724 2725 return 0; 2726 } 2727 2728 #ifdef CONFIG_PM 2729 int stmmac_suspend(struct net_device *ndev) 2730 { 2731 struct stmmac_priv *priv = netdev_priv(ndev); 2732 unsigned long flags; 2733 2734 if (!ndev || !netif_running(ndev)) 2735 return 0; 2736 2737 if (priv->phydev) 2738 phy_stop(priv->phydev); 2739 2740 spin_lock_irqsave(&priv->lock, flags); 2741 2742 netif_device_detach(ndev); 2743 netif_stop_queue(ndev); 2744 2745 napi_disable(&priv->napi); 2746 2747 /* Stop TX/RX DMA */ 2748 priv->hw->dma->stop_tx(priv->ioaddr); 2749 priv->hw->dma->stop_rx(priv->ioaddr); 2750 2751 stmmac_clear_descriptors(priv); 2752 2753 /* Enable Power down mode by programming the PMT regs */ 2754 if (device_may_wakeup(priv->device)) 2755 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 2756 else { 2757 stmmac_set_mac(priv->ioaddr, false); 2758 /* Disable clock in case of PWM is off */ 2759 clk_disable_unprepare(priv->stmmac_clk); 2760 } 2761 spin_unlock_irqrestore(&priv->lock, flags); 2762 return 0; 2763 } 2764 2765 int stmmac_resume(struct net_device *ndev) 2766 { 2767 struct stmmac_priv *priv = netdev_priv(ndev); 2768 unsigned long flags; 2769 2770 if (!netif_running(ndev)) 2771 return 0; 2772 2773 spin_lock_irqsave(&priv->lock, flags); 2774 2775 /* Power Down bit, into the PM register, is cleared 2776 * automatically as soon as a magic packet or a Wake-up frame 2777 * is received. Anyway, it's better to manually clear 2778 * this bit because it can generate problems while resuming 2779 * from another devices (e.g. serial console). 2780 */ 2781 if (device_may_wakeup(priv->device)) 2782 priv->hw->mac->pmt(priv->ioaddr, 0); 2783 else 2784 /* enable the clk prevously disabled */ 2785 clk_prepare_enable(priv->stmmac_clk); 2786 2787 netif_device_attach(ndev); 2788 2789 /* Enable the MAC and DMA */ 2790 stmmac_set_mac(priv->ioaddr, true); 2791 priv->hw->dma->start_tx(priv->ioaddr); 2792 priv->hw->dma->start_rx(priv->ioaddr); 2793 2794 napi_enable(&priv->napi); 2795 2796 netif_start_queue(ndev); 2797 2798 spin_unlock_irqrestore(&priv->lock, flags); 2799 2800 if (priv->phydev) 2801 phy_start(priv->phydev); 2802 2803 return 0; 2804 } 2805 2806 int stmmac_freeze(struct net_device *ndev) 2807 { 2808 if (!ndev || !netif_running(ndev)) 2809 return 0; 2810 2811 return stmmac_release(ndev); 2812 } 2813 2814 int stmmac_restore(struct net_device *ndev) 2815 { 2816 if (!ndev || !netif_running(ndev)) 2817 return 0; 2818 2819 return stmmac_open(ndev); 2820 } 2821 #endif /* CONFIG_PM */ 2822 2823 /* Driver can be configured w/ and w/ both PCI and Platf drivers 2824 * depending on the configuration selected. 2825 */ 2826 static int __init stmmac_init(void) 2827 { 2828 int ret; 2829 2830 ret = stmmac_register_platform(); 2831 if (ret) 2832 goto err; 2833 ret = stmmac_register_pci(); 2834 if (ret) 2835 goto err_pci; 2836 return 0; 2837 err_pci: 2838 stmmac_unregister_platform(); 2839 err: 2840 pr_err("stmmac: driver registration failed\n"); 2841 return ret; 2842 } 2843 2844 static void __exit stmmac_exit(void) 2845 { 2846 stmmac_unregister_platform(); 2847 stmmac_unregister_pci(); 2848 } 2849 2850 module_init(stmmac_init); 2851 module_exit(stmmac_exit); 2852 2853 #ifndef MODULE 2854 static int __init stmmac_cmdline_opt(char *str) 2855 { 2856 char *opt; 2857 2858 if (!str || !*str) 2859 return -EINVAL; 2860 while ((opt = strsep(&str, ",")) != NULL) { 2861 if (!strncmp(opt, "debug:", 6)) { 2862 if (kstrtoint(opt + 6, 0, &debug)) 2863 goto err; 2864 } else if (!strncmp(opt, "phyaddr:", 8)) { 2865 if (kstrtoint(opt + 8, 0, &phyaddr)) 2866 goto err; 2867 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2868 if (kstrtoint(opt + 11, 0, &dma_txsize)) 2869 goto err; 2870 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2871 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 2872 goto err; 2873 } else if (!strncmp(opt, "buf_sz:", 7)) { 2874 if (kstrtoint(opt + 7, 0, &buf_sz)) 2875 goto err; 2876 } else if (!strncmp(opt, "tc:", 3)) { 2877 if (kstrtoint(opt + 3, 0, &tc)) 2878 goto err; 2879 } else if (!strncmp(opt, "watchdog:", 9)) { 2880 if (kstrtoint(opt + 9, 0, &watchdog)) 2881 goto err; 2882 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2883 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 2884 goto err; 2885 } else if (!strncmp(opt, "pause:", 6)) { 2886 if (kstrtoint(opt + 6, 0, &pause)) 2887 goto err; 2888 } else if (!strncmp(opt, "eee_timer:", 10)) { 2889 if (kstrtoint(opt + 10, 0, &eee_timer)) 2890 goto err; 2891 } else if (!strncmp(opt, "chain_mode:", 11)) { 2892 if (kstrtoint(opt + 11, 0, &chain_mode)) 2893 goto err; 2894 } 2895 } 2896 return 0; 2897 2898 err: 2899 pr_err("%s: ERROR broken module parameter conversion", __func__); 2900 return -EINVAL; 2901 } 2902 2903 __setup("stmmaceth=", stmmac_cmdline_opt); 2904 #endif /* MODULE */ 2905 2906 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 2907 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 2908 MODULE_LICENSE("GPL"); 2909