1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->has_sun8i) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->en_tx_lpi_clockgating); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 return 0; 913 } 914 915 static void stmmac_release_ptp(struct stmmac_priv *priv) 916 { 917 clk_disable_unprepare(priv->plat->clk_ptp_ref); 918 stmmac_ptp_unregister(priv); 919 } 920 921 /** 922 * stmmac_mac_flow_ctrl - Configure flow control in all queues 923 * @priv: driver private structure 924 * @duplex: duplex passed to the next function 925 * Description: It is used for configuring the flow control in all queues 926 */ 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 928 { 929 u32 tx_cnt = priv->plat->tx_queues_to_use; 930 931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 932 priv->pause, tx_cnt); 933 } 934 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 936 phy_interface_t interface) 937 { 938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 939 940 if (!priv->hw->xpcs) 941 return NULL; 942 943 return &priv->hw->xpcs->pcs; 944 } 945 946 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 947 const struct phylink_link_state *state) 948 { 949 /* Nothing to do, xpcs_config() handles everything */ 950 } 951 952 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 953 { 954 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 955 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 956 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 957 bool *hs_enable = &fpe_cfg->hs_enable; 958 959 if (is_up && *hs_enable) { 960 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 961 } else { 962 *lo_state = FPE_STATE_OFF; 963 *lp_state = FPE_STATE_OFF; 964 } 965 } 966 967 static void stmmac_mac_link_down(struct phylink_config *config, 968 unsigned int mode, phy_interface_t interface) 969 { 970 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 971 972 stmmac_mac_set(priv, priv->ioaddr, false); 973 priv->eee_active = false; 974 priv->tx_lpi_enabled = false; 975 priv->eee_enabled = stmmac_eee_init(priv); 976 stmmac_set_eee_pls(priv, priv->hw, false); 977 978 if (priv->dma_cap.fpesel) 979 stmmac_fpe_link_state_handle(priv, false); 980 } 981 982 static void stmmac_mac_link_up(struct phylink_config *config, 983 struct phy_device *phy, 984 unsigned int mode, phy_interface_t interface, 985 int speed, int duplex, 986 bool tx_pause, bool rx_pause) 987 { 988 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 989 u32 old_ctrl, ctrl; 990 991 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 992 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 993 994 if (interface == PHY_INTERFACE_MODE_USXGMII) { 995 switch (speed) { 996 case SPEED_10000: 997 ctrl |= priv->hw->link.xgmii.speed10000; 998 break; 999 case SPEED_5000: 1000 ctrl |= priv->hw->link.xgmii.speed5000; 1001 break; 1002 case SPEED_2500: 1003 ctrl |= priv->hw->link.xgmii.speed2500; 1004 break; 1005 default: 1006 return; 1007 } 1008 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1009 switch (speed) { 1010 case SPEED_100000: 1011 ctrl |= priv->hw->link.xlgmii.speed100000; 1012 break; 1013 case SPEED_50000: 1014 ctrl |= priv->hw->link.xlgmii.speed50000; 1015 break; 1016 case SPEED_40000: 1017 ctrl |= priv->hw->link.xlgmii.speed40000; 1018 break; 1019 case SPEED_25000: 1020 ctrl |= priv->hw->link.xlgmii.speed25000; 1021 break; 1022 case SPEED_10000: 1023 ctrl |= priv->hw->link.xgmii.speed10000; 1024 break; 1025 case SPEED_2500: 1026 ctrl |= priv->hw->link.speed2500; 1027 break; 1028 case SPEED_1000: 1029 ctrl |= priv->hw->link.speed1000; 1030 break; 1031 default: 1032 return; 1033 } 1034 } else { 1035 switch (speed) { 1036 case SPEED_2500: 1037 ctrl |= priv->hw->link.speed2500; 1038 break; 1039 case SPEED_1000: 1040 ctrl |= priv->hw->link.speed1000; 1041 break; 1042 case SPEED_100: 1043 ctrl |= priv->hw->link.speed100; 1044 break; 1045 case SPEED_10: 1046 ctrl |= priv->hw->link.speed10; 1047 break; 1048 default: 1049 return; 1050 } 1051 } 1052 1053 priv->speed = speed; 1054 1055 if (priv->plat->fix_mac_speed) 1056 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1057 1058 if (!duplex) 1059 ctrl &= ~priv->hw->link.duplex; 1060 else 1061 ctrl |= priv->hw->link.duplex; 1062 1063 /* Flow Control operation */ 1064 if (tx_pause && rx_pause) 1065 stmmac_mac_flow_ctrl(priv, duplex); 1066 1067 if (ctrl != old_ctrl) 1068 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1069 1070 stmmac_mac_set(priv, priv->ioaddr, true); 1071 if (phy && priv->dma_cap.eee) { 1072 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1073 priv->eee_enabled = stmmac_eee_init(priv); 1074 priv->tx_lpi_enabled = priv->eee_enabled; 1075 stmmac_set_eee_pls(priv, priv->hw, true); 1076 } 1077 1078 if (priv->dma_cap.fpesel) 1079 stmmac_fpe_link_state_handle(priv, true); 1080 } 1081 1082 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1083 .validate = phylink_generic_validate, 1084 .mac_select_pcs = stmmac_mac_select_pcs, 1085 .mac_config = stmmac_mac_config, 1086 .mac_link_down = stmmac_mac_link_down, 1087 .mac_link_up = stmmac_mac_link_up, 1088 }; 1089 1090 /** 1091 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1092 * @priv: driver private structure 1093 * Description: this is to verify if the HW supports the PCS. 1094 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1095 * configured for the TBI, RTBI, or SGMII PHY interface. 1096 */ 1097 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1098 { 1099 int interface = priv->plat->interface; 1100 1101 if (priv->dma_cap.pcs) { 1102 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1103 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1104 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1105 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1106 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1107 priv->hw->pcs = STMMAC_PCS_RGMII; 1108 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1109 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1110 priv->hw->pcs = STMMAC_PCS_SGMII; 1111 } 1112 } 1113 } 1114 1115 /** 1116 * stmmac_init_phy - PHY initialization 1117 * @dev: net device structure 1118 * Description: it initializes the driver's PHY state, and attaches the PHY 1119 * to the mac driver. 1120 * Return value: 1121 * 0 on success 1122 */ 1123 static int stmmac_init_phy(struct net_device *dev) 1124 { 1125 struct stmmac_priv *priv = netdev_priv(dev); 1126 struct fwnode_handle *fwnode; 1127 int ret; 1128 1129 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1130 if (!fwnode) 1131 fwnode = dev_fwnode(priv->device); 1132 1133 if (fwnode) 1134 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1135 1136 /* Some DT bindings do not set-up the PHY handle. Let's try to 1137 * manually parse it 1138 */ 1139 if (!fwnode || ret) { 1140 int addr = priv->plat->phy_addr; 1141 struct phy_device *phydev; 1142 1143 phydev = mdiobus_get_phy(priv->mii, addr); 1144 if (!phydev) { 1145 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1146 return -ENODEV; 1147 } 1148 1149 ret = phylink_connect_phy(priv->phylink, phydev); 1150 } 1151 1152 if (!priv->plat->pmt) { 1153 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1154 1155 phylink_ethtool_get_wol(priv->phylink, &wol); 1156 device_set_wakeup_capable(priv->device, !!wol.supported); 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int stmmac_phy_setup(struct stmmac_priv *priv) 1163 { 1164 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1165 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1166 int max_speed = priv->plat->max_speed; 1167 int mode = priv->plat->phy_interface; 1168 struct phylink *phylink; 1169 1170 priv->phylink_config.dev = &priv->dev->dev; 1171 priv->phylink_config.type = PHYLINK_NETDEV; 1172 if (priv->plat->mdio_bus_data) 1173 priv->phylink_config.ovr_an_inband = 1174 mdio_bus_data->xpcs_an_inband; 1175 1176 if (!fwnode) 1177 fwnode = dev_fwnode(priv->device); 1178 1179 /* Set the platform/firmware specified interface mode */ 1180 __set_bit(mode, priv->phylink_config.supported_interfaces); 1181 1182 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1183 if (priv->hw->xpcs) 1184 xpcs_get_interfaces(priv->hw->xpcs, 1185 priv->phylink_config.supported_interfaces); 1186 1187 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1188 MAC_10 | MAC_100; 1189 1190 if (!max_speed || max_speed >= 1000) 1191 priv->phylink_config.mac_capabilities |= MAC_1000; 1192 1193 if (priv->plat->has_gmac4) { 1194 if (!max_speed || max_speed >= 2500) 1195 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1196 } else if (priv->plat->has_xgmac) { 1197 if (!max_speed || max_speed >= 2500) 1198 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1199 if (!max_speed || max_speed >= 5000) 1200 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1201 if (!max_speed || max_speed >= 10000) 1202 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1203 if (!max_speed || max_speed >= 25000) 1204 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1205 if (!max_speed || max_speed >= 40000) 1206 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1207 if (!max_speed || max_speed >= 50000) 1208 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1209 if (!max_speed || max_speed >= 100000) 1210 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1211 } 1212 1213 /* Half-Duplex can only work with single queue */ 1214 if (priv->plat->tx_queues_to_use > 1) 1215 priv->phylink_config.mac_capabilities &= 1216 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1217 1218 phylink = phylink_create(&priv->phylink_config, fwnode, 1219 mode, &stmmac_phylink_mac_ops); 1220 if (IS_ERR(phylink)) 1221 return PTR_ERR(phylink); 1222 1223 priv->phylink = phylink; 1224 return 0; 1225 } 1226 1227 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1228 struct stmmac_dma_conf *dma_conf) 1229 { 1230 u32 rx_cnt = priv->plat->rx_queues_to_use; 1231 unsigned int desc_size; 1232 void *head_rx; 1233 u32 queue; 1234 1235 /* Display RX rings */ 1236 for (queue = 0; queue < rx_cnt; queue++) { 1237 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1238 1239 pr_info("\tRX Queue %u rings\n", queue); 1240 1241 if (priv->extend_desc) { 1242 head_rx = (void *)rx_q->dma_erx; 1243 desc_size = sizeof(struct dma_extended_desc); 1244 } else { 1245 head_rx = (void *)rx_q->dma_rx; 1246 desc_size = sizeof(struct dma_desc); 1247 } 1248 1249 /* Display RX ring */ 1250 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1251 rx_q->dma_rx_phy, desc_size); 1252 } 1253 } 1254 1255 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1256 struct stmmac_dma_conf *dma_conf) 1257 { 1258 u32 tx_cnt = priv->plat->tx_queues_to_use; 1259 unsigned int desc_size; 1260 void *head_tx; 1261 u32 queue; 1262 1263 /* Display TX rings */ 1264 for (queue = 0; queue < tx_cnt; queue++) { 1265 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1266 1267 pr_info("\tTX Queue %d rings\n", queue); 1268 1269 if (priv->extend_desc) { 1270 head_tx = (void *)tx_q->dma_etx; 1271 desc_size = sizeof(struct dma_extended_desc); 1272 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1273 head_tx = (void *)tx_q->dma_entx; 1274 desc_size = sizeof(struct dma_edesc); 1275 } else { 1276 head_tx = (void *)tx_q->dma_tx; 1277 desc_size = sizeof(struct dma_desc); 1278 } 1279 1280 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1281 tx_q->dma_tx_phy, desc_size); 1282 } 1283 } 1284 1285 static void stmmac_display_rings(struct stmmac_priv *priv, 1286 struct stmmac_dma_conf *dma_conf) 1287 { 1288 /* Display RX ring */ 1289 stmmac_display_rx_rings(priv, dma_conf); 1290 1291 /* Display TX ring */ 1292 stmmac_display_tx_rings(priv, dma_conf); 1293 } 1294 1295 static int stmmac_set_bfsize(int mtu, int bufsize) 1296 { 1297 int ret = bufsize; 1298 1299 if (mtu >= BUF_SIZE_8KiB) 1300 ret = BUF_SIZE_16KiB; 1301 else if (mtu >= BUF_SIZE_4KiB) 1302 ret = BUF_SIZE_8KiB; 1303 else if (mtu >= BUF_SIZE_2KiB) 1304 ret = BUF_SIZE_4KiB; 1305 else if (mtu > DEFAULT_BUFSIZE) 1306 ret = BUF_SIZE_2KiB; 1307 else 1308 ret = DEFAULT_BUFSIZE; 1309 1310 return ret; 1311 } 1312 1313 /** 1314 * stmmac_clear_rx_descriptors - clear RX descriptors 1315 * @priv: driver private structure 1316 * @dma_conf: structure to take the dma data 1317 * @queue: RX queue index 1318 * Description: this function is called to clear the RX descriptors 1319 * in case of both basic and extended descriptors are used. 1320 */ 1321 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1322 struct stmmac_dma_conf *dma_conf, 1323 u32 queue) 1324 { 1325 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1326 int i; 1327 1328 /* Clear the RX descriptors */ 1329 for (i = 0; i < dma_conf->dma_rx_size; i++) 1330 if (priv->extend_desc) 1331 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1332 priv->use_riwt, priv->mode, 1333 (i == dma_conf->dma_rx_size - 1), 1334 dma_conf->dma_buf_sz); 1335 else 1336 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1337 priv->use_riwt, priv->mode, 1338 (i == dma_conf->dma_rx_size - 1), 1339 dma_conf->dma_buf_sz); 1340 } 1341 1342 /** 1343 * stmmac_clear_tx_descriptors - clear tx descriptors 1344 * @priv: driver private structure 1345 * @dma_conf: structure to take the dma data 1346 * @queue: TX queue index. 1347 * Description: this function is called to clear the TX descriptors 1348 * in case of both basic and extended descriptors are used. 1349 */ 1350 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1351 struct stmmac_dma_conf *dma_conf, 1352 u32 queue) 1353 { 1354 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1355 int i; 1356 1357 /* Clear the TX descriptors */ 1358 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1359 int last = (i == (dma_conf->dma_tx_size - 1)); 1360 struct dma_desc *p; 1361 1362 if (priv->extend_desc) 1363 p = &tx_q->dma_etx[i].basic; 1364 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1365 p = &tx_q->dma_entx[i].basic; 1366 else 1367 p = &tx_q->dma_tx[i]; 1368 1369 stmmac_init_tx_desc(priv, p, priv->mode, last); 1370 } 1371 } 1372 1373 /** 1374 * stmmac_clear_descriptors - clear descriptors 1375 * @priv: driver private structure 1376 * @dma_conf: structure to take the dma data 1377 * Description: this function is called to clear the TX and RX descriptors 1378 * in case of both basic and extended descriptors are used. 1379 */ 1380 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1381 struct stmmac_dma_conf *dma_conf) 1382 { 1383 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1384 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1385 u32 queue; 1386 1387 /* Clear the RX descriptors */ 1388 for (queue = 0; queue < rx_queue_cnt; queue++) 1389 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1390 1391 /* Clear the TX descriptors */ 1392 for (queue = 0; queue < tx_queue_cnt; queue++) 1393 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1394 } 1395 1396 /** 1397 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1398 * @priv: driver private structure 1399 * @dma_conf: structure to take the dma data 1400 * @p: descriptor pointer 1401 * @i: descriptor index 1402 * @flags: gfp flag 1403 * @queue: RX queue index 1404 * Description: this function is called to allocate a receive buffer, perform 1405 * the DMA mapping and init the descriptor. 1406 */ 1407 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1408 struct stmmac_dma_conf *dma_conf, 1409 struct dma_desc *p, 1410 int i, gfp_t flags, u32 queue) 1411 { 1412 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1413 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1414 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1415 1416 if (priv->dma_cap.addr64 <= 32) 1417 gfp |= GFP_DMA32; 1418 1419 if (!buf->page) { 1420 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1421 if (!buf->page) 1422 return -ENOMEM; 1423 buf->page_offset = stmmac_rx_offset(priv); 1424 } 1425 1426 if (priv->sph && !buf->sec_page) { 1427 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1428 if (!buf->sec_page) 1429 return -ENOMEM; 1430 1431 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1432 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1433 } else { 1434 buf->sec_page = NULL; 1435 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1436 } 1437 1438 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1439 1440 stmmac_set_desc_addr(priv, p, buf->addr); 1441 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1442 stmmac_init_desc3(priv, p); 1443 1444 return 0; 1445 } 1446 1447 /** 1448 * stmmac_free_rx_buffer - free RX dma buffers 1449 * @priv: private structure 1450 * @rx_q: RX queue 1451 * @i: buffer index. 1452 */ 1453 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1454 struct stmmac_rx_queue *rx_q, 1455 int i) 1456 { 1457 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1458 1459 if (buf->page) 1460 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1461 buf->page = NULL; 1462 1463 if (buf->sec_page) 1464 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1465 buf->sec_page = NULL; 1466 } 1467 1468 /** 1469 * stmmac_free_tx_buffer - free RX dma buffers 1470 * @priv: private structure 1471 * @dma_conf: structure to take the dma data 1472 * @queue: RX queue index 1473 * @i: buffer index. 1474 */ 1475 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1476 struct stmmac_dma_conf *dma_conf, 1477 u32 queue, int i) 1478 { 1479 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1480 1481 if (tx_q->tx_skbuff_dma[i].buf && 1482 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1483 if (tx_q->tx_skbuff_dma[i].map_as_page) 1484 dma_unmap_page(priv->device, 1485 tx_q->tx_skbuff_dma[i].buf, 1486 tx_q->tx_skbuff_dma[i].len, 1487 DMA_TO_DEVICE); 1488 else 1489 dma_unmap_single(priv->device, 1490 tx_q->tx_skbuff_dma[i].buf, 1491 tx_q->tx_skbuff_dma[i].len, 1492 DMA_TO_DEVICE); 1493 } 1494 1495 if (tx_q->xdpf[i] && 1496 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1497 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1498 xdp_return_frame(tx_q->xdpf[i]); 1499 tx_q->xdpf[i] = NULL; 1500 } 1501 1502 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1503 tx_q->xsk_frames_done++; 1504 1505 if (tx_q->tx_skbuff[i] && 1506 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1507 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1508 tx_q->tx_skbuff[i] = NULL; 1509 } 1510 1511 tx_q->tx_skbuff_dma[i].buf = 0; 1512 tx_q->tx_skbuff_dma[i].map_as_page = false; 1513 } 1514 1515 /** 1516 * dma_free_rx_skbufs - free RX dma buffers 1517 * @priv: private structure 1518 * @dma_conf: structure to take the dma data 1519 * @queue: RX queue index 1520 */ 1521 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1522 struct stmmac_dma_conf *dma_conf, 1523 u32 queue) 1524 { 1525 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1526 int i; 1527 1528 for (i = 0; i < dma_conf->dma_rx_size; i++) 1529 stmmac_free_rx_buffer(priv, rx_q, i); 1530 } 1531 1532 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1533 struct stmmac_dma_conf *dma_conf, 1534 u32 queue, gfp_t flags) 1535 { 1536 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1537 int i; 1538 1539 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1540 struct dma_desc *p; 1541 int ret; 1542 1543 if (priv->extend_desc) 1544 p = &((rx_q->dma_erx + i)->basic); 1545 else 1546 p = rx_q->dma_rx + i; 1547 1548 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1549 queue); 1550 if (ret) 1551 return ret; 1552 1553 rx_q->buf_alloc_num++; 1554 } 1555 1556 return 0; 1557 } 1558 1559 /** 1560 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1561 * @priv: private structure 1562 * @dma_conf: structure to take the dma data 1563 * @queue: RX queue index 1564 */ 1565 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1566 struct stmmac_dma_conf *dma_conf, 1567 u32 queue) 1568 { 1569 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1570 int i; 1571 1572 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1573 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1574 1575 if (!buf->xdp) 1576 continue; 1577 1578 xsk_buff_free(buf->xdp); 1579 buf->xdp = NULL; 1580 } 1581 } 1582 1583 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1584 struct stmmac_dma_conf *dma_conf, 1585 u32 queue) 1586 { 1587 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1588 int i; 1589 1590 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1591 struct stmmac_rx_buffer *buf; 1592 dma_addr_t dma_addr; 1593 struct dma_desc *p; 1594 1595 if (priv->extend_desc) 1596 p = (struct dma_desc *)(rx_q->dma_erx + i); 1597 else 1598 p = rx_q->dma_rx + i; 1599 1600 buf = &rx_q->buf_pool[i]; 1601 1602 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1603 if (!buf->xdp) 1604 return -ENOMEM; 1605 1606 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1607 stmmac_set_desc_addr(priv, p, dma_addr); 1608 rx_q->buf_alloc_num++; 1609 } 1610 1611 return 0; 1612 } 1613 1614 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1615 { 1616 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1617 return NULL; 1618 1619 return xsk_get_pool_from_qid(priv->dev, queue); 1620 } 1621 1622 /** 1623 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1624 * @priv: driver private structure 1625 * @dma_conf: structure to take the dma data 1626 * @queue: RX queue index 1627 * @flags: gfp flag. 1628 * Description: this function initializes the DMA RX descriptors 1629 * and allocates the socket buffers. It supports the chained and ring 1630 * modes. 1631 */ 1632 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1633 struct stmmac_dma_conf *dma_conf, 1634 u32 queue, gfp_t flags) 1635 { 1636 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1637 int ret; 1638 1639 netif_dbg(priv, probe, priv->dev, 1640 "(%s) dma_rx_phy=0x%08x\n", __func__, 1641 (u32)rx_q->dma_rx_phy); 1642 1643 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1644 1645 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1646 1647 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1648 1649 if (rx_q->xsk_pool) { 1650 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1651 MEM_TYPE_XSK_BUFF_POOL, 1652 NULL)); 1653 netdev_info(priv->dev, 1654 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1655 rx_q->queue_index); 1656 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1657 } else { 1658 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1659 MEM_TYPE_PAGE_POOL, 1660 rx_q->page_pool)); 1661 netdev_info(priv->dev, 1662 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1663 rx_q->queue_index); 1664 } 1665 1666 if (rx_q->xsk_pool) { 1667 /* RX XDP ZC buffer pool may not be populated, e.g. 1668 * xdpsock TX-only. 1669 */ 1670 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1671 } else { 1672 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1673 if (ret < 0) 1674 return -ENOMEM; 1675 } 1676 1677 /* Setup the chained descriptor addresses */ 1678 if (priv->mode == STMMAC_CHAIN_MODE) { 1679 if (priv->extend_desc) 1680 stmmac_mode_init(priv, rx_q->dma_erx, 1681 rx_q->dma_rx_phy, 1682 dma_conf->dma_rx_size, 1); 1683 else 1684 stmmac_mode_init(priv, rx_q->dma_rx, 1685 rx_q->dma_rx_phy, 1686 dma_conf->dma_rx_size, 0); 1687 } 1688 1689 return 0; 1690 } 1691 1692 static int init_dma_rx_desc_rings(struct net_device *dev, 1693 struct stmmac_dma_conf *dma_conf, 1694 gfp_t flags) 1695 { 1696 struct stmmac_priv *priv = netdev_priv(dev); 1697 u32 rx_count = priv->plat->rx_queues_to_use; 1698 int queue; 1699 int ret; 1700 1701 /* RX INITIALIZATION */ 1702 netif_dbg(priv, probe, priv->dev, 1703 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1704 1705 for (queue = 0; queue < rx_count; queue++) { 1706 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1707 if (ret) 1708 goto err_init_rx_buffers; 1709 } 1710 1711 return 0; 1712 1713 err_init_rx_buffers: 1714 while (queue >= 0) { 1715 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1716 1717 if (rx_q->xsk_pool) 1718 dma_free_rx_xskbufs(priv, dma_conf, queue); 1719 else 1720 dma_free_rx_skbufs(priv, dma_conf, queue); 1721 1722 rx_q->buf_alloc_num = 0; 1723 rx_q->xsk_pool = NULL; 1724 1725 queue--; 1726 } 1727 1728 return ret; 1729 } 1730 1731 /** 1732 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1733 * @priv: driver private structure 1734 * @dma_conf: structure to take the dma data 1735 * @queue: TX queue index 1736 * Description: this function initializes the DMA TX descriptors 1737 * and allocates the socket buffers. It supports the chained and ring 1738 * modes. 1739 */ 1740 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1741 struct stmmac_dma_conf *dma_conf, 1742 u32 queue) 1743 { 1744 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1745 int i; 1746 1747 netif_dbg(priv, probe, priv->dev, 1748 "(%s) dma_tx_phy=0x%08x\n", __func__, 1749 (u32)tx_q->dma_tx_phy); 1750 1751 /* Setup the chained descriptor addresses */ 1752 if (priv->mode == STMMAC_CHAIN_MODE) { 1753 if (priv->extend_desc) 1754 stmmac_mode_init(priv, tx_q->dma_etx, 1755 tx_q->dma_tx_phy, 1756 dma_conf->dma_tx_size, 1); 1757 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1758 stmmac_mode_init(priv, tx_q->dma_tx, 1759 tx_q->dma_tx_phy, 1760 dma_conf->dma_tx_size, 0); 1761 } 1762 1763 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1764 1765 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1766 struct dma_desc *p; 1767 1768 if (priv->extend_desc) 1769 p = &((tx_q->dma_etx + i)->basic); 1770 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1771 p = &((tx_q->dma_entx + i)->basic); 1772 else 1773 p = tx_q->dma_tx + i; 1774 1775 stmmac_clear_desc(priv, p); 1776 1777 tx_q->tx_skbuff_dma[i].buf = 0; 1778 tx_q->tx_skbuff_dma[i].map_as_page = false; 1779 tx_q->tx_skbuff_dma[i].len = 0; 1780 tx_q->tx_skbuff_dma[i].last_segment = false; 1781 tx_q->tx_skbuff[i] = NULL; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int init_dma_tx_desc_rings(struct net_device *dev, 1788 struct stmmac_dma_conf *dma_conf) 1789 { 1790 struct stmmac_priv *priv = netdev_priv(dev); 1791 u32 tx_queue_cnt; 1792 u32 queue; 1793 1794 tx_queue_cnt = priv->plat->tx_queues_to_use; 1795 1796 for (queue = 0; queue < tx_queue_cnt; queue++) 1797 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1798 1799 return 0; 1800 } 1801 1802 /** 1803 * init_dma_desc_rings - init the RX/TX descriptor rings 1804 * @dev: net device structure 1805 * @dma_conf: structure to take the dma data 1806 * @flags: gfp flag. 1807 * Description: this function initializes the DMA RX/TX descriptors 1808 * and allocates the socket buffers. It supports the chained and ring 1809 * modes. 1810 */ 1811 static int init_dma_desc_rings(struct net_device *dev, 1812 struct stmmac_dma_conf *dma_conf, 1813 gfp_t flags) 1814 { 1815 struct stmmac_priv *priv = netdev_priv(dev); 1816 int ret; 1817 1818 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1819 if (ret) 1820 return ret; 1821 1822 ret = init_dma_tx_desc_rings(dev, dma_conf); 1823 1824 stmmac_clear_descriptors(priv, dma_conf); 1825 1826 if (netif_msg_hw(priv)) 1827 stmmac_display_rings(priv, dma_conf); 1828 1829 return ret; 1830 } 1831 1832 /** 1833 * dma_free_tx_skbufs - free TX dma buffers 1834 * @priv: private structure 1835 * @dma_conf: structure to take the dma data 1836 * @queue: TX queue index 1837 */ 1838 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1839 struct stmmac_dma_conf *dma_conf, 1840 u32 queue) 1841 { 1842 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1843 int i; 1844 1845 tx_q->xsk_frames_done = 0; 1846 1847 for (i = 0; i < dma_conf->dma_tx_size; i++) 1848 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1849 1850 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1851 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1852 tx_q->xsk_frames_done = 0; 1853 tx_q->xsk_pool = NULL; 1854 } 1855 } 1856 1857 /** 1858 * stmmac_free_tx_skbufs - free TX skb buffers 1859 * @priv: private structure 1860 */ 1861 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1862 { 1863 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1864 u32 queue; 1865 1866 for (queue = 0; queue < tx_queue_cnt; queue++) 1867 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1868 } 1869 1870 /** 1871 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1872 * @priv: private structure 1873 * @dma_conf: structure to take the dma data 1874 * @queue: RX queue index 1875 */ 1876 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1877 struct stmmac_dma_conf *dma_conf, 1878 u32 queue) 1879 { 1880 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1881 1882 /* Release the DMA RX socket buffers */ 1883 if (rx_q->xsk_pool) 1884 dma_free_rx_xskbufs(priv, dma_conf, queue); 1885 else 1886 dma_free_rx_skbufs(priv, dma_conf, queue); 1887 1888 rx_q->buf_alloc_num = 0; 1889 rx_q->xsk_pool = NULL; 1890 1891 /* Free DMA regions of consistent memory previously allocated */ 1892 if (!priv->extend_desc) 1893 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1894 sizeof(struct dma_desc), 1895 rx_q->dma_rx, rx_q->dma_rx_phy); 1896 else 1897 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1898 sizeof(struct dma_extended_desc), 1899 rx_q->dma_erx, rx_q->dma_rx_phy); 1900 1901 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1902 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1903 1904 kfree(rx_q->buf_pool); 1905 if (rx_q->page_pool) 1906 page_pool_destroy(rx_q->page_pool); 1907 } 1908 1909 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1910 struct stmmac_dma_conf *dma_conf) 1911 { 1912 u32 rx_count = priv->plat->rx_queues_to_use; 1913 u32 queue; 1914 1915 /* Free RX queue resources */ 1916 for (queue = 0; queue < rx_count; queue++) 1917 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1918 } 1919 1920 /** 1921 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1922 * @priv: private structure 1923 * @dma_conf: structure to take the dma data 1924 * @queue: TX queue index 1925 */ 1926 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1927 struct stmmac_dma_conf *dma_conf, 1928 u32 queue) 1929 { 1930 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1931 size_t size; 1932 void *addr; 1933 1934 /* Release the DMA TX socket buffers */ 1935 dma_free_tx_skbufs(priv, dma_conf, queue); 1936 1937 if (priv->extend_desc) { 1938 size = sizeof(struct dma_extended_desc); 1939 addr = tx_q->dma_etx; 1940 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1941 size = sizeof(struct dma_edesc); 1942 addr = tx_q->dma_entx; 1943 } else { 1944 size = sizeof(struct dma_desc); 1945 addr = tx_q->dma_tx; 1946 } 1947 1948 size *= dma_conf->dma_tx_size; 1949 1950 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1951 1952 kfree(tx_q->tx_skbuff_dma); 1953 kfree(tx_q->tx_skbuff); 1954 } 1955 1956 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1957 struct stmmac_dma_conf *dma_conf) 1958 { 1959 u32 tx_count = priv->plat->tx_queues_to_use; 1960 u32 queue; 1961 1962 /* Free TX queue resources */ 1963 for (queue = 0; queue < tx_count; queue++) 1964 __free_dma_tx_desc_resources(priv, dma_conf, queue); 1965 } 1966 1967 /** 1968 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1969 * @priv: private structure 1970 * @dma_conf: structure to take the dma data 1971 * @queue: RX queue index 1972 * Description: according to which descriptor can be used (extend or basic) 1973 * this function allocates the resources for TX and RX paths. In case of 1974 * reception, for example, it pre-allocated the RX socket buffer in order to 1975 * allow zero-copy mechanism. 1976 */ 1977 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 1978 struct stmmac_dma_conf *dma_conf, 1979 u32 queue) 1980 { 1981 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1982 struct stmmac_channel *ch = &priv->channel[queue]; 1983 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1984 struct page_pool_params pp_params = { 0 }; 1985 unsigned int num_pages; 1986 unsigned int napi_id; 1987 int ret; 1988 1989 rx_q->queue_index = queue; 1990 rx_q->priv_data = priv; 1991 1992 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1993 pp_params.pool_size = dma_conf->dma_rx_size; 1994 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 1995 pp_params.order = ilog2(num_pages); 1996 pp_params.nid = dev_to_node(priv->device); 1997 pp_params.dev = priv->device; 1998 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1999 pp_params.offset = stmmac_rx_offset(priv); 2000 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2001 2002 rx_q->page_pool = page_pool_create(&pp_params); 2003 if (IS_ERR(rx_q->page_pool)) { 2004 ret = PTR_ERR(rx_q->page_pool); 2005 rx_q->page_pool = NULL; 2006 return ret; 2007 } 2008 2009 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2010 sizeof(*rx_q->buf_pool), 2011 GFP_KERNEL); 2012 if (!rx_q->buf_pool) 2013 return -ENOMEM; 2014 2015 if (priv->extend_desc) { 2016 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2017 dma_conf->dma_rx_size * 2018 sizeof(struct dma_extended_desc), 2019 &rx_q->dma_rx_phy, 2020 GFP_KERNEL); 2021 if (!rx_q->dma_erx) 2022 return -ENOMEM; 2023 2024 } else { 2025 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2026 dma_conf->dma_rx_size * 2027 sizeof(struct dma_desc), 2028 &rx_q->dma_rx_phy, 2029 GFP_KERNEL); 2030 if (!rx_q->dma_rx) 2031 return -ENOMEM; 2032 } 2033 2034 if (stmmac_xdp_is_enabled(priv) && 2035 test_bit(queue, priv->af_xdp_zc_qps)) 2036 napi_id = ch->rxtx_napi.napi_id; 2037 else 2038 napi_id = ch->rx_napi.napi_id; 2039 2040 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2041 rx_q->queue_index, 2042 napi_id); 2043 if (ret) { 2044 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2045 return -EINVAL; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2052 struct stmmac_dma_conf *dma_conf) 2053 { 2054 u32 rx_count = priv->plat->rx_queues_to_use; 2055 u32 queue; 2056 int ret; 2057 2058 /* RX queues buffers and DMA */ 2059 for (queue = 0; queue < rx_count; queue++) { 2060 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2061 if (ret) 2062 goto err_dma; 2063 } 2064 2065 return 0; 2066 2067 err_dma: 2068 free_dma_rx_desc_resources(priv, dma_conf); 2069 2070 return ret; 2071 } 2072 2073 /** 2074 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2075 * @priv: private structure 2076 * @dma_conf: structure to take the dma data 2077 * @queue: TX queue index 2078 * Description: according to which descriptor can be used (extend or basic) 2079 * this function allocates the resources for TX and RX paths. In case of 2080 * reception, for example, it pre-allocated the RX socket buffer in order to 2081 * allow zero-copy mechanism. 2082 */ 2083 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2084 struct stmmac_dma_conf *dma_conf, 2085 u32 queue) 2086 { 2087 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2088 size_t size; 2089 void *addr; 2090 2091 tx_q->queue_index = queue; 2092 tx_q->priv_data = priv; 2093 2094 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2095 sizeof(*tx_q->tx_skbuff_dma), 2096 GFP_KERNEL); 2097 if (!tx_q->tx_skbuff_dma) 2098 return -ENOMEM; 2099 2100 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2101 sizeof(struct sk_buff *), 2102 GFP_KERNEL); 2103 if (!tx_q->tx_skbuff) 2104 return -ENOMEM; 2105 2106 if (priv->extend_desc) 2107 size = sizeof(struct dma_extended_desc); 2108 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2109 size = sizeof(struct dma_edesc); 2110 else 2111 size = sizeof(struct dma_desc); 2112 2113 size *= dma_conf->dma_tx_size; 2114 2115 addr = dma_alloc_coherent(priv->device, size, 2116 &tx_q->dma_tx_phy, GFP_KERNEL); 2117 if (!addr) 2118 return -ENOMEM; 2119 2120 if (priv->extend_desc) 2121 tx_q->dma_etx = addr; 2122 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2123 tx_q->dma_entx = addr; 2124 else 2125 tx_q->dma_tx = addr; 2126 2127 return 0; 2128 } 2129 2130 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2131 struct stmmac_dma_conf *dma_conf) 2132 { 2133 u32 tx_count = priv->plat->tx_queues_to_use; 2134 u32 queue; 2135 int ret; 2136 2137 /* TX queues buffers and DMA */ 2138 for (queue = 0; queue < tx_count; queue++) { 2139 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2140 if (ret) 2141 goto err_dma; 2142 } 2143 2144 return 0; 2145 2146 err_dma: 2147 free_dma_tx_desc_resources(priv, dma_conf); 2148 return ret; 2149 } 2150 2151 /** 2152 * alloc_dma_desc_resources - alloc TX/RX resources. 2153 * @priv: private structure 2154 * @dma_conf: structure to take the dma data 2155 * Description: according to which descriptor can be used (extend or basic) 2156 * this function allocates the resources for TX and RX paths. In case of 2157 * reception, for example, it pre-allocated the RX socket buffer in order to 2158 * allow zero-copy mechanism. 2159 */ 2160 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2161 struct stmmac_dma_conf *dma_conf) 2162 { 2163 /* RX Allocation */ 2164 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2165 2166 if (ret) 2167 return ret; 2168 2169 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2170 2171 return ret; 2172 } 2173 2174 /** 2175 * free_dma_desc_resources - free dma desc resources 2176 * @priv: private structure 2177 * @dma_conf: structure to take the dma data 2178 */ 2179 static void free_dma_desc_resources(struct stmmac_priv *priv, 2180 struct stmmac_dma_conf *dma_conf) 2181 { 2182 /* Release the DMA TX socket buffers */ 2183 free_dma_tx_desc_resources(priv, dma_conf); 2184 2185 /* Release the DMA RX socket buffers later 2186 * to ensure all pending XDP_TX buffers are returned. 2187 */ 2188 free_dma_rx_desc_resources(priv, dma_conf); 2189 } 2190 2191 /** 2192 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2193 * @priv: driver private structure 2194 * Description: It is used for enabling the rx queues in the MAC 2195 */ 2196 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2197 { 2198 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2199 int queue; 2200 u8 mode; 2201 2202 for (queue = 0; queue < rx_queues_count; queue++) { 2203 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2204 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2205 } 2206 } 2207 2208 /** 2209 * stmmac_start_rx_dma - start RX DMA channel 2210 * @priv: driver private structure 2211 * @chan: RX channel index 2212 * Description: 2213 * This starts a RX DMA channel 2214 */ 2215 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2216 { 2217 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2218 stmmac_start_rx(priv, priv->ioaddr, chan); 2219 } 2220 2221 /** 2222 * stmmac_start_tx_dma - start TX DMA channel 2223 * @priv: driver private structure 2224 * @chan: TX channel index 2225 * Description: 2226 * This starts a TX DMA channel 2227 */ 2228 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2229 { 2230 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2231 stmmac_start_tx(priv, priv->ioaddr, chan); 2232 } 2233 2234 /** 2235 * stmmac_stop_rx_dma - stop RX DMA channel 2236 * @priv: driver private structure 2237 * @chan: RX channel index 2238 * Description: 2239 * This stops a RX DMA channel 2240 */ 2241 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2242 { 2243 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2244 stmmac_stop_rx(priv, priv->ioaddr, chan); 2245 } 2246 2247 /** 2248 * stmmac_stop_tx_dma - stop TX DMA channel 2249 * @priv: driver private structure 2250 * @chan: TX channel index 2251 * Description: 2252 * This stops a TX DMA channel 2253 */ 2254 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2255 { 2256 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2257 stmmac_stop_tx(priv, priv->ioaddr, chan); 2258 } 2259 2260 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2261 { 2262 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2263 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2264 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2265 u32 chan; 2266 2267 for (chan = 0; chan < dma_csr_ch; chan++) { 2268 struct stmmac_channel *ch = &priv->channel[chan]; 2269 unsigned long flags; 2270 2271 spin_lock_irqsave(&ch->lock, flags); 2272 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2273 spin_unlock_irqrestore(&ch->lock, flags); 2274 } 2275 } 2276 2277 /** 2278 * stmmac_start_all_dma - start all RX and TX DMA channels 2279 * @priv: driver private structure 2280 * Description: 2281 * This starts all the RX and TX DMA channels 2282 */ 2283 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2284 { 2285 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2286 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2287 u32 chan = 0; 2288 2289 for (chan = 0; chan < rx_channels_count; chan++) 2290 stmmac_start_rx_dma(priv, chan); 2291 2292 for (chan = 0; chan < tx_channels_count; chan++) 2293 stmmac_start_tx_dma(priv, chan); 2294 } 2295 2296 /** 2297 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2298 * @priv: driver private structure 2299 * Description: 2300 * This stops the RX and TX DMA channels 2301 */ 2302 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2303 { 2304 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2305 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2306 u32 chan = 0; 2307 2308 for (chan = 0; chan < rx_channels_count; chan++) 2309 stmmac_stop_rx_dma(priv, chan); 2310 2311 for (chan = 0; chan < tx_channels_count; chan++) 2312 stmmac_stop_tx_dma(priv, chan); 2313 } 2314 2315 /** 2316 * stmmac_dma_operation_mode - HW DMA operation mode 2317 * @priv: driver private structure 2318 * Description: it is used for configuring the DMA operation mode register in 2319 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2320 */ 2321 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2322 { 2323 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2324 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2325 int rxfifosz = priv->plat->rx_fifo_size; 2326 int txfifosz = priv->plat->tx_fifo_size; 2327 u32 txmode = 0; 2328 u32 rxmode = 0; 2329 u32 chan = 0; 2330 u8 qmode = 0; 2331 2332 if (rxfifosz == 0) 2333 rxfifosz = priv->dma_cap.rx_fifo_size; 2334 if (txfifosz == 0) 2335 txfifosz = priv->dma_cap.tx_fifo_size; 2336 2337 /* Adjust for real per queue fifo size */ 2338 rxfifosz /= rx_channels_count; 2339 txfifosz /= tx_channels_count; 2340 2341 if (priv->plat->force_thresh_dma_mode) { 2342 txmode = tc; 2343 rxmode = tc; 2344 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2345 /* 2346 * In case of GMAC, SF mode can be enabled 2347 * to perform the TX COE in HW. This depends on: 2348 * 1) TX COE if actually supported 2349 * 2) There is no bugged Jumbo frame support 2350 * that needs to not insert csum in the TDES. 2351 */ 2352 txmode = SF_DMA_MODE; 2353 rxmode = SF_DMA_MODE; 2354 priv->xstats.threshold = SF_DMA_MODE; 2355 } else { 2356 txmode = tc; 2357 rxmode = SF_DMA_MODE; 2358 } 2359 2360 /* configure all channels */ 2361 for (chan = 0; chan < rx_channels_count; chan++) { 2362 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2363 u32 buf_size; 2364 2365 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2366 2367 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2368 rxfifosz, qmode); 2369 2370 if (rx_q->xsk_pool) { 2371 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2372 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2373 buf_size, 2374 chan); 2375 } else { 2376 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2377 priv->dma_conf.dma_buf_sz, 2378 chan); 2379 } 2380 } 2381 2382 for (chan = 0; chan < tx_channels_count; chan++) { 2383 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2384 2385 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2386 txfifosz, qmode); 2387 } 2388 } 2389 2390 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2391 { 2392 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2393 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2394 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2395 unsigned int entry = tx_q->cur_tx; 2396 struct dma_desc *tx_desc = NULL; 2397 struct xdp_desc xdp_desc; 2398 bool work_done = true; 2399 2400 /* Avoids TX time-out as we are sharing with slow path */ 2401 txq_trans_cond_update(nq); 2402 2403 budget = min(budget, stmmac_tx_avail(priv, queue)); 2404 2405 while (budget-- > 0) { 2406 dma_addr_t dma_addr; 2407 bool set_ic; 2408 2409 /* We are sharing with slow path and stop XSK TX desc submission when 2410 * available TX ring is less than threshold. 2411 */ 2412 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2413 !netif_carrier_ok(priv->dev)) { 2414 work_done = false; 2415 break; 2416 } 2417 2418 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2419 break; 2420 2421 if (likely(priv->extend_desc)) 2422 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2423 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2424 tx_desc = &tx_q->dma_entx[entry].basic; 2425 else 2426 tx_desc = tx_q->dma_tx + entry; 2427 2428 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2429 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2430 2431 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2432 2433 /* To return XDP buffer to XSK pool, we simple call 2434 * xsk_tx_completed(), so we don't need to fill up 2435 * 'buf' and 'xdpf'. 2436 */ 2437 tx_q->tx_skbuff_dma[entry].buf = 0; 2438 tx_q->xdpf[entry] = NULL; 2439 2440 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2441 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2442 tx_q->tx_skbuff_dma[entry].last_segment = true; 2443 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2444 2445 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2446 2447 tx_q->tx_count_frames++; 2448 2449 if (!priv->tx_coal_frames[queue]) 2450 set_ic = false; 2451 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2452 set_ic = true; 2453 else 2454 set_ic = false; 2455 2456 if (set_ic) { 2457 tx_q->tx_count_frames = 0; 2458 stmmac_set_tx_ic(priv, tx_desc); 2459 priv->xstats.tx_set_ic_bit++; 2460 } 2461 2462 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2463 true, priv->mode, true, true, 2464 xdp_desc.len); 2465 2466 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2467 2468 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2469 entry = tx_q->cur_tx; 2470 } 2471 2472 if (tx_desc) { 2473 stmmac_flush_tx_descriptors(priv, queue); 2474 xsk_tx_release(pool); 2475 } 2476 2477 /* Return true if all of the 3 conditions are met 2478 * a) TX Budget is still available 2479 * b) work_done = true when XSK TX desc peek is empty (no more 2480 * pending XSK TX for transmission) 2481 */ 2482 return !!budget && work_done; 2483 } 2484 2485 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2486 { 2487 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2488 tc += 64; 2489 2490 if (priv->plat->force_thresh_dma_mode) 2491 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2492 else 2493 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2494 chan); 2495 2496 priv->xstats.threshold = tc; 2497 } 2498 } 2499 2500 /** 2501 * stmmac_tx_clean - to manage the transmission completion 2502 * @priv: driver private structure 2503 * @budget: napi budget limiting this functions packet handling 2504 * @queue: TX queue index 2505 * Description: it reclaims the transmit resources after transmission completes. 2506 */ 2507 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2508 { 2509 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2510 unsigned int bytes_compl = 0, pkts_compl = 0; 2511 unsigned int entry, xmits = 0, count = 0; 2512 2513 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2514 2515 priv->xstats.tx_clean++; 2516 2517 tx_q->xsk_frames_done = 0; 2518 2519 entry = tx_q->dirty_tx; 2520 2521 /* Try to clean all TX complete frame in 1 shot */ 2522 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2523 struct xdp_frame *xdpf; 2524 struct sk_buff *skb; 2525 struct dma_desc *p; 2526 int status; 2527 2528 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2529 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2530 xdpf = tx_q->xdpf[entry]; 2531 skb = NULL; 2532 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2533 xdpf = NULL; 2534 skb = tx_q->tx_skbuff[entry]; 2535 } else { 2536 xdpf = NULL; 2537 skb = NULL; 2538 } 2539 2540 if (priv->extend_desc) 2541 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2542 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2543 p = &tx_q->dma_entx[entry].basic; 2544 else 2545 p = tx_q->dma_tx + entry; 2546 2547 status = stmmac_tx_status(priv, &priv->dev->stats, 2548 &priv->xstats, p, priv->ioaddr); 2549 /* Check if the descriptor is owned by the DMA */ 2550 if (unlikely(status & tx_dma_own)) 2551 break; 2552 2553 count++; 2554 2555 /* Make sure descriptor fields are read after reading 2556 * the own bit. 2557 */ 2558 dma_rmb(); 2559 2560 /* Just consider the last segment and ...*/ 2561 if (likely(!(status & tx_not_ls))) { 2562 /* ... verify the status error condition */ 2563 if (unlikely(status & tx_err)) { 2564 priv->dev->stats.tx_errors++; 2565 if (unlikely(status & tx_err_bump_tc)) 2566 stmmac_bump_dma_threshold(priv, queue); 2567 } else { 2568 priv->dev->stats.tx_packets++; 2569 priv->xstats.tx_pkt_n++; 2570 priv->xstats.txq_stats[queue].tx_pkt_n++; 2571 } 2572 if (skb) 2573 stmmac_get_tx_hwtstamp(priv, p, skb); 2574 } 2575 2576 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2577 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2578 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2579 dma_unmap_page(priv->device, 2580 tx_q->tx_skbuff_dma[entry].buf, 2581 tx_q->tx_skbuff_dma[entry].len, 2582 DMA_TO_DEVICE); 2583 else 2584 dma_unmap_single(priv->device, 2585 tx_q->tx_skbuff_dma[entry].buf, 2586 tx_q->tx_skbuff_dma[entry].len, 2587 DMA_TO_DEVICE); 2588 tx_q->tx_skbuff_dma[entry].buf = 0; 2589 tx_q->tx_skbuff_dma[entry].len = 0; 2590 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2591 } 2592 2593 stmmac_clean_desc3(priv, tx_q, p); 2594 2595 tx_q->tx_skbuff_dma[entry].last_segment = false; 2596 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2597 2598 if (xdpf && 2599 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2600 xdp_return_frame_rx_napi(xdpf); 2601 tx_q->xdpf[entry] = NULL; 2602 } 2603 2604 if (xdpf && 2605 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2606 xdp_return_frame(xdpf); 2607 tx_q->xdpf[entry] = NULL; 2608 } 2609 2610 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2611 tx_q->xsk_frames_done++; 2612 2613 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2614 if (likely(skb)) { 2615 pkts_compl++; 2616 bytes_compl += skb->len; 2617 dev_consume_skb_any(skb); 2618 tx_q->tx_skbuff[entry] = NULL; 2619 } 2620 } 2621 2622 stmmac_release_tx_desc(priv, p, priv->mode); 2623 2624 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2625 } 2626 tx_q->dirty_tx = entry; 2627 2628 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2629 pkts_compl, bytes_compl); 2630 2631 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2632 queue))) && 2633 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2634 2635 netif_dbg(priv, tx_done, priv->dev, 2636 "%s: restart transmit\n", __func__); 2637 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2638 } 2639 2640 if (tx_q->xsk_pool) { 2641 bool work_done; 2642 2643 if (tx_q->xsk_frames_done) 2644 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2645 2646 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2647 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2648 2649 /* For XSK TX, we try to send as many as possible. 2650 * If XSK work done (XSK TX desc empty and budget still 2651 * available), return "budget - 1" to reenable TX IRQ. 2652 * Else, return "budget" to make NAPI continue polling. 2653 */ 2654 work_done = stmmac_xdp_xmit_zc(priv, queue, 2655 STMMAC_XSK_TX_BUDGET_MAX); 2656 if (work_done) 2657 xmits = budget - 1; 2658 else 2659 xmits = budget; 2660 } 2661 2662 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2663 priv->eee_sw_timer_en) { 2664 if (stmmac_enable_eee_mode(priv)) 2665 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2666 } 2667 2668 /* We still have pending packets, let's call for a new scheduling */ 2669 if (tx_q->dirty_tx != tx_q->cur_tx) 2670 hrtimer_start(&tx_q->txtimer, 2671 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2672 HRTIMER_MODE_REL); 2673 2674 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2675 2676 /* Combine decisions from TX clean and XSK TX */ 2677 return max(count, xmits); 2678 } 2679 2680 /** 2681 * stmmac_tx_err - to manage the tx error 2682 * @priv: driver private structure 2683 * @chan: channel index 2684 * Description: it cleans the descriptors and restarts the transmission 2685 * in case of transmission errors. 2686 */ 2687 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2688 { 2689 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2690 2691 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2692 2693 stmmac_stop_tx_dma(priv, chan); 2694 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2695 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2696 stmmac_reset_tx_queue(priv, chan); 2697 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2698 tx_q->dma_tx_phy, chan); 2699 stmmac_start_tx_dma(priv, chan); 2700 2701 priv->dev->stats.tx_errors++; 2702 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2703 } 2704 2705 /** 2706 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2707 * @priv: driver private structure 2708 * @txmode: TX operating mode 2709 * @rxmode: RX operating mode 2710 * @chan: channel index 2711 * Description: it is used for configuring of the DMA operation mode in 2712 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2713 * mode. 2714 */ 2715 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2716 u32 rxmode, u32 chan) 2717 { 2718 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2719 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2720 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2721 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2722 int rxfifosz = priv->plat->rx_fifo_size; 2723 int txfifosz = priv->plat->tx_fifo_size; 2724 2725 if (rxfifosz == 0) 2726 rxfifosz = priv->dma_cap.rx_fifo_size; 2727 if (txfifosz == 0) 2728 txfifosz = priv->dma_cap.tx_fifo_size; 2729 2730 /* Adjust for real per queue fifo size */ 2731 rxfifosz /= rx_channels_count; 2732 txfifosz /= tx_channels_count; 2733 2734 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2735 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2736 } 2737 2738 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2739 { 2740 int ret; 2741 2742 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2743 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2744 if (ret && (ret != -EINVAL)) { 2745 stmmac_global_err(priv); 2746 return true; 2747 } 2748 2749 return false; 2750 } 2751 2752 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2753 { 2754 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2755 &priv->xstats, chan, dir); 2756 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2757 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2758 struct stmmac_channel *ch = &priv->channel[chan]; 2759 struct napi_struct *rx_napi; 2760 struct napi_struct *tx_napi; 2761 unsigned long flags; 2762 2763 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2764 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2765 2766 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2767 if (napi_schedule_prep(rx_napi)) { 2768 spin_lock_irqsave(&ch->lock, flags); 2769 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2770 spin_unlock_irqrestore(&ch->lock, flags); 2771 __napi_schedule(rx_napi); 2772 } 2773 } 2774 2775 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2776 if (napi_schedule_prep(tx_napi)) { 2777 spin_lock_irqsave(&ch->lock, flags); 2778 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2779 spin_unlock_irqrestore(&ch->lock, flags); 2780 __napi_schedule(tx_napi); 2781 } 2782 } 2783 2784 return status; 2785 } 2786 2787 /** 2788 * stmmac_dma_interrupt - DMA ISR 2789 * @priv: driver private structure 2790 * Description: this is the DMA ISR. It is called by the main ISR. 2791 * It calls the dwmac dma routine and schedule poll method in case of some 2792 * work can be done. 2793 */ 2794 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2795 { 2796 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2797 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2798 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2799 tx_channel_count : rx_channel_count; 2800 u32 chan; 2801 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2802 2803 /* Make sure we never check beyond our status buffer. */ 2804 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2805 channels_to_check = ARRAY_SIZE(status); 2806 2807 for (chan = 0; chan < channels_to_check; chan++) 2808 status[chan] = stmmac_napi_check(priv, chan, 2809 DMA_DIR_RXTX); 2810 2811 for (chan = 0; chan < tx_channel_count; chan++) { 2812 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2813 /* Try to bump up the dma threshold on this failure */ 2814 stmmac_bump_dma_threshold(priv, chan); 2815 } else if (unlikely(status[chan] == tx_hard_error)) { 2816 stmmac_tx_err(priv, chan); 2817 } 2818 } 2819 } 2820 2821 /** 2822 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2823 * @priv: driver private structure 2824 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2825 */ 2826 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2827 { 2828 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2829 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2830 2831 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2832 2833 if (priv->dma_cap.rmon) { 2834 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2835 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2836 } else 2837 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2838 } 2839 2840 /** 2841 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2842 * @priv: driver private structure 2843 * Description: 2844 * new GMAC chip generations have a new register to indicate the 2845 * presence of the optional feature/functions. 2846 * This can be also used to override the value passed through the 2847 * platform and necessary for old MAC10/100 and GMAC chips. 2848 */ 2849 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2850 { 2851 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2852 } 2853 2854 /** 2855 * stmmac_check_ether_addr - check if the MAC addr is valid 2856 * @priv: driver private structure 2857 * Description: 2858 * it is to verify if the MAC address is valid, in case of failures it 2859 * generates a random MAC address 2860 */ 2861 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2862 { 2863 u8 addr[ETH_ALEN]; 2864 2865 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2866 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2867 if (is_valid_ether_addr(addr)) 2868 eth_hw_addr_set(priv->dev, addr); 2869 else 2870 eth_hw_addr_random(priv->dev); 2871 dev_info(priv->device, "device MAC address %pM\n", 2872 priv->dev->dev_addr); 2873 } 2874 } 2875 2876 /** 2877 * stmmac_init_dma_engine - DMA init. 2878 * @priv: driver private structure 2879 * Description: 2880 * It inits the DMA invoking the specific MAC/GMAC callback. 2881 * Some DMA parameters can be passed from the platform; 2882 * in case of these are not passed a default is kept for the MAC or GMAC. 2883 */ 2884 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2885 { 2886 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2887 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2888 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2889 struct stmmac_rx_queue *rx_q; 2890 struct stmmac_tx_queue *tx_q; 2891 u32 chan = 0; 2892 int atds = 0; 2893 int ret = 0; 2894 2895 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2896 dev_err(priv->device, "Invalid DMA configuration\n"); 2897 return -EINVAL; 2898 } 2899 2900 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2901 atds = 1; 2902 2903 ret = stmmac_reset(priv, priv->ioaddr); 2904 if (ret) { 2905 dev_err(priv->device, "Failed to reset the dma\n"); 2906 return ret; 2907 } 2908 2909 /* DMA Configuration */ 2910 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2911 2912 if (priv->plat->axi) 2913 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2914 2915 /* DMA CSR Channel configuration */ 2916 for (chan = 0; chan < dma_csr_ch; chan++) { 2917 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2918 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2919 } 2920 2921 /* DMA RX Channel Configuration */ 2922 for (chan = 0; chan < rx_channels_count; chan++) { 2923 rx_q = &priv->dma_conf.rx_queue[chan]; 2924 2925 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2926 rx_q->dma_rx_phy, chan); 2927 2928 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2929 (rx_q->buf_alloc_num * 2930 sizeof(struct dma_desc)); 2931 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2932 rx_q->rx_tail_addr, chan); 2933 } 2934 2935 /* DMA TX Channel Configuration */ 2936 for (chan = 0; chan < tx_channels_count; chan++) { 2937 tx_q = &priv->dma_conf.tx_queue[chan]; 2938 2939 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2940 tx_q->dma_tx_phy, chan); 2941 2942 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2943 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2944 tx_q->tx_tail_addr, chan); 2945 } 2946 2947 return ret; 2948 } 2949 2950 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2951 { 2952 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2953 2954 hrtimer_start(&tx_q->txtimer, 2955 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2956 HRTIMER_MODE_REL); 2957 } 2958 2959 /** 2960 * stmmac_tx_timer - mitigation sw timer for tx. 2961 * @t: data pointer 2962 * Description: 2963 * This is the timer handler to directly invoke the stmmac_tx_clean. 2964 */ 2965 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2966 { 2967 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2968 struct stmmac_priv *priv = tx_q->priv_data; 2969 struct stmmac_channel *ch; 2970 struct napi_struct *napi; 2971 2972 ch = &priv->channel[tx_q->queue_index]; 2973 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2974 2975 if (likely(napi_schedule_prep(napi))) { 2976 unsigned long flags; 2977 2978 spin_lock_irqsave(&ch->lock, flags); 2979 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2980 spin_unlock_irqrestore(&ch->lock, flags); 2981 __napi_schedule(napi); 2982 } 2983 2984 return HRTIMER_NORESTART; 2985 } 2986 2987 /** 2988 * stmmac_init_coalesce - init mitigation options. 2989 * @priv: driver private structure 2990 * Description: 2991 * This inits the coalesce parameters: i.e. timer rate, 2992 * timer handler and default threshold used for enabling the 2993 * interrupt on completion bit. 2994 */ 2995 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2996 { 2997 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2998 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2999 u32 chan; 3000 3001 for (chan = 0; chan < tx_channel_count; chan++) { 3002 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3003 3004 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3005 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3006 3007 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3008 tx_q->txtimer.function = stmmac_tx_timer; 3009 } 3010 3011 for (chan = 0; chan < rx_channel_count; chan++) 3012 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3013 } 3014 3015 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3016 { 3017 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3018 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3019 u32 chan; 3020 3021 /* set TX ring length */ 3022 for (chan = 0; chan < tx_channels_count; chan++) 3023 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3024 (priv->dma_conf.dma_tx_size - 1), chan); 3025 3026 /* set RX ring length */ 3027 for (chan = 0; chan < rx_channels_count; chan++) 3028 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3029 (priv->dma_conf.dma_rx_size - 1), chan); 3030 } 3031 3032 /** 3033 * stmmac_set_tx_queue_weight - Set TX queue weight 3034 * @priv: driver private structure 3035 * Description: It is used for setting TX queues weight 3036 */ 3037 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3038 { 3039 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3040 u32 weight; 3041 u32 queue; 3042 3043 for (queue = 0; queue < tx_queues_count; queue++) { 3044 weight = priv->plat->tx_queues_cfg[queue].weight; 3045 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3046 } 3047 } 3048 3049 /** 3050 * stmmac_configure_cbs - Configure CBS in TX queue 3051 * @priv: driver private structure 3052 * Description: It is used for configuring CBS in AVB TX queues 3053 */ 3054 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3055 { 3056 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3057 u32 mode_to_use; 3058 u32 queue; 3059 3060 /* queue 0 is reserved for legacy traffic */ 3061 for (queue = 1; queue < tx_queues_count; queue++) { 3062 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3063 if (mode_to_use == MTL_QUEUE_DCB) 3064 continue; 3065 3066 stmmac_config_cbs(priv, priv->hw, 3067 priv->plat->tx_queues_cfg[queue].send_slope, 3068 priv->plat->tx_queues_cfg[queue].idle_slope, 3069 priv->plat->tx_queues_cfg[queue].high_credit, 3070 priv->plat->tx_queues_cfg[queue].low_credit, 3071 queue); 3072 } 3073 } 3074 3075 /** 3076 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3077 * @priv: driver private structure 3078 * Description: It is used for mapping RX queues to RX dma channels 3079 */ 3080 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3081 { 3082 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3083 u32 queue; 3084 u32 chan; 3085 3086 for (queue = 0; queue < rx_queues_count; queue++) { 3087 chan = priv->plat->rx_queues_cfg[queue].chan; 3088 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3089 } 3090 } 3091 3092 /** 3093 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3094 * @priv: driver private structure 3095 * Description: It is used for configuring the RX Queue Priority 3096 */ 3097 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3098 { 3099 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3100 u32 queue; 3101 u32 prio; 3102 3103 for (queue = 0; queue < rx_queues_count; queue++) { 3104 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3105 continue; 3106 3107 prio = priv->plat->rx_queues_cfg[queue].prio; 3108 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3109 } 3110 } 3111 3112 /** 3113 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3114 * @priv: driver private structure 3115 * Description: It is used for configuring the TX Queue Priority 3116 */ 3117 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3118 { 3119 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3120 u32 queue; 3121 u32 prio; 3122 3123 for (queue = 0; queue < tx_queues_count; queue++) { 3124 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3125 continue; 3126 3127 prio = priv->plat->tx_queues_cfg[queue].prio; 3128 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3129 } 3130 } 3131 3132 /** 3133 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3134 * @priv: driver private structure 3135 * Description: It is used for configuring the RX queue routing 3136 */ 3137 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3138 { 3139 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3140 u32 queue; 3141 u8 packet; 3142 3143 for (queue = 0; queue < rx_queues_count; queue++) { 3144 /* no specific packet type routing specified for the queue */ 3145 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3146 continue; 3147 3148 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3149 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3150 } 3151 } 3152 3153 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3154 { 3155 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3156 priv->rss.enable = false; 3157 return; 3158 } 3159 3160 if (priv->dev->features & NETIF_F_RXHASH) 3161 priv->rss.enable = true; 3162 else 3163 priv->rss.enable = false; 3164 3165 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3166 priv->plat->rx_queues_to_use); 3167 } 3168 3169 /** 3170 * stmmac_mtl_configuration - Configure MTL 3171 * @priv: driver private structure 3172 * Description: It is used for configurring MTL 3173 */ 3174 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3175 { 3176 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3177 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3178 3179 if (tx_queues_count > 1) 3180 stmmac_set_tx_queue_weight(priv); 3181 3182 /* Configure MTL RX algorithms */ 3183 if (rx_queues_count > 1) 3184 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3185 priv->plat->rx_sched_algorithm); 3186 3187 /* Configure MTL TX algorithms */ 3188 if (tx_queues_count > 1) 3189 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3190 priv->plat->tx_sched_algorithm); 3191 3192 /* Configure CBS in AVB TX queues */ 3193 if (tx_queues_count > 1) 3194 stmmac_configure_cbs(priv); 3195 3196 /* Map RX MTL to DMA channels */ 3197 stmmac_rx_queue_dma_chan_map(priv); 3198 3199 /* Enable MAC RX Queues */ 3200 stmmac_mac_enable_rx_queues(priv); 3201 3202 /* Set RX priorities */ 3203 if (rx_queues_count > 1) 3204 stmmac_mac_config_rx_queues_prio(priv); 3205 3206 /* Set TX priorities */ 3207 if (tx_queues_count > 1) 3208 stmmac_mac_config_tx_queues_prio(priv); 3209 3210 /* Set RX routing */ 3211 if (rx_queues_count > 1) 3212 stmmac_mac_config_rx_queues_routing(priv); 3213 3214 /* Receive Side Scaling */ 3215 if (rx_queues_count > 1) 3216 stmmac_mac_config_rss(priv); 3217 } 3218 3219 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3220 { 3221 if (priv->dma_cap.asp) { 3222 netdev_info(priv->dev, "Enabling Safety Features\n"); 3223 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3224 priv->plat->safety_feat_cfg); 3225 } else { 3226 netdev_info(priv->dev, "No Safety Features support found\n"); 3227 } 3228 } 3229 3230 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3231 { 3232 char *name; 3233 3234 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3235 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3236 3237 name = priv->wq_name; 3238 sprintf(name, "%s-fpe", priv->dev->name); 3239 3240 priv->fpe_wq = create_singlethread_workqueue(name); 3241 if (!priv->fpe_wq) { 3242 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3243 3244 return -ENOMEM; 3245 } 3246 netdev_info(priv->dev, "FPE workqueue start"); 3247 3248 return 0; 3249 } 3250 3251 /** 3252 * stmmac_hw_setup - setup mac in a usable state. 3253 * @dev : pointer to the device structure. 3254 * @ptp_register: register PTP if set 3255 * Description: 3256 * this is the main function to setup the HW in a usable state because the 3257 * dma engine is reset, the core registers are configured (e.g. AXI, 3258 * Checksum features, timers). The DMA is ready to start receiving and 3259 * transmitting. 3260 * Return value: 3261 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3262 * file on failure. 3263 */ 3264 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3265 { 3266 struct stmmac_priv *priv = netdev_priv(dev); 3267 u32 rx_cnt = priv->plat->rx_queues_to_use; 3268 u32 tx_cnt = priv->plat->tx_queues_to_use; 3269 bool sph_en; 3270 u32 chan; 3271 int ret; 3272 3273 /* DMA initialization and SW reset */ 3274 ret = stmmac_init_dma_engine(priv); 3275 if (ret < 0) { 3276 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3277 __func__); 3278 return ret; 3279 } 3280 3281 /* Copy the MAC addr into the HW */ 3282 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3283 3284 /* PS and related bits will be programmed according to the speed */ 3285 if (priv->hw->pcs) { 3286 int speed = priv->plat->mac_port_sel_speed; 3287 3288 if ((speed == SPEED_10) || (speed == SPEED_100) || 3289 (speed == SPEED_1000)) { 3290 priv->hw->ps = speed; 3291 } else { 3292 dev_warn(priv->device, "invalid port speed\n"); 3293 priv->hw->ps = 0; 3294 } 3295 } 3296 3297 /* Initialize the MAC Core */ 3298 stmmac_core_init(priv, priv->hw, dev); 3299 3300 /* Initialize MTL*/ 3301 stmmac_mtl_configuration(priv); 3302 3303 /* Initialize Safety Features */ 3304 stmmac_safety_feat_configuration(priv); 3305 3306 ret = stmmac_rx_ipc(priv, priv->hw); 3307 if (!ret) { 3308 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3309 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3310 priv->hw->rx_csum = 0; 3311 } 3312 3313 /* Enable the MAC Rx/Tx */ 3314 stmmac_mac_set(priv, priv->ioaddr, true); 3315 3316 /* Set the HW DMA mode and the COE */ 3317 stmmac_dma_operation_mode(priv); 3318 3319 stmmac_mmc_setup(priv); 3320 3321 if (ptp_register) { 3322 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3323 if (ret < 0) 3324 netdev_warn(priv->dev, 3325 "failed to enable PTP reference clock: %pe\n", 3326 ERR_PTR(ret)); 3327 } 3328 3329 ret = stmmac_init_ptp(priv); 3330 if (ret == -EOPNOTSUPP) 3331 netdev_info(priv->dev, "PTP not supported by HW\n"); 3332 else if (ret) 3333 netdev_warn(priv->dev, "PTP init failed\n"); 3334 else if (ptp_register) 3335 stmmac_ptp_register(priv); 3336 3337 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3338 3339 /* Convert the timer from msec to usec */ 3340 if (!priv->tx_lpi_timer) 3341 priv->tx_lpi_timer = eee_timer * 1000; 3342 3343 if (priv->use_riwt) { 3344 u32 queue; 3345 3346 for (queue = 0; queue < rx_cnt; queue++) { 3347 if (!priv->rx_riwt[queue]) 3348 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3349 3350 stmmac_rx_watchdog(priv, priv->ioaddr, 3351 priv->rx_riwt[queue], queue); 3352 } 3353 } 3354 3355 if (priv->hw->pcs) 3356 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3357 3358 /* set TX and RX rings length */ 3359 stmmac_set_rings_length(priv); 3360 3361 /* Enable TSO */ 3362 if (priv->tso) { 3363 for (chan = 0; chan < tx_cnt; chan++) { 3364 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3365 3366 /* TSO and TBS cannot co-exist */ 3367 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3368 continue; 3369 3370 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3371 } 3372 } 3373 3374 /* Enable Split Header */ 3375 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3376 for (chan = 0; chan < rx_cnt; chan++) 3377 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3378 3379 3380 /* VLAN Tag Insertion */ 3381 if (priv->dma_cap.vlins) 3382 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3383 3384 /* TBS */ 3385 for (chan = 0; chan < tx_cnt; chan++) { 3386 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3387 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3388 3389 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3390 } 3391 3392 /* Configure real RX and TX queues */ 3393 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3394 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3395 3396 /* Start the ball rolling... */ 3397 stmmac_start_all_dma(priv); 3398 3399 if (priv->dma_cap.fpesel) { 3400 stmmac_fpe_start_wq(priv); 3401 3402 if (priv->plat->fpe_cfg->enable) 3403 stmmac_fpe_handshake(priv, true); 3404 } 3405 3406 return 0; 3407 } 3408 3409 static void stmmac_hw_teardown(struct net_device *dev) 3410 { 3411 struct stmmac_priv *priv = netdev_priv(dev); 3412 3413 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3414 } 3415 3416 static void stmmac_free_irq(struct net_device *dev, 3417 enum request_irq_err irq_err, int irq_idx) 3418 { 3419 struct stmmac_priv *priv = netdev_priv(dev); 3420 int j; 3421 3422 switch (irq_err) { 3423 case REQ_IRQ_ERR_ALL: 3424 irq_idx = priv->plat->tx_queues_to_use; 3425 fallthrough; 3426 case REQ_IRQ_ERR_TX: 3427 for (j = irq_idx - 1; j >= 0; j--) { 3428 if (priv->tx_irq[j] > 0) { 3429 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3430 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3431 } 3432 } 3433 irq_idx = priv->plat->rx_queues_to_use; 3434 fallthrough; 3435 case REQ_IRQ_ERR_RX: 3436 for (j = irq_idx - 1; j >= 0; j--) { 3437 if (priv->rx_irq[j] > 0) { 3438 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3439 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3440 } 3441 } 3442 3443 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3444 free_irq(priv->sfty_ue_irq, dev); 3445 fallthrough; 3446 case REQ_IRQ_ERR_SFTY_UE: 3447 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3448 free_irq(priv->sfty_ce_irq, dev); 3449 fallthrough; 3450 case REQ_IRQ_ERR_SFTY_CE: 3451 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3452 free_irq(priv->lpi_irq, dev); 3453 fallthrough; 3454 case REQ_IRQ_ERR_LPI: 3455 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3456 free_irq(priv->wol_irq, dev); 3457 fallthrough; 3458 case REQ_IRQ_ERR_WOL: 3459 free_irq(dev->irq, dev); 3460 fallthrough; 3461 case REQ_IRQ_ERR_MAC: 3462 case REQ_IRQ_ERR_NO: 3463 /* If MAC IRQ request error, no more IRQ to free */ 3464 break; 3465 } 3466 } 3467 3468 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3469 { 3470 struct stmmac_priv *priv = netdev_priv(dev); 3471 enum request_irq_err irq_err; 3472 cpumask_t cpu_mask; 3473 int irq_idx = 0; 3474 char *int_name; 3475 int ret; 3476 int i; 3477 3478 /* For common interrupt */ 3479 int_name = priv->int_name_mac; 3480 sprintf(int_name, "%s:%s", dev->name, "mac"); 3481 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3482 0, int_name, dev); 3483 if (unlikely(ret < 0)) { 3484 netdev_err(priv->dev, 3485 "%s: alloc mac MSI %d (error: %d)\n", 3486 __func__, dev->irq, ret); 3487 irq_err = REQ_IRQ_ERR_MAC; 3488 goto irq_error; 3489 } 3490 3491 /* Request the Wake IRQ in case of another line 3492 * is used for WoL 3493 */ 3494 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3495 int_name = priv->int_name_wol; 3496 sprintf(int_name, "%s:%s", dev->name, "wol"); 3497 ret = request_irq(priv->wol_irq, 3498 stmmac_mac_interrupt, 3499 0, int_name, dev); 3500 if (unlikely(ret < 0)) { 3501 netdev_err(priv->dev, 3502 "%s: alloc wol MSI %d (error: %d)\n", 3503 __func__, priv->wol_irq, ret); 3504 irq_err = REQ_IRQ_ERR_WOL; 3505 goto irq_error; 3506 } 3507 } 3508 3509 /* Request the LPI IRQ in case of another line 3510 * is used for LPI 3511 */ 3512 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3513 int_name = priv->int_name_lpi; 3514 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3515 ret = request_irq(priv->lpi_irq, 3516 stmmac_mac_interrupt, 3517 0, int_name, dev); 3518 if (unlikely(ret < 0)) { 3519 netdev_err(priv->dev, 3520 "%s: alloc lpi MSI %d (error: %d)\n", 3521 __func__, priv->lpi_irq, ret); 3522 irq_err = REQ_IRQ_ERR_LPI; 3523 goto irq_error; 3524 } 3525 } 3526 3527 /* Request the Safety Feature Correctible Error line in 3528 * case of another line is used 3529 */ 3530 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3531 int_name = priv->int_name_sfty_ce; 3532 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3533 ret = request_irq(priv->sfty_ce_irq, 3534 stmmac_safety_interrupt, 3535 0, int_name, dev); 3536 if (unlikely(ret < 0)) { 3537 netdev_err(priv->dev, 3538 "%s: alloc sfty ce MSI %d (error: %d)\n", 3539 __func__, priv->sfty_ce_irq, ret); 3540 irq_err = REQ_IRQ_ERR_SFTY_CE; 3541 goto irq_error; 3542 } 3543 } 3544 3545 /* Request the Safety Feature Uncorrectible Error line in 3546 * case of another line is used 3547 */ 3548 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3549 int_name = priv->int_name_sfty_ue; 3550 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3551 ret = request_irq(priv->sfty_ue_irq, 3552 stmmac_safety_interrupt, 3553 0, int_name, dev); 3554 if (unlikely(ret < 0)) { 3555 netdev_err(priv->dev, 3556 "%s: alloc sfty ue MSI %d (error: %d)\n", 3557 __func__, priv->sfty_ue_irq, ret); 3558 irq_err = REQ_IRQ_ERR_SFTY_UE; 3559 goto irq_error; 3560 } 3561 } 3562 3563 /* Request Rx MSI irq */ 3564 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3565 if (i >= MTL_MAX_RX_QUEUES) 3566 break; 3567 if (priv->rx_irq[i] == 0) 3568 continue; 3569 3570 int_name = priv->int_name_rx_irq[i]; 3571 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3572 ret = request_irq(priv->rx_irq[i], 3573 stmmac_msi_intr_rx, 3574 0, int_name, &priv->dma_conf.rx_queue[i]); 3575 if (unlikely(ret < 0)) { 3576 netdev_err(priv->dev, 3577 "%s: alloc rx-%d MSI %d (error: %d)\n", 3578 __func__, i, priv->rx_irq[i], ret); 3579 irq_err = REQ_IRQ_ERR_RX; 3580 irq_idx = i; 3581 goto irq_error; 3582 } 3583 cpumask_clear(&cpu_mask); 3584 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3585 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3586 } 3587 3588 /* Request Tx MSI irq */ 3589 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3590 if (i >= MTL_MAX_TX_QUEUES) 3591 break; 3592 if (priv->tx_irq[i] == 0) 3593 continue; 3594 3595 int_name = priv->int_name_tx_irq[i]; 3596 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3597 ret = request_irq(priv->tx_irq[i], 3598 stmmac_msi_intr_tx, 3599 0, int_name, &priv->dma_conf.tx_queue[i]); 3600 if (unlikely(ret < 0)) { 3601 netdev_err(priv->dev, 3602 "%s: alloc tx-%d MSI %d (error: %d)\n", 3603 __func__, i, priv->tx_irq[i], ret); 3604 irq_err = REQ_IRQ_ERR_TX; 3605 irq_idx = i; 3606 goto irq_error; 3607 } 3608 cpumask_clear(&cpu_mask); 3609 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3610 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3611 } 3612 3613 return 0; 3614 3615 irq_error: 3616 stmmac_free_irq(dev, irq_err, irq_idx); 3617 return ret; 3618 } 3619 3620 static int stmmac_request_irq_single(struct net_device *dev) 3621 { 3622 struct stmmac_priv *priv = netdev_priv(dev); 3623 enum request_irq_err irq_err; 3624 int ret; 3625 3626 ret = request_irq(dev->irq, stmmac_interrupt, 3627 IRQF_SHARED, dev->name, dev); 3628 if (unlikely(ret < 0)) { 3629 netdev_err(priv->dev, 3630 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3631 __func__, dev->irq, ret); 3632 irq_err = REQ_IRQ_ERR_MAC; 3633 goto irq_error; 3634 } 3635 3636 /* Request the Wake IRQ in case of another line 3637 * is used for WoL 3638 */ 3639 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3640 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3641 IRQF_SHARED, dev->name, dev); 3642 if (unlikely(ret < 0)) { 3643 netdev_err(priv->dev, 3644 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3645 __func__, priv->wol_irq, ret); 3646 irq_err = REQ_IRQ_ERR_WOL; 3647 goto irq_error; 3648 } 3649 } 3650 3651 /* Request the IRQ lines */ 3652 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3653 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3654 IRQF_SHARED, dev->name, dev); 3655 if (unlikely(ret < 0)) { 3656 netdev_err(priv->dev, 3657 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3658 __func__, priv->lpi_irq, ret); 3659 irq_err = REQ_IRQ_ERR_LPI; 3660 goto irq_error; 3661 } 3662 } 3663 3664 return 0; 3665 3666 irq_error: 3667 stmmac_free_irq(dev, irq_err, 0); 3668 return ret; 3669 } 3670 3671 static int stmmac_request_irq(struct net_device *dev) 3672 { 3673 struct stmmac_priv *priv = netdev_priv(dev); 3674 int ret; 3675 3676 /* Request the IRQ lines */ 3677 if (priv->plat->multi_msi_en) 3678 ret = stmmac_request_irq_multi_msi(dev); 3679 else 3680 ret = stmmac_request_irq_single(dev); 3681 3682 return ret; 3683 } 3684 3685 /** 3686 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3687 * @priv: driver private structure 3688 * @mtu: MTU to setup the dma queue and buf with 3689 * Description: Allocate and generate a dma_conf based on the provided MTU. 3690 * Allocate the Tx/Rx DMA queue and init them. 3691 * Return value: 3692 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3693 */ 3694 static struct stmmac_dma_conf * 3695 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3696 { 3697 struct stmmac_dma_conf *dma_conf; 3698 int chan, bfsize, ret; 3699 3700 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3701 if (!dma_conf) { 3702 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3703 __func__); 3704 return ERR_PTR(-ENOMEM); 3705 } 3706 3707 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3708 if (bfsize < 0) 3709 bfsize = 0; 3710 3711 if (bfsize < BUF_SIZE_16KiB) 3712 bfsize = stmmac_set_bfsize(mtu, 0); 3713 3714 dma_conf->dma_buf_sz = bfsize; 3715 /* Chose the tx/rx size from the already defined one in the 3716 * priv struct. (if defined) 3717 */ 3718 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3719 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3720 3721 if (!dma_conf->dma_tx_size) 3722 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3723 if (!dma_conf->dma_rx_size) 3724 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3725 3726 /* Earlier check for TBS */ 3727 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3728 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3729 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3730 3731 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3732 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3733 } 3734 3735 ret = alloc_dma_desc_resources(priv, dma_conf); 3736 if (ret < 0) { 3737 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3738 __func__); 3739 goto alloc_error; 3740 } 3741 3742 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3743 if (ret < 0) { 3744 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3745 __func__); 3746 goto init_error; 3747 } 3748 3749 return dma_conf; 3750 3751 init_error: 3752 free_dma_desc_resources(priv, dma_conf); 3753 alloc_error: 3754 kfree(dma_conf); 3755 return ERR_PTR(ret); 3756 } 3757 3758 /** 3759 * __stmmac_open - open entry point of the driver 3760 * @dev : pointer to the device structure. 3761 * @dma_conf : structure to take the dma data 3762 * Description: 3763 * This function is the open entry point of the driver. 3764 * Return value: 3765 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3766 * file on failure. 3767 */ 3768 static int __stmmac_open(struct net_device *dev, 3769 struct stmmac_dma_conf *dma_conf) 3770 { 3771 struct stmmac_priv *priv = netdev_priv(dev); 3772 int mode = priv->plat->phy_interface; 3773 u32 chan; 3774 int ret; 3775 3776 ret = pm_runtime_resume_and_get(priv->device); 3777 if (ret < 0) 3778 return ret; 3779 3780 if (priv->hw->pcs != STMMAC_PCS_TBI && 3781 priv->hw->pcs != STMMAC_PCS_RTBI && 3782 (!priv->hw->xpcs || 3783 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3784 ret = stmmac_init_phy(dev); 3785 if (ret) { 3786 netdev_err(priv->dev, 3787 "%s: Cannot attach to PHY (error: %d)\n", 3788 __func__, ret); 3789 goto init_phy_error; 3790 } 3791 } 3792 3793 /* Extra statistics */ 3794 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3795 priv->xstats.threshold = tc; 3796 3797 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3798 3799 buf_sz = dma_conf->dma_buf_sz; 3800 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3801 3802 stmmac_reset_queues_param(priv); 3803 3804 ret = stmmac_hw_setup(dev, true); 3805 if (ret < 0) { 3806 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3807 goto init_error; 3808 } 3809 3810 stmmac_init_coalesce(priv); 3811 3812 phylink_start(priv->phylink); 3813 /* We may have called phylink_speed_down before */ 3814 phylink_speed_up(priv->phylink); 3815 3816 ret = stmmac_request_irq(dev); 3817 if (ret) 3818 goto irq_error; 3819 3820 stmmac_enable_all_queues(priv); 3821 netif_tx_start_all_queues(priv->dev); 3822 stmmac_enable_all_dma_irq(priv); 3823 3824 return 0; 3825 3826 irq_error: 3827 phylink_stop(priv->phylink); 3828 3829 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3830 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3831 3832 stmmac_hw_teardown(dev); 3833 init_error: 3834 free_dma_desc_resources(priv, &priv->dma_conf); 3835 phylink_disconnect_phy(priv->phylink); 3836 init_phy_error: 3837 pm_runtime_put(priv->device); 3838 return ret; 3839 } 3840 3841 static int stmmac_open(struct net_device *dev) 3842 { 3843 struct stmmac_priv *priv = netdev_priv(dev); 3844 struct stmmac_dma_conf *dma_conf; 3845 int ret; 3846 3847 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3848 if (IS_ERR(dma_conf)) 3849 return PTR_ERR(dma_conf); 3850 3851 ret = __stmmac_open(dev, dma_conf); 3852 kfree(dma_conf); 3853 return ret; 3854 } 3855 3856 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3857 { 3858 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3859 3860 if (priv->fpe_wq) 3861 destroy_workqueue(priv->fpe_wq); 3862 3863 netdev_info(priv->dev, "FPE workqueue stop"); 3864 } 3865 3866 /** 3867 * stmmac_release - close entry point of the driver 3868 * @dev : device pointer. 3869 * Description: 3870 * This is the stop entry point of the driver. 3871 */ 3872 static int stmmac_release(struct net_device *dev) 3873 { 3874 struct stmmac_priv *priv = netdev_priv(dev); 3875 u32 chan; 3876 3877 if (device_may_wakeup(priv->device)) 3878 phylink_speed_down(priv->phylink, false); 3879 /* Stop and disconnect the PHY */ 3880 phylink_stop(priv->phylink); 3881 phylink_disconnect_phy(priv->phylink); 3882 3883 stmmac_disable_all_queues(priv); 3884 3885 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3886 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3887 3888 netif_tx_disable(dev); 3889 3890 /* Free the IRQ lines */ 3891 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3892 3893 if (priv->eee_enabled) { 3894 priv->tx_path_in_lpi_mode = false; 3895 del_timer_sync(&priv->eee_ctrl_timer); 3896 } 3897 3898 /* Stop TX/RX DMA and clear the descriptors */ 3899 stmmac_stop_all_dma(priv); 3900 3901 /* Release and free the Rx/Tx resources */ 3902 free_dma_desc_resources(priv, &priv->dma_conf); 3903 3904 /* Disable the MAC Rx/Tx */ 3905 stmmac_mac_set(priv, priv->ioaddr, false); 3906 3907 netif_carrier_off(dev); 3908 3909 stmmac_release_ptp(priv); 3910 3911 pm_runtime_put(priv->device); 3912 3913 if (priv->dma_cap.fpesel) 3914 stmmac_fpe_stop_wq(priv); 3915 3916 return 0; 3917 } 3918 3919 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3920 struct stmmac_tx_queue *tx_q) 3921 { 3922 u16 tag = 0x0, inner_tag = 0x0; 3923 u32 inner_type = 0x0; 3924 struct dma_desc *p; 3925 3926 if (!priv->dma_cap.vlins) 3927 return false; 3928 if (!skb_vlan_tag_present(skb)) 3929 return false; 3930 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3931 inner_tag = skb_vlan_tag_get(skb); 3932 inner_type = STMMAC_VLAN_INSERT; 3933 } 3934 3935 tag = skb_vlan_tag_get(skb); 3936 3937 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3938 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3939 else 3940 p = &tx_q->dma_tx[tx_q->cur_tx]; 3941 3942 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3943 return false; 3944 3945 stmmac_set_tx_owner(priv, p); 3946 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 3947 return true; 3948 } 3949 3950 /** 3951 * stmmac_tso_allocator - close entry point of the driver 3952 * @priv: driver private structure 3953 * @des: buffer start address 3954 * @total_len: total length to fill in descriptors 3955 * @last_segment: condition for the last descriptor 3956 * @queue: TX queue index 3957 * Description: 3958 * This function fills descriptor and request new descriptors according to 3959 * buffer length to fill 3960 */ 3961 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3962 int total_len, bool last_segment, u32 queue) 3963 { 3964 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3965 struct dma_desc *desc; 3966 u32 buff_size; 3967 int tmp_len; 3968 3969 tmp_len = total_len; 3970 3971 while (tmp_len > 0) { 3972 dma_addr_t curr_addr; 3973 3974 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3975 priv->dma_conf.dma_tx_size); 3976 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3977 3978 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3979 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3980 else 3981 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3982 3983 curr_addr = des + (total_len - tmp_len); 3984 if (priv->dma_cap.addr64 <= 32) 3985 desc->des0 = cpu_to_le32(curr_addr); 3986 else 3987 stmmac_set_desc_addr(priv, desc, curr_addr); 3988 3989 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3990 TSO_MAX_BUFF_SIZE : tmp_len; 3991 3992 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3993 0, 1, 3994 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3995 0, 0); 3996 3997 tmp_len -= TSO_MAX_BUFF_SIZE; 3998 } 3999 } 4000 4001 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4002 { 4003 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4004 int desc_size; 4005 4006 if (likely(priv->extend_desc)) 4007 desc_size = sizeof(struct dma_extended_desc); 4008 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4009 desc_size = sizeof(struct dma_edesc); 4010 else 4011 desc_size = sizeof(struct dma_desc); 4012 4013 /* The own bit must be the latest setting done when prepare the 4014 * descriptor and then barrier is needed to make sure that 4015 * all is coherent before granting the DMA engine. 4016 */ 4017 wmb(); 4018 4019 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4020 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4021 } 4022 4023 /** 4024 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4025 * @skb : the socket buffer 4026 * @dev : device pointer 4027 * Description: this is the transmit function that is called on TSO frames 4028 * (support available on GMAC4 and newer chips). 4029 * Diagram below show the ring programming in case of TSO frames: 4030 * 4031 * First Descriptor 4032 * -------- 4033 * | DES0 |---> buffer1 = L2/L3/L4 header 4034 * | DES1 |---> TCP Payload (can continue on next descr...) 4035 * | DES2 |---> buffer 1 and 2 len 4036 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4037 * -------- 4038 * | 4039 * ... 4040 * | 4041 * -------- 4042 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4043 * | DES1 | --| 4044 * | DES2 | --> buffer 1 and 2 len 4045 * | DES3 | 4046 * -------- 4047 * 4048 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4049 */ 4050 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4051 { 4052 struct dma_desc *desc, *first, *mss_desc = NULL; 4053 struct stmmac_priv *priv = netdev_priv(dev); 4054 int nfrags = skb_shinfo(skb)->nr_frags; 4055 u32 queue = skb_get_queue_mapping(skb); 4056 unsigned int first_entry, tx_packets; 4057 int tmp_pay_len = 0, first_tx; 4058 struct stmmac_tx_queue *tx_q; 4059 bool has_vlan, set_ic; 4060 u8 proto_hdr_len, hdr; 4061 u32 pay_len, mss; 4062 dma_addr_t des; 4063 int i; 4064 4065 tx_q = &priv->dma_conf.tx_queue[queue]; 4066 first_tx = tx_q->cur_tx; 4067 4068 /* Compute header lengths */ 4069 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4070 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4071 hdr = sizeof(struct udphdr); 4072 } else { 4073 proto_hdr_len = skb_tcp_all_headers(skb); 4074 hdr = tcp_hdrlen(skb); 4075 } 4076 4077 /* Desc availability based on threshold should be enough safe */ 4078 if (unlikely(stmmac_tx_avail(priv, queue) < 4079 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4080 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4081 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4082 queue)); 4083 /* This is a hard error, log it. */ 4084 netdev_err(priv->dev, 4085 "%s: Tx Ring full when queue awake\n", 4086 __func__); 4087 } 4088 return NETDEV_TX_BUSY; 4089 } 4090 4091 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4092 4093 mss = skb_shinfo(skb)->gso_size; 4094 4095 /* set new MSS value if needed */ 4096 if (mss != tx_q->mss) { 4097 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4098 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4099 else 4100 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4101 4102 stmmac_set_mss(priv, mss_desc, mss); 4103 tx_q->mss = mss; 4104 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4105 priv->dma_conf.dma_tx_size); 4106 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4107 } 4108 4109 if (netif_msg_tx_queued(priv)) { 4110 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4111 __func__, hdr, proto_hdr_len, pay_len, mss); 4112 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4113 skb->data_len); 4114 } 4115 4116 /* Check if VLAN can be inserted by HW */ 4117 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4118 4119 first_entry = tx_q->cur_tx; 4120 WARN_ON(tx_q->tx_skbuff[first_entry]); 4121 4122 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4123 desc = &tx_q->dma_entx[first_entry].basic; 4124 else 4125 desc = &tx_q->dma_tx[first_entry]; 4126 first = desc; 4127 4128 if (has_vlan) 4129 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4130 4131 /* first descriptor: fill Headers on Buf1 */ 4132 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4133 DMA_TO_DEVICE); 4134 if (dma_mapping_error(priv->device, des)) 4135 goto dma_map_err; 4136 4137 tx_q->tx_skbuff_dma[first_entry].buf = des; 4138 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4139 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4140 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4141 4142 if (priv->dma_cap.addr64 <= 32) { 4143 first->des0 = cpu_to_le32(des); 4144 4145 /* Fill start of payload in buff2 of first descriptor */ 4146 if (pay_len) 4147 first->des1 = cpu_to_le32(des + proto_hdr_len); 4148 4149 /* If needed take extra descriptors to fill the remaining payload */ 4150 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4151 } else { 4152 stmmac_set_desc_addr(priv, first, des); 4153 tmp_pay_len = pay_len; 4154 des += proto_hdr_len; 4155 pay_len = 0; 4156 } 4157 4158 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4159 4160 /* Prepare fragments */ 4161 for (i = 0; i < nfrags; i++) { 4162 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4163 4164 des = skb_frag_dma_map(priv->device, frag, 0, 4165 skb_frag_size(frag), 4166 DMA_TO_DEVICE); 4167 if (dma_mapping_error(priv->device, des)) 4168 goto dma_map_err; 4169 4170 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4171 (i == nfrags - 1), queue); 4172 4173 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4174 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4175 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4176 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4177 } 4178 4179 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4180 4181 /* Only the last descriptor gets to point to the skb. */ 4182 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4183 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4184 4185 /* Manage tx mitigation */ 4186 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4187 tx_q->tx_count_frames += tx_packets; 4188 4189 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4190 set_ic = true; 4191 else if (!priv->tx_coal_frames[queue]) 4192 set_ic = false; 4193 else if (tx_packets > priv->tx_coal_frames[queue]) 4194 set_ic = true; 4195 else if ((tx_q->tx_count_frames % 4196 priv->tx_coal_frames[queue]) < tx_packets) 4197 set_ic = true; 4198 else 4199 set_ic = false; 4200 4201 if (set_ic) { 4202 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4203 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4204 else 4205 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4206 4207 tx_q->tx_count_frames = 0; 4208 stmmac_set_tx_ic(priv, desc); 4209 priv->xstats.tx_set_ic_bit++; 4210 } 4211 4212 /* We've used all descriptors we need for this skb, however, 4213 * advance cur_tx so that it references a fresh descriptor. 4214 * ndo_start_xmit will fill this descriptor the next time it's 4215 * called and stmmac_tx_clean may clean up to this descriptor. 4216 */ 4217 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4218 4219 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4220 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4221 __func__); 4222 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4223 } 4224 4225 dev->stats.tx_bytes += skb->len; 4226 priv->xstats.tx_tso_frames++; 4227 priv->xstats.tx_tso_nfrags += nfrags; 4228 4229 if (priv->sarc_type) 4230 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4231 4232 skb_tx_timestamp(skb); 4233 4234 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4235 priv->hwts_tx_en)) { 4236 /* declare that device is doing timestamping */ 4237 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4238 stmmac_enable_tx_timestamp(priv, first); 4239 } 4240 4241 /* Complete the first descriptor before granting the DMA */ 4242 stmmac_prepare_tso_tx_desc(priv, first, 1, 4243 proto_hdr_len, 4244 pay_len, 4245 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4246 hdr / 4, (skb->len - proto_hdr_len)); 4247 4248 /* If context desc is used to change MSS */ 4249 if (mss_desc) { 4250 /* Make sure that first descriptor has been completely 4251 * written, including its own bit. This is because MSS is 4252 * actually before first descriptor, so we need to make 4253 * sure that MSS's own bit is the last thing written. 4254 */ 4255 dma_wmb(); 4256 stmmac_set_tx_owner(priv, mss_desc); 4257 } 4258 4259 if (netif_msg_pktdata(priv)) { 4260 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4261 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4262 tx_q->cur_tx, first, nfrags); 4263 pr_info(">>> frame to be transmitted: "); 4264 print_pkt(skb->data, skb_headlen(skb)); 4265 } 4266 4267 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4268 4269 stmmac_flush_tx_descriptors(priv, queue); 4270 stmmac_tx_timer_arm(priv, queue); 4271 4272 return NETDEV_TX_OK; 4273 4274 dma_map_err: 4275 dev_err(priv->device, "Tx dma map failed\n"); 4276 dev_kfree_skb(skb); 4277 priv->dev->stats.tx_dropped++; 4278 return NETDEV_TX_OK; 4279 } 4280 4281 /** 4282 * stmmac_xmit - Tx entry point of the driver 4283 * @skb : the socket buffer 4284 * @dev : device pointer 4285 * Description : this is the tx entry point of the driver. 4286 * It programs the chain or the ring and supports oversized frames 4287 * and SG feature. 4288 */ 4289 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4290 { 4291 unsigned int first_entry, tx_packets, enh_desc; 4292 struct stmmac_priv *priv = netdev_priv(dev); 4293 unsigned int nopaged_len = skb_headlen(skb); 4294 int i, csum_insertion = 0, is_jumbo = 0; 4295 u32 queue = skb_get_queue_mapping(skb); 4296 int nfrags = skb_shinfo(skb)->nr_frags; 4297 int gso = skb_shinfo(skb)->gso_type; 4298 struct dma_edesc *tbs_desc = NULL; 4299 struct dma_desc *desc, *first; 4300 struct stmmac_tx_queue *tx_q; 4301 bool has_vlan, set_ic; 4302 int entry, first_tx; 4303 dma_addr_t des; 4304 4305 tx_q = &priv->dma_conf.tx_queue[queue]; 4306 first_tx = tx_q->cur_tx; 4307 4308 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4309 stmmac_disable_eee_mode(priv); 4310 4311 /* Manage oversized TCP frames for GMAC4 device */ 4312 if (skb_is_gso(skb) && priv->tso) { 4313 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4314 return stmmac_tso_xmit(skb, dev); 4315 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4316 return stmmac_tso_xmit(skb, dev); 4317 } 4318 4319 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4320 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4321 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4322 queue)); 4323 /* This is a hard error, log it. */ 4324 netdev_err(priv->dev, 4325 "%s: Tx Ring full when queue awake\n", 4326 __func__); 4327 } 4328 return NETDEV_TX_BUSY; 4329 } 4330 4331 /* Check if VLAN can be inserted by HW */ 4332 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4333 4334 entry = tx_q->cur_tx; 4335 first_entry = entry; 4336 WARN_ON(tx_q->tx_skbuff[first_entry]); 4337 4338 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4339 4340 if (likely(priv->extend_desc)) 4341 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4342 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4343 desc = &tx_q->dma_entx[entry].basic; 4344 else 4345 desc = tx_q->dma_tx + entry; 4346 4347 first = desc; 4348 4349 if (has_vlan) 4350 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4351 4352 enh_desc = priv->plat->enh_desc; 4353 /* To program the descriptors according to the size of the frame */ 4354 if (enh_desc) 4355 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4356 4357 if (unlikely(is_jumbo)) { 4358 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4359 if (unlikely(entry < 0) && (entry != -EINVAL)) 4360 goto dma_map_err; 4361 } 4362 4363 for (i = 0; i < nfrags; i++) { 4364 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4365 int len = skb_frag_size(frag); 4366 bool last_segment = (i == (nfrags - 1)); 4367 4368 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4369 WARN_ON(tx_q->tx_skbuff[entry]); 4370 4371 if (likely(priv->extend_desc)) 4372 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4373 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4374 desc = &tx_q->dma_entx[entry].basic; 4375 else 4376 desc = tx_q->dma_tx + entry; 4377 4378 des = skb_frag_dma_map(priv->device, frag, 0, len, 4379 DMA_TO_DEVICE); 4380 if (dma_mapping_error(priv->device, des)) 4381 goto dma_map_err; /* should reuse desc w/o issues */ 4382 4383 tx_q->tx_skbuff_dma[entry].buf = des; 4384 4385 stmmac_set_desc_addr(priv, desc, des); 4386 4387 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4388 tx_q->tx_skbuff_dma[entry].len = len; 4389 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4390 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4391 4392 /* Prepare the descriptor and set the own bit too */ 4393 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4394 priv->mode, 1, last_segment, skb->len); 4395 } 4396 4397 /* Only the last descriptor gets to point to the skb. */ 4398 tx_q->tx_skbuff[entry] = skb; 4399 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4400 4401 /* According to the coalesce parameter the IC bit for the latest 4402 * segment is reset and the timer re-started to clean the tx status. 4403 * This approach takes care about the fragments: desc is the first 4404 * element in case of no SG. 4405 */ 4406 tx_packets = (entry + 1) - first_tx; 4407 tx_q->tx_count_frames += tx_packets; 4408 4409 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4410 set_ic = true; 4411 else if (!priv->tx_coal_frames[queue]) 4412 set_ic = false; 4413 else if (tx_packets > priv->tx_coal_frames[queue]) 4414 set_ic = true; 4415 else if ((tx_q->tx_count_frames % 4416 priv->tx_coal_frames[queue]) < tx_packets) 4417 set_ic = true; 4418 else 4419 set_ic = false; 4420 4421 if (set_ic) { 4422 if (likely(priv->extend_desc)) 4423 desc = &tx_q->dma_etx[entry].basic; 4424 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4425 desc = &tx_q->dma_entx[entry].basic; 4426 else 4427 desc = &tx_q->dma_tx[entry]; 4428 4429 tx_q->tx_count_frames = 0; 4430 stmmac_set_tx_ic(priv, desc); 4431 priv->xstats.tx_set_ic_bit++; 4432 } 4433 4434 /* We've used all descriptors we need for this skb, however, 4435 * advance cur_tx so that it references a fresh descriptor. 4436 * ndo_start_xmit will fill this descriptor the next time it's 4437 * called and stmmac_tx_clean may clean up to this descriptor. 4438 */ 4439 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4440 tx_q->cur_tx = entry; 4441 4442 if (netif_msg_pktdata(priv)) { 4443 netdev_dbg(priv->dev, 4444 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4445 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4446 entry, first, nfrags); 4447 4448 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4449 print_pkt(skb->data, skb->len); 4450 } 4451 4452 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4453 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4454 __func__); 4455 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4456 } 4457 4458 dev->stats.tx_bytes += skb->len; 4459 4460 if (priv->sarc_type) 4461 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4462 4463 skb_tx_timestamp(skb); 4464 4465 /* Ready to fill the first descriptor and set the OWN bit w/o any 4466 * problems because all the descriptors are actually ready to be 4467 * passed to the DMA engine. 4468 */ 4469 if (likely(!is_jumbo)) { 4470 bool last_segment = (nfrags == 0); 4471 4472 des = dma_map_single(priv->device, skb->data, 4473 nopaged_len, DMA_TO_DEVICE); 4474 if (dma_mapping_error(priv->device, des)) 4475 goto dma_map_err; 4476 4477 tx_q->tx_skbuff_dma[first_entry].buf = des; 4478 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4479 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4480 4481 stmmac_set_desc_addr(priv, first, des); 4482 4483 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4484 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4485 4486 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4487 priv->hwts_tx_en)) { 4488 /* declare that device is doing timestamping */ 4489 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4490 stmmac_enable_tx_timestamp(priv, first); 4491 } 4492 4493 /* Prepare the first descriptor setting the OWN bit too */ 4494 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4495 csum_insertion, priv->mode, 0, last_segment, 4496 skb->len); 4497 } 4498 4499 if (tx_q->tbs & STMMAC_TBS_EN) { 4500 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4501 4502 tbs_desc = &tx_q->dma_entx[first_entry]; 4503 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4504 } 4505 4506 stmmac_set_tx_owner(priv, first); 4507 4508 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4509 4510 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4511 4512 stmmac_flush_tx_descriptors(priv, queue); 4513 stmmac_tx_timer_arm(priv, queue); 4514 4515 return NETDEV_TX_OK; 4516 4517 dma_map_err: 4518 netdev_err(priv->dev, "Tx DMA map failed\n"); 4519 dev_kfree_skb(skb); 4520 priv->dev->stats.tx_dropped++; 4521 return NETDEV_TX_OK; 4522 } 4523 4524 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4525 { 4526 struct vlan_ethhdr *veth; 4527 __be16 vlan_proto; 4528 u16 vlanid; 4529 4530 veth = (struct vlan_ethhdr *)skb->data; 4531 vlan_proto = veth->h_vlan_proto; 4532 4533 if ((vlan_proto == htons(ETH_P_8021Q) && 4534 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4535 (vlan_proto == htons(ETH_P_8021AD) && 4536 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4537 /* pop the vlan tag */ 4538 vlanid = ntohs(veth->h_vlan_TCI); 4539 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4540 skb_pull(skb, VLAN_HLEN); 4541 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4542 } 4543 } 4544 4545 /** 4546 * stmmac_rx_refill - refill used skb preallocated buffers 4547 * @priv: driver private structure 4548 * @queue: RX queue index 4549 * Description : this is to reallocate the skb for the reception process 4550 * that is based on zero-copy. 4551 */ 4552 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4553 { 4554 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4555 int dirty = stmmac_rx_dirty(priv, queue); 4556 unsigned int entry = rx_q->dirty_rx; 4557 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4558 4559 if (priv->dma_cap.addr64 <= 32) 4560 gfp |= GFP_DMA32; 4561 4562 while (dirty-- > 0) { 4563 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4564 struct dma_desc *p; 4565 bool use_rx_wd; 4566 4567 if (priv->extend_desc) 4568 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4569 else 4570 p = rx_q->dma_rx + entry; 4571 4572 if (!buf->page) { 4573 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4574 if (!buf->page) 4575 break; 4576 } 4577 4578 if (priv->sph && !buf->sec_page) { 4579 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4580 if (!buf->sec_page) 4581 break; 4582 4583 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4584 } 4585 4586 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4587 4588 stmmac_set_desc_addr(priv, p, buf->addr); 4589 if (priv->sph) 4590 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4591 else 4592 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4593 stmmac_refill_desc3(priv, rx_q, p); 4594 4595 rx_q->rx_count_frames++; 4596 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4597 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4598 rx_q->rx_count_frames = 0; 4599 4600 use_rx_wd = !priv->rx_coal_frames[queue]; 4601 use_rx_wd |= rx_q->rx_count_frames > 0; 4602 if (!priv->use_riwt) 4603 use_rx_wd = false; 4604 4605 dma_wmb(); 4606 stmmac_set_rx_owner(priv, p, use_rx_wd); 4607 4608 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4609 } 4610 rx_q->dirty_rx = entry; 4611 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4612 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4613 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4614 } 4615 4616 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4617 struct dma_desc *p, 4618 int status, unsigned int len) 4619 { 4620 unsigned int plen = 0, hlen = 0; 4621 int coe = priv->hw->rx_csum; 4622 4623 /* Not first descriptor, buffer is always zero */ 4624 if (priv->sph && len) 4625 return 0; 4626 4627 /* First descriptor, get split header length */ 4628 stmmac_get_rx_header_len(priv, p, &hlen); 4629 if (priv->sph && hlen) { 4630 priv->xstats.rx_split_hdr_pkt_n++; 4631 return hlen; 4632 } 4633 4634 /* First descriptor, not last descriptor and not split header */ 4635 if (status & rx_not_ls) 4636 return priv->dma_conf.dma_buf_sz; 4637 4638 plen = stmmac_get_rx_frame_len(priv, p, coe); 4639 4640 /* First descriptor and last descriptor and not split header */ 4641 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4642 } 4643 4644 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4645 struct dma_desc *p, 4646 int status, unsigned int len) 4647 { 4648 int coe = priv->hw->rx_csum; 4649 unsigned int plen = 0; 4650 4651 /* Not split header, buffer is not available */ 4652 if (!priv->sph) 4653 return 0; 4654 4655 /* Not last descriptor */ 4656 if (status & rx_not_ls) 4657 return priv->dma_conf.dma_buf_sz; 4658 4659 plen = stmmac_get_rx_frame_len(priv, p, coe); 4660 4661 /* Last descriptor */ 4662 return plen - len; 4663 } 4664 4665 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4666 struct xdp_frame *xdpf, bool dma_map) 4667 { 4668 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4669 unsigned int entry = tx_q->cur_tx; 4670 struct dma_desc *tx_desc; 4671 dma_addr_t dma_addr; 4672 bool set_ic; 4673 4674 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4675 return STMMAC_XDP_CONSUMED; 4676 4677 if (likely(priv->extend_desc)) 4678 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4679 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4680 tx_desc = &tx_q->dma_entx[entry].basic; 4681 else 4682 tx_desc = tx_q->dma_tx + entry; 4683 4684 if (dma_map) { 4685 dma_addr = dma_map_single(priv->device, xdpf->data, 4686 xdpf->len, DMA_TO_DEVICE); 4687 if (dma_mapping_error(priv->device, dma_addr)) 4688 return STMMAC_XDP_CONSUMED; 4689 4690 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4691 } else { 4692 struct page *page = virt_to_page(xdpf->data); 4693 4694 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4695 xdpf->headroom; 4696 dma_sync_single_for_device(priv->device, dma_addr, 4697 xdpf->len, DMA_BIDIRECTIONAL); 4698 4699 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4700 } 4701 4702 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4703 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4704 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4705 tx_q->tx_skbuff_dma[entry].last_segment = true; 4706 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4707 4708 tx_q->xdpf[entry] = xdpf; 4709 4710 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4711 4712 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4713 true, priv->mode, true, true, 4714 xdpf->len); 4715 4716 tx_q->tx_count_frames++; 4717 4718 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4719 set_ic = true; 4720 else 4721 set_ic = false; 4722 4723 if (set_ic) { 4724 tx_q->tx_count_frames = 0; 4725 stmmac_set_tx_ic(priv, tx_desc); 4726 priv->xstats.tx_set_ic_bit++; 4727 } 4728 4729 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4730 4731 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4732 tx_q->cur_tx = entry; 4733 4734 return STMMAC_XDP_TX; 4735 } 4736 4737 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4738 int cpu) 4739 { 4740 int index = cpu; 4741 4742 if (unlikely(index < 0)) 4743 index = 0; 4744 4745 while (index >= priv->plat->tx_queues_to_use) 4746 index -= priv->plat->tx_queues_to_use; 4747 4748 return index; 4749 } 4750 4751 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4752 struct xdp_buff *xdp) 4753 { 4754 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4755 int cpu = smp_processor_id(); 4756 struct netdev_queue *nq; 4757 int queue; 4758 int res; 4759 4760 if (unlikely(!xdpf)) 4761 return STMMAC_XDP_CONSUMED; 4762 4763 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4764 nq = netdev_get_tx_queue(priv->dev, queue); 4765 4766 __netif_tx_lock(nq, cpu); 4767 /* Avoids TX time-out as we are sharing with slow path */ 4768 txq_trans_cond_update(nq); 4769 4770 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4771 if (res == STMMAC_XDP_TX) 4772 stmmac_flush_tx_descriptors(priv, queue); 4773 4774 __netif_tx_unlock(nq); 4775 4776 return res; 4777 } 4778 4779 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4780 struct bpf_prog *prog, 4781 struct xdp_buff *xdp) 4782 { 4783 u32 act; 4784 int res; 4785 4786 act = bpf_prog_run_xdp(prog, xdp); 4787 switch (act) { 4788 case XDP_PASS: 4789 res = STMMAC_XDP_PASS; 4790 break; 4791 case XDP_TX: 4792 res = stmmac_xdp_xmit_back(priv, xdp); 4793 break; 4794 case XDP_REDIRECT: 4795 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4796 res = STMMAC_XDP_CONSUMED; 4797 else 4798 res = STMMAC_XDP_REDIRECT; 4799 break; 4800 default: 4801 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4802 fallthrough; 4803 case XDP_ABORTED: 4804 trace_xdp_exception(priv->dev, prog, act); 4805 fallthrough; 4806 case XDP_DROP: 4807 res = STMMAC_XDP_CONSUMED; 4808 break; 4809 } 4810 4811 return res; 4812 } 4813 4814 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4815 struct xdp_buff *xdp) 4816 { 4817 struct bpf_prog *prog; 4818 int res; 4819 4820 prog = READ_ONCE(priv->xdp_prog); 4821 if (!prog) { 4822 res = STMMAC_XDP_PASS; 4823 goto out; 4824 } 4825 4826 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4827 out: 4828 return ERR_PTR(-res); 4829 } 4830 4831 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4832 int xdp_status) 4833 { 4834 int cpu = smp_processor_id(); 4835 int queue; 4836 4837 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4838 4839 if (xdp_status & STMMAC_XDP_TX) 4840 stmmac_tx_timer_arm(priv, queue); 4841 4842 if (xdp_status & STMMAC_XDP_REDIRECT) 4843 xdp_do_flush(); 4844 } 4845 4846 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4847 struct xdp_buff *xdp) 4848 { 4849 unsigned int metasize = xdp->data - xdp->data_meta; 4850 unsigned int datasize = xdp->data_end - xdp->data; 4851 struct sk_buff *skb; 4852 4853 skb = __napi_alloc_skb(&ch->rxtx_napi, 4854 xdp->data_end - xdp->data_hard_start, 4855 GFP_ATOMIC | __GFP_NOWARN); 4856 if (unlikely(!skb)) 4857 return NULL; 4858 4859 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4860 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4861 if (metasize) 4862 skb_metadata_set(skb, metasize); 4863 4864 return skb; 4865 } 4866 4867 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4868 struct dma_desc *p, struct dma_desc *np, 4869 struct xdp_buff *xdp) 4870 { 4871 struct stmmac_channel *ch = &priv->channel[queue]; 4872 unsigned int len = xdp->data_end - xdp->data; 4873 enum pkt_hash_types hash_type; 4874 int coe = priv->hw->rx_csum; 4875 struct sk_buff *skb; 4876 u32 hash; 4877 4878 skb = stmmac_construct_skb_zc(ch, xdp); 4879 if (!skb) { 4880 priv->dev->stats.rx_dropped++; 4881 return; 4882 } 4883 4884 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4885 stmmac_rx_vlan(priv->dev, skb); 4886 skb->protocol = eth_type_trans(skb, priv->dev); 4887 4888 if (unlikely(!coe)) 4889 skb_checksum_none_assert(skb); 4890 else 4891 skb->ip_summed = CHECKSUM_UNNECESSARY; 4892 4893 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4894 skb_set_hash(skb, hash, hash_type); 4895 4896 skb_record_rx_queue(skb, queue); 4897 napi_gro_receive(&ch->rxtx_napi, skb); 4898 4899 priv->dev->stats.rx_packets++; 4900 priv->dev->stats.rx_bytes += len; 4901 } 4902 4903 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4904 { 4905 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4906 unsigned int entry = rx_q->dirty_rx; 4907 struct dma_desc *rx_desc = NULL; 4908 bool ret = true; 4909 4910 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4911 4912 while (budget-- > 0 && entry != rx_q->cur_rx) { 4913 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4914 dma_addr_t dma_addr; 4915 bool use_rx_wd; 4916 4917 if (!buf->xdp) { 4918 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4919 if (!buf->xdp) { 4920 ret = false; 4921 break; 4922 } 4923 } 4924 4925 if (priv->extend_desc) 4926 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4927 else 4928 rx_desc = rx_q->dma_rx + entry; 4929 4930 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4931 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4932 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4933 stmmac_refill_desc3(priv, rx_q, rx_desc); 4934 4935 rx_q->rx_count_frames++; 4936 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4937 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4938 rx_q->rx_count_frames = 0; 4939 4940 use_rx_wd = !priv->rx_coal_frames[queue]; 4941 use_rx_wd |= rx_q->rx_count_frames > 0; 4942 if (!priv->use_riwt) 4943 use_rx_wd = false; 4944 4945 dma_wmb(); 4946 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4947 4948 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4949 } 4950 4951 if (rx_desc) { 4952 rx_q->dirty_rx = entry; 4953 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4954 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4955 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4956 } 4957 4958 return ret; 4959 } 4960 4961 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4962 { 4963 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4964 unsigned int count = 0, error = 0, len = 0; 4965 int dirty = stmmac_rx_dirty(priv, queue); 4966 unsigned int next_entry = rx_q->cur_rx; 4967 unsigned int desc_size; 4968 struct bpf_prog *prog; 4969 bool failure = false; 4970 int xdp_status = 0; 4971 int status = 0; 4972 4973 if (netif_msg_rx_status(priv)) { 4974 void *rx_head; 4975 4976 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4977 if (priv->extend_desc) { 4978 rx_head = (void *)rx_q->dma_erx; 4979 desc_size = sizeof(struct dma_extended_desc); 4980 } else { 4981 rx_head = (void *)rx_q->dma_rx; 4982 desc_size = sizeof(struct dma_desc); 4983 } 4984 4985 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 4986 rx_q->dma_rx_phy, desc_size); 4987 } 4988 while (count < limit) { 4989 struct stmmac_rx_buffer *buf; 4990 unsigned int buf1_len = 0; 4991 struct dma_desc *np, *p; 4992 int entry; 4993 int res; 4994 4995 if (!count && rx_q->state_saved) { 4996 error = rx_q->state.error; 4997 len = rx_q->state.len; 4998 } else { 4999 rx_q->state_saved = false; 5000 error = 0; 5001 len = 0; 5002 } 5003 5004 if (count >= limit) 5005 break; 5006 5007 read_again: 5008 buf1_len = 0; 5009 entry = next_entry; 5010 buf = &rx_q->buf_pool[entry]; 5011 5012 if (dirty >= STMMAC_RX_FILL_BATCH) { 5013 failure = failure || 5014 !stmmac_rx_refill_zc(priv, queue, dirty); 5015 dirty = 0; 5016 } 5017 5018 if (priv->extend_desc) 5019 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5020 else 5021 p = rx_q->dma_rx + entry; 5022 5023 /* read the status of the incoming frame */ 5024 status = stmmac_rx_status(priv, &priv->dev->stats, 5025 &priv->xstats, p); 5026 /* check if managed by the DMA otherwise go ahead */ 5027 if (unlikely(status & dma_own)) 5028 break; 5029 5030 /* Prefetch the next RX descriptor */ 5031 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5032 priv->dma_conf.dma_rx_size); 5033 next_entry = rx_q->cur_rx; 5034 5035 if (priv->extend_desc) 5036 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5037 else 5038 np = rx_q->dma_rx + next_entry; 5039 5040 prefetch(np); 5041 5042 /* Ensure a valid XSK buffer before proceed */ 5043 if (!buf->xdp) 5044 break; 5045 5046 if (priv->extend_desc) 5047 stmmac_rx_extended_status(priv, &priv->dev->stats, 5048 &priv->xstats, 5049 rx_q->dma_erx + entry); 5050 if (unlikely(status == discard_frame)) { 5051 xsk_buff_free(buf->xdp); 5052 buf->xdp = NULL; 5053 dirty++; 5054 error = 1; 5055 if (!priv->hwts_rx_en) 5056 priv->dev->stats.rx_errors++; 5057 } 5058 5059 if (unlikely(error && (status & rx_not_ls))) 5060 goto read_again; 5061 if (unlikely(error)) { 5062 count++; 5063 continue; 5064 } 5065 5066 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5067 if (likely(status & rx_not_ls)) { 5068 xsk_buff_free(buf->xdp); 5069 buf->xdp = NULL; 5070 dirty++; 5071 count++; 5072 goto read_again; 5073 } 5074 5075 /* XDP ZC Frame only support primary buffers for now */ 5076 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5077 len += buf1_len; 5078 5079 /* ACS is disabled; strip manually. */ 5080 if (likely(!(status & rx_not_ls))) { 5081 buf1_len -= ETH_FCS_LEN; 5082 len -= ETH_FCS_LEN; 5083 } 5084 5085 /* RX buffer is good and fit into a XSK pool buffer */ 5086 buf->xdp->data_end = buf->xdp->data + buf1_len; 5087 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5088 5089 prog = READ_ONCE(priv->xdp_prog); 5090 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5091 5092 switch (res) { 5093 case STMMAC_XDP_PASS: 5094 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5095 xsk_buff_free(buf->xdp); 5096 break; 5097 case STMMAC_XDP_CONSUMED: 5098 xsk_buff_free(buf->xdp); 5099 priv->dev->stats.rx_dropped++; 5100 break; 5101 case STMMAC_XDP_TX: 5102 case STMMAC_XDP_REDIRECT: 5103 xdp_status |= res; 5104 break; 5105 } 5106 5107 buf->xdp = NULL; 5108 dirty++; 5109 count++; 5110 } 5111 5112 if (status & rx_not_ls) { 5113 rx_q->state_saved = true; 5114 rx_q->state.error = error; 5115 rx_q->state.len = len; 5116 } 5117 5118 stmmac_finalize_xdp_rx(priv, xdp_status); 5119 5120 priv->xstats.rx_pkt_n += count; 5121 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5122 5123 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5124 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5125 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5126 else 5127 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5128 5129 return (int)count; 5130 } 5131 5132 return failure ? limit : (int)count; 5133 } 5134 5135 /** 5136 * stmmac_rx - manage the receive process 5137 * @priv: driver private structure 5138 * @limit: napi bugget 5139 * @queue: RX queue index. 5140 * Description : this the function called by the napi poll method. 5141 * It gets all the frames inside the ring. 5142 */ 5143 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5144 { 5145 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5146 struct stmmac_channel *ch = &priv->channel[queue]; 5147 unsigned int count = 0, error = 0, len = 0; 5148 int status = 0, coe = priv->hw->rx_csum; 5149 unsigned int next_entry = rx_q->cur_rx; 5150 enum dma_data_direction dma_dir; 5151 unsigned int desc_size; 5152 struct sk_buff *skb = NULL; 5153 struct xdp_buff xdp; 5154 int xdp_status = 0; 5155 int buf_sz; 5156 5157 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5158 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5159 5160 if (netif_msg_rx_status(priv)) { 5161 void *rx_head; 5162 5163 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5164 if (priv->extend_desc) { 5165 rx_head = (void *)rx_q->dma_erx; 5166 desc_size = sizeof(struct dma_extended_desc); 5167 } else { 5168 rx_head = (void *)rx_q->dma_rx; 5169 desc_size = sizeof(struct dma_desc); 5170 } 5171 5172 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5173 rx_q->dma_rx_phy, desc_size); 5174 } 5175 while (count < limit) { 5176 unsigned int buf1_len = 0, buf2_len = 0; 5177 enum pkt_hash_types hash_type; 5178 struct stmmac_rx_buffer *buf; 5179 struct dma_desc *np, *p; 5180 int entry; 5181 u32 hash; 5182 5183 if (!count && rx_q->state_saved) { 5184 skb = rx_q->state.skb; 5185 error = rx_q->state.error; 5186 len = rx_q->state.len; 5187 } else { 5188 rx_q->state_saved = false; 5189 skb = NULL; 5190 error = 0; 5191 len = 0; 5192 } 5193 5194 if (count >= limit) 5195 break; 5196 5197 read_again: 5198 buf1_len = 0; 5199 buf2_len = 0; 5200 entry = next_entry; 5201 buf = &rx_q->buf_pool[entry]; 5202 5203 if (priv->extend_desc) 5204 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5205 else 5206 p = rx_q->dma_rx + entry; 5207 5208 /* read the status of the incoming frame */ 5209 status = stmmac_rx_status(priv, &priv->dev->stats, 5210 &priv->xstats, p); 5211 /* check if managed by the DMA otherwise go ahead */ 5212 if (unlikely(status & dma_own)) 5213 break; 5214 5215 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5216 priv->dma_conf.dma_rx_size); 5217 next_entry = rx_q->cur_rx; 5218 5219 if (priv->extend_desc) 5220 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5221 else 5222 np = rx_q->dma_rx + next_entry; 5223 5224 prefetch(np); 5225 5226 if (priv->extend_desc) 5227 stmmac_rx_extended_status(priv, &priv->dev->stats, 5228 &priv->xstats, rx_q->dma_erx + entry); 5229 if (unlikely(status == discard_frame)) { 5230 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5231 buf->page = NULL; 5232 error = 1; 5233 if (!priv->hwts_rx_en) 5234 priv->dev->stats.rx_errors++; 5235 } 5236 5237 if (unlikely(error && (status & rx_not_ls))) 5238 goto read_again; 5239 if (unlikely(error)) { 5240 dev_kfree_skb(skb); 5241 skb = NULL; 5242 count++; 5243 continue; 5244 } 5245 5246 /* Buffer is good. Go on. */ 5247 5248 prefetch(page_address(buf->page) + buf->page_offset); 5249 if (buf->sec_page) 5250 prefetch(page_address(buf->sec_page)); 5251 5252 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5253 len += buf1_len; 5254 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5255 len += buf2_len; 5256 5257 /* ACS is disabled; strip manually. */ 5258 if (likely(!(status & rx_not_ls))) { 5259 if (buf2_len) { 5260 buf2_len -= ETH_FCS_LEN; 5261 len -= ETH_FCS_LEN; 5262 } else if (buf1_len) { 5263 buf1_len -= ETH_FCS_LEN; 5264 len -= ETH_FCS_LEN; 5265 } 5266 } 5267 5268 if (!skb) { 5269 unsigned int pre_len, sync_len; 5270 5271 dma_sync_single_for_cpu(priv->device, buf->addr, 5272 buf1_len, dma_dir); 5273 5274 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5275 xdp_prepare_buff(&xdp, page_address(buf->page), 5276 buf->page_offset, buf1_len, false); 5277 5278 pre_len = xdp.data_end - xdp.data_hard_start - 5279 buf->page_offset; 5280 skb = stmmac_xdp_run_prog(priv, &xdp); 5281 /* Due xdp_adjust_tail: DMA sync for_device 5282 * cover max len CPU touch 5283 */ 5284 sync_len = xdp.data_end - xdp.data_hard_start - 5285 buf->page_offset; 5286 sync_len = max(sync_len, pre_len); 5287 5288 /* For Not XDP_PASS verdict */ 5289 if (IS_ERR(skb)) { 5290 unsigned int xdp_res = -PTR_ERR(skb); 5291 5292 if (xdp_res & STMMAC_XDP_CONSUMED) { 5293 page_pool_put_page(rx_q->page_pool, 5294 virt_to_head_page(xdp.data), 5295 sync_len, true); 5296 buf->page = NULL; 5297 priv->dev->stats.rx_dropped++; 5298 5299 /* Clear skb as it was set as 5300 * status by XDP program. 5301 */ 5302 skb = NULL; 5303 5304 if (unlikely((status & rx_not_ls))) 5305 goto read_again; 5306 5307 count++; 5308 continue; 5309 } else if (xdp_res & (STMMAC_XDP_TX | 5310 STMMAC_XDP_REDIRECT)) { 5311 xdp_status |= xdp_res; 5312 buf->page = NULL; 5313 skb = NULL; 5314 count++; 5315 continue; 5316 } 5317 } 5318 } 5319 5320 if (!skb) { 5321 /* XDP program may expand or reduce tail */ 5322 buf1_len = xdp.data_end - xdp.data; 5323 5324 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5325 if (!skb) { 5326 priv->dev->stats.rx_dropped++; 5327 count++; 5328 goto drain_data; 5329 } 5330 5331 /* XDP program may adjust header */ 5332 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5333 skb_put(skb, buf1_len); 5334 5335 /* Data payload copied into SKB, page ready for recycle */ 5336 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5337 buf->page = NULL; 5338 } else if (buf1_len) { 5339 dma_sync_single_for_cpu(priv->device, buf->addr, 5340 buf1_len, dma_dir); 5341 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5342 buf->page, buf->page_offset, buf1_len, 5343 priv->dma_conf.dma_buf_sz); 5344 5345 /* Data payload appended into SKB */ 5346 page_pool_release_page(rx_q->page_pool, buf->page); 5347 buf->page = NULL; 5348 } 5349 5350 if (buf2_len) { 5351 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5352 buf2_len, dma_dir); 5353 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5354 buf->sec_page, 0, buf2_len, 5355 priv->dma_conf.dma_buf_sz); 5356 5357 /* Data payload appended into SKB */ 5358 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5359 buf->sec_page = NULL; 5360 } 5361 5362 drain_data: 5363 if (likely(status & rx_not_ls)) 5364 goto read_again; 5365 if (!skb) 5366 continue; 5367 5368 /* Got entire packet into SKB. Finish it. */ 5369 5370 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5371 stmmac_rx_vlan(priv->dev, skb); 5372 skb->protocol = eth_type_trans(skb, priv->dev); 5373 5374 if (unlikely(!coe)) 5375 skb_checksum_none_assert(skb); 5376 else 5377 skb->ip_summed = CHECKSUM_UNNECESSARY; 5378 5379 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5380 skb_set_hash(skb, hash, hash_type); 5381 5382 skb_record_rx_queue(skb, queue); 5383 napi_gro_receive(&ch->rx_napi, skb); 5384 skb = NULL; 5385 5386 priv->dev->stats.rx_packets++; 5387 priv->dev->stats.rx_bytes += len; 5388 count++; 5389 } 5390 5391 if (status & rx_not_ls || skb) { 5392 rx_q->state_saved = true; 5393 rx_q->state.skb = skb; 5394 rx_q->state.error = error; 5395 rx_q->state.len = len; 5396 } 5397 5398 stmmac_finalize_xdp_rx(priv, xdp_status); 5399 5400 stmmac_rx_refill(priv, queue); 5401 5402 priv->xstats.rx_pkt_n += count; 5403 priv->xstats.rxq_stats[queue].rx_pkt_n += count; 5404 5405 return count; 5406 } 5407 5408 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5409 { 5410 struct stmmac_channel *ch = 5411 container_of(napi, struct stmmac_channel, rx_napi); 5412 struct stmmac_priv *priv = ch->priv_data; 5413 u32 chan = ch->index; 5414 int work_done; 5415 5416 priv->xstats.napi_poll++; 5417 5418 work_done = stmmac_rx(priv, budget, chan); 5419 if (work_done < budget && napi_complete_done(napi, work_done)) { 5420 unsigned long flags; 5421 5422 spin_lock_irqsave(&ch->lock, flags); 5423 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5424 spin_unlock_irqrestore(&ch->lock, flags); 5425 } 5426 5427 return work_done; 5428 } 5429 5430 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5431 { 5432 struct stmmac_channel *ch = 5433 container_of(napi, struct stmmac_channel, tx_napi); 5434 struct stmmac_priv *priv = ch->priv_data; 5435 u32 chan = ch->index; 5436 int work_done; 5437 5438 priv->xstats.napi_poll++; 5439 5440 work_done = stmmac_tx_clean(priv, budget, chan); 5441 work_done = min(work_done, budget); 5442 5443 if (work_done < budget && napi_complete_done(napi, work_done)) { 5444 unsigned long flags; 5445 5446 spin_lock_irqsave(&ch->lock, flags); 5447 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5448 spin_unlock_irqrestore(&ch->lock, flags); 5449 } 5450 5451 return work_done; 5452 } 5453 5454 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5455 { 5456 struct stmmac_channel *ch = 5457 container_of(napi, struct stmmac_channel, rxtx_napi); 5458 struct stmmac_priv *priv = ch->priv_data; 5459 int rx_done, tx_done, rxtx_done; 5460 u32 chan = ch->index; 5461 5462 priv->xstats.napi_poll++; 5463 5464 tx_done = stmmac_tx_clean(priv, budget, chan); 5465 tx_done = min(tx_done, budget); 5466 5467 rx_done = stmmac_rx_zc(priv, budget, chan); 5468 5469 rxtx_done = max(tx_done, rx_done); 5470 5471 /* If either TX or RX work is not complete, return budget 5472 * and keep pooling 5473 */ 5474 if (rxtx_done >= budget) 5475 return budget; 5476 5477 /* all work done, exit the polling mode */ 5478 if (napi_complete_done(napi, rxtx_done)) { 5479 unsigned long flags; 5480 5481 spin_lock_irqsave(&ch->lock, flags); 5482 /* Both RX and TX work done are compelte, 5483 * so enable both RX & TX IRQs. 5484 */ 5485 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5486 spin_unlock_irqrestore(&ch->lock, flags); 5487 } 5488 5489 return min(rxtx_done, budget - 1); 5490 } 5491 5492 /** 5493 * stmmac_tx_timeout 5494 * @dev : Pointer to net device structure 5495 * @txqueue: the index of the hanging transmit queue 5496 * Description: this function is called when a packet transmission fails to 5497 * complete within a reasonable time. The driver will mark the error in the 5498 * netdev structure and arrange for the device to be reset to a sane state 5499 * in order to transmit a new packet. 5500 */ 5501 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5502 { 5503 struct stmmac_priv *priv = netdev_priv(dev); 5504 5505 stmmac_global_err(priv); 5506 } 5507 5508 /** 5509 * stmmac_set_rx_mode - entry point for multicast addressing 5510 * @dev : pointer to the device structure 5511 * Description: 5512 * This function is a driver entry point which gets called by the kernel 5513 * whenever multicast addresses must be enabled/disabled. 5514 * Return value: 5515 * void. 5516 */ 5517 static void stmmac_set_rx_mode(struct net_device *dev) 5518 { 5519 struct stmmac_priv *priv = netdev_priv(dev); 5520 5521 stmmac_set_filter(priv, priv->hw, dev); 5522 } 5523 5524 /** 5525 * stmmac_change_mtu - entry point to change MTU size for the device. 5526 * @dev : device pointer. 5527 * @new_mtu : the new MTU size for the device. 5528 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5529 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5530 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5531 * Return value: 5532 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5533 * file on failure. 5534 */ 5535 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5536 { 5537 struct stmmac_priv *priv = netdev_priv(dev); 5538 int txfifosz = priv->plat->tx_fifo_size; 5539 struct stmmac_dma_conf *dma_conf; 5540 const int mtu = new_mtu; 5541 int ret; 5542 5543 if (txfifosz == 0) 5544 txfifosz = priv->dma_cap.tx_fifo_size; 5545 5546 txfifosz /= priv->plat->tx_queues_to_use; 5547 5548 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5549 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5550 return -EINVAL; 5551 } 5552 5553 new_mtu = STMMAC_ALIGN(new_mtu); 5554 5555 /* If condition true, FIFO is too small or MTU too large */ 5556 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5557 return -EINVAL; 5558 5559 if (netif_running(dev)) { 5560 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5561 /* Try to allocate the new DMA conf with the new mtu */ 5562 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5563 if (IS_ERR(dma_conf)) { 5564 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5565 mtu); 5566 return PTR_ERR(dma_conf); 5567 } 5568 5569 stmmac_release(dev); 5570 5571 ret = __stmmac_open(dev, dma_conf); 5572 kfree(dma_conf); 5573 if (ret) { 5574 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5575 return ret; 5576 } 5577 5578 stmmac_set_rx_mode(dev); 5579 } 5580 5581 dev->mtu = mtu; 5582 netdev_update_features(dev); 5583 5584 return 0; 5585 } 5586 5587 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5588 netdev_features_t features) 5589 { 5590 struct stmmac_priv *priv = netdev_priv(dev); 5591 5592 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5593 features &= ~NETIF_F_RXCSUM; 5594 5595 if (!priv->plat->tx_coe) 5596 features &= ~NETIF_F_CSUM_MASK; 5597 5598 /* Some GMAC devices have a bugged Jumbo frame support that 5599 * needs to have the Tx COE disabled for oversized frames 5600 * (due to limited buffer sizes). In this case we disable 5601 * the TX csum insertion in the TDES and not use SF. 5602 */ 5603 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5604 features &= ~NETIF_F_CSUM_MASK; 5605 5606 /* Disable tso if asked by ethtool */ 5607 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5608 if (features & NETIF_F_TSO) 5609 priv->tso = true; 5610 else 5611 priv->tso = false; 5612 } 5613 5614 return features; 5615 } 5616 5617 static int stmmac_set_features(struct net_device *netdev, 5618 netdev_features_t features) 5619 { 5620 struct stmmac_priv *priv = netdev_priv(netdev); 5621 5622 /* Keep the COE Type in case of csum is supporting */ 5623 if (features & NETIF_F_RXCSUM) 5624 priv->hw->rx_csum = priv->plat->rx_coe; 5625 else 5626 priv->hw->rx_csum = 0; 5627 /* No check needed because rx_coe has been set before and it will be 5628 * fixed in case of issue. 5629 */ 5630 stmmac_rx_ipc(priv, priv->hw); 5631 5632 if (priv->sph_cap) { 5633 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5634 u32 chan; 5635 5636 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5637 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5638 } 5639 5640 return 0; 5641 } 5642 5643 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5644 { 5645 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5646 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5647 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5648 bool *hs_enable = &fpe_cfg->hs_enable; 5649 5650 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5651 return; 5652 5653 /* If LP has sent verify mPacket, LP is FPE capable */ 5654 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5655 if (*lp_state < FPE_STATE_CAPABLE) 5656 *lp_state = FPE_STATE_CAPABLE; 5657 5658 /* If user has requested FPE enable, quickly response */ 5659 if (*hs_enable) 5660 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5661 MPACKET_RESPONSE); 5662 } 5663 5664 /* If Local has sent verify mPacket, Local is FPE capable */ 5665 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5666 if (*lo_state < FPE_STATE_CAPABLE) 5667 *lo_state = FPE_STATE_CAPABLE; 5668 } 5669 5670 /* If LP has sent response mPacket, LP is entering FPE ON */ 5671 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5672 *lp_state = FPE_STATE_ENTERING_ON; 5673 5674 /* If Local has sent response mPacket, Local is entering FPE ON */ 5675 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5676 *lo_state = FPE_STATE_ENTERING_ON; 5677 5678 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5679 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5680 priv->fpe_wq) { 5681 queue_work(priv->fpe_wq, &priv->fpe_task); 5682 } 5683 } 5684 5685 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5686 { 5687 u32 rx_cnt = priv->plat->rx_queues_to_use; 5688 u32 tx_cnt = priv->plat->tx_queues_to_use; 5689 u32 queues_count; 5690 u32 queue; 5691 bool xmac; 5692 5693 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5694 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5695 5696 if (priv->irq_wake) 5697 pm_wakeup_event(priv->device, 0); 5698 5699 if (priv->dma_cap.estsel) 5700 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5701 &priv->xstats, tx_cnt); 5702 5703 if (priv->dma_cap.fpesel) { 5704 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5705 priv->dev); 5706 5707 stmmac_fpe_event_status(priv, status); 5708 } 5709 5710 /* To handle GMAC own interrupts */ 5711 if ((priv->plat->has_gmac) || xmac) { 5712 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5713 5714 if (unlikely(status)) { 5715 /* For LPI we need to save the tx status */ 5716 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5717 priv->tx_path_in_lpi_mode = true; 5718 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5719 priv->tx_path_in_lpi_mode = false; 5720 } 5721 5722 for (queue = 0; queue < queues_count; queue++) { 5723 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5724 queue); 5725 } 5726 5727 /* PCS link status */ 5728 if (priv->hw->pcs) { 5729 if (priv->xstats.pcs_link) 5730 netif_carrier_on(priv->dev); 5731 else 5732 netif_carrier_off(priv->dev); 5733 } 5734 5735 stmmac_timestamp_interrupt(priv, priv); 5736 } 5737 } 5738 5739 /** 5740 * stmmac_interrupt - main ISR 5741 * @irq: interrupt number. 5742 * @dev_id: to pass the net device pointer. 5743 * Description: this is the main driver interrupt service routine. 5744 * It can call: 5745 * o DMA service routine (to manage incoming frame reception and transmission 5746 * status) 5747 * o Core interrupts to manage: remote wake-up, management counter, LPI 5748 * interrupts. 5749 */ 5750 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5751 { 5752 struct net_device *dev = (struct net_device *)dev_id; 5753 struct stmmac_priv *priv = netdev_priv(dev); 5754 5755 /* Check if adapter is up */ 5756 if (test_bit(STMMAC_DOWN, &priv->state)) 5757 return IRQ_HANDLED; 5758 5759 /* Check if a fatal error happened */ 5760 if (stmmac_safety_feat_interrupt(priv)) 5761 return IRQ_HANDLED; 5762 5763 /* To handle Common interrupts */ 5764 stmmac_common_interrupt(priv); 5765 5766 /* To handle DMA interrupts */ 5767 stmmac_dma_interrupt(priv); 5768 5769 return IRQ_HANDLED; 5770 } 5771 5772 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5773 { 5774 struct net_device *dev = (struct net_device *)dev_id; 5775 struct stmmac_priv *priv = netdev_priv(dev); 5776 5777 if (unlikely(!dev)) { 5778 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5779 return IRQ_NONE; 5780 } 5781 5782 /* Check if adapter is up */ 5783 if (test_bit(STMMAC_DOWN, &priv->state)) 5784 return IRQ_HANDLED; 5785 5786 /* To handle Common interrupts */ 5787 stmmac_common_interrupt(priv); 5788 5789 return IRQ_HANDLED; 5790 } 5791 5792 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5793 { 5794 struct net_device *dev = (struct net_device *)dev_id; 5795 struct stmmac_priv *priv = netdev_priv(dev); 5796 5797 if (unlikely(!dev)) { 5798 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5799 return IRQ_NONE; 5800 } 5801 5802 /* Check if adapter is up */ 5803 if (test_bit(STMMAC_DOWN, &priv->state)) 5804 return IRQ_HANDLED; 5805 5806 /* Check if a fatal error happened */ 5807 stmmac_safety_feat_interrupt(priv); 5808 5809 return IRQ_HANDLED; 5810 } 5811 5812 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5813 { 5814 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5815 struct stmmac_dma_conf *dma_conf; 5816 int chan = tx_q->queue_index; 5817 struct stmmac_priv *priv; 5818 int status; 5819 5820 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5821 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5822 5823 if (unlikely(!data)) { 5824 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5825 return IRQ_NONE; 5826 } 5827 5828 /* Check if adapter is up */ 5829 if (test_bit(STMMAC_DOWN, &priv->state)) 5830 return IRQ_HANDLED; 5831 5832 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5833 5834 if (unlikely(status & tx_hard_error_bump_tc)) { 5835 /* Try to bump up the dma threshold on this failure */ 5836 stmmac_bump_dma_threshold(priv, chan); 5837 } else if (unlikely(status == tx_hard_error)) { 5838 stmmac_tx_err(priv, chan); 5839 } 5840 5841 return IRQ_HANDLED; 5842 } 5843 5844 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5845 { 5846 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5847 struct stmmac_dma_conf *dma_conf; 5848 int chan = rx_q->queue_index; 5849 struct stmmac_priv *priv; 5850 5851 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5852 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5853 5854 if (unlikely(!data)) { 5855 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5856 return IRQ_NONE; 5857 } 5858 5859 /* Check if adapter is up */ 5860 if (test_bit(STMMAC_DOWN, &priv->state)) 5861 return IRQ_HANDLED; 5862 5863 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5864 5865 return IRQ_HANDLED; 5866 } 5867 5868 #ifdef CONFIG_NET_POLL_CONTROLLER 5869 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5870 * to allow network I/O with interrupts disabled. 5871 */ 5872 static void stmmac_poll_controller(struct net_device *dev) 5873 { 5874 struct stmmac_priv *priv = netdev_priv(dev); 5875 int i; 5876 5877 /* If adapter is down, do nothing */ 5878 if (test_bit(STMMAC_DOWN, &priv->state)) 5879 return; 5880 5881 if (priv->plat->multi_msi_en) { 5882 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5883 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 5884 5885 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5886 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 5887 } else { 5888 disable_irq(dev->irq); 5889 stmmac_interrupt(dev->irq, dev); 5890 enable_irq(dev->irq); 5891 } 5892 } 5893 #endif 5894 5895 /** 5896 * stmmac_ioctl - Entry point for the Ioctl 5897 * @dev: Device pointer. 5898 * @rq: An IOCTL specefic structure, that can contain a pointer to 5899 * a proprietary structure used to pass information to the driver. 5900 * @cmd: IOCTL command 5901 * Description: 5902 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5903 */ 5904 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5905 { 5906 struct stmmac_priv *priv = netdev_priv (dev); 5907 int ret = -EOPNOTSUPP; 5908 5909 if (!netif_running(dev)) 5910 return -EINVAL; 5911 5912 switch (cmd) { 5913 case SIOCGMIIPHY: 5914 case SIOCGMIIREG: 5915 case SIOCSMIIREG: 5916 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5917 break; 5918 case SIOCSHWTSTAMP: 5919 ret = stmmac_hwtstamp_set(dev, rq); 5920 break; 5921 case SIOCGHWTSTAMP: 5922 ret = stmmac_hwtstamp_get(dev, rq); 5923 break; 5924 default: 5925 break; 5926 } 5927 5928 return ret; 5929 } 5930 5931 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5932 void *cb_priv) 5933 { 5934 struct stmmac_priv *priv = cb_priv; 5935 int ret = -EOPNOTSUPP; 5936 5937 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5938 return ret; 5939 5940 __stmmac_disable_all_queues(priv); 5941 5942 switch (type) { 5943 case TC_SETUP_CLSU32: 5944 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5945 break; 5946 case TC_SETUP_CLSFLOWER: 5947 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5948 break; 5949 default: 5950 break; 5951 } 5952 5953 stmmac_enable_all_queues(priv); 5954 return ret; 5955 } 5956 5957 static LIST_HEAD(stmmac_block_cb_list); 5958 5959 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5960 void *type_data) 5961 { 5962 struct stmmac_priv *priv = netdev_priv(ndev); 5963 5964 switch (type) { 5965 case TC_SETUP_BLOCK: 5966 return flow_block_cb_setup_simple(type_data, 5967 &stmmac_block_cb_list, 5968 stmmac_setup_tc_block_cb, 5969 priv, priv, true); 5970 case TC_SETUP_QDISC_CBS: 5971 return stmmac_tc_setup_cbs(priv, priv, type_data); 5972 case TC_SETUP_QDISC_TAPRIO: 5973 return stmmac_tc_setup_taprio(priv, priv, type_data); 5974 case TC_SETUP_QDISC_ETF: 5975 return stmmac_tc_setup_etf(priv, priv, type_data); 5976 default: 5977 return -EOPNOTSUPP; 5978 } 5979 } 5980 5981 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5982 struct net_device *sb_dev) 5983 { 5984 int gso = skb_shinfo(skb)->gso_type; 5985 5986 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5987 /* 5988 * There is no way to determine the number of TSO/USO 5989 * capable Queues. Let's use always the Queue 0 5990 * because if TSO/USO is supported then at least this 5991 * one will be capable. 5992 */ 5993 return 0; 5994 } 5995 5996 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5997 } 5998 5999 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6000 { 6001 struct stmmac_priv *priv = netdev_priv(ndev); 6002 int ret = 0; 6003 6004 ret = pm_runtime_resume_and_get(priv->device); 6005 if (ret < 0) 6006 return ret; 6007 6008 ret = eth_mac_addr(ndev, addr); 6009 if (ret) 6010 goto set_mac_error; 6011 6012 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6013 6014 set_mac_error: 6015 pm_runtime_put(priv->device); 6016 6017 return ret; 6018 } 6019 6020 #ifdef CONFIG_DEBUG_FS 6021 static struct dentry *stmmac_fs_dir; 6022 6023 static void sysfs_display_ring(void *head, int size, int extend_desc, 6024 struct seq_file *seq, dma_addr_t dma_phy_addr) 6025 { 6026 int i; 6027 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6028 struct dma_desc *p = (struct dma_desc *)head; 6029 dma_addr_t dma_addr; 6030 6031 for (i = 0; i < size; i++) { 6032 if (extend_desc) { 6033 dma_addr = dma_phy_addr + i * sizeof(*ep); 6034 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6035 i, &dma_addr, 6036 le32_to_cpu(ep->basic.des0), 6037 le32_to_cpu(ep->basic.des1), 6038 le32_to_cpu(ep->basic.des2), 6039 le32_to_cpu(ep->basic.des3)); 6040 ep++; 6041 } else { 6042 dma_addr = dma_phy_addr + i * sizeof(*p); 6043 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6044 i, &dma_addr, 6045 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6046 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6047 p++; 6048 } 6049 seq_printf(seq, "\n"); 6050 } 6051 } 6052 6053 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6054 { 6055 struct net_device *dev = seq->private; 6056 struct stmmac_priv *priv = netdev_priv(dev); 6057 u32 rx_count = priv->plat->rx_queues_to_use; 6058 u32 tx_count = priv->plat->tx_queues_to_use; 6059 u32 queue; 6060 6061 if ((dev->flags & IFF_UP) == 0) 6062 return 0; 6063 6064 for (queue = 0; queue < rx_count; queue++) { 6065 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6066 6067 seq_printf(seq, "RX Queue %d:\n", queue); 6068 6069 if (priv->extend_desc) { 6070 seq_printf(seq, "Extended descriptor ring:\n"); 6071 sysfs_display_ring((void *)rx_q->dma_erx, 6072 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6073 } else { 6074 seq_printf(seq, "Descriptor ring:\n"); 6075 sysfs_display_ring((void *)rx_q->dma_rx, 6076 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6077 } 6078 } 6079 6080 for (queue = 0; queue < tx_count; queue++) { 6081 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6082 6083 seq_printf(seq, "TX Queue %d:\n", queue); 6084 6085 if (priv->extend_desc) { 6086 seq_printf(seq, "Extended descriptor ring:\n"); 6087 sysfs_display_ring((void *)tx_q->dma_etx, 6088 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6089 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6090 seq_printf(seq, "Descriptor ring:\n"); 6091 sysfs_display_ring((void *)tx_q->dma_tx, 6092 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6093 } 6094 } 6095 6096 return 0; 6097 } 6098 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6099 6100 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6101 { 6102 struct net_device *dev = seq->private; 6103 struct stmmac_priv *priv = netdev_priv(dev); 6104 6105 if (!priv->hw_cap_support) { 6106 seq_printf(seq, "DMA HW features not supported\n"); 6107 return 0; 6108 } 6109 6110 seq_printf(seq, "==============================\n"); 6111 seq_printf(seq, "\tDMA HW features\n"); 6112 seq_printf(seq, "==============================\n"); 6113 6114 seq_printf(seq, "\t10/100 Mbps: %s\n", 6115 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6116 seq_printf(seq, "\t1000 Mbps: %s\n", 6117 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6118 seq_printf(seq, "\tHalf duplex: %s\n", 6119 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6120 seq_printf(seq, "\tHash Filter: %s\n", 6121 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6122 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6123 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6124 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6125 (priv->dma_cap.pcs) ? "Y" : "N"); 6126 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6127 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6128 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6129 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6130 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6131 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6132 seq_printf(seq, "\tRMON module: %s\n", 6133 (priv->dma_cap.rmon) ? "Y" : "N"); 6134 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6135 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6136 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6137 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6138 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6139 (priv->dma_cap.eee) ? "Y" : "N"); 6140 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6141 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6142 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6143 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6144 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6145 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6146 } else { 6147 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6148 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6149 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6150 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6151 } 6152 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6153 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6154 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6155 priv->dma_cap.number_rx_channel); 6156 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6157 priv->dma_cap.number_tx_channel); 6158 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6159 priv->dma_cap.number_rx_queues); 6160 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6161 priv->dma_cap.number_tx_queues); 6162 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6163 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6164 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6165 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6166 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6167 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6168 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6169 priv->dma_cap.pps_out_num); 6170 seq_printf(seq, "\tSafety Features: %s\n", 6171 priv->dma_cap.asp ? "Y" : "N"); 6172 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6173 priv->dma_cap.frpsel ? "Y" : "N"); 6174 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6175 priv->dma_cap.addr64); 6176 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6177 priv->dma_cap.rssen ? "Y" : "N"); 6178 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6179 priv->dma_cap.vlhash ? "Y" : "N"); 6180 seq_printf(seq, "\tSplit Header: %s\n", 6181 priv->dma_cap.sphen ? "Y" : "N"); 6182 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6183 priv->dma_cap.vlins ? "Y" : "N"); 6184 seq_printf(seq, "\tDouble VLAN: %s\n", 6185 priv->dma_cap.dvlan ? "Y" : "N"); 6186 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6187 priv->dma_cap.l3l4fnum); 6188 seq_printf(seq, "\tARP Offloading: %s\n", 6189 priv->dma_cap.arpoffsel ? "Y" : "N"); 6190 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6191 priv->dma_cap.estsel ? "Y" : "N"); 6192 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6193 priv->dma_cap.fpesel ? "Y" : "N"); 6194 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6195 priv->dma_cap.tbssel ? "Y" : "N"); 6196 return 0; 6197 } 6198 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6199 6200 /* Use network device events to rename debugfs file entries. 6201 */ 6202 static int stmmac_device_event(struct notifier_block *unused, 6203 unsigned long event, void *ptr) 6204 { 6205 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6206 struct stmmac_priv *priv = netdev_priv(dev); 6207 6208 if (dev->netdev_ops != &stmmac_netdev_ops) 6209 goto done; 6210 6211 switch (event) { 6212 case NETDEV_CHANGENAME: 6213 if (priv->dbgfs_dir) 6214 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6215 priv->dbgfs_dir, 6216 stmmac_fs_dir, 6217 dev->name); 6218 break; 6219 } 6220 done: 6221 return NOTIFY_DONE; 6222 } 6223 6224 static struct notifier_block stmmac_notifier = { 6225 .notifier_call = stmmac_device_event, 6226 }; 6227 6228 static void stmmac_init_fs(struct net_device *dev) 6229 { 6230 struct stmmac_priv *priv = netdev_priv(dev); 6231 6232 rtnl_lock(); 6233 6234 /* Create per netdev entries */ 6235 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6236 6237 /* Entry to report DMA RX/TX rings */ 6238 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6239 &stmmac_rings_status_fops); 6240 6241 /* Entry to report the DMA HW features */ 6242 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6243 &stmmac_dma_cap_fops); 6244 6245 rtnl_unlock(); 6246 } 6247 6248 static void stmmac_exit_fs(struct net_device *dev) 6249 { 6250 struct stmmac_priv *priv = netdev_priv(dev); 6251 6252 debugfs_remove_recursive(priv->dbgfs_dir); 6253 } 6254 #endif /* CONFIG_DEBUG_FS */ 6255 6256 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6257 { 6258 unsigned char *data = (unsigned char *)&vid_le; 6259 unsigned char data_byte = 0; 6260 u32 crc = ~0x0; 6261 u32 temp = 0; 6262 int i, bits; 6263 6264 bits = get_bitmask_order(VLAN_VID_MASK); 6265 for (i = 0; i < bits; i++) { 6266 if ((i % 8) == 0) 6267 data_byte = data[i / 8]; 6268 6269 temp = ((crc & 1) ^ data_byte) & 1; 6270 crc >>= 1; 6271 data_byte >>= 1; 6272 6273 if (temp) 6274 crc ^= 0xedb88320; 6275 } 6276 6277 return crc; 6278 } 6279 6280 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6281 { 6282 u32 crc, hash = 0; 6283 __le16 pmatch = 0; 6284 int count = 0; 6285 u16 vid = 0; 6286 6287 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6288 __le16 vid_le = cpu_to_le16(vid); 6289 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6290 hash |= (1 << crc); 6291 count++; 6292 } 6293 6294 if (!priv->dma_cap.vlhash) { 6295 if (count > 2) /* VID = 0 always passes filter */ 6296 return -EOPNOTSUPP; 6297 6298 pmatch = cpu_to_le16(vid); 6299 hash = 0; 6300 } 6301 6302 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6303 } 6304 6305 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6306 { 6307 struct stmmac_priv *priv = netdev_priv(ndev); 6308 bool is_double = false; 6309 int ret; 6310 6311 if (be16_to_cpu(proto) == ETH_P_8021AD) 6312 is_double = true; 6313 6314 set_bit(vid, priv->active_vlans); 6315 ret = stmmac_vlan_update(priv, is_double); 6316 if (ret) { 6317 clear_bit(vid, priv->active_vlans); 6318 return ret; 6319 } 6320 6321 if (priv->hw->num_vlan) { 6322 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6323 if (ret) 6324 return ret; 6325 } 6326 6327 return 0; 6328 } 6329 6330 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6331 { 6332 struct stmmac_priv *priv = netdev_priv(ndev); 6333 bool is_double = false; 6334 int ret; 6335 6336 ret = pm_runtime_resume_and_get(priv->device); 6337 if (ret < 0) 6338 return ret; 6339 6340 if (be16_to_cpu(proto) == ETH_P_8021AD) 6341 is_double = true; 6342 6343 clear_bit(vid, priv->active_vlans); 6344 6345 if (priv->hw->num_vlan) { 6346 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6347 if (ret) 6348 goto del_vlan_error; 6349 } 6350 6351 ret = stmmac_vlan_update(priv, is_double); 6352 6353 del_vlan_error: 6354 pm_runtime_put(priv->device); 6355 6356 return ret; 6357 } 6358 6359 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6360 { 6361 struct stmmac_priv *priv = netdev_priv(dev); 6362 6363 switch (bpf->command) { 6364 case XDP_SETUP_PROG: 6365 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6366 case XDP_SETUP_XSK_POOL: 6367 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6368 bpf->xsk.queue_id); 6369 default: 6370 return -EOPNOTSUPP; 6371 } 6372 } 6373 6374 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6375 struct xdp_frame **frames, u32 flags) 6376 { 6377 struct stmmac_priv *priv = netdev_priv(dev); 6378 int cpu = smp_processor_id(); 6379 struct netdev_queue *nq; 6380 int i, nxmit = 0; 6381 int queue; 6382 6383 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6384 return -ENETDOWN; 6385 6386 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6387 return -EINVAL; 6388 6389 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6390 nq = netdev_get_tx_queue(priv->dev, queue); 6391 6392 __netif_tx_lock(nq, cpu); 6393 /* Avoids TX time-out as we are sharing with slow path */ 6394 txq_trans_cond_update(nq); 6395 6396 for (i = 0; i < num_frames; i++) { 6397 int res; 6398 6399 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6400 if (res == STMMAC_XDP_CONSUMED) 6401 break; 6402 6403 nxmit++; 6404 } 6405 6406 if (flags & XDP_XMIT_FLUSH) { 6407 stmmac_flush_tx_descriptors(priv, queue); 6408 stmmac_tx_timer_arm(priv, queue); 6409 } 6410 6411 __netif_tx_unlock(nq); 6412 6413 return nxmit; 6414 } 6415 6416 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6417 { 6418 struct stmmac_channel *ch = &priv->channel[queue]; 6419 unsigned long flags; 6420 6421 spin_lock_irqsave(&ch->lock, flags); 6422 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6423 spin_unlock_irqrestore(&ch->lock, flags); 6424 6425 stmmac_stop_rx_dma(priv, queue); 6426 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6427 } 6428 6429 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6430 { 6431 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6432 struct stmmac_channel *ch = &priv->channel[queue]; 6433 unsigned long flags; 6434 u32 buf_size; 6435 int ret; 6436 6437 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6438 if (ret) { 6439 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6440 return; 6441 } 6442 6443 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6444 if (ret) { 6445 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6446 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6447 return; 6448 } 6449 6450 stmmac_reset_rx_queue(priv, queue); 6451 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6452 6453 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6454 rx_q->dma_rx_phy, rx_q->queue_index); 6455 6456 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6457 sizeof(struct dma_desc)); 6458 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6459 rx_q->rx_tail_addr, rx_q->queue_index); 6460 6461 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6462 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6463 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6464 buf_size, 6465 rx_q->queue_index); 6466 } else { 6467 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6468 priv->dma_conf.dma_buf_sz, 6469 rx_q->queue_index); 6470 } 6471 6472 stmmac_start_rx_dma(priv, queue); 6473 6474 spin_lock_irqsave(&ch->lock, flags); 6475 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6476 spin_unlock_irqrestore(&ch->lock, flags); 6477 } 6478 6479 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6480 { 6481 struct stmmac_channel *ch = &priv->channel[queue]; 6482 unsigned long flags; 6483 6484 spin_lock_irqsave(&ch->lock, flags); 6485 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6486 spin_unlock_irqrestore(&ch->lock, flags); 6487 6488 stmmac_stop_tx_dma(priv, queue); 6489 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6490 } 6491 6492 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6493 { 6494 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6495 struct stmmac_channel *ch = &priv->channel[queue]; 6496 unsigned long flags; 6497 int ret; 6498 6499 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6500 if (ret) { 6501 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6502 return; 6503 } 6504 6505 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6506 if (ret) { 6507 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6508 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6509 return; 6510 } 6511 6512 stmmac_reset_tx_queue(priv, queue); 6513 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6514 6515 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6516 tx_q->dma_tx_phy, tx_q->queue_index); 6517 6518 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6519 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6520 6521 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6522 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6523 tx_q->tx_tail_addr, tx_q->queue_index); 6524 6525 stmmac_start_tx_dma(priv, queue); 6526 6527 spin_lock_irqsave(&ch->lock, flags); 6528 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6529 spin_unlock_irqrestore(&ch->lock, flags); 6530 } 6531 6532 void stmmac_xdp_release(struct net_device *dev) 6533 { 6534 struct stmmac_priv *priv = netdev_priv(dev); 6535 u32 chan; 6536 6537 /* Disable NAPI process */ 6538 stmmac_disable_all_queues(priv); 6539 6540 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6541 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6542 6543 /* Free the IRQ lines */ 6544 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6545 6546 /* Stop TX/RX DMA channels */ 6547 stmmac_stop_all_dma(priv); 6548 6549 /* Release and free the Rx/Tx resources */ 6550 free_dma_desc_resources(priv, &priv->dma_conf); 6551 6552 /* Disable the MAC Rx/Tx */ 6553 stmmac_mac_set(priv, priv->ioaddr, false); 6554 6555 /* set trans_start so we don't get spurious 6556 * watchdogs during reset 6557 */ 6558 netif_trans_update(dev); 6559 netif_carrier_off(dev); 6560 } 6561 6562 int stmmac_xdp_open(struct net_device *dev) 6563 { 6564 struct stmmac_priv *priv = netdev_priv(dev); 6565 u32 rx_cnt = priv->plat->rx_queues_to_use; 6566 u32 tx_cnt = priv->plat->tx_queues_to_use; 6567 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6568 struct stmmac_rx_queue *rx_q; 6569 struct stmmac_tx_queue *tx_q; 6570 u32 buf_size; 6571 bool sph_en; 6572 u32 chan; 6573 int ret; 6574 6575 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6576 if (ret < 0) { 6577 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6578 __func__); 6579 goto dma_desc_error; 6580 } 6581 6582 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6583 if (ret < 0) { 6584 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6585 __func__); 6586 goto init_error; 6587 } 6588 6589 /* DMA CSR Channel configuration */ 6590 for (chan = 0; chan < dma_csr_ch; chan++) { 6591 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6592 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6593 } 6594 6595 /* Adjust Split header */ 6596 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6597 6598 /* DMA RX Channel Configuration */ 6599 for (chan = 0; chan < rx_cnt; chan++) { 6600 rx_q = &priv->dma_conf.rx_queue[chan]; 6601 6602 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6603 rx_q->dma_rx_phy, chan); 6604 6605 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6606 (rx_q->buf_alloc_num * 6607 sizeof(struct dma_desc)); 6608 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6609 rx_q->rx_tail_addr, chan); 6610 6611 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6612 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6613 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6614 buf_size, 6615 rx_q->queue_index); 6616 } else { 6617 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6618 priv->dma_conf.dma_buf_sz, 6619 rx_q->queue_index); 6620 } 6621 6622 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6623 } 6624 6625 /* DMA TX Channel Configuration */ 6626 for (chan = 0; chan < tx_cnt; chan++) { 6627 tx_q = &priv->dma_conf.tx_queue[chan]; 6628 6629 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6630 tx_q->dma_tx_phy, chan); 6631 6632 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6633 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6634 tx_q->tx_tail_addr, chan); 6635 6636 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6637 tx_q->txtimer.function = stmmac_tx_timer; 6638 } 6639 6640 /* Enable the MAC Rx/Tx */ 6641 stmmac_mac_set(priv, priv->ioaddr, true); 6642 6643 /* Start Rx & Tx DMA Channels */ 6644 stmmac_start_all_dma(priv); 6645 6646 ret = stmmac_request_irq(dev); 6647 if (ret) 6648 goto irq_error; 6649 6650 /* Enable NAPI process*/ 6651 stmmac_enable_all_queues(priv); 6652 netif_carrier_on(dev); 6653 netif_tx_start_all_queues(dev); 6654 stmmac_enable_all_dma_irq(priv); 6655 6656 return 0; 6657 6658 irq_error: 6659 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6660 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6661 6662 stmmac_hw_teardown(dev); 6663 init_error: 6664 free_dma_desc_resources(priv, &priv->dma_conf); 6665 dma_desc_error: 6666 return ret; 6667 } 6668 6669 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6670 { 6671 struct stmmac_priv *priv = netdev_priv(dev); 6672 struct stmmac_rx_queue *rx_q; 6673 struct stmmac_tx_queue *tx_q; 6674 struct stmmac_channel *ch; 6675 6676 if (test_bit(STMMAC_DOWN, &priv->state) || 6677 !netif_carrier_ok(priv->dev)) 6678 return -ENETDOWN; 6679 6680 if (!stmmac_xdp_is_enabled(priv)) 6681 return -EINVAL; 6682 6683 if (queue >= priv->plat->rx_queues_to_use || 6684 queue >= priv->plat->tx_queues_to_use) 6685 return -EINVAL; 6686 6687 rx_q = &priv->dma_conf.rx_queue[queue]; 6688 tx_q = &priv->dma_conf.tx_queue[queue]; 6689 ch = &priv->channel[queue]; 6690 6691 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6692 return -EINVAL; 6693 6694 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6695 /* EQoS does not have per-DMA channel SW interrupt, 6696 * so we schedule RX Napi straight-away. 6697 */ 6698 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6699 __napi_schedule(&ch->rxtx_napi); 6700 } 6701 6702 return 0; 6703 } 6704 6705 static const struct net_device_ops stmmac_netdev_ops = { 6706 .ndo_open = stmmac_open, 6707 .ndo_start_xmit = stmmac_xmit, 6708 .ndo_stop = stmmac_release, 6709 .ndo_change_mtu = stmmac_change_mtu, 6710 .ndo_fix_features = stmmac_fix_features, 6711 .ndo_set_features = stmmac_set_features, 6712 .ndo_set_rx_mode = stmmac_set_rx_mode, 6713 .ndo_tx_timeout = stmmac_tx_timeout, 6714 .ndo_eth_ioctl = stmmac_ioctl, 6715 .ndo_setup_tc = stmmac_setup_tc, 6716 .ndo_select_queue = stmmac_select_queue, 6717 #ifdef CONFIG_NET_POLL_CONTROLLER 6718 .ndo_poll_controller = stmmac_poll_controller, 6719 #endif 6720 .ndo_set_mac_address = stmmac_set_mac_address, 6721 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6722 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6723 .ndo_bpf = stmmac_bpf, 6724 .ndo_xdp_xmit = stmmac_xdp_xmit, 6725 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6726 }; 6727 6728 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6729 { 6730 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6731 return; 6732 if (test_bit(STMMAC_DOWN, &priv->state)) 6733 return; 6734 6735 netdev_err(priv->dev, "Reset adapter.\n"); 6736 6737 rtnl_lock(); 6738 netif_trans_update(priv->dev); 6739 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6740 usleep_range(1000, 2000); 6741 6742 set_bit(STMMAC_DOWN, &priv->state); 6743 dev_close(priv->dev); 6744 dev_open(priv->dev, NULL); 6745 clear_bit(STMMAC_DOWN, &priv->state); 6746 clear_bit(STMMAC_RESETING, &priv->state); 6747 rtnl_unlock(); 6748 } 6749 6750 static void stmmac_service_task(struct work_struct *work) 6751 { 6752 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6753 service_task); 6754 6755 stmmac_reset_subtask(priv); 6756 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6757 } 6758 6759 /** 6760 * stmmac_hw_init - Init the MAC device 6761 * @priv: driver private structure 6762 * Description: this function is to configure the MAC device according to 6763 * some platform parameters or the HW capability register. It prepares the 6764 * driver to use either ring or chain modes and to setup either enhanced or 6765 * normal descriptors. 6766 */ 6767 static int stmmac_hw_init(struct stmmac_priv *priv) 6768 { 6769 int ret; 6770 6771 /* dwmac-sun8i only work in chain mode */ 6772 if (priv->plat->has_sun8i) 6773 chain_mode = 1; 6774 priv->chain_mode = chain_mode; 6775 6776 /* Initialize HW Interface */ 6777 ret = stmmac_hwif_init(priv); 6778 if (ret) 6779 return ret; 6780 6781 /* Get the HW capability (new GMAC newer than 3.50a) */ 6782 priv->hw_cap_support = stmmac_get_hw_features(priv); 6783 if (priv->hw_cap_support) { 6784 dev_info(priv->device, "DMA HW capability register supported\n"); 6785 6786 /* We can override some gmac/dma configuration fields: e.g. 6787 * enh_desc, tx_coe (e.g. that are passed through the 6788 * platform) with the values from the HW capability 6789 * register (if supported). 6790 */ 6791 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6792 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6793 !priv->plat->use_phy_wol; 6794 priv->hw->pmt = priv->plat->pmt; 6795 if (priv->dma_cap.hash_tb_sz) { 6796 priv->hw->multicast_filter_bins = 6797 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6798 priv->hw->mcast_bits_log2 = 6799 ilog2(priv->hw->multicast_filter_bins); 6800 } 6801 6802 /* TXCOE doesn't work in thresh DMA mode */ 6803 if (priv->plat->force_thresh_dma_mode) 6804 priv->plat->tx_coe = 0; 6805 else 6806 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6807 6808 /* In case of GMAC4 rx_coe is from HW cap register. */ 6809 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6810 6811 if (priv->dma_cap.rx_coe_type2) 6812 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6813 else if (priv->dma_cap.rx_coe_type1) 6814 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6815 6816 } else { 6817 dev_info(priv->device, "No HW DMA feature register supported\n"); 6818 } 6819 6820 if (priv->plat->rx_coe) { 6821 priv->hw->rx_csum = priv->plat->rx_coe; 6822 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6823 if (priv->synopsys_id < DWMAC_CORE_4_00) 6824 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6825 } 6826 if (priv->plat->tx_coe) 6827 dev_info(priv->device, "TX Checksum insertion supported\n"); 6828 6829 if (priv->plat->pmt) { 6830 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6831 device_set_wakeup_capable(priv->device, 1); 6832 } 6833 6834 if (priv->dma_cap.tsoen) 6835 dev_info(priv->device, "TSO supported\n"); 6836 6837 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6838 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6839 6840 /* Run HW quirks, if any */ 6841 if (priv->hwif_quirks) { 6842 ret = priv->hwif_quirks(priv); 6843 if (ret) 6844 return ret; 6845 } 6846 6847 /* Rx Watchdog is available in the COREs newer than the 3.40. 6848 * In some case, for example on bugged HW this feature 6849 * has to be disable and this can be done by passing the 6850 * riwt_off field from the platform. 6851 */ 6852 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6853 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6854 priv->use_riwt = 1; 6855 dev_info(priv->device, 6856 "Enable RX Mitigation via HW Watchdog Timer\n"); 6857 } 6858 6859 return 0; 6860 } 6861 6862 static void stmmac_napi_add(struct net_device *dev) 6863 { 6864 struct stmmac_priv *priv = netdev_priv(dev); 6865 u32 queue, maxq; 6866 6867 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6868 6869 for (queue = 0; queue < maxq; queue++) { 6870 struct stmmac_channel *ch = &priv->channel[queue]; 6871 6872 ch->priv_data = priv; 6873 ch->index = queue; 6874 spin_lock_init(&ch->lock); 6875 6876 if (queue < priv->plat->rx_queues_to_use) { 6877 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6878 NAPI_POLL_WEIGHT); 6879 } 6880 if (queue < priv->plat->tx_queues_to_use) { 6881 netif_napi_add_tx(dev, &ch->tx_napi, 6882 stmmac_napi_poll_tx); 6883 } 6884 if (queue < priv->plat->rx_queues_to_use && 6885 queue < priv->plat->tx_queues_to_use) { 6886 netif_napi_add(dev, &ch->rxtx_napi, 6887 stmmac_napi_poll_rxtx, 6888 NAPI_POLL_WEIGHT); 6889 } 6890 } 6891 } 6892 6893 static void stmmac_napi_del(struct net_device *dev) 6894 { 6895 struct stmmac_priv *priv = netdev_priv(dev); 6896 u32 queue, maxq; 6897 6898 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6899 6900 for (queue = 0; queue < maxq; queue++) { 6901 struct stmmac_channel *ch = &priv->channel[queue]; 6902 6903 if (queue < priv->plat->rx_queues_to_use) 6904 netif_napi_del(&ch->rx_napi); 6905 if (queue < priv->plat->tx_queues_to_use) 6906 netif_napi_del(&ch->tx_napi); 6907 if (queue < priv->plat->rx_queues_to_use && 6908 queue < priv->plat->tx_queues_to_use) { 6909 netif_napi_del(&ch->rxtx_napi); 6910 } 6911 } 6912 } 6913 6914 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6915 { 6916 struct stmmac_priv *priv = netdev_priv(dev); 6917 int ret = 0; 6918 6919 if (netif_running(dev)) 6920 stmmac_release(dev); 6921 6922 stmmac_napi_del(dev); 6923 6924 priv->plat->rx_queues_to_use = rx_cnt; 6925 priv->plat->tx_queues_to_use = tx_cnt; 6926 6927 stmmac_napi_add(dev); 6928 6929 if (netif_running(dev)) 6930 ret = stmmac_open(dev); 6931 6932 return ret; 6933 } 6934 6935 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6936 { 6937 struct stmmac_priv *priv = netdev_priv(dev); 6938 int ret = 0; 6939 6940 if (netif_running(dev)) 6941 stmmac_release(dev); 6942 6943 priv->dma_conf.dma_rx_size = rx_size; 6944 priv->dma_conf.dma_tx_size = tx_size; 6945 6946 if (netif_running(dev)) 6947 ret = stmmac_open(dev); 6948 6949 return ret; 6950 } 6951 6952 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6953 static void stmmac_fpe_lp_task(struct work_struct *work) 6954 { 6955 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6956 fpe_task); 6957 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6958 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6959 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6960 bool *hs_enable = &fpe_cfg->hs_enable; 6961 bool *enable = &fpe_cfg->enable; 6962 int retries = 20; 6963 6964 while (retries-- > 0) { 6965 /* Bail out immediately if FPE handshake is OFF */ 6966 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6967 break; 6968 6969 if (*lo_state == FPE_STATE_ENTERING_ON && 6970 *lp_state == FPE_STATE_ENTERING_ON) { 6971 stmmac_fpe_configure(priv, priv->ioaddr, 6972 priv->plat->tx_queues_to_use, 6973 priv->plat->rx_queues_to_use, 6974 *enable); 6975 6976 netdev_info(priv->dev, "configured FPE\n"); 6977 6978 *lo_state = FPE_STATE_ON; 6979 *lp_state = FPE_STATE_ON; 6980 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6981 break; 6982 } 6983 6984 if ((*lo_state == FPE_STATE_CAPABLE || 6985 *lo_state == FPE_STATE_ENTERING_ON) && 6986 *lp_state != FPE_STATE_ON) { 6987 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6988 *lo_state, *lp_state); 6989 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6990 MPACKET_VERIFY); 6991 } 6992 /* Sleep then retry */ 6993 msleep(500); 6994 } 6995 6996 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6997 } 6998 6999 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7000 { 7001 if (priv->plat->fpe_cfg->hs_enable != enable) { 7002 if (enable) { 7003 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7004 MPACKET_VERIFY); 7005 } else { 7006 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7007 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7008 } 7009 7010 priv->plat->fpe_cfg->hs_enable = enable; 7011 } 7012 } 7013 7014 /** 7015 * stmmac_dvr_probe 7016 * @device: device pointer 7017 * @plat_dat: platform data pointer 7018 * @res: stmmac resource pointer 7019 * Description: this is the main probe function used to 7020 * call the alloc_etherdev, allocate the priv structure. 7021 * Return: 7022 * returns 0 on success, otherwise errno. 7023 */ 7024 int stmmac_dvr_probe(struct device *device, 7025 struct plat_stmmacenet_data *plat_dat, 7026 struct stmmac_resources *res) 7027 { 7028 struct net_device *ndev = NULL; 7029 struct stmmac_priv *priv; 7030 u32 rxq; 7031 int i, ret = 0; 7032 7033 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7034 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7035 if (!ndev) 7036 return -ENOMEM; 7037 7038 SET_NETDEV_DEV(ndev, device); 7039 7040 priv = netdev_priv(ndev); 7041 priv->device = device; 7042 priv->dev = ndev; 7043 7044 stmmac_set_ethtool_ops(ndev); 7045 priv->pause = pause; 7046 priv->plat = plat_dat; 7047 priv->ioaddr = res->addr; 7048 priv->dev->base_addr = (unsigned long)res->addr; 7049 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 7050 7051 priv->dev->irq = res->irq; 7052 priv->wol_irq = res->wol_irq; 7053 priv->lpi_irq = res->lpi_irq; 7054 priv->sfty_ce_irq = res->sfty_ce_irq; 7055 priv->sfty_ue_irq = res->sfty_ue_irq; 7056 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7057 priv->rx_irq[i] = res->rx_irq[i]; 7058 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7059 priv->tx_irq[i] = res->tx_irq[i]; 7060 7061 if (!is_zero_ether_addr(res->mac)) 7062 eth_hw_addr_set(priv->dev, res->mac); 7063 7064 dev_set_drvdata(device, priv->dev); 7065 7066 /* Verify driver arguments */ 7067 stmmac_verify_args(); 7068 7069 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7070 if (!priv->af_xdp_zc_qps) 7071 return -ENOMEM; 7072 7073 /* Allocate workqueue */ 7074 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7075 if (!priv->wq) { 7076 dev_err(priv->device, "failed to create workqueue\n"); 7077 return -ENOMEM; 7078 } 7079 7080 INIT_WORK(&priv->service_task, stmmac_service_task); 7081 7082 /* Initialize Link Partner FPE workqueue */ 7083 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7084 7085 /* Override with kernel parameters if supplied XXX CRS XXX 7086 * this needs to have multiple instances 7087 */ 7088 if ((phyaddr >= 0) && (phyaddr <= 31)) 7089 priv->plat->phy_addr = phyaddr; 7090 7091 if (priv->plat->stmmac_rst) { 7092 ret = reset_control_assert(priv->plat->stmmac_rst); 7093 reset_control_deassert(priv->plat->stmmac_rst); 7094 /* Some reset controllers have only reset callback instead of 7095 * assert + deassert callbacks pair. 7096 */ 7097 if (ret == -ENOTSUPP) 7098 reset_control_reset(priv->plat->stmmac_rst); 7099 } 7100 7101 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7102 if (ret == -ENOTSUPP) 7103 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7104 ERR_PTR(ret)); 7105 7106 /* Init MAC and get the capabilities */ 7107 ret = stmmac_hw_init(priv); 7108 if (ret) 7109 goto error_hw_init; 7110 7111 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7112 */ 7113 if (priv->synopsys_id < DWMAC_CORE_5_20) 7114 priv->plat->dma_cfg->dche = false; 7115 7116 stmmac_check_ether_addr(priv); 7117 7118 ndev->netdev_ops = &stmmac_netdev_ops; 7119 7120 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7121 NETIF_F_RXCSUM; 7122 7123 ret = stmmac_tc_init(priv, priv); 7124 if (!ret) { 7125 ndev->hw_features |= NETIF_F_HW_TC; 7126 } 7127 7128 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 7129 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7130 if (priv->plat->has_gmac4) 7131 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7132 priv->tso = true; 7133 dev_info(priv->device, "TSO feature enabled\n"); 7134 } 7135 7136 if (priv->dma_cap.sphen && !priv->plat->sph_disable) { 7137 ndev->hw_features |= NETIF_F_GRO; 7138 priv->sph_cap = true; 7139 priv->sph = priv->sph_cap; 7140 dev_info(priv->device, "SPH feature enabled\n"); 7141 } 7142 7143 /* The current IP register MAC_HW_Feature1[ADDR64] only define 7144 * 32/40/64 bit width, but some SOC support others like i.MX8MP 7145 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 7146 * So overwrite dma_cap.addr64 according to HW real design. 7147 */ 7148 if (priv->plat->addr64) 7149 priv->dma_cap.addr64 = priv->plat->addr64; 7150 7151 if (priv->dma_cap.addr64) { 7152 ret = dma_set_mask_and_coherent(device, 7153 DMA_BIT_MASK(priv->dma_cap.addr64)); 7154 if (!ret) { 7155 dev_info(priv->device, "Using %d bits DMA width\n", 7156 priv->dma_cap.addr64); 7157 7158 /* 7159 * If more than 32 bits can be addressed, make sure to 7160 * enable enhanced addressing mode. 7161 */ 7162 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7163 priv->plat->dma_cfg->eame = true; 7164 } else { 7165 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7166 if (ret) { 7167 dev_err(priv->device, "Failed to set DMA Mask\n"); 7168 goto error_hw_init; 7169 } 7170 7171 priv->dma_cap.addr64 = 32; 7172 } 7173 } 7174 7175 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7176 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7177 #ifdef STMMAC_VLAN_TAG_USED 7178 /* Both mac100 and gmac support receive VLAN tag detection */ 7179 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7180 if (priv->dma_cap.vlhash) { 7181 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7182 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7183 } 7184 if (priv->dma_cap.vlins) { 7185 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7186 if (priv->dma_cap.dvlan) 7187 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7188 } 7189 #endif 7190 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7191 7192 /* Initialize RSS */ 7193 rxq = priv->plat->rx_queues_to_use; 7194 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7195 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7196 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7197 7198 if (priv->dma_cap.rssen && priv->plat->rss_en) 7199 ndev->features |= NETIF_F_RXHASH; 7200 7201 /* MTU range: 46 - hw-specific max */ 7202 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7203 if (priv->plat->has_xgmac) 7204 ndev->max_mtu = XGMAC_JUMBO_LEN; 7205 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7206 ndev->max_mtu = JUMBO_LEN; 7207 else 7208 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7209 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7210 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7211 */ 7212 if ((priv->plat->maxmtu < ndev->max_mtu) && 7213 (priv->plat->maxmtu >= ndev->min_mtu)) 7214 ndev->max_mtu = priv->plat->maxmtu; 7215 else if (priv->plat->maxmtu < ndev->min_mtu) 7216 dev_warn(priv->device, 7217 "%s: warning: maxmtu having invalid value (%d)\n", 7218 __func__, priv->plat->maxmtu); 7219 7220 if (flow_ctrl) 7221 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7222 7223 /* Setup channels NAPI */ 7224 stmmac_napi_add(ndev); 7225 7226 mutex_init(&priv->lock); 7227 7228 /* If a specific clk_csr value is passed from the platform 7229 * this means that the CSR Clock Range selection cannot be 7230 * changed at run-time and it is fixed. Viceversa the driver'll try to 7231 * set the MDC clock dynamically according to the csr actual 7232 * clock input. 7233 */ 7234 if (priv->plat->clk_csr >= 0) 7235 priv->clk_csr = priv->plat->clk_csr; 7236 else 7237 stmmac_clk_csr_set(priv); 7238 7239 stmmac_check_pcs_mode(priv); 7240 7241 pm_runtime_get_noresume(device); 7242 pm_runtime_set_active(device); 7243 if (!pm_runtime_enabled(device)) 7244 pm_runtime_enable(device); 7245 7246 if (priv->hw->pcs != STMMAC_PCS_TBI && 7247 priv->hw->pcs != STMMAC_PCS_RTBI) { 7248 /* MDIO bus Registration */ 7249 ret = stmmac_mdio_register(ndev); 7250 if (ret < 0) { 7251 dev_err_probe(priv->device, ret, 7252 "%s: MDIO bus (id: %d) registration failed\n", 7253 __func__, priv->plat->bus_id); 7254 goto error_mdio_register; 7255 } 7256 } 7257 7258 if (priv->plat->speed_mode_2500) 7259 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7260 7261 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7262 ret = stmmac_xpcs_setup(priv->mii); 7263 if (ret) 7264 goto error_xpcs_setup; 7265 } 7266 7267 ret = stmmac_phy_setup(priv); 7268 if (ret) { 7269 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7270 goto error_phy_setup; 7271 } 7272 7273 ret = register_netdev(ndev); 7274 if (ret) { 7275 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7276 __func__, ret); 7277 goto error_netdev_register; 7278 } 7279 7280 if (priv->plat->serdes_powerup) { 7281 ret = priv->plat->serdes_powerup(ndev, 7282 priv->plat->bsp_priv); 7283 7284 if (ret < 0) 7285 goto error_serdes_powerup; 7286 } 7287 7288 #ifdef CONFIG_DEBUG_FS 7289 stmmac_init_fs(ndev); 7290 #endif 7291 7292 if (priv->plat->dump_debug_regs) 7293 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7294 7295 /* Let pm_runtime_put() disable the clocks. 7296 * If CONFIG_PM is not enabled, the clocks will stay powered. 7297 */ 7298 pm_runtime_put(device); 7299 7300 return ret; 7301 7302 error_serdes_powerup: 7303 unregister_netdev(ndev); 7304 error_netdev_register: 7305 phylink_destroy(priv->phylink); 7306 error_xpcs_setup: 7307 error_phy_setup: 7308 if (priv->hw->pcs != STMMAC_PCS_TBI && 7309 priv->hw->pcs != STMMAC_PCS_RTBI) 7310 stmmac_mdio_unregister(ndev); 7311 error_mdio_register: 7312 stmmac_napi_del(ndev); 7313 error_hw_init: 7314 destroy_workqueue(priv->wq); 7315 bitmap_free(priv->af_xdp_zc_qps); 7316 7317 return ret; 7318 } 7319 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7320 7321 /** 7322 * stmmac_dvr_remove 7323 * @dev: device pointer 7324 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7325 * changes the link status, releases the DMA descriptor rings. 7326 */ 7327 int stmmac_dvr_remove(struct device *dev) 7328 { 7329 struct net_device *ndev = dev_get_drvdata(dev); 7330 struct stmmac_priv *priv = netdev_priv(ndev); 7331 7332 netdev_info(priv->dev, "%s: removing driver", __func__); 7333 7334 pm_runtime_get_sync(dev); 7335 7336 stmmac_stop_all_dma(priv); 7337 stmmac_mac_set(priv, priv->ioaddr, false); 7338 netif_carrier_off(ndev); 7339 unregister_netdev(ndev); 7340 7341 /* Serdes power down needs to happen after VLAN filter 7342 * is deleted that is triggered by unregister_netdev(). 7343 */ 7344 if (priv->plat->serdes_powerdown) 7345 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7346 7347 #ifdef CONFIG_DEBUG_FS 7348 stmmac_exit_fs(ndev); 7349 #endif 7350 phylink_destroy(priv->phylink); 7351 if (priv->plat->stmmac_rst) 7352 reset_control_assert(priv->plat->stmmac_rst); 7353 reset_control_assert(priv->plat->stmmac_ahb_rst); 7354 if (priv->hw->pcs != STMMAC_PCS_TBI && 7355 priv->hw->pcs != STMMAC_PCS_RTBI) 7356 stmmac_mdio_unregister(ndev); 7357 destroy_workqueue(priv->wq); 7358 mutex_destroy(&priv->lock); 7359 bitmap_free(priv->af_xdp_zc_qps); 7360 7361 pm_runtime_disable(dev); 7362 pm_runtime_put_noidle(dev); 7363 7364 return 0; 7365 } 7366 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7367 7368 /** 7369 * stmmac_suspend - suspend callback 7370 * @dev: device pointer 7371 * Description: this is the function to suspend the device and it is called 7372 * by the platform driver to stop the network queue, release the resources, 7373 * program the PMT register (for WoL), clean and release driver resources. 7374 */ 7375 int stmmac_suspend(struct device *dev) 7376 { 7377 struct net_device *ndev = dev_get_drvdata(dev); 7378 struct stmmac_priv *priv = netdev_priv(ndev); 7379 u32 chan; 7380 7381 if (!ndev || !netif_running(ndev)) 7382 return 0; 7383 7384 mutex_lock(&priv->lock); 7385 7386 netif_device_detach(ndev); 7387 7388 stmmac_disable_all_queues(priv); 7389 7390 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7391 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7392 7393 if (priv->eee_enabled) { 7394 priv->tx_path_in_lpi_mode = false; 7395 del_timer_sync(&priv->eee_ctrl_timer); 7396 } 7397 7398 /* Stop TX/RX DMA */ 7399 stmmac_stop_all_dma(priv); 7400 7401 if (priv->plat->serdes_powerdown) 7402 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7403 7404 /* Enable Power down mode by programming the PMT regs */ 7405 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7406 stmmac_pmt(priv, priv->hw, priv->wolopts); 7407 priv->irq_wake = 1; 7408 } else { 7409 stmmac_mac_set(priv, priv->ioaddr, false); 7410 pinctrl_pm_select_sleep_state(priv->device); 7411 } 7412 7413 mutex_unlock(&priv->lock); 7414 7415 rtnl_lock(); 7416 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7417 phylink_suspend(priv->phylink, true); 7418 } else { 7419 if (device_may_wakeup(priv->device)) 7420 phylink_speed_down(priv->phylink, false); 7421 phylink_suspend(priv->phylink, false); 7422 } 7423 rtnl_unlock(); 7424 7425 if (priv->dma_cap.fpesel) { 7426 /* Disable FPE */ 7427 stmmac_fpe_configure(priv, priv->ioaddr, 7428 priv->plat->tx_queues_to_use, 7429 priv->plat->rx_queues_to_use, false); 7430 7431 stmmac_fpe_handshake(priv, false); 7432 stmmac_fpe_stop_wq(priv); 7433 } 7434 7435 priv->speed = SPEED_UNKNOWN; 7436 return 0; 7437 } 7438 EXPORT_SYMBOL_GPL(stmmac_suspend); 7439 7440 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7441 { 7442 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7443 7444 rx_q->cur_rx = 0; 7445 rx_q->dirty_rx = 0; 7446 } 7447 7448 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7449 { 7450 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7451 7452 tx_q->cur_tx = 0; 7453 tx_q->dirty_tx = 0; 7454 tx_q->mss = 0; 7455 7456 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7457 } 7458 7459 /** 7460 * stmmac_reset_queues_param - reset queue parameters 7461 * @priv: device pointer 7462 */ 7463 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7464 { 7465 u32 rx_cnt = priv->plat->rx_queues_to_use; 7466 u32 tx_cnt = priv->plat->tx_queues_to_use; 7467 u32 queue; 7468 7469 for (queue = 0; queue < rx_cnt; queue++) 7470 stmmac_reset_rx_queue(priv, queue); 7471 7472 for (queue = 0; queue < tx_cnt; queue++) 7473 stmmac_reset_tx_queue(priv, queue); 7474 } 7475 7476 /** 7477 * stmmac_resume - resume callback 7478 * @dev: device pointer 7479 * Description: when resume this function is invoked to setup the DMA and CORE 7480 * in a usable state. 7481 */ 7482 int stmmac_resume(struct device *dev) 7483 { 7484 struct net_device *ndev = dev_get_drvdata(dev); 7485 struct stmmac_priv *priv = netdev_priv(ndev); 7486 int ret; 7487 7488 if (!netif_running(ndev)) 7489 return 0; 7490 7491 /* Power Down bit, into the PM register, is cleared 7492 * automatically as soon as a magic packet or a Wake-up frame 7493 * is received. Anyway, it's better to manually clear 7494 * this bit because it can generate problems while resuming 7495 * from another devices (e.g. serial console). 7496 */ 7497 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7498 mutex_lock(&priv->lock); 7499 stmmac_pmt(priv, priv->hw, 0); 7500 mutex_unlock(&priv->lock); 7501 priv->irq_wake = 0; 7502 } else { 7503 pinctrl_pm_select_default_state(priv->device); 7504 /* reset the phy so that it's ready */ 7505 if (priv->mii) 7506 stmmac_mdio_reset(priv->mii); 7507 } 7508 7509 if (priv->plat->serdes_powerup) { 7510 ret = priv->plat->serdes_powerup(ndev, 7511 priv->plat->bsp_priv); 7512 7513 if (ret < 0) 7514 return ret; 7515 } 7516 7517 rtnl_lock(); 7518 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7519 phylink_resume(priv->phylink); 7520 } else { 7521 phylink_resume(priv->phylink); 7522 if (device_may_wakeup(priv->device)) 7523 phylink_speed_up(priv->phylink); 7524 } 7525 rtnl_unlock(); 7526 7527 rtnl_lock(); 7528 mutex_lock(&priv->lock); 7529 7530 stmmac_reset_queues_param(priv); 7531 7532 stmmac_free_tx_skbufs(priv); 7533 stmmac_clear_descriptors(priv, &priv->dma_conf); 7534 7535 stmmac_hw_setup(ndev, false); 7536 stmmac_init_coalesce(priv); 7537 stmmac_set_rx_mode(ndev); 7538 7539 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7540 7541 stmmac_enable_all_queues(priv); 7542 stmmac_enable_all_dma_irq(priv); 7543 7544 mutex_unlock(&priv->lock); 7545 rtnl_unlock(); 7546 7547 netif_device_attach(ndev); 7548 7549 return 0; 7550 } 7551 EXPORT_SYMBOL_GPL(stmmac_resume); 7552 7553 #ifndef MODULE 7554 static int __init stmmac_cmdline_opt(char *str) 7555 { 7556 char *opt; 7557 7558 if (!str || !*str) 7559 return 1; 7560 while ((opt = strsep(&str, ",")) != NULL) { 7561 if (!strncmp(opt, "debug:", 6)) { 7562 if (kstrtoint(opt + 6, 0, &debug)) 7563 goto err; 7564 } else if (!strncmp(opt, "phyaddr:", 8)) { 7565 if (kstrtoint(opt + 8, 0, &phyaddr)) 7566 goto err; 7567 } else if (!strncmp(opt, "buf_sz:", 7)) { 7568 if (kstrtoint(opt + 7, 0, &buf_sz)) 7569 goto err; 7570 } else if (!strncmp(opt, "tc:", 3)) { 7571 if (kstrtoint(opt + 3, 0, &tc)) 7572 goto err; 7573 } else if (!strncmp(opt, "watchdog:", 9)) { 7574 if (kstrtoint(opt + 9, 0, &watchdog)) 7575 goto err; 7576 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7577 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7578 goto err; 7579 } else if (!strncmp(opt, "pause:", 6)) { 7580 if (kstrtoint(opt + 6, 0, &pause)) 7581 goto err; 7582 } else if (!strncmp(opt, "eee_timer:", 10)) { 7583 if (kstrtoint(opt + 10, 0, &eee_timer)) 7584 goto err; 7585 } else if (!strncmp(opt, "chain_mode:", 11)) { 7586 if (kstrtoint(opt + 11, 0, &chain_mode)) 7587 goto err; 7588 } 7589 } 7590 return 1; 7591 7592 err: 7593 pr_err("%s: ERROR broken module parameter conversion", __func__); 7594 return 1; 7595 } 7596 7597 __setup("stmmaceth=", stmmac_cmdline_opt); 7598 #endif /* MODULE */ 7599 7600 static int __init stmmac_init(void) 7601 { 7602 #ifdef CONFIG_DEBUG_FS 7603 /* Create debugfs main directory if it doesn't exist yet */ 7604 if (!stmmac_fs_dir) 7605 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7606 register_netdevice_notifier(&stmmac_notifier); 7607 #endif 7608 7609 return 0; 7610 } 7611 7612 static void __exit stmmac_exit(void) 7613 { 7614 #ifdef CONFIG_DEBUG_FS 7615 unregister_netdevice_notifier(&stmmac_notifier); 7616 debugfs_remove_recursive(stmmac_fs_dir); 7617 #endif 7618 } 7619 7620 module_init(stmmac_init) 7621 module_exit(stmmac_exit) 7622 7623 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7624 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7625 MODULE_LICENSE("GPL"); 7626