1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_STMMAC_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_STMMAC_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 57 58 /* Module parameters */ 59 #define TX_TIMEO 5000 60 static int watchdog = TX_TIMEO; 61 module_param(watchdog, int, S_IRUGO | S_IWUSR); 62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 63 64 static int debug = -1; 65 module_param(debug, int, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 67 68 static int phyaddr = -1; 69 module_param(phyaddr, int, S_IRUGO); 70 MODULE_PARM_DESC(phyaddr, "Physical device address"); 71 72 #define DMA_TX_SIZE 256 73 static int dma_txsize = DMA_TX_SIZE; 74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 76 77 #define DMA_RX_SIZE 256 78 static int dma_rxsize = DMA_RX_SIZE; 79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 81 82 static int flow_ctrl = FLOW_OFF; 83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 85 86 static int pause = PAUSE_TIME; 87 module_param(pause, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 89 90 #define TC_DEFAULT 64 91 static int tc = TC_DEFAULT; 92 module_param(tc, int, S_IRUGO | S_IWUSR); 93 MODULE_PARM_DESC(tc, "DMA threshold control value"); 94 95 #define DMA_BUFFER_SIZE BUF_SIZE_4KiB 96 static int buf_sz = DMA_BUFFER_SIZE; 97 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 99 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 101 NETIF_MSG_LINK | NETIF_MSG_IFUP | 102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 103 104 #define STMMAC_DEFAULT_LPI_TIMER 1000 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 109 110 /* By default the driver will use the ring mode to manage tx and rx descriptors 111 * but passing this value so user can force to use the chain instead of the ring 112 */ 113 static unsigned int chain_mode; 114 module_param(chain_mode, int, S_IRUGO); 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 116 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 118 119 #ifdef CONFIG_STMMAC_DEBUG_FS 120 static int stmmac_init_fs(struct net_device *dev); 121 static void stmmac_exit_fs(void); 122 #endif 123 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 125 126 /** 127 * stmmac_verify_args - verify the driver parameters. 128 * Description: it verifies if some wrong parameter is passed to the driver. 129 * Note that wrong parameters are replaced with the default values. 130 */ 131 static void stmmac_verify_args(void) 132 { 133 if (unlikely(watchdog < 0)) 134 watchdog = TX_TIMEO; 135 if (unlikely(dma_rxsize < 0)) 136 dma_rxsize = DMA_RX_SIZE; 137 if (unlikely(dma_txsize < 0)) 138 dma_txsize = DMA_TX_SIZE; 139 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 140 buf_sz = DMA_BUFFER_SIZE; 141 if (unlikely(flow_ctrl > 1)) 142 flow_ctrl = FLOW_AUTO; 143 else if (likely(flow_ctrl < 0)) 144 flow_ctrl = FLOW_OFF; 145 if (unlikely((pause < 0) || (pause > 0xffff))) 146 pause = PAUSE_TIME; 147 if (eee_timer < 0) 148 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 149 } 150 151 /** 152 * stmmac_clk_csr_set - dynamically set the MDC clock 153 * @priv: driver private structure 154 * Description: this is to dynamically set the MDC clock according to the csr 155 * clock input. 156 * Note: 157 * If a specific clk_csr value is passed from the platform 158 * this means that the CSR Clock Range selection cannot be 159 * changed at run-time and it is fixed (as reported in the driver 160 * documentation). Viceversa the driver will try to set the MDC 161 * clock dynamically according to the actual clock input. 162 */ 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 164 { 165 u32 clk_rate; 166 167 clk_rate = clk_get_rate(priv->stmmac_clk); 168 169 /* Platform provided default clk_csr would be assumed valid 170 * for all other cases except for the below mentioned ones. 171 * For values higher than the IEEE 802.3 specified frequency 172 * we can not estimate the proper divider as it is not known 173 * the frequency of clk_csr_i. So we do not change the default 174 * divider. 175 */ 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 177 if (clk_rate < CSR_F_35M) 178 priv->clk_csr = STMMAC_CSR_20_35M; 179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 180 priv->clk_csr = STMMAC_CSR_35_60M; 181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 182 priv->clk_csr = STMMAC_CSR_60_100M; 183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 184 priv->clk_csr = STMMAC_CSR_100_150M; 185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 186 priv->clk_csr = STMMAC_CSR_150_250M; 187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 188 priv->clk_csr = STMMAC_CSR_250_300M; 189 } 190 } 191 192 static void print_pkt(unsigned char *buf, int len) 193 { 194 int j; 195 pr_debug("len = %d byte, buf addr: 0x%p", len, buf); 196 for (j = 0; j < len; j++) { 197 if ((j % 16) == 0) 198 pr_debug("\n %03x:", j); 199 pr_debug(" %02x", buf[j]); 200 } 201 pr_debug("\n"); 202 } 203 204 /* minimum number of free TX descriptors required to wake up TX process */ 205 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 206 207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 208 { 209 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 210 } 211 212 /** 213 * stmmac_hw_fix_mac_speed: callback for speed selection 214 * @priv: driver private structure 215 * Description: on some platforms (e.g. ST), some HW system configuraton 216 * registers have to be set according to the link speed negotiated. 217 */ 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 219 { 220 struct phy_device *phydev = priv->phydev; 221 222 if (likely(priv->plat->fix_mac_speed)) 223 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 224 } 225 226 /** 227 * stmmac_enable_eee_mode: Check and enter in LPI mode 228 * @priv: driver private structure 229 * Description: this function is to verify and enter in LPI mode for EEE. 230 */ 231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 232 { 233 /* Check and enter in LPI mode */ 234 if ((priv->dirty_tx == priv->cur_tx) && 235 (priv->tx_path_in_lpi_mode == false)) 236 priv->hw->mac->set_eee_mode(priv->ioaddr); 237 } 238 239 /** 240 * stmmac_disable_eee_mode: disable/exit from EEE 241 * @priv: driver private structure 242 * Description: this function is to exit and disable EEE in case of 243 * LPI state is true. This is called by the xmit. 244 */ 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 246 { 247 priv->hw->mac->reset_eee_mode(priv->ioaddr); 248 del_timer_sync(&priv->eee_ctrl_timer); 249 priv->tx_path_in_lpi_mode = false; 250 } 251 252 /** 253 * stmmac_eee_ctrl_timer: EEE TX SW timer. 254 * @arg : data hook 255 * Description: 256 * if there is no data transfer and if we are not in LPI state, 257 * then MAC Transmitter can be moved to LPI state. 258 */ 259 static void stmmac_eee_ctrl_timer(unsigned long arg) 260 { 261 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 262 263 stmmac_enable_eee_mode(priv); 264 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 265 } 266 267 /** 268 * stmmac_eee_init: init EEE 269 * @priv: driver private structure 270 * Description: 271 * If the EEE support has been enabled while configuring the driver, 272 * if the GMAC actually supports the EEE (from the HW cap reg) and the 273 * phy can also manage EEE, so enable the LPI state and start the timer 274 * to verify if the tx path can enter in LPI state. 275 */ 276 bool stmmac_eee_init(struct stmmac_priv *priv) 277 { 278 bool ret = false; 279 280 /* Using PCS we cannot dial with the phy registers at this stage 281 * so we do not support extra feature like EEE. 282 */ 283 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 284 (priv->pcs == STMMAC_PCS_RTBI)) 285 goto out; 286 287 /* MAC core supports the EEE feature. */ 288 if (priv->dma_cap.eee) { 289 /* Check if the PHY supports EEE */ 290 if (phy_init_eee(priv->phydev, 1)) 291 goto out; 292 293 if (!priv->eee_active) { 294 priv->eee_active = 1; 295 init_timer(&priv->eee_ctrl_timer); 296 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 297 priv->eee_ctrl_timer.data = (unsigned long)priv; 298 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); 299 add_timer(&priv->eee_ctrl_timer); 300 301 priv->hw->mac->set_eee_timer(priv->ioaddr, 302 STMMAC_DEFAULT_LIT_LS, 303 priv->tx_lpi_timer); 304 } else 305 /* Set HW EEE according to the speed */ 306 priv->hw->mac->set_eee_pls(priv->ioaddr, 307 priv->phydev->link); 308 309 pr_info("stmmac: Energy-Efficient Ethernet initialized\n"); 310 311 ret = true; 312 } 313 out: 314 return ret; 315 } 316 317 /* stmmac_get_tx_hwtstamp: get HW TX timestamps 318 * @priv: driver private structure 319 * @entry : descriptor index to be used. 320 * @skb : the socket buffer 321 * Description : 322 * This function will read timestamp from the descriptor & pass it to stack. 323 * and also perform some sanity checks. 324 */ 325 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 326 unsigned int entry, struct sk_buff *skb) 327 { 328 struct skb_shared_hwtstamps shhwtstamp; 329 u64 ns; 330 void *desc = NULL; 331 332 if (!priv->hwts_tx_en) 333 return; 334 335 /* exit if skb doesn't support hw tstamp */ 336 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 337 return; 338 339 if (priv->adv_ts) 340 desc = (priv->dma_etx + entry); 341 else 342 desc = (priv->dma_tx + entry); 343 344 /* check tx tstamp status */ 345 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 346 return; 347 348 /* get the valid tstamp */ 349 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 350 351 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 352 shhwtstamp.hwtstamp = ns_to_ktime(ns); 353 /* pass tstamp to stack */ 354 skb_tstamp_tx(skb, &shhwtstamp); 355 356 return; 357 } 358 359 /* stmmac_get_rx_hwtstamp: get HW RX timestamps 360 * @priv: driver private structure 361 * @entry : descriptor index to be used. 362 * @skb : the socket buffer 363 * Description : 364 * This function will read received packet's timestamp from the descriptor 365 * and pass it to stack. It also perform some sanity checks. 366 */ 367 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 368 unsigned int entry, struct sk_buff *skb) 369 { 370 struct skb_shared_hwtstamps *shhwtstamp = NULL; 371 u64 ns; 372 void *desc = NULL; 373 374 if (!priv->hwts_rx_en) 375 return; 376 377 if (priv->adv_ts) 378 desc = (priv->dma_erx + entry); 379 else 380 desc = (priv->dma_rx + entry); 381 382 /* exit if rx tstamp is not valid */ 383 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 384 return; 385 386 /* get valid tstamp */ 387 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 388 shhwtstamp = skb_hwtstamps(skb); 389 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 390 shhwtstamp->hwtstamp = ns_to_ktime(ns); 391 } 392 393 /** 394 * stmmac_hwtstamp_ioctl - control hardware timestamping. 395 * @dev: device pointer. 396 * @ifr: An IOCTL specefic structure, that can contain a pointer to 397 * a proprietary structure used to pass information to the driver. 398 * Description: 399 * This function configures the MAC to enable/disable both outgoing(TX) 400 * and incoming(RX) packets time stamping based on user input. 401 * Return Value: 402 * 0 on success and an appropriate -ve integer on failure. 403 */ 404 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 405 { 406 struct stmmac_priv *priv = netdev_priv(dev); 407 struct hwtstamp_config config; 408 struct timespec now; 409 u64 temp = 0; 410 u32 ptp_v2 = 0; 411 u32 tstamp_all = 0; 412 u32 ptp_over_ipv4_udp = 0; 413 u32 ptp_over_ipv6_udp = 0; 414 u32 ptp_over_ethernet = 0; 415 u32 snap_type_sel = 0; 416 u32 ts_master_en = 0; 417 u32 ts_event_en = 0; 418 u32 value = 0; 419 420 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 421 netdev_alert(priv->dev, "No support for HW time stamping\n"); 422 priv->hwts_tx_en = 0; 423 priv->hwts_rx_en = 0; 424 425 return -EOPNOTSUPP; 426 } 427 428 if (copy_from_user(&config, ifr->ifr_data, 429 sizeof(struct hwtstamp_config))) 430 return -EFAULT; 431 432 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 433 __func__, config.flags, config.tx_type, config.rx_filter); 434 435 /* reserved for future extensions */ 436 if (config.flags) 437 return -EINVAL; 438 439 if (config.tx_type != HWTSTAMP_TX_OFF && 440 config.tx_type != HWTSTAMP_TX_ON) 441 return -ERANGE; 442 443 if (priv->adv_ts) { 444 switch (config.rx_filter) { 445 case HWTSTAMP_FILTER_NONE: 446 /* time stamp no incoming packet at all */ 447 config.rx_filter = HWTSTAMP_FILTER_NONE; 448 break; 449 450 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 451 /* PTP v1, UDP, any kind of event packet */ 452 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 453 /* take time stamp for all event messages */ 454 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 455 456 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 457 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 458 break; 459 460 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 461 /* PTP v1, UDP, Sync packet */ 462 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 463 /* take time stamp for SYNC messages only */ 464 ts_event_en = PTP_TCR_TSEVNTENA; 465 466 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 467 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 468 break; 469 470 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 471 /* PTP v1, UDP, Delay_req packet */ 472 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 473 /* take time stamp for Delay_Req messages only */ 474 ts_master_en = PTP_TCR_TSMSTRENA; 475 ts_event_en = PTP_TCR_TSEVNTENA; 476 477 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 478 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 479 break; 480 481 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 482 /* PTP v2, UDP, any kind of event packet */ 483 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 484 ptp_v2 = PTP_TCR_TSVER2ENA; 485 /* take time stamp for all event messages */ 486 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 487 488 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 489 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 490 break; 491 492 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 493 /* PTP v2, UDP, Sync packet */ 494 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 495 ptp_v2 = PTP_TCR_TSVER2ENA; 496 /* take time stamp for SYNC messages only */ 497 ts_event_en = PTP_TCR_TSEVNTENA; 498 499 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 500 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 501 break; 502 503 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 504 /* PTP v2, UDP, Delay_req packet */ 505 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 506 ptp_v2 = PTP_TCR_TSVER2ENA; 507 /* take time stamp for Delay_Req messages only */ 508 ts_master_en = PTP_TCR_TSMSTRENA; 509 ts_event_en = PTP_TCR_TSEVNTENA; 510 511 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 512 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 513 break; 514 515 case HWTSTAMP_FILTER_PTP_V2_EVENT: 516 /* PTP v2/802.AS1 any layer, any kind of event packet */ 517 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 518 ptp_v2 = PTP_TCR_TSVER2ENA; 519 /* take time stamp for all event messages */ 520 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 521 522 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 523 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 524 ptp_over_ethernet = PTP_TCR_TSIPENA; 525 break; 526 527 case HWTSTAMP_FILTER_PTP_V2_SYNC: 528 /* PTP v2/802.AS1, any layer, Sync packet */ 529 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 530 ptp_v2 = PTP_TCR_TSVER2ENA; 531 /* take time stamp for SYNC messages only */ 532 ts_event_en = PTP_TCR_TSEVNTENA; 533 534 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 535 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 536 ptp_over_ethernet = PTP_TCR_TSIPENA; 537 break; 538 539 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 540 /* PTP v2/802.AS1, any layer, Delay_req packet */ 541 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 542 ptp_v2 = PTP_TCR_TSVER2ENA; 543 /* take time stamp for Delay_Req messages only */ 544 ts_master_en = PTP_TCR_TSMSTRENA; 545 ts_event_en = PTP_TCR_TSEVNTENA; 546 547 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 548 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 549 ptp_over_ethernet = PTP_TCR_TSIPENA; 550 break; 551 552 case HWTSTAMP_FILTER_ALL: 553 /* time stamp any incoming packet */ 554 config.rx_filter = HWTSTAMP_FILTER_ALL; 555 tstamp_all = PTP_TCR_TSENALL; 556 break; 557 558 default: 559 return -ERANGE; 560 } 561 } else { 562 switch (config.rx_filter) { 563 case HWTSTAMP_FILTER_NONE: 564 config.rx_filter = HWTSTAMP_FILTER_NONE; 565 break; 566 default: 567 /* PTP v1, UDP, any kind of event packet */ 568 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 569 break; 570 } 571 } 572 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 573 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 574 575 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 576 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 577 else { 578 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 579 tstamp_all | ptp_v2 | ptp_over_ethernet | 580 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 581 ts_master_en | snap_type_sel); 582 583 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 584 585 /* program Sub Second Increment reg */ 586 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 587 588 /* calculate default added value: 589 * formula is : 590 * addend = (2^32)/freq_div_ratio; 591 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz 592 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK; 593 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to 594 * achive 20ns accuracy. 595 * 596 * 2^x * y == (y << x), hence 597 * 2^32 * 50000000 ==> (50000000 << 32) 598 */ 599 temp = (u64) (50000000ULL << 32); 600 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK); 601 priv->hw->ptp->config_addend(priv->ioaddr, 602 priv->default_addend); 603 604 /* initialize system time */ 605 getnstimeofday(&now); 606 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 607 now.tv_nsec); 608 } 609 610 return copy_to_user(ifr->ifr_data, &config, 611 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 612 } 613 614 /** 615 * stmmac_init_ptp: init PTP 616 * @priv: driver private structure 617 * Description: this is to verify if the HW supports the PTPv1 or v2. 618 * This is done by looking at the HW cap. register. 619 * Also it registers the ptp driver. 620 */ 621 static int stmmac_init_ptp(struct stmmac_priv *priv) 622 { 623 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 624 return -EOPNOTSUPP; 625 626 priv->adv_ts = 0; 627 if (priv->dma_cap.atime_stamp && priv->extend_desc) 628 priv->adv_ts = 1; 629 630 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 631 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 632 633 if (netif_msg_hw(priv) && priv->adv_ts) 634 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 635 636 priv->hw->ptp = &stmmac_ptp; 637 priv->hwts_tx_en = 0; 638 priv->hwts_rx_en = 0; 639 640 return stmmac_ptp_register(priv); 641 } 642 643 static void stmmac_release_ptp(struct stmmac_priv *priv) 644 { 645 stmmac_ptp_unregister(priv); 646 } 647 648 /** 649 * stmmac_adjust_link 650 * @dev: net device structure 651 * Description: it adjusts the link parameters. 652 */ 653 static void stmmac_adjust_link(struct net_device *dev) 654 { 655 struct stmmac_priv *priv = netdev_priv(dev); 656 struct phy_device *phydev = priv->phydev; 657 unsigned long flags; 658 int new_state = 0; 659 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 660 661 if (phydev == NULL) 662 return; 663 664 spin_lock_irqsave(&priv->lock, flags); 665 666 if (phydev->link) { 667 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 668 669 /* Now we make sure that we can be in full duplex mode. 670 * If not, we operate in half-duplex mode. */ 671 if (phydev->duplex != priv->oldduplex) { 672 new_state = 1; 673 if (!(phydev->duplex)) 674 ctrl &= ~priv->hw->link.duplex; 675 else 676 ctrl |= priv->hw->link.duplex; 677 priv->oldduplex = phydev->duplex; 678 } 679 /* Flow Control operation */ 680 if (phydev->pause) 681 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 682 fc, pause_time); 683 684 if (phydev->speed != priv->speed) { 685 new_state = 1; 686 switch (phydev->speed) { 687 case 1000: 688 if (likely(priv->plat->has_gmac)) 689 ctrl &= ~priv->hw->link.port; 690 stmmac_hw_fix_mac_speed(priv); 691 break; 692 case 100: 693 case 10: 694 if (priv->plat->has_gmac) { 695 ctrl |= priv->hw->link.port; 696 if (phydev->speed == SPEED_100) { 697 ctrl |= priv->hw->link.speed; 698 } else { 699 ctrl &= ~(priv->hw->link.speed); 700 } 701 } else { 702 ctrl &= ~priv->hw->link.port; 703 } 704 stmmac_hw_fix_mac_speed(priv); 705 break; 706 default: 707 if (netif_msg_link(priv)) 708 pr_warn("%s: Speed (%d) not 10/100\n", 709 dev->name, phydev->speed); 710 break; 711 } 712 713 priv->speed = phydev->speed; 714 } 715 716 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 717 718 if (!priv->oldlink) { 719 new_state = 1; 720 priv->oldlink = 1; 721 } 722 } else if (priv->oldlink) { 723 new_state = 1; 724 priv->oldlink = 0; 725 priv->speed = 0; 726 priv->oldduplex = -1; 727 } 728 729 if (new_state && netif_msg_link(priv)) 730 phy_print_status(phydev); 731 732 /* At this stage, it could be needed to setup the EEE or adjust some 733 * MAC related HW registers. 734 */ 735 priv->eee_enabled = stmmac_eee_init(priv); 736 737 spin_unlock_irqrestore(&priv->lock, flags); 738 } 739 740 /** 741 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported 742 * @priv: driver private structure 743 * Description: this is to verify if the HW supports the PCS. 744 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 745 * configured for the TBI, RTBI, or SGMII PHY interface. 746 */ 747 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 748 { 749 int interface = priv->plat->interface; 750 751 if (priv->dma_cap.pcs) { 752 if ((interface == PHY_INTERFACE_MODE_RGMII) || 753 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 754 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 755 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 756 pr_debug("STMMAC: PCS RGMII support enable\n"); 757 priv->pcs = STMMAC_PCS_RGMII; 758 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 759 pr_debug("STMMAC: PCS SGMII support enable\n"); 760 priv->pcs = STMMAC_PCS_SGMII; 761 } 762 } 763 } 764 765 /** 766 * stmmac_init_phy - PHY initialization 767 * @dev: net device structure 768 * Description: it initializes the driver's PHY state, and attaches the PHY 769 * to the mac driver. 770 * Return value: 771 * 0 on success 772 */ 773 static int stmmac_init_phy(struct net_device *dev) 774 { 775 struct stmmac_priv *priv = netdev_priv(dev); 776 struct phy_device *phydev; 777 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 778 char bus_id[MII_BUS_ID_SIZE]; 779 int interface = priv->plat->interface; 780 int max_speed = priv->plat->max_speed; 781 priv->oldlink = 0; 782 priv->speed = 0; 783 priv->oldduplex = -1; 784 785 if (priv->plat->phy_bus_name) 786 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 787 priv->plat->phy_bus_name, priv->plat->bus_id); 788 else 789 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 790 priv->plat->bus_id); 791 792 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 793 priv->plat->phy_addr); 794 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 795 796 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); 797 798 if (IS_ERR(phydev)) { 799 pr_err("%s: Could not attach to PHY\n", dev->name); 800 return PTR_ERR(phydev); 801 } 802 803 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 804 if ((interface == PHY_INTERFACE_MODE_MII) || 805 (interface == PHY_INTERFACE_MODE_RMII) || 806 (max_speed < 1000 && max_speed > 0)) 807 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 808 SUPPORTED_1000baseT_Full); 809 810 /* 811 * Broken HW is sometimes missing the pull-up resistor on the 812 * MDIO line, which results in reads to non-existent devices returning 813 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 814 * device as well. 815 * Note: phydev->phy_id is the result of reading the UID PHY registers. 816 */ 817 if (phydev->phy_id == 0) { 818 phy_disconnect(phydev); 819 return -ENODEV; 820 } 821 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 822 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 823 824 priv->phydev = phydev; 825 826 return 0; 827 } 828 829 /** 830 * stmmac_display_ring: display ring 831 * @head: pointer to the head of the ring passed. 832 * @size: size of the ring. 833 * @extend_desc: to verify if extended descriptors are used. 834 * Description: display the control/status and buffer descriptors. 835 */ 836 static void stmmac_display_ring(void *head, int size, int extend_desc) 837 { 838 int i; 839 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 840 struct dma_desc *p = (struct dma_desc *)head; 841 842 for (i = 0; i < size; i++) { 843 u64 x; 844 if (extend_desc) { 845 x = *(u64 *) ep; 846 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 847 i, (unsigned int)virt_to_phys(ep), 848 (unsigned int)x, (unsigned int)(x >> 32), 849 ep->basic.des2, ep->basic.des3); 850 ep++; 851 } else { 852 x = *(u64 *) p; 853 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 854 i, (unsigned int)virt_to_phys(p), 855 (unsigned int)x, (unsigned int)(x >> 32), 856 p->des2, p->des3); 857 p++; 858 } 859 pr_info("\n"); 860 } 861 } 862 863 static void stmmac_display_rings(struct stmmac_priv *priv) 864 { 865 unsigned int txsize = priv->dma_tx_size; 866 unsigned int rxsize = priv->dma_rx_size; 867 868 if (priv->extend_desc) { 869 pr_info("Extended RX descriptor ring:\n"); 870 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 871 pr_info("Extended TX descriptor ring:\n"); 872 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 873 } else { 874 pr_info("RX descriptor ring:\n"); 875 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 876 pr_info("TX descriptor ring:\n"); 877 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 878 } 879 } 880 881 static int stmmac_set_bfsize(int mtu, int bufsize) 882 { 883 int ret = bufsize; 884 885 if (mtu >= BUF_SIZE_4KiB) 886 ret = BUF_SIZE_8KiB; 887 else if (mtu >= BUF_SIZE_2KiB) 888 ret = BUF_SIZE_4KiB; 889 else if (mtu >= DMA_BUFFER_SIZE) 890 ret = BUF_SIZE_2KiB; 891 else 892 ret = DMA_BUFFER_SIZE; 893 894 return ret; 895 } 896 897 /** 898 * stmmac_clear_descriptors: clear descriptors 899 * @priv: driver private structure 900 * Description: this function is called to clear the tx and rx descriptors 901 * in case of both basic and extended descriptors are used. 902 */ 903 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 904 { 905 int i; 906 unsigned int txsize = priv->dma_tx_size; 907 unsigned int rxsize = priv->dma_rx_size; 908 909 /* Clear the Rx/Tx descriptors */ 910 for (i = 0; i < rxsize; i++) 911 if (priv->extend_desc) 912 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 913 priv->use_riwt, priv->mode, 914 (i == rxsize - 1)); 915 else 916 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 917 priv->use_riwt, priv->mode, 918 (i == rxsize - 1)); 919 for (i = 0; i < txsize; i++) 920 if (priv->extend_desc) 921 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 922 priv->mode, 923 (i == txsize - 1)); 924 else 925 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 926 priv->mode, 927 (i == txsize - 1)); 928 } 929 930 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 931 int i) 932 { 933 struct sk_buff *skb; 934 935 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, 936 GFP_KERNEL); 937 if (!skb) { 938 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 939 return -ENOMEM; 940 } 941 skb_reserve(skb, NET_IP_ALIGN); 942 priv->rx_skbuff[i] = skb; 943 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 944 priv->dma_buf_sz, 945 DMA_FROM_DEVICE); 946 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 947 pr_err("%s: DMA mapping error\n", __func__); 948 dev_kfree_skb_any(skb); 949 return -EINVAL; 950 } 951 952 p->des2 = priv->rx_skbuff_dma[i]; 953 954 if ((priv->mode == STMMAC_RING_MODE) && 955 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 956 priv->hw->ring->init_desc3(p); 957 958 return 0; 959 } 960 961 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 962 { 963 if (priv->rx_skbuff[i]) { 964 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 965 priv->dma_buf_sz, DMA_FROM_DEVICE); 966 dev_kfree_skb_any(priv->rx_skbuff[i]); 967 } 968 priv->rx_skbuff[i] = NULL; 969 } 970 971 /** 972 * init_dma_desc_rings - init the RX/TX descriptor rings 973 * @dev: net device structure 974 * Description: this function initializes the DMA RX/TX descriptors 975 * and allocates the socket buffers. It suppors the chained and ring 976 * modes. 977 */ 978 static int init_dma_desc_rings(struct net_device *dev) 979 { 980 int i; 981 struct stmmac_priv *priv = netdev_priv(dev); 982 unsigned int txsize = priv->dma_tx_size; 983 unsigned int rxsize = priv->dma_rx_size; 984 unsigned int bfsize = 0; 985 int ret = -ENOMEM; 986 987 /* Set the max buffer size according to the DESC mode 988 * and the MTU. Note that RING mode allows 16KiB bsize. 989 */ 990 if (priv->mode == STMMAC_RING_MODE) 991 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 992 993 if (bfsize < BUF_SIZE_16KiB) 994 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 995 996 priv->dma_buf_sz = bfsize; 997 998 if (netif_msg_probe(priv)) 999 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1000 txsize, rxsize, bfsize); 1001 1002 if (netif_msg_probe(priv)) { 1003 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1004 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1005 1006 /* RX INITIALIZATION */ 1007 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1008 } 1009 for (i = 0; i < rxsize; i++) { 1010 struct dma_desc *p; 1011 if (priv->extend_desc) 1012 p = &((priv->dma_erx + i)->basic); 1013 else 1014 p = priv->dma_rx + i; 1015 1016 ret = stmmac_init_rx_buffers(priv, p, i); 1017 if (ret) 1018 goto err_init_rx_buffers; 1019 1020 if (netif_msg_probe(priv)) 1021 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1022 priv->rx_skbuff[i]->data, 1023 (unsigned int)priv->rx_skbuff_dma[i]); 1024 } 1025 priv->cur_rx = 0; 1026 priv->dirty_rx = (unsigned int)(i - rxsize); 1027 buf_sz = bfsize; 1028 1029 /* Setup the chained descriptor addresses */ 1030 if (priv->mode == STMMAC_CHAIN_MODE) { 1031 if (priv->extend_desc) { 1032 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy, 1033 rxsize, 1); 1034 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy, 1035 txsize, 1); 1036 } else { 1037 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy, 1038 rxsize, 0); 1039 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy, 1040 txsize, 0); 1041 } 1042 } 1043 1044 /* TX INITIALIZATION */ 1045 for (i = 0; i < txsize; i++) { 1046 struct dma_desc *p; 1047 if (priv->extend_desc) 1048 p = &((priv->dma_etx + i)->basic); 1049 else 1050 p = priv->dma_tx + i; 1051 p->des2 = 0; 1052 priv->tx_skbuff_dma[i] = 0; 1053 priv->tx_skbuff[i] = NULL; 1054 } 1055 1056 priv->dirty_tx = 0; 1057 priv->cur_tx = 0; 1058 1059 stmmac_clear_descriptors(priv); 1060 1061 if (netif_msg_hw(priv)) 1062 stmmac_display_rings(priv); 1063 1064 return 0; 1065 err_init_rx_buffers: 1066 while (--i >= 0) 1067 stmmac_free_rx_buffers(priv, i); 1068 return ret; 1069 } 1070 1071 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1072 { 1073 int i; 1074 1075 for (i = 0; i < priv->dma_rx_size; i++) 1076 stmmac_free_rx_buffers(priv, i); 1077 } 1078 1079 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1080 { 1081 int i; 1082 1083 for (i = 0; i < priv->dma_tx_size; i++) { 1084 struct dma_desc *p; 1085 1086 if (priv->extend_desc) 1087 p = &((priv->dma_etx + i)->basic); 1088 else 1089 p = priv->dma_tx + i; 1090 1091 if (priv->tx_skbuff_dma[i]) { 1092 dma_unmap_single(priv->device, 1093 priv->tx_skbuff_dma[i], 1094 priv->hw->desc->get_tx_len(p), 1095 DMA_TO_DEVICE); 1096 priv->tx_skbuff_dma[i] = 0; 1097 } 1098 1099 if (priv->tx_skbuff[i] != NULL) { 1100 dev_kfree_skb_any(priv->tx_skbuff[i]); 1101 priv->tx_skbuff[i] = NULL; 1102 } 1103 } 1104 } 1105 1106 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1107 { 1108 unsigned int txsize = priv->dma_tx_size; 1109 unsigned int rxsize = priv->dma_rx_size; 1110 int ret = -ENOMEM; 1111 1112 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1113 GFP_KERNEL); 1114 if (!priv->rx_skbuff_dma) 1115 return -ENOMEM; 1116 1117 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1118 GFP_KERNEL); 1119 if (!priv->rx_skbuff) 1120 goto err_rx_skbuff; 1121 1122 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t), 1123 GFP_KERNEL); 1124 if (!priv->tx_skbuff_dma) 1125 goto err_tx_skbuff_dma; 1126 1127 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1128 GFP_KERNEL); 1129 if (!priv->tx_skbuff) 1130 goto err_tx_skbuff; 1131 1132 if (priv->extend_desc) { 1133 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * 1134 sizeof(struct 1135 dma_extended_desc), 1136 &priv->dma_rx_phy, 1137 GFP_KERNEL); 1138 if (!priv->dma_erx) 1139 goto err_dma; 1140 1141 priv->dma_etx = dma_alloc_coherent(priv->device, txsize * 1142 sizeof(struct 1143 dma_extended_desc), 1144 &priv->dma_tx_phy, 1145 GFP_KERNEL); 1146 if (!priv->dma_etx) { 1147 dma_free_coherent(priv->device, priv->dma_rx_size * 1148 sizeof(struct dma_extended_desc), 1149 priv->dma_erx, priv->dma_rx_phy); 1150 goto err_dma; 1151 } 1152 } else { 1153 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * 1154 sizeof(struct dma_desc), 1155 &priv->dma_rx_phy, 1156 GFP_KERNEL); 1157 if (!priv->dma_rx) 1158 goto err_dma; 1159 1160 priv->dma_tx = dma_alloc_coherent(priv->device, txsize * 1161 sizeof(struct dma_desc), 1162 &priv->dma_tx_phy, 1163 GFP_KERNEL); 1164 if (!priv->dma_tx) { 1165 dma_free_coherent(priv->device, priv->dma_rx_size * 1166 sizeof(struct dma_desc), 1167 priv->dma_rx, priv->dma_rx_phy); 1168 goto err_dma; 1169 } 1170 } 1171 1172 return 0; 1173 1174 err_dma: 1175 kfree(priv->tx_skbuff); 1176 err_tx_skbuff: 1177 kfree(priv->tx_skbuff_dma); 1178 err_tx_skbuff_dma: 1179 kfree(priv->rx_skbuff); 1180 err_rx_skbuff: 1181 kfree(priv->rx_skbuff_dma); 1182 return ret; 1183 } 1184 1185 static void free_dma_desc_resources(struct stmmac_priv *priv) 1186 { 1187 /* Release the DMA TX/RX socket buffers */ 1188 dma_free_rx_skbufs(priv); 1189 dma_free_tx_skbufs(priv); 1190 1191 /* Free DMA regions of consistent memory previously allocated */ 1192 if (!priv->extend_desc) { 1193 dma_free_coherent(priv->device, 1194 priv->dma_tx_size * sizeof(struct dma_desc), 1195 priv->dma_tx, priv->dma_tx_phy); 1196 dma_free_coherent(priv->device, 1197 priv->dma_rx_size * sizeof(struct dma_desc), 1198 priv->dma_rx, priv->dma_rx_phy); 1199 } else { 1200 dma_free_coherent(priv->device, priv->dma_tx_size * 1201 sizeof(struct dma_extended_desc), 1202 priv->dma_etx, priv->dma_tx_phy); 1203 dma_free_coherent(priv->device, priv->dma_rx_size * 1204 sizeof(struct dma_extended_desc), 1205 priv->dma_erx, priv->dma_rx_phy); 1206 } 1207 kfree(priv->rx_skbuff_dma); 1208 kfree(priv->rx_skbuff); 1209 kfree(priv->tx_skbuff_dma); 1210 kfree(priv->tx_skbuff); 1211 } 1212 1213 /** 1214 * stmmac_dma_operation_mode - HW DMA operation mode 1215 * @priv: driver private structure 1216 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 1217 * or Store-And-Forward capability. 1218 */ 1219 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1220 { 1221 if (priv->plat->force_thresh_dma_mode) 1222 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); 1223 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1224 /* 1225 * In case of GMAC, SF mode can be enabled 1226 * to perform the TX COE in HW. This depends on: 1227 * 1) TX COE if actually supported 1228 * 2) There is no bugged Jumbo frame support 1229 * that needs to not insert csum in the TDES. 1230 */ 1231 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); 1232 tc = SF_DMA_MODE; 1233 } else 1234 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1235 } 1236 1237 /** 1238 * stmmac_tx_clean: 1239 * @priv: driver private structure 1240 * Description: it reclaims resources after transmission completes. 1241 */ 1242 static void stmmac_tx_clean(struct stmmac_priv *priv) 1243 { 1244 unsigned int txsize = priv->dma_tx_size; 1245 1246 spin_lock(&priv->tx_lock); 1247 1248 priv->xstats.tx_clean++; 1249 1250 while (priv->dirty_tx != priv->cur_tx) { 1251 int last; 1252 unsigned int entry = priv->dirty_tx % txsize; 1253 struct sk_buff *skb = priv->tx_skbuff[entry]; 1254 struct dma_desc *p; 1255 1256 if (priv->extend_desc) 1257 p = (struct dma_desc *)(priv->dma_etx + entry); 1258 else 1259 p = priv->dma_tx + entry; 1260 1261 /* Check if the descriptor is owned by the DMA. */ 1262 if (priv->hw->desc->get_tx_owner(p)) 1263 break; 1264 1265 /* Verify tx error by looking at the last segment. */ 1266 last = priv->hw->desc->get_tx_ls(p); 1267 if (likely(last)) { 1268 int tx_error = 1269 priv->hw->desc->tx_status(&priv->dev->stats, 1270 &priv->xstats, p, 1271 priv->ioaddr); 1272 if (likely(tx_error == 0)) { 1273 priv->dev->stats.tx_packets++; 1274 priv->xstats.tx_pkt_n++; 1275 } else 1276 priv->dev->stats.tx_errors++; 1277 1278 stmmac_get_tx_hwtstamp(priv, entry, skb); 1279 } 1280 if (netif_msg_tx_done(priv)) 1281 pr_debug("%s: curr %d, dirty %d\n", __func__, 1282 priv->cur_tx, priv->dirty_tx); 1283 1284 if (likely(priv->tx_skbuff_dma[entry])) { 1285 dma_unmap_single(priv->device, 1286 priv->tx_skbuff_dma[entry], 1287 priv->hw->desc->get_tx_len(p), 1288 DMA_TO_DEVICE); 1289 priv->tx_skbuff_dma[entry] = 0; 1290 } 1291 priv->hw->ring->clean_desc3(priv, p); 1292 1293 if (likely(skb != NULL)) { 1294 dev_kfree_skb(skb); 1295 priv->tx_skbuff[entry] = NULL; 1296 } 1297 1298 priv->hw->desc->release_tx_desc(p, priv->mode); 1299 1300 priv->dirty_tx++; 1301 } 1302 if (unlikely(netif_queue_stopped(priv->dev) && 1303 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1304 netif_tx_lock(priv->dev); 1305 if (netif_queue_stopped(priv->dev) && 1306 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1307 if (netif_msg_tx_done(priv)) 1308 pr_debug("%s: restart transmit\n", __func__); 1309 netif_wake_queue(priv->dev); 1310 } 1311 netif_tx_unlock(priv->dev); 1312 } 1313 1314 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1315 stmmac_enable_eee_mode(priv); 1316 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1317 } 1318 spin_unlock(&priv->tx_lock); 1319 } 1320 1321 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1322 { 1323 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1324 } 1325 1326 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1327 { 1328 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1329 } 1330 1331 /** 1332 * stmmac_tx_err: irq tx error mng function 1333 * @priv: driver private structure 1334 * Description: it cleans the descriptors and restarts the transmission 1335 * in case of errors. 1336 */ 1337 static void stmmac_tx_err(struct stmmac_priv *priv) 1338 { 1339 int i; 1340 int txsize = priv->dma_tx_size; 1341 netif_stop_queue(priv->dev); 1342 1343 priv->hw->dma->stop_tx(priv->ioaddr); 1344 dma_free_tx_skbufs(priv); 1345 for (i = 0; i < txsize; i++) 1346 if (priv->extend_desc) 1347 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1348 priv->mode, 1349 (i == txsize - 1)); 1350 else 1351 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1352 priv->mode, 1353 (i == txsize - 1)); 1354 priv->dirty_tx = 0; 1355 priv->cur_tx = 0; 1356 priv->hw->dma->start_tx(priv->ioaddr); 1357 1358 priv->dev->stats.tx_errors++; 1359 netif_wake_queue(priv->dev); 1360 } 1361 1362 /** 1363 * stmmac_dma_interrupt: DMA ISR 1364 * @priv: driver private structure 1365 * Description: this is the DMA ISR. It is called by the main ISR. 1366 * It calls the dwmac dma routine to understand which type of interrupt 1367 * happened. In case of there is a Normal interrupt and either TX or RX 1368 * interrupt happened so the NAPI is scheduled. 1369 */ 1370 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1371 { 1372 int status; 1373 1374 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1375 if (likely((status & handle_rx)) || (status & handle_tx)) { 1376 if (likely(napi_schedule_prep(&priv->napi))) { 1377 stmmac_disable_dma_irq(priv); 1378 __napi_schedule(&priv->napi); 1379 } 1380 } 1381 if (unlikely(status & tx_hard_error_bump_tc)) { 1382 /* Try to bump up the dma threshold on this failure */ 1383 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 1384 tc += 64; 1385 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 1386 priv->xstats.threshold = tc; 1387 } 1388 } else if (unlikely(status == tx_hard_error)) 1389 stmmac_tx_err(priv); 1390 } 1391 1392 /** 1393 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1394 * @priv: driver private structure 1395 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1396 */ 1397 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1398 { 1399 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1400 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1401 1402 dwmac_mmc_intr_all_mask(priv->ioaddr); 1403 1404 if (priv->dma_cap.rmon) { 1405 dwmac_mmc_ctrl(priv->ioaddr, mode); 1406 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1407 } else 1408 pr_info(" No MAC Management Counters available\n"); 1409 } 1410 1411 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1412 { 1413 u32 hwid = priv->hw->synopsys_uid; 1414 1415 /* Check Synopsys Id (not available on old chips) */ 1416 if (likely(hwid)) { 1417 u32 uid = ((hwid & 0x0000ff00) >> 8); 1418 u32 synid = (hwid & 0x000000ff); 1419 1420 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1421 uid, synid); 1422 1423 return synid; 1424 } 1425 return 0; 1426 } 1427 1428 /** 1429 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors 1430 * @priv: driver private structure 1431 * Description: select the Enhanced/Alternate or Normal descriptors. 1432 * In case of Enhanced/Alternate, it looks at the extended descriptors are 1433 * supported by the HW cap. register. 1434 */ 1435 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1436 { 1437 if (priv->plat->enh_desc) { 1438 pr_info(" Enhanced/Alternate descriptors\n"); 1439 1440 /* GMAC older than 3.50 has no extended descriptors */ 1441 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1442 pr_info("\tEnabled extended descriptors\n"); 1443 priv->extend_desc = 1; 1444 } else 1445 pr_warn("Extended descriptors not supported\n"); 1446 1447 priv->hw->desc = &enh_desc_ops; 1448 } else { 1449 pr_info(" Normal descriptors\n"); 1450 priv->hw->desc = &ndesc_ops; 1451 } 1452 } 1453 1454 /** 1455 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. 1456 * @priv: driver private structure 1457 * Description: 1458 * new GMAC chip generations have a new register to indicate the 1459 * presence of the optional feature/functions. 1460 * This can be also used to override the value passed through the 1461 * platform and necessary for old MAC10/100 and GMAC chips. 1462 */ 1463 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1464 { 1465 u32 hw_cap = 0; 1466 1467 if (priv->hw->dma->get_hw_feature) { 1468 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1469 1470 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1471 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1472 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1473 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1474 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1475 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1476 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1477 priv->dma_cap.pmt_remote_wake_up = 1478 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1479 priv->dma_cap.pmt_magic_frame = 1480 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1481 /* MMC */ 1482 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1483 /* IEEE 1588-2002 */ 1484 priv->dma_cap.time_stamp = 1485 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1486 /* IEEE 1588-2008 */ 1487 priv->dma_cap.atime_stamp = 1488 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1489 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1490 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1491 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1492 /* TX and RX csum */ 1493 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1494 priv->dma_cap.rx_coe_type1 = 1495 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1496 priv->dma_cap.rx_coe_type2 = 1497 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1498 priv->dma_cap.rxfifo_over_2048 = 1499 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1500 /* TX and RX number of channels */ 1501 priv->dma_cap.number_rx_channel = 1502 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1503 priv->dma_cap.number_tx_channel = 1504 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1505 /* Alternate (enhanced) DESC mode */ 1506 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1507 } 1508 1509 return hw_cap; 1510 } 1511 1512 /** 1513 * stmmac_check_ether_addr: check if the MAC addr is valid 1514 * @priv: driver private structure 1515 * Description: 1516 * it is to verify if the MAC address is valid, in case of failures it 1517 * generates a random MAC address 1518 */ 1519 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1520 { 1521 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1522 priv->hw->mac->get_umac_addr((void __iomem *) 1523 priv->dev->base_addr, 1524 priv->dev->dev_addr, 0); 1525 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1526 eth_hw_addr_random(priv->dev); 1527 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1528 priv->dev->dev_addr); 1529 } 1530 } 1531 1532 /** 1533 * stmmac_init_dma_engine: DMA init. 1534 * @priv: driver private structure 1535 * Description: 1536 * It inits the DMA invoking the specific MAC/GMAC callback. 1537 * Some DMA parameters can be passed from the platform; 1538 * in case of these are not passed a default is kept for the MAC or GMAC. 1539 */ 1540 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1541 { 1542 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1543 int mixed_burst = 0; 1544 int atds = 0; 1545 1546 if (priv->plat->dma_cfg) { 1547 pbl = priv->plat->dma_cfg->pbl; 1548 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1549 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1550 burst_len = priv->plat->dma_cfg->burst_len; 1551 } 1552 1553 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1554 atds = 1; 1555 1556 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1557 burst_len, priv->dma_tx_phy, 1558 priv->dma_rx_phy, atds); 1559 } 1560 1561 /** 1562 * stmmac_tx_timer: mitigation sw timer for tx. 1563 * @data: data pointer 1564 * Description: 1565 * This is the timer handler to directly invoke the stmmac_tx_clean. 1566 */ 1567 static void stmmac_tx_timer(unsigned long data) 1568 { 1569 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1570 1571 stmmac_tx_clean(priv); 1572 } 1573 1574 /** 1575 * stmmac_init_tx_coalesce: init tx mitigation options. 1576 * @priv: driver private structure 1577 * Description: 1578 * This inits the transmit coalesce parameters: i.e. timer rate, 1579 * timer handler and default threshold used for enabling the 1580 * interrupt on completion bit. 1581 */ 1582 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1583 { 1584 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1585 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1586 init_timer(&priv->txtimer); 1587 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1588 priv->txtimer.data = (unsigned long)priv; 1589 priv->txtimer.function = stmmac_tx_timer; 1590 add_timer(&priv->txtimer); 1591 } 1592 1593 /** 1594 * stmmac_hw_setup: setup mac in a usable state. 1595 * @dev : pointer to the device structure. 1596 * Description: 1597 * This function sets up the ip in a usable state. 1598 * Return value: 1599 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1600 * file on failure. 1601 */ 1602 static int stmmac_hw_setup(struct net_device *dev) 1603 { 1604 struct stmmac_priv *priv = netdev_priv(dev); 1605 int ret; 1606 1607 ret = init_dma_desc_rings(dev); 1608 if (ret < 0) { 1609 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1610 return ret; 1611 } 1612 /* DMA initialization and SW reset */ 1613 ret = stmmac_init_dma_engine(priv); 1614 if (ret < 0) { 1615 pr_err("%s: DMA engine initialization failed\n", __func__); 1616 return ret; 1617 } 1618 1619 /* Copy the MAC addr into the HW */ 1620 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1621 1622 /* If required, perform hw setup of the bus. */ 1623 if (priv->plat->bus_setup) 1624 priv->plat->bus_setup(priv->ioaddr); 1625 1626 /* Initialize the MAC Core */ 1627 priv->hw->mac->core_init(priv->ioaddr, dev->mtu); 1628 1629 /* Enable the MAC Rx/Tx */ 1630 stmmac_set_mac(priv->ioaddr, true); 1631 1632 /* Set the HW DMA mode and the COE */ 1633 stmmac_dma_operation_mode(priv); 1634 1635 stmmac_mmc_setup(priv); 1636 1637 ret = stmmac_init_ptp(priv); 1638 if (ret && ret != -EOPNOTSUPP) 1639 pr_warn("%s: failed PTP initialisation\n", __func__); 1640 1641 #ifdef CONFIG_STMMAC_DEBUG_FS 1642 ret = stmmac_init_fs(dev); 1643 if (ret < 0) 1644 pr_warn("%s: failed debugFS registration\n", __func__); 1645 #endif 1646 /* Start the ball rolling... */ 1647 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1648 priv->hw->dma->start_tx(priv->ioaddr); 1649 priv->hw->dma->start_rx(priv->ioaddr); 1650 1651 /* Dump DMA/MAC registers */ 1652 if (netif_msg_hw(priv)) { 1653 priv->hw->mac->dump_regs(priv->ioaddr); 1654 priv->hw->dma->dump_regs(priv->ioaddr); 1655 } 1656 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1657 1658 priv->eee_enabled = stmmac_eee_init(priv); 1659 1660 stmmac_init_tx_coalesce(priv); 1661 1662 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1663 priv->rx_riwt = MAX_DMA_RIWT; 1664 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1665 } 1666 1667 if (priv->pcs && priv->hw->mac->ctrl_ane) 1668 priv->hw->mac->ctrl_ane(priv->ioaddr, 0); 1669 1670 return 0; 1671 } 1672 1673 /** 1674 * stmmac_open - open entry point of the driver 1675 * @dev : pointer to the device structure. 1676 * Description: 1677 * This function is the open entry point of the driver. 1678 * Return value: 1679 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1680 * file on failure. 1681 */ 1682 static int stmmac_open(struct net_device *dev) 1683 { 1684 struct stmmac_priv *priv = netdev_priv(dev); 1685 int ret; 1686 1687 stmmac_check_ether_addr(priv); 1688 1689 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1690 priv->pcs != STMMAC_PCS_RTBI) { 1691 ret = stmmac_init_phy(dev); 1692 if (ret) { 1693 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1694 __func__, ret); 1695 goto phy_error; 1696 } 1697 } 1698 1699 /* Extra statistics */ 1700 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1701 priv->xstats.threshold = tc; 1702 1703 /* Create and initialize the TX/RX descriptors chains. */ 1704 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1705 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1706 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1707 1708 alloc_dma_desc_resources(priv); 1709 if (ret < 0) { 1710 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1711 goto dma_desc_error; 1712 } 1713 1714 ret = stmmac_hw_setup(dev); 1715 if (ret < 0) { 1716 pr_err("%s: Hw setup failed\n", __func__); 1717 goto init_error; 1718 } 1719 1720 if (priv->phydev) 1721 phy_start(priv->phydev); 1722 1723 /* Request the IRQ lines */ 1724 ret = request_irq(dev->irq, stmmac_interrupt, 1725 IRQF_SHARED, dev->name, dev); 1726 if (unlikely(ret < 0)) { 1727 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1728 __func__, dev->irq, ret); 1729 goto init_error; 1730 } 1731 1732 /* Request the Wake IRQ in case of another line is used for WoL */ 1733 if (priv->wol_irq != dev->irq) { 1734 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1735 IRQF_SHARED, dev->name, dev); 1736 if (unlikely(ret < 0)) { 1737 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1738 __func__, priv->wol_irq, ret); 1739 goto wolirq_error; 1740 } 1741 } 1742 1743 /* Request the IRQ lines */ 1744 if (priv->lpi_irq != -ENXIO) { 1745 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1746 dev->name, dev); 1747 if (unlikely(ret < 0)) { 1748 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1749 __func__, priv->lpi_irq, ret); 1750 goto lpiirq_error; 1751 } 1752 } 1753 1754 napi_enable(&priv->napi); 1755 netif_start_queue(dev); 1756 1757 return 0; 1758 1759 lpiirq_error: 1760 if (priv->wol_irq != dev->irq) 1761 free_irq(priv->wol_irq, dev); 1762 wolirq_error: 1763 free_irq(dev->irq, dev); 1764 1765 init_error: 1766 free_dma_desc_resources(priv); 1767 dma_desc_error: 1768 if (priv->phydev) 1769 phy_disconnect(priv->phydev); 1770 phy_error: 1771 clk_disable_unprepare(priv->stmmac_clk); 1772 1773 return ret; 1774 } 1775 1776 /** 1777 * stmmac_release - close entry point of the driver 1778 * @dev : device pointer. 1779 * Description: 1780 * This is the stop entry point of the driver. 1781 */ 1782 static int stmmac_release(struct net_device *dev) 1783 { 1784 struct stmmac_priv *priv = netdev_priv(dev); 1785 1786 if (priv->eee_enabled) 1787 del_timer_sync(&priv->eee_ctrl_timer); 1788 1789 /* Stop and disconnect the PHY */ 1790 if (priv->phydev) { 1791 phy_stop(priv->phydev); 1792 phy_disconnect(priv->phydev); 1793 priv->phydev = NULL; 1794 } 1795 1796 netif_stop_queue(dev); 1797 1798 napi_disable(&priv->napi); 1799 1800 del_timer_sync(&priv->txtimer); 1801 1802 /* Free the IRQ lines */ 1803 free_irq(dev->irq, dev); 1804 if (priv->wol_irq != dev->irq) 1805 free_irq(priv->wol_irq, dev); 1806 if (priv->lpi_irq != -ENXIO) 1807 free_irq(priv->lpi_irq, dev); 1808 1809 /* Stop TX/RX DMA and clear the descriptors */ 1810 priv->hw->dma->stop_tx(priv->ioaddr); 1811 priv->hw->dma->stop_rx(priv->ioaddr); 1812 1813 /* Release and free the Rx/Tx resources */ 1814 free_dma_desc_resources(priv); 1815 1816 /* Disable the MAC Rx/Tx */ 1817 stmmac_set_mac(priv->ioaddr, false); 1818 1819 netif_carrier_off(dev); 1820 1821 #ifdef CONFIG_STMMAC_DEBUG_FS 1822 stmmac_exit_fs(); 1823 #endif 1824 1825 stmmac_release_ptp(priv); 1826 1827 return 0; 1828 } 1829 1830 /** 1831 * stmmac_xmit: Tx entry point of the driver 1832 * @skb : the socket buffer 1833 * @dev : device pointer 1834 * Description : this is the tx entry point of the driver. 1835 * It programs the chain or the ring and supports oversized frames 1836 * and SG feature. 1837 */ 1838 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1839 { 1840 struct stmmac_priv *priv = netdev_priv(dev); 1841 unsigned int txsize = priv->dma_tx_size; 1842 unsigned int entry; 1843 int i, csum_insertion = 0, is_jumbo = 0; 1844 int nfrags = skb_shinfo(skb)->nr_frags; 1845 struct dma_desc *desc, *first; 1846 unsigned int nopaged_len = skb_headlen(skb); 1847 1848 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1849 if (!netif_queue_stopped(dev)) { 1850 netif_stop_queue(dev); 1851 /* This is a hard error, log it. */ 1852 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1853 } 1854 return NETDEV_TX_BUSY; 1855 } 1856 1857 spin_lock(&priv->tx_lock); 1858 1859 if (priv->tx_path_in_lpi_mode) 1860 stmmac_disable_eee_mode(priv); 1861 1862 entry = priv->cur_tx % txsize; 1863 1864 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1865 1866 if (priv->extend_desc) 1867 desc = (struct dma_desc *)(priv->dma_etx + entry); 1868 else 1869 desc = priv->dma_tx + entry; 1870 1871 first = desc; 1872 1873 /* To program the descriptors according to the size of the frame */ 1874 if (priv->mode == STMMAC_RING_MODE) { 1875 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len, 1876 priv->plat->enh_desc); 1877 if (unlikely(is_jumbo)) 1878 entry = priv->hw->ring->jumbo_frm(priv, skb, 1879 csum_insertion); 1880 } else { 1881 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len, 1882 priv->plat->enh_desc); 1883 if (unlikely(is_jumbo)) 1884 entry = priv->hw->chain->jumbo_frm(priv, skb, 1885 csum_insertion); 1886 } 1887 if (likely(!is_jumbo)) { 1888 desc->des2 = dma_map_single(priv->device, skb->data, 1889 nopaged_len, DMA_TO_DEVICE); 1890 priv->tx_skbuff_dma[entry] = desc->des2; 1891 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1892 csum_insertion, priv->mode); 1893 } else 1894 desc = first; 1895 1896 for (i = 0; i < nfrags; i++) { 1897 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1898 int len = skb_frag_size(frag); 1899 1900 priv->tx_skbuff[entry] = NULL; 1901 entry = (++priv->cur_tx) % txsize; 1902 if (priv->extend_desc) 1903 desc = (struct dma_desc *)(priv->dma_etx + entry); 1904 else 1905 desc = priv->dma_tx + entry; 1906 1907 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1908 DMA_TO_DEVICE); 1909 priv->tx_skbuff_dma[entry] = desc->des2; 1910 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 1911 priv->mode); 1912 wmb(); 1913 priv->hw->desc->set_tx_owner(desc); 1914 wmb(); 1915 } 1916 1917 priv->tx_skbuff[entry] = skb; 1918 1919 /* Finalize the latest segment. */ 1920 priv->hw->desc->close_tx_desc(desc); 1921 1922 wmb(); 1923 /* According to the coalesce parameter the IC bit for the latest 1924 * segment could be reset and the timer re-started to invoke the 1925 * stmmac_tx function. This approach takes care about the fragments. 1926 */ 1927 priv->tx_count_frames += nfrags + 1; 1928 if (priv->tx_coal_frames > priv->tx_count_frames) { 1929 priv->hw->desc->clear_tx_ic(desc); 1930 priv->xstats.tx_reset_ic_bit++; 1931 mod_timer(&priv->txtimer, 1932 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1933 } else 1934 priv->tx_count_frames = 0; 1935 1936 /* To avoid raise condition */ 1937 priv->hw->desc->set_tx_owner(first); 1938 wmb(); 1939 1940 priv->cur_tx++; 1941 1942 if (netif_msg_pktdata(priv)) { 1943 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 1944 __func__, (priv->cur_tx % txsize), 1945 (priv->dirty_tx % txsize), entry, first, nfrags); 1946 1947 if (priv->extend_desc) 1948 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 1949 else 1950 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 1951 1952 pr_debug(">>> frame to be transmitted: "); 1953 print_pkt(skb->data, skb->len); 1954 } 1955 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1956 if (netif_msg_hw(priv)) 1957 pr_debug("%s: stop transmitted packets\n", __func__); 1958 netif_stop_queue(dev); 1959 } 1960 1961 dev->stats.tx_bytes += skb->len; 1962 1963 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1964 priv->hwts_tx_en)) { 1965 /* declare that device is doing timestamping */ 1966 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1967 priv->hw->desc->enable_tx_timestamp(first); 1968 } 1969 1970 if (!priv->hwts_tx_en) 1971 skb_tx_timestamp(skb); 1972 1973 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1974 1975 spin_unlock(&priv->tx_lock); 1976 1977 return NETDEV_TX_OK; 1978 } 1979 1980 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 1981 { 1982 struct ethhdr *ehdr; 1983 u16 vlanid; 1984 1985 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 1986 NETIF_F_HW_VLAN_CTAG_RX && 1987 !__vlan_get_tag(skb, &vlanid)) { 1988 /* pop the vlan tag */ 1989 ehdr = (struct ethhdr *)skb->data; 1990 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 1991 skb_pull(skb, VLAN_HLEN); 1992 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 1993 } 1994 } 1995 1996 1997 /** 1998 * stmmac_rx_refill: refill used skb preallocated buffers 1999 * @priv: driver private structure 2000 * Description : this is to reallocate the skb for the reception process 2001 * that is based on zero-copy. 2002 */ 2003 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2004 { 2005 unsigned int rxsize = priv->dma_rx_size; 2006 int bfsize = priv->dma_buf_sz; 2007 2008 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2009 unsigned int entry = priv->dirty_rx % rxsize; 2010 struct dma_desc *p; 2011 2012 if (priv->extend_desc) 2013 p = (struct dma_desc *)(priv->dma_erx + entry); 2014 else 2015 p = priv->dma_rx + entry; 2016 2017 if (likely(priv->rx_skbuff[entry] == NULL)) { 2018 struct sk_buff *skb; 2019 2020 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2021 2022 if (unlikely(skb == NULL)) 2023 break; 2024 2025 priv->rx_skbuff[entry] = skb; 2026 priv->rx_skbuff_dma[entry] = 2027 dma_map_single(priv->device, skb->data, bfsize, 2028 DMA_FROM_DEVICE); 2029 2030 p->des2 = priv->rx_skbuff_dma[entry]; 2031 2032 priv->hw->ring->refill_desc3(priv, p); 2033 2034 if (netif_msg_rx_status(priv)) 2035 pr_debug("\trefill entry #%d\n", entry); 2036 } 2037 wmb(); 2038 priv->hw->desc->set_rx_owner(p); 2039 wmb(); 2040 } 2041 } 2042 2043 /** 2044 * stmmac_rx_refill: refill used skb preallocated buffers 2045 * @priv: driver private structure 2046 * @limit: napi bugget. 2047 * Description : this the function called by the napi poll method. 2048 * It gets all the frames inside the ring. 2049 */ 2050 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2051 { 2052 unsigned int rxsize = priv->dma_rx_size; 2053 unsigned int entry = priv->cur_rx % rxsize; 2054 unsigned int next_entry; 2055 unsigned int count = 0; 2056 int coe = priv->plat->rx_coe; 2057 2058 if (netif_msg_rx_status(priv)) { 2059 pr_debug("%s: descriptor ring:\n", __func__); 2060 if (priv->extend_desc) 2061 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2062 else 2063 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2064 } 2065 while (count < limit) { 2066 int status; 2067 struct dma_desc *p; 2068 2069 if (priv->extend_desc) 2070 p = (struct dma_desc *)(priv->dma_erx + entry); 2071 else 2072 p = priv->dma_rx + entry; 2073 2074 if (priv->hw->desc->get_rx_owner(p)) 2075 break; 2076 2077 count++; 2078 2079 next_entry = (++priv->cur_rx) % rxsize; 2080 if (priv->extend_desc) 2081 prefetch(priv->dma_erx + next_entry); 2082 else 2083 prefetch(priv->dma_rx + next_entry); 2084 2085 /* read the status of the incoming frame */ 2086 status = priv->hw->desc->rx_status(&priv->dev->stats, 2087 &priv->xstats, p); 2088 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2089 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2090 &priv->xstats, 2091 priv->dma_erx + 2092 entry); 2093 if (unlikely(status == discard_frame)) { 2094 priv->dev->stats.rx_errors++; 2095 if (priv->hwts_rx_en && !priv->extend_desc) { 2096 /* DESC2 & DESC3 will be overwitten by device 2097 * with timestamp value, hence reinitialize 2098 * them in stmmac_rx_refill() function so that 2099 * device can reuse it. 2100 */ 2101 priv->rx_skbuff[entry] = NULL; 2102 dma_unmap_single(priv->device, 2103 priv->rx_skbuff_dma[entry], 2104 priv->dma_buf_sz, 2105 DMA_FROM_DEVICE); 2106 } 2107 } else { 2108 struct sk_buff *skb; 2109 int frame_len; 2110 2111 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2112 2113 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2114 * Type frames (LLC/LLC-SNAP) 2115 */ 2116 if (unlikely(status != llc_snap)) 2117 frame_len -= ETH_FCS_LEN; 2118 2119 if (netif_msg_rx_status(priv)) { 2120 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2121 p, entry, p->des2); 2122 if (frame_len > ETH_FRAME_LEN) 2123 pr_debug("\tframe size %d, COE: %d\n", 2124 frame_len, status); 2125 } 2126 skb = priv->rx_skbuff[entry]; 2127 if (unlikely(!skb)) { 2128 pr_err("%s: Inconsistent Rx descriptor chain\n", 2129 priv->dev->name); 2130 priv->dev->stats.rx_dropped++; 2131 break; 2132 } 2133 prefetch(skb->data - NET_IP_ALIGN); 2134 priv->rx_skbuff[entry] = NULL; 2135 2136 stmmac_get_rx_hwtstamp(priv, entry, skb); 2137 2138 skb_put(skb, frame_len); 2139 dma_unmap_single(priv->device, 2140 priv->rx_skbuff_dma[entry], 2141 priv->dma_buf_sz, DMA_FROM_DEVICE); 2142 2143 if (netif_msg_pktdata(priv)) { 2144 pr_debug("frame received (%dbytes)", frame_len); 2145 print_pkt(skb->data, frame_len); 2146 } 2147 2148 stmmac_rx_vlan(priv->dev, skb); 2149 2150 skb->protocol = eth_type_trans(skb, priv->dev); 2151 2152 if (unlikely(!coe)) 2153 skb_checksum_none_assert(skb); 2154 else 2155 skb->ip_summed = CHECKSUM_UNNECESSARY; 2156 2157 napi_gro_receive(&priv->napi, skb); 2158 2159 priv->dev->stats.rx_packets++; 2160 priv->dev->stats.rx_bytes += frame_len; 2161 } 2162 entry = next_entry; 2163 } 2164 2165 stmmac_rx_refill(priv); 2166 2167 priv->xstats.rx_pkt_n += count; 2168 2169 return count; 2170 } 2171 2172 /** 2173 * stmmac_poll - stmmac poll method (NAPI) 2174 * @napi : pointer to the napi structure. 2175 * @budget : maximum number of packets that the current CPU can receive from 2176 * all interfaces. 2177 * Description : 2178 * To look at the incoming frames and clear the tx resources. 2179 */ 2180 static int stmmac_poll(struct napi_struct *napi, int budget) 2181 { 2182 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2183 int work_done = 0; 2184 2185 priv->xstats.napi_poll++; 2186 stmmac_tx_clean(priv); 2187 2188 work_done = stmmac_rx(priv, budget); 2189 if (work_done < budget) { 2190 napi_complete(napi); 2191 stmmac_enable_dma_irq(priv); 2192 } 2193 return work_done; 2194 } 2195 2196 /** 2197 * stmmac_tx_timeout 2198 * @dev : Pointer to net device structure 2199 * Description: this function is called when a packet transmission fails to 2200 * complete within a reasonable time. The driver will mark the error in the 2201 * netdev structure and arrange for the device to be reset to a sane state 2202 * in order to transmit a new packet. 2203 */ 2204 static void stmmac_tx_timeout(struct net_device *dev) 2205 { 2206 struct stmmac_priv *priv = netdev_priv(dev); 2207 2208 /* Clear Tx resources and restart transmitting again */ 2209 stmmac_tx_err(priv); 2210 } 2211 2212 /* Configuration changes (passed on by ifconfig) */ 2213 static int stmmac_config(struct net_device *dev, struct ifmap *map) 2214 { 2215 if (dev->flags & IFF_UP) /* can't act on a running interface */ 2216 return -EBUSY; 2217 2218 /* Don't allow changing the I/O address */ 2219 if (map->base_addr != dev->base_addr) { 2220 pr_warn("%s: can't change I/O address\n", dev->name); 2221 return -EOPNOTSUPP; 2222 } 2223 2224 /* Don't allow changing the IRQ */ 2225 if (map->irq != dev->irq) { 2226 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq); 2227 return -EOPNOTSUPP; 2228 } 2229 2230 return 0; 2231 } 2232 2233 /** 2234 * stmmac_set_rx_mode - entry point for multicast addressing 2235 * @dev : pointer to the device structure 2236 * Description: 2237 * This function is a driver entry point which gets called by the kernel 2238 * whenever multicast addresses must be enabled/disabled. 2239 * Return value: 2240 * void. 2241 */ 2242 static void stmmac_set_rx_mode(struct net_device *dev) 2243 { 2244 struct stmmac_priv *priv = netdev_priv(dev); 2245 2246 spin_lock(&priv->lock); 2247 priv->hw->mac->set_filter(dev, priv->synopsys_id); 2248 spin_unlock(&priv->lock); 2249 } 2250 2251 /** 2252 * stmmac_change_mtu - entry point to change MTU size for the device. 2253 * @dev : device pointer. 2254 * @new_mtu : the new MTU size for the device. 2255 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2256 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2257 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2258 * Return value: 2259 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2260 * file on failure. 2261 */ 2262 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2263 { 2264 struct stmmac_priv *priv = netdev_priv(dev); 2265 int max_mtu; 2266 2267 if (netif_running(dev)) { 2268 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2269 return -EBUSY; 2270 } 2271 2272 if (priv->plat->enh_desc) 2273 max_mtu = JUMBO_LEN; 2274 else 2275 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2276 2277 if (priv->plat->maxmtu < max_mtu) 2278 max_mtu = priv->plat->maxmtu; 2279 2280 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2281 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2282 return -EINVAL; 2283 } 2284 2285 dev->mtu = new_mtu; 2286 netdev_update_features(dev); 2287 2288 return 0; 2289 } 2290 2291 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2292 netdev_features_t features) 2293 { 2294 struct stmmac_priv *priv = netdev_priv(dev); 2295 2296 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2297 features &= ~NETIF_F_RXCSUM; 2298 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 2299 features &= ~NETIF_F_IPV6_CSUM; 2300 if (!priv->plat->tx_coe) 2301 features &= ~NETIF_F_ALL_CSUM; 2302 2303 /* Some GMAC devices have a bugged Jumbo frame support that 2304 * needs to have the Tx COE disabled for oversized frames 2305 * (due to limited buffer sizes). In this case we disable 2306 * the TX csum insertionin the TDES and not use SF. 2307 */ 2308 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2309 features &= ~NETIF_F_ALL_CSUM; 2310 2311 return features; 2312 } 2313 2314 /** 2315 * stmmac_interrupt - main ISR 2316 * @irq: interrupt number. 2317 * @dev_id: to pass the net device pointer. 2318 * Description: this is the main driver interrupt service routine. 2319 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI 2320 * interrupts. 2321 */ 2322 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2323 { 2324 struct net_device *dev = (struct net_device *)dev_id; 2325 struct stmmac_priv *priv = netdev_priv(dev); 2326 2327 if (priv->irq_wake) 2328 pm_wakeup_event(priv->device, 0); 2329 2330 if (unlikely(!dev)) { 2331 pr_err("%s: invalid dev pointer\n", __func__); 2332 return IRQ_NONE; 2333 } 2334 2335 /* To handle GMAC own interrupts */ 2336 if (priv->plat->has_gmac) { 2337 int status = priv->hw->mac->host_irq_status((void __iomem *) 2338 dev->base_addr, 2339 &priv->xstats); 2340 if (unlikely(status)) { 2341 /* For LPI we need to save the tx status */ 2342 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2343 priv->tx_path_in_lpi_mode = true; 2344 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2345 priv->tx_path_in_lpi_mode = false; 2346 } 2347 } 2348 2349 /* To handle DMA interrupts */ 2350 stmmac_dma_interrupt(priv); 2351 2352 return IRQ_HANDLED; 2353 } 2354 2355 #ifdef CONFIG_NET_POLL_CONTROLLER 2356 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2357 * to allow network I/O with interrupts disabled. 2358 */ 2359 static void stmmac_poll_controller(struct net_device *dev) 2360 { 2361 disable_irq(dev->irq); 2362 stmmac_interrupt(dev->irq, dev); 2363 enable_irq(dev->irq); 2364 } 2365 #endif 2366 2367 /** 2368 * stmmac_ioctl - Entry point for the Ioctl 2369 * @dev: Device pointer. 2370 * @rq: An IOCTL specefic structure, that can contain a pointer to 2371 * a proprietary structure used to pass information to the driver. 2372 * @cmd: IOCTL command 2373 * Description: 2374 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2375 */ 2376 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2377 { 2378 struct stmmac_priv *priv = netdev_priv(dev); 2379 int ret = -EOPNOTSUPP; 2380 2381 if (!netif_running(dev)) 2382 return -EINVAL; 2383 2384 switch (cmd) { 2385 case SIOCGMIIPHY: 2386 case SIOCGMIIREG: 2387 case SIOCSMIIREG: 2388 if (!priv->phydev) 2389 return -EINVAL; 2390 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2391 break; 2392 case SIOCSHWTSTAMP: 2393 ret = stmmac_hwtstamp_ioctl(dev, rq); 2394 break; 2395 default: 2396 break; 2397 } 2398 2399 return ret; 2400 } 2401 2402 #ifdef CONFIG_STMMAC_DEBUG_FS 2403 static struct dentry *stmmac_fs_dir; 2404 static struct dentry *stmmac_rings_status; 2405 static struct dentry *stmmac_dma_cap; 2406 2407 static void sysfs_display_ring(void *head, int size, int extend_desc, 2408 struct seq_file *seq) 2409 { 2410 int i; 2411 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2412 struct dma_desc *p = (struct dma_desc *)head; 2413 2414 for (i = 0; i < size; i++) { 2415 u64 x; 2416 if (extend_desc) { 2417 x = *(u64 *) ep; 2418 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2419 i, (unsigned int)virt_to_phys(ep), 2420 (unsigned int)x, (unsigned int)(x >> 32), 2421 ep->basic.des2, ep->basic.des3); 2422 ep++; 2423 } else { 2424 x = *(u64 *) p; 2425 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2426 i, (unsigned int)virt_to_phys(ep), 2427 (unsigned int)x, (unsigned int)(x >> 32), 2428 p->des2, p->des3); 2429 p++; 2430 } 2431 seq_printf(seq, "\n"); 2432 } 2433 } 2434 2435 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2436 { 2437 struct net_device *dev = seq->private; 2438 struct stmmac_priv *priv = netdev_priv(dev); 2439 unsigned int txsize = priv->dma_tx_size; 2440 unsigned int rxsize = priv->dma_rx_size; 2441 2442 if (priv->extend_desc) { 2443 seq_printf(seq, "Extended RX descriptor ring:\n"); 2444 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2445 seq_printf(seq, "Extended TX descriptor ring:\n"); 2446 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2447 } else { 2448 seq_printf(seq, "RX descriptor ring:\n"); 2449 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2450 seq_printf(seq, "TX descriptor ring:\n"); 2451 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2458 { 2459 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2460 } 2461 2462 static const struct file_operations stmmac_rings_status_fops = { 2463 .owner = THIS_MODULE, 2464 .open = stmmac_sysfs_ring_open, 2465 .read = seq_read, 2466 .llseek = seq_lseek, 2467 .release = single_release, 2468 }; 2469 2470 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2471 { 2472 struct net_device *dev = seq->private; 2473 struct stmmac_priv *priv = netdev_priv(dev); 2474 2475 if (!priv->hw_cap_support) { 2476 seq_printf(seq, "DMA HW features not supported\n"); 2477 return 0; 2478 } 2479 2480 seq_printf(seq, "==============================\n"); 2481 seq_printf(seq, "\tDMA HW features\n"); 2482 seq_printf(seq, "==============================\n"); 2483 2484 seq_printf(seq, "\t10/100 Mbps %s\n", 2485 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2486 seq_printf(seq, "\t1000 Mbps %s\n", 2487 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2488 seq_printf(seq, "\tHalf duple %s\n", 2489 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2490 seq_printf(seq, "\tHash Filter: %s\n", 2491 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2492 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2493 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2494 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2495 (priv->dma_cap.pcs) ? "Y" : "N"); 2496 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2497 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2498 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2499 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2500 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2501 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2502 seq_printf(seq, "\tRMON module: %s\n", 2503 (priv->dma_cap.rmon) ? "Y" : "N"); 2504 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2505 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2506 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2507 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2508 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2509 (priv->dma_cap.eee) ? "Y" : "N"); 2510 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2511 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2512 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2513 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2514 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2515 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2516 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2517 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2518 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2519 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2520 priv->dma_cap.number_rx_channel); 2521 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2522 priv->dma_cap.number_tx_channel); 2523 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2524 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2525 2526 return 0; 2527 } 2528 2529 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2530 { 2531 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2532 } 2533 2534 static const struct file_operations stmmac_dma_cap_fops = { 2535 .owner = THIS_MODULE, 2536 .open = stmmac_sysfs_dma_cap_open, 2537 .read = seq_read, 2538 .llseek = seq_lseek, 2539 .release = single_release, 2540 }; 2541 2542 static int stmmac_init_fs(struct net_device *dev) 2543 { 2544 /* Create debugfs entries */ 2545 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 2546 2547 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 2548 pr_err("ERROR %s, debugfs create directory failed\n", 2549 STMMAC_RESOURCE_NAME); 2550 2551 return -ENOMEM; 2552 } 2553 2554 /* Entry to report DMA RX/TX rings */ 2555 stmmac_rings_status = debugfs_create_file("descriptors_status", 2556 S_IRUGO, stmmac_fs_dir, dev, 2557 &stmmac_rings_status_fops); 2558 2559 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 2560 pr_info("ERROR creating stmmac ring debugfs file\n"); 2561 debugfs_remove(stmmac_fs_dir); 2562 2563 return -ENOMEM; 2564 } 2565 2566 /* Entry to report the DMA HW features */ 2567 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 2568 dev, &stmmac_dma_cap_fops); 2569 2570 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 2571 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2572 debugfs_remove(stmmac_rings_status); 2573 debugfs_remove(stmmac_fs_dir); 2574 2575 return -ENOMEM; 2576 } 2577 2578 return 0; 2579 } 2580 2581 static void stmmac_exit_fs(void) 2582 { 2583 debugfs_remove(stmmac_rings_status); 2584 debugfs_remove(stmmac_dma_cap); 2585 debugfs_remove(stmmac_fs_dir); 2586 } 2587 #endif /* CONFIG_STMMAC_DEBUG_FS */ 2588 2589 static const struct net_device_ops stmmac_netdev_ops = { 2590 .ndo_open = stmmac_open, 2591 .ndo_start_xmit = stmmac_xmit, 2592 .ndo_stop = stmmac_release, 2593 .ndo_change_mtu = stmmac_change_mtu, 2594 .ndo_fix_features = stmmac_fix_features, 2595 .ndo_set_rx_mode = stmmac_set_rx_mode, 2596 .ndo_tx_timeout = stmmac_tx_timeout, 2597 .ndo_do_ioctl = stmmac_ioctl, 2598 .ndo_set_config = stmmac_config, 2599 #ifdef CONFIG_NET_POLL_CONTROLLER 2600 .ndo_poll_controller = stmmac_poll_controller, 2601 #endif 2602 .ndo_set_mac_address = eth_mac_addr, 2603 }; 2604 2605 /** 2606 * stmmac_hw_init - Init the MAC device 2607 * @priv: driver private structure 2608 * Description: this function detects which MAC device 2609 * (GMAC/MAC10-100) has to attached, checks the HW capability 2610 * (if supported) and sets the driver's features (for example 2611 * to use the ring or chaine mode or support the normal/enh 2612 * descriptor structure). 2613 */ 2614 static int stmmac_hw_init(struct stmmac_priv *priv) 2615 { 2616 int ret; 2617 struct mac_device_info *mac; 2618 2619 /* Identify the MAC HW device */ 2620 if (priv->plat->has_gmac) { 2621 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2622 mac = dwmac1000_setup(priv->ioaddr); 2623 } else { 2624 mac = dwmac100_setup(priv->ioaddr); 2625 } 2626 if (!mac) 2627 return -ENOMEM; 2628 2629 priv->hw = mac; 2630 2631 /* Get and dump the chip ID */ 2632 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2633 2634 /* To use the chained or ring mode */ 2635 if (chain_mode) { 2636 priv->hw->chain = &chain_mode_ops; 2637 pr_info(" Chain mode enabled\n"); 2638 priv->mode = STMMAC_CHAIN_MODE; 2639 } else { 2640 priv->hw->ring = &ring_mode_ops; 2641 pr_info(" Ring mode enabled\n"); 2642 priv->mode = STMMAC_RING_MODE; 2643 } 2644 2645 /* Get the HW capability (new GMAC newer than 3.50a) */ 2646 priv->hw_cap_support = stmmac_get_hw_features(priv); 2647 if (priv->hw_cap_support) { 2648 pr_info(" DMA HW capability register supported"); 2649 2650 /* We can override some gmac/dma configuration fields: e.g. 2651 * enh_desc, tx_coe (e.g. that are passed through the 2652 * platform) with the values from the HW capability 2653 * register (if supported). 2654 */ 2655 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2656 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2657 2658 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2659 2660 if (priv->dma_cap.rx_coe_type2) 2661 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2662 else if (priv->dma_cap.rx_coe_type1) 2663 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2664 2665 } else 2666 pr_info(" No HW DMA feature register supported"); 2667 2668 /* To use alternate (extended) or normal descriptor structures */ 2669 stmmac_selec_desc_mode(priv); 2670 2671 ret = priv->hw->mac->rx_ipc(priv->ioaddr); 2672 if (!ret) { 2673 pr_warn(" RX IPC Checksum Offload not configured.\n"); 2674 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2675 } 2676 2677 if (priv->plat->rx_coe) 2678 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2679 priv->plat->rx_coe); 2680 if (priv->plat->tx_coe) 2681 pr_info(" TX Checksum insertion supported\n"); 2682 2683 if (priv->plat->pmt) { 2684 pr_info(" Wake-Up On Lan supported\n"); 2685 device_set_wakeup_capable(priv->device, 1); 2686 } 2687 2688 return 0; 2689 } 2690 2691 /** 2692 * stmmac_dvr_probe 2693 * @device: device pointer 2694 * @plat_dat: platform data pointer 2695 * @addr: iobase memory address 2696 * Description: this is the main probe function used to 2697 * call the alloc_etherdev, allocate the priv structure. 2698 */ 2699 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 2700 struct plat_stmmacenet_data *plat_dat, 2701 void __iomem *addr) 2702 { 2703 int ret = 0; 2704 struct net_device *ndev = NULL; 2705 struct stmmac_priv *priv; 2706 2707 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2708 if (!ndev) 2709 return NULL; 2710 2711 SET_NETDEV_DEV(ndev, device); 2712 2713 priv = netdev_priv(ndev); 2714 priv->device = device; 2715 priv->dev = ndev; 2716 2717 ether_setup(ndev); 2718 2719 stmmac_set_ethtool_ops(ndev); 2720 priv->pause = pause; 2721 priv->plat = plat_dat; 2722 priv->ioaddr = addr; 2723 priv->dev->base_addr = (unsigned long)addr; 2724 2725 /* Verify driver arguments */ 2726 stmmac_verify_args(); 2727 2728 /* Override with kernel parameters if supplied XXX CRS XXX 2729 * this needs to have multiple instances 2730 */ 2731 if ((phyaddr >= 0) && (phyaddr <= 31)) 2732 priv->plat->phy_addr = phyaddr; 2733 2734 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2735 if (IS_ERR(priv->stmmac_clk)) { 2736 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2737 __func__); 2738 ret = PTR_ERR(priv->stmmac_clk); 2739 goto error_clk_get; 2740 } 2741 clk_prepare_enable(priv->stmmac_clk); 2742 2743 priv->stmmac_rst = devm_reset_control_get(priv->device, 2744 STMMAC_RESOURCE_NAME); 2745 if (IS_ERR(priv->stmmac_rst)) { 2746 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2747 ret = -EPROBE_DEFER; 2748 goto error_hw_init; 2749 } 2750 dev_info(priv->device, "no reset control found\n"); 2751 priv->stmmac_rst = NULL; 2752 } 2753 if (priv->stmmac_rst) 2754 reset_control_deassert(priv->stmmac_rst); 2755 2756 /* Init MAC and get the capabilities */ 2757 ret = stmmac_hw_init(priv); 2758 if (ret) 2759 goto error_hw_init; 2760 2761 ndev->netdev_ops = &stmmac_netdev_ops; 2762 2763 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2764 NETIF_F_RXCSUM; 2765 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2766 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2767 #ifdef STMMAC_VLAN_TAG_USED 2768 /* Both mac100 and gmac support receive VLAN tag detection */ 2769 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2770 #endif 2771 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2772 2773 if (flow_ctrl) 2774 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2775 2776 /* Rx Watchdog is available in the COREs newer than the 3.40. 2777 * In some case, for example on bugged HW this feature 2778 * has to be disable and this can be done by passing the 2779 * riwt_off field from the platform. 2780 */ 2781 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2782 priv->use_riwt = 1; 2783 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2784 } 2785 2786 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2787 2788 spin_lock_init(&priv->lock); 2789 spin_lock_init(&priv->tx_lock); 2790 2791 ret = register_netdev(ndev); 2792 if (ret) { 2793 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2794 goto error_netdev_register; 2795 } 2796 2797 /* If a specific clk_csr value is passed from the platform 2798 * this means that the CSR Clock Range selection cannot be 2799 * changed at run-time and it is fixed. Viceversa the driver'll try to 2800 * set the MDC clock dynamically according to the csr actual 2801 * clock input. 2802 */ 2803 if (!priv->plat->clk_csr) 2804 stmmac_clk_csr_set(priv); 2805 else 2806 priv->clk_csr = priv->plat->clk_csr; 2807 2808 stmmac_check_pcs_mode(priv); 2809 2810 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2811 priv->pcs != STMMAC_PCS_RTBI) { 2812 /* MDIO bus Registration */ 2813 ret = stmmac_mdio_register(ndev); 2814 if (ret < 0) { 2815 pr_debug("%s: MDIO bus (id: %d) registration failed", 2816 __func__, priv->plat->bus_id); 2817 goto error_mdio_register; 2818 } 2819 } 2820 2821 return priv; 2822 2823 error_mdio_register: 2824 unregister_netdev(ndev); 2825 error_netdev_register: 2826 netif_napi_del(&priv->napi); 2827 error_hw_init: 2828 clk_disable_unprepare(priv->stmmac_clk); 2829 error_clk_get: 2830 free_netdev(ndev); 2831 2832 return ERR_PTR(ret); 2833 } 2834 2835 /** 2836 * stmmac_dvr_remove 2837 * @ndev: net device pointer 2838 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2839 * changes the link status, releases the DMA descriptor rings. 2840 */ 2841 int stmmac_dvr_remove(struct net_device *ndev) 2842 { 2843 struct stmmac_priv *priv = netdev_priv(ndev); 2844 2845 pr_info("%s:\n\tremoving driver", __func__); 2846 2847 priv->hw->dma->stop_rx(priv->ioaddr); 2848 priv->hw->dma->stop_tx(priv->ioaddr); 2849 2850 stmmac_set_mac(priv->ioaddr, false); 2851 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2852 priv->pcs != STMMAC_PCS_RTBI) 2853 stmmac_mdio_unregister(ndev); 2854 netif_carrier_off(ndev); 2855 unregister_netdev(ndev); 2856 if (priv->stmmac_rst) 2857 reset_control_assert(priv->stmmac_rst); 2858 clk_disable_unprepare(priv->stmmac_clk); 2859 free_netdev(ndev); 2860 2861 return 0; 2862 } 2863 2864 #ifdef CONFIG_PM 2865 int stmmac_suspend(struct net_device *ndev) 2866 { 2867 struct stmmac_priv *priv = netdev_priv(ndev); 2868 unsigned long flags; 2869 2870 if (!ndev || !netif_running(ndev)) 2871 return 0; 2872 2873 if (priv->phydev) 2874 phy_stop(priv->phydev); 2875 2876 spin_lock_irqsave(&priv->lock, flags); 2877 2878 netif_device_detach(ndev); 2879 netif_stop_queue(ndev); 2880 2881 napi_disable(&priv->napi); 2882 2883 /* Stop TX/RX DMA */ 2884 priv->hw->dma->stop_tx(priv->ioaddr); 2885 priv->hw->dma->stop_rx(priv->ioaddr); 2886 2887 stmmac_clear_descriptors(priv); 2888 2889 /* Enable Power down mode by programming the PMT regs */ 2890 if (device_may_wakeup(priv->device)) { 2891 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 2892 priv->irq_wake = 1; 2893 } else { 2894 stmmac_set_mac(priv->ioaddr, false); 2895 pinctrl_pm_select_sleep_state(priv->device); 2896 /* Disable clock in case of PWM is off */ 2897 clk_disable_unprepare(priv->stmmac_clk); 2898 } 2899 spin_unlock_irqrestore(&priv->lock, flags); 2900 return 0; 2901 } 2902 2903 int stmmac_resume(struct net_device *ndev) 2904 { 2905 struct stmmac_priv *priv = netdev_priv(ndev); 2906 unsigned long flags; 2907 2908 if (!netif_running(ndev)) 2909 return 0; 2910 2911 spin_lock_irqsave(&priv->lock, flags); 2912 2913 /* Power Down bit, into the PM register, is cleared 2914 * automatically as soon as a magic packet or a Wake-up frame 2915 * is received. Anyway, it's better to manually clear 2916 * this bit because it can generate problems while resuming 2917 * from another devices (e.g. serial console). 2918 */ 2919 if (device_may_wakeup(priv->device)) { 2920 priv->hw->mac->pmt(priv->ioaddr, 0); 2921 priv->irq_wake = 0; 2922 } else { 2923 pinctrl_pm_select_default_state(priv->device); 2924 /* enable the clk prevously disabled */ 2925 clk_prepare_enable(priv->stmmac_clk); 2926 /* reset the phy so that it's ready */ 2927 if (priv->mii) 2928 stmmac_mdio_reset(priv->mii); 2929 } 2930 2931 netif_device_attach(ndev); 2932 2933 stmmac_hw_setup(ndev); 2934 2935 napi_enable(&priv->napi); 2936 2937 netif_start_queue(ndev); 2938 2939 spin_unlock_irqrestore(&priv->lock, flags); 2940 2941 if (priv->phydev) 2942 phy_start(priv->phydev); 2943 2944 return 0; 2945 } 2946 #endif /* CONFIG_PM */ 2947 2948 /* Driver can be configured w/ and w/ both PCI and Platf drivers 2949 * depending on the configuration selected. 2950 */ 2951 static int __init stmmac_init(void) 2952 { 2953 int ret; 2954 2955 ret = stmmac_register_platform(); 2956 if (ret) 2957 goto err; 2958 ret = stmmac_register_pci(); 2959 if (ret) 2960 goto err_pci; 2961 return 0; 2962 err_pci: 2963 stmmac_unregister_platform(); 2964 err: 2965 pr_err("stmmac: driver registration failed\n"); 2966 return ret; 2967 } 2968 2969 static void __exit stmmac_exit(void) 2970 { 2971 stmmac_unregister_platform(); 2972 stmmac_unregister_pci(); 2973 } 2974 2975 module_init(stmmac_init); 2976 module_exit(stmmac_exit); 2977 2978 #ifndef MODULE 2979 static int __init stmmac_cmdline_opt(char *str) 2980 { 2981 char *opt; 2982 2983 if (!str || !*str) 2984 return -EINVAL; 2985 while ((opt = strsep(&str, ",")) != NULL) { 2986 if (!strncmp(opt, "debug:", 6)) { 2987 if (kstrtoint(opt + 6, 0, &debug)) 2988 goto err; 2989 } else if (!strncmp(opt, "phyaddr:", 8)) { 2990 if (kstrtoint(opt + 8, 0, &phyaddr)) 2991 goto err; 2992 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2993 if (kstrtoint(opt + 11, 0, &dma_txsize)) 2994 goto err; 2995 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2996 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 2997 goto err; 2998 } else if (!strncmp(opt, "buf_sz:", 7)) { 2999 if (kstrtoint(opt + 7, 0, &buf_sz)) 3000 goto err; 3001 } else if (!strncmp(opt, "tc:", 3)) { 3002 if (kstrtoint(opt + 3, 0, &tc)) 3003 goto err; 3004 } else if (!strncmp(opt, "watchdog:", 9)) { 3005 if (kstrtoint(opt + 9, 0, &watchdog)) 3006 goto err; 3007 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3008 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3009 goto err; 3010 } else if (!strncmp(opt, "pause:", 6)) { 3011 if (kstrtoint(opt + 6, 0, &pause)) 3012 goto err; 3013 } else if (!strncmp(opt, "eee_timer:", 10)) { 3014 if (kstrtoint(opt + 10, 0, &eee_timer)) 3015 goto err; 3016 } else if (!strncmp(opt, "chain_mode:", 11)) { 3017 if (kstrtoint(opt + 11, 0, &chain_mode)) 3018 goto err; 3019 } 3020 } 3021 return 0; 3022 3023 err: 3024 pr_err("%s: ERROR broken module parameter conversion", __func__); 3025 return -EINVAL; 3026 } 3027 3028 __setup("stmmaceth=", stmmac_cmdline_opt); 3029 #endif /* MODULE */ 3030 3031 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3032 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3033 MODULE_LICENSE("GPL"); 3034