1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 67 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 180 { 181 if (!test_bit(STMMAC_DOWN, &priv->state) && 182 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 183 queue_work(priv->wq, &priv->service_task); 184 } 185 186 static void stmmac_global_err(struct stmmac_priv *priv) 187 { 188 netif_carrier_off(priv->dev); 189 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 190 stmmac_service_event_schedule(priv); 191 } 192 193 /** 194 * stmmac_clk_csr_set - dynamically set the MDC clock 195 * @priv: driver private structure 196 * Description: this is to dynamically set the MDC clock according to the csr 197 * clock input. 198 * Note: 199 * If a specific clk_csr value is passed from the platform 200 * this means that the CSR Clock Range selection cannot be 201 * changed at run-time and it is fixed (as reported in the driver 202 * documentation). Viceversa the driver will try to set the MDC 203 * clock dynamically according to the actual clock input. 204 */ 205 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 206 { 207 u32 clk_rate; 208 209 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 210 211 /* Platform provided default clk_csr would be assumed valid 212 * for all other cases except for the below mentioned ones. 213 * For values higher than the IEEE 802.3 specified frequency 214 * we can not estimate the proper divider as it is not known 215 * the frequency of clk_csr_i. So we do not change the default 216 * divider. 217 */ 218 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 219 if (clk_rate < CSR_F_35M) 220 priv->clk_csr = STMMAC_CSR_20_35M; 221 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 222 priv->clk_csr = STMMAC_CSR_35_60M; 223 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 224 priv->clk_csr = STMMAC_CSR_60_100M; 225 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 226 priv->clk_csr = STMMAC_CSR_100_150M; 227 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 228 priv->clk_csr = STMMAC_CSR_150_250M; 229 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 230 priv->clk_csr = STMMAC_CSR_250_300M; 231 } 232 233 if (priv->plat->has_sun8i) { 234 if (clk_rate > 160000000) 235 priv->clk_csr = 0x03; 236 else if (clk_rate > 80000000) 237 priv->clk_csr = 0x02; 238 else if (clk_rate > 40000000) 239 priv->clk_csr = 0x01; 240 else 241 priv->clk_csr = 0; 242 } 243 244 if (priv->plat->has_xgmac) { 245 if (clk_rate > 400000000) 246 priv->clk_csr = 0x5; 247 else if (clk_rate > 350000000) 248 priv->clk_csr = 0x4; 249 else if (clk_rate > 300000000) 250 priv->clk_csr = 0x3; 251 else if (clk_rate > 250000000) 252 priv->clk_csr = 0x2; 253 else if (clk_rate > 150000000) 254 priv->clk_csr = 0x1; 255 else 256 priv->clk_csr = 0x0; 257 } 258 } 259 260 static void print_pkt(unsigned char *buf, int len) 261 { 262 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 263 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 264 } 265 266 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 267 { 268 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 269 u32 avail; 270 271 if (tx_q->dirty_tx > tx_q->cur_tx) 272 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 273 else 274 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 275 276 return avail; 277 } 278 279 /** 280 * stmmac_rx_dirty - Get RX queue dirty 281 * @priv: driver private structure 282 * @queue: RX queue index 283 */ 284 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 285 { 286 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 287 u32 dirty; 288 289 if (rx_q->dirty_rx <= rx_q->cur_rx) 290 dirty = rx_q->cur_rx - rx_q->dirty_rx; 291 else 292 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 293 294 return dirty; 295 } 296 297 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 298 { 299 int tx_lpi_timer; 300 301 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 302 priv->eee_sw_timer_en = en ? 0 : 1; 303 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 304 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 305 } 306 307 /** 308 * stmmac_enable_eee_mode - check and enter in LPI mode 309 * @priv: driver private structure 310 * Description: this function is to verify and enter in LPI mode in case of 311 * EEE. 312 */ 313 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 314 { 315 u32 tx_cnt = priv->plat->tx_queues_to_use; 316 u32 queue; 317 318 /* check if all TX queues have the work finished */ 319 for (queue = 0; queue < tx_cnt; queue++) { 320 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 321 322 if (tx_q->dirty_tx != tx_q->cur_tx) 323 return; /* still unfinished work */ 324 } 325 326 /* Check and enter in LPI mode */ 327 if (!priv->tx_path_in_lpi_mode) 328 stmmac_set_eee_mode(priv, priv->hw, 329 priv->plat->en_tx_lpi_clockgating); 330 } 331 332 /** 333 * stmmac_disable_eee_mode - disable and exit from LPI mode 334 * @priv: driver private structure 335 * Description: this function is to exit and disable EEE in case of 336 * LPI state is true. This is called by the xmit. 337 */ 338 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 339 { 340 if (!priv->eee_sw_timer_en) { 341 stmmac_lpi_entry_timer_config(priv, 0); 342 return; 343 } 344 345 stmmac_reset_eee_mode(priv, priv->hw); 346 del_timer_sync(&priv->eee_ctrl_timer); 347 priv->tx_path_in_lpi_mode = false; 348 } 349 350 /** 351 * stmmac_eee_ctrl_timer - EEE TX SW timer. 352 * @t: timer_list struct containing private info 353 * Description: 354 * if there is no data transfer and if we are not in LPI state, 355 * then MAC Transmitter can be moved to LPI state. 356 */ 357 static void stmmac_eee_ctrl_timer(struct timer_list *t) 358 { 359 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 360 361 stmmac_enable_eee_mode(priv); 362 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 363 } 364 365 /** 366 * stmmac_eee_init - init EEE 367 * @priv: driver private structure 368 * Description: 369 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 370 * can also manage EEE, this function enable the LPI state and start related 371 * timer. 372 */ 373 bool stmmac_eee_init(struct stmmac_priv *priv) 374 { 375 int eee_tw_timer = priv->eee_tw_timer; 376 377 /* Using PCS we cannot dial with the phy registers at this stage 378 * so we do not support extra feature like EEE. 379 */ 380 if (priv->hw->pcs == STMMAC_PCS_TBI || 381 priv->hw->pcs == STMMAC_PCS_RTBI) 382 return false; 383 384 /* Check if MAC core supports the EEE feature. */ 385 if (!priv->dma_cap.eee) 386 return false; 387 388 mutex_lock(&priv->lock); 389 390 /* Check if it needs to be deactivated */ 391 if (!priv->eee_active) { 392 if (priv->eee_enabled) { 393 netdev_dbg(priv->dev, "disable EEE\n"); 394 stmmac_lpi_entry_timer_config(priv, 0); 395 del_timer_sync(&priv->eee_ctrl_timer); 396 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 397 } 398 mutex_unlock(&priv->lock); 399 return false; 400 } 401 402 if (priv->eee_active && !priv->eee_enabled) { 403 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 404 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 405 eee_tw_timer); 406 } 407 408 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 409 del_timer_sync(&priv->eee_ctrl_timer); 410 priv->tx_path_in_lpi_mode = false; 411 stmmac_lpi_entry_timer_config(priv, 1); 412 } else { 413 stmmac_lpi_entry_timer_config(priv, 0); 414 mod_timer(&priv->eee_ctrl_timer, 415 STMMAC_LPI_T(priv->tx_lpi_timer)); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 if (priv->synopsys_id != DWMAC_CORE_5_10) 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 * as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 clk_disable_unprepare(priv->plat->clk_ptp_ref); 791 stmmac_ptp_unregister(priv); 792 } 793 794 /** 795 * stmmac_mac_flow_ctrl - Configure flow control in all queues 796 * @priv: driver private structure 797 * @duplex: duplex passed to the next function 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 if (!max_speed || (max_speed >= 25000)) { 853 phylink_set(mac_supported, 25000baseCR_Full); 854 phylink_set(mac_supported, 25000baseKR_Full); 855 phylink_set(mac_supported, 25000baseSR_Full); 856 } 857 if (!max_speed || (max_speed >= 40000)) { 858 phylink_set(mac_supported, 40000baseKR4_Full); 859 phylink_set(mac_supported, 40000baseCR4_Full); 860 phylink_set(mac_supported, 40000baseSR4_Full); 861 phylink_set(mac_supported, 40000baseLR4_Full); 862 } 863 if (!max_speed || (max_speed >= 50000)) { 864 phylink_set(mac_supported, 50000baseCR2_Full); 865 phylink_set(mac_supported, 50000baseKR2_Full); 866 phylink_set(mac_supported, 50000baseSR2_Full); 867 phylink_set(mac_supported, 50000baseKR_Full); 868 phylink_set(mac_supported, 50000baseSR_Full); 869 phylink_set(mac_supported, 50000baseCR_Full); 870 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 871 phylink_set(mac_supported, 50000baseDR_Full); 872 } 873 if (!max_speed || (max_speed >= 100000)) { 874 phylink_set(mac_supported, 100000baseKR4_Full); 875 phylink_set(mac_supported, 100000baseSR4_Full); 876 phylink_set(mac_supported, 100000baseCR4_Full); 877 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 878 phylink_set(mac_supported, 100000baseKR2_Full); 879 phylink_set(mac_supported, 100000baseSR2_Full); 880 phylink_set(mac_supported, 100000baseCR2_Full); 881 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 882 phylink_set(mac_supported, 100000baseDR2_Full); 883 } 884 } 885 886 /* Half-Duplex can only work with single queue */ 887 if (tx_cnt > 1) { 888 phylink_set(mask, 10baseT_Half); 889 phylink_set(mask, 100baseT_Half); 890 phylink_set(mask, 1000baseT_Half); 891 } 892 893 linkmode_and(supported, supported, mac_supported); 894 linkmode_andnot(supported, supported, mask); 895 896 linkmode_and(state->advertising, state->advertising, mac_supported); 897 linkmode_andnot(state->advertising, state->advertising, mask); 898 899 /* If PCS is supported, check which modes it supports. */ 900 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 901 } 902 903 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 904 struct phylink_link_state *state) 905 { 906 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 907 908 state->link = 0; 909 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 910 } 911 912 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 913 const struct phylink_link_state *state) 914 { 915 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 916 917 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 918 } 919 920 static void stmmac_mac_an_restart(struct phylink_config *config) 921 { 922 /* Not Supported */ 923 } 924 925 static void stmmac_mac_link_down(struct phylink_config *config, 926 unsigned int mode, phy_interface_t interface) 927 { 928 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 929 930 stmmac_mac_set(priv, priv->ioaddr, false); 931 priv->eee_active = false; 932 priv->tx_lpi_enabled = false; 933 stmmac_eee_init(priv); 934 stmmac_set_eee_pls(priv, priv->hw, false); 935 } 936 937 static void stmmac_mac_link_up(struct phylink_config *config, 938 struct phy_device *phy, 939 unsigned int mode, phy_interface_t interface, 940 int speed, int duplex, 941 bool tx_pause, bool rx_pause) 942 { 943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 944 u32 ctrl; 945 946 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 947 948 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 949 ctrl &= ~priv->hw->link.speed_mask; 950 951 if (interface == PHY_INTERFACE_MODE_USXGMII) { 952 switch (speed) { 953 case SPEED_10000: 954 ctrl |= priv->hw->link.xgmii.speed10000; 955 break; 956 case SPEED_5000: 957 ctrl |= priv->hw->link.xgmii.speed5000; 958 break; 959 case SPEED_2500: 960 ctrl |= priv->hw->link.xgmii.speed2500; 961 break; 962 default: 963 return; 964 } 965 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 966 switch (speed) { 967 case SPEED_100000: 968 ctrl |= priv->hw->link.xlgmii.speed100000; 969 break; 970 case SPEED_50000: 971 ctrl |= priv->hw->link.xlgmii.speed50000; 972 break; 973 case SPEED_40000: 974 ctrl |= priv->hw->link.xlgmii.speed40000; 975 break; 976 case SPEED_25000: 977 ctrl |= priv->hw->link.xlgmii.speed25000; 978 break; 979 case SPEED_10000: 980 ctrl |= priv->hw->link.xgmii.speed10000; 981 break; 982 case SPEED_2500: 983 ctrl |= priv->hw->link.speed2500; 984 break; 985 case SPEED_1000: 986 ctrl |= priv->hw->link.speed1000; 987 break; 988 default: 989 return; 990 } 991 } else { 992 switch (speed) { 993 case SPEED_2500: 994 ctrl |= priv->hw->link.speed2500; 995 break; 996 case SPEED_1000: 997 ctrl |= priv->hw->link.speed1000; 998 break; 999 case SPEED_100: 1000 ctrl |= priv->hw->link.speed100; 1001 break; 1002 case SPEED_10: 1003 ctrl |= priv->hw->link.speed10; 1004 break; 1005 default: 1006 return; 1007 } 1008 } 1009 1010 priv->speed = speed; 1011 1012 if (priv->plat->fix_mac_speed) 1013 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1014 1015 if (!duplex) 1016 ctrl &= ~priv->hw->link.duplex; 1017 else 1018 ctrl |= priv->hw->link.duplex; 1019 1020 /* Flow Control operation */ 1021 if (tx_pause && rx_pause) 1022 stmmac_mac_flow_ctrl(priv, duplex); 1023 1024 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1025 1026 stmmac_mac_set(priv, priv->ioaddr, true); 1027 if (phy && priv->dma_cap.eee) { 1028 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1029 priv->eee_enabled = stmmac_eee_init(priv); 1030 priv->tx_lpi_enabled = priv->eee_enabled; 1031 stmmac_set_eee_pls(priv, priv->hw, true); 1032 } 1033 } 1034 1035 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1036 .validate = stmmac_validate, 1037 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1038 .mac_config = stmmac_mac_config, 1039 .mac_an_restart = stmmac_mac_an_restart, 1040 .mac_link_down = stmmac_mac_link_down, 1041 .mac_link_up = stmmac_mac_link_up, 1042 }; 1043 1044 /** 1045 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1046 * @priv: driver private structure 1047 * Description: this is to verify if the HW supports the PCS. 1048 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1049 * configured for the TBI, RTBI, or SGMII PHY interface. 1050 */ 1051 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1052 { 1053 int interface = priv->plat->interface; 1054 1055 if (priv->dma_cap.pcs) { 1056 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1057 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1058 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1059 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1060 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1061 priv->hw->pcs = STMMAC_PCS_RGMII; 1062 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1063 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1064 priv->hw->pcs = STMMAC_PCS_SGMII; 1065 } 1066 } 1067 } 1068 1069 /** 1070 * stmmac_init_phy - PHY initialization 1071 * @dev: net device structure 1072 * Description: it initializes the driver's PHY state, and attaches the PHY 1073 * to the mac driver. 1074 * Return value: 1075 * 0 on success 1076 */ 1077 static int stmmac_init_phy(struct net_device *dev) 1078 { 1079 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1080 struct stmmac_priv *priv = netdev_priv(dev); 1081 struct device_node *node; 1082 int ret; 1083 1084 node = priv->plat->phylink_node; 1085 1086 if (node) 1087 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1088 1089 /* Some DT bindings do not set-up the PHY handle. Let's try to 1090 * manually parse it 1091 */ 1092 if (!node || ret) { 1093 int addr = priv->plat->phy_addr; 1094 struct phy_device *phydev; 1095 1096 phydev = mdiobus_get_phy(priv->mii, addr); 1097 if (!phydev) { 1098 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1099 return -ENODEV; 1100 } 1101 1102 ret = phylink_connect_phy(priv->phylink, phydev); 1103 } 1104 1105 phylink_ethtool_get_wol(priv->phylink, &wol); 1106 device_set_wakeup_capable(priv->device, !!wol.supported); 1107 1108 return ret; 1109 } 1110 1111 static int stmmac_phy_setup(struct stmmac_priv *priv) 1112 { 1113 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1114 int mode = priv->plat->phy_interface; 1115 struct phylink *phylink; 1116 1117 priv->phylink_config.dev = &priv->dev->dev; 1118 priv->phylink_config.type = PHYLINK_NETDEV; 1119 priv->phylink_config.pcs_poll = true; 1120 1121 if (!fwnode) 1122 fwnode = dev_fwnode(priv->device); 1123 1124 phylink = phylink_create(&priv->phylink_config, fwnode, 1125 mode, &stmmac_phylink_mac_ops); 1126 if (IS_ERR(phylink)) 1127 return PTR_ERR(phylink); 1128 1129 priv->phylink = phylink; 1130 return 0; 1131 } 1132 1133 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1134 { 1135 u32 rx_cnt = priv->plat->rx_queues_to_use; 1136 void *head_rx; 1137 u32 queue; 1138 1139 /* Display RX rings */ 1140 for (queue = 0; queue < rx_cnt; queue++) { 1141 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1142 1143 pr_info("\tRX Queue %u rings\n", queue); 1144 1145 if (priv->extend_desc) 1146 head_rx = (void *)rx_q->dma_erx; 1147 else 1148 head_rx = (void *)rx_q->dma_rx; 1149 1150 /* Display RX ring */ 1151 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true); 1152 } 1153 } 1154 1155 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1156 { 1157 u32 tx_cnt = priv->plat->tx_queues_to_use; 1158 void *head_tx; 1159 u32 queue; 1160 1161 /* Display TX rings */ 1162 for (queue = 0; queue < tx_cnt; queue++) { 1163 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1164 1165 pr_info("\tTX Queue %d rings\n", queue); 1166 1167 if (priv->extend_desc) 1168 head_tx = (void *)tx_q->dma_etx; 1169 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1170 head_tx = (void *)tx_q->dma_entx; 1171 else 1172 head_tx = (void *)tx_q->dma_tx; 1173 1174 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false); 1175 } 1176 } 1177 1178 static void stmmac_display_rings(struct stmmac_priv *priv) 1179 { 1180 /* Display RX ring */ 1181 stmmac_display_rx_rings(priv); 1182 1183 /* Display TX ring */ 1184 stmmac_display_tx_rings(priv); 1185 } 1186 1187 static int stmmac_set_bfsize(int mtu, int bufsize) 1188 { 1189 int ret = bufsize; 1190 1191 if (mtu >= BUF_SIZE_8KiB) 1192 ret = BUF_SIZE_16KiB; 1193 else if (mtu >= BUF_SIZE_4KiB) 1194 ret = BUF_SIZE_8KiB; 1195 else if (mtu >= BUF_SIZE_2KiB) 1196 ret = BUF_SIZE_4KiB; 1197 else if (mtu > DEFAULT_BUFSIZE) 1198 ret = BUF_SIZE_2KiB; 1199 else 1200 ret = DEFAULT_BUFSIZE; 1201 1202 return ret; 1203 } 1204 1205 /** 1206 * stmmac_clear_rx_descriptors - clear RX descriptors 1207 * @priv: driver private structure 1208 * @queue: RX queue index 1209 * Description: this function is called to clear the RX descriptors 1210 * in case of both basic and extended descriptors are used. 1211 */ 1212 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1213 { 1214 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1215 int i; 1216 1217 /* Clear the RX descriptors */ 1218 for (i = 0; i < priv->dma_rx_size; i++) 1219 if (priv->extend_desc) 1220 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1221 priv->use_riwt, priv->mode, 1222 (i == priv->dma_rx_size - 1), 1223 priv->dma_buf_sz); 1224 else 1225 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1226 priv->use_riwt, priv->mode, 1227 (i == priv->dma_rx_size - 1), 1228 priv->dma_buf_sz); 1229 } 1230 1231 /** 1232 * stmmac_clear_tx_descriptors - clear tx descriptors 1233 * @priv: driver private structure 1234 * @queue: TX queue index. 1235 * Description: this function is called to clear the TX descriptors 1236 * in case of both basic and extended descriptors are used. 1237 */ 1238 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1239 { 1240 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1241 int i; 1242 1243 /* Clear the TX descriptors */ 1244 for (i = 0; i < priv->dma_tx_size; i++) { 1245 int last = (i == (priv->dma_tx_size - 1)); 1246 struct dma_desc *p; 1247 1248 if (priv->extend_desc) 1249 p = &tx_q->dma_etx[i].basic; 1250 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1251 p = &tx_q->dma_entx[i].basic; 1252 else 1253 p = &tx_q->dma_tx[i]; 1254 1255 stmmac_init_tx_desc(priv, p, priv->mode, last); 1256 } 1257 } 1258 1259 /** 1260 * stmmac_clear_descriptors - clear descriptors 1261 * @priv: driver private structure 1262 * Description: this function is called to clear the TX and RX descriptors 1263 * in case of both basic and extended descriptors are used. 1264 */ 1265 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1266 { 1267 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1268 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1269 u32 queue; 1270 1271 /* Clear the RX descriptors */ 1272 for (queue = 0; queue < rx_queue_cnt; queue++) 1273 stmmac_clear_rx_descriptors(priv, queue); 1274 1275 /* Clear the TX descriptors */ 1276 for (queue = 0; queue < tx_queue_cnt; queue++) 1277 stmmac_clear_tx_descriptors(priv, queue); 1278 } 1279 1280 /** 1281 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1282 * @priv: driver private structure 1283 * @p: descriptor pointer 1284 * @i: descriptor index 1285 * @flags: gfp flag 1286 * @queue: RX queue index 1287 * Description: this function is called to allocate a receive buffer, perform 1288 * the DMA mapping and init the descriptor. 1289 */ 1290 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1291 int i, gfp_t flags, u32 queue) 1292 { 1293 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1294 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1295 1296 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1297 if (!buf->page) 1298 return -ENOMEM; 1299 1300 if (priv->sph) { 1301 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1302 if (!buf->sec_page) 1303 return -ENOMEM; 1304 1305 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1306 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1307 } else { 1308 buf->sec_page = NULL; 1309 } 1310 1311 buf->addr = page_pool_get_dma_addr(buf->page); 1312 stmmac_set_desc_addr(priv, p, buf->addr); 1313 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1314 stmmac_init_desc3(priv, p); 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * stmmac_free_rx_buffer - free RX dma buffers 1321 * @priv: private structure 1322 * @queue: RX queue index 1323 * @i: buffer index. 1324 */ 1325 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1326 { 1327 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1328 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1329 1330 if (buf->page) 1331 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1332 buf->page = NULL; 1333 1334 if (buf->sec_page) 1335 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1336 buf->sec_page = NULL; 1337 } 1338 1339 /** 1340 * stmmac_free_tx_buffer - free RX dma buffers 1341 * @priv: private structure 1342 * @queue: RX queue index 1343 * @i: buffer index. 1344 */ 1345 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1346 { 1347 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1348 1349 if (tx_q->tx_skbuff_dma[i].buf) { 1350 if (tx_q->tx_skbuff_dma[i].map_as_page) 1351 dma_unmap_page(priv->device, 1352 tx_q->tx_skbuff_dma[i].buf, 1353 tx_q->tx_skbuff_dma[i].len, 1354 DMA_TO_DEVICE); 1355 else 1356 dma_unmap_single(priv->device, 1357 tx_q->tx_skbuff_dma[i].buf, 1358 tx_q->tx_skbuff_dma[i].len, 1359 DMA_TO_DEVICE); 1360 } 1361 1362 if (tx_q->tx_skbuff[i]) { 1363 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1364 tx_q->tx_skbuff[i] = NULL; 1365 tx_q->tx_skbuff_dma[i].buf = 0; 1366 tx_q->tx_skbuff_dma[i].map_as_page = false; 1367 } 1368 } 1369 1370 /** 1371 * init_dma_rx_desc_rings - init the RX descriptor rings 1372 * @dev: net device structure 1373 * @flags: gfp flag. 1374 * Description: this function initializes the DMA RX descriptors 1375 * and allocates the socket buffers. It supports the chained and ring 1376 * modes. 1377 */ 1378 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1379 { 1380 struct stmmac_priv *priv = netdev_priv(dev); 1381 u32 rx_count = priv->plat->rx_queues_to_use; 1382 int ret = -ENOMEM; 1383 int queue; 1384 int i; 1385 1386 /* RX INITIALIZATION */ 1387 netif_dbg(priv, probe, priv->dev, 1388 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1389 1390 for (queue = 0; queue < rx_count; queue++) { 1391 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1392 1393 netif_dbg(priv, probe, priv->dev, 1394 "(%s) dma_rx_phy=0x%08x\n", __func__, 1395 (u32)rx_q->dma_rx_phy); 1396 1397 stmmac_clear_rx_descriptors(priv, queue); 1398 1399 for (i = 0; i < priv->dma_rx_size; i++) { 1400 struct dma_desc *p; 1401 1402 if (priv->extend_desc) 1403 p = &((rx_q->dma_erx + i)->basic); 1404 else 1405 p = rx_q->dma_rx + i; 1406 1407 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1408 queue); 1409 if (ret) 1410 goto err_init_rx_buffers; 1411 } 1412 1413 rx_q->cur_rx = 0; 1414 rx_q->dirty_rx = (unsigned int)(i - priv->dma_rx_size); 1415 1416 /* Setup the chained descriptor addresses */ 1417 if (priv->mode == STMMAC_CHAIN_MODE) { 1418 if (priv->extend_desc) 1419 stmmac_mode_init(priv, rx_q->dma_erx, 1420 rx_q->dma_rx_phy, 1421 priv->dma_rx_size, 1); 1422 else 1423 stmmac_mode_init(priv, rx_q->dma_rx, 1424 rx_q->dma_rx_phy, 1425 priv->dma_rx_size, 0); 1426 } 1427 } 1428 1429 return 0; 1430 1431 err_init_rx_buffers: 1432 while (queue >= 0) { 1433 while (--i >= 0) 1434 stmmac_free_rx_buffer(priv, queue, i); 1435 1436 if (queue == 0) 1437 break; 1438 1439 i = priv->dma_rx_size; 1440 queue--; 1441 } 1442 1443 return ret; 1444 } 1445 1446 /** 1447 * init_dma_tx_desc_rings - init the TX descriptor rings 1448 * @dev: net device structure. 1449 * Description: this function initializes the DMA TX descriptors 1450 * and allocates the socket buffers. It supports the chained and ring 1451 * modes. 1452 */ 1453 static int init_dma_tx_desc_rings(struct net_device *dev) 1454 { 1455 struct stmmac_priv *priv = netdev_priv(dev); 1456 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1457 u32 queue; 1458 int i; 1459 1460 for (queue = 0; queue < tx_queue_cnt; queue++) { 1461 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1462 1463 netif_dbg(priv, probe, priv->dev, 1464 "(%s) dma_tx_phy=0x%08x\n", __func__, 1465 (u32)tx_q->dma_tx_phy); 1466 1467 /* Setup the chained descriptor addresses */ 1468 if (priv->mode == STMMAC_CHAIN_MODE) { 1469 if (priv->extend_desc) 1470 stmmac_mode_init(priv, tx_q->dma_etx, 1471 tx_q->dma_tx_phy, 1472 priv->dma_tx_size, 1); 1473 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1474 stmmac_mode_init(priv, tx_q->dma_tx, 1475 tx_q->dma_tx_phy, 1476 priv->dma_tx_size, 0); 1477 } 1478 1479 for (i = 0; i < priv->dma_tx_size; i++) { 1480 struct dma_desc *p; 1481 if (priv->extend_desc) 1482 p = &((tx_q->dma_etx + i)->basic); 1483 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1484 p = &((tx_q->dma_entx + i)->basic); 1485 else 1486 p = tx_q->dma_tx + i; 1487 1488 stmmac_clear_desc(priv, p); 1489 1490 tx_q->tx_skbuff_dma[i].buf = 0; 1491 tx_q->tx_skbuff_dma[i].map_as_page = false; 1492 tx_q->tx_skbuff_dma[i].len = 0; 1493 tx_q->tx_skbuff_dma[i].last_segment = false; 1494 tx_q->tx_skbuff[i] = NULL; 1495 } 1496 1497 tx_q->dirty_tx = 0; 1498 tx_q->cur_tx = 0; 1499 tx_q->mss = 0; 1500 1501 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1502 } 1503 1504 return 0; 1505 } 1506 1507 /** 1508 * init_dma_desc_rings - init the RX/TX descriptor rings 1509 * @dev: net device structure 1510 * @flags: gfp flag. 1511 * Description: this function initializes the DMA RX/TX descriptors 1512 * and allocates the socket buffers. It supports the chained and ring 1513 * modes. 1514 */ 1515 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1516 { 1517 struct stmmac_priv *priv = netdev_priv(dev); 1518 int ret; 1519 1520 ret = init_dma_rx_desc_rings(dev, flags); 1521 if (ret) 1522 return ret; 1523 1524 ret = init_dma_tx_desc_rings(dev); 1525 1526 stmmac_clear_descriptors(priv); 1527 1528 if (netif_msg_hw(priv)) 1529 stmmac_display_rings(priv); 1530 1531 return ret; 1532 } 1533 1534 /** 1535 * dma_free_rx_skbufs - free RX dma buffers 1536 * @priv: private structure 1537 * @queue: RX queue index 1538 */ 1539 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1540 { 1541 int i; 1542 1543 for (i = 0; i < priv->dma_rx_size; i++) 1544 stmmac_free_rx_buffer(priv, queue, i); 1545 } 1546 1547 /** 1548 * dma_free_tx_skbufs - free TX dma buffers 1549 * @priv: private structure 1550 * @queue: TX queue index 1551 */ 1552 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1553 { 1554 int i; 1555 1556 for (i = 0; i < priv->dma_tx_size; i++) 1557 stmmac_free_tx_buffer(priv, queue, i); 1558 } 1559 1560 /** 1561 * free_dma_rx_desc_resources - free RX dma desc resources 1562 * @priv: private structure 1563 */ 1564 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1565 { 1566 u32 rx_count = priv->plat->rx_queues_to_use; 1567 u32 queue; 1568 1569 /* Free RX queue resources */ 1570 for (queue = 0; queue < rx_count; queue++) { 1571 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1572 1573 /* Release the DMA RX socket buffers */ 1574 dma_free_rx_skbufs(priv, queue); 1575 1576 /* Free DMA regions of consistent memory previously allocated */ 1577 if (!priv->extend_desc) 1578 dma_free_coherent(priv->device, priv->dma_rx_size * 1579 sizeof(struct dma_desc), 1580 rx_q->dma_rx, rx_q->dma_rx_phy); 1581 else 1582 dma_free_coherent(priv->device, priv->dma_rx_size * 1583 sizeof(struct dma_extended_desc), 1584 rx_q->dma_erx, rx_q->dma_rx_phy); 1585 1586 kfree(rx_q->buf_pool); 1587 if (rx_q->page_pool) 1588 page_pool_destroy(rx_q->page_pool); 1589 } 1590 } 1591 1592 /** 1593 * free_dma_tx_desc_resources - free TX dma desc resources 1594 * @priv: private structure 1595 */ 1596 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1597 { 1598 u32 tx_count = priv->plat->tx_queues_to_use; 1599 u32 queue; 1600 1601 /* Free TX queue resources */ 1602 for (queue = 0; queue < tx_count; queue++) { 1603 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1604 size_t size; 1605 void *addr; 1606 1607 /* Release the DMA TX socket buffers */ 1608 dma_free_tx_skbufs(priv, queue); 1609 1610 if (priv->extend_desc) { 1611 size = sizeof(struct dma_extended_desc); 1612 addr = tx_q->dma_etx; 1613 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1614 size = sizeof(struct dma_edesc); 1615 addr = tx_q->dma_entx; 1616 } else { 1617 size = sizeof(struct dma_desc); 1618 addr = tx_q->dma_tx; 1619 } 1620 1621 size *= priv->dma_tx_size; 1622 1623 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1624 1625 kfree(tx_q->tx_skbuff_dma); 1626 kfree(tx_q->tx_skbuff); 1627 } 1628 } 1629 1630 /** 1631 * alloc_dma_rx_desc_resources - alloc RX resources. 1632 * @priv: private structure 1633 * Description: according to which descriptor can be used (extend or basic) 1634 * this function allocates the resources for TX and RX paths. In case of 1635 * reception, for example, it pre-allocated the RX socket buffer in order to 1636 * allow zero-copy mechanism. 1637 */ 1638 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1639 { 1640 u32 rx_count = priv->plat->rx_queues_to_use; 1641 int ret = -ENOMEM; 1642 u32 queue; 1643 1644 /* RX queues buffers and DMA */ 1645 for (queue = 0; queue < rx_count; queue++) { 1646 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1647 struct page_pool_params pp_params = { 0 }; 1648 unsigned int num_pages; 1649 1650 rx_q->queue_index = queue; 1651 rx_q->priv_data = priv; 1652 1653 pp_params.flags = PP_FLAG_DMA_MAP; 1654 pp_params.pool_size = priv->dma_rx_size; 1655 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1656 pp_params.order = ilog2(num_pages); 1657 pp_params.nid = dev_to_node(priv->device); 1658 pp_params.dev = priv->device; 1659 pp_params.dma_dir = DMA_FROM_DEVICE; 1660 1661 rx_q->page_pool = page_pool_create(&pp_params); 1662 if (IS_ERR(rx_q->page_pool)) { 1663 ret = PTR_ERR(rx_q->page_pool); 1664 rx_q->page_pool = NULL; 1665 goto err_dma; 1666 } 1667 1668 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1669 sizeof(*rx_q->buf_pool), 1670 GFP_KERNEL); 1671 if (!rx_q->buf_pool) 1672 goto err_dma; 1673 1674 if (priv->extend_desc) { 1675 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1676 priv->dma_rx_size * 1677 sizeof(struct dma_extended_desc), 1678 &rx_q->dma_rx_phy, 1679 GFP_KERNEL); 1680 if (!rx_q->dma_erx) 1681 goto err_dma; 1682 1683 } else { 1684 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1685 priv->dma_rx_size * 1686 sizeof(struct dma_desc), 1687 &rx_q->dma_rx_phy, 1688 GFP_KERNEL); 1689 if (!rx_q->dma_rx) 1690 goto err_dma; 1691 } 1692 } 1693 1694 return 0; 1695 1696 err_dma: 1697 free_dma_rx_desc_resources(priv); 1698 1699 return ret; 1700 } 1701 1702 /** 1703 * alloc_dma_tx_desc_resources - alloc TX resources. 1704 * @priv: private structure 1705 * Description: according to which descriptor can be used (extend or basic) 1706 * this function allocates the resources for TX and RX paths. In case of 1707 * reception, for example, it pre-allocated the RX socket buffer in order to 1708 * allow zero-copy mechanism. 1709 */ 1710 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1711 { 1712 u32 tx_count = priv->plat->tx_queues_to_use; 1713 int ret = -ENOMEM; 1714 u32 queue; 1715 1716 /* TX queues buffers and DMA */ 1717 for (queue = 0; queue < tx_count; queue++) { 1718 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1719 size_t size; 1720 void *addr; 1721 1722 tx_q->queue_index = queue; 1723 tx_q->priv_data = priv; 1724 1725 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 1726 sizeof(*tx_q->tx_skbuff_dma), 1727 GFP_KERNEL); 1728 if (!tx_q->tx_skbuff_dma) 1729 goto err_dma; 1730 1731 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 1732 sizeof(struct sk_buff *), 1733 GFP_KERNEL); 1734 if (!tx_q->tx_skbuff) 1735 goto err_dma; 1736 1737 if (priv->extend_desc) 1738 size = sizeof(struct dma_extended_desc); 1739 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1740 size = sizeof(struct dma_edesc); 1741 else 1742 size = sizeof(struct dma_desc); 1743 1744 size *= priv->dma_tx_size; 1745 1746 addr = dma_alloc_coherent(priv->device, size, 1747 &tx_q->dma_tx_phy, GFP_KERNEL); 1748 if (!addr) 1749 goto err_dma; 1750 1751 if (priv->extend_desc) 1752 tx_q->dma_etx = addr; 1753 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1754 tx_q->dma_entx = addr; 1755 else 1756 tx_q->dma_tx = addr; 1757 } 1758 1759 return 0; 1760 1761 err_dma: 1762 free_dma_tx_desc_resources(priv); 1763 return ret; 1764 } 1765 1766 /** 1767 * alloc_dma_desc_resources - alloc TX/RX resources. 1768 * @priv: private structure 1769 * Description: according to which descriptor can be used (extend or basic) 1770 * this function allocates the resources for TX and RX paths. In case of 1771 * reception, for example, it pre-allocated the RX socket buffer in order to 1772 * allow zero-copy mechanism. 1773 */ 1774 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1775 { 1776 /* RX Allocation */ 1777 int ret = alloc_dma_rx_desc_resources(priv); 1778 1779 if (ret) 1780 return ret; 1781 1782 ret = alloc_dma_tx_desc_resources(priv); 1783 1784 return ret; 1785 } 1786 1787 /** 1788 * free_dma_desc_resources - free dma desc resources 1789 * @priv: private structure 1790 */ 1791 static void free_dma_desc_resources(struct stmmac_priv *priv) 1792 { 1793 /* Release the DMA RX socket buffers */ 1794 free_dma_rx_desc_resources(priv); 1795 1796 /* Release the DMA TX socket buffers */ 1797 free_dma_tx_desc_resources(priv); 1798 } 1799 1800 /** 1801 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1802 * @priv: driver private structure 1803 * Description: It is used for enabling the rx queues in the MAC 1804 */ 1805 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1806 { 1807 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1808 int queue; 1809 u8 mode; 1810 1811 for (queue = 0; queue < rx_queues_count; queue++) { 1812 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1813 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1814 } 1815 } 1816 1817 /** 1818 * stmmac_start_rx_dma - start RX DMA channel 1819 * @priv: driver private structure 1820 * @chan: RX channel index 1821 * Description: 1822 * This starts a RX DMA channel 1823 */ 1824 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1825 { 1826 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1827 stmmac_start_rx(priv, priv->ioaddr, chan); 1828 } 1829 1830 /** 1831 * stmmac_start_tx_dma - start TX DMA channel 1832 * @priv: driver private structure 1833 * @chan: TX channel index 1834 * Description: 1835 * This starts a TX DMA channel 1836 */ 1837 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1838 { 1839 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1840 stmmac_start_tx(priv, priv->ioaddr, chan); 1841 } 1842 1843 /** 1844 * stmmac_stop_rx_dma - stop RX DMA channel 1845 * @priv: driver private structure 1846 * @chan: RX channel index 1847 * Description: 1848 * This stops a RX DMA channel 1849 */ 1850 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1851 { 1852 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1853 stmmac_stop_rx(priv, priv->ioaddr, chan); 1854 } 1855 1856 /** 1857 * stmmac_stop_tx_dma - stop TX DMA channel 1858 * @priv: driver private structure 1859 * @chan: TX channel index 1860 * Description: 1861 * This stops a TX DMA channel 1862 */ 1863 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1864 { 1865 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1866 stmmac_stop_tx(priv, priv->ioaddr, chan); 1867 } 1868 1869 /** 1870 * stmmac_start_all_dma - start all RX and TX DMA channels 1871 * @priv: driver private structure 1872 * Description: 1873 * This starts all the RX and TX DMA channels 1874 */ 1875 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1876 { 1877 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1878 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1879 u32 chan = 0; 1880 1881 for (chan = 0; chan < rx_channels_count; chan++) 1882 stmmac_start_rx_dma(priv, chan); 1883 1884 for (chan = 0; chan < tx_channels_count; chan++) 1885 stmmac_start_tx_dma(priv, chan); 1886 } 1887 1888 /** 1889 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1890 * @priv: driver private structure 1891 * Description: 1892 * This stops the RX and TX DMA channels 1893 */ 1894 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1895 { 1896 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1897 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1898 u32 chan = 0; 1899 1900 for (chan = 0; chan < rx_channels_count; chan++) 1901 stmmac_stop_rx_dma(priv, chan); 1902 1903 for (chan = 0; chan < tx_channels_count; chan++) 1904 stmmac_stop_tx_dma(priv, chan); 1905 } 1906 1907 /** 1908 * stmmac_dma_operation_mode - HW DMA operation mode 1909 * @priv: driver private structure 1910 * Description: it is used for configuring the DMA operation mode register in 1911 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1912 */ 1913 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1914 { 1915 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1916 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1917 int rxfifosz = priv->plat->rx_fifo_size; 1918 int txfifosz = priv->plat->tx_fifo_size; 1919 u32 txmode = 0; 1920 u32 rxmode = 0; 1921 u32 chan = 0; 1922 u8 qmode = 0; 1923 1924 if (rxfifosz == 0) 1925 rxfifosz = priv->dma_cap.rx_fifo_size; 1926 if (txfifosz == 0) 1927 txfifosz = priv->dma_cap.tx_fifo_size; 1928 1929 /* Adjust for real per queue fifo size */ 1930 rxfifosz /= rx_channels_count; 1931 txfifosz /= tx_channels_count; 1932 1933 if (priv->plat->force_thresh_dma_mode) { 1934 txmode = tc; 1935 rxmode = tc; 1936 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1937 /* 1938 * In case of GMAC, SF mode can be enabled 1939 * to perform the TX COE in HW. This depends on: 1940 * 1) TX COE if actually supported 1941 * 2) There is no bugged Jumbo frame support 1942 * that needs to not insert csum in the TDES. 1943 */ 1944 txmode = SF_DMA_MODE; 1945 rxmode = SF_DMA_MODE; 1946 priv->xstats.threshold = SF_DMA_MODE; 1947 } else { 1948 txmode = tc; 1949 rxmode = SF_DMA_MODE; 1950 } 1951 1952 /* configure all channels */ 1953 for (chan = 0; chan < rx_channels_count; chan++) { 1954 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1955 1956 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1957 rxfifosz, qmode); 1958 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1959 chan); 1960 } 1961 1962 for (chan = 0; chan < tx_channels_count; chan++) { 1963 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1964 1965 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1966 txfifosz, qmode); 1967 } 1968 } 1969 1970 /** 1971 * stmmac_tx_clean - to manage the transmission completion 1972 * @priv: driver private structure 1973 * @budget: napi budget limiting this functions packet handling 1974 * @queue: TX queue index 1975 * Description: it reclaims the transmit resources after transmission completes. 1976 */ 1977 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1978 { 1979 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1980 unsigned int bytes_compl = 0, pkts_compl = 0; 1981 unsigned int entry, count = 0; 1982 1983 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1984 1985 priv->xstats.tx_clean++; 1986 1987 entry = tx_q->dirty_tx; 1988 while ((entry != tx_q->cur_tx) && (count < budget)) { 1989 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1990 struct dma_desc *p; 1991 int status; 1992 1993 if (priv->extend_desc) 1994 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1995 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1996 p = &tx_q->dma_entx[entry].basic; 1997 else 1998 p = tx_q->dma_tx + entry; 1999 2000 status = stmmac_tx_status(priv, &priv->dev->stats, 2001 &priv->xstats, p, priv->ioaddr); 2002 /* Check if the descriptor is owned by the DMA */ 2003 if (unlikely(status & tx_dma_own)) 2004 break; 2005 2006 count++; 2007 2008 /* Make sure descriptor fields are read after reading 2009 * the own bit. 2010 */ 2011 dma_rmb(); 2012 2013 /* Just consider the last segment and ...*/ 2014 if (likely(!(status & tx_not_ls))) { 2015 /* ... verify the status error condition */ 2016 if (unlikely(status & tx_err)) { 2017 priv->dev->stats.tx_errors++; 2018 } else { 2019 priv->dev->stats.tx_packets++; 2020 priv->xstats.tx_pkt_n++; 2021 } 2022 stmmac_get_tx_hwtstamp(priv, p, skb); 2023 } 2024 2025 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2026 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2027 dma_unmap_page(priv->device, 2028 tx_q->tx_skbuff_dma[entry].buf, 2029 tx_q->tx_skbuff_dma[entry].len, 2030 DMA_TO_DEVICE); 2031 else 2032 dma_unmap_single(priv->device, 2033 tx_q->tx_skbuff_dma[entry].buf, 2034 tx_q->tx_skbuff_dma[entry].len, 2035 DMA_TO_DEVICE); 2036 tx_q->tx_skbuff_dma[entry].buf = 0; 2037 tx_q->tx_skbuff_dma[entry].len = 0; 2038 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2039 } 2040 2041 stmmac_clean_desc3(priv, tx_q, p); 2042 2043 tx_q->tx_skbuff_dma[entry].last_segment = false; 2044 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2045 2046 if (likely(skb != NULL)) { 2047 pkts_compl++; 2048 bytes_compl += skb->len; 2049 dev_consume_skb_any(skb); 2050 tx_q->tx_skbuff[entry] = NULL; 2051 } 2052 2053 stmmac_release_tx_desc(priv, p, priv->mode); 2054 2055 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2056 } 2057 tx_q->dirty_tx = entry; 2058 2059 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2060 pkts_compl, bytes_compl); 2061 2062 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2063 queue))) && 2064 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2065 2066 netif_dbg(priv, tx_done, priv->dev, 2067 "%s: restart transmit\n", __func__); 2068 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2069 } 2070 2071 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2072 priv->eee_sw_timer_en) { 2073 stmmac_enable_eee_mode(priv); 2074 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2075 } 2076 2077 /* We still have pending packets, let's call for a new scheduling */ 2078 if (tx_q->dirty_tx != tx_q->cur_tx) 2079 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2080 2081 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2082 2083 return count; 2084 } 2085 2086 /** 2087 * stmmac_tx_err - to manage the tx error 2088 * @priv: driver private structure 2089 * @chan: channel index 2090 * Description: it cleans the descriptors and restarts the transmission 2091 * in case of transmission errors. 2092 */ 2093 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2094 { 2095 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2096 2097 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2098 2099 stmmac_stop_tx_dma(priv, chan); 2100 dma_free_tx_skbufs(priv, chan); 2101 stmmac_clear_tx_descriptors(priv, chan); 2102 tx_q->dirty_tx = 0; 2103 tx_q->cur_tx = 0; 2104 tx_q->mss = 0; 2105 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2106 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2107 tx_q->dma_tx_phy, chan); 2108 stmmac_start_tx_dma(priv, chan); 2109 2110 priv->dev->stats.tx_errors++; 2111 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2112 } 2113 2114 /** 2115 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2116 * @priv: driver private structure 2117 * @txmode: TX operating mode 2118 * @rxmode: RX operating mode 2119 * @chan: channel index 2120 * Description: it is used for configuring of the DMA operation mode in 2121 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2122 * mode. 2123 */ 2124 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2125 u32 rxmode, u32 chan) 2126 { 2127 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2128 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2129 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2130 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2131 int rxfifosz = priv->plat->rx_fifo_size; 2132 int txfifosz = priv->plat->tx_fifo_size; 2133 2134 if (rxfifosz == 0) 2135 rxfifosz = priv->dma_cap.rx_fifo_size; 2136 if (txfifosz == 0) 2137 txfifosz = priv->dma_cap.tx_fifo_size; 2138 2139 /* Adjust for real per queue fifo size */ 2140 rxfifosz /= rx_channels_count; 2141 txfifosz /= tx_channels_count; 2142 2143 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2144 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2145 } 2146 2147 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2148 { 2149 int ret; 2150 2151 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2152 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2153 if (ret && (ret != -EINVAL)) { 2154 stmmac_global_err(priv); 2155 return true; 2156 } 2157 2158 return false; 2159 } 2160 2161 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2162 { 2163 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2164 &priv->xstats, chan); 2165 struct stmmac_channel *ch = &priv->channel[chan]; 2166 unsigned long flags; 2167 2168 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2169 if (napi_schedule_prep(&ch->rx_napi)) { 2170 spin_lock_irqsave(&ch->lock, flags); 2171 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2172 spin_unlock_irqrestore(&ch->lock, flags); 2173 __napi_schedule_irqoff(&ch->rx_napi); 2174 } 2175 } 2176 2177 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2178 if (napi_schedule_prep(&ch->tx_napi)) { 2179 spin_lock_irqsave(&ch->lock, flags); 2180 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2181 spin_unlock_irqrestore(&ch->lock, flags); 2182 __napi_schedule_irqoff(&ch->tx_napi); 2183 } 2184 } 2185 2186 return status; 2187 } 2188 2189 /** 2190 * stmmac_dma_interrupt - DMA ISR 2191 * @priv: driver private structure 2192 * Description: this is the DMA ISR. It is called by the main ISR. 2193 * It calls the dwmac dma routine and schedule poll method in case of some 2194 * work can be done. 2195 */ 2196 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2197 { 2198 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2199 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2200 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2201 tx_channel_count : rx_channel_count; 2202 u32 chan; 2203 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2204 2205 /* Make sure we never check beyond our status buffer. */ 2206 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2207 channels_to_check = ARRAY_SIZE(status); 2208 2209 for (chan = 0; chan < channels_to_check; chan++) 2210 status[chan] = stmmac_napi_check(priv, chan); 2211 2212 for (chan = 0; chan < tx_channel_count; chan++) { 2213 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2214 /* Try to bump up the dma threshold on this failure */ 2215 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2216 (tc <= 256)) { 2217 tc += 64; 2218 if (priv->plat->force_thresh_dma_mode) 2219 stmmac_set_dma_operation_mode(priv, 2220 tc, 2221 tc, 2222 chan); 2223 else 2224 stmmac_set_dma_operation_mode(priv, 2225 tc, 2226 SF_DMA_MODE, 2227 chan); 2228 priv->xstats.threshold = tc; 2229 } 2230 } else if (unlikely(status[chan] == tx_hard_error)) { 2231 stmmac_tx_err(priv, chan); 2232 } 2233 } 2234 } 2235 2236 /** 2237 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2238 * @priv: driver private structure 2239 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2240 */ 2241 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2242 { 2243 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2244 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2245 2246 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2247 2248 if (priv->dma_cap.rmon) { 2249 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2250 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2251 } else 2252 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2253 } 2254 2255 /** 2256 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2257 * @priv: driver private structure 2258 * Description: 2259 * new GMAC chip generations have a new register to indicate the 2260 * presence of the optional feature/functions. 2261 * This can be also used to override the value passed through the 2262 * platform and necessary for old MAC10/100 and GMAC chips. 2263 */ 2264 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2265 { 2266 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2267 } 2268 2269 /** 2270 * stmmac_check_ether_addr - check if the MAC addr is valid 2271 * @priv: driver private structure 2272 * Description: 2273 * it is to verify if the MAC address is valid, in case of failures it 2274 * generates a random MAC address 2275 */ 2276 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2277 { 2278 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2279 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2280 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2281 eth_hw_addr_random(priv->dev); 2282 dev_info(priv->device, "device MAC address %pM\n", 2283 priv->dev->dev_addr); 2284 } 2285 } 2286 2287 /** 2288 * stmmac_init_dma_engine - DMA init. 2289 * @priv: driver private structure 2290 * Description: 2291 * It inits the DMA invoking the specific MAC/GMAC callback. 2292 * Some DMA parameters can be passed from the platform; 2293 * in case of these are not passed a default is kept for the MAC or GMAC. 2294 */ 2295 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2296 { 2297 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2298 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2299 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2300 struct stmmac_rx_queue *rx_q; 2301 struct stmmac_tx_queue *tx_q; 2302 u32 chan = 0; 2303 int atds = 0; 2304 int ret = 0; 2305 2306 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2307 dev_err(priv->device, "Invalid DMA configuration\n"); 2308 return -EINVAL; 2309 } 2310 2311 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2312 atds = 1; 2313 2314 ret = stmmac_reset(priv, priv->ioaddr); 2315 if (ret) { 2316 dev_err(priv->device, "Failed to reset the dma\n"); 2317 return ret; 2318 } 2319 2320 /* DMA Configuration */ 2321 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2322 2323 if (priv->plat->axi) 2324 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2325 2326 /* DMA CSR Channel configuration */ 2327 for (chan = 0; chan < dma_csr_ch; chan++) 2328 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2329 2330 /* DMA RX Channel Configuration */ 2331 for (chan = 0; chan < rx_channels_count; chan++) { 2332 rx_q = &priv->rx_queue[chan]; 2333 2334 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2335 rx_q->dma_rx_phy, chan); 2336 2337 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2338 (priv->dma_rx_size * 2339 sizeof(struct dma_desc)); 2340 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2341 rx_q->rx_tail_addr, chan); 2342 } 2343 2344 /* DMA TX Channel Configuration */ 2345 for (chan = 0; chan < tx_channels_count; chan++) { 2346 tx_q = &priv->tx_queue[chan]; 2347 2348 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2349 tx_q->dma_tx_phy, chan); 2350 2351 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2352 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2353 tx_q->tx_tail_addr, chan); 2354 } 2355 2356 return ret; 2357 } 2358 2359 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2360 { 2361 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2362 2363 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2364 } 2365 2366 /** 2367 * stmmac_tx_timer - mitigation sw timer for tx. 2368 * @t: data pointer 2369 * Description: 2370 * This is the timer handler to directly invoke the stmmac_tx_clean. 2371 */ 2372 static void stmmac_tx_timer(struct timer_list *t) 2373 { 2374 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2375 struct stmmac_priv *priv = tx_q->priv_data; 2376 struct stmmac_channel *ch; 2377 2378 ch = &priv->channel[tx_q->queue_index]; 2379 2380 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2381 unsigned long flags; 2382 2383 spin_lock_irqsave(&ch->lock, flags); 2384 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2385 spin_unlock_irqrestore(&ch->lock, flags); 2386 __napi_schedule(&ch->tx_napi); 2387 } 2388 } 2389 2390 /** 2391 * stmmac_init_coalesce - init mitigation options. 2392 * @priv: driver private structure 2393 * Description: 2394 * This inits the coalesce parameters: i.e. timer rate, 2395 * timer handler and default threshold used for enabling the 2396 * interrupt on completion bit. 2397 */ 2398 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2399 { 2400 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2401 u32 chan; 2402 2403 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2404 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2405 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2406 2407 for (chan = 0; chan < tx_channel_count; chan++) { 2408 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2409 2410 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2411 } 2412 } 2413 2414 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2415 { 2416 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2417 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2418 u32 chan; 2419 2420 /* set TX ring length */ 2421 for (chan = 0; chan < tx_channels_count; chan++) 2422 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2423 (priv->dma_tx_size - 1), chan); 2424 2425 /* set RX ring length */ 2426 for (chan = 0; chan < rx_channels_count; chan++) 2427 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2428 (priv->dma_rx_size - 1), chan); 2429 } 2430 2431 /** 2432 * stmmac_set_tx_queue_weight - Set TX queue weight 2433 * @priv: driver private structure 2434 * Description: It is used for setting TX queues weight 2435 */ 2436 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2437 { 2438 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2439 u32 weight; 2440 u32 queue; 2441 2442 for (queue = 0; queue < tx_queues_count; queue++) { 2443 weight = priv->plat->tx_queues_cfg[queue].weight; 2444 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2445 } 2446 } 2447 2448 /** 2449 * stmmac_configure_cbs - Configure CBS in TX queue 2450 * @priv: driver private structure 2451 * Description: It is used for configuring CBS in AVB TX queues 2452 */ 2453 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2454 { 2455 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2456 u32 mode_to_use; 2457 u32 queue; 2458 2459 /* queue 0 is reserved for legacy traffic */ 2460 for (queue = 1; queue < tx_queues_count; queue++) { 2461 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2462 if (mode_to_use == MTL_QUEUE_DCB) 2463 continue; 2464 2465 stmmac_config_cbs(priv, priv->hw, 2466 priv->plat->tx_queues_cfg[queue].send_slope, 2467 priv->plat->tx_queues_cfg[queue].idle_slope, 2468 priv->plat->tx_queues_cfg[queue].high_credit, 2469 priv->plat->tx_queues_cfg[queue].low_credit, 2470 queue); 2471 } 2472 } 2473 2474 /** 2475 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2476 * @priv: driver private structure 2477 * Description: It is used for mapping RX queues to RX dma channels 2478 */ 2479 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2480 { 2481 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2482 u32 queue; 2483 u32 chan; 2484 2485 for (queue = 0; queue < rx_queues_count; queue++) { 2486 chan = priv->plat->rx_queues_cfg[queue].chan; 2487 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2488 } 2489 } 2490 2491 /** 2492 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2493 * @priv: driver private structure 2494 * Description: It is used for configuring the RX Queue Priority 2495 */ 2496 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2497 { 2498 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2499 u32 queue; 2500 u32 prio; 2501 2502 for (queue = 0; queue < rx_queues_count; queue++) { 2503 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2504 continue; 2505 2506 prio = priv->plat->rx_queues_cfg[queue].prio; 2507 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2508 } 2509 } 2510 2511 /** 2512 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2513 * @priv: driver private structure 2514 * Description: It is used for configuring the TX Queue Priority 2515 */ 2516 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2517 { 2518 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2519 u32 queue; 2520 u32 prio; 2521 2522 for (queue = 0; queue < tx_queues_count; queue++) { 2523 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2524 continue; 2525 2526 prio = priv->plat->tx_queues_cfg[queue].prio; 2527 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2528 } 2529 } 2530 2531 /** 2532 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2533 * @priv: driver private structure 2534 * Description: It is used for configuring the RX queue routing 2535 */ 2536 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2537 { 2538 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2539 u32 queue; 2540 u8 packet; 2541 2542 for (queue = 0; queue < rx_queues_count; queue++) { 2543 /* no specific packet type routing specified for the queue */ 2544 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2545 continue; 2546 2547 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2548 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2549 } 2550 } 2551 2552 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2553 { 2554 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2555 priv->rss.enable = false; 2556 return; 2557 } 2558 2559 if (priv->dev->features & NETIF_F_RXHASH) 2560 priv->rss.enable = true; 2561 else 2562 priv->rss.enable = false; 2563 2564 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2565 priv->plat->rx_queues_to_use); 2566 } 2567 2568 /** 2569 * stmmac_mtl_configuration - Configure MTL 2570 * @priv: driver private structure 2571 * Description: It is used for configurring MTL 2572 */ 2573 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2574 { 2575 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2576 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2577 2578 if (tx_queues_count > 1) 2579 stmmac_set_tx_queue_weight(priv); 2580 2581 /* Configure MTL RX algorithms */ 2582 if (rx_queues_count > 1) 2583 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2584 priv->plat->rx_sched_algorithm); 2585 2586 /* Configure MTL TX algorithms */ 2587 if (tx_queues_count > 1) 2588 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2589 priv->plat->tx_sched_algorithm); 2590 2591 /* Configure CBS in AVB TX queues */ 2592 if (tx_queues_count > 1) 2593 stmmac_configure_cbs(priv); 2594 2595 /* Map RX MTL to DMA channels */ 2596 stmmac_rx_queue_dma_chan_map(priv); 2597 2598 /* Enable MAC RX Queues */ 2599 stmmac_mac_enable_rx_queues(priv); 2600 2601 /* Set RX priorities */ 2602 if (rx_queues_count > 1) 2603 stmmac_mac_config_rx_queues_prio(priv); 2604 2605 /* Set TX priorities */ 2606 if (tx_queues_count > 1) 2607 stmmac_mac_config_tx_queues_prio(priv); 2608 2609 /* Set RX routing */ 2610 if (rx_queues_count > 1) 2611 stmmac_mac_config_rx_queues_routing(priv); 2612 2613 /* Receive Side Scaling */ 2614 if (rx_queues_count > 1) 2615 stmmac_mac_config_rss(priv); 2616 } 2617 2618 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2619 { 2620 if (priv->dma_cap.asp) { 2621 netdev_info(priv->dev, "Enabling Safety Features\n"); 2622 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2623 } else { 2624 netdev_info(priv->dev, "No Safety Features support found\n"); 2625 } 2626 } 2627 2628 /** 2629 * stmmac_hw_setup - setup mac in a usable state. 2630 * @dev : pointer to the device structure. 2631 * @init_ptp: initialize PTP if set 2632 * Description: 2633 * this is the main function to setup the HW in a usable state because the 2634 * dma engine is reset, the core registers are configured (e.g. AXI, 2635 * Checksum features, timers). The DMA is ready to start receiving and 2636 * transmitting. 2637 * Return value: 2638 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2639 * file on failure. 2640 */ 2641 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2642 { 2643 struct stmmac_priv *priv = netdev_priv(dev); 2644 u32 rx_cnt = priv->plat->rx_queues_to_use; 2645 u32 tx_cnt = priv->plat->tx_queues_to_use; 2646 u32 chan; 2647 int ret; 2648 2649 /* DMA initialization and SW reset */ 2650 ret = stmmac_init_dma_engine(priv); 2651 if (ret < 0) { 2652 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2653 __func__); 2654 return ret; 2655 } 2656 2657 /* Copy the MAC addr into the HW */ 2658 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2659 2660 /* PS and related bits will be programmed according to the speed */ 2661 if (priv->hw->pcs) { 2662 int speed = priv->plat->mac_port_sel_speed; 2663 2664 if ((speed == SPEED_10) || (speed == SPEED_100) || 2665 (speed == SPEED_1000)) { 2666 priv->hw->ps = speed; 2667 } else { 2668 dev_warn(priv->device, "invalid port speed\n"); 2669 priv->hw->ps = 0; 2670 } 2671 } 2672 2673 /* Initialize the MAC Core */ 2674 stmmac_core_init(priv, priv->hw, dev); 2675 2676 /* Initialize MTL*/ 2677 stmmac_mtl_configuration(priv); 2678 2679 /* Initialize Safety Features */ 2680 stmmac_safety_feat_configuration(priv); 2681 2682 ret = stmmac_rx_ipc(priv, priv->hw); 2683 if (!ret) { 2684 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2685 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2686 priv->hw->rx_csum = 0; 2687 } 2688 2689 /* Enable the MAC Rx/Tx */ 2690 stmmac_mac_set(priv, priv->ioaddr, true); 2691 2692 /* Set the HW DMA mode and the COE */ 2693 stmmac_dma_operation_mode(priv); 2694 2695 stmmac_mmc_setup(priv); 2696 2697 if (init_ptp) { 2698 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2699 if (ret < 0) 2700 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2701 2702 ret = stmmac_init_ptp(priv); 2703 if (ret == -EOPNOTSUPP) 2704 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2705 else if (ret) 2706 netdev_warn(priv->dev, "PTP init failed\n"); 2707 } 2708 2709 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 2710 2711 /* Convert the timer from msec to usec */ 2712 if (!priv->tx_lpi_timer) 2713 priv->tx_lpi_timer = eee_timer * 1000; 2714 2715 if (priv->use_riwt) { 2716 if (!priv->rx_riwt) 2717 priv->rx_riwt = DEF_DMA_RIWT; 2718 2719 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2720 } 2721 2722 if (priv->hw->pcs) 2723 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2724 2725 /* set TX and RX rings length */ 2726 stmmac_set_rings_length(priv); 2727 2728 /* Enable TSO */ 2729 if (priv->tso) { 2730 for (chan = 0; chan < tx_cnt; chan++) 2731 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2732 } 2733 2734 /* Enable Split Header */ 2735 if (priv->sph && priv->hw->rx_csum) { 2736 for (chan = 0; chan < rx_cnt; chan++) 2737 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2738 } 2739 2740 /* VLAN Tag Insertion */ 2741 if (priv->dma_cap.vlins) 2742 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2743 2744 /* TBS */ 2745 for (chan = 0; chan < tx_cnt; chan++) { 2746 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2747 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2748 2749 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2750 } 2751 2752 /* Configure real RX and TX queues */ 2753 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 2754 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 2755 2756 /* Start the ball rolling... */ 2757 stmmac_start_all_dma(priv); 2758 2759 return 0; 2760 } 2761 2762 static void stmmac_hw_teardown(struct net_device *dev) 2763 { 2764 struct stmmac_priv *priv = netdev_priv(dev); 2765 2766 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2767 } 2768 2769 /** 2770 * stmmac_open - open entry point of the driver 2771 * @dev : pointer to the device structure. 2772 * Description: 2773 * This function is the open entry point of the driver. 2774 * Return value: 2775 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2776 * file on failure. 2777 */ 2778 static int stmmac_open(struct net_device *dev) 2779 { 2780 struct stmmac_priv *priv = netdev_priv(dev); 2781 int bfsize = 0; 2782 u32 chan; 2783 int ret; 2784 2785 if (priv->hw->pcs != STMMAC_PCS_TBI && 2786 priv->hw->pcs != STMMAC_PCS_RTBI && 2787 priv->hw->xpcs == NULL) { 2788 ret = stmmac_init_phy(dev); 2789 if (ret) { 2790 netdev_err(priv->dev, 2791 "%s: Cannot attach to PHY (error: %d)\n", 2792 __func__, ret); 2793 return ret; 2794 } 2795 } 2796 2797 /* Extra statistics */ 2798 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2799 priv->xstats.threshold = tc; 2800 2801 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2802 if (bfsize < 0) 2803 bfsize = 0; 2804 2805 if (bfsize < BUF_SIZE_16KiB) 2806 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2807 2808 priv->dma_buf_sz = bfsize; 2809 buf_sz = bfsize; 2810 2811 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2812 2813 if (!priv->dma_tx_size) 2814 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 2815 if (!priv->dma_rx_size) 2816 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 2817 2818 /* Earlier check for TBS */ 2819 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2820 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2821 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2822 2823 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2824 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2825 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2826 } 2827 2828 ret = alloc_dma_desc_resources(priv); 2829 if (ret < 0) { 2830 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2831 __func__); 2832 goto dma_desc_error; 2833 } 2834 2835 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2836 if (ret < 0) { 2837 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2838 __func__); 2839 goto init_error; 2840 } 2841 2842 ret = stmmac_hw_setup(dev, true); 2843 if (ret < 0) { 2844 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2845 goto init_error; 2846 } 2847 2848 stmmac_init_coalesce(priv); 2849 2850 phylink_start(priv->phylink); 2851 /* We may have called phylink_speed_down before */ 2852 phylink_speed_up(priv->phylink); 2853 2854 /* Request the IRQ lines */ 2855 ret = request_irq(dev->irq, stmmac_interrupt, 2856 IRQF_SHARED, dev->name, dev); 2857 if (unlikely(ret < 0)) { 2858 netdev_err(priv->dev, 2859 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2860 __func__, dev->irq, ret); 2861 goto irq_error; 2862 } 2863 2864 /* Request the Wake IRQ in case of another line is used for WoL */ 2865 if (priv->wol_irq != dev->irq) { 2866 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2867 IRQF_SHARED, dev->name, dev); 2868 if (unlikely(ret < 0)) { 2869 netdev_err(priv->dev, 2870 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2871 __func__, priv->wol_irq, ret); 2872 goto wolirq_error; 2873 } 2874 } 2875 2876 /* Request the IRQ lines */ 2877 if (priv->lpi_irq > 0) { 2878 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2879 dev->name, dev); 2880 if (unlikely(ret < 0)) { 2881 netdev_err(priv->dev, 2882 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2883 __func__, priv->lpi_irq, ret); 2884 goto lpiirq_error; 2885 } 2886 } 2887 2888 stmmac_enable_all_queues(priv); 2889 netif_tx_start_all_queues(priv->dev); 2890 2891 return 0; 2892 2893 lpiirq_error: 2894 if (priv->wol_irq != dev->irq) 2895 free_irq(priv->wol_irq, dev); 2896 wolirq_error: 2897 free_irq(dev->irq, dev); 2898 irq_error: 2899 phylink_stop(priv->phylink); 2900 2901 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2902 del_timer_sync(&priv->tx_queue[chan].txtimer); 2903 2904 stmmac_hw_teardown(dev); 2905 init_error: 2906 free_dma_desc_resources(priv); 2907 dma_desc_error: 2908 phylink_disconnect_phy(priv->phylink); 2909 return ret; 2910 } 2911 2912 /** 2913 * stmmac_release - close entry point of the driver 2914 * @dev : device pointer. 2915 * Description: 2916 * This is the stop entry point of the driver. 2917 */ 2918 static int stmmac_release(struct net_device *dev) 2919 { 2920 struct stmmac_priv *priv = netdev_priv(dev); 2921 u32 chan; 2922 2923 if (priv->eee_enabled) 2924 del_timer_sync(&priv->eee_ctrl_timer); 2925 2926 if (device_may_wakeup(priv->device)) 2927 phylink_speed_down(priv->phylink, false); 2928 /* Stop and disconnect the PHY */ 2929 phylink_stop(priv->phylink); 2930 phylink_disconnect_phy(priv->phylink); 2931 2932 stmmac_disable_all_queues(priv); 2933 2934 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2935 del_timer_sync(&priv->tx_queue[chan].txtimer); 2936 2937 /* Free the IRQ lines */ 2938 free_irq(dev->irq, dev); 2939 if (priv->wol_irq != dev->irq) 2940 free_irq(priv->wol_irq, dev); 2941 if (priv->lpi_irq > 0) 2942 free_irq(priv->lpi_irq, dev); 2943 2944 /* Stop TX/RX DMA and clear the descriptors */ 2945 stmmac_stop_all_dma(priv); 2946 2947 /* Release and free the Rx/Tx resources */ 2948 free_dma_desc_resources(priv); 2949 2950 /* Disable the MAC Rx/Tx */ 2951 stmmac_mac_set(priv, priv->ioaddr, false); 2952 2953 netif_carrier_off(dev); 2954 2955 stmmac_release_ptp(priv); 2956 2957 return 0; 2958 } 2959 2960 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2961 struct stmmac_tx_queue *tx_q) 2962 { 2963 u16 tag = 0x0, inner_tag = 0x0; 2964 u32 inner_type = 0x0; 2965 struct dma_desc *p; 2966 2967 if (!priv->dma_cap.vlins) 2968 return false; 2969 if (!skb_vlan_tag_present(skb)) 2970 return false; 2971 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2972 inner_tag = skb_vlan_tag_get(skb); 2973 inner_type = STMMAC_VLAN_INSERT; 2974 } 2975 2976 tag = skb_vlan_tag_get(skb); 2977 2978 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2979 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2980 else 2981 p = &tx_q->dma_tx[tx_q->cur_tx]; 2982 2983 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2984 return false; 2985 2986 stmmac_set_tx_owner(priv, p); 2987 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2988 return true; 2989 } 2990 2991 /** 2992 * stmmac_tso_allocator - close entry point of the driver 2993 * @priv: driver private structure 2994 * @des: buffer start address 2995 * @total_len: total length to fill in descriptors 2996 * @last_segment: condition for the last descriptor 2997 * @queue: TX queue index 2998 * Description: 2999 * This function fills descriptor and request new descriptors according to 3000 * buffer length to fill 3001 */ 3002 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3003 int total_len, bool last_segment, u32 queue) 3004 { 3005 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3006 struct dma_desc *desc; 3007 u32 buff_size; 3008 int tmp_len; 3009 3010 tmp_len = total_len; 3011 3012 while (tmp_len > 0) { 3013 dma_addr_t curr_addr; 3014 3015 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3016 priv->dma_tx_size); 3017 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3018 3019 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3020 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3021 else 3022 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3023 3024 curr_addr = des + (total_len - tmp_len); 3025 if (priv->dma_cap.addr64 <= 32) 3026 desc->des0 = cpu_to_le32(curr_addr); 3027 else 3028 stmmac_set_desc_addr(priv, desc, curr_addr); 3029 3030 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3031 TSO_MAX_BUFF_SIZE : tmp_len; 3032 3033 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3034 0, 1, 3035 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3036 0, 0); 3037 3038 tmp_len -= TSO_MAX_BUFF_SIZE; 3039 } 3040 } 3041 3042 /** 3043 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3044 * @skb : the socket buffer 3045 * @dev : device pointer 3046 * Description: this is the transmit function that is called on TSO frames 3047 * (support available on GMAC4 and newer chips). 3048 * Diagram below show the ring programming in case of TSO frames: 3049 * 3050 * First Descriptor 3051 * -------- 3052 * | DES0 |---> buffer1 = L2/L3/L4 header 3053 * | DES1 |---> TCP Payload (can continue on next descr...) 3054 * | DES2 |---> buffer 1 and 2 len 3055 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3056 * -------- 3057 * | 3058 * ... 3059 * | 3060 * -------- 3061 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3062 * | DES1 | --| 3063 * | DES2 | --> buffer 1 and 2 len 3064 * | DES3 | 3065 * -------- 3066 * 3067 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3068 */ 3069 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3070 { 3071 struct dma_desc *desc, *first, *mss_desc = NULL; 3072 struct stmmac_priv *priv = netdev_priv(dev); 3073 int desc_size, tmp_pay_len = 0, first_tx; 3074 int nfrags = skb_shinfo(skb)->nr_frags; 3075 u32 queue = skb_get_queue_mapping(skb); 3076 unsigned int first_entry, tx_packets; 3077 struct stmmac_tx_queue *tx_q; 3078 bool has_vlan, set_ic; 3079 u8 proto_hdr_len, hdr; 3080 u32 pay_len, mss; 3081 dma_addr_t des; 3082 int i; 3083 3084 tx_q = &priv->tx_queue[queue]; 3085 first_tx = tx_q->cur_tx; 3086 3087 /* Compute header lengths */ 3088 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3089 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3090 hdr = sizeof(struct udphdr); 3091 } else { 3092 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3093 hdr = tcp_hdrlen(skb); 3094 } 3095 3096 /* Desc availability based on threshold should be enough safe */ 3097 if (unlikely(stmmac_tx_avail(priv, queue) < 3098 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3099 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3100 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3101 queue)); 3102 /* This is a hard error, log it. */ 3103 netdev_err(priv->dev, 3104 "%s: Tx Ring full when queue awake\n", 3105 __func__); 3106 } 3107 return NETDEV_TX_BUSY; 3108 } 3109 3110 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3111 3112 mss = skb_shinfo(skb)->gso_size; 3113 3114 /* set new MSS value if needed */ 3115 if (mss != tx_q->mss) { 3116 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3117 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3118 else 3119 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3120 3121 stmmac_set_mss(priv, mss_desc, mss); 3122 tx_q->mss = mss; 3123 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3124 priv->dma_tx_size); 3125 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3126 } 3127 3128 if (netif_msg_tx_queued(priv)) { 3129 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3130 __func__, hdr, proto_hdr_len, pay_len, mss); 3131 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3132 skb->data_len); 3133 } 3134 3135 /* Check if VLAN can be inserted by HW */ 3136 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3137 3138 first_entry = tx_q->cur_tx; 3139 WARN_ON(tx_q->tx_skbuff[first_entry]); 3140 3141 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3142 desc = &tx_q->dma_entx[first_entry].basic; 3143 else 3144 desc = &tx_q->dma_tx[first_entry]; 3145 first = desc; 3146 3147 if (has_vlan) 3148 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3149 3150 /* first descriptor: fill Headers on Buf1 */ 3151 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3152 DMA_TO_DEVICE); 3153 if (dma_mapping_error(priv->device, des)) 3154 goto dma_map_err; 3155 3156 tx_q->tx_skbuff_dma[first_entry].buf = des; 3157 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3158 3159 if (priv->dma_cap.addr64 <= 32) { 3160 first->des0 = cpu_to_le32(des); 3161 3162 /* Fill start of payload in buff2 of first descriptor */ 3163 if (pay_len) 3164 first->des1 = cpu_to_le32(des + proto_hdr_len); 3165 3166 /* If needed take extra descriptors to fill the remaining payload */ 3167 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3168 } else { 3169 stmmac_set_desc_addr(priv, first, des); 3170 tmp_pay_len = pay_len; 3171 des += proto_hdr_len; 3172 pay_len = 0; 3173 } 3174 3175 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3176 3177 /* Prepare fragments */ 3178 for (i = 0; i < nfrags; i++) { 3179 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3180 3181 des = skb_frag_dma_map(priv->device, frag, 0, 3182 skb_frag_size(frag), 3183 DMA_TO_DEVICE); 3184 if (dma_mapping_error(priv->device, des)) 3185 goto dma_map_err; 3186 3187 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3188 (i == nfrags - 1), queue); 3189 3190 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3191 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3192 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3193 } 3194 3195 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3196 3197 /* Only the last descriptor gets to point to the skb. */ 3198 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3199 3200 /* Manage tx mitigation */ 3201 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3202 tx_q->tx_count_frames += tx_packets; 3203 3204 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3205 set_ic = true; 3206 else if (!priv->tx_coal_frames) 3207 set_ic = false; 3208 else if (tx_packets > priv->tx_coal_frames) 3209 set_ic = true; 3210 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3211 set_ic = true; 3212 else 3213 set_ic = false; 3214 3215 if (set_ic) { 3216 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3217 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3218 else 3219 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3220 3221 tx_q->tx_count_frames = 0; 3222 stmmac_set_tx_ic(priv, desc); 3223 priv->xstats.tx_set_ic_bit++; 3224 } 3225 3226 /* We've used all descriptors we need for this skb, however, 3227 * advance cur_tx so that it references a fresh descriptor. 3228 * ndo_start_xmit will fill this descriptor the next time it's 3229 * called and stmmac_tx_clean may clean up to this descriptor. 3230 */ 3231 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3232 3233 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3234 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3235 __func__); 3236 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3237 } 3238 3239 dev->stats.tx_bytes += skb->len; 3240 priv->xstats.tx_tso_frames++; 3241 priv->xstats.tx_tso_nfrags += nfrags; 3242 3243 if (priv->sarc_type) 3244 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3245 3246 skb_tx_timestamp(skb); 3247 3248 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3249 priv->hwts_tx_en)) { 3250 /* declare that device is doing timestamping */ 3251 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3252 stmmac_enable_tx_timestamp(priv, first); 3253 } 3254 3255 /* Complete the first descriptor before granting the DMA */ 3256 stmmac_prepare_tso_tx_desc(priv, first, 1, 3257 proto_hdr_len, 3258 pay_len, 3259 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3260 hdr / 4, (skb->len - proto_hdr_len)); 3261 3262 /* If context desc is used to change MSS */ 3263 if (mss_desc) { 3264 /* Make sure that first descriptor has been completely 3265 * written, including its own bit. This is because MSS is 3266 * actually before first descriptor, so we need to make 3267 * sure that MSS's own bit is the last thing written. 3268 */ 3269 dma_wmb(); 3270 stmmac_set_tx_owner(priv, mss_desc); 3271 } 3272 3273 /* The own bit must be the latest setting done when prepare the 3274 * descriptor and then barrier is needed to make sure that 3275 * all is coherent before granting the DMA engine. 3276 */ 3277 wmb(); 3278 3279 if (netif_msg_pktdata(priv)) { 3280 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3281 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3282 tx_q->cur_tx, first, nfrags); 3283 pr_info(">>> frame to be transmitted: "); 3284 print_pkt(skb->data, skb_headlen(skb)); 3285 } 3286 3287 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3288 3289 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3290 desc_size = sizeof(struct dma_edesc); 3291 else 3292 desc_size = sizeof(struct dma_desc); 3293 3294 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3295 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3296 stmmac_tx_timer_arm(priv, queue); 3297 3298 return NETDEV_TX_OK; 3299 3300 dma_map_err: 3301 dev_err(priv->device, "Tx dma map failed\n"); 3302 dev_kfree_skb(skb); 3303 priv->dev->stats.tx_dropped++; 3304 return NETDEV_TX_OK; 3305 } 3306 3307 /** 3308 * stmmac_xmit - Tx entry point of the driver 3309 * @skb : the socket buffer 3310 * @dev : device pointer 3311 * Description : this is the tx entry point of the driver. 3312 * It programs the chain or the ring and supports oversized frames 3313 * and SG feature. 3314 */ 3315 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3316 { 3317 unsigned int first_entry, tx_packets, enh_desc; 3318 struct stmmac_priv *priv = netdev_priv(dev); 3319 unsigned int nopaged_len = skb_headlen(skb); 3320 int i, csum_insertion = 0, is_jumbo = 0; 3321 u32 queue = skb_get_queue_mapping(skb); 3322 int nfrags = skb_shinfo(skb)->nr_frags; 3323 int gso = skb_shinfo(skb)->gso_type; 3324 struct dma_edesc *tbs_desc = NULL; 3325 int entry, desc_size, first_tx; 3326 struct dma_desc *desc, *first; 3327 struct stmmac_tx_queue *tx_q; 3328 bool has_vlan, set_ic; 3329 dma_addr_t des; 3330 3331 tx_q = &priv->tx_queue[queue]; 3332 first_tx = tx_q->cur_tx; 3333 3334 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 3335 stmmac_disable_eee_mode(priv); 3336 3337 /* Manage oversized TCP frames for GMAC4 device */ 3338 if (skb_is_gso(skb) && priv->tso) { 3339 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3340 return stmmac_tso_xmit(skb, dev); 3341 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3342 return stmmac_tso_xmit(skb, dev); 3343 } 3344 3345 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3346 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3347 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3348 queue)); 3349 /* This is a hard error, log it. */ 3350 netdev_err(priv->dev, 3351 "%s: Tx Ring full when queue awake\n", 3352 __func__); 3353 } 3354 return NETDEV_TX_BUSY; 3355 } 3356 3357 /* Check if VLAN can be inserted by HW */ 3358 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3359 3360 entry = tx_q->cur_tx; 3361 first_entry = entry; 3362 WARN_ON(tx_q->tx_skbuff[first_entry]); 3363 3364 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3365 3366 if (likely(priv->extend_desc)) 3367 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3368 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3369 desc = &tx_q->dma_entx[entry].basic; 3370 else 3371 desc = tx_q->dma_tx + entry; 3372 3373 first = desc; 3374 3375 if (has_vlan) 3376 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3377 3378 enh_desc = priv->plat->enh_desc; 3379 /* To program the descriptors according to the size of the frame */ 3380 if (enh_desc) 3381 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3382 3383 if (unlikely(is_jumbo)) { 3384 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3385 if (unlikely(entry < 0) && (entry != -EINVAL)) 3386 goto dma_map_err; 3387 } 3388 3389 for (i = 0; i < nfrags; i++) { 3390 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3391 int len = skb_frag_size(frag); 3392 bool last_segment = (i == (nfrags - 1)); 3393 3394 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3395 WARN_ON(tx_q->tx_skbuff[entry]); 3396 3397 if (likely(priv->extend_desc)) 3398 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3399 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3400 desc = &tx_q->dma_entx[entry].basic; 3401 else 3402 desc = tx_q->dma_tx + entry; 3403 3404 des = skb_frag_dma_map(priv->device, frag, 0, len, 3405 DMA_TO_DEVICE); 3406 if (dma_mapping_error(priv->device, des)) 3407 goto dma_map_err; /* should reuse desc w/o issues */ 3408 3409 tx_q->tx_skbuff_dma[entry].buf = des; 3410 3411 stmmac_set_desc_addr(priv, desc, des); 3412 3413 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3414 tx_q->tx_skbuff_dma[entry].len = len; 3415 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3416 3417 /* Prepare the descriptor and set the own bit too */ 3418 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3419 priv->mode, 1, last_segment, skb->len); 3420 } 3421 3422 /* Only the last descriptor gets to point to the skb. */ 3423 tx_q->tx_skbuff[entry] = skb; 3424 3425 /* According to the coalesce parameter the IC bit for the latest 3426 * segment is reset and the timer re-started to clean the tx status. 3427 * This approach takes care about the fragments: desc is the first 3428 * element in case of no SG. 3429 */ 3430 tx_packets = (entry + 1) - first_tx; 3431 tx_q->tx_count_frames += tx_packets; 3432 3433 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3434 set_ic = true; 3435 else if (!priv->tx_coal_frames) 3436 set_ic = false; 3437 else if (tx_packets > priv->tx_coal_frames) 3438 set_ic = true; 3439 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3440 set_ic = true; 3441 else 3442 set_ic = false; 3443 3444 if (set_ic) { 3445 if (likely(priv->extend_desc)) 3446 desc = &tx_q->dma_etx[entry].basic; 3447 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3448 desc = &tx_q->dma_entx[entry].basic; 3449 else 3450 desc = &tx_q->dma_tx[entry]; 3451 3452 tx_q->tx_count_frames = 0; 3453 stmmac_set_tx_ic(priv, desc); 3454 priv->xstats.tx_set_ic_bit++; 3455 } 3456 3457 /* We've used all descriptors we need for this skb, however, 3458 * advance cur_tx so that it references a fresh descriptor. 3459 * ndo_start_xmit will fill this descriptor the next time it's 3460 * called and stmmac_tx_clean may clean up to this descriptor. 3461 */ 3462 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3463 tx_q->cur_tx = entry; 3464 3465 if (netif_msg_pktdata(priv)) { 3466 netdev_dbg(priv->dev, 3467 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3468 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3469 entry, first, nfrags); 3470 3471 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3472 print_pkt(skb->data, skb->len); 3473 } 3474 3475 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3476 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3477 __func__); 3478 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3479 } 3480 3481 dev->stats.tx_bytes += skb->len; 3482 3483 if (priv->sarc_type) 3484 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3485 3486 skb_tx_timestamp(skb); 3487 3488 /* Ready to fill the first descriptor and set the OWN bit w/o any 3489 * problems because all the descriptors are actually ready to be 3490 * passed to the DMA engine. 3491 */ 3492 if (likely(!is_jumbo)) { 3493 bool last_segment = (nfrags == 0); 3494 3495 des = dma_map_single(priv->device, skb->data, 3496 nopaged_len, DMA_TO_DEVICE); 3497 if (dma_mapping_error(priv->device, des)) 3498 goto dma_map_err; 3499 3500 tx_q->tx_skbuff_dma[first_entry].buf = des; 3501 3502 stmmac_set_desc_addr(priv, first, des); 3503 3504 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3505 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3506 3507 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3508 priv->hwts_tx_en)) { 3509 /* declare that device is doing timestamping */ 3510 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3511 stmmac_enable_tx_timestamp(priv, first); 3512 } 3513 3514 /* Prepare the first descriptor setting the OWN bit too */ 3515 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3516 csum_insertion, priv->mode, 0, last_segment, 3517 skb->len); 3518 } 3519 3520 if (tx_q->tbs & STMMAC_TBS_EN) { 3521 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3522 3523 tbs_desc = &tx_q->dma_entx[first_entry]; 3524 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3525 } 3526 3527 stmmac_set_tx_owner(priv, first); 3528 3529 /* The own bit must be the latest setting done when prepare the 3530 * descriptor and then barrier is needed to make sure that 3531 * all is coherent before granting the DMA engine. 3532 */ 3533 wmb(); 3534 3535 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3536 3537 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3538 3539 if (likely(priv->extend_desc)) 3540 desc_size = sizeof(struct dma_extended_desc); 3541 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3542 desc_size = sizeof(struct dma_edesc); 3543 else 3544 desc_size = sizeof(struct dma_desc); 3545 3546 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3547 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3548 stmmac_tx_timer_arm(priv, queue); 3549 3550 return NETDEV_TX_OK; 3551 3552 dma_map_err: 3553 netdev_err(priv->dev, "Tx DMA map failed\n"); 3554 dev_kfree_skb(skb); 3555 priv->dev->stats.tx_dropped++; 3556 return NETDEV_TX_OK; 3557 } 3558 3559 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3560 { 3561 struct vlan_ethhdr *veth; 3562 __be16 vlan_proto; 3563 u16 vlanid; 3564 3565 veth = (struct vlan_ethhdr *)skb->data; 3566 vlan_proto = veth->h_vlan_proto; 3567 3568 if ((vlan_proto == htons(ETH_P_8021Q) && 3569 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3570 (vlan_proto == htons(ETH_P_8021AD) && 3571 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3572 /* pop the vlan tag */ 3573 vlanid = ntohs(veth->h_vlan_TCI); 3574 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3575 skb_pull(skb, VLAN_HLEN); 3576 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3577 } 3578 } 3579 3580 /** 3581 * stmmac_rx_refill - refill used skb preallocated buffers 3582 * @priv: driver private structure 3583 * @queue: RX queue index 3584 * Description : this is to reallocate the skb for the reception process 3585 * that is based on zero-copy. 3586 */ 3587 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3588 { 3589 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3590 int len, dirty = stmmac_rx_dirty(priv, queue); 3591 unsigned int entry = rx_q->dirty_rx; 3592 3593 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3594 3595 while (dirty-- > 0) { 3596 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3597 struct dma_desc *p; 3598 bool use_rx_wd; 3599 3600 if (priv->extend_desc) 3601 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3602 else 3603 p = rx_q->dma_rx + entry; 3604 3605 if (!buf->page) { 3606 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3607 if (!buf->page) 3608 break; 3609 } 3610 3611 if (priv->sph && !buf->sec_page) { 3612 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3613 if (!buf->sec_page) 3614 break; 3615 3616 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3617 3618 dma_sync_single_for_device(priv->device, buf->sec_addr, 3619 len, DMA_FROM_DEVICE); 3620 } 3621 3622 buf->addr = page_pool_get_dma_addr(buf->page); 3623 3624 /* Sync whole allocation to device. This will invalidate old 3625 * data. 3626 */ 3627 dma_sync_single_for_device(priv->device, buf->addr, len, 3628 DMA_FROM_DEVICE); 3629 3630 stmmac_set_desc_addr(priv, p, buf->addr); 3631 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3632 stmmac_refill_desc3(priv, rx_q, p); 3633 3634 rx_q->rx_count_frames++; 3635 rx_q->rx_count_frames += priv->rx_coal_frames; 3636 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3637 rx_q->rx_count_frames = 0; 3638 3639 use_rx_wd = !priv->rx_coal_frames; 3640 use_rx_wd |= rx_q->rx_count_frames > 0; 3641 if (!priv->use_riwt) 3642 use_rx_wd = false; 3643 3644 dma_wmb(); 3645 stmmac_set_rx_owner(priv, p, use_rx_wd); 3646 3647 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 3648 } 3649 rx_q->dirty_rx = entry; 3650 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3651 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3652 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3653 } 3654 3655 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3656 struct dma_desc *p, 3657 int status, unsigned int len) 3658 { 3659 unsigned int plen = 0, hlen = 0; 3660 int coe = priv->hw->rx_csum; 3661 3662 /* Not first descriptor, buffer is always zero */ 3663 if (priv->sph && len) 3664 return 0; 3665 3666 /* First descriptor, get split header length */ 3667 stmmac_get_rx_header_len(priv, p, &hlen); 3668 if (priv->sph && hlen) { 3669 priv->xstats.rx_split_hdr_pkt_n++; 3670 return hlen; 3671 } 3672 3673 /* First descriptor, not last descriptor and not split header */ 3674 if (status & rx_not_ls) 3675 return priv->dma_buf_sz; 3676 3677 plen = stmmac_get_rx_frame_len(priv, p, coe); 3678 3679 /* First descriptor and last descriptor and not split header */ 3680 return min_t(unsigned int, priv->dma_buf_sz, plen); 3681 } 3682 3683 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3684 struct dma_desc *p, 3685 int status, unsigned int len) 3686 { 3687 int coe = priv->hw->rx_csum; 3688 unsigned int plen = 0; 3689 3690 /* Not split header, buffer is not available */ 3691 if (!priv->sph) 3692 return 0; 3693 3694 /* Not last descriptor */ 3695 if (status & rx_not_ls) 3696 return priv->dma_buf_sz; 3697 3698 plen = stmmac_get_rx_frame_len(priv, p, coe); 3699 3700 /* Last descriptor */ 3701 return plen - len; 3702 } 3703 3704 /** 3705 * stmmac_rx - manage the receive process 3706 * @priv: driver private structure 3707 * @limit: napi bugget 3708 * @queue: RX queue index. 3709 * Description : this the function called by the napi poll method. 3710 * It gets all the frames inside the ring. 3711 */ 3712 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3713 { 3714 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3715 struct stmmac_channel *ch = &priv->channel[queue]; 3716 unsigned int count = 0, error = 0, len = 0; 3717 int status = 0, coe = priv->hw->rx_csum; 3718 unsigned int next_entry = rx_q->cur_rx; 3719 struct sk_buff *skb = NULL; 3720 3721 if (netif_msg_rx_status(priv)) { 3722 void *rx_head; 3723 3724 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3725 if (priv->extend_desc) 3726 rx_head = (void *)rx_q->dma_erx; 3727 else 3728 rx_head = (void *)rx_q->dma_rx; 3729 3730 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true); 3731 } 3732 while (count < limit) { 3733 unsigned int buf1_len = 0, buf2_len = 0; 3734 enum pkt_hash_types hash_type; 3735 struct stmmac_rx_buffer *buf; 3736 struct dma_desc *np, *p; 3737 int entry; 3738 u32 hash; 3739 3740 if (!count && rx_q->state_saved) { 3741 skb = rx_q->state.skb; 3742 error = rx_q->state.error; 3743 len = rx_q->state.len; 3744 } else { 3745 rx_q->state_saved = false; 3746 skb = NULL; 3747 error = 0; 3748 len = 0; 3749 } 3750 3751 if (count >= limit) 3752 break; 3753 3754 read_again: 3755 buf1_len = 0; 3756 buf2_len = 0; 3757 entry = next_entry; 3758 buf = &rx_q->buf_pool[entry]; 3759 3760 if (priv->extend_desc) 3761 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3762 else 3763 p = rx_q->dma_rx + entry; 3764 3765 /* read the status of the incoming frame */ 3766 status = stmmac_rx_status(priv, &priv->dev->stats, 3767 &priv->xstats, p); 3768 /* check if managed by the DMA otherwise go ahead */ 3769 if (unlikely(status & dma_own)) 3770 break; 3771 3772 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 3773 priv->dma_rx_size); 3774 next_entry = rx_q->cur_rx; 3775 3776 if (priv->extend_desc) 3777 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3778 else 3779 np = rx_q->dma_rx + next_entry; 3780 3781 prefetch(np); 3782 3783 if (priv->extend_desc) 3784 stmmac_rx_extended_status(priv, &priv->dev->stats, 3785 &priv->xstats, rx_q->dma_erx + entry); 3786 if (unlikely(status == discard_frame)) { 3787 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3788 buf->page = NULL; 3789 error = 1; 3790 if (!priv->hwts_rx_en) 3791 priv->dev->stats.rx_errors++; 3792 } 3793 3794 if (unlikely(error && (status & rx_not_ls))) 3795 goto read_again; 3796 if (unlikely(error)) { 3797 dev_kfree_skb(skb); 3798 skb = NULL; 3799 count++; 3800 continue; 3801 } 3802 3803 /* Buffer is good. Go on. */ 3804 3805 prefetch(page_address(buf->page)); 3806 if (buf->sec_page) 3807 prefetch(page_address(buf->sec_page)); 3808 3809 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3810 len += buf1_len; 3811 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3812 len += buf2_len; 3813 3814 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3815 * Type frames (LLC/LLC-SNAP) 3816 * 3817 * llc_snap is never checked in GMAC >= 4, so this ACS 3818 * feature is always disabled and packets need to be 3819 * stripped manually. 3820 */ 3821 if (likely(!(status & rx_not_ls)) && 3822 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3823 unlikely(status != llc_snap))) { 3824 if (buf2_len) 3825 buf2_len -= ETH_FCS_LEN; 3826 else 3827 buf1_len -= ETH_FCS_LEN; 3828 3829 len -= ETH_FCS_LEN; 3830 } 3831 3832 if (!skb) { 3833 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3834 if (!skb) { 3835 priv->dev->stats.rx_dropped++; 3836 count++; 3837 goto drain_data; 3838 } 3839 3840 dma_sync_single_for_cpu(priv->device, buf->addr, 3841 buf1_len, DMA_FROM_DEVICE); 3842 skb_copy_to_linear_data(skb, page_address(buf->page), 3843 buf1_len); 3844 skb_put(skb, buf1_len); 3845 3846 /* Data payload copied into SKB, page ready for recycle */ 3847 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3848 buf->page = NULL; 3849 } else if (buf1_len) { 3850 dma_sync_single_for_cpu(priv->device, buf->addr, 3851 buf1_len, DMA_FROM_DEVICE); 3852 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3853 buf->page, 0, buf1_len, 3854 priv->dma_buf_sz); 3855 3856 /* Data payload appended into SKB */ 3857 page_pool_release_page(rx_q->page_pool, buf->page); 3858 buf->page = NULL; 3859 } 3860 3861 if (buf2_len) { 3862 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3863 buf2_len, DMA_FROM_DEVICE); 3864 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3865 buf->sec_page, 0, buf2_len, 3866 priv->dma_buf_sz); 3867 3868 /* Data payload appended into SKB */ 3869 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3870 buf->sec_page = NULL; 3871 } 3872 3873 drain_data: 3874 if (likely(status & rx_not_ls)) 3875 goto read_again; 3876 if (!skb) 3877 continue; 3878 3879 /* Got entire packet into SKB. Finish it. */ 3880 3881 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3882 stmmac_rx_vlan(priv->dev, skb); 3883 skb->protocol = eth_type_trans(skb, priv->dev); 3884 3885 if (unlikely(!coe)) 3886 skb_checksum_none_assert(skb); 3887 else 3888 skb->ip_summed = CHECKSUM_UNNECESSARY; 3889 3890 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3891 skb_set_hash(skb, hash, hash_type); 3892 3893 skb_record_rx_queue(skb, queue); 3894 napi_gro_receive(&ch->rx_napi, skb); 3895 skb = NULL; 3896 3897 priv->dev->stats.rx_packets++; 3898 priv->dev->stats.rx_bytes += len; 3899 count++; 3900 } 3901 3902 if (status & rx_not_ls || skb) { 3903 rx_q->state_saved = true; 3904 rx_q->state.skb = skb; 3905 rx_q->state.error = error; 3906 rx_q->state.len = len; 3907 } 3908 3909 stmmac_rx_refill(priv, queue); 3910 3911 priv->xstats.rx_pkt_n += count; 3912 3913 return count; 3914 } 3915 3916 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3917 { 3918 struct stmmac_channel *ch = 3919 container_of(napi, struct stmmac_channel, rx_napi); 3920 struct stmmac_priv *priv = ch->priv_data; 3921 u32 chan = ch->index; 3922 int work_done; 3923 3924 priv->xstats.napi_poll++; 3925 3926 work_done = stmmac_rx(priv, budget, chan); 3927 if (work_done < budget && napi_complete_done(napi, work_done)) { 3928 unsigned long flags; 3929 3930 spin_lock_irqsave(&ch->lock, flags); 3931 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3932 spin_unlock_irqrestore(&ch->lock, flags); 3933 } 3934 3935 return work_done; 3936 } 3937 3938 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3939 { 3940 struct stmmac_channel *ch = 3941 container_of(napi, struct stmmac_channel, tx_napi); 3942 struct stmmac_priv *priv = ch->priv_data; 3943 u32 chan = ch->index; 3944 int work_done; 3945 3946 priv->xstats.napi_poll++; 3947 3948 work_done = stmmac_tx_clean(priv, priv->dma_tx_size, chan); 3949 work_done = min(work_done, budget); 3950 3951 if (work_done < budget && napi_complete_done(napi, work_done)) { 3952 unsigned long flags; 3953 3954 spin_lock_irqsave(&ch->lock, flags); 3955 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3956 spin_unlock_irqrestore(&ch->lock, flags); 3957 } 3958 3959 return work_done; 3960 } 3961 3962 /** 3963 * stmmac_tx_timeout 3964 * @dev : Pointer to net device structure 3965 * @txqueue: the index of the hanging transmit queue 3966 * Description: this function is called when a packet transmission fails to 3967 * complete within a reasonable time. The driver will mark the error in the 3968 * netdev structure and arrange for the device to be reset to a sane state 3969 * in order to transmit a new packet. 3970 */ 3971 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3972 { 3973 struct stmmac_priv *priv = netdev_priv(dev); 3974 3975 stmmac_global_err(priv); 3976 } 3977 3978 /** 3979 * stmmac_set_rx_mode - entry point for multicast addressing 3980 * @dev : pointer to the device structure 3981 * Description: 3982 * This function is a driver entry point which gets called by the kernel 3983 * whenever multicast addresses must be enabled/disabled. 3984 * Return value: 3985 * void. 3986 */ 3987 static void stmmac_set_rx_mode(struct net_device *dev) 3988 { 3989 struct stmmac_priv *priv = netdev_priv(dev); 3990 3991 stmmac_set_filter(priv, priv->hw, dev); 3992 } 3993 3994 /** 3995 * stmmac_change_mtu - entry point to change MTU size for the device. 3996 * @dev : device pointer. 3997 * @new_mtu : the new MTU size for the device. 3998 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3999 * to drive packet transmission. Ethernet has an MTU of 1500 octets 4000 * (ETH_DATA_LEN). This value can be changed with ifconfig. 4001 * Return value: 4002 * 0 on success and an appropriate (-)ve integer as defined in errno.h 4003 * file on failure. 4004 */ 4005 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 4006 { 4007 struct stmmac_priv *priv = netdev_priv(dev); 4008 int txfifosz = priv->plat->tx_fifo_size; 4009 4010 if (txfifosz == 0) 4011 txfifosz = priv->dma_cap.tx_fifo_size; 4012 4013 txfifosz /= priv->plat->tx_queues_to_use; 4014 4015 if (netif_running(dev)) { 4016 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 4017 return -EBUSY; 4018 } 4019 4020 new_mtu = STMMAC_ALIGN(new_mtu); 4021 4022 /* If condition true, FIFO is too small or MTU too large */ 4023 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 4024 return -EINVAL; 4025 4026 dev->mtu = new_mtu; 4027 4028 netdev_update_features(dev); 4029 4030 return 0; 4031 } 4032 4033 static netdev_features_t stmmac_fix_features(struct net_device *dev, 4034 netdev_features_t features) 4035 { 4036 struct stmmac_priv *priv = netdev_priv(dev); 4037 4038 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4039 features &= ~NETIF_F_RXCSUM; 4040 4041 if (!priv->plat->tx_coe) 4042 features &= ~NETIF_F_CSUM_MASK; 4043 4044 /* Some GMAC devices have a bugged Jumbo frame support that 4045 * needs to have the Tx COE disabled for oversized frames 4046 * (due to limited buffer sizes). In this case we disable 4047 * the TX csum insertion in the TDES and not use SF. 4048 */ 4049 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4050 features &= ~NETIF_F_CSUM_MASK; 4051 4052 /* Disable tso if asked by ethtool */ 4053 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4054 if (features & NETIF_F_TSO) 4055 priv->tso = true; 4056 else 4057 priv->tso = false; 4058 } 4059 4060 return features; 4061 } 4062 4063 static int stmmac_set_features(struct net_device *netdev, 4064 netdev_features_t features) 4065 { 4066 struct stmmac_priv *priv = netdev_priv(netdev); 4067 bool sph_en; 4068 u32 chan; 4069 4070 /* Keep the COE Type in case of csum is supporting */ 4071 if (features & NETIF_F_RXCSUM) 4072 priv->hw->rx_csum = priv->plat->rx_coe; 4073 else 4074 priv->hw->rx_csum = 0; 4075 /* No check needed because rx_coe has been set before and it will be 4076 * fixed in case of issue. 4077 */ 4078 stmmac_rx_ipc(priv, priv->hw); 4079 4080 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4081 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4082 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4083 4084 return 0; 4085 } 4086 4087 /** 4088 * stmmac_interrupt - main ISR 4089 * @irq: interrupt number. 4090 * @dev_id: to pass the net device pointer (must be valid). 4091 * Description: this is the main driver interrupt service routine. 4092 * It can call: 4093 * o DMA service routine (to manage incoming frame reception and transmission 4094 * status) 4095 * o Core interrupts to manage: remote wake-up, management counter, LPI 4096 * interrupts. 4097 */ 4098 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4099 { 4100 struct net_device *dev = (struct net_device *)dev_id; 4101 struct stmmac_priv *priv = netdev_priv(dev); 4102 u32 rx_cnt = priv->plat->rx_queues_to_use; 4103 u32 tx_cnt = priv->plat->tx_queues_to_use; 4104 u32 queues_count; 4105 u32 queue; 4106 bool xmac; 4107 4108 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4109 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4110 4111 if (priv->irq_wake) 4112 pm_wakeup_event(priv->device, 0); 4113 4114 /* Check if adapter is up */ 4115 if (test_bit(STMMAC_DOWN, &priv->state)) 4116 return IRQ_HANDLED; 4117 /* Check if a fatal error happened */ 4118 if (stmmac_safety_feat_interrupt(priv)) 4119 return IRQ_HANDLED; 4120 4121 /* To handle GMAC own interrupts */ 4122 if ((priv->plat->has_gmac) || xmac) { 4123 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4124 int mtl_status; 4125 4126 if (unlikely(status)) { 4127 /* For LPI we need to save the tx status */ 4128 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4129 priv->tx_path_in_lpi_mode = true; 4130 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4131 priv->tx_path_in_lpi_mode = false; 4132 } 4133 4134 for (queue = 0; queue < queues_count; queue++) { 4135 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4136 4137 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4138 queue); 4139 if (mtl_status != -EINVAL) 4140 status |= mtl_status; 4141 4142 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4143 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4144 rx_q->rx_tail_addr, 4145 queue); 4146 } 4147 4148 /* PCS link status */ 4149 if (priv->hw->pcs) { 4150 if (priv->xstats.pcs_link) 4151 netif_carrier_on(dev); 4152 else 4153 netif_carrier_off(dev); 4154 } 4155 } 4156 4157 /* To handle DMA interrupts */ 4158 stmmac_dma_interrupt(priv); 4159 4160 return IRQ_HANDLED; 4161 } 4162 4163 #ifdef CONFIG_NET_POLL_CONTROLLER 4164 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4165 * to allow network I/O with interrupts disabled. 4166 */ 4167 static void stmmac_poll_controller(struct net_device *dev) 4168 { 4169 disable_irq(dev->irq); 4170 stmmac_interrupt(dev->irq, dev); 4171 enable_irq(dev->irq); 4172 } 4173 #endif 4174 4175 /** 4176 * stmmac_ioctl - Entry point for the Ioctl 4177 * @dev: Device pointer. 4178 * @rq: An IOCTL specefic structure, that can contain a pointer to 4179 * a proprietary structure used to pass information to the driver. 4180 * @cmd: IOCTL command 4181 * Description: 4182 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4183 */ 4184 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4185 { 4186 struct stmmac_priv *priv = netdev_priv (dev); 4187 int ret = -EOPNOTSUPP; 4188 4189 if (!netif_running(dev)) 4190 return -EINVAL; 4191 4192 switch (cmd) { 4193 case SIOCGMIIPHY: 4194 case SIOCGMIIREG: 4195 case SIOCSMIIREG: 4196 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4197 break; 4198 case SIOCSHWTSTAMP: 4199 ret = stmmac_hwtstamp_set(dev, rq); 4200 break; 4201 case SIOCGHWTSTAMP: 4202 ret = stmmac_hwtstamp_get(dev, rq); 4203 break; 4204 default: 4205 break; 4206 } 4207 4208 return ret; 4209 } 4210 4211 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4212 void *cb_priv) 4213 { 4214 struct stmmac_priv *priv = cb_priv; 4215 int ret = -EOPNOTSUPP; 4216 4217 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4218 return ret; 4219 4220 stmmac_disable_all_queues(priv); 4221 4222 switch (type) { 4223 case TC_SETUP_CLSU32: 4224 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4225 break; 4226 case TC_SETUP_CLSFLOWER: 4227 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4228 break; 4229 default: 4230 break; 4231 } 4232 4233 stmmac_enable_all_queues(priv); 4234 return ret; 4235 } 4236 4237 static LIST_HEAD(stmmac_block_cb_list); 4238 4239 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4240 void *type_data) 4241 { 4242 struct stmmac_priv *priv = netdev_priv(ndev); 4243 4244 switch (type) { 4245 case TC_SETUP_BLOCK: 4246 return flow_block_cb_setup_simple(type_data, 4247 &stmmac_block_cb_list, 4248 stmmac_setup_tc_block_cb, 4249 priv, priv, true); 4250 case TC_SETUP_QDISC_CBS: 4251 return stmmac_tc_setup_cbs(priv, priv, type_data); 4252 case TC_SETUP_QDISC_TAPRIO: 4253 return stmmac_tc_setup_taprio(priv, priv, type_data); 4254 case TC_SETUP_QDISC_ETF: 4255 return stmmac_tc_setup_etf(priv, priv, type_data); 4256 default: 4257 return -EOPNOTSUPP; 4258 } 4259 } 4260 4261 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4262 struct net_device *sb_dev) 4263 { 4264 int gso = skb_shinfo(skb)->gso_type; 4265 4266 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4267 /* 4268 * There is no way to determine the number of TSO/USO 4269 * capable Queues. Let's use always the Queue 0 4270 * because if TSO/USO is supported then at least this 4271 * one will be capable. 4272 */ 4273 return 0; 4274 } 4275 4276 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4277 } 4278 4279 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4280 { 4281 struct stmmac_priv *priv = netdev_priv(ndev); 4282 int ret = 0; 4283 4284 ret = eth_mac_addr(ndev, addr); 4285 if (ret) 4286 return ret; 4287 4288 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4289 4290 return ret; 4291 } 4292 4293 #ifdef CONFIG_DEBUG_FS 4294 static struct dentry *stmmac_fs_dir; 4295 4296 static void sysfs_display_ring(void *head, int size, int extend_desc, 4297 struct seq_file *seq) 4298 { 4299 int i; 4300 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4301 struct dma_desc *p = (struct dma_desc *)head; 4302 4303 for (i = 0; i < size; i++) { 4304 if (extend_desc) { 4305 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4306 i, (unsigned int)virt_to_phys(ep), 4307 le32_to_cpu(ep->basic.des0), 4308 le32_to_cpu(ep->basic.des1), 4309 le32_to_cpu(ep->basic.des2), 4310 le32_to_cpu(ep->basic.des3)); 4311 ep++; 4312 } else { 4313 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4314 i, (unsigned int)virt_to_phys(p), 4315 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4316 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4317 p++; 4318 } 4319 seq_printf(seq, "\n"); 4320 } 4321 } 4322 4323 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4324 { 4325 struct net_device *dev = seq->private; 4326 struct stmmac_priv *priv = netdev_priv(dev); 4327 u32 rx_count = priv->plat->rx_queues_to_use; 4328 u32 tx_count = priv->plat->tx_queues_to_use; 4329 u32 queue; 4330 4331 if ((dev->flags & IFF_UP) == 0) 4332 return 0; 4333 4334 for (queue = 0; queue < rx_count; queue++) { 4335 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4336 4337 seq_printf(seq, "RX Queue %d:\n", queue); 4338 4339 if (priv->extend_desc) { 4340 seq_printf(seq, "Extended descriptor ring:\n"); 4341 sysfs_display_ring((void *)rx_q->dma_erx, 4342 priv->dma_rx_size, 1, seq); 4343 } else { 4344 seq_printf(seq, "Descriptor ring:\n"); 4345 sysfs_display_ring((void *)rx_q->dma_rx, 4346 priv->dma_rx_size, 0, seq); 4347 } 4348 } 4349 4350 for (queue = 0; queue < tx_count; queue++) { 4351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4352 4353 seq_printf(seq, "TX Queue %d:\n", queue); 4354 4355 if (priv->extend_desc) { 4356 seq_printf(seq, "Extended descriptor ring:\n"); 4357 sysfs_display_ring((void *)tx_q->dma_etx, 4358 priv->dma_tx_size, 1, seq); 4359 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4360 seq_printf(seq, "Descriptor ring:\n"); 4361 sysfs_display_ring((void *)tx_q->dma_tx, 4362 priv->dma_tx_size, 0, seq); 4363 } 4364 } 4365 4366 return 0; 4367 } 4368 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4369 4370 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4371 { 4372 struct net_device *dev = seq->private; 4373 struct stmmac_priv *priv = netdev_priv(dev); 4374 4375 if (!priv->hw_cap_support) { 4376 seq_printf(seq, "DMA HW features not supported\n"); 4377 return 0; 4378 } 4379 4380 seq_printf(seq, "==============================\n"); 4381 seq_printf(seq, "\tDMA HW features\n"); 4382 seq_printf(seq, "==============================\n"); 4383 4384 seq_printf(seq, "\t10/100 Mbps: %s\n", 4385 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4386 seq_printf(seq, "\t1000 Mbps: %s\n", 4387 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4388 seq_printf(seq, "\tHalf duplex: %s\n", 4389 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4390 seq_printf(seq, "\tHash Filter: %s\n", 4391 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4392 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4393 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4394 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4395 (priv->dma_cap.pcs) ? "Y" : "N"); 4396 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4397 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4398 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4399 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4400 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4401 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4402 seq_printf(seq, "\tRMON module: %s\n", 4403 (priv->dma_cap.rmon) ? "Y" : "N"); 4404 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4405 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4406 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4407 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4408 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4409 (priv->dma_cap.eee) ? "Y" : "N"); 4410 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4411 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4412 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4413 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4414 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4415 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4416 } else { 4417 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4418 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4419 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4420 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4421 } 4422 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4423 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4424 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4425 priv->dma_cap.number_rx_channel); 4426 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4427 priv->dma_cap.number_tx_channel); 4428 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4429 priv->dma_cap.number_rx_queues); 4430 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4431 priv->dma_cap.number_tx_queues); 4432 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4433 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4434 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4435 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4436 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4437 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4438 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4439 priv->dma_cap.pps_out_num); 4440 seq_printf(seq, "\tSafety Features: %s\n", 4441 priv->dma_cap.asp ? "Y" : "N"); 4442 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4443 priv->dma_cap.frpsel ? "Y" : "N"); 4444 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4445 priv->dma_cap.addr64); 4446 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4447 priv->dma_cap.rssen ? "Y" : "N"); 4448 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4449 priv->dma_cap.vlhash ? "Y" : "N"); 4450 seq_printf(seq, "\tSplit Header: %s\n", 4451 priv->dma_cap.sphen ? "Y" : "N"); 4452 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4453 priv->dma_cap.vlins ? "Y" : "N"); 4454 seq_printf(seq, "\tDouble VLAN: %s\n", 4455 priv->dma_cap.dvlan ? "Y" : "N"); 4456 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4457 priv->dma_cap.l3l4fnum); 4458 seq_printf(seq, "\tARP Offloading: %s\n", 4459 priv->dma_cap.arpoffsel ? "Y" : "N"); 4460 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4461 priv->dma_cap.estsel ? "Y" : "N"); 4462 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4463 priv->dma_cap.fpesel ? "Y" : "N"); 4464 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4465 priv->dma_cap.tbssel ? "Y" : "N"); 4466 return 0; 4467 } 4468 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4469 4470 /* Use network device events to rename debugfs file entries. 4471 */ 4472 static int stmmac_device_event(struct notifier_block *unused, 4473 unsigned long event, void *ptr) 4474 { 4475 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4476 struct stmmac_priv *priv = netdev_priv(dev); 4477 4478 if (dev->netdev_ops != &stmmac_netdev_ops) 4479 goto done; 4480 4481 switch (event) { 4482 case NETDEV_CHANGENAME: 4483 if (priv->dbgfs_dir) 4484 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4485 priv->dbgfs_dir, 4486 stmmac_fs_dir, 4487 dev->name); 4488 break; 4489 } 4490 done: 4491 return NOTIFY_DONE; 4492 } 4493 4494 static struct notifier_block stmmac_notifier = { 4495 .notifier_call = stmmac_device_event, 4496 }; 4497 4498 static void stmmac_init_fs(struct net_device *dev) 4499 { 4500 struct stmmac_priv *priv = netdev_priv(dev); 4501 4502 rtnl_lock(); 4503 4504 /* Create per netdev entries */ 4505 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4506 4507 /* Entry to report DMA RX/TX rings */ 4508 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4509 &stmmac_rings_status_fops); 4510 4511 /* Entry to report the DMA HW features */ 4512 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4513 &stmmac_dma_cap_fops); 4514 4515 rtnl_unlock(); 4516 } 4517 4518 static void stmmac_exit_fs(struct net_device *dev) 4519 { 4520 struct stmmac_priv *priv = netdev_priv(dev); 4521 4522 debugfs_remove_recursive(priv->dbgfs_dir); 4523 } 4524 #endif /* CONFIG_DEBUG_FS */ 4525 4526 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4527 { 4528 unsigned char *data = (unsigned char *)&vid_le; 4529 unsigned char data_byte = 0; 4530 u32 crc = ~0x0; 4531 u32 temp = 0; 4532 int i, bits; 4533 4534 bits = get_bitmask_order(VLAN_VID_MASK); 4535 for (i = 0; i < bits; i++) { 4536 if ((i % 8) == 0) 4537 data_byte = data[i / 8]; 4538 4539 temp = ((crc & 1) ^ data_byte) & 1; 4540 crc >>= 1; 4541 data_byte >>= 1; 4542 4543 if (temp) 4544 crc ^= 0xedb88320; 4545 } 4546 4547 return crc; 4548 } 4549 4550 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4551 { 4552 u32 crc, hash = 0; 4553 __le16 pmatch = 0; 4554 int count = 0; 4555 u16 vid = 0; 4556 4557 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4558 __le16 vid_le = cpu_to_le16(vid); 4559 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4560 hash |= (1 << crc); 4561 count++; 4562 } 4563 4564 if (!priv->dma_cap.vlhash) { 4565 if (count > 2) /* VID = 0 always passes filter */ 4566 return -EOPNOTSUPP; 4567 4568 pmatch = cpu_to_le16(vid); 4569 hash = 0; 4570 } 4571 4572 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4573 } 4574 4575 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4576 { 4577 struct stmmac_priv *priv = netdev_priv(ndev); 4578 bool is_double = false; 4579 int ret; 4580 4581 if (be16_to_cpu(proto) == ETH_P_8021AD) 4582 is_double = true; 4583 4584 set_bit(vid, priv->active_vlans); 4585 ret = stmmac_vlan_update(priv, is_double); 4586 if (ret) { 4587 clear_bit(vid, priv->active_vlans); 4588 return ret; 4589 } 4590 4591 if (priv->hw->num_vlan) { 4592 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4593 if (ret) 4594 return ret; 4595 } 4596 4597 return 0; 4598 } 4599 4600 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4601 { 4602 struct stmmac_priv *priv = netdev_priv(ndev); 4603 bool is_double = false; 4604 int ret; 4605 4606 if (be16_to_cpu(proto) == ETH_P_8021AD) 4607 is_double = true; 4608 4609 clear_bit(vid, priv->active_vlans); 4610 4611 if (priv->hw->num_vlan) { 4612 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4613 if (ret) 4614 return ret; 4615 } 4616 4617 return stmmac_vlan_update(priv, is_double); 4618 } 4619 4620 static const struct net_device_ops stmmac_netdev_ops = { 4621 .ndo_open = stmmac_open, 4622 .ndo_start_xmit = stmmac_xmit, 4623 .ndo_stop = stmmac_release, 4624 .ndo_change_mtu = stmmac_change_mtu, 4625 .ndo_fix_features = stmmac_fix_features, 4626 .ndo_set_features = stmmac_set_features, 4627 .ndo_set_rx_mode = stmmac_set_rx_mode, 4628 .ndo_tx_timeout = stmmac_tx_timeout, 4629 .ndo_do_ioctl = stmmac_ioctl, 4630 .ndo_setup_tc = stmmac_setup_tc, 4631 .ndo_select_queue = stmmac_select_queue, 4632 #ifdef CONFIG_NET_POLL_CONTROLLER 4633 .ndo_poll_controller = stmmac_poll_controller, 4634 #endif 4635 .ndo_set_mac_address = stmmac_set_mac_address, 4636 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4637 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4638 }; 4639 4640 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4641 { 4642 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4643 return; 4644 if (test_bit(STMMAC_DOWN, &priv->state)) 4645 return; 4646 4647 netdev_err(priv->dev, "Reset adapter.\n"); 4648 4649 rtnl_lock(); 4650 netif_trans_update(priv->dev); 4651 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4652 usleep_range(1000, 2000); 4653 4654 set_bit(STMMAC_DOWN, &priv->state); 4655 dev_close(priv->dev); 4656 dev_open(priv->dev, NULL); 4657 clear_bit(STMMAC_DOWN, &priv->state); 4658 clear_bit(STMMAC_RESETING, &priv->state); 4659 rtnl_unlock(); 4660 } 4661 4662 static void stmmac_service_task(struct work_struct *work) 4663 { 4664 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4665 service_task); 4666 4667 stmmac_reset_subtask(priv); 4668 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4669 } 4670 4671 /** 4672 * stmmac_hw_init - Init the MAC device 4673 * @priv: driver private structure 4674 * Description: this function is to configure the MAC device according to 4675 * some platform parameters or the HW capability register. It prepares the 4676 * driver to use either ring or chain modes and to setup either enhanced or 4677 * normal descriptors. 4678 */ 4679 static int stmmac_hw_init(struct stmmac_priv *priv) 4680 { 4681 int ret; 4682 4683 /* dwmac-sun8i only work in chain mode */ 4684 if (priv->plat->has_sun8i) 4685 chain_mode = 1; 4686 priv->chain_mode = chain_mode; 4687 4688 /* Initialize HW Interface */ 4689 ret = stmmac_hwif_init(priv); 4690 if (ret) 4691 return ret; 4692 4693 /* Get the HW capability (new GMAC newer than 3.50a) */ 4694 priv->hw_cap_support = stmmac_get_hw_features(priv); 4695 if (priv->hw_cap_support) { 4696 dev_info(priv->device, "DMA HW capability register supported\n"); 4697 4698 /* We can override some gmac/dma configuration fields: e.g. 4699 * enh_desc, tx_coe (e.g. that are passed through the 4700 * platform) with the values from the HW capability 4701 * register (if supported). 4702 */ 4703 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4704 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4705 priv->hw->pmt = priv->plat->pmt; 4706 if (priv->dma_cap.hash_tb_sz) { 4707 priv->hw->multicast_filter_bins = 4708 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4709 priv->hw->mcast_bits_log2 = 4710 ilog2(priv->hw->multicast_filter_bins); 4711 } 4712 4713 /* TXCOE doesn't work in thresh DMA mode */ 4714 if (priv->plat->force_thresh_dma_mode) 4715 priv->plat->tx_coe = 0; 4716 else 4717 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4718 4719 /* In case of GMAC4 rx_coe is from HW cap register. */ 4720 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4721 4722 if (priv->dma_cap.rx_coe_type2) 4723 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4724 else if (priv->dma_cap.rx_coe_type1) 4725 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4726 4727 } else { 4728 dev_info(priv->device, "No HW DMA feature register supported\n"); 4729 } 4730 4731 if (priv->plat->rx_coe) { 4732 priv->hw->rx_csum = priv->plat->rx_coe; 4733 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4734 if (priv->synopsys_id < DWMAC_CORE_4_00) 4735 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4736 } 4737 if (priv->plat->tx_coe) 4738 dev_info(priv->device, "TX Checksum insertion supported\n"); 4739 4740 if (priv->plat->pmt) { 4741 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4742 device_set_wakeup_capable(priv->device, 1); 4743 } 4744 4745 if (priv->dma_cap.tsoen) 4746 dev_info(priv->device, "TSO supported\n"); 4747 4748 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 4749 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 4750 4751 /* Run HW quirks, if any */ 4752 if (priv->hwif_quirks) { 4753 ret = priv->hwif_quirks(priv); 4754 if (ret) 4755 return ret; 4756 } 4757 4758 /* Rx Watchdog is available in the COREs newer than the 3.40. 4759 * In some case, for example on bugged HW this feature 4760 * has to be disable and this can be done by passing the 4761 * riwt_off field from the platform. 4762 */ 4763 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4764 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4765 priv->use_riwt = 1; 4766 dev_info(priv->device, 4767 "Enable RX Mitigation via HW Watchdog Timer\n"); 4768 } 4769 4770 return 0; 4771 } 4772 4773 static void stmmac_napi_add(struct net_device *dev) 4774 { 4775 struct stmmac_priv *priv = netdev_priv(dev); 4776 u32 queue, maxq; 4777 4778 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4779 4780 for (queue = 0; queue < maxq; queue++) { 4781 struct stmmac_channel *ch = &priv->channel[queue]; 4782 4783 ch->priv_data = priv; 4784 ch->index = queue; 4785 spin_lock_init(&ch->lock); 4786 4787 if (queue < priv->plat->rx_queues_to_use) { 4788 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 4789 NAPI_POLL_WEIGHT); 4790 } 4791 if (queue < priv->plat->tx_queues_to_use) { 4792 netif_tx_napi_add(dev, &ch->tx_napi, 4793 stmmac_napi_poll_tx, 4794 NAPI_POLL_WEIGHT); 4795 } 4796 } 4797 } 4798 4799 static void stmmac_napi_del(struct net_device *dev) 4800 { 4801 struct stmmac_priv *priv = netdev_priv(dev); 4802 u32 queue, maxq; 4803 4804 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4805 4806 for (queue = 0; queue < maxq; queue++) { 4807 struct stmmac_channel *ch = &priv->channel[queue]; 4808 4809 if (queue < priv->plat->rx_queues_to_use) 4810 netif_napi_del(&ch->rx_napi); 4811 if (queue < priv->plat->tx_queues_to_use) 4812 netif_napi_del(&ch->tx_napi); 4813 } 4814 } 4815 4816 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 4817 { 4818 struct stmmac_priv *priv = netdev_priv(dev); 4819 int ret = 0; 4820 4821 if (netif_running(dev)) 4822 stmmac_release(dev); 4823 4824 stmmac_napi_del(dev); 4825 4826 priv->plat->rx_queues_to_use = rx_cnt; 4827 priv->plat->tx_queues_to_use = tx_cnt; 4828 4829 stmmac_napi_add(dev); 4830 4831 if (netif_running(dev)) 4832 ret = stmmac_open(dev); 4833 4834 return ret; 4835 } 4836 4837 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 4838 { 4839 struct stmmac_priv *priv = netdev_priv(dev); 4840 int ret = 0; 4841 4842 if (netif_running(dev)) 4843 stmmac_release(dev); 4844 4845 priv->dma_rx_size = rx_size; 4846 priv->dma_tx_size = tx_size; 4847 4848 if (netif_running(dev)) 4849 ret = stmmac_open(dev); 4850 4851 return ret; 4852 } 4853 4854 /** 4855 * stmmac_dvr_probe 4856 * @device: device pointer 4857 * @plat_dat: platform data pointer 4858 * @res: stmmac resource pointer 4859 * Description: this is the main probe function used to 4860 * call the alloc_etherdev, allocate the priv structure. 4861 * Return: 4862 * returns 0 on success, otherwise errno. 4863 */ 4864 int stmmac_dvr_probe(struct device *device, 4865 struct plat_stmmacenet_data *plat_dat, 4866 struct stmmac_resources *res) 4867 { 4868 struct net_device *ndev = NULL; 4869 struct stmmac_priv *priv; 4870 u32 rxq; 4871 int i, ret = 0; 4872 4873 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4874 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4875 if (!ndev) 4876 return -ENOMEM; 4877 4878 SET_NETDEV_DEV(ndev, device); 4879 4880 priv = netdev_priv(ndev); 4881 priv->device = device; 4882 priv->dev = ndev; 4883 4884 stmmac_set_ethtool_ops(ndev); 4885 priv->pause = pause; 4886 priv->plat = plat_dat; 4887 priv->ioaddr = res->addr; 4888 priv->dev->base_addr = (unsigned long)res->addr; 4889 4890 priv->dev->irq = res->irq; 4891 priv->wol_irq = res->wol_irq; 4892 priv->lpi_irq = res->lpi_irq; 4893 4894 if (!IS_ERR_OR_NULL(res->mac)) 4895 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4896 4897 dev_set_drvdata(device, priv->dev); 4898 4899 /* Verify driver arguments */ 4900 stmmac_verify_args(); 4901 4902 /* Allocate workqueue */ 4903 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4904 if (!priv->wq) { 4905 dev_err(priv->device, "failed to create workqueue\n"); 4906 return -ENOMEM; 4907 } 4908 4909 INIT_WORK(&priv->service_task, stmmac_service_task); 4910 4911 /* Override with kernel parameters if supplied XXX CRS XXX 4912 * this needs to have multiple instances 4913 */ 4914 if ((phyaddr >= 0) && (phyaddr <= 31)) 4915 priv->plat->phy_addr = phyaddr; 4916 4917 if (priv->plat->stmmac_rst) { 4918 ret = reset_control_assert(priv->plat->stmmac_rst); 4919 reset_control_deassert(priv->plat->stmmac_rst); 4920 /* Some reset controllers have only reset callback instead of 4921 * assert + deassert callbacks pair. 4922 */ 4923 if (ret == -ENOTSUPP) 4924 reset_control_reset(priv->plat->stmmac_rst); 4925 } 4926 4927 /* Init MAC and get the capabilities */ 4928 ret = stmmac_hw_init(priv); 4929 if (ret) 4930 goto error_hw_init; 4931 4932 stmmac_check_ether_addr(priv); 4933 4934 ndev->netdev_ops = &stmmac_netdev_ops; 4935 4936 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4937 NETIF_F_RXCSUM; 4938 4939 ret = stmmac_tc_init(priv, priv); 4940 if (!ret) { 4941 ndev->hw_features |= NETIF_F_HW_TC; 4942 } 4943 4944 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4945 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4946 if (priv->plat->has_gmac4) 4947 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4948 priv->tso = true; 4949 dev_info(priv->device, "TSO feature enabled\n"); 4950 } 4951 4952 if (priv->dma_cap.sphen) { 4953 ndev->hw_features |= NETIF_F_GRO; 4954 priv->sph = true; 4955 dev_info(priv->device, "SPH feature enabled\n"); 4956 } 4957 4958 if (priv->dma_cap.addr64) { 4959 ret = dma_set_mask_and_coherent(device, 4960 DMA_BIT_MASK(priv->dma_cap.addr64)); 4961 if (!ret) { 4962 dev_info(priv->device, "Using %d bits DMA width\n", 4963 priv->dma_cap.addr64); 4964 4965 /* 4966 * If more than 32 bits can be addressed, make sure to 4967 * enable enhanced addressing mode. 4968 */ 4969 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4970 priv->plat->dma_cfg->eame = true; 4971 } else { 4972 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4973 if (ret) { 4974 dev_err(priv->device, "Failed to set DMA Mask\n"); 4975 goto error_hw_init; 4976 } 4977 4978 priv->dma_cap.addr64 = 32; 4979 } 4980 } 4981 4982 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4983 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4984 #ifdef STMMAC_VLAN_TAG_USED 4985 /* Both mac100 and gmac support receive VLAN tag detection */ 4986 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4987 if (priv->dma_cap.vlhash) { 4988 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4989 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4990 } 4991 if (priv->dma_cap.vlins) { 4992 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4993 if (priv->dma_cap.dvlan) 4994 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4995 } 4996 #endif 4997 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4998 4999 /* Initialize RSS */ 5000 rxq = priv->plat->rx_queues_to_use; 5001 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 5002 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 5003 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 5004 5005 if (priv->dma_cap.rssen && priv->plat->rss_en) 5006 ndev->features |= NETIF_F_RXHASH; 5007 5008 /* MTU range: 46 - hw-specific max */ 5009 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 5010 if (priv->plat->has_xgmac) 5011 ndev->max_mtu = XGMAC_JUMBO_LEN; 5012 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 5013 ndev->max_mtu = JUMBO_LEN; 5014 else 5015 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 5016 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 5017 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 5018 */ 5019 if ((priv->plat->maxmtu < ndev->max_mtu) && 5020 (priv->plat->maxmtu >= ndev->min_mtu)) 5021 ndev->max_mtu = priv->plat->maxmtu; 5022 else if (priv->plat->maxmtu < ndev->min_mtu) 5023 dev_warn(priv->device, 5024 "%s: warning: maxmtu having invalid value (%d)\n", 5025 __func__, priv->plat->maxmtu); 5026 5027 if (flow_ctrl) 5028 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 5029 5030 /* Setup channels NAPI */ 5031 stmmac_napi_add(ndev); 5032 5033 mutex_init(&priv->lock); 5034 5035 /* If a specific clk_csr value is passed from the platform 5036 * this means that the CSR Clock Range selection cannot be 5037 * changed at run-time and it is fixed. Viceversa the driver'll try to 5038 * set the MDC clock dynamically according to the csr actual 5039 * clock input. 5040 */ 5041 if (priv->plat->clk_csr >= 0) 5042 priv->clk_csr = priv->plat->clk_csr; 5043 else 5044 stmmac_clk_csr_set(priv); 5045 5046 stmmac_check_pcs_mode(priv); 5047 5048 if (priv->hw->pcs != STMMAC_PCS_TBI && 5049 priv->hw->pcs != STMMAC_PCS_RTBI) { 5050 /* MDIO bus Registration */ 5051 ret = stmmac_mdio_register(ndev); 5052 if (ret < 0) { 5053 dev_err(priv->device, 5054 "%s: MDIO bus (id: %d) registration failed", 5055 __func__, priv->plat->bus_id); 5056 goto error_mdio_register; 5057 } 5058 } 5059 5060 ret = stmmac_phy_setup(priv); 5061 if (ret) { 5062 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 5063 goto error_phy_setup; 5064 } 5065 5066 ret = register_netdev(ndev); 5067 if (ret) { 5068 dev_err(priv->device, "%s: ERROR %i registering the device\n", 5069 __func__, ret); 5070 goto error_netdev_register; 5071 } 5072 5073 if (priv->plat->serdes_powerup) { 5074 ret = priv->plat->serdes_powerup(ndev, 5075 priv->plat->bsp_priv); 5076 5077 if (ret < 0) 5078 goto error_serdes_powerup; 5079 } 5080 5081 #ifdef CONFIG_DEBUG_FS 5082 stmmac_init_fs(ndev); 5083 #endif 5084 5085 return ret; 5086 5087 error_serdes_powerup: 5088 unregister_netdev(ndev); 5089 error_netdev_register: 5090 phylink_destroy(priv->phylink); 5091 error_phy_setup: 5092 if (priv->hw->pcs != STMMAC_PCS_TBI && 5093 priv->hw->pcs != STMMAC_PCS_RTBI) 5094 stmmac_mdio_unregister(ndev); 5095 error_mdio_register: 5096 stmmac_napi_del(ndev); 5097 error_hw_init: 5098 destroy_workqueue(priv->wq); 5099 5100 return ret; 5101 } 5102 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5103 5104 /** 5105 * stmmac_dvr_remove 5106 * @dev: device pointer 5107 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5108 * changes the link status, releases the DMA descriptor rings. 5109 */ 5110 int stmmac_dvr_remove(struct device *dev) 5111 { 5112 struct net_device *ndev = dev_get_drvdata(dev); 5113 struct stmmac_priv *priv = netdev_priv(ndev); 5114 5115 netdev_info(priv->dev, "%s: removing driver", __func__); 5116 5117 stmmac_stop_all_dma(priv); 5118 5119 if (priv->plat->serdes_powerdown) 5120 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5121 5122 stmmac_mac_set(priv, priv->ioaddr, false); 5123 netif_carrier_off(ndev); 5124 unregister_netdev(ndev); 5125 #ifdef CONFIG_DEBUG_FS 5126 stmmac_exit_fs(ndev); 5127 #endif 5128 phylink_destroy(priv->phylink); 5129 if (priv->plat->stmmac_rst) 5130 reset_control_assert(priv->plat->stmmac_rst); 5131 clk_disable_unprepare(priv->plat->pclk); 5132 clk_disable_unprepare(priv->plat->stmmac_clk); 5133 if (priv->hw->pcs != STMMAC_PCS_TBI && 5134 priv->hw->pcs != STMMAC_PCS_RTBI) 5135 stmmac_mdio_unregister(ndev); 5136 destroy_workqueue(priv->wq); 5137 mutex_destroy(&priv->lock); 5138 5139 return 0; 5140 } 5141 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5142 5143 /** 5144 * stmmac_suspend - suspend callback 5145 * @dev: device pointer 5146 * Description: this is the function to suspend the device and it is called 5147 * by the platform driver to stop the network queue, release the resources, 5148 * program the PMT register (for WoL), clean and release driver resources. 5149 */ 5150 int stmmac_suspend(struct device *dev) 5151 { 5152 struct net_device *ndev = dev_get_drvdata(dev); 5153 struct stmmac_priv *priv = netdev_priv(ndev); 5154 u32 chan; 5155 5156 if (!ndev || !netif_running(ndev)) 5157 return 0; 5158 5159 phylink_mac_change(priv->phylink, false); 5160 5161 mutex_lock(&priv->lock); 5162 5163 netif_device_detach(ndev); 5164 5165 stmmac_disable_all_queues(priv); 5166 5167 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5168 del_timer_sync(&priv->tx_queue[chan].txtimer); 5169 5170 /* Stop TX/RX DMA */ 5171 stmmac_stop_all_dma(priv); 5172 5173 if (priv->plat->serdes_powerdown) 5174 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5175 5176 /* Enable Power down mode by programming the PMT regs */ 5177 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5178 stmmac_pmt(priv, priv->hw, priv->wolopts); 5179 priv->irq_wake = 1; 5180 } else { 5181 mutex_unlock(&priv->lock); 5182 rtnl_lock(); 5183 if (device_may_wakeup(priv->device)) 5184 phylink_speed_down(priv->phylink, false); 5185 phylink_stop(priv->phylink); 5186 rtnl_unlock(); 5187 mutex_lock(&priv->lock); 5188 5189 stmmac_mac_set(priv, priv->ioaddr, false); 5190 pinctrl_pm_select_sleep_state(priv->device); 5191 /* Disable clock in case of PWM is off */ 5192 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5193 clk_disable_unprepare(priv->plat->pclk); 5194 clk_disable_unprepare(priv->plat->stmmac_clk); 5195 } 5196 mutex_unlock(&priv->lock); 5197 5198 priv->speed = SPEED_UNKNOWN; 5199 return 0; 5200 } 5201 EXPORT_SYMBOL_GPL(stmmac_suspend); 5202 5203 /** 5204 * stmmac_reset_queues_param - reset queue parameters 5205 * @priv: device pointer 5206 */ 5207 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5208 { 5209 u32 rx_cnt = priv->plat->rx_queues_to_use; 5210 u32 tx_cnt = priv->plat->tx_queues_to_use; 5211 u32 queue; 5212 5213 for (queue = 0; queue < rx_cnt; queue++) { 5214 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5215 5216 rx_q->cur_rx = 0; 5217 rx_q->dirty_rx = 0; 5218 } 5219 5220 for (queue = 0; queue < tx_cnt; queue++) { 5221 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5222 5223 tx_q->cur_tx = 0; 5224 tx_q->dirty_tx = 0; 5225 tx_q->mss = 0; 5226 } 5227 } 5228 5229 /** 5230 * stmmac_resume - resume callback 5231 * @dev: device pointer 5232 * Description: when resume this function is invoked to setup the DMA and CORE 5233 * in a usable state. 5234 */ 5235 int stmmac_resume(struct device *dev) 5236 { 5237 struct net_device *ndev = dev_get_drvdata(dev); 5238 struct stmmac_priv *priv = netdev_priv(ndev); 5239 int ret; 5240 5241 if (!netif_running(ndev)) 5242 return 0; 5243 5244 /* Power Down bit, into the PM register, is cleared 5245 * automatically as soon as a magic packet or a Wake-up frame 5246 * is received. Anyway, it's better to manually clear 5247 * this bit because it can generate problems while resuming 5248 * from another devices (e.g. serial console). 5249 */ 5250 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5251 mutex_lock(&priv->lock); 5252 stmmac_pmt(priv, priv->hw, 0); 5253 mutex_unlock(&priv->lock); 5254 priv->irq_wake = 0; 5255 } else { 5256 pinctrl_pm_select_default_state(priv->device); 5257 /* enable the clk previously disabled */ 5258 clk_prepare_enable(priv->plat->stmmac_clk); 5259 clk_prepare_enable(priv->plat->pclk); 5260 if (priv->plat->clk_ptp_ref) 5261 clk_prepare_enable(priv->plat->clk_ptp_ref); 5262 /* reset the phy so that it's ready */ 5263 if (priv->mii) 5264 stmmac_mdio_reset(priv->mii); 5265 } 5266 5267 if (priv->plat->serdes_powerup) { 5268 ret = priv->plat->serdes_powerup(ndev, 5269 priv->plat->bsp_priv); 5270 5271 if (ret < 0) 5272 return ret; 5273 } 5274 5275 rtnl_lock(); 5276 mutex_lock(&priv->lock); 5277 5278 stmmac_reset_queues_param(priv); 5279 5280 stmmac_clear_descriptors(priv); 5281 5282 stmmac_hw_setup(ndev, false); 5283 stmmac_init_coalesce(priv); 5284 stmmac_set_rx_mode(ndev); 5285 5286 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5287 5288 stmmac_enable_all_queues(priv); 5289 5290 mutex_unlock(&priv->lock); 5291 rtnl_unlock(); 5292 5293 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 5294 rtnl_lock(); 5295 phylink_start(priv->phylink); 5296 /* We may have called phylink_speed_down before */ 5297 phylink_speed_up(priv->phylink); 5298 rtnl_unlock(); 5299 } 5300 5301 phylink_mac_change(priv->phylink, true); 5302 5303 netif_device_attach(ndev); 5304 5305 return 0; 5306 } 5307 EXPORT_SYMBOL_GPL(stmmac_resume); 5308 5309 #ifndef MODULE 5310 static int __init stmmac_cmdline_opt(char *str) 5311 { 5312 char *opt; 5313 5314 if (!str || !*str) 5315 return -EINVAL; 5316 while ((opt = strsep(&str, ",")) != NULL) { 5317 if (!strncmp(opt, "debug:", 6)) { 5318 if (kstrtoint(opt + 6, 0, &debug)) 5319 goto err; 5320 } else if (!strncmp(opt, "phyaddr:", 8)) { 5321 if (kstrtoint(opt + 8, 0, &phyaddr)) 5322 goto err; 5323 } else if (!strncmp(opt, "buf_sz:", 7)) { 5324 if (kstrtoint(opt + 7, 0, &buf_sz)) 5325 goto err; 5326 } else if (!strncmp(opt, "tc:", 3)) { 5327 if (kstrtoint(opt + 3, 0, &tc)) 5328 goto err; 5329 } else if (!strncmp(opt, "watchdog:", 9)) { 5330 if (kstrtoint(opt + 9, 0, &watchdog)) 5331 goto err; 5332 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5333 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5334 goto err; 5335 } else if (!strncmp(opt, "pause:", 6)) { 5336 if (kstrtoint(opt + 6, 0, &pause)) 5337 goto err; 5338 } else if (!strncmp(opt, "eee_timer:", 10)) { 5339 if (kstrtoint(opt + 10, 0, &eee_timer)) 5340 goto err; 5341 } else if (!strncmp(opt, "chain_mode:", 11)) { 5342 if (kstrtoint(opt + 11, 0, &chain_mode)) 5343 goto err; 5344 } 5345 } 5346 return 0; 5347 5348 err: 5349 pr_err("%s: ERROR broken module parameter conversion", __func__); 5350 return -EINVAL; 5351 } 5352 5353 __setup("stmmaceth=", stmmac_cmdline_opt); 5354 #endif /* MODULE */ 5355 5356 static int __init stmmac_init(void) 5357 { 5358 #ifdef CONFIG_DEBUG_FS 5359 /* Create debugfs main directory if it doesn't exist yet */ 5360 if (!stmmac_fs_dir) 5361 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5362 register_netdevice_notifier(&stmmac_notifier); 5363 #endif 5364 5365 return 0; 5366 } 5367 5368 static void __exit stmmac_exit(void) 5369 { 5370 #ifdef CONFIG_DEBUG_FS 5371 unregister_netdevice_notifier(&stmmac_notifier); 5372 debugfs_remove_recursive(stmmac_fs_dir); 5373 #endif 5374 } 5375 5376 module_init(stmmac_init) 5377 module_exit(stmmac_exit) 5378 5379 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5380 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5381 MODULE_LICENSE("GPL"); 5382