1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 22 #define REG_SPACE_SIZE 0x1060 23 #define MAC100_ETHTOOL_NAME "st_mac100" 24 #define GMAC_ETHTOOL_NAME "st_gmac" 25 26 #define ETHTOOL_DMA_OFFSET 55 27 28 struct stmmac_stats { 29 char stat_string[ETH_GSTRING_LEN]; 30 int sizeof_stat; 31 int stat_offset; 32 }; 33 34 #define STMMAC_STAT(m) \ 35 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \ 36 offsetof(struct stmmac_priv, xstats.m)} 37 38 static const struct stmmac_stats stmmac_gstrings_stats[] = { 39 /* Transmit errors */ 40 STMMAC_STAT(tx_underflow), 41 STMMAC_STAT(tx_carrier), 42 STMMAC_STAT(tx_losscarrier), 43 STMMAC_STAT(vlan_tag), 44 STMMAC_STAT(tx_deferred), 45 STMMAC_STAT(tx_vlan), 46 STMMAC_STAT(tx_jabber), 47 STMMAC_STAT(tx_frame_flushed), 48 STMMAC_STAT(tx_payload_error), 49 STMMAC_STAT(tx_ip_header_error), 50 /* Receive errors */ 51 STMMAC_STAT(rx_desc), 52 STMMAC_STAT(sa_filter_fail), 53 STMMAC_STAT(overflow_error), 54 STMMAC_STAT(ipc_csum_error), 55 STMMAC_STAT(rx_collision), 56 STMMAC_STAT(rx_crc_errors), 57 STMMAC_STAT(dribbling_bit), 58 STMMAC_STAT(rx_length), 59 STMMAC_STAT(rx_mii), 60 STMMAC_STAT(rx_multicast), 61 STMMAC_STAT(rx_gmac_overflow), 62 STMMAC_STAT(rx_watchdog), 63 STMMAC_STAT(da_rx_filter_fail), 64 STMMAC_STAT(sa_rx_filter_fail), 65 STMMAC_STAT(rx_missed_cntr), 66 STMMAC_STAT(rx_overflow_cntr), 67 STMMAC_STAT(rx_vlan), 68 /* Tx/Rx IRQ error info */ 69 STMMAC_STAT(tx_undeflow_irq), 70 STMMAC_STAT(tx_process_stopped_irq), 71 STMMAC_STAT(tx_jabber_irq), 72 STMMAC_STAT(rx_overflow_irq), 73 STMMAC_STAT(rx_buf_unav_irq), 74 STMMAC_STAT(rx_process_stopped_irq), 75 STMMAC_STAT(rx_watchdog_irq), 76 STMMAC_STAT(tx_early_irq), 77 STMMAC_STAT(fatal_bus_error_irq), 78 /* Tx/Rx IRQ Events */ 79 STMMAC_STAT(rx_early_irq), 80 STMMAC_STAT(threshold), 81 STMMAC_STAT(tx_pkt_n), 82 STMMAC_STAT(rx_pkt_n), 83 STMMAC_STAT(normal_irq_n), 84 STMMAC_STAT(rx_normal_irq_n), 85 STMMAC_STAT(napi_poll), 86 STMMAC_STAT(tx_normal_irq_n), 87 STMMAC_STAT(tx_clean), 88 STMMAC_STAT(tx_set_ic_bit), 89 STMMAC_STAT(irq_receive_pmt_irq_n), 90 /* MMC info */ 91 STMMAC_STAT(mmc_tx_irq_n), 92 STMMAC_STAT(mmc_rx_irq_n), 93 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 94 /* EEE */ 95 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 96 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 97 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 98 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 99 STMMAC_STAT(phy_eee_wakeup_error_n), 100 /* Extended RDES status */ 101 STMMAC_STAT(ip_hdr_err), 102 STMMAC_STAT(ip_payload_err), 103 STMMAC_STAT(ip_csum_bypassed), 104 STMMAC_STAT(ipv4_pkt_rcvd), 105 STMMAC_STAT(ipv6_pkt_rcvd), 106 STMMAC_STAT(no_ptp_rx_msg_type_ext), 107 STMMAC_STAT(ptp_rx_msg_type_sync), 108 STMMAC_STAT(ptp_rx_msg_type_follow_up), 109 STMMAC_STAT(ptp_rx_msg_type_delay_req), 110 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 111 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 112 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 113 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 114 STMMAC_STAT(ptp_rx_msg_type_announce), 115 STMMAC_STAT(ptp_rx_msg_type_management), 116 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 117 STMMAC_STAT(ptp_frame_type), 118 STMMAC_STAT(ptp_ver), 119 STMMAC_STAT(timestamp_dropped), 120 STMMAC_STAT(av_pkt_rcvd), 121 STMMAC_STAT(av_tagged_pkt_rcvd), 122 STMMAC_STAT(vlan_tag_priority_val), 123 STMMAC_STAT(l3_filter_match), 124 STMMAC_STAT(l4_filter_match), 125 STMMAC_STAT(l3_l4_filter_no_match), 126 /* PCS */ 127 STMMAC_STAT(irq_pcs_ane_n), 128 STMMAC_STAT(irq_pcs_link_n), 129 STMMAC_STAT(irq_rgmii_n), 130 /* DEBUG */ 131 STMMAC_STAT(mtl_tx_status_fifo_full), 132 STMMAC_STAT(mtl_tx_fifo_not_empty), 133 STMMAC_STAT(mmtl_fifo_ctrl), 134 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 135 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 136 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 138 STMMAC_STAT(mac_tx_in_pause), 139 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 140 STMMAC_STAT(mac_tx_frame_ctrl_idle), 141 STMMAC_STAT(mac_tx_frame_ctrl_wait), 142 STMMAC_STAT(mac_tx_frame_ctrl_pause), 143 STMMAC_STAT(mac_gmii_tx_proto_engine), 144 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 145 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 146 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 148 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 149 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 150 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 152 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 153 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 154 STMMAC_STAT(mac_gmii_rx_proto_engine), 155 /* TSO */ 156 STMMAC_STAT(tx_tso_frames), 157 STMMAC_STAT(tx_tso_nfrags), 158 }; 159 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 160 161 /* HW MAC Management counters (if supported) */ 162 #define STMMAC_MMC_STAT(m) \ 163 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \ 164 offsetof(struct stmmac_priv, mmc.m)} 165 166 static const struct stmmac_stats stmmac_mmc[] = { 167 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 168 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 169 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 170 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 171 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 172 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 173 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 174 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 175 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 176 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 177 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 178 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 179 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 180 STMMAC_MMC_STAT(mmc_tx_underflow_error), 181 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 182 STMMAC_MMC_STAT(mmc_tx_multicol_g), 183 STMMAC_MMC_STAT(mmc_tx_deferred), 184 STMMAC_MMC_STAT(mmc_tx_latecol), 185 STMMAC_MMC_STAT(mmc_tx_exesscol), 186 STMMAC_MMC_STAT(mmc_tx_carrier_error), 187 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 188 STMMAC_MMC_STAT(mmc_tx_framecount_g), 189 STMMAC_MMC_STAT(mmc_tx_excessdef), 190 STMMAC_MMC_STAT(mmc_tx_pause_frame), 191 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 192 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 193 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 194 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 195 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 196 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 197 STMMAC_MMC_STAT(mmc_rx_crc_error), 198 STMMAC_MMC_STAT(mmc_rx_align_error), 199 STMMAC_MMC_STAT(mmc_rx_run_error), 200 STMMAC_MMC_STAT(mmc_rx_jabber_error), 201 STMMAC_MMC_STAT(mmc_rx_undersize_g), 202 STMMAC_MMC_STAT(mmc_rx_oversize_g), 203 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 204 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 205 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 206 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 207 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 208 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 209 STMMAC_MMC_STAT(mmc_rx_unicast_g), 210 STMMAC_MMC_STAT(mmc_rx_length_error), 211 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 212 STMMAC_MMC_STAT(mmc_rx_pause_frames), 213 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 214 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 215 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 216 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 217 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 218 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 219 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 220 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 221 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 222 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 223 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 224 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 225 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 226 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 227 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 228 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 229 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 230 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 231 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 232 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 233 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 234 STMMAC_MMC_STAT(mmc_rx_udp_gd), 235 STMMAC_MMC_STAT(mmc_rx_udp_err), 236 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 237 STMMAC_MMC_STAT(mmc_rx_tcp_err), 238 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 239 STMMAC_MMC_STAT(mmc_rx_icmp_err), 240 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 241 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 242 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 243 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 244 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 245 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 246 }; 247 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 248 249 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 250 struct ethtool_drvinfo *info) 251 { 252 struct stmmac_priv *priv = netdev_priv(dev); 253 254 if (priv->plat->has_gmac || priv->plat->has_gmac4) 255 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 256 else 257 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 258 sizeof(info->driver)); 259 260 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 261 } 262 263 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 264 struct ethtool_link_ksettings *cmd) 265 { 266 struct stmmac_priv *priv = netdev_priv(dev); 267 268 if (priv->hw->pcs & STMMAC_PCS_RGMII || 269 priv->hw->pcs & STMMAC_PCS_SGMII) { 270 struct rgmii_adv adv; 271 u32 supported, advertising, lp_advertising; 272 273 if (!priv->xstats.pcs_link) { 274 cmd->base.speed = SPEED_UNKNOWN; 275 cmd->base.duplex = DUPLEX_UNKNOWN; 276 return 0; 277 } 278 cmd->base.duplex = priv->xstats.pcs_duplex; 279 280 cmd->base.speed = priv->xstats.pcs_speed; 281 282 /* Get and convert ADV/LP_ADV from the HW AN registers */ 283 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 284 return -EOPNOTSUPP; /* should never happen indeed */ 285 286 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 287 288 ethtool_convert_link_mode_to_legacy_u32( 289 &supported, cmd->link_modes.supported); 290 ethtool_convert_link_mode_to_legacy_u32( 291 &advertising, cmd->link_modes.advertising); 292 ethtool_convert_link_mode_to_legacy_u32( 293 &lp_advertising, cmd->link_modes.lp_advertising); 294 295 if (adv.pause & STMMAC_PCS_PAUSE) 296 advertising |= ADVERTISED_Pause; 297 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 298 advertising |= ADVERTISED_Asym_Pause; 299 if (adv.lp_pause & STMMAC_PCS_PAUSE) 300 lp_advertising |= ADVERTISED_Pause; 301 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 302 lp_advertising |= ADVERTISED_Asym_Pause; 303 304 /* Reg49[3] always set because ANE is always supported */ 305 cmd->base.autoneg = ADVERTISED_Autoneg; 306 supported |= SUPPORTED_Autoneg; 307 advertising |= ADVERTISED_Autoneg; 308 lp_advertising |= ADVERTISED_Autoneg; 309 310 if (adv.duplex) { 311 supported |= (SUPPORTED_1000baseT_Full | 312 SUPPORTED_100baseT_Full | 313 SUPPORTED_10baseT_Full); 314 advertising |= (ADVERTISED_1000baseT_Full | 315 ADVERTISED_100baseT_Full | 316 ADVERTISED_10baseT_Full); 317 } else { 318 supported |= (SUPPORTED_1000baseT_Half | 319 SUPPORTED_100baseT_Half | 320 SUPPORTED_10baseT_Half); 321 advertising |= (ADVERTISED_1000baseT_Half | 322 ADVERTISED_100baseT_Half | 323 ADVERTISED_10baseT_Half); 324 } 325 if (adv.lp_duplex) 326 lp_advertising |= (ADVERTISED_1000baseT_Full | 327 ADVERTISED_100baseT_Full | 328 ADVERTISED_10baseT_Full); 329 else 330 lp_advertising |= (ADVERTISED_1000baseT_Half | 331 ADVERTISED_100baseT_Half | 332 ADVERTISED_10baseT_Half); 333 cmd->base.port = PORT_OTHER; 334 335 ethtool_convert_legacy_u32_to_link_mode( 336 cmd->link_modes.supported, supported); 337 ethtool_convert_legacy_u32_to_link_mode( 338 cmd->link_modes.advertising, advertising); 339 ethtool_convert_legacy_u32_to_link_mode( 340 cmd->link_modes.lp_advertising, lp_advertising); 341 342 return 0; 343 } 344 345 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 346 } 347 348 static int 349 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 350 const struct ethtool_link_ksettings *cmd) 351 { 352 struct stmmac_priv *priv = netdev_priv(dev); 353 354 if (priv->hw->pcs & STMMAC_PCS_RGMII || 355 priv->hw->pcs & STMMAC_PCS_SGMII) { 356 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 357 358 /* Only support ANE */ 359 if (cmd->base.autoneg != AUTONEG_ENABLE) 360 return -EINVAL; 361 362 mask &= (ADVERTISED_1000baseT_Half | 363 ADVERTISED_1000baseT_Full | 364 ADVERTISED_100baseT_Half | 365 ADVERTISED_100baseT_Full | 366 ADVERTISED_10baseT_Half | 367 ADVERTISED_10baseT_Full); 368 369 mutex_lock(&priv->lock); 370 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 371 mutex_unlock(&priv->lock); 372 373 return 0; 374 } 375 376 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 377 } 378 379 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 380 { 381 struct stmmac_priv *priv = netdev_priv(dev); 382 return priv->msg_enable; 383 } 384 385 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 386 { 387 struct stmmac_priv *priv = netdev_priv(dev); 388 priv->msg_enable = level; 389 390 } 391 392 static int stmmac_check_if_running(struct net_device *dev) 393 { 394 if (!netif_running(dev)) 395 return -EBUSY; 396 return 0; 397 } 398 399 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 400 { 401 return REG_SPACE_SIZE; 402 } 403 404 static void stmmac_ethtool_gregs(struct net_device *dev, 405 struct ethtool_regs *regs, void *space) 406 { 407 u32 *reg_space = (u32 *) space; 408 409 struct stmmac_priv *priv = netdev_priv(dev); 410 411 memset(reg_space, 0x0, REG_SPACE_SIZE); 412 413 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 414 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 415 /* Copy DMA registers to where ethtool expects them */ 416 memcpy(®_space[ETHTOOL_DMA_OFFSET], ®_space[DMA_BUS_MODE / 4], 417 NUM_DWMAC1000_DMA_REGS * 4); 418 } 419 420 static int stmmac_nway_reset(struct net_device *dev) 421 { 422 struct stmmac_priv *priv = netdev_priv(dev); 423 424 return phylink_ethtool_nway_reset(priv->phylink); 425 } 426 427 static void 428 stmmac_get_pauseparam(struct net_device *netdev, 429 struct ethtool_pauseparam *pause) 430 { 431 struct stmmac_priv *priv = netdev_priv(netdev); 432 struct rgmii_adv adv_lp; 433 434 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 435 pause->autoneg = 1; 436 if (!adv_lp.pause) 437 return; 438 } else { 439 phylink_ethtool_get_pauseparam(priv->phylink, pause); 440 } 441 } 442 443 static int 444 stmmac_set_pauseparam(struct net_device *netdev, 445 struct ethtool_pauseparam *pause) 446 { 447 struct stmmac_priv *priv = netdev_priv(netdev); 448 struct rgmii_adv adv_lp; 449 450 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 451 pause->autoneg = 1; 452 if (!adv_lp.pause) 453 return -EOPNOTSUPP; 454 return 0; 455 } else { 456 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 457 } 458 } 459 460 static void stmmac_get_ethtool_stats(struct net_device *dev, 461 struct ethtool_stats *dummy, u64 *data) 462 { 463 struct stmmac_priv *priv = netdev_priv(dev); 464 u32 rx_queues_count = priv->plat->rx_queues_to_use; 465 u32 tx_queues_count = priv->plat->tx_queues_to_use; 466 unsigned long count; 467 int i, j = 0, ret; 468 469 if (priv->dma_cap.asp) { 470 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 471 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 472 &count, NULL)) 473 data[j++] = count; 474 } 475 } 476 477 /* Update the DMA HW counters for dwmac10/100 */ 478 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 479 priv->ioaddr); 480 if (ret) { 481 /* If supported, for new GMAC chips expose the MMC counters */ 482 if (priv->dma_cap.rmon) { 483 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 484 485 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 486 char *p; 487 p = (char *)priv + stmmac_mmc[i].stat_offset; 488 489 data[j++] = (stmmac_mmc[i].sizeof_stat == 490 sizeof(u64)) ? (*(u64 *)p) : 491 (*(u32 *)p); 492 } 493 } 494 if (priv->eee_enabled) { 495 int val = phylink_get_eee_err(priv->phylink); 496 if (val) 497 priv->xstats.phy_eee_wakeup_error_n = val; 498 } 499 500 if (priv->synopsys_id >= DWMAC_CORE_3_50) 501 stmmac_mac_debug(priv, priv->ioaddr, 502 (void *)&priv->xstats, 503 rx_queues_count, tx_queues_count); 504 } 505 for (i = 0; i < STMMAC_STATS_LEN; i++) { 506 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 507 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 508 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 509 } 510 } 511 512 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 513 { 514 struct stmmac_priv *priv = netdev_priv(netdev); 515 int i, len, safety_len = 0; 516 517 switch (sset) { 518 case ETH_SS_STATS: 519 len = STMMAC_STATS_LEN; 520 521 if (priv->dma_cap.rmon) 522 len += STMMAC_MMC_STATS_LEN; 523 if (priv->dma_cap.asp) { 524 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 525 if (!stmmac_safety_feat_dump(priv, 526 &priv->sstats, i, 527 NULL, NULL)) 528 safety_len++; 529 } 530 531 len += safety_len; 532 } 533 534 return len; 535 case ETH_SS_TEST: 536 return stmmac_selftest_get_count(priv); 537 default: 538 return -EOPNOTSUPP; 539 } 540 } 541 542 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 543 { 544 int i; 545 u8 *p = data; 546 struct stmmac_priv *priv = netdev_priv(dev); 547 548 switch (stringset) { 549 case ETH_SS_STATS: 550 if (priv->dma_cap.asp) { 551 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 552 const char *desc; 553 if (!stmmac_safety_feat_dump(priv, 554 &priv->sstats, i, 555 NULL, &desc)) { 556 memcpy(p, desc, ETH_GSTRING_LEN); 557 p += ETH_GSTRING_LEN; 558 } 559 } 560 } 561 if (priv->dma_cap.rmon) 562 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 563 memcpy(p, stmmac_mmc[i].stat_string, 564 ETH_GSTRING_LEN); 565 p += ETH_GSTRING_LEN; 566 } 567 for (i = 0; i < STMMAC_STATS_LEN; i++) { 568 memcpy(p, stmmac_gstrings_stats[i].stat_string, 569 ETH_GSTRING_LEN); 570 p += ETH_GSTRING_LEN; 571 } 572 break; 573 case ETH_SS_TEST: 574 stmmac_selftest_get_strings(priv, p); 575 break; 576 default: 577 WARN_ON(1); 578 break; 579 } 580 } 581 582 /* Currently only support WOL through Magic packet. */ 583 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 584 { 585 struct stmmac_priv *priv = netdev_priv(dev); 586 587 mutex_lock(&priv->lock); 588 if (device_can_wakeup(priv->device)) { 589 wol->supported = WAKE_MAGIC | WAKE_UCAST; 590 wol->wolopts = priv->wolopts; 591 } 592 mutex_unlock(&priv->lock); 593 } 594 595 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 596 { 597 struct stmmac_priv *priv = netdev_priv(dev); 598 u32 support = WAKE_MAGIC | WAKE_UCAST; 599 600 /* By default almost all GMAC devices support the WoL via 601 * magic frame but we can disable it if the HW capability 602 * register shows no support for pmt_magic_frame. */ 603 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 604 wol->wolopts &= ~WAKE_MAGIC; 605 606 if (!device_can_wakeup(priv->device)) 607 return -EINVAL; 608 609 if (wol->wolopts & ~support) 610 return -EINVAL; 611 612 if (wol->wolopts) { 613 pr_info("stmmac: wakeup enable\n"); 614 device_set_wakeup_enable(priv->device, 1); 615 enable_irq_wake(priv->wol_irq); 616 } else { 617 device_set_wakeup_enable(priv->device, 0); 618 disable_irq_wake(priv->wol_irq); 619 } 620 621 mutex_lock(&priv->lock); 622 priv->wolopts = wol->wolopts; 623 mutex_unlock(&priv->lock); 624 625 return 0; 626 } 627 628 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 629 struct ethtool_eee *edata) 630 { 631 struct stmmac_priv *priv = netdev_priv(dev); 632 633 if (!priv->dma_cap.eee) 634 return -EOPNOTSUPP; 635 636 edata->eee_enabled = priv->eee_enabled; 637 edata->eee_active = priv->eee_active; 638 edata->tx_lpi_timer = priv->tx_lpi_timer; 639 640 return phylink_ethtool_get_eee(priv->phylink, edata); 641 } 642 643 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 644 struct ethtool_eee *edata) 645 { 646 struct stmmac_priv *priv = netdev_priv(dev); 647 int ret; 648 649 if (!edata->eee_enabled) { 650 stmmac_disable_eee_mode(priv); 651 } else { 652 /* We are asking for enabling the EEE but it is safe 653 * to verify all by invoking the eee_init function. 654 * In case of failure it will return an error. 655 */ 656 edata->eee_enabled = stmmac_eee_init(priv); 657 if (!edata->eee_enabled) 658 return -EOPNOTSUPP; 659 } 660 661 ret = phylink_ethtool_set_eee(priv->phylink, edata); 662 if (ret) 663 return ret; 664 665 priv->eee_enabled = edata->eee_enabled; 666 priv->tx_lpi_timer = edata->tx_lpi_timer; 667 return 0; 668 } 669 670 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 671 { 672 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 673 674 if (!clk) { 675 clk = priv->plat->clk_ref_rate; 676 if (!clk) 677 return 0; 678 } 679 680 return (usec * (clk / 1000000)) / 256; 681 } 682 683 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 684 { 685 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 686 687 if (!clk) { 688 clk = priv->plat->clk_ref_rate; 689 if (!clk) 690 return 0; 691 } 692 693 return (riwt * 256) / (clk / 1000000); 694 } 695 696 static int stmmac_get_coalesce(struct net_device *dev, 697 struct ethtool_coalesce *ec) 698 { 699 struct stmmac_priv *priv = netdev_priv(dev); 700 701 ec->tx_coalesce_usecs = priv->tx_coal_timer; 702 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 703 704 if (priv->use_riwt) { 705 ec->rx_max_coalesced_frames = priv->rx_coal_frames; 706 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 707 } 708 709 return 0; 710 } 711 712 static int stmmac_set_coalesce(struct net_device *dev, 713 struct ethtool_coalesce *ec) 714 { 715 struct stmmac_priv *priv = netdev_priv(dev); 716 u32 rx_cnt = priv->plat->rx_queues_to_use; 717 unsigned int rx_riwt; 718 719 /* Check not supported parameters */ 720 if ((ec->rx_coalesce_usecs_irq) || 721 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) || 722 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) || 723 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) || 724 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) || 725 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) || 726 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) || 727 (ec->rx_max_coalesced_frames_high) || 728 (ec->tx_max_coalesced_frames_irq) || 729 (ec->stats_block_coalesce_usecs) || 730 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval)) 731 return -EOPNOTSUPP; 732 733 if (ec->rx_coalesce_usecs == 0) 734 return -EINVAL; 735 736 if ((ec->tx_coalesce_usecs == 0) && 737 (ec->tx_max_coalesced_frames == 0)) 738 return -EINVAL; 739 740 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 741 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 742 return -EINVAL; 743 744 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 745 746 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 747 return -EINVAL; 748 else if (!priv->use_riwt) 749 return -EOPNOTSUPP; 750 751 /* Only copy relevant parameters, ignore all others. */ 752 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 753 priv->tx_coal_timer = ec->tx_coalesce_usecs; 754 priv->rx_coal_frames = ec->rx_max_coalesced_frames; 755 priv->rx_riwt = rx_riwt; 756 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 757 758 return 0; 759 } 760 761 static int stmmac_get_ts_info(struct net_device *dev, 762 struct ethtool_ts_info *info) 763 { 764 struct stmmac_priv *priv = netdev_priv(dev); 765 766 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 767 768 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 769 SOF_TIMESTAMPING_TX_HARDWARE | 770 SOF_TIMESTAMPING_RX_SOFTWARE | 771 SOF_TIMESTAMPING_RX_HARDWARE | 772 SOF_TIMESTAMPING_SOFTWARE | 773 SOF_TIMESTAMPING_RAW_HARDWARE; 774 775 if (priv->ptp_clock) 776 info->phc_index = ptp_clock_index(priv->ptp_clock); 777 778 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 779 780 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 781 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 782 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 783 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 784 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 785 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 786 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 787 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 788 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 789 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 790 (1 << HWTSTAMP_FILTER_ALL)); 791 return 0; 792 } else 793 return ethtool_op_get_ts_info(dev, info); 794 } 795 796 static int stmmac_get_tunable(struct net_device *dev, 797 const struct ethtool_tunable *tuna, void *data) 798 { 799 struct stmmac_priv *priv = netdev_priv(dev); 800 int ret = 0; 801 802 switch (tuna->id) { 803 case ETHTOOL_RX_COPYBREAK: 804 *(u32 *)data = priv->rx_copybreak; 805 break; 806 default: 807 ret = -EINVAL; 808 break; 809 } 810 811 return ret; 812 } 813 814 static int stmmac_set_tunable(struct net_device *dev, 815 const struct ethtool_tunable *tuna, 816 const void *data) 817 { 818 struct stmmac_priv *priv = netdev_priv(dev); 819 int ret = 0; 820 821 switch (tuna->id) { 822 case ETHTOOL_RX_COPYBREAK: 823 priv->rx_copybreak = *(u32 *)data; 824 break; 825 default: 826 ret = -EINVAL; 827 break; 828 } 829 830 return ret; 831 } 832 833 static const struct ethtool_ops stmmac_ethtool_ops = { 834 .begin = stmmac_check_if_running, 835 .get_drvinfo = stmmac_ethtool_getdrvinfo, 836 .get_msglevel = stmmac_ethtool_getmsglevel, 837 .set_msglevel = stmmac_ethtool_setmsglevel, 838 .get_regs = stmmac_ethtool_gregs, 839 .get_regs_len = stmmac_ethtool_get_regs_len, 840 .get_link = ethtool_op_get_link, 841 .nway_reset = stmmac_nway_reset, 842 .get_pauseparam = stmmac_get_pauseparam, 843 .set_pauseparam = stmmac_set_pauseparam, 844 .self_test = stmmac_selftest_run, 845 .get_ethtool_stats = stmmac_get_ethtool_stats, 846 .get_strings = stmmac_get_strings, 847 .get_wol = stmmac_get_wol, 848 .set_wol = stmmac_set_wol, 849 .get_eee = stmmac_ethtool_op_get_eee, 850 .set_eee = stmmac_ethtool_op_set_eee, 851 .get_sset_count = stmmac_get_sset_count, 852 .get_ts_info = stmmac_get_ts_info, 853 .get_coalesce = stmmac_get_coalesce, 854 .set_coalesce = stmmac_set_coalesce, 855 .get_tunable = stmmac_get_tunable, 856 .set_tunable = stmmac_set_tunable, 857 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 858 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 859 }; 860 861 void stmmac_set_ethtool_ops(struct net_device *netdev) 862 { 863 netdev->ethtool_ops = &stmmac_ethtool_ops; 864 } 865