1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3   STMMAC Ethtool support
4 
5   Copyright (C) 2007-2009  STMicroelectronics Ltd
6 
7 
8   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10 
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/mii.h>
15 #include <linux/phylink.h>
16 #include <linux/net_tstamp.h>
17 #include <asm/io.h>
18 
19 #include "stmmac.h"
20 #include "dwmac_dma.h"
21 #include "dwxgmac2.h"
22 
23 #define REG_SPACE_SIZE	0x1060
24 #define GMAC4_REG_SPACE_SIZE	0x116C
25 #define MAC100_ETHTOOL_NAME	"st_mac100"
26 #define GMAC_ETHTOOL_NAME	"st_gmac"
27 #define XGMAC_ETHTOOL_NAME	"st_xgmac"
28 
29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
30  *
31  * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
32  * same time due to the conflicting macro names.
33  */
34 #define GMAC4_DMA_CHAN_BASE_ADDR  0x00001100
35 
36 #define ETHTOOL_DMA_OFFSET	55
37 
38 struct stmmac_stats {
39 	char stat_string[ETH_GSTRING_LEN];
40 	int sizeof_stat;
41 	int stat_offset;
42 };
43 
44 #define STMMAC_STAT(m)	\
45 	{ #m, sizeof_field(struct stmmac_extra_stats, m),	\
46 	offsetof(struct stmmac_priv, xstats.m)}
47 
48 static const struct stmmac_stats stmmac_gstrings_stats[] = {
49 	/* Transmit errors */
50 	STMMAC_STAT(tx_underflow),
51 	STMMAC_STAT(tx_carrier),
52 	STMMAC_STAT(tx_losscarrier),
53 	STMMAC_STAT(vlan_tag),
54 	STMMAC_STAT(tx_deferred),
55 	STMMAC_STAT(tx_vlan),
56 	STMMAC_STAT(tx_jabber),
57 	STMMAC_STAT(tx_frame_flushed),
58 	STMMAC_STAT(tx_payload_error),
59 	STMMAC_STAT(tx_ip_header_error),
60 	/* Receive errors */
61 	STMMAC_STAT(rx_desc),
62 	STMMAC_STAT(sa_filter_fail),
63 	STMMAC_STAT(overflow_error),
64 	STMMAC_STAT(ipc_csum_error),
65 	STMMAC_STAT(rx_collision),
66 	STMMAC_STAT(rx_crc_errors),
67 	STMMAC_STAT(dribbling_bit),
68 	STMMAC_STAT(rx_length),
69 	STMMAC_STAT(rx_mii),
70 	STMMAC_STAT(rx_multicast),
71 	STMMAC_STAT(rx_gmac_overflow),
72 	STMMAC_STAT(rx_watchdog),
73 	STMMAC_STAT(da_rx_filter_fail),
74 	STMMAC_STAT(sa_rx_filter_fail),
75 	STMMAC_STAT(rx_missed_cntr),
76 	STMMAC_STAT(rx_overflow_cntr),
77 	STMMAC_STAT(rx_vlan),
78 	STMMAC_STAT(rx_split_hdr_pkt_n),
79 	/* Tx/Rx IRQ error info */
80 	STMMAC_STAT(tx_undeflow_irq),
81 	STMMAC_STAT(tx_process_stopped_irq),
82 	STMMAC_STAT(tx_jabber_irq),
83 	STMMAC_STAT(rx_overflow_irq),
84 	STMMAC_STAT(rx_buf_unav_irq),
85 	STMMAC_STAT(rx_process_stopped_irq),
86 	STMMAC_STAT(rx_watchdog_irq),
87 	STMMAC_STAT(tx_early_irq),
88 	STMMAC_STAT(fatal_bus_error_irq),
89 	/* Tx/Rx IRQ Events */
90 	STMMAC_STAT(rx_early_irq),
91 	STMMAC_STAT(threshold),
92 	STMMAC_STAT(irq_receive_pmt_irq_n),
93 	/* MMC info */
94 	STMMAC_STAT(mmc_tx_irq_n),
95 	STMMAC_STAT(mmc_rx_irq_n),
96 	STMMAC_STAT(mmc_rx_csum_offload_irq_n),
97 	/* EEE */
98 	STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
99 	STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
100 	STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
101 	STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
102 	STMMAC_STAT(phy_eee_wakeup_error_n),
103 	/* Extended RDES status */
104 	STMMAC_STAT(ip_hdr_err),
105 	STMMAC_STAT(ip_payload_err),
106 	STMMAC_STAT(ip_csum_bypassed),
107 	STMMAC_STAT(ipv4_pkt_rcvd),
108 	STMMAC_STAT(ipv6_pkt_rcvd),
109 	STMMAC_STAT(no_ptp_rx_msg_type_ext),
110 	STMMAC_STAT(ptp_rx_msg_type_sync),
111 	STMMAC_STAT(ptp_rx_msg_type_follow_up),
112 	STMMAC_STAT(ptp_rx_msg_type_delay_req),
113 	STMMAC_STAT(ptp_rx_msg_type_delay_resp),
114 	STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
115 	STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
116 	STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
117 	STMMAC_STAT(ptp_rx_msg_type_announce),
118 	STMMAC_STAT(ptp_rx_msg_type_management),
119 	STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
120 	STMMAC_STAT(ptp_frame_type),
121 	STMMAC_STAT(ptp_ver),
122 	STMMAC_STAT(timestamp_dropped),
123 	STMMAC_STAT(av_pkt_rcvd),
124 	STMMAC_STAT(av_tagged_pkt_rcvd),
125 	STMMAC_STAT(vlan_tag_priority_val),
126 	STMMAC_STAT(l3_filter_match),
127 	STMMAC_STAT(l4_filter_match),
128 	STMMAC_STAT(l3_l4_filter_no_match),
129 	/* PCS */
130 	STMMAC_STAT(irq_pcs_ane_n),
131 	STMMAC_STAT(irq_pcs_link_n),
132 	STMMAC_STAT(irq_rgmii_n),
133 	/* DEBUG */
134 	STMMAC_STAT(mtl_tx_status_fifo_full),
135 	STMMAC_STAT(mtl_tx_fifo_not_empty),
136 	STMMAC_STAT(mmtl_fifo_ctrl),
137 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
138 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
139 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
140 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
141 	STMMAC_STAT(mac_tx_in_pause),
142 	STMMAC_STAT(mac_tx_frame_ctrl_xfer),
143 	STMMAC_STAT(mac_tx_frame_ctrl_idle),
144 	STMMAC_STAT(mac_tx_frame_ctrl_wait),
145 	STMMAC_STAT(mac_tx_frame_ctrl_pause),
146 	STMMAC_STAT(mac_gmii_tx_proto_engine),
147 	STMMAC_STAT(mtl_rx_fifo_fill_level_full),
148 	STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
149 	STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
150 	STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
151 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
152 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
153 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
154 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
155 	STMMAC_STAT(mtl_rx_fifo_ctrl_active),
156 	STMMAC_STAT(mac_rx_frame_ctrl_fifo),
157 	STMMAC_STAT(mac_gmii_rx_proto_engine),
158 	/* EST */
159 	STMMAC_STAT(mtl_est_cgce),
160 	STMMAC_STAT(mtl_est_hlbs),
161 	STMMAC_STAT(mtl_est_hlbf),
162 	STMMAC_STAT(mtl_est_btre),
163 	STMMAC_STAT(mtl_est_btrlm),
164 };
165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
166 
167 /* statistics collected in queue which will be summed up for all TX or RX
168  * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n).
169  */
170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = {
171 	"rx_pkt_n",
172 	"rx_normal_irq_n",
173 	"tx_pkt_n",
174 	"tx_normal_irq_n",
175 	"tx_clean",
176 	"tx_set_ic_bit",
177 	"tx_tso_frames",
178 	"tx_tso_nfrags",
179 	"normal_irq_n",
180 	"napi_poll",
181 };
182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string)
183 
184 /* HW MAC Management counters (if supported) */
185 #define STMMAC_MMC_STAT(m)	\
186 	{ #m, sizeof_field(struct stmmac_counters, m),	\
187 	offsetof(struct stmmac_priv, mmc.m)}
188 
189 static const struct stmmac_stats stmmac_mmc[] = {
190 	STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
191 	STMMAC_MMC_STAT(mmc_tx_framecount_gb),
192 	STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
193 	STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
194 	STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
195 	STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
196 	STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
197 	STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
198 	STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
199 	STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
200 	STMMAC_MMC_STAT(mmc_tx_unicast_gb),
201 	STMMAC_MMC_STAT(mmc_tx_multicast_gb),
202 	STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
203 	STMMAC_MMC_STAT(mmc_tx_underflow_error),
204 	STMMAC_MMC_STAT(mmc_tx_singlecol_g),
205 	STMMAC_MMC_STAT(mmc_tx_multicol_g),
206 	STMMAC_MMC_STAT(mmc_tx_deferred),
207 	STMMAC_MMC_STAT(mmc_tx_latecol),
208 	STMMAC_MMC_STAT(mmc_tx_exesscol),
209 	STMMAC_MMC_STAT(mmc_tx_carrier_error),
210 	STMMAC_MMC_STAT(mmc_tx_octetcount_g),
211 	STMMAC_MMC_STAT(mmc_tx_framecount_g),
212 	STMMAC_MMC_STAT(mmc_tx_excessdef),
213 	STMMAC_MMC_STAT(mmc_tx_pause_frame),
214 	STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
215 	STMMAC_MMC_STAT(mmc_rx_framecount_gb),
216 	STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
217 	STMMAC_MMC_STAT(mmc_rx_octetcount_g),
218 	STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
219 	STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
220 	STMMAC_MMC_STAT(mmc_rx_crc_error),
221 	STMMAC_MMC_STAT(mmc_rx_align_error),
222 	STMMAC_MMC_STAT(mmc_rx_run_error),
223 	STMMAC_MMC_STAT(mmc_rx_jabber_error),
224 	STMMAC_MMC_STAT(mmc_rx_undersize_g),
225 	STMMAC_MMC_STAT(mmc_rx_oversize_g),
226 	STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
227 	STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
228 	STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
229 	STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
230 	STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
231 	STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
232 	STMMAC_MMC_STAT(mmc_rx_unicast_g),
233 	STMMAC_MMC_STAT(mmc_rx_length_error),
234 	STMMAC_MMC_STAT(mmc_rx_autofrangetype),
235 	STMMAC_MMC_STAT(mmc_rx_pause_frames),
236 	STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
237 	STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
238 	STMMAC_MMC_STAT(mmc_rx_watchdog_error),
239 	STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
240 	STMMAC_MMC_STAT(mmc_rx_ipc_intr),
241 	STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
242 	STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
243 	STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
244 	STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
245 	STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
246 	STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
247 	STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
248 	STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
249 	STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
250 	STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
251 	STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
252 	STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
253 	STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
254 	STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
255 	STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
256 	STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
257 	STMMAC_MMC_STAT(mmc_rx_udp_gd),
258 	STMMAC_MMC_STAT(mmc_rx_udp_err),
259 	STMMAC_MMC_STAT(mmc_rx_tcp_gd),
260 	STMMAC_MMC_STAT(mmc_rx_tcp_err),
261 	STMMAC_MMC_STAT(mmc_rx_icmp_gd),
262 	STMMAC_MMC_STAT(mmc_rx_icmp_err),
263 	STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
264 	STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
265 	STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
266 	STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
267 	STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
268 	STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
269 	STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
270 	STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
271 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
272 	STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
273 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
274 	STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
275 };
276 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
277 
278 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = {
279 	"tx_pkt_n",
280 	"tx_irq_n",
281 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string)
282 };
283 
284 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = {
285 	"rx_pkt_n",
286 	"rx_irq_n",
287 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string)
288 };
289 
290 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
291 				      struct ethtool_drvinfo *info)
292 {
293 	struct stmmac_priv *priv = netdev_priv(dev);
294 
295 	if (priv->plat->has_gmac || priv->plat->has_gmac4)
296 		strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
297 	else if (priv->plat->has_xgmac)
298 		strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
299 	else
300 		strscpy(info->driver, MAC100_ETHTOOL_NAME,
301 			sizeof(info->driver));
302 
303 	if (priv->plat->pdev) {
304 		strscpy(info->bus_info, pci_name(priv->plat->pdev),
305 			sizeof(info->bus_info));
306 	}
307 }
308 
309 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
310 					     struct ethtool_link_ksettings *cmd)
311 {
312 	struct stmmac_priv *priv = netdev_priv(dev);
313 
314 	if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) &&
315 	    (priv->hw->pcs & STMMAC_PCS_RGMII ||
316 	     priv->hw->pcs & STMMAC_PCS_SGMII)) {
317 		struct rgmii_adv adv;
318 		u32 supported, advertising, lp_advertising;
319 
320 		if (!priv->xstats.pcs_link) {
321 			cmd->base.speed = SPEED_UNKNOWN;
322 			cmd->base.duplex = DUPLEX_UNKNOWN;
323 			return 0;
324 		}
325 		cmd->base.duplex = priv->xstats.pcs_duplex;
326 
327 		cmd->base.speed = priv->xstats.pcs_speed;
328 
329 		/* Get and convert ADV/LP_ADV from the HW AN registers */
330 		if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
331 			return -EOPNOTSUPP;	/* should never happen indeed */
332 
333 		/* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
334 
335 		ethtool_convert_link_mode_to_legacy_u32(
336 			&supported, cmd->link_modes.supported);
337 		ethtool_convert_link_mode_to_legacy_u32(
338 			&advertising, cmd->link_modes.advertising);
339 		ethtool_convert_link_mode_to_legacy_u32(
340 			&lp_advertising, cmd->link_modes.lp_advertising);
341 
342 		if (adv.pause & STMMAC_PCS_PAUSE)
343 			advertising |= ADVERTISED_Pause;
344 		if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
345 			advertising |= ADVERTISED_Asym_Pause;
346 		if (adv.lp_pause & STMMAC_PCS_PAUSE)
347 			lp_advertising |= ADVERTISED_Pause;
348 		if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
349 			lp_advertising |= ADVERTISED_Asym_Pause;
350 
351 		/* Reg49[3] always set because ANE is always supported */
352 		cmd->base.autoneg = ADVERTISED_Autoneg;
353 		supported |= SUPPORTED_Autoneg;
354 		advertising |= ADVERTISED_Autoneg;
355 		lp_advertising |= ADVERTISED_Autoneg;
356 
357 		if (adv.duplex) {
358 			supported |= (SUPPORTED_1000baseT_Full |
359 				      SUPPORTED_100baseT_Full |
360 				      SUPPORTED_10baseT_Full);
361 			advertising |= (ADVERTISED_1000baseT_Full |
362 					ADVERTISED_100baseT_Full |
363 					ADVERTISED_10baseT_Full);
364 		} else {
365 			supported |= (SUPPORTED_1000baseT_Half |
366 				      SUPPORTED_100baseT_Half |
367 				      SUPPORTED_10baseT_Half);
368 			advertising |= (ADVERTISED_1000baseT_Half |
369 					ADVERTISED_100baseT_Half |
370 					ADVERTISED_10baseT_Half);
371 		}
372 		if (adv.lp_duplex)
373 			lp_advertising |= (ADVERTISED_1000baseT_Full |
374 					   ADVERTISED_100baseT_Full |
375 					   ADVERTISED_10baseT_Full);
376 		else
377 			lp_advertising |= (ADVERTISED_1000baseT_Half |
378 					   ADVERTISED_100baseT_Half |
379 					   ADVERTISED_10baseT_Half);
380 		cmd->base.port = PORT_OTHER;
381 
382 		ethtool_convert_legacy_u32_to_link_mode(
383 			cmd->link_modes.supported, supported);
384 		ethtool_convert_legacy_u32_to_link_mode(
385 			cmd->link_modes.advertising, advertising);
386 		ethtool_convert_legacy_u32_to_link_mode(
387 			cmd->link_modes.lp_advertising, lp_advertising);
388 
389 		return 0;
390 	}
391 
392 	return phylink_ethtool_ksettings_get(priv->phylink, cmd);
393 }
394 
395 static int
396 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
397 				  const struct ethtool_link_ksettings *cmd)
398 {
399 	struct stmmac_priv *priv = netdev_priv(dev);
400 
401 	if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) &&
402 	    (priv->hw->pcs & STMMAC_PCS_RGMII ||
403 	     priv->hw->pcs & STMMAC_PCS_SGMII)) {
404 		/* Only support ANE */
405 		if (cmd->base.autoneg != AUTONEG_ENABLE)
406 			return -EINVAL;
407 
408 		mutex_lock(&priv->lock);
409 		stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
410 		mutex_unlock(&priv->lock);
411 
412 		return 0;
413 	}
414 
415 	return phylink_ethtool_ksettings_set(priv->phylink, cmd);
416 }
417 
418 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
419 {
420 	struct stmmac_priv *priv = netdev_priv(dev);
421 	return priv->msg_enable;
422 }
423 
424 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
425 {
426 	struct stmmac_priv *priv = netdev_priv(dev);
427 	priv->msg_enable = level;
428 
429 }
430 
431 static int stmmac_check_if_running(struct net_device *dev)
432 {
433 	if (!netif_running(dev))
434 		return -EBUSY;
435 	return 0;
436 }
437 
438 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
439 {
440 	struct stmmac_priv *priv = netdev_priv(dev);
441 
442 	if (priv->plat->has_xgmac)
443 		return XGMAC_REGSIZE * 4;
444 	else if (priv->plat->has_gmac4)
445 		return GMAC4_REG_SPACE_SIZE;
446 	return REG_SPACE_SIZE;
447 }
448 
449 static void stmmac_ethtool_gregs(struct net_device *dev,
450 			  struct ethtool_regs *regs, void *space)
451 {
452 	struct stmmac_priv *priv = netdev_priv(dev);
453 	u32 *reg_space = (u32 *) space;
454 
455 	stmmac_dump_mac_regs(priv, priv->hw, reg_space);
456 	stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
457 
458 	/* Copy DMA registers to where ethtool expects them */
459 	if (priv->plat->has_gmac4) {
460 		/* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
461 		memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
462 		       &reg_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
463 		       NUM_DWMAC4_DMA_REGS * 4);
464 	} else if (!priv->plat->has_xgmac) {
465 		memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
466 		       &reg_space[DMA_BUS_MODE / 4],
467 		       NUM_DWMAC1000_DMA_REGS * 4);
468 	}
469 }
470 
471 static int stmmac_nway_reset(struct net_device *dev)
472 {
473 	struct stmmac_priv *priv = netdev_priv(dev);
474 
475 	return phylink_ethtool_nway_reset(priv->phylink);
476 }
477 
478 static void stmmac_get_ringparam(struct net_device *netdev,
479 				 struct ethtool_ringparam *ring,
480 				 struct kernel_ethtool_ringparam *kernel_ring,
481 				 struct netlink_ext_ack *extack)
482 {
483 	struct stmmac_priv *priv = netdev_priv(netdev);
484 
485 	ring->rx_max_pending = DMA_MAX_RX_SIZE;
486 	ring->tx_max_pending = DMA_MAX_TX_SIZE;
487 	ring->rx_pending = priv->dma_conf.dma_rx_size;
488 	ring->tx_pending = priv->dma_conf.dma_tx_size;
489 }
490 
491 static int stmmac_set_ringparam(struct net_device *netdev,
492 				struct ethtool_ringparam *ring,
493 				struct kernel_ethtool_ringparam *kernel_ring,
494 				struct netlink_ext_ack *extack)
495 {
496 	if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
497 	    ring->rx_pending < DMA_MIN_RX_SIZE ||
498 	    ring->rx_pending > DMA_MAX_RX_SIZE ||
499 	    !is_power_of_2(ring->rx_pending) ||
500 	    ring->tx_pending < DMA_MIN_TX_SIZE ||
501 	    ring->tx_pending > DMA_MAX_TX_SIZE ||
502 	    !is_power_of_2(ring->tx_pending))
503 		return -EINVAL;
504 
505 	return stmmac_reinit_ringparam(netdev, ring->rx_pending,
506 				       ring->tx_pending);
507 }
508 
509 static void
510 stmmac_get_pauseparam(struct net_device *netdev,
511 		      struct ethtool_pauseparam *pause)
512 {
513 	struct stmmac_priv *priv = netdev_priv(netdev);
514 	struct rgmii_adv adv_lp;
515 
516 	if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
517 		pause->autoneg = 1;
518 		if (!adv_lp.pause)
519 			return;
520 	} else {
521 		phylink_ethtool_get_pauseparam(priv->phylink, pause);
522 	}
523 }
524 
525 static int
526 stmmac_set_pauseparam(struct net_device *netdev,
527 		      struct ethtool_pauseparam *pause)
528 {
529 	struct stmmac_priv *priv = netdev_priv(netdev);
530 	struct rgmii_adv adv_lp;
531 
532 	if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
533 		pause->autoneg = 1;
534 		if (!adv_lp.pause)
535 			return -EOPNOTSUPP;
536 		return 0;
537 	} else {
538 		return phylink_ethtool_set_pauseparam(priv->phylink, pause);
539 	}
540 }
541 
542 static u64 stmmac_get_rx_normal_irq_n(struct stmmac_priv *priv, int q)
543 {
544 	u64 total;
545 	int cpu;
546 
547 	total = 0;
548 	for_each_possible_cpu(cpu) {
549 		struct stmmac_pcpu_stats *pcpu;
550 		unsigned int start;
551 		u64 irq_n;
552 
553 		pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu);
554 		do {
555 			start = u64_stats_fetch_begin(&pcpu->syncp);
556 			irq_n = u64_stats_read(&pcpu->rx_normal_irq_n[q]);
557 		} while (u64_stats_fetch_retry(&pcpu->syncp, start));
558 		total += irq_n;
559 	}
560 	return total;
561 }
562 
563 static u64 stmmac_get_tx_normal_irq_n(struct stmmac_priv *priv, int q)
564 {
565 	u64 total;
566 	int cpu;
567 
568 	total = 0;
569 	for_each_possible_cpu(cpu) {
570 		struct stmmac_pcpu_stats *pcpu;
571 		unsigned int start;
572 		u64 irq_n;
573 
574 		pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu);
575 		do {
576 			start = u64_stats_fetch_begin(&pcpu->syncp);
577 			irq_n = u64_stats_read(&pcpu->tx_normal_irq_n[q]);
578 		} while (u64_stats_fetch_retry(&pcpu->syncp, start));
579 		total += irq_n;
580 	}
581 	return total;
582 }
583 
584 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)
585 {
586 	u32 tx_cnt = priv->plat->tx_queues_to_use;
587 	u32 rx_cnt = priv->plat->rx_queues_to_use;
588 	unsigned int start;
589 	int q;
590 
591 	for (q = 0; q < tx_cnt; q++) {
592 		struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
593 		u64 pkt_n;
594 
595 		do {
596 			start = u64_stats_fetch_begin(&txq_stats->napi_syncp);
597 			pkt_n = u64_stats_read(&txq_stats->napi.tx_pkt_n);
598 		} while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start));
599 
600 		*data++ = pkt_n;
601 		*data++ = stmmac_get_tx_normal_irq_n(priv, q);
602 	}
603 
604 	for (q = 0; q < rx_cnt; q++) {
605 		struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q];
606 		u64 pkt_n;
607 
608 		do {
609 			start = u64_stats_fetch_begin(&rxq_stats->napi_syncp);
610 			pkt_n = u64_stats_read(&rxq_stats->napi.rx_pkt_n);
611 		} while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start));
612 
613 		*data++ = pkt_n;
614 		*data++ = stmmac_get_rx_normal_irq_n(priv, q);
615 	}
616 }
617 
618 static void stmmac_get_ethtool_stats(struct net_device *dev,
619 				 struct ethtool_stats *dummy, u64 *data)
620 {
621 	struct stmmac_priv *priv = netdev_priv(dev);
622 	u32 rx_queues_count = priv->plat->rx_queues_to_use;
623 	u32 tx_queues_count = priv->plat->tx_queues_to_use;
624 	u64 napi_poll = 0, normal_irq_n = 0;
625 	int i, j = 0, pos, ret;
626 	unsigned long count;
627 	unsigned int start;
628 
629 	if (priv->dma_cap.asp) {
630 		for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
631 			if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
632 						&count, NULL))
633 				data[j++] = count;
634 		}
635 	}
636 
637 	/* Update the DMA HW counters for dwmac10/100 */
638 	ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr);
639 	if (ret) {
640 		/* If supported, for new GMAC chips expose the MMC counters */
641 		if (priv->dma_cap.rmon) {
642 			stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
643 
644 			for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
645 				char *p;
646 				p = (char *)priv + stmmac_mmc[i].stat_offset;
647 
648 				data[j++] = (stmmac_mmc[i].sizeof_stat ==
649 					     sizeof(u64)) ? (*(u64 *)p) :
650 					     (*(u32 *)p);
651 			}
652 		}
653 		if (priv->eee_enabled) {
654 			int val = phylink_get_eee_err(priv->phylink);
655 			if (val)
656 				priv->xstats.phy_eee_wakeup_error_n = val;
657 		}
658 
659 		if (priv->synopsys_id >= DWMAC_CORE_3_50)
660 			stmmac_mac_debug(priv, priv->ioaddr,
661 					(void *)&priv->xstats,
662 					rx_queues_count, tx_queues_count);
663 	}
664 	for (i = 0; i < STMMAC_STATS_LEN; i++) {
665 		char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
666 		data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
667 			     sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
668 	}
669 
670 	pos = j;
671 	for (i = 0; i < rx_queues_count; i++) {
672 		struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i];
673 		struct stmmac_napi_rx_stats snapshot;
674 		u64 n_irq;
675 
676 		j = pos;
677 		do {
678 			start = u64_stats_fetch_begin(&rxq_stats->napi_syncp);
679 			snapshot = rxq_stats->napi;
680 		} while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start));
681 
682 		data[j++] += u64_stats_read(&snapshot.rx_pkt_n);
683 		n_irq = stmmac_get_rx_normal_irq_n(priv, i);
684 		data[j++] += n_irq;
685 		normal_irq_n += n_irq;
686 		napi_poll += u64_stats_read(&snapshot.poll);
687 	}
688 
689 	pos = j;
690 	for (i = 0; i < tx_queues_count; i++) {
691 		struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i];
692 		struct stmmac_napi_tx_stats napi_snapshot;
693 		struct stmmac_q_tx_stats q_snapshot;
694 		u64 n_irq;
695 
696 		j = pos;
697 		do {
698 			start = u64_stats_fetch_begin(&txq_stats->q_syncp);
699 			q_snapshot = txq_stats->q;
700 		} while (u64_stats_fetch_retry(&txq_stats->q_syncp, start));
701 		do {
702 			start = u64_stats_fetch_begin(&txq_stats->napi_syncp);
703 			napi_snapshot = txq_stats->napi;
704 		} while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start));
705 
706 		data[j++] += u64_stats_read(&napi_snapshot.tx_pkt_n);
707 		n_irq = stmmac_get_tx_normal_irq_n(priv, i);
708 		data[j++] += n_irq;
709 		normal_irq_n += n_irq;
710 		data[j++] += u64_stats_read(&napi_snapshot.tx_clean);
711 		data[j++] += u64_stats_read(&q_snapshot.tx_set_ic_bit) +
712 			u64_stats_read(&napi_snapshot.tx_set_ic_bit);
713 		data[j++] += u64_stats_read(&q_snapshot.tx_tso_frames);
714 		data[j++] += u64_stats_read(&q_snapshot.tx_tso_nfrags);
715 		napi_poll += u64_stats_read(&napi_snapshot.poll);
716 	}
717 	normal_irq_n += priv->xstats.rx_early_irq;
718 	data[j++] = normal_irq_n;
719 	data[j++] = napi_poll;
720 
721 	stmmac_get_per_qstats(priv, &data[j]);
722 }
723 
724 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
725 {
726 	struct stmmac_priv *priv = netdev_priv(netdev);
727 	u32 tx_cnt = priv->plat->tx_queues_to_use;
728 	u32 rx_cnt = priv->plat->rx_queues_to_use;
729 	int i, len, safety_len = 0;
730 
731 	switch (sset) {
732 	case ETH_SS_STATS:
733 		len = STMMAC_STATS_LEN + STMMAC_QSTATS +
734 		      STMMAC_TXQ_STATS * tx_cnt +
735 		      STMMAC_RXQ_STATS * rx_cnt;
736 
737 		if (priv->dma_cap.rmon)
738 			len += STMMAC_MMC_STATS_LEN;
739 		if (priv->dma_cap.asp) {
740 			for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
741 				if (!stmmac_safety_feat_dump(priv,
742 							&priv->sstats, i,
743 							NULL, NULL))
744 					safety_len++;
745 			}
746 
747 			len += safety_len;
748 		}
749 
750 		return len;
751 	case ETH_SS_TEST:
752 		return stmmac_selftest_get_count(priv);
753 	default:
754 		return -EOPNOTSUPP;
755 	}
756 }
757 
758 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data)
759 {
760 	u32 tx_cnt = priv->plat->tx_queues_to_use;
761 	u32 rx_cnt = priv->plat->rx_queues_to_use;
762 	int q, stat;
763 
764 	for (q = 0; q < tx_cnt; q++) {
765 		for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
766 			snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
767 				 stmmac_qstats_tx_string[stat]);
768 			data += ETH_GSTRING_LEN;
769 		}
770 	}
771 	for (q = 0; q < rx_cnt; q++) {
772 		for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
773 			snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
774 				 stmmac_qstats_rx_string[stat]);
775 			data += ETH_GSTRING_LEN;
776 		}
777 	}
778 }
779 
780 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
781 {
782 	int i;
783 	u8 *p = data;
784 	struct stmmac_priv *priv = netdev_priv(dev);
785 
786 	switch (stringset) {
787 	case ETH_SS_STATS:
788 		if (priv->dma_cap.asp) {
789 			for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
790 				const char *desc;
791 				if (!stmmac_safety_feat_dump(priv,
792 							&priv->sstats, i,
793 							NULL, &desc)) {
794 					memcpy(p, desc, ETH_GSTRING_LEN);
795 					p += ETH_GSTRING_LEN;
796 				}
797 			}
798 		}
799 		if (priv->dma_cap.rmon)
800 			for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
801 				memcpy(p, stmmac_mmc[i].stat_string,
802 				       ETH_GSTRING_LEN);
803 				p += ETH_GSTRING_LEN;
804 			}
805 		for (i = 0; i < STMMAC_STATS_LEN; i++) {
806 			memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN);
807 			p += ETH_GSTRING_LEN;
808 		}
809 		for (i = 0; i < STMMAC_QSTATS; i++) {
810 			memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN);
811 			p += ETH_GSTRING_LEN;
812 		}
813 		stmmac_get_qstats_string(priv, p);
814 		break;
815 	case ETH_SS_TEST:
816 		stmmac_selftest_get_strings(priv, p);
817 		break;
818 	default:
819 		WARN_ON(1);
820 		break;
821 	}
822 }
823 
824 /* Currently only support WOL through Magic packet. */
825 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
826 {
827 	struct stmmac_priv *priv = netdev_priv(dev);
828 
829 	if (!priv->plat->pmt)
830 		return phylink_ethtool_get_wol(priv->phylink, wol);
831 
832 	mutex_lock(&priv->lock);
833 	if (device_can_wakeup(priv->device)) {
834 		wol->supported = WAKE_MAGIC | WAKE_UCAST;
835 		if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame)
836 			wol->supported &= ~WAKE_MAGIC;
837 		wol->wolopts = priv->wolopts;
838 	}
839 	mutex_unlock(&priv->lock);
840 }
841 
842 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
843 {
844 	struct stmmac_priv *priv = netdev_priv(dev);
845 	u32 support = WAKE_MAGIC | WAKE_UCAST;
846 
847 	if (!device_can_wakeup(priv->device))
848 		return -EOPNOTSUPP;
849 
850 	if (!priv->plat->pmt) {
851 		int ret = phylink_ethtool_set_wol(priv->phylink, wol);
852 
853 		if (!ret)
854 			device_set_wakeup_enable(priv->device, !!wol->wolopts);
855 		return ret;
856 	}
857 
858 	/* By default almost all GMAC devices support the WoL via
859 	 * magic frame but we can disable it if the HW capability
860 	 * register shows no support for pmt_magic_frame. */
861 	if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
862 		wol->wolopts &= ~WAKE_MAGIC;
863 
864 	if (wol->wolopts & ~support)
865 		return -EINVAL;
866 
867 	if (wol->wolopts) {
868 		pr_info("stmmac: wakeup enable\n");
869 		device_set_wakeup_enable(priv->device, 1);
870 		/* Avoid unbalanced enable_irq_wake calls */
871 		if (priv->wol_irq_disabled)
872 			enable_irq_wake(priv->wol_irq);
873 		priv->wol_irq_disabled = false;
874 	} else {
875 		device_set_wakeup_enable(priv->device, 0);
876 		/* Avoid unbalanced disable_irq_wake calls */
877 		if (!priv->wol_irq_disabled)
878 			disable_irq_wake(priv->wol_irq);
879 		priv->wol_irq_disabled = true;
880 	}
881 
882 	mutex_lock(&priv->lock);
883 	priv->wolopts = wol->wolopts;
884 	mutex_unlock(&priv->lock);
885 
886 	return 0;
887 }
888 
889 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
890 				     struct ethtool_eee *edata)
891 {
892 	struct stmmac_priv *priv = netdev_priv(dev);
893 
894 	if (!priv->dma_cap.eee)
895 		return -EOPNOTSUPP;
896 
897 	edata->eee_enabled = priv->eee_enabled;
898 	edata->eee_active = priv->eee_active;
899 	edata->tx_lpi_timer = priv->tx_lpi_timer;
900 	edata->tx_lpi_enabled = priv->tx_lpi_enabled;
901 
902 	return phylink_ethtool_get_eee(priv->phylink, edata);
903 }
904 
905 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
906 				     struct ethtool_eee *edata)
907 {
908 	struct stmmac_priv *priv = netdev_priv(dev);
909 	int ret;
910 
911 	if (!priv->dma_cap.eee)
912 		return -EOPNOTSUPP;
913 
914 	if (priv->tx_lpi_enabled != edata->tx_lpi_enabled)
915 		netdev_warn(priv->dev,
916 			    "Setting EEE tx-lpi is not supported\n");
917 
918 	if (!edata->eee_enabled)
919 		stmmac_disable_eee_mode(priv);
920 
921 	ret = phylink_ethtool_set_eee(priv->phylink, edata);
922 	if (ret)
923 		return ret;
924 
925 	if (edata->eee_enabled &&
926 	    priv->tx_lpi_timer != edata->tx_lpi_timer) {
927 		priv->tx_lpi_timer = edata->tx_lpi_timer;
928 		stmmac_eee_init(priv);
929 	}
930 
931 	return 0;
932 }
933 
934 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
935 {
936 	unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
937 
938 	if (!clk) {
939 		clk = priv->plat->clk_ref_rate;
940 		if (!clk)
941 			return 0;
942 	}
943 
944 	return (usec * (clk / 1000000)) / 256;
945 }
946 
947 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
948 {
949 	unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
950 
951 	if (!clk) {
952 		clk = priv->plat->clk_ref_rate;
953 		if (!clk)
954 			return 0;
955 	}
956 
957 	return (riwt * 256) / (clk / 1000000);
958 }
959 
960 static int __stmmac_get_coalesce(struct net_device *dev,
961 				 struct ethtool_coalesce *ec,
962 				 int queue)
963 {
964 	struct stmmac_priv *priv = netdev_priv(dev);
965 	u32 max_cnt;
966 	u32 rx_cnt;
967 	u32 tx_cnt;
968 
969 	rx_cnt = priv->plat->rx_queues_to_use;
970 	tx_cnt = priv->plat->tx_queues_to_use;
971 	max_cnt = max(rx_cnt, tx_cnt);
972 
973 	if (queue < 0)
974 		queue = 0;
975 	else if (queue >= max_cnt)
976 		return -EINVAL;
977 
978 	if (queue < tx_cnt) {
979 		ec->tx_coalesce_usecs = priv->tx_coal_timer[queue];
980 		ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue];
981 	} else {
982 		ec->tx_coalesce_usecs = 0;
983 		ec->tx_max_coalesced_frames = 0;
984 	}
985 
986 	if (priv->use_riwt && queue < rx_cnt) {
987 		ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue];
988 		ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue],
989 							 priv);
990 	} else {
991 		ec->rx_max_coalesced_frames = 0;
992 		ec->rx_coalesce_usecs = 0;
993 	}
994 
995 	return 0;
996 }
997 
998 static int stmmac_get_coalesce(struct net_device *dev,
999 			       struct ethtool_coalesce *ec,
1000 			       struct kernel_ethtool_coalesce *kernel_coal,
1001 			       struct netlink_ext_ack *extack)
1002 {
1003 	return __stmmac_get_coalesce(dev, ec, -1);
1004 }
1005 
1006 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue,
1007 					 struct ethtool_coalesce *ec)
1008 {
1009 	return __stmmac_get_coalesce(dev, ec, queue);
1010 }
1011 
1012 static int __stmmac_set_coalesce(struct net_device *dev,
1013 				 struct ethtool_coalesce *ec,
1014 				 int queue)
1015 {
1016 	struct stmmac_priv *priv = netdev_priv(dev);
1017 	bool all_queues = false;
1018 	unsigned int rx_riwt;
1019 	u32 max_cnt;
1020 	u32 rx_cnt;
1021 	u32 tx_cnt;
1022 
1023 	rx_cnt = priv->plat->rx_queues_to_use;
1024 	tx_cnt = priv->plat->tx_queues_to_use;
1025 	max_cnt = max(rx_cnt, tx_cnt);
1026 
1027 	if (queue < 0)
1028 		all_queues = true;
1029 	else if (queue >= max_cnt)
1030 		return -EINVAL;
1031 
1032 	if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) {
1033 		rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
1034 
1035 		if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
1036 			return -EINVAL;
1037 
1038 		if (all_queues) {
1039 			int i;
1040 
1041 			for (i = 0; i < rx_cnt; i++) {
1042 				priv->rx_riwt[i] = rx_riwt;
1043 				stmmac_rx_watchdog(priv, priv->ioaddr,
1044 						   rx_riwt, i);
1045 				priv->rx_coal_frames[i] =
1046 					ec->rx_max_coalesced_frames;
1047 			}
1048 		} else if (queue < rx_cnt) {
1049 			priv->rx_riwt[queue] = rx_riwt;
1050 			stmmac_rx_watchdog(priv, priv->ioaddr,
1051 					   rx_riwt, queue);
1052 			priv->rx_coal_frames[queue] =
1053 				ec->rx_max_coalesced_frames;
1054 		}
1055 	}
1056 
1057 	if ((ec->tx_coalesce_usecs == 0) &&
1058 	    (ec->tx_max_coalesced_frames == 0))
1059 		return -EINVAL;
1060 
1061 	if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
1062 	    (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
1063 		return -EINVAL;
1064 
1065 	if (all_queues) {
1066 		int i;
1067 
1068 		for (i = 0; i < tx_cnt; i++) {
1069 			priv->tx_coal_frames[i] =
1070 				ec->tx_max_coalesced_frames;
1071 			priv->tx_coal_timer[i] =
1072 				ec->tx_coalesce_usecs;
1073 		}
1074 	} else if (queue < tx_cnt) {
1075 		priv->tx_coal_frames[queue] =
1076 			ec->tx_max_coalesced_frames;
1077 		priv->tx_coal_timer[queue] =
1078 			ec->tx_coalesce_usecs;
1079 	}
1080 
1081 	return 0;
1082 }
1083 
1084 static int stmmac_set_coalesce(struct net_device *dev,
1085 			       struct ethtool_coalesce *ec,
1086 			       struct kernel_ethtool_coalesce *kernel_coal,
1087 			       struct netlink_ext_ack *extack)
1088 {
1089 	return __stmmac_set_coalesce(dev, ec, -1);
1090 }
1091 
1092 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue,
1093 					 struct ethtool_coalesce *ec)
1094 {
1095 	return __stmmac_set_coalesce(dev, ec, queue);
1096 }
1097 
1098 static int stmmac_get_rxnfc(struct net_device *dev,
1099 			    struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1100 {
1101 	struct stmmac_priv *priv = netdev_priv(dev);
1102 
1103 	switch (rxnfc->cmd) {
1104 	case ETHTOOL_GRXRINGS:
1105 		rxnfc->data = priv->plat->rx_queues_to_use;
1106 		break;
1107 	default:
1108 		return -EOPNOTSUPP;
1109 	}
1110 
1111 	return 0;
1112 }
1113 
1114 static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
1115 {
1116 	struct stmmac_priv *priv = netdev_priv(dev);
1117 
1118 	return sizeof(priv->rss.key);
1119 }
1120 
1121 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
1122 {
1123 	struct stmmac_priv *priv = netdev_priv(dev);
1124 
1125 	return ARRAY_SIZE(priv->rss.table);
1126 }
1127 
1128 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1129 			   u8 *hfunc)
1130 {
1131 	struct stmmac_priv *priv = netdev_priv(dev);
1132 	int i;
1133 
1134 	if (indir) {
1135 		for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1136 			indir[i] = priv->rss.table[i];
1137 	}
1138 
1139 	if (key)
1140 		memcpy(key, priv->rss.key, sizeof(priv->rss.key));
1141 	if (hfunc)
1142 		*hfunc = ETH_RSS_HASH_TOP;
1143 
1144 	return 0;
1145 }
1146 
1147 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,
1148 			   const u8 *key, const u8 hfunc)
1149 {
1150 	struct stmmac_priv *priv = netdev_priv(dev);
1151 	int i;
1152 
1153 	if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP))
1154 		return -EOPNOTSUPP;
1155 
1156 	if (indir) {
1157 		for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1158 			priv->rss.table[i] = indir[i];
1159 	}
1160 
1161 	if (key)
1162 		memcpy(priv->rss.key, key, sizeof(priv->rss.key));
1163 
1164 	return stmmac_rss_configure(priv, priv->hw, &priv->rss,
1165 				    priv->plat->rx_queues_to_use);
1166 }
1167 
1168 static void stmmac_get_channels(struct net_device *dev,
1169 				struct ethtool_channels *chan)
1170 {
1171 	struct stmmac_priv *priv = netdev_priv(dev);
1172 
1173 	chan->rx_count = priv->plat->rx_queues_to_use;
1174 	chan->tx_count = priv->plat->tx_queues_to_use;
1175 	chan->max_rx = priv->dma_cap.number_rx_queues;
1176 	chan->max_tx = priv->dma_cap.number_tx_queues;
1177 }
1178 
1179 static int stmmac_set_channels(struct net_device *dev,
1180 			       struct ethtool_channels *chan)
1181 {
1182 	struct stmmac_priv *priv = netdev_priv(dev);
1183 
1184 	if (chan->rx_count > priv->dma_cap.number_rx_queues ||
1185 	    chan->tx_count > priv->dma_cap.number_tx_queues ||
1186 	    !chan->rx_count || !chan->tx_count)
1187 		return -EINVAL;
1188 
1189 	return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
1190 }
1191 
1192 static int stmmac_get_ts_info(struct net_device *dev,
1193 			      struct ethtool_ts_info *info)
1194 {
1195 	struct stmmac_priv *priv = netdev_priv(dev);
1196 
1197 	if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
1198 
1199 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1200 					SOF_TIMESTAMPING_TX_HARDWARE |
1201 					SOF_TIMESTAMPING_RX_SOFTWARE |
1202 					SOF_TIMESTAMPING_RX_HARDWARE |
1203 					SOF_TIMESTAMPING_SOFTWARE |
1204 					SOF_TIMESTAMPING_RAW_HARDWARE;
1205 
1206 		if (priv->ptp_clock)
1207 			info->phc_index = ptp_clock_index(priv->ptp_clock);
1208 
1209 		info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1210 
1211 		info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
1212 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1213 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1214 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1215 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1216 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1217 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1218 				    (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1219 				    (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1220 				    (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
1221 				    (1 << HWTSTAMP_FILTER_ALL));
1222 		return 0;
1223 	} else
1224 		return ethtool_op_get_ts_info(dev, info);
1225 }
1226 
1227 static int stmmac_get_tunable(struct net_device *dev,
1228 			      const struct ethtool_tunable *tuna, void *data)
1229 {
1230 	struct stmmac_priv *priv = netdev_priv(dev);
1231 	int ret = 0;
1232 
1233 	switch (tuna->id) {
1234 	case ETHTOOL_RX_COPYBREAK:
1235 		*(u32 *)data = priv->rx_copybreak;
1236 		break;
1237 	default:
1238 		ret = -EINVAL;
1239 		break;
1240 	}
1241 
1242 	return ret;
1243 }
1244 
1245 static int stmmac_set_tunable(struct net_device *dev,
1246 			      const struct ethtool_tunable *tuna,
1247 			      const void *data)
1248 {
1249 	struct stmmac_priv *priv = netdev_priv(dev);
1250 	int ret = 0;
1251 
1252 	switch (tuna->id) {
1253 	case ETHTOOL_RX_COPYBREAK:
1254 		priv->rx_copybreak = *(u32 *)data;
1255 		break;
1256 	default:
1257 		ret = -EINVAL;
1258 		break;
1259 	}
1260 
1261 	return ret;
1262 }
1263 
1264 static const struct ethtool_ops stmmac_ethtool_ops = {
1265 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1266 				     ETHTOOL_COALESCE_MAX_FRAMES,
1267 	.begin = stmmac_check_if_running,
1268 	.get_drvinfo = stmmac_ethtool_getdrvinfo,
1269 	.get_msglevel = stmmac_ethtool_getmsglevel,
1270 	.set_msglevel = stmmac_ethtool_setmsglevel,
1271 	.get_regs = stmmac_ethtool_gregs,
1272 	.get_regs_len = stmmac_ethtool_get_regs_len,
1273 	.get_link = ethtool_op_get_link,
1274 	.nway_reset = stmmac_nway_reset,
1275 	.get_ringparam = stmmac_get_ringparam,
1276 	.set_ringparam = stmmac_set_ringparam,
1277 	.get_pauseparam = stmmac_get_pauseparam,
1278 	.set_pauseparam = stmmac_set_pauseparam,
1279 	.self_test = stmmac_selftest_run,
1280 	.get_ethtool_stats = stmmac_get_ethtool_stats,
1281 	.get_strings = stmmac_get_strings,
1282 	.get_wol = stmmac_get_wol,
1283 	.set_wol = stmmac_set_wol,
1284 	.get_eee = stmmac_ethtool_op_get_eee,
1285 	.set_eee = stmmac_ethtool_op_set_eee,
1286 	.get_sset_count	= stmmac_get_sset_count,
1287 	.get_rxnfc = stmmac_get_rxnfc,
1288 	.get_rxfh_key_size = stmmac_get_rxfh_key_size,
1289 	.get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1290 	.get_rxfh = stmmac_get_rxfh,
1291 	.set_rxfh = stmmac_set_rxfh,
1292 	.get_ts_info = stmmac_get_ts_info,
1293 	.get_coalesce = stmmac_get_coalesce,
1294 	.set_coalesce = stmmac_set_coalesce,
1295 	.get_per_queue_coalesce = stmmac_get_per_queue_coalesce,
1296 	.set_per_queue_coalesce = stmmac_set_per_queue_coalesce,
1297 	.get_channels = stmmac_get_channels,
1298 	.set_channels = stmmac_set_channels,
1299 	.get_tunable = stmmac_get_tunable,
1300 	.set_tunable = stmmac_set_tunable,
1301 	.get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1302 	.set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1303 };
1304 
1305 void stmmac_set_ethtool_ops(struct net_device *netdev)
1306 {
1307 	netdev->ethtool_ops = &stmmac_ethtool_ops;
1308 }
1309