1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define MAC100_ETHTOOL_NAME "st_mac100" 25 #define GMAC_ETHTOOL_NAME "st_gmac" 26 #define XGMAC_ETHTOOL_NAME "st_xgmac" 27 28 #define ETHTOOL_DMA_OFFSET 55 29 30 struct stmmac_stats { 31 char stat_string[ETH_GSTRING_LEN]; 32 int sizeof_stat; 33 int stat_offset; 34 }; 35 36 #define STMMAC_STAT(m) \ 37 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 38 offsetof(struct stmmac_priv, xstats.m)} 39 40 static const struct stmmac_stats stmmac_gstrings_stats[] = { 41 /* Transmit errors */ 42 STMMAC_STAT(tx_underflow), 43 STMMAC_STAT(tx_carrier), 44 STMMAC_STAT(tx_losscarrier), 45 STMMAC_STAT(vlan_tag), 46 STMMAC_STAT(tx_deferred), 47 STMMAC_STAT(tx_vlan), 48 STMMAC_STAT(tx_jabber), 49 STMMAC_STAT(tx_frame_flushed), 50 STMMAC_STAT(tx_payload_error), 51 STMMAC_STAT(tx_ip_header_error), 52 /* Receive errors */ 53 STMMAC_STAT(rx_desc), 54 STMMAC_STAT(sa_filter_fail), 55 STMMAC_STAT(overflow_error), 56 STMMAC_STAT(ipc_csum_error), 57 STMMAC_STAT(rx_collision), 58 STMMAC_STAT(rx_crc_errors), 59 STMMAC_STAT(dribbling_bit), 60 STMMAC_STAT(rx_length), 61 STMMAC_STAT(rx_mii), 62 STMMAC_STAT(rx_multicast), 63 STMMAC_STAT(rx_gmac_overflow), 64 STMMAC_STAT(rx_watchdog), 65 STMMAC_STAT(da_rx_filter_fail), 66 STMMAC_STAT(sa_rx_filter_fail), 67 STMMAC_STAT(rx_missed_cntr), 68 STMMAC_STAT(rx_overflow_cntr), 69 STMMAC_STAT(rx_vlan), 70 STMMAC_STAT(rx_split_hdr_pkt_n), 71 /* Tx/Rx IRQ error info */ 72 STMMAC_STAT(tx_undeflow_irq), 73 STMMAC_STAT(tx_process_stopped_irq), 74 STMMAC_STAT(tx_jabber_irq), 75 STMMAC_STAT(rx_overflow_irq), 76 STMMAC_STAT(rx_buf_unav_irq), 77 STMMAC_STAT(rx_process_stopped_irq), 78 STMMAC_STAT(rx_watchdog_irq), 79 STMMAC_STAT(tx_early_irq), 80 STMMAC_STAT(fatal_bus_error_irq), 81 /* Tx/Rx IRQ Events */ 82 STMMAC_STAT(rx_early_irq), 83 STMMAC_STAT(threshold), 84 STMMAC_STAT(tx_pkt_n), 85 STMMAC_STAT(rx_pkt_n), 86 STMMAC_STAT(normal_irq_n), 87 STMMAC_STAT(rx_normal_irq_n), 88 STMMAC_STAT(napi_poll), 89 STMMAC_STAT(tx_normal_irq_n), 90 STMMAC_STAT(tx_clean), 91 STMMAC_STAT(tx_set_ic_bit), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* TSO */ 159 STMMAC_STAT(tx_tso_frames), 160 STMMAC_STAT(tx_tso_nfrags), 161 /* EST */ 162 STMMAC_STAT(mtl_est_cgce), 163 STMMAC_STAT(mtl_est_hlbs), 164 STMMAC_STAT(mtl_est_hlbf), 165 STMMAC_STAT(mtl_est_btre), 166 STMMAC_STAT(mtl_est_btrlm), 167 }; 168 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 169 170 /* HW MAC Management counters (if supported) */ 171 #define STMMAC_MMC_STAT(m) \ 172 { #m, sizeof_field(struct stmmac_counters, m), \ 173 offsetof(struct stmmac_priv, mmc.m)} 174 175 static const struct stmmac_stats stmmac_mmc[] = { 176 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 177 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 178 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 179 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 180 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 181 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 182 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 183 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 184 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 185 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 186 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 187 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 188 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 189 STMMAC_MMC_STAT(mmc_tx_underflow_error), 190 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 191 STMMAC_MMC_STAT(mmc_tx_multicol_g), 192 STMMAC_MMC_STAT(mmc_tx_deferred), 193 STMMAC_MMC_STAT(mmc_tx_latecol), 194 STMMAC_MMC_STAT(mmc_tx_exesscol), 195 STMMAC_MMC_STAT(mmc_tx_carrier_error), 196 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 197 STMMAC_MMC_STAT(mmc_tx_framecount_g), 198 STMMAC_MMC_STAT(mmc_tx_excessdef), 199 STMMAC_MMC_STAT(mmc_tx_pause_frame), 200 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 201 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 202 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 203 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 204 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 205 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 206 STMMAC_MMC_STAT(mmc_rx_crc_error), 207 STMMAC_MMC_STAT(mmc_rx_align_error), 208 STMMAC_MMC_STAT(mmc_rx_run_error), 209 STMMAC_MMC_STAT(mmc_rx_jabber_error), 210 STMMAC_MMC_STAT(mmc_rx_undersize_g), 211 STMMAC_MMC_STAT(mmc_rx_oversize_g), 212 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 213 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 214 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 215 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 216 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 217 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 218 STMMAC_MMC_STAT(mmc_rx_unicast_g), 219 STMMAC_MMC_STAT(mmc_rx_length_error), 220 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 221 STMMAC_MMC_STAT(mmc_rx_pause_frames), 222 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 223 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 224 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 225 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 226 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 227 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 228 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 229 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 230 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 231 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 232 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 233 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 234 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 235 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 236 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 237 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 238 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 239 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 240 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 241 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 242 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 243 STMMAC_MMC_STAT(mmc_rx_udp_gd), 244 STMMAC_MMC_STAT(mmc_rx_udp_err), 245 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 246 STMMAC_MMC_STAT(mmc_rx_tcp_err), 247 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 248 STMMAC_MMC_STAT(mmc_rx_icmp_err), 249 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 250 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 251 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 253 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 254 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 255 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 256 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 257 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 258 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 259 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 260 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 261 }; 262 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 263 264 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 265 struct ethtool_drvinfo *info) 266 { 267 struct stmmac_priv *priv = netdev_priv(dev); 268 269 if (priv->plat->has_gmac || priv->plat->has_gmac4) 270 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 271 else if (priv->plat->has_xgmac) 272 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 273 else 274 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 275 sizeof(info->driver)); 276 277 if (priv->plat->pdev) { 278 strlcpy(info->bus_info, pci_name(priv->plat->pdev), 279 sizeof(info->bus_info)); 280 } 281 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 282 } 283 284 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 285 struct ethtool_link_ksettings *cmd) 286 { 287 struct stmmac_priv *priv = netdev_priv(dev); 288 289 if (priv->hw->pcs & STMMAC_PCS_RGMII || 290 priv->hw->pcs & STMMAC_PCS_SGMII) { 291 struct rgmii_adv adv; 292 u32 supported, advertising, lp_advertising; 293 294 if (!priv->xstats.pcs_link) { 295 cmd->base.speed = SPEED_UNKNOWN; 296 cmd->base.duplex = DUPLEX_UNKNOWN; 297 return 0; 298 } 299 cmd->base.duplex = priv->xstats.pcs_duplex; 300 301 cmd->base.speed = priv->xstats.pcs_speed; 302 303 /* Get and convert ADV/LP_ADV from the HW AN registers */ 304 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 305 return -EOPNOTSUPP; /* should never happen indeed */ 306 307 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 308 309 ethtool_convert_link_mode_to_legacy_u32( 310 &supported, cmd->link_modes.supported); 311 ethtool_convert_link_mode_to_legacy_u32( 312 &advertising, cmd->link_modes.advertising); 313 ethtool_convert_link_mode_to_legacy_u32( 314 &lp_advertising, cmd->link_modes.lp_advertising); 315 316 if (adv.pause & STMMAC_PCS_PAUSE) 317 advertising |= ADVERTISED_Pause; 318 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 319 advertising |= ADVERTISED_Asym_Pause; 320 if (adv.lp_pause & STMMAC_PCS_PAUSE) 321 lp_advertising |= ADVERTISED_Pause; 322 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 323 lp_advertising |= ADVERTISED_Asym_Pause; 324 325 /* Reg49[3] always set because ANE is always supported */ 326 cmd->base.autoneg = ADVERTISED_Autoneg; 327 supported |= SUPPORTED_Autoneg; 328 advertising |= ADVERTISED_Autoneg; 329 lp_advertising |= ADVERTISED_Autoneg; 330 331 if (adv.duplex) { 332 supported |= (SUPPORTED_1000baseT_Full | 333 SUPPORTED_100baseT_Full | 334 SUPPORTED_10baseT_Full); 335 advertising |= (ADVERTISED_1000baseT_Full | 336 ADVERTISED_100baseT_Full | 337 ADVERTISED_10baseT_Full); 338 } else { 339 supported |= (SUPPORTED_1000baseT_Half | 340 SUPPORTED_100baseT_Half | 341 SUPPORTED_10baseT_Half); 342 advertising |= (ADVERTISED_1000baseT_Half | 343 ADVERTISED_100baseT_Half | 344 ADVERTISED_10baseT_Half); 345 } 346 if (adv.lp_duplex) 347 lp_advertising |= (ADVERTISED_1000baseT_Full | 348 ADVERTISED_100baseT_Full | 349 ADVERTISED_10baseT_Full); 350 else 351 lp_advertising |= (ADVERTISED_1000baseT_Half | 352 ADVERTISED_100baseT_Half | 353 ADVERTISED_10baseT_Half); 354 cmd->base.port = PORT_OTHER; 355 356 ethtool_convert_legacy_u32_to_link_mode( 357 cmd->link_modes.supported, supported); 358 ethtool_convert_legacy_u32_to_link_mode( 359 cmd->link_modes.advertising, advertising); 360 ethtool_convert_legacy_u32_to_link_mode( 361 cmd->link_modes.lp_advertising, lp_advertising); 362 363 return 0; 364 } 365 366 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 367 } 368 369 static int 370 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 371 const struct ethtool_link_ksettings *cmd) 372 { 373 struct stmmac_priv *priv = netdev_priv(dev); 374 375 if (priv->hw->pcs & STMMAC_PCS_RGMII || 376 priv->hw->pcs & STMMAC_PCS_SGMII) { 377 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 378 379 /* Only support ANE */ 380 if (cmd->base.autoneg != AUTONEG_ENABLE) 381 return -EINVAL; 382 383 mask &= (ADVERTISED_1000baseT_Half | 384 ADVERTISED_1000baseT_Full | 385 ADVERTISED_100baseT_Half | 386 ADVERTISED_100baseT_Full | 387 ADVERTISED_10baseT_Half | 388 ADVERTISED_10baseT_Full); 389 390 mutex_lock(&priv->lock); 391 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 392 mutex_unlock(&priv->lock); 393 394 return 0; 395 } 396 397 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 398 } 399 400 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 401 { 402 struct stmmac_priv *priv = netdev_priv(dev); 403 return priv->msg_enable; 404 } 405 406 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 407 { 408 struct stmmac_priv *priv = netdev_priv(dev); 409 priv->msg_enable = level; 410 411 } 412 413 static int stmmac_check_if_running(struct net_device *dev) 414 { 415 if (!netif_running(dev)) 416 return -EBUSY; 417 return 0; 418 } 419 420 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 421 { 422 struct stmmac_priv *priv = netdev_priv(dev); 423 424 if (priv->plat->has_xgmac) 425 return XGMAC_REGSIZE * 4; 426 return REG_SPACE_SIZE; 427 } 428 429 static void stmmac_ethtool_gregs(struct net_device *dev, 430 struct ethtool_regs *regs, void *space) 431 { 432 struct stmmac_priv *priv = netdev_priv(dev); 433 u32 *reg_space = (u32 *) space; 434 435 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 436 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 437 438 if (!priv->plat->has_xgmac) { 439 /* Copy DMA registers to where ethtool expects them */ 440 memcpy(®_space[ETHTOOL_DMA_OFFSET], 441 ®_space[DMA_BUS_MODE / 4], 442 NUM_DWMAC1000_DMA_REGS * 4); 443 } 444 } 445 446 static int stmmac_nway_reset(struct net_device *dev) 447 { 448 struct stmmac_priv *priv = netdev_priv(dev); 449 450 return phylink_ethtool_nway_reset(priv->phylink); 451 } 452 453 static void stmmac_get_ringparam(struct net_device *netdev, 454 struct ethtool_ringparam *ring) 455 { 456 struct stmmac_priv *priv = netdev_priv(netdev); 457 458 ring->rx_max_pending = DMA_MAX_RX_SIZE; 459 ring->tx_max_pending = DMA_MAX_TX_SIZE; 460 ring->rx_pending = priv->dma_rx_size; 461 ring->tx_pending = priv->dma_tx_size; 462 } 463 464 static int stmmac_set_ringparam(struct net_device *netdev, 465 struct ethtool_ringparam *ring) 466 { 467 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 468 ring->rx_pending < DMA_MIN_RX_SIZE || 469 ring->rx_pending > DMA_MAX_RX_SIZE || 470 !is_power_of_2(ring->rx_pending) || 471 ring->tx_pending < DMA_MIN_TX_SIZE || 472 ring->tx_pending > DMA_MAX_TX_SIZE || 473 !is_power_of_2(ring->tx_pending)) 474 return -EINVAL; 475 476 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 477 ring->tx_pending); 478 } 479 480 static void 481 stmmac_get_pauseparam(struct net_device *netdev, 482 struct ethtool_pauseparam *pause) 483 { 484 struct stmmac_priv *priv = netdev_priv(netdev); 485 struct rgmii_adv adv_lp; 486 487 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 488 pause->autoneg = 1; 489 if (!adv_lp.pause) 490 return; 491 } else { 492 phylink_ethtool_get_pauseparam(priv->phylink, pause); 493 } 494 } 495 496 static int 497 stmmac_set_pauseparam(struct net_device *netdev, 498 struct ethtool_pauseparam *pause) 499 { 500 struct stmmac_priv *priv = netdev_priv(netdev); 501 struct rgmii_adv adv_lp; 502 503 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 504 pause->autoneg = 1; 505 if (!adv_lp.pause) 506 return -EOPNOTSUPP; 507 return 0; 508 } else { 509 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 510 } 511 } 512 513 static void stmmac_get_ethtool_stats(struct net_device *dev, 514 struct ethtool_stats *dummy, u64 *data) 515 { 516 struct stmmac_priv *priv = netdev_priv(dev); 517 u32 rx_queues_count = priv->plat->rx_queues_to_use; 518 u32 tx_queues_count = priv->plat->tx_queues_to_use; 519 unsigned long count; 520 int i, j = 0, ret; 521 522 if (priv->dma_cap.asp) { 523 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 524 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 525 &count, NULL)) 526 data[j++] = count; 527 } 528 } 529 530 /* Update the DMA HW counters for dwmac10/100 */ 531 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 532 priv->ioaddr); 533 if (ret) { 534 /* If supported, for new GMAC chips expose the MMC counters */ 535 if (priv->dma_cap.rmon) { 536 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 537 538 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 539 char *p; 540 p = (char *)priv + stmmac_mmc[i].stat_offset; 541 542 data[j++] = (stmmac_mmc[i].sizeof_stat == 543 sizeof(u64)) ? (*(u64 *)p) : 544 (*(u32 *)p); 545 } 546 } 547 if (priv->eee_enabled) { 548 int val = phylink_get_eee_err(priv->phylink); 549 if (val) 550 priv->xstats.phy_eee_wakeup_error_n = val; 551 } 552 553 if (priv->synopsys_id >= DWMAC_CORE_3_50) 554 stmmac_mac_debug(priv, priv->ioaddr, 555 (void *)&priv->xstats, 556 rx_queues_count, tx_queues_count); 557 } 558 for (i = 0; i < STMMAC_STATS_LEN; i++) { 559 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 560 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 561 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 562 } 563 } 564 565 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 566 { 567 struct stmmac_priv *priv = netdev_priv(netdev); 568 int i, len, safety_len = 0; 569 570 switch (sset) { 571 case ETH_SS_STATS: 572 len = STMMAC_STATS_LEN; 573 574 if (priv->dma_cap.rmon) 575 len += STMMAC_MMC_STATS_LEN; 576 if (priv->dma_cap.asp) { 577 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 578 if (!stmmac_safety_feat_dump(priv, 579 &priv->sstats, i, 580 NULL, NULL)) 581 safety_len++; 582 } 583 584 len += safety_len; 585 } 586 587 return len; 588 case ETH_SS_TEST: 589 return stmmac_selftest_get_count(priv); 590 default: 591 return -EOPNOTSUPP; 592 } 593 } 594 595 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 596 { 597 int i; 598 u8 *p = data; 599 struct stmmac_priv *priv = netdev_priv(dev); 600 601 switch (stringset) { 602 case ETH_SS_STATS: 603 if (priv->dma_cap.asp) { 604 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 605 const char *desc; 606 if (!stmmac_safety_feat_dump(priv, 607 &priv->sstats, i, 608 NULL, &desc)) { 609 memcpy(p, desc, ETH_GSTRING_LEN); 610 p += ETH_GSTRING_LEN; 611 } 612 } 613 } 614 if (priv->dma_cap.rmon) 615 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 616 memcpy(p, stmmac_mmc[i].stat_string, 617 ETH_GSTRING_LEN); 618 p += ETH_GSTRING_LEN; 619 } 620 for (i = 0; i < STMMAC_STATS_LEN; i++) { 621 memcpy(p, stmmac_gstrings_stats[i].stat_string, 622 ETH_GSTRING_LEN); 623 p += ETH_GSTRING_LEN; 624 } 625 break; 626 case ETH_SS_TEST: 627 stmmac_selftest_get_strings(priv, p); 628 break; 629 default: 630 WARN_ON(1); 631 break; 632 } 633 } 634 635 /* Currently only support WOL through Magic packet. */ 636 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 637 { 638 struct stmmac_priv *priv = netdev_priv(dev); 639 640 if (!priv->plat->pmt) 641 return phylink_ethtool_get_wol(priv->phylink, wol); 642 643 mutex_lock(&priv->lock); 644 if (device_can_wakeup(priv->device)) { 645 wol->supported = WAKE_MAGIC | WAKE_UCAST; 646 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 647 wol->supported &= ~WAKE_MAGIC; 648 wol->wolopts = priv->wolopts; 649 } 650 mutex_unlock(&priv->lock); 651 } 652 653 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 654 { 655 struct stmmac_priv *priv = netdev_priv(dev); 656 u32 support = WAKE_MAGIC | WAKE_UCAST; 657 658 if (!device_can_wakeup(priv->device)) 659 return -EOPNOTSUPP; 660 661 if (!priv->plat->pmt) { 662 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 663 664 if (!ret) 665 device_set_wakeup_enable(priv->device, !!wol->wolopts); 666 return ret; 667 } 668 669 /* By default almost all GMAC devices support the WoL via 670 * magic frame but we can disable it if the HW capability 671 * register shows no support for pmt_magic_frame. */ 672 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 673 wol->wolopts &= ~WAKE_MAGIC; 674 675 if (wol->wolopts & ~support) 676 return -EINVAL; 677 678 if (wol->wolopts) { 679 pr_info("stmmac: wakeup enable\n"); 680 device_set_wakeup_enable(priv->device, 1); 681 enable_irq_wake(priv->wol_irq); 682 } else { 683 device_set_wakeup_enable(priv->device, 0); 684 disable_irq_wake(priv->wol_irq); 685 } 686 687 mutex_lock(&priv->lock); 688 priv->wolopts = wol->wolopts; 689 mutex_unlock(&priv->lock); 690 691 return 0; 692 } 693 694 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 695 struct ethtool_eee *edata) 696 { 697 struct stmmac_priv *priv = netdev_priv(dev); 698 699 if (!priv->dma_cap.eee) 700 return -EOPNOTSUPP; 701 702 edata->eee_enabled = priv->eee_enabled; 703 edata->eee_active = priv->eee_active; 704 edata->tx_lpi_timer = priv->tx_lpi_timer; 705 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 706 707 return phylink_ethtool_get_eee(priv->phylink, edata); 708 } 709 710 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 711 struct ethtool_eee *edata) 712 { 713 struct stmmac_priv *priv = netdev_priv(dev); 714 int ret; 715 716 if (!priv->dma_cap.eee) 717 return -EOPNOTSUPP; 718 719 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 720 netdev_warn(priv->dev, 721 "Setting EEE tx-lpi is not supported\n"); 722 723 if (!edata->eee_enabled) 724 stmmac_disable_eee_mode(priv); 725 726 ret = phylink_ethtool_set_eee(priv->phylink, edata); 727 if (ret) 728 return ret; 729 730 if (edata->eee_enabled && 731 priv->tx_lpi_timer != edata->tx_lpi_timer) { 732 priv->tx_lpi_timer = edata->tx_lpi_timer; 733 stmmac_eee_init(priv); 734 } 735 736 return 0; 737 } 738 739 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 740 { 741 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 742 743 if (!clk) { 744 clk = priv->plat->clk_ref_rate; 745 if (!clk) 746 return 0; 747 } 748 749 return (usec * (clk / 1000000)) / 256; 750 } 751 752 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 753 { 754 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 755 756 if (!clk) { 757 clk = priv->plat->clk_ref_rate; 758 if (!clk) 759 return 0; 760 } 761 762 return (riwt * 256) / (clk / 1000000); 763 } 764 765 static int __stmmac_get_coalesce(struct net_device *dev, 766 struct ethtool_coalesce *ec, 767 int queue) 768 { 769 struct stmmac_priv *priv = netdev_priv(dev); 770 u32 max_cnt; 771 u32 rx_cnt; 772 u32 tx_cnt; 773 774 rx_cnt = priv->plat->rx_queues_to_use; 775 tx_cnt = priv->plat->tx_queues_to_use; 776 max_cnt = max(rx_cnt, tx_cnt); 777 778 if (queue < 0) 779 queue = 0; 780 else if (queue >= max_cnt) 781 return -EINVAL; 782 783 if (queue < tx_cnt) { 784 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 785 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 786 } else { 787 ec->tx_coalesce_usecs = 0; 788 ec->tx_max_coalesced_frames = 0; 789 } 790 791 if (priv->use_riwt && queue < rx_cnt) { 792 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 793 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 794 priv); 795 } else { 796 ec->rx_max_coalesced_frames = 0; 797 ec->rx_coalesce_usecs = 0; 798 } 799 800 return 0; 801 } 802 803 static int stmmac_get_coalesce(struct net_device *dev, 804 struct ethtool_coalesce *ec) 805 { 806 return __stmmac_get_coalesce(dev, ec, -1); 807 } 808 809 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 810 struct ethtool_coalesce *ec) 811 { 812 return __stmmac_get_coalesce(dev, ec, queue); 813 } 814 815 static int __stmmac_set_coalesce(struct net_device *dev, 816 struct ethtool_coalesce *ec, 817 int queue) 818 { 819 struct stmmac_priv *priv = netdev_priv(dev); 820 bool all_queues = false; 821 unsigned int rx_riwt; 822 u32 max_cnt; 823 u32 rx_cnt; 824 u32 tx_cnt; 825 826 rx_cnt = priv->plat->rx_queues_to_use; 827 tx_cnt = priv->plat->tx_queues_to_use; 828 max_cnt = max(rx_cnt, tx_cnt); 829 830 if (queue < 0) 831 all_queues = true; 832 else if (queue >= max_cnt) 833 return -EINVAL; 834 835 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 836 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 837 838 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 839 return -EINVAL; 840 841 if (all_queues) { 842 int i; 843 844 for (i = 0; i < rx_cnt; i++) { 845 priv->rx_riwt[i] = rx_riwt; 846 stmmac_rx_watchdog(priv, priv->ioaddr, 847 rx_riwt, i); 848 priv->rx_coal_frames[i] = 849 ec->rx_max_coalesced_frames; 850 } 851 } else if (queue < rx_cnt) { 852 priv->rx_riwt[queue] = rx_riwt; 853 stmmac_rx_watchdog(priv, priv->ioaddr, 854 rx_riwt, queue); 855 priv->rx_coal_frames[queue] = 856 ec->rx_max_coalesced_frames; 857 } 858 } 859 860 if ((ec->tx_coalesce_usecs == 0) && 861 (ec->tx_max_coalesced_frames == 0)) 862 return -EINVAL; 863 864 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 865 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 866 return -EINVAL; 867 868 if (all_queues) { 869 int i; 870 871 for (i = 0; i < tx_cnt; i++) { 872 priv->tx_coal_frames[i] = 873 ec->tx_max_coalesced_frames; 874 priv->tx_coal_timer[i] = 875 ec->tx_coalesce_usecs; 876 } 877 } else if (queue < tx_cnt) { 878 priv->tx_coal_frames[queue] = 879 ec->tx_max_coalesced_frames; 880 priv->tx_coal_timer[queue] = 881 ec->tx_coalesce_usecs; 882 } 883 884 return 0; 885 } 886 887 static int stmmac_set_coalesce(struct net_device *dev, 888 struct ethtool_coalesce *ec) 889 { 890 return __stmmac_set_coalesce(dev, ec, -1); 891 } 892 893 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 894 struct ethtool_coalesce *ec) 895 { 896 return __stmmac_set_coalesce(dev, ec, queue); 897 } 898 899 static int stmmac_get_rxnfc(struct net_device *dev, 900 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 901 { 902 struct stmmac_priv *priv = netdev_priv(dev); 903 904 switch (rxnfc->cmd) { 905 case ETHTOOL_GRXRINGS: 906 rxnfc->data = priv->plat->rx_queues_to_use; 907 break; 908 default: 909 return -EOPNOTSUPP; 910 } 911 912 return 0; 913 } 914 915 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 916 { 917 struct stmmac_priv *priv = netdev_priv(dev); 918 919 return sizeof(priv->rss.key); 920 } 921 922 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 923 { 924 struct stmmac_priv *priv = netdev_priv(dev); 925 926 return ARRAY_SIZE(priv->rss.table); 927 } 928 929 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 930 u8 *hfunc) 931 { 932 struct stmmac_priv *priv = netdev_priv(dev); 933 int i; 934 935 if (indir) { 936 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 937 indir[i] = priv->rss.table[i]; 938 } 939 940 if (key) 941 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 942 if (hfunc) 943 *hfunc = ETH_RSS_HASH_TOP; 944 945 return 0; 946 } 947 948 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 949 const u8 *key, const u8 hfunc) 950 { 951 struct stmmac_priv *priv = netdev_priv(dev); 952 int i; 953 954 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 955 return -EOPNOTSUPP; 956 957 if (indir) { 958 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 959 priv->rss.table[i] = indir[i]; 960 } 961 962 if (key) 963 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 964 965 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 966 priv->plat->rx_queues_to_use); 967 } 968 969 static void stmmac_get_channels(struct net_device *dev, 970 struct ethtool_channels *chan) 971 { 972 struct stmmac_priv *priv = netdev_priv(dev); 973 974 chan->rx_count = priv->plat->rx_queues_to_use; 975 chan->tx_count = priv->plat->tx_queues_to_use; 976 chan->max_rx = priv->dma_cap.number_rx_queues; 977 chan->max_tx = priv->dma_cap.number_tx_queues; 978 } 979 980 static int stmmac_set_channels(struct net_device *dev, 981 struct ethtool_channels *chan) 982 { 983 struct stmmac_priv *priv = netdev_priv(dev); 984 985 if (chan->rx_count > priv->dma_cap.number_rx_queues || 986 chan->tx_count > priv->dma_cap.number_tx_queues || 987 !chan->rx_count || !chan->tx_count) 988 return -EINVAL; 989 990 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 991 } 992 993 static int stmmac_get_ts_info(struct net_device *dev, 994 struct ethtool_ts_info *info) 995 { 996 struct stmmac_priv *priv = netdev_priv(dev); 997 998 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 999 1000 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1001 SOF_TIMESTAMPING_TX_HARDWARE | 1002 SOF_TIMESTAMPING_RX_SOFTWARE | 1003 SOF_TIMESTAMPING_RX_HARDWARE | 1004 SOF_TIMESTAMPING_SOFTWARE | 1005 SOF_TIMESTAMPING_RAW_HARDWARE; 1006 1007 if (priv->ptp_clock) 1008 info->phc_index = ptp_clock_index(priv->ptp_clock); 1009 1010 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1011 1012 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1013 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1014 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1015 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1016 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1017 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1018 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1019 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1020 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1021 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1022 (1 << HWTSTAMP_FILTER_ALL)); 1023 return 0; 1024 } else 1025 return ethtool_op_get_ts_info(dev, info); 1026 } 1027 1028 static int stmmac_get_tunable(struct net_device *dev, 1029 const struct ethtool_tunable *tuna, void *data) 1030 { 1031 struct stmmac_priv *priv = netdev_priv(dev); 1032 int ret = 0; 1033 1034 switch (tuna->id) { 1035 case ETHTOOL_RX_COPYBREAK: 1036 *(u32 *)data = priv->rx_copybreak; 1037 break; 1038 default: 1039 ret = -EINVAL; 1040 break; 1041 } 1042 1043 return ret; 1044 } 1045 1046 static int stmmac_set_tunable(struct net_device *dev, 1047 const struct ethtool_tunable *tuna, 1048 const void *data) 1049 { 1050 struct stmmac_priv *priv = netdev_priv(dev); 1051 int ret = 0; 1052 1053 switch (tuna->id) { 1054 case ETHTOOL_RX_COPYBREAK: 1055 priv->rx_copybreak = *(u32 *)data; 1056 break; 1057 default: 1058 ret = -EINVAL; 1059 break; 1060 } 1061 1062 return ret; 1063 } 1064 1065 static const struct ethtool_ops stmmac_ethtool_ops = { 1066 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1067 ETHTOOL_COALESCE_MAX_FRAMES, 1068 .begin = stmmac_check_if_running, 1069 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1070 .get_msglevel = stmmac_ethtool_getmsglevel, 1071 .set_msglevel = stmmac_ethtool_setmsglevel, 1072 .get_regs = stmmac_ethtool_gregs, 1073 .get_regs_len = stmmac_ethtool_get_regs_len, 1074 .get_link = ethtool_op_get_link, 1075 .nway_reset = stmmac_nway_reset, 1076 .get_ringparam = stmmac_get_ringparam, 1077 .set_ringparam = stmmac_set_ringparam, 1078 .get_pauseparam = stmmac_get_pauseparam, 1079 .set_pauseparam = stmmac_set_pauseparam, 1080 .self_test = stmmac_selftest_run, 1081 .get_ethtool_stats = stmmac_get_ethtool_stats, 1082 .get_strings = stmmac_get_strings, 1083 .get_wol = stmmac_get_wol, 1084 .set_wol = stmmac_set_wol, 1085 .get_eee = stmmac_ethtool_op_get_eee, 1086 .set_eee = stmmac_ethtool_op_set_eee, 1087 .get_sset_count = stmmac_get_sset_count, 1088 .get_rxnfc = stmmac_get_rxnfc, 1089 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1090 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1091 .get_rxfh = stmmac_get_rxfh, 1092 .set_rxfh = stmmac_set_rxfh, 1093 .get_ts_info = stmmac_get_ts_info, 1094 .get_coalesce = stmmac_get_coalesce, 1095 .set_coalesce = stmmac_set_coalesce, 1096 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1097 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1098 .get_channels = stmmac_get_channels, 1099 .set_channels = stmmac_set_channels, 1100 .get_tunable = stmmac_get_tunable, 1101 .set_tunable = stmmac_set_tunable, 1102 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1103 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1104 }; 1105 1106 void stmmac_set_ethtool_ops(struct net_device *netdev) 1107 { 1108 netdev->ethtool_ops = &stmmac_ethtool_ops; 1109 } 1110