1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define MAC100_ETHTOOL_NAME "st_mac100" 25 #define GMAC_ETHTOOL_NAME "st_gmac" 26 #define XGMAC_ETHTOOL_NAME "st_xgmac" 27 28 #define ETHTOOL_DMA_OFFSET 55 29 30 struct stmmac_stats { 31 char stat_string[ETH_GSTRING_LEN]; 32 int sizeof_stat; 33 int stat_offset; 34 }; 35 36 #define STMMAC_STAT(m) \ 37 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 38 offsetof(struct stmmac_priv, xstats.m)} 39 40 static const struct stmmac_stats stmmac_gstrings_stats[] = { 41 /* Transmit errors */ 42 STMMAC_STAT(tx_underflow), 43 STMMAC_STAT(tx_carrier), 44 STMMAC_STAT(tx_losscarrier), 45 STMMAC_STAT(vlan_tag), 46 STMMAC_STAT(tx_deferred), 47 STMMAC_STAT(tx_vlan), 48 STMMAC_STAT(tx_jabber), 49 STMMAC_STAT(tx_frame_flushed), 50 STMMAC_STAT(tx_payload_error), 51 STMMAC_STAT(tx_ip_header_error), 52 /* Receive errors */ 53 STMMAC_STAT(rx_desc), 54 STMMAC_STAT(sa_filter_fail), 55 STMMAC_STAT(overflow_error), 56 STMMAC_STAT(ipc_csum_error), 57 STMMAC_STAT(rx_collision), 58 STMMAC_STAT(rx_crc_errors), 59 STMMAC_STAT(dribbling_bit), 60 STMMAC_STAT(rx_length), 61 STMMAC_STAT(rx_mii), 62 STMMAC_STAT(rx_multicast), 63 STMMAC_STAT(rx_gmac_overflow), 64 STMMAC_STAT(rx_watchdog), 65 STMMAC_STAT(da_rx_filter_fail), 66 STMMAC_STAT(sa_rx_filter_fail), 67 STMMAC_STAT(rx_missed_cntr), 68 STMMAC_STAT(rx_overflow_cntr), 69 STMMAC_STAT(rx_vlan), 70 STMMAC_STAT(rx_split_hdr_pkt_n), 71 /* Tx/Rx IRQ error info */ 72 STMMAC_STAT(tx_undeflow_irq), 73 STMMAC_STAT(tx_process_stopped_irq), 74 STMMAC_STAT(tx_jabber_irq), 75 STMMAC_STAT(rx_overflow_irq), 76 STMMAC_STAT(rx_buf_unav_irq), 77 STMMAC_STAT(rx_process_stopped_irq), 78 STMMAC_STAT(rx_watchdog_irq), 79 STMMAC_STAT(tx_early_irq), 80 STMMAC_STAT(fatal_bus_error_irq), 81 /* Tx/Rx IRQ Events */ 82 STMMAC_STAT(rx_early_irq), 83 STMMAC_STAT(threshold), 84 STMMAC_STAT(tx_pkt_n), 85 STMMAC_STAT(rx_pkt_n), 86 STMMAC_STAT(normal_irq_n), 87 STMMAC_STAT(rx_normal_irq_n), 88 STMMAC_STAT(napi_poll), 89 STMMAC_STAT(tx_normal_irq_n), 90 STMMAC_STAT(tx_clean), 91 STMMAC_STAT(tx_set_ic_bit), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* TSO */ 159 STMMAC_STAT(tx_tso_frames), 160 STMMAC_STAT(tx_tso_nfrags), 161 /* EST */ 162 STMMAC_STAT(mtl_est_cgce), 163 STMMAC_STAT(mtl_est_hlbs), 164 STMMAC_STAT(mtl_est_hlbf), 165 STMMAC_STAT(mtl_est_btre), 166 STMMAC_STAT(mtl_est_btrlm), 167 }; 168 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 169 170 /* HW MAC Management counters (if supported) */ 171 #define STMMAC_MMC_STAT(m) \ 172 { #m, sizeof_field(struct stmmac_counters, m), \ 173 offsetof(struct stmmac_priv, mmc.m)} 174 175 static const struct stmmac_stats stmmac_mmc[] = { 176 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 177 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 178 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 179 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 180 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 181 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 182 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 183 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 184 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 185 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 186 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 187 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 188 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 189 STMMAC_MMC_STAT(mmc_tx_underflow_error), 190 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 191 STMMAC_MMC_STAT(mmc_tx_multicol_g), 192 STMMAC_MMC_STAT(mmc_tx_deferred), 193 STMMAC_MMC_STAT(mmc_tx_latecol), 194 STMMAC_MMC_STAT(mmc_tx_exesscol), 195 STMMAC_MMC_STAT(mmc_tx_carrier_error), 196 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 197 STMMAC_MMC_STAT(mmc_tx_framecount_g), 198 STMMAC_MMC_STAT(mmc_tx_excessdef), 199 STMMAC_MMC_STAT(mmc_tx_pause_frame), 200 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 201 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 202 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 203 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 204 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 205 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 206 STMMAC_MMC_STAT(mmc_rx_crc_error), 207 STMMAC_MMC_STAT(mmc_rx_align_error), 208 STMMAC_MMC_STAT(mmc_rx_run_error), 209 STMMAC_MMC_STAT(mmc_rx_jabber_error), 210 STMMAC_MMC_STAT(mmc_rx_undersize_g), 211 STMMAC_MMC_STAT(mmc_rx_oversize_g), 212 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 213 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 214 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 215 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 216 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 217 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 218 STMMAC_MMC_STAT(mmc_rx_unicast_g), 219 STMMAC_MMC_STAT(mmc_rx_length_error), 220 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 221 STMMAC_MMC_STAT(mmc_rx_pause_frames), 222 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 223 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 224 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 225 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 226 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 227 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 228 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 229 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 230 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 231 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 232 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 233 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 234 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 235 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 236 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 237 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 238 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 239 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 240 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 241 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 242 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 243 STMMAC_MMC_STAT(mmc_rx_udp_gd), 244 STMMAC_MMC_STAT(mmc_rx_udp_err), 245 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 246 STMMAC_MMC_STAT(mmc_rx_tcp_err), 247 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 248 STMMAC_MMC_STAT(mmc_rx_icmp_err), 249 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 250 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 251 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 253 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 254 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 255 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 256 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 257 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 258 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 259 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 260 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 261 }; 262 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 263 264 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 265 "tx_pkt_n", 266 "tx_irq_n", 267 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 268 }; 269 270 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 271 "rx_pkt_n", 272 "rx_irq_n", 273 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 274 }; 275 276 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 277 struct ethtool_drvinfo *info) 278 { 279 struct stmmac_priv *priv = netdev_priv(dev); 280 281 if (priv->plat->has_gmac || priv->plat->has_gmac4) 282 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 283 else if (priv->plat->has_xgmac) 284 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 285 else 286 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 287 sizeof(info->driver)); 288 289 if (priv->plat->pdev) { 290 strlcpy(info->bus_info, pci_name(priv->plat->pdev), 291 sizeof(info->bus_info)); 292 } 293 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 294 } 295 296 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 297 struct ethtool_link_ksettings *cmd) 298 { 299 struct stmmac_priv *priv = netdev_priv(dev); 300 301 if (priv->hw->pcs & STMMAC_PCS_RGMII || 302 priv->hw->pcs & STMMAC_PCS_SGMII) { 303 struct rgmii_adv adv; 304 u32 supported, advertising, lp_advertising; 305 306 if (!priv->xstats.pcs_link) { 307 cmd->base.speed = SPEED_UNKNOWN; 308 cmd->base.duplex = DUPLEX_UNKNOWN; 309 return 0; 310 } 311 cmd->base.duplex = priv->xstats.pcs_duplex; 312 313 cmd->base.speed = priv->xstats.pcs_speed; 314 315 /* Get and convert ADV/LP_ADV from the HW AN registers */ 316 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 317 return -EOPNOTSUPP; /* should never happen indeed */ 318 319 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 320 321 ethtool_convert_link_mode_to_legacy_u32( 322 &supported, cmd->link_modes.supported); 323 ethtool_convert_link_mode_to_legacy_u32( 324 &advertising, cmd->link_modes.advertising); 325 ethtool_convert_link_mode_to_legacy_u32( 326 &lp_advertising, cmd->link_modes.lp_advertising); 327 328 if (adv.pause & STMMAC_PCS_PAUSE) 329 advertising |= ADVERTISED_Pause; 330 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 331 advertising |= ADVERTISED_Asym_Pause; 332 if (adv.lp_pause & STMMAC_PCS_PAUSE) 333 lp_advertising |= ADVERTISED_Pause; 334 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 335 lp_advertising |= ADVERTISED_Asym_Pause; 336 337 /* Reg49[3] always set because ANE is always supported */ 338 cmd->base.autoneg = ADVERTISED_Autoneg; 339 supported |= SUPPORTED_Autoneg; 340 advertising |= ADVERTISED_Autoneg; 341 lp_advertising |= ADVERTISED_Autoneg; 342 343 if (adv.duplex) { 344 supported |= (SUPPORTED_1000baseT_Full | 345 SUPPORTED_100baseT_Full | 346 SUPPORTED_10baseT_Full); 347 advertising |= (ADVERTISED_1000baseT_Full | 348 ADVERTISED_100baseT_Full | 349 ADVERTISED_10baseT_Full); 350 } else { 351 supported |= (SUPPORTED_1000baseT_Half | 352 SUPPORTED_100baseT_Half | 353 SUPPORTED_10baseT_Half); 354 advertising |= (ADVERTISED_1000baseT_Half | 355 ADVERTISED_100baseT_Half | 356 ADVERTISED_10baseT_Half); 357 } 358 if (adv.lp_duplex) 359 lp_advertising |= (ADVERTISED_1000baseT_Full | 360 ADVERTISED_100baseT_Full | 361 ADVERTISED_10baseT_Full); 362 else 363 lp_advertising |= (ADVERTISED_1000baseT_Half | 364 ADVERTISED_100baseT_Half | 365 ADVERTISED_10baseT_Half); 366 cmd->base.port = PORT_OTHER; 367 368 ethtool_convert_legacy_u32_to_link_mode( 369 cmd->link_modes.supported, supported); 370 ethtool_convert_legacy_u32_to_link_mode( 371 cmd->link_modes.advertising, advertising); 372 ethtool_convert_legacy_u32_to_link_mode( 373 cmd->link_modes.lp_advertising, lp_advertising); 374 375 return 0; 376 } 377 378 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 379 } 380 381 static int 382 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 383 const struct ethtool_link_ksettings *cmd) 384 { 385 struct stmmac_priv *priv = netdev_priv(dev); 386 387 if (priv->hw->pcs & STMMAC_PCS_RGMII || 388 priv->hw->pcs & STMMAC_PCS_SGMII) { 389 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 390 391 /* Only support ANE */ 392 if (cmd->base.autoneg != AUTONEG_ENABLE) 393 return -EINVAL; 394 395 mask &= (ADVERTISED_1000baseT_Half | 396 ADVERTISED_1000baseT_Full | 397 ADVERTISED_100baseT_Half | 398 ADVERTISED_100baseT_Full | 399 ADVERTISED_10baseT_Half | 400 ADVERTISED_10baseT_Full); 401 402 mutex_lock(&priv->lock); 403 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 404 mutex_unlock(&priv->lock); 405 406 return 0; 407 } 408 409 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 410 } 411 412 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 413 { 414 struct stmmac_priv *priv = netdev_priv(dev); 415 return priv->msg_enable; 416 } 417 418 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 419 { 420 struct stmmac_priv *priv = netdev_priv(dev); 421 priv->msg_enable = level; 422 423 } 424 425 static int stmmac_check_if_running(struct net_device *dev) 426 { 427 if (!netif_running(dev)) 428 return -EBUSY; 429 return 0; 430 } 431 432 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 433 { 434 struct stmmac_priv *priv = netdev_priv(dev); 435 436 if (priv->plat->has_xgmac) 437 return XGMAC_REGSIZE * 4; 438 return REG_SPACE_SIZE; 439 } 440 441 static void stmmac_ethtool_gregs(struct net_device *dev, 442 struct ethtool_regs *regs, void *space) 443 { 444 struct stmmac_priv *priv = netdev_priv(dev); 445 u32 *reg_space = (u32 *) space; 446 447 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 448 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 449 450 if (!priv->plat->has_xgmac) { 451 /* Copy DMA registers to where ethtool expects them */ 452 memcpy(®_space[ETHTOOL_DMA_OFFSET], 453 ®_space[DMA_BUS_MODE / 4], 454 NUM_DWMAC1000_DMA_REGS * 4); 455 } 456 } 457 458 static int stmmac_nway_reset(struct net_device *dev) 459 { 460 struct stmmac_priv *priv = netdev_priv(dev); 461 462 return phylink_ethtool_nway_reset(priv->phylink); 463 } 464 465 static void stmmac_get_ringparam(struct net_device *netdev, 466 struct ethtool_ringparam *ring) 467 { 468 struct stmmac_priv *priv = netdev_priv(netdev); 469 470 ring->rx_max_pending = DMA_MAX_RX_SIZE; 471 ring->tx_max_pending = DMA_MAX_TX_SIZE; 472 ring->rx_pending = priv->dma_rx_size; 473 ring->tx_pending = priv->dma_tx_size; 474 } 475 476 static int stmmac_set_ringparam(struct net_device *netdev, 477 struct ethtool_ringparam *ring) 478 { 479 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 480 ring->rx_pending < DMA_MIN_RX_SIZE || 481 ring->rx_pending > DMA_MAX_RX_SIZE || 482 !is_power_of_2(ring->rx_pending) || 483 ring->tx_pending < DMA_MIN_TX_SIZE || 484 ring->tx_pending > DMA_MAX_TX_SIZE || 485 !is_power_of_2(ring->tx_pending)) 486 return -EINVAL; 487 488 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 489 ring->tx_pending); 490 } 491 492 static void 493 stmmac_get_pauseparam(struct net_device *netdev, 494 struct ethtool_pauseparam *pause) 495 { 496 struct stmmac_priv *priv = netdev_priv(netdev); 497 struct rgmii_adv adv_lp; 498 499 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 500 pause->autoneg = 1; 501 if (!adv_lp.pause) 502 return; 503 } else { 504 phylink_ethtool_get_pauseparam(priv->phylink, pause); 505 } 506 } 507 508 static int 509 stmmac_set_pauseparam(struct net_device *netdev, 510 struct ethtool_pauseparam *pause) 511 { 512 struct stmmac_priv *priv = netdev_priv(netdev); 513 struct rgmii_adv adv_lp; 514 515 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 516 pause->autoneg = 1; 517 if (!adv_lp.pause) 518 return -EOPNOTSUPP; 519 return 0; 520 } else { 521 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 522 } 523 } 524 525 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 526 { 527 u32 tx_cnt = priv->plat->tx_queues_to_use; 528 u32 rx_cnt = priv->plat->rx_queues_to_use; 529 int q, stat; 530 char *p; 531 532 for (q = 0; q < tx_cnt; q++) { 533 p = (char *)priv + offsetof(struct stmmac_priv, 534 xstats.txq_stats[q].tx_pkt_n); 535 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 536 *data++ = (*(u64 *)p); 537 p += sizeof(u64 *); 538 } 539 } 540 for (q = 0; q < rx_cnt; q++) { 541 p = (char *)priv + offsetof(struct stmmac_priv, 542 xstats.rxq_stats[q].rx_pkt_n); 543 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 544 *data++ = (*(u64 *)p); 545 p += sizeof(u64 *); 546 } 547 } 548 } 549 550 static void stmmac_get_ethtool_stats(struct net_device *dev, 551 struct ethtool_stats *dummy, u64 *data) 552 { 553 struct stmmac_priv *priv = netdev_priv(dev); 554 u32 rx_queues_count = priv->plat->rx_queues_to_use; 555 u32 tx_queues_count = priv->plat->tx_queues_to_use; 556 unsigned long count; 557 int i, j = 0, ret; 558 559 if (priv->dma_cap.asp) { 560 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 561 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 562 &count, NULL)) 563 data[j++] = count; 564 } 565 } 566 567 /* Update the DMA HW counters for dwmac10/100 */ 568 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 569 priv->ioaddr); 570 if (ret) { 571 /* If supported, for new GMAC chips expose the MMC counters */ 572 if (priv->dma_cap.rmon) { 573 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 574 575 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 576 char *p; 577 p = (char *)priv + stmmac_mmc[i].stat_offset; 578 579 data[j++] = (stmmac_mmc[i].sizeof_stat == 580 sizeof(u64)) ? (*(u64 *)p) : 581 (*(u32 *)p); 582 } 583 } 584 if (priv->eee_enabled) { 585 int val = phylink_get_eee_err(priv->phylink); 586 if (val) 587 priv->xstats.phy_eee_wakeup_error_n = val; 588 } 589 590 if (priv->synopsys_id >= DWMAC_CORE_3_50) 591 stmmac_mac_debug(priv, priv->ioaddr, 592 (void *)&priv->xstats, 593 rx_queues_count, tx_queues_count); 594 } 595 for (i = 0; i < STMMAC_STATS_LEN; i++) { 596 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 597 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 598 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 599 } 600 stmmac_get_per_qstats(priv, &data[j]); 601 } 602 603 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 604 { 605 struct stmmac_priv *priv = netdev_priv(netdev); 606 u32 tx_cnt = priv->plat->tx_queues_to_use; 607 u32 rx_cnt = priv->plat->rx_queues_to_use; 608 int i, len, safety_len = 0; 609 610 switch (sset) { 611 case ETH_SS_STATS: 612 len = STMMAC_STATS_LEN + 613 STMMAC_TXQ_STATS * tx_cnt + 614 STMMAC_RXQ_STATS * rx_cnt; 615 616 if (priv->dma_cap.rmon) 617 len += STMMAC_MMC_STATS_LEN; 618 if (priv->dma_cap.asp) { 619 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 620 if (!stmmac_safety_feat_dump(priv, 621 &priv->sstats, i, 622 NULL, NULL)) 623 safety_len++; 624 } 625 626 len += safety_len; 627 } 628 629 return len; 630 case ETH_SS_TEST: 631 return stmmac_selftest_get_count(priv); 632 default: 633 return -EOPNOTSUPP; 634 } 635 } 636 637 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 638 { 639 u32 tx_cnt = priv->plat->tx_queues_to_use; 640 u32 rx_cnt = priv->plat->rx_queues_to_use; 641 int q, stat; 642 643 for (q = 0; q < tx_cnt; q++) { 644 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 645 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 646 stmmac_qstats_tx_string[stat]); 647 data += ETH_GSTRING_LEN; 648 } 649 } 650 for (q = 0; q < rx_cnt; q++) { 651 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 652 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 653 stmmac_qstats_rx_string[stat]); 654 data += ETH_GSTRING_LEN; 655 } 656 } 657 } 658 659 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 660 { 661 int i; 662 u8 *p = data; 663 struct stmmac_priv *priv = netdev_priv(dev); 664 665 switch (stringset) { 666 case ETH_SS_STATS: 667 if (priv->dma_cap.asp) { 668 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 669 const char *desc; 670 if (!stmmac_safety_feat_dump(priv, 671 &priv->sstats, i, 672 NULL, &desc)) { 673 memcpy(p, desc, ETH_GSTRING_LEN); 674 p += ETH_GSTRING_LEN; 675 } 676 } 677 } 678 if (priv->dma_cap.rmon) 679 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 680 memcpy(p, stmmac_mmc[i].stat_string, 681 ETH_GSTRING_LEN); 682 p += ETH_GSTRING_LEN; 683 } 684 for (i = 0; i < STMMAC_STATS_LEN; i++) { 685 memcpy(p, stmmac_gstrings_stats[i].stat_string, 686 ETH_GSTRING_LEN); 687 p += ETH_GSTRING_LEN; 688 } 689 stmmac_get_qstats_string(priv, p); 690 break; 691 case ETH_SS_TEST: 692 stmmac_selftest_get_strings(priv, p); 693 break; 694 default: 695 WARN_ON(1); 696 break; 697 } 698 } 699 700 /* Currently only support WOL through Magic packet. */ 701 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 702 { 703 struct stmmac_priv *priv = netdev_priv(dev); 704 705 if (!priv->plat->pmt) 706 return phylink_ethtool_get_wol(priv->phylink, wol); 707 708 mutex_lock(&priv->lock); 709 if (device_can_wakeup(priv->device)) { 710 wol->supported = WAKE_MAGIC | WAKE_UCAST; 711 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 712 wol->supported &= ~WAKE_MAGIC; 713 wol->wolopts = priv->wolopts; 714 } 715 mutex_unlock(&priv->lock); 716 } 717 718 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 719 { 720 struct stmmac_priv *priv = netdev_priv(dev); 721 u32 support = WAKE_MAGIC | WAKE_UCAST; 722 723 if (!device_can_wakeup(priv->device)) 724 return -EOPNOTSUPP; 725 726 if (!priv->plat->pmt) { 727 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 728 729 if (!ret) 730 device_set_wakeup_enable(priv->device, !!wol->wolopts); 731 return ret; 732 } 733 734 /* By default almost all GMAC devices support the WoL via 735 * magic frame but we can disable it if the HW capability 736 * register shows no support for pmt_magic_frame. */ 737 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 738 wol->wolopts &= ~WAKE_MAGIC; 739 740 if (wol->wolopts & ~support) 741 return -EINVAL; 742 743 if (wol->wolopts) { 744 pr_info("stmmac: wakeup enable\n"); 745 device_set_wakeup_enable(priv->device, 1); 746 enable_irq_wake(priv->wol_irq); 747 } else { 748 device_set_wakeup_enable(priv->device, 0); 749 disable_irq_wake(priv->wol_irq); 750 } 751 752 mutex_lock(&priv->lock); 753 priv->wolopts = wol->wolopts; 754 mutex_unlock(&priv->lock); 755 756 return 0; 757 } 758 759 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 760 struct ethtool_eee *edata) 761 { 762 struct stmmac_priv *priv = netdev_priv(dev); 763 764 if (!priv->dma_cap.eee) 765 return -EOPNOTSUPP; 766 767 edata->eee_enabled = priv->eee_enabled; 768 edata->eee_active = priv->eee_active; 769 edata->tx_lpi_timer = priv->tx_lpi_timer; 770 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 771 772 return phylink_ethtool_get_eee(priv->phylink, edata); 773 } 774 775 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 776 struct ethtool_eee *edata) 777 { 778 struct stmmac_priv *priv = netdev_priv(dev); 779 int ret; 780 781 if (!priv->dma_cap.eee) 782 return -EOPNOTSUPP; 783 784 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 785 netdev_warn(priv->dev, 786 "Setting EEE tx-lpi is not supported\n"); 787 788 if (priv->hw->xpcs) { 789 ret = xpcs_config_eee(priv->hw->xpcs, 790 priv->plat->mult_fact_100ns, 791 edata->eee_enabled); 792 if (ret) 793 return ret; 794 } 795 796 if (!edata->eee_enabled) 797 stmmac_disable_eee_mode(priv); 798 799 ret = phylink_ethtool_set_eee(priv->phylink, edata); 800 if (ret) 801 return ret; 802 803 if (edata->eee_enabled && 804 priv->tx_lpi_timer != edata->tx_lpi_timer) { 805 priv->tx_lpi_timer = edata->tx_lpi_timer; 806 stmmac_eee_init(priv); 807 } 808 809 return 0; 810 } 811 812 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 813 { 814 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 815 816 if (!clk) { 817 clk = priv->plat->clk_ref_rate; 818 if (!clk) 819 return 0; 820 } 821 822 return (usec * (clk / 1000000)) / 256; 823 } 824 825 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 826 { 827 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 828 829 if (!clk) { 830 clk = priv->plat->clk_ref_rate; 831 if (!clk) 832 return 0; 833 } 834 835 return (riwt * 256) / (clk / 1000000); 836 } 837 838 static int __stmmac_get_coalesce(struct net_device *dev, 839 struct ethtool_coalesce *ec, 840 int queue) 841 { 842 struct stmmac_priv *priv = netdev_priv(dev); 843 u32 max_cnt; 844 u32 rx_cnt; 845 u32 tx_cnt; 846 847 rx_cnt = priv->plat->rx_queues_to_use; 848 tx_cnt = priv->plat->tx_queues_to_use; 849 max_cnt = max(rx_cnt, tx_cnt); 850 851 if (queue < 0) 852 queue = 0; 853 else if (queue >= max_cnt) 854 return -EINVAL; 855 856 if (queue < tx_cnt) { 857 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 858 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 859 } else { 860 ec->tx_coalesce_usecs = 0; 861 ec->tx_max_coalesced_frames = 0; 862 } 863 864 if (priv->use_riwt && queue < rx_cnt) { 865 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 866 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 867 priv); 868 } else { 869 ec->rx_max_coalesced_frames = 0; 870 ec->rx_coalesce_usecs = 0; 871 } 872 873 return 0; 874 } 875 876 static int stmmac_get_coalesce(struct net_device *dev, 877 struct ethtool_coalesce *ec, 878 struct kernel_ethtool_coalesce *kernel_coal, 879 struct netlink_ext_ack *extack) 880 { 881 return __stmmac_get_coalesce(dev, ec, -1); 882 } 883 884 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 885 struct ethtool_coalesce *ec) 886 { 887 return __stmmac_get_coalesce(dev, ec, queue); 888 } 889 890 static int __stmmac_set_coalesce(struct net_device *dev, 891 struct ethtool_coalesce *ec, 892 int queue) 893 { 894 struct stmmac_priv *priv = netdev_priv(dev); 895 bool all_queues = false; 896 unsigned int rx_riwt; 897 u32 max_cnt; 898 u32 rx_cnt; 899 u32 tx_cnt; 900 901 rx_cnt = priv->plat->rx_queues_to_use; 902 tx_cnt = priv->plat->tx_queues_to_use; 903 max_cnt = max(rx_cnt, tx_cnt); 904 905 if (queue < 0) 906 all_queues = true; 907 else if (queue >= max_cnt) 908 return -EINVAL; 909 910 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 911 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 912 913 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 914 return -EINVAL; 915 916 if (all_queues) { 917 int i; 918 919 for (i = 0; i < rx_cnt; i++) { 920 priv->rx_riwt[i] = rx_riwt; 921 stmmac_rx_watchdog(priv, priv->ioaddr, 922 rx_riwt, i); 923 priv->rx_coal_frames[i] = 924 ec->rx_max_coalesced_frames; 925 } 926 } else if (queue < rx_cnt) { 927 priv->rx_riwt[queue] = rx_riwt; 928 stmmac_rx_watchdog(priv, priv->ioaddr, 929 rx_riwt, queue); 930 priv->rx_coal_frames[queue] = 931 ec->rx_max_coalesced_frames; 932 } 933 } 934 935 if ((ec->tx_coalesce_usecs == 0) && 936 (ec->tx_max_coalesced_frames == 0)) 937 return -EINVAL; 938 939 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 940 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 941 return -EINVAL; 942 943 if (all_queues) { 944 int i; 945 946 for (i = 0; i < tx_cnt; i++) { 947 priv->tx_coal_frames[i] = 948 ec->tx_max_coalesced_frames; 949 priv->tx_coal_timer[i] = 950 ec->tx_coalesce_usecs; 951 } 952 } else if (queue < tx_cnt) { 953 priv->tx_coal_frames[queue] = 954 ec->tx_max_coalesced_frames; 955 priv->tx_coal_timer[queue] = 956 ec->tx_coalesce_usecs; 957 } 958 959 return 0; 960 } 961 962 static int stmmac_set_coalesce(struct net_device *dev, 963 struct ethtool_coalesce *ec, 964 struct kernel_ethtool_coalesce *kernel_coal, 965 struct netlink_ext_ack *extack) 966 { 967 return __stmmac_set_coalesce(dev, ec, -1); 968 } 969 970 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 971 struct ethtool_coalesce *ec) 972 { 973 return __stmmac_set_coalesce(dev, ec, queue); 974 } 975 976 static int stmmac_get_rxnfc(struct net_device *dev, 977 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 978 { 979 struct stmmac_priv *priv = netdev_priv(dev); 980 981 switch (rxnfc->cmd) { 982 case ETHTOOL_GRXRINGS: 983 rxnfc->data = priv->plat->rx_queues_to_use; 984 break; 985 default: 986 return -EOPNOTSUPP; 987 } 988 989 return 0; 990 } 991 992 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 993 { 994 struct stmmac_priv *priv = netdev_priv(dev); 995 996 return sizeof(priv->rss.key); 997 } 998 999 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1000 { 1001 struct stmmac_priv *priv = netdev_priv(dev); 1002 1003 return ARRAY_SIZE(priv->rss.table); 1004 } 1005 1006 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1007 u8 *hfunc) 1008 { 1009 struct stmmac_priv *priv = netdev_priv(dev); 1010 int i; 1011 1012 if (indir) { 1013 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1014 indir[i] = priv->rss.table[i]; 1015 } 1016 1017 if (key) 1018 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 1019 if (hfunc) 1020 *hfunc = ETH_RSS_HASH_TOP; 1021 1022 return 0; 1023 } 1024 1025 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 1026 const u8 *key, const u8 hfunc) 1027 { 1028 struct stmmac_priv *priv = netdev_priv(dev); 1029 int i; 1030 1031 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 1032 return -EOPNOTSUPP; 1033 1034 if (indir) { 1035 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1036 priv->rss.table[i] = indir[i]; 1037 } 1038 1039 if (key) 1040 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 1041 1042 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1043 priv->plat->rx_queues_to_use); 1044 } 1045 1046 static void stmmac_get_channels(struct net_device *dev, 1047 struct ethtool_channels *chan) 1048 { 1049 struct stmmac_priv *priv = netdev_priv(dev); 1050 1051 chan->rx_count = priv->plat->rx_queues_to_use; 1052 chan->tx_count = priv->plat->tx_queues_to_use; 1053 chan->max_rx = priv->dma_cap.number_rx_queues; 1054 chan->max_tx = priv->dma_cap.number_tx_queues; 1055 } 1056 1057 static int stmmac_set_channels(struct net_device *dev, 1058 struct ethtool_channels *chan) 1059 { 1060 struct stmmac_priv *priv = netdev_priv(dev); 1061 1062 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1063 chan->tx_count > priv->dma_cap.number_tx_queues || 1064 !chan->rx_count || !chan->tx_count) 1065 return -EINVAL; 1066 1067 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1068 } 1069 1070 static int stmmac_get_ts_info(struct net_device *dev, 1071 struct ethtool_ts_info *info) 1072 { 1073 struct stmmac_priv *priv = netdev_priv(dev); 1074 1075 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1076 1077 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1078 SOF_TIMESTAMPING_TX_HARDWARE | 1079 SOF_TIMESTAMPING_RX_SOFTWARE | 1080 SOF_TIMESTAMPING_RX_HARDWARE | 1081 SOF_TIMESTAMPING_SOFTWARE | 1082 SOF_TIMESTAMPING_RAW_HARDWARE; 1083 1084 if (priv->ptp_clock) 1085 info->phc_index = ptp_clock_index(priv->ptp_clock); 1086 1087 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1088 1089 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1090 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1091 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1092 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1093 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1094 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1095 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1096 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1097 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1098 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1099 (1 << HWTSTAMP_FILTER_ALL)); 1100 return 0; 1101 } else 1102 return ethtool_op_get_ts_info(dev, info); 1103 } 1104 1105 static int stmmac_get_tunable(struct net_device *dev, 1106 const struct ethtool_tunable *tuna, void *data) 1107 { 1108 struct stmmac_priv *priv = netdev_priv(dev); 1109 int ret = 0; 1110 1111 switch (tuna->id) { 1112 case ETHTOOL_RX_COPYBREAK: 1113 *(u32 *)data = priv->rx_copybreak; 1114 break; 1115 default: 1116 ret = -EINVAL; 1117 break; 1118 } 1119 1120 return ret; 1121 } 1122 1123 static int stmmac_set_tunable(struct net_device *dev, 1124 const struct ethtool_tunable *tuna, 1125 const void *data) 1126 { 1127 struct stmmac_priv *priv = netdev_priv(dev); 1128 int ret = 0; 1129 1130 switch (tuna->id) { 1131 case ETHTOOL_RX_COPYBREAK: 1132 priv->rx_copybreak = *(u32 *)data; 1133 break; 1134 default: 1135 ret = -EINVAL; 1136 break; 1137 } 1138 1139 return ret; 1140 } 1141 1142 static const struct ethtool_ops stmmac_ethtool_ops = { 1143 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1144 ETHTOOL_COALESCE_MAX_FRAMES, 1145 .begin = stmmac_check_if_running, 1146 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1147 .get_msglevel = stmmac_ethtool_getmsglevel, 1148 .set_msglevel = stmmac_ethtool_setmsglevel, 1149 .get_regs = stmmac_ethtool_gregs, 1150 .get_regs_len = stmmac_ethtool_get_regs_len, 1151 .get_link = ethtool_op_get_link, 1152 .nway_reset = stmmac_nway_reset, 1153 .get_ringparam = stmmac_get_ringparam, 1154 .set_ringparam = stmmac_set_ringparam, 1155 .get_pauseparam = stmmac_get_pauseparam, 1156 .set_pauseparam = stmmac_set_pauseparam, 1157 .self_test = stmmac_selftest_run, 1158 .get_ethtool_stats = stmmac_get_ethtool_stats, 1159 .get_strings = stmmac_get_strings, 1160 .get_wol = stmmac_get_wol, 1161 .set_wol = stmmac_set_wol, 1162 .get_eee = stmmac_ethtool_op_get_eee, 1163 .set_eee = stmmac_ethtool_op_set_eee, 1164 .get_sset_count = stmmac_get_sset_count, 1165 .get_rxnfc = stmmac_get_rxnfc, 1166 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1167 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1168 .get_rxfh = stmmac_get_rxfh, 1169 .set_rxfh = stmmac_set_rxfh, 1170 .get_ts_info = stmmac_get_ts_info, 1171 .get_coalesce = stmmac_get_coalesce, 1172 .set_coalesce = stmmac_set_coalesce, 1173 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1174 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1175 .get_channels = stmmac_get_channels, 1176 .set_channels = stmmac_set_channels, 1177 .get_tunable = stmmac_get_tunable, 1178 .set_tunable = stmmac_set_tunable, 1179 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1180 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1181 }; 1182 1183 void stmmac_set_ethtool_ops(struct net_device *netdev) 1184 { 1185 netdev->ethtool_ops = &stmmac_ethtool_ops; 1186 } 1187