1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define GMAC4_REG_SPACE_SIZE 0x116C 25 #define MAC100_ETHTOOL_NAME "st_mac100" 26 #define GMAC_ETHTOOL_NAME "st_gmac" 27 #define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(tx_pkt_n), 93 STMMAC_STAT(rx_pkt_n), 94 STMMAC_STAT(normal_irq_n), 95 STMMAC_STAT(rx_normal_irq_n), 96 STMMAC_STAT(napi_poll), 97 STMMAC_STAT(tx_normal_irq_n), 98 STMMAC_STAT(tx_clean), 99 STMMAC_STAT(tx_set_ic_bit), 100 STMMAC_STAT(irq_receive_pmt_irq_n), 101 /* MMC info */ 102 STMMAC_STAT(mmc_tx_irq_n), 103 STMMAC_STAT(mmc_rx_irq_n), 104 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 105 /* EEE */ 106 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 107 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 108 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 109 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 110 STMMAC_STAT(phy_eee_wakeup_error_n), 111 /* Extended RDES status */ 112 STMMAC_STAT(ip_hdr_err), 113 STMMAC_STAT(ip_payload_err), 114 STMMAC_STAT(ip_csum_bypassed), 115 STMMAC_STAT(ipv4_pkt_rcvd), 116 STMMAC_STAT(ipv6_pkt_rcvd), 117 STMMAC_STAT(no_ptp_rx_msg_type_ext), 118 STMMAC_STAT(ptp_rx_msg_type_sync), 119 STMMAC_STAT(ptp_rx_msg_type_follow_up), 120 STMMAC_STAT(ptp_rx_msg_type_delay_req), 121 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 122 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 123 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 124 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 125 STMMAC_STAT(ptp_rx_msg_type_announce), 126 STMMAC_STAT(ptp_rx_msg_type_management), 127 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 128 STMMAC_STAT(ptp_frame_type), 129 STMMAC_STAT(ptp_ver), 130 STMMAC_STAT(timestamp_dropped), 131 STMMAC_STAT(av_pkt_rcvd), 132 STMMAC_STAT(av_tagged_pkt_rcvd), 133 STMMAC_STAT(vlan_tag_priority_val), 134 STMMAC_STAT(l3_filter_match), 135 STMMAC_STAT(l4_filter_match), 136 STMMAC_STAT(l3_l4_filter_no_match), 137 /* PCS */ 138 STMMAC_STAT(irq_pcs_ane_n), 139 STMMAC_STAT(irq_pcs_link_n), 140 STMMAC_STAT(irq_rgmii_n), 141 /* DEBUG */ 142 STMMAC_STAT(mtl_tx_status_fifo_full), 143 STMMAC_STAT(mtl_tx_fifo_not_empty), 144 STMMAC_STAT(mmtl_fifo_ctrl), 145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 148 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 149 STMMAC_STAT(mac_tx_in_pause), 150 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 151 STMMAC_STAT(mac_tx_frame_ctrl_idle), 152 STMMAC_STAT(mac_tx_frame_ctrl_wait), 153 STMMAC_STAT(mac_tx_frame_ctrl_pause), 154 STMMAC_STAT(mac_gmii_tx_proto_engine), 155 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 156 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 157 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 158 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 162 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 163 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 164 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 165 STMMAC_STAT(mac_gmii_rx_proto_engine), 166 /* TSO */ 167 STMMAC_STAT(tx_tso_frames), 168 STMMAC_STAT(tx_tso_nfrags), 169 /* EST */ 170 STMMAC_STAT(mtl_est_cgce), 171 STMMAC_STAT(mtl_est_hlbs), 172 STMMAC_STAT(mtl_est_hlbf), 173 STMMAC_STAT(mtl_est_btre), 174 STMMAC_STAT(mtl_est_btrlm), 175 }; 176 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 177 178 /* HW MAC Management counters (if supported) */ 179 #define STMMAC_MMC_STAT(m) \ 180 { #m, sizeof_field(struct stmmac_counters, m), \ 181 offsetof(struct stmmac_priv, mmc.m)} 182 183 static const struct stmmac_stats stmmac_mmc[] = { 184 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 185 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 186 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 187 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 188 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 189 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 190 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 191 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 192 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 193 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 194 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 195 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 196 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 197 STMMAC_MMC_STAT(mmc_tx_underflow_error), 198 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 199 STMMAC_MMC_STAT(mmc_tx_multicol_g), 200 STMMAC_MMC_STAT(mmc_tx_deferred), 201 STMMAC_MMC_STAT(mmc_tx_latecol), 202 STMMAC_MMC_STAT(mmc_tx_exesscol), 203 STMMAC_MMC_STAT(mmc_tx_carrier_error), 204 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 205 STMMAC_MMC_STAT(mmc_tx_framecount_g), 206 STMMAC_MMC_STAT(mmc_tx_excessdef), 207 STMMAC_MMC_STAT(mmc_tx_pause_frame), 208 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 209 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 210 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 211 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 212 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 213 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 214 STMMAC_MMC_STAT(mmc_rx_crc_error), 215 STMMAC_MMC_STAT(mmc_rx_align_error), 216 STMMAC_MMC_STAT(mmc_rx_run_error), 217 STMMAC_MMC_STAT(mmc_rx_jabber_error), 218 STMMAC_MMC_STAT(mmc_rx_undersize_g), 219 STMMAC_MMC_STAT(mmc_rx_oversize_g), 220 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 221 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 222 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 223 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 224 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 225 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 226 STMMAC_MMC_STAT(mmc_rx_unicast_g), 227 STMMAC_MMC_STAT(mmc_rx_length_error), 228 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 229 STMMAC_MMC_STAT(mmc_rx_pause_frames), 230 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 231 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 232 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 233 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 234 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 235 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 236 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 237 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 238 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 239 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 240 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 241 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 242 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 243 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 244 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 245 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 246 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 247 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 248 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 249 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 250 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 251 STMMAC_MMC_STAT(mmc_rx_udp_gd), 252 STMMAC_MMC_STAT(mmc_rx_udp_err), 253 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 254 STMMAC_MMC_STAT(mmc_rx_tcp_err), 255 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 256 STMMAC_MMC_STAT(mmc_rx_icmp_err), 257 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 258 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 259 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 260 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 261 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 262 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 263 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 264 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 265 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 266 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 267 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 268 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 269 }; 270 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 271 272 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 273 "tx_pkt_n", 274 "tx_irq_n", 275 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 276 }; 277 278 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 279 "rx_pkt_n", 280 "rx_irq_n", 281 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 282 }; 283 284 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 285 struct ethtool_drvinfo *info) 286 { 287 struct stmmac_priv *priv = netdev_priv(dev); 288 289 if (priv->plat->has_gmac || priv->plat->has_gmac4) 290 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 291 else if (priv->plat->has_xgmac) 292 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 293 else 294 strscpy(info->driver, MAC100_ETHTOOL_NAME, 295 sizeof(info->driver)); 296 297 if (priv->plat->pdev) { 298 strscpy(info->bus_info, pci_name(priv->plat->pdev), 299 sizeof(info->bus_info)); 300 } 301 } 302 303 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 304 struct ethtool_link_ksettings *cmd) 305 { 306 struct stmmac_priv *priv = netdev_priv(dev); 307 308 if (priv->hw->pcs & STMMAC_PCS_RGMII || 309 priv->hw->pcs & STMMAC_PCS_SGMII) { 310 struct rgmii_adv adv; 311 u32 supported, advertising, lp_advertising; 312 313 if (!priv->xstats.pcs_link) { 314 cmd->base.speed = SPEED_UNKNOWN; 315 cmd->base.duplex = DUPLEX_UNKNOWN; 316 return 0; 317 } 318 cmd->base.duplex = priv->xstats.pcs_duplex; 319 320 cmd->base.speed = priv->xstats.pcs_speed; 321 322 /* Get and convert ADV/LP_ADV from the HW AN registers */ 323 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 324 return -EOPNOTSUPP; /* should never happen indeed */ 325 326 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 327 328 ethtool_convert_link_mode_to_legacy_u32( 329 &supported, cmd->link_modes.supported); 330 ethtool_convert_link_mode_to_legacy_u32( 331 &advertising, cmd->link_modes.advertising); 332 ethtool_convert_link_mode_to_legacy_u32( 333 &lp_advertising, cmd->link_modes.lp_advertising); 334 335 if (adv.pause & STMMAC_PCS_PAUSE) 336 advertising |= ADVERTISED_Pause; 337 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 338 advertising |= ADVERTISED_Asym_Pause; 339 if (adv.lp_pause & STMMAC_PCS_PAUSE) 340 lp_advertising |= ADVERTISED_Pause; 341 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 342 lp_advertising |= ADVERTISED_Asym_Pause; 343 344 /* Reg49[3] always set because ANE is always supported */ 345 cmd->base.autoneg = ADVERTISED_Autoneg; 346 supported |= SUPPORTED_Autoneg; 347 advertising |= ADVERTISED_Autoneg; 348 lp_advertising |= ADVERTISED_Autoneg; 349 350 if (adv.duplex) { 351 supported |= (SUPPORTED_1000baseT_Full | 352 SUPPORTED_100baseT_Full | 353 SUPPORTED_10baseT_Full); 354 advertising |= (ADVERTISED_1000baseT_Full | 355 ADVERTISED_100baseT_Full | 356 ADVERTISED_10baseT_Full); 357 } else { 358 supported |= (SUPPORTED_1000baseT_Half | 359 SUPPORTED_100baseT_Half | 360 SUPPORTED_10baseT_Half); 361 advertising |= (ADVERTISED_1000baseT_Half | 362 ADVERTISED_100baseT_Half | 363 ADVERTISED_10baseT_Half); 364 } 365 if (adv.lp_duplex) 366 lp_advertising |= (ADVERTISED_1000baseT_Full | 367 ADVERTISED_100baseT_Full | 368 ADVERTISED_10baseT_Full); 369 else 370 lp_advertising |= (ADVERTISED_1000baseT_Half | 371 ADVERTISED_100baseT_Half | 372 ADVERTISED_10baseT_Half); 373 cmd->base.port = PORT_OTHER; 374 375 ethtool_convert_legacy_u32_to_link_mode( 376 cmd->link_modes.supported, supported); 377 ethtool_convert_legacy_u32_to_link_mode( 378 cmd->link_modes.advertising, advertising); 379 ethtool_convert_legacy_u32_to_link_mode( 380 cmd->link_modes.lp_advertising, lp_advertising); 381 382 return 0; 383 } 384 385 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 386 } 387 388 static int 389 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 390 const struct ethtool_link_ksettings *cmd) 391 { 392 struct stmmac_priv *priv = netdev_priv(dev); 393 394 if (priv->hw->pcs & STMMAC_PCS_RGMII || 395 priv->hw->pcs & STMMAC_PCS_SGMII) { 396 /* Only support ANE */ 397 if (cmd->base.autoneg != AUTONEG_ENABLE) 398 return -EINVAL; 399 400 mutex_lock(&priv->lock); 401 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 402 mutex_unlock(&priv->lock); 403 404 return 0; 405 } 406 407 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 408 } 409 410 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 411 { 412 struct stmmac_priv *priv = netdev_priv(dev); 413 return priv->msg_enable; 414 } 415 416 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 417 { 418 struct stmmac_priv *priv = netdev_priv(dev); 419 priv->msg_enable = level; 420 421 } 422 423 static int stmmac_check_if_running(struct net_device *dev) 424 { 425 if (!netif_running(dev)) 426 return -EBUSY; 427 return 0; 428 } 429 430 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 431 { 432 struct stmmac_priv *priv = netdev_priv(dev); 433 434 if (priv->plat->has_xgmac) 435 return XGMAC_REGSIZE * 4; 436 else if (priv->plat->has_gmac4) 437 return GMAC4_REG_SPACE_SIZE; 438 return REG_SPACE_SIZE; 439 } 440 441 static void stmmac_ethtool_gregs(struct net_device *dev, 442 struct ethtool_regs *regs, void *space) 443 { 444 struct stmmac_priv *priv = netdev_priv(dev); 445 u32 *reg_space = (u32 *) space; 446 447 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 448 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 449 450 /* Copy DMA registers to where ethtool expects them */ 451 if (priv->plat->has_gmac4) { 452 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 453 memcpy(®_space[ETHTOOL_DMA_OFFSET], 454 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 455 NUM_DWMAC4_DMA_REGS * 4); 456 } else if (!priv->plat->has_xgmac) { 457 memcpy(®_space[ETHTOOL_DMA_OFFSET], 458 ®_space[DMA_BUS_MODE / 4], 459 NUM_DWMAC1000_DMA_REGS * 4); 460 } 461 } 462 463 static int stmmac_nway_reset(struct net_device *dev) 464 { 465 struct stmmac_priv *priv = netdev_priv(dev); 466 467 return phylink_ethtool_nway_reset(priv->phylink); 468 } 469 470 static void stmmac_get_ringparam(struct net_device *netdev, 471 struct ethtool_ringparam *ring, 472 struct kernel_ethtool_ringparam *kernel_ring, 473 struct netlink_ext_ack *extack) 474 { 475 struct stmmac_priv *priv = netdev_priv(netdev); 476 477 ring->rx_max_pending = DMA_MAX_RX_SIZE; 478 ring->tx_max_pending = DMA_MAX_TX_SIZE; 479 ring->rx_pending = priv->dma_conf.dma_rx_size; 480 ring->tx_pending = priv->dma_conf.dma_tx_size; 481 } 482 483 static int stmmac_set_ringparam(struct net_device *netdev, 484 struct ethtool_ringparam *ring, 485 struct kernel_ethtool_ringparam *kernel_ring, 486 struct netlink_ext_ack *extack) 487 { 488 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 489 ring->rx_pending < DMA_MIN_RX_SIZE || 490 ring->rx_pending > DMA_MAX_RX_SIZE || 491 !is_power_of_2(ring->rx_pending) || 492 ring->tx_pending < DMA_MIN_TX_SIZE || 493 ring->tx_pending > DMA_MAX_TX_SIZE || 494 !is_power_of_2(ring->tx_pending)) 495 return -EINVAL; 496 497 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 498 ring->tx_pending); 499 } 500 501 static void 502 stmmac_get_pauseparam(struct net_device *netdev, 503 struct ethtool_pauseparam *pause) 504 { 505 struct stmmac_priv *priv = netdev_priv(netdev); 506 struct rgmii_adv adv_lp; 507 508 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 509 pause->autoneg = 1; 510 if (!adv_lp.pause) 511 return; 512 } else { 513 phylink_ethtool_get_pauseparam(priv->phylink, pause); 514 } 515 } 516 517 static int 518 stmmac_set_pauseparam(struct net_device *netdev, 519 struct ethtool_pauseparam *pause) 520 { 521 struct stmmac_priv *priv = netdev_priv(netdev); 522 struct rgmii_adv adv_lp; 523 524 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 525 pause->autoneg = 1; 526 if (!adv_lp.pause) 527 return -EOPNOTSUPP; 528 return 0; 529 } else { 530 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 531 } 532 } 533 534 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 535 { 536 u32 tx_cnt = priv->plat->tx_queues_to_use; 537 u32 rx_cnt = priv->plat->rx_queues_to_use; 538 int q, stat; 539 char *p; 540 541 for (q = 0; q < tx_cnt; q++) { 542 p = (char *)priv + offsetof(struct stmmac_priv, 543 xstats.txq_stats[q].tx_pkt_n); 544 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 545 *data++ = (*(unsigned long *)p); 546 p += sizeof(unsigned long); 547 } 548 } 549 for (q = 0; q < rx_cnt; q++) { 550 p = (char *)priv + offsetof(struct stmmac_priv, 551 xstats.rxq_stats[q].rx_pkt_n); 552 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 553 *data++ = (*(unsigned long *)p); 554 p += sizeof(unsigned long); 555 } 556 } 557 } 558 559 static void stmmac_get_ethtool_stats(struct net_device *dev, 560 struct ethtool_stats *dummy, u64 *data) 561 { 562 struct stmmac_priv *priv = netdev_priv(dev); 563 u32 rx_queues_count = priv->plat->rx_queues_to_use; 564 u32 tx_queues_count = priv->plat->tx_queues_to_use; 565 unsigned long count; 566 int i, j = 0, ret; 567 568 if (priv->dma_cap.asp) { 569 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 570 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 571 &count, NULL)) 572 data[j++] = count; 573 } 574 } 575 576 /* Update the DMA HW counters for dwmac10/100 */ 577 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 578 priv->ioaddr); 579 if (ret) { 580 /* If supported, for new GMAC chips expose the MMC counters */ 581 if (priv->dma_cap.rmon) { 582 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 583 584 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 585 char *p; 586 p = (char *)priv + stmmac_mmc[i].stat_offset; 587 588 data[j++] = (stmmac_mmc[i].sizeof_stat == 589 sizeof(u64)) ? (*(u64 *)p) : 590 (*(u32 *)p); 591 } 592 } 593 if (priv->eee_enabled) { 594 int val = phylink_get_eee_err(priv->phylink); 595 if (val) 596 priv->xstats.phy_eee_wakeup_error_n = val; 597 } 598 599 if (priv->synopsys_id >= DWMAC_CORE_3_50) 600 stmmac_mac_debug(priv, priv->ioaddr, 601 (void *)&priv->xstats, 602 rx_queues_count, tx_queues_count); 603 } 604 for (i = 0; i < STMMAC_STATS_LEN; i++) { 605 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 606 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 607 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 608 } 609 stmmac_get_per_qstats(priv, &data[j]); 610 } 611 612 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 613 { 614 struct stmmac_priv *priv = netdev_priv(netdev); 615 u32 tx_cnt = priv->plat->tx_queues_to_use; 616 u32 rx_cnt = priv->plat->rx_queues_to_use; 617 int i, len, safety_len = 0; 618 619 switch (sset) { 620 case ETH_SS_STATS: 621 len = STMMAC_STATS_LEN + 622 STMMAC_TXQ_STATS * tx_cnt + 623 STMMAC_RXQ_STATS * rx_cnt; 624 625 if (priv->dma_cap.rmon) 626 len += STMMAC_MMC_STATS_LEN; 627 if (priv->dma_cap.asp) { 628 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 629 if (!stmmac_safety_feat_dump(priv, 630 &priv->sstats, i, 631 NULL, NULL)) 632 safety_len++; 633 } 634 635 len += safety_len; 636 } 637 638 return len; 639 case ETH_SS_TEST: 640 return stmmac_selftest_get_count(priv); 641 default: 642 return -EOPNOTSUPP; 643 } 644 } 645 646 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 647 { 648 u32 tx_cnt = priv->plat->tx_queues_to_use; 649 u32 rx_cnt = priv->plat->rx_queues_to_use; 650 int q, stat; 651 652 for (q = 0; q < tx_cnt; q++) { 653 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 654 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 655 stmmac_qstats_tx_string[stat]); 656 data += ETH_GSTRING_LEN; 657 } 658 } 659 for (q = 0; q < rx_cnt; q++) { 660 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 661 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 662 stmmac_qstats_rx_string[stat]); 663 data += ETH_GSTRING_LEN; 664 } 665 } 666 } 667 668 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 669 { 670 int i; 671 u8 *p = data; 672 struct stmmac_priv *priv = netdev_priv(dev); 673 674 switch (stringset) { 675 case ETH_SS_STATS: 676 if (priv->dma_cap.asp) { 677 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 678 const char *desc; 679 if (!stmmac_safety_feat_dump(priv, 680 &priv->sstats, i, 681 NULL, &desc)) { 682 memcpy(p, desc, ETH_GSTRING_LEN); 683 p += ETH_GSTRING_LEN; 684 } 685 } 686 } 687 if (priv->dma_cap.rmon) 688 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 689 memcpy(p, stmmac_mmc[i].stat_string, 690 ETH_GSTRING_LEN); 691 p += ETH_GSTRING_LEN; 692 } 693 for (i = 0; i < STMMAC_STATS_LEN; i++) { 694 memcpy(p, stmmac_gstrings_stats[i].stat_string, 695 ETH_GSTRING_LEN); 696 p += ETH_GSTRING_LEN; 697 } 698 stmmac_get_qstats_string(priv, p); 699 break; 700 case ETH_SS_TEST: 701 stmmac_selftest_get_strings(priv, p); 702 break; 703 default: 704 WARN_ON(1); 705 break; 706 } 707 } 708 709 /* Currently only support WOL through Magic packet. */ 710 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 711 { 712 struct stmmac_priv *priv = netdev_priv(dev); 713 714 if (!priv->plat->pmt) 715 return phylink_ethtool_get_wol(priv->phylink, wol); 716 717 mutex_lock(&priv->lock); 718 if (device_can_wakeup(priv->device)) { 719 wol->supported = WAKE_MAGIC | WAKE_UCAST; 720 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 721 wol->supported &= ~WAKE_MAGIC; 722 wol->wolopts = priv->wolopts; 723 } 724 mutex_unlock(&priv->lock); 725 } 726 727 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 728 { 729 struct stmmac_priv *priv = netdev_priv(dev); 730 u32 support = WAKE_MAGIC | WAKE_UCAST; 731 732 if (!device_can_wakeup(priv->device)) 733 return -EOPNOTSUPP; 734 735 if (!priv->plat->pmt) { 736 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 737 738 if (!ret) 739 device_set_wakeup_enable(priv->device, !!wol->wolopts); 740 return ret; 741 } 742 743 /* By default almost all GMAC devices support the WoL via 744 * magic frame but we can disable it if the HW capability 745 * register shows no support for pmt_magic_frame. */ 746 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 747 wol->wolopts &= ~WAKE_MAGIC; 748 749 if (wol->wolopts & ~support) 750 return -EINVAL; 751 752 if (wol->wolopts) { 753 pr_info("stmmac: wakeup enable\n"); 754 device_set_wakeup_enable(priv->device, 1); 755 enable_irq_wake(priv->wol_irq); 756 } else { 757 device_set_wakeup_enable(priv->device, 0); 758 disable_irq_wake(priv->wol_irq); 759 } 760 761 mutex_lock(&priv->lock); 762 priv->wolopts = wol->wolopts; 763 mutex_unlock(&priv->lock); 764 765 return 0; 766 } 767 768 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 769 struct ethtool_eee *edata) 770 { 771 struct stmmac_priv *priv = netdev_priv(dev); 772 773 if (!priv->dma_cap.eee) 774 return -EOPNOTSUPP; 775 776 edata->eee_enabled = priv->eee_enabled; 777 edata->eee_active = priv->eee_active; 778 edata->tx_lpi_timer = priv->tx_lpi_timer; 779 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 780 781 return phylink_ethtool_get_eee(priv->phylink, edata); 782 } 783 784 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 785 struct ethtool_eee *edata) 786 { 787 struct stmmac_priv *priv = netdev_priv(dev); 788 int ret; 789 790 if (!priv->dma_cap.eee) 791 return -EOPNOTSUPP; 792 793 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 794 netdev_warn(priv->dev, 795 "Setting EEE tx-lpi is not supported\n"); 796 797 if (!edata->eee_enabled) 798 stmmac_disable_eee_mode(priv); 799 800 ret = phylink_ethtool_set_eee(priv->phylink, edata); 801 if (ret) 802 return ret; 803 804 if (edata->eee_enabled && 805 priv->tx_lpi_timer != edata->tx_lpi_timer) { 806 priv->tx_lpi_timer = edata->tx_lpi_timer; 807 stmmac_eee_init(priv); 808 } 809 810 return 0; 811 } 812 813 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 814 { 815 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 816 817 if (!clk) { 818 clk = priv->plat->clk_ref_rate; 819 if (!clk) 820 return 0; 821 } 822 823 return (usec * (clk / 1000000)) / 256; 824 } 825 826 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 827 { 828 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 829 830 if (!clk) { 831 clk = priv->plat->clk_ref_rate; 832 if (!clk) 833 return 0; 834 } 835 836 return (riwt * 256) / (clk / 1000000); 837 } 838 839 static int __stmmac_get_coalesce(struct net_device *dev, 840 struct ethtool_coalesce *ec, 841 int queue) 842 { 843 struct stmmac_priv *priv = netdev_priv(dev); 844 u32 max_cnt; 845 u32 rx_cnt; 846 u32 tx_cnt; 847 848 rx_cnt = priv->plat->rx_queues_to_use; 849 tx_cnt = priv->plat->tx_queues_to_use; 850 max_cnt = max(rx_cnt, tx_cnt); 851 852 if (queue < 0) 853 queue = 0; 854 else if (queue >= max_cnt) 855 return -EINVAL; 856 857 if (queue < tx_cnt) { 858 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 859 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 860 } else { 861 ec->tx_coalesce_usecs = 0; 862 ec->tx_max_coalesced_frames = 0; 863 } 864 865 if (priv->use_riwt && queue < rx_cnt) { 866 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 867 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 868 priv); 869 } else { 870 ec->rx_max_coalesced_frames = 0; 871 ec->rx_coalesce_usecs = 0; 872 } 873 874 return 0; 875 } 876 877 static int stmmac_get_coalesce(struct net_device *dev, 878 struct ethtool_coalesce *ec, 879 struct kernel_ethtool_coalesce *kernel_coal, 880 struct netlink_ext_ack *extack) 881 { 882 return __stmmac_get_coalesce(dev, ec, -1); 883 } 884 885 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 886 struct ethtool_coalesce *ec) 887 { 888 return __stmmac_get_coalesce(dev, ec, queue); 889 } 890 891 static int __stmmac_set_coalesce(struct net_device *dev, 892 struct ethtool_coalesce *ec, 893 int queue) 894 { 895 struct stmmac_priv *priv = netdev_priv(dev); 896 bool all_queues = false; 897 unsigned int rx_riwt; 898 u32 max_cnt; 899 u32 rx_cnt; 900 u32 tx_cnt; 901 902 rx_cnt = priv->plat->rx_queues_to_use; 903 tx_cnt = priv->plat->tx_queues_to_use; 904 max_cnt = max(rx_cnt, tx_cnt); 905 906 if (queue < 0) 907 all_queues = true; 908 else if (queue >= max_cnt) 909 return -EINVAL; 910 911 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 912 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 913 914 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 915 return -EINVAL; 916 917 if (all_queues) { 918 int i; 919 920 for (i = 0; i < rx_cnt; i++) { 921 priv->rx_riwt[i] = rx_riwt; 922 stmmac_rx_watchdog(priv, priv->ioaddr, 923 rx_riwt, i); 924 priv->rx_coal_frames[i] = 925 ec->rx_max_coalesced_frames; 926 } 927 } else if (queue < rx_cnt) { 928 priv->rx_riwt[queue] = rx_riwt; 929 stmmac_rx_watchdog(priv, priv->ioaddr, 930 rx_riwt, queue); 931 priv->rx_coal_frames[queue] = 932 ec->rx_max_coalesced_frames; 933 } 934 } 935 936 if ((ec->tx_coalesce_usecs == 0) && 937 (ec->tx_max_coalesced_frames == 0)) 938 return -EINVAL; 939 940 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 941 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 942 return -EINVAL; 943 944 if (all_queues) { 945 int i; 946 947 for (i = 0; i < tx_cnt; i++) { 948 priv->tx_coal_frames[i] = 949 ec->tx_max_coalesced_frames; 950 priv->tx_coal_timer[i] = 951 ec->tx_coalesce_usecs; 952 } 953 } else if (queue < tx_cnt) { 954 priv->tx_coal_frames[queue] = 955 ec->tx_max_coalesced_frames; 956 priv->tx_coal_timer[queue] = 957 ec->tx_coalesce_usecs; 958 } 959 960 return 0; 961 } 962 963 static int stmmac_set_coalesce(struct net_device *dev, 964 struct ethtool_coalesce *ec, 965 struct kernel_ethtool_coalesce *kernel_coal, 966 struct netlink_ext_ack *extack) 967 { 968 return __stmmac_set_coalesce(dev, ec, -1); 969 } 970 971 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 972 struct ethtool_coalesce *ec) 973 { 974 return __stmmac_set_coalesce(dev, ec, queue); 975 } 976 977 static int stmmac_get_rxnfc(struct net_device *dev, 978 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 979 { 980 struct stmmac_priv *priv = netdev_priv(dev); 981 982 switch (rxnfc->cmd) { 983 case ETHTOOL_GRXRINGS: 984 rxnfc->data = priv->plat->rx_queues_to_use; 985 break; 986 default: 987 return -EOPNOTSUPP; 988 } 989 990 return 0; 991 } 992 993 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 994 { 995 struct stmmac_priv *priv = netdev_priv(dev); 996 997 return sizeof(priv->rss.key); 998 } 999 1000 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1001 { 1002 struct stmmac_priv *priv = netdev_priv(dev); 1003 1004 return ARRAY_SIZE(priv->rss.table); 1005 } 1006 1007 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1008 u8 *hfunc) 1009 { 1010 struct stmmac_priv *priv = netdev_priv(dev); 1011 int i; 1012 1013 if (indir) { 1014 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1015 indir[i] = priv->rss.table[i]; 1016 } 1017 1018 if (key) 1019 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 1020 if (hfunc) 1021 *hfunc = ETH_RSS_HASH_TOP; 1022 1023 return 0; 1024 } 1025 1026 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 1027 const u8 *key, const u8 hfunc) 1028 { 1029 struct stmmac_priv *priv = netdev_priv(dev); 1030 int i; 1031 1032 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 1033 return -EOPNOTSUPP; 1034 1035 if (indir) { 1036 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1037 priv->rss.table[i] = indir[i]; 1038 } 1039 1040 if (key) 1041 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 1042 1043 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1044 priv->plat->rx_queues_to_use); 1045 } 1046 1047 static void stmmac_get_channels(struct net_device *dev, 1048 struct ethtool_channels *chan) 1049 { 1050 struct stmmac_priv *priv = netdev_priv(dev); 1051 1052 chan->rx_count = priv->plat->rx_queues_to_use; 1053 chan->tx_count = priv->plat->tx_queues_to_use; 1054 chan->max_rx = priv->dma_cap.number_rx_queues; 1055 chan->max_tx = priv->dma_cap.number_tx_queues; 1056 } 1057 1058 static int stmmac_set_channels(struct net_device *dev, 1059 struct ethtool_channels *chan) 1060 { 1061 struct stmmac_priv *priv = netdev_priv(dev); 1062 1063 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1064 chan->tx_count > priv->dma_cap.number_tx_queues || 1065 !chan->rx_count || !chan->tx_count) 1066 return -EINVAL; 1067 1068 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1069 } 1070 1071 static int stmmac_get_ts_info(struct net_device *dev, 1072 struct ethtool_ts_info *info) 1073 { 1074 struct stmmac_priv *priv = netdev_priv(dev); 1075 1076 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1077 1078 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1079 SOF_TIMESTAMPING_TX_HARDWARE | 1080 SOF_TIMESTAMPING_RX_SOFTWARE | 1081 SOF_TIMESTAMPING_RX_HARDWARE | 1082 SOF_TIMESTAMPING_SOFTWARE | 1083 SOF_TIMESTAMPING_RAW_HARDWARE; 1084 1085 if (priv->ptp_clock) 1086 info->phc_index = ptp_clock_index(priv->ptp_clock); 1087 1088 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1089 1090 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1091 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1092 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1093 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1094 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1095 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1096 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1097 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1098 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1099 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1100 (1 << HWTSTAMP_FILTER_ALL)); 1101 return 0; 1102 } else 1103 return ethtool_op_get_ts_info(dev, info); 1104 } 1105 1106 static int stmmac_get_tunable(struct net_device *dev, 1107 const struct ethtool_tunable *tuna, void *data) 1108 { 1109 struct stmmac_priv *priv = netdev_priv(dev); 1110 int ret = 0; 1111 1112 switch (tuna->id) { 1113 case ETHTOOL_RX_COPYBREAK: 1114 *(u32 *)data = priv->rx_copybreak; 1115 break; 1116 default: 1117 ret = -EINVAL; 1118 break; 1119 } 1120 1121 return ret; 1122 } 1123 1124 static int stmmac_set_tunable(struct net_device *dev, 1125 const struct ethtool_tunable *tuna, 1126 const void *data) 1127 { 1128 struct stmmac_priv *priv = netdev_priv(dev); 1129 int ret = 0; 1130 1131 switch (tuna->id) { 1132 case ETHTOOL_RX_COPYBREAK: 1133 priv->rx_copybreak = *(u32 *)data; 1134 break; 1135 default: 1136 ret = -EINVAL; 1137 break; 1138 } 1139 1140 return ret; 1141 } 1142 1143 static const struct ethtool_ops stmmac_ethtool_ops = { 1144 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1145 ETHTOOL_COALESCE_MAX_FRAMES, 1146 .begin = stmmac_check_if_running, 1147 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1148 .get_msglevel = stmmac_ethtool_getmsglevel, 1149 .set_msglevel = stmmac_ethtool_setmsglevel, 1150 .get_regs = stmmac_ethtool_gregs, 1151 .get_regs_len = stmmac_ethtool_get_regs_len, 1152 .get_link = ethtool_op_get_link, 1153 .nway_reset = stmmac_nway_reset, 1154 .get_ringparam = stmmac_get_ringparam, 1155 .set_ringparam = stmmac_set_ringparam, 1156 .get_pauseparam = stmmac_get_pauseparam, 1157 .set_pauseparam = stmmac_set_pauseparam, 1158 .self_test = stmmac_selftest_run, 1159 .get_ethtool_stats = stmmac_get_ethtool_stats, 1160 .get_strings = stmmac_get_strings, 1161 .get_wol = stmmac_get_wol, 1162 .set_wol = stmmac_set_wol, 1163 .get_eee = stmmac_ethtool_op_get_eee, 1164 .set_eee = stmmac_ethtool_op_set_eee, 1165 .get_sset_count = stmmac_get_sset_count, 1166 .get_rxnfc = stmmac_get_rxnfc, 1167 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1168 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1169 .get_rxfh = stmmac_get_rxfh, 1170 .set_rxfh = stmmac_set_rxfh, 1171 .get_ts_info = stmmac_get_ts_info, 1172 .get_coalesce = stmmac_get_coalesce, 1173 .set_coalesce = stmmac_set_coalesce, 1174 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1175 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1176 .get_channels = stmmac_get_channels, 1177 .set_channels = stmmac_set_channels, 1178 .get_tunable = stmmac_get_tunable, 1179 .set_tunable = stmmac_set_tunable, 1180 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1181 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1182 }; 1183 1184 void stmmac_set_ethtool_ops(struct net_device *netdev) 1185 { 1186 netdev->ethtool_ops = &stmmac_ethtool_ops; 1187 } 1188