1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define GMAC4_REG_SPACE_SIZE 0x116C 25 #define MAC100_ETHTOOL_NAME "st_mac100" 26 #define GMAC_ETHTOOL_NAME "st_gmac" 27 #define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* EST */ 159 STMMAC_STAT(mtl_est_cgce), 160 STMMAC_STAT(mtl_est_hlbs), 161 STMMAC_STAT(mtl_est_hlbf), 162 STMMAC_STAT(mtl_est_btre), 163 STMMAC_STAT(mtl_est_btrlm), 164 }; 165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 166 167 /* statistics collected in queue which will be summed up for all TX or RX 168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 169 */ 170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 171 "rx_pkt_n", 172 "rx_normal_irq_n", 173 "tx_pkt_n", 174 "tx_normal_irq_n", 175 "tx_clean", 176 "tx_set_ic_bit", 177 "tx_tso_frames", 178 "tx_tso_nfrags", 179 "normal_irq_n", 180 "napi_poll", 181 }; 182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 183 184 /* HW MAC Management counters (if supported) */ 185 #define STMMAC_MMC_STAT(m) \ 186 { #m, sizeof_field(struct stmmac_counters, m), \ 187 offsetof(struct stmmac_priv, mmc.m)} 188 189 static const struct stmmac_stats stmmac_mmc[] = { 190 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 191 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 192 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 193 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 195 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 201 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 203 STMMAC_MMC_STAT(mmc_tx_underflow_error), 204 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 205 STMMAC_MMC_STAT(mmc_tx_multicol_g), 206 STMMAC_MMC_STAT(mmc_tx_deferred), 207 STMMAC_MMC_STAT(mmc_tx_latecol), 208 STMMAC_MMC_STAT(mmc_tx_exesscol), 209 STMMAC_MMC_STAT(mmc_tx_carrier_error), 210 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 211 STMMAC_MMC_STAT(mmc_tx_framecount_g), 212 STMMAC_MMC_STAT(mmc_tx_excessdef), 213 STMMAC_MMC_STAT(mmc_tx_pause_frame), 214 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 215 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 216 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 217 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 218 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 219 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 220 STMMAC_MMC_STAT(mmc_rx_crc_error), 221 STMMAC_MMC_STAT(mmc_rx_align_error), 222 STMMAC_MMC_STAT(mmc_rx_run_error), 223 STMMAC_MMC_STAT(mmc_rx_jabber_error), 224 STMMAC_MMC_STAT(mmc_rx_undersize_g), 225 STMMAC_MMC_STAT(mmc_rx_oversize_g), 226 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 227 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 228 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 229 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 230 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_unicast_g), 233 STMMAC_MMC_STAT(mmc_rx_length_error), 234 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 235 STMMAC_MMC_STAT(mmc_rx_pause_frames), 236 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 237 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 238 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 239 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 240 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 241 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 242 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 243 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 244 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 245 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 246 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 247 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 248 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 251 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 253 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 254 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 255 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 256 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 257 STMMAC_MMC_STAT(mmc_rx_udp_gd), 258 STMMAC_MMC_STAT(mmc_rx_udp_err), 259 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 260 STMMAC_MMC_STAT(mmc_rx_tcp_err), 261 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 262 STMMAC_MMC_STAT(mmc_rx_icmp_err), 263 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 264 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 265 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 266 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 267 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 268 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 269 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 270 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 271 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 272 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 273 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 274 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 275 }; 276 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 277 278 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 279 "tx_pkt_n", 280 "tx_irq_n", 281 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 282 }; 283 284 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 285 "rx_pkt_n", 286 "rx_irq_n", 287 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 288 }; 289 290 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 291 struct ethtool_drvinfo *info) 292 { 293 struct stmmac_priv *priv = netdev_priv(dev); 294 295 if (priv->plat->has_gmac || priv->plat->has_gmac4) 296 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 297 else if (priv->plat->has_xgmac) 298 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 299 else 300 strscpy(info->driver, MAC100_ETHTOOL_NAME, 301 sizeof(info->driver)); 302 303 if (priv->plat->pdev) { 304 strscpy(info->bus_info, pci_name(priv->plat->pdev), 305 sizeof(info->bus_info)); 306 } 307 } 308 309 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 310 struct ethtool_link_ksettings *cmd) 311 { 312 struct stmmac_priv *priv = netdev_priv(dev); 313 314 if (priv->hw->pcs & STMMAC_PCS_RGMII || 315 priv->hw->pcs & STMMAC_PCS_SGMII) { 316 struct rgmii_adv adv; 317 u32 supported, advertising, lp_advertising; 318 319 if (!priv->xstats.pcs_link) { 320 cmd->base.speed = SPEED_UNKNOWN; 321 cmd->base.duplex = DUPLEX_UNKNOWN; 322 return 0; 323 } 324 cmd->base.duplex = priv->xstats.pcs_duplex; 325 326 cmd->base.speed = priv->xstats.pcs_speed; 327 328 /* Get and convert ADV/LP_ADV from the HW AN registers */ 329 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 330 return -EOPNOTSUPP; /* should never happen indeed */ 331 332 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 333 334 ethtool_convert_link_mode_to_legacy_u32( 335 &supported, cmd->link_modes.supported); 336 ethtool_convert_link_mode_to_legacy_u32( 337 &advertising, cmd->link_modes.advertising); 338 ethtool_convert_link_mode_to_legacy_u32( 339 &lp_advertising, cmd->link_modes.lp_advertising); 340 341 if (adv.pause & STMMAC_PCS_PAUSE) 342 advertising |= ADVERTISED_Pause; 343 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 344 advertising |= ADVERTISED_Asym_Pause; 345 if (adv.lp_pause & STMMAC_PCS_PAUSE) 346 lp_advertising |= ADVERTISED_Pause; 347 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 348 lp_advertising |= ADVERTISED_Asym_Pause; 349 350 /* Reg49[3] always set because ANE is always supported */ 351 cmd->base.autoneg = ADVERTISED_Autoneg; 352 supported |= SUPPORTED_Autoneg; 353 advertising |= ADVERTISED_Autoneg; 354 lp_advertising |= ADVERTISED_Autoneg; 355 356 if (adv.duplex) { 357 supported |= (SUPPORTED_1000baseT_Full | 358 SUPPORTED_100baseT_Full | 359 SUPPORTED_10baseT_Full); 360 advertising |= (ADVERTISED_1000baseT_Full | 361 ADVERTISED_100baseT_Full | 362 ADVERTISED_10baseT_Full); 363 } else { 364 supported |= (SUPPORTED_1000baseT_Half | 365 SUPPORTED_100baseT_Half | 366 SUPPORTED_10baseT_Half); 367 advertising |= (ADVERTISED_1000baseT_Half | 368 ADVERTISED_100baseT_Half | 369 ADVERTISED_10baseT_Half); 370 } 371 if (adv.lp_duplex) 372 lp_advertising |= (ADVERTISED_1000baseT_Full | 373 ADVERTISED_100baseT_Full | 374 ADVERTISED_10baseT_Full); 375 else 376 lp_advertising |= (ADVERTISED_1000baseT_Half | 377 ADVERTISED_100baseT_Half | 378 ADVERTISED_10baseT_Half); 379 cmd->base.port = PORT_OTHER; 380 381 ethtool_convert_legacy_u32_to_link_mode( 382 cmd->link_modes.supported, supported); 383 ethtool_convert_legacy_u32_to_link_mode( 384 cmd->link_modes.advertising, advertising); 385 ethtool_convert_legacy_u32_to_link_mode( 386 cmd->link_modes.lp_advertising, lp_advertising); 387 388 return 0; 389 } 390 391 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 392 } 393 394 static int 395 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 396 const struct ethtool_link_ksettings *cmd) 397 { 398 struct stmmac_priv *priv = netdev_priv(dev); 399 400 if (priv->hw->pcs & STMMAC_PCS_RGMII || 401 priv->hw->pcs & STMMAC_PCS_SGMII) { 402 /* Only support ANE */ 403 if (cmd->base.autoneg != AUTONEG_ENABLE) 404 return -EINVAL; 405 406 mutex_lock(&priv->lock); 407 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 408 mutex_unlock(&priv->lock); 409 410 return 0; 411 } 412 413 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 414 } 415 416 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 417 { 418 struct stmmac_priv *priv = netdev_priv(dev); 419 return priv->msg_enable; 420 } 421 422 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 423 { 424 struct stmmac_priv *priv = netdev_priv(dev); 425 priv->msg_enable = level; 426 427 } 428 429 static int stmmac_check_if_running(struct net_device *dev) 430 { 431 if (!netif_running(dev)) 432 return -EBUSY; 433 return 0; 434 } 435 436 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 437 { 438 struct stmmac_priv *priv = netdev_priv(dev); 439 440 if (priv->plat->has_xgmac) 441 return XGMAC_REGSIZE * 4; 442 else if (priv->plat->has_gmac4) 443 return GMAC4_REG_SPACE_SIZE; 444 return REG_SPACE_SIZE; 445 } 446 447 static void stmmac_ethtool_gregs(struct net_device *dev, 448 struct ethtool_regs *regs, void *space) 449 { 450 struct stmmac_priv *priv = netdev_priv(dev); 451 u32 *reg_space = (u32 *) space; 452 453 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 454 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 455 456 /* Copy DMA registers to where ethtool expects them */ 457 if (priv->plat->has_gmac4) { 458 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 459 memcpy(®_space[ETHTOOL_DMA_OFFSET], 460 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 461 NUM_DWMAC4_DMA_REGS * 4); 462 } else if (!priv->plat->has_xgmac) { 463 memcpy(®_space[ETHTOOL_DMA_OFFSET], 464 ®_space[DMA_BUS_MODE / 4], 465 NUM_DWMAC1000_DMA_REGS * 4); 466 } 467 } 468 469 static int stmmac_nway_reset(struct net_device *dev) 470 { 471 struct stmmac_priv *priv = netdev_priv(dev); 472 473 return phylink_ethtool_nway_reset(priv->phylink); 474 } 475 476 static void stmmac_get_ringparam(struct net_device *netdev, 477 struct ethtool_ringparam *ring, 478 struct kernel_ethtool_ringparam *kernel_ring, 479 struct netlink_ext_ack *extack) 480 { 481 struct stmmac_priv *priv = netdev_priv(netdev); 482 483 ring->rx_max_pending = DMA_MAX_RX_SIZE; 484 ring->tx_max_pending = DMA_MAX_TX_SIZE; 485 ring->rx_pending = priv->dma_conf.dma_rx_size; 486 ring->tx_pending = priv->dma_conf.dma_tx_size; 487 } 488 489 static int stmmac_set_ringparam(struct net_device *netdev, 490 struct ethtool_ringparam *ring, 491 struct kernel_ethtool_ringparam *kernel_ring, 492 struct netlink_ext_ack *extack) 493 { 494 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 495 ring->rx_pending < DMA_MIN_RX_SIZE || 496 ring->rx_pending > DMA_MAX_RX_SIZE || 497 !is_power_of_2(ring->rx_pending) || 498 ring->tx_pending < DMA_MIN_TX_SIZE || 499 ring->tx_pending > DMA_MAX_TX_SIZE || 500 !is_power_of_2(ring->tx_pending)) 501 return -EINVAL; 502 503 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 504 ring->tx_pending); 505 } 506 507 static void 508 stmmac_get_pauseparam(struct net_device *netdev, 509 struct ethtool_pauseparam *pause) 510 { 511 struct stmmac_priv *priv = netdev_priv(netdev); 512 struct rgmii_adv adv_lp; 513 514 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 515 pause->autoneg = 1; 516 if (!adv_lp.pause) 517 return; 518 } else { 519 phylink_ethtool_get_pauseparam(priv->phylink, pause); 520 } 521 } 522 523 static int 524 stmmac_set_pauseparam(struct net_device *netdev, 525 struct ethtool_pauseparam *pause) 526 { 527 struct stmmac_priv *priv = netdev_priv(netdev); 528 struct rgmii_adv adv_lp; 529 530 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 531 pause->autoneg = 1; 532 if (!adv_lp.pause) 533 return -EOPNOTSUPP; 534 return 0; 535 } else { 536 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 537 } 538 } 539 540 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 541 { 542 u32 tx_cnt = priv->plat->tx_queues_to_use; 543 u32 rx_cnt = priv->plat->rx_queues_to_use; 544 unsigned int start; 545 int q, stat; 546 u64 *pos; 547 char *p; 548 549 pos = data; 550 for (q = 0; q < tx_cnt; q++) { 551 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[q]; 552 struct stmmac_txq_stats snapshot; 553 554 data = pos; 555 do { 556 start = u64_stats_fetch_begin(&tx_q->txq_stats.syncp); 557 snapshot = tx_q->txq_stats; 558 } while (u64_stats_fetch_retry(&tx_q->txq_stats.syncp, start)); 559 560 p = (char *)&snapshot + offsetof(struct stmmac_txq_stats, tx_pkt_n); 561 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 562 *data++ += (*(u64 *)p); 563 p += sizeof(u64); 564 } 565 } 566 567 pos = data; 568 for (q = 0; q < rx_cnt; q++) { 569 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[q]; 570 struct stmmac_rxq_stats snapshot; 571 572 data = pos; 573 do { 574 start = u64_stats_fetch_begin(&rx_q->rxq_stats.syncp); 575 snapshot = rx_q->rxq_stats; 576 } while (u64_stats_fetch_retry(&rx_q->rxq_stats.syncp, start)); 577 578 p = (char *)&snapshot + offsetof(struct stmmac_rxq_stats, rx_pkt_n); 579 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 580 *data++ += (*(u64 *)p); 581 p += sizeof(u64); 582 } 583 } 584 } 585 586 static void stmmac_get_ethtool_stats(struct net_device *dev, 587 struct ethtool_stats *dummy, u64 *data) 588 { 589 struct stmmac_priv *priv = netdev_priv(dev); 590 u32 rx_queues_count = priv->plat->rx_queues_to_use; 591 u32 tx_queues_count = priv->plat->tx_queues_to_use; 592 u64 napi_poll = 0, normal_irq_n = 0; 593 int i, j = 0, pos, ret; 594 unsigned long count; 595 unsigned int start; 596 597 if (priv->dma_cap.asp) { 598 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 599 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 600 &count, NULL)) 601 data[j++] = count; 602 } 603 } 604 605 /* Update the DMA HW counters for dwmac10/100 */ 606 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 607 if (ret) { 608 /* If supported, for new GMAC chips expose the MMC counters */ 609 if (priv->dma_cap.rmon) { 610 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 611 612 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 613 char *p; 614 p = (char *)priv + stmmac_mmc[i].stat_offset; 615 616 data[j++] = (stmmac_mmc[i].sizeof_stat == 617 sizeof(u64)) ? (*(u64 *)p) : 618 (*(u32 *)p); 619 } 620 } 621 if (priv->eee_enabled) { 622 int val = phylink_get_eee_err(priv->phylink); 623 if (val) 624 priv->xstats.phy_eee_wakeup_error_n = val; 625 } 626 627 if (priv->synopsys_id >= DWMAC_CORE_3_50) 628 stmmac_mac_debug(priv, priv->ioaddr, 629 (void *)&priv->xstats, 630 rx_queues_count, tx_queues_count); 631 } 632 for (i = 0; i < STMMAC_STATS_LEN; i++) { 633 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 634 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 635 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 636 } 637 638 pos = j; 639 for (i = 0; i < rx_queues_count; i++) { 640 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[i]; 641 struct stmmac_rxq_stats snapshot; 642 643 j = pos; 644 do { 645 start = u64_stats_fetch_begin(&rx_q->rxq_stats.syncp); 646 snapshot = rx_q->rxq_stats; 647 } while (u64_stats_fetch_retry(&rx_q->rxq_stats.syncp, start)); 648 649 data[j++] += snapshot.rx_pkt_n; 650 data[j++] += snapshot.rx_normal_irq_n; 651 normal_irq_n += snapshot.rx_normal_irq_n; 652 napi_poll += snapshot.napi_poll; 653 } 654 655 pos = j; 656 for (i = 0; i < tx_queues_count; i++) { 657 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[i]; 658 struct stmmac_txq_stats snapshot; 659 660 j = pos; 661 do { 662 start = u64_stats_fetch_begin(&tx_q->txq_stats.syncp); 663 snapshot = tx_q->txq_stats; 664 } while (u64_stats_fetch_retry(&tx_q->txq_stats.syncp, start)); 665 666 data[j++] += snapshot.tx_pkt_n; 667 data[j++] += snapshot.tx_normal_irq_n; 668 normal_irq_n += snapshot.tx_normal_irq_n; 669 data[j++] += snapshot.tx_clean; 670 data[j++] += snapshot.tx_set_ic_bit; 671 data[j++] += snapshot.tx_tso_frames; 672 data[j++] += snapshot.tx_tso_nfrags; 673 napi_poll += snapshot.napi_poll; 674 } 675 normal_irq_n += priv->xstats.rx_early_irq; 676 data[j++] = normal_irq_n; 677 data[j++] = napi_poll; 678 679 stmmac_get_per_qstats(priv, &data[j]); 680 } 681 682 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 683 { 684 struct stmmac_priv *priv = netdev_priv(netdev); 685 u32 tx_cnt = priv->plat->tx_queues_to_use; 686 u32 rx_cnt = priv->plat->rx_queues_to_use; 687 int i, len, safety_len = 0; 688 689 switch (sset) { 690 case ETH_SS_STATS: 691 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 692 STMMAC_TXQ_STATS * tx_cnt + 693 STMMAC_RXQ_STATS * rx_cnt; 694 695 if (priv->dma_cap.rmon) 696 len += STMMAC_MMC_STATS_LEN; 697 if (priv->dma_cap.asp) { 698 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 699 if (!stmmac_safety_feat_dump(priv, 700 &priv->sstats, i, 701 NULL, NULL)) 702 safety_len++; 703 } 704 705 len += safety_len; 706 } 707 708 return len; 709 case ETH_SS_TEST: 710 return stmmac_selftest_get_count(priv); 711 default: 712 return -EOPNOTSUPP; 713 } 714 } 715 716 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 717 { 718 u32 tx_cnt = priv->plat->tx_queues_to_use; 719 u32 rx_cnt = priv->plat->rx_queues_to_use; 720 int q, stat; 721 722 for (q = 0; q < tx_cnt; q++) { 723 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 724 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 725 stmmac_qstats_tx_string[stat]); 726 data += ETH_GSTRING_LEN; 727 } 728 } 729 for (q = 0; q < rx_cnt; q++) { 730 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 731 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 732 stmmac_qstats_rx_string[stat]); 733 data += ETH_GSTRING_LEN; 734 } 735 } 736 } 737 738 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 739 { 740 int i; 741 u8 *p = data; 742 struct stmmac_priv *priv = netdev_priv(dev); 743 744 switch (stringset) { 745 case ETH_SS_STATS: 746 if (priv->dma_cap.asp) { 747 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 748 const char *desc; 749 if (!stmmac_safety_feat_dump(priv, 750 &priv->sstats, i, 751 NULL, &desc)) { 752 memcpy(p, desc, ETH_GSTRING_LEN); 753 p += ETH_GSTRING_LEN; 754 } 755 } 756 } 757 if (priv->dma_cap.rmon) 758 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 759 memcpy(p, stmmac_mmc[i].stat_string, 760 ETH_GSTRING_LEN); 761 p += ETH_GSTRING_LEN; 762 } 763 for (i = 0; i < STMMAC_STATS_LEN; i++) { 764 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 765 p += ETH_GSTRING_LEN; 766 } 767 for (i = 0; i < STMMAC_QSTATS; i++) { 768 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 769 p += ETH_GSTRING_LEN; 770 } 771 stmmac_get_qstats_string(priv, p); 772 break; 773 case ETH_SS_TEST: 774 stmmac_selftest_get_strings(priv, p); 775 break; 776 default: 777 WARN_ON(1); 778 break; 779 } 780 } 781 782 /* Currently only support WOL through Magic packet. */ 783 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 784 { 785 struct stmmac_priv *priv = netdev_priv(dev); 786 787 if (!priv->plat->pmt) 788 return phylink_ethtool_get_wol(priv->phylink, wol); 789 790 mutex_lock(&priv->lock); 791 if (device_can_wakeup(priv->device)) { 792 wol->supported = WAKE_MAGIC | WAKE_UCAST; 793 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 794 wol->supported &= ~WAKE_MAGIC; 795 wol->wolopts = priv->wolopts; 796 } 797 mutex_unlock(&priv->lock); 798 } 799 800 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 801 { 802 struct stmmac_priv *priv = netdev_priv(dev); 803 u32 support = WAKE_MAGIC | WAKE_UCAST; 804 805 if (!device_can_wakeup(priv->device)) 806 return -EOPNOTSUPP; 807 808 if (!priv->plat->pmt) { 809 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 810 811 if (!ret) 812 device_set_wakeup_enable(priv->device, !!wol->wolopts); 813 return ret; 814 } 815 816 /* By default almost all GMAC devices support the WoL via 817 * magic frame but we can disable it if the HW capability 818 * register shows no support for pmt_magic_frame. */ 819 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 820 wol->wolopts &= ~WAKE_MAGIC; 821 822 if (wol->wolopts & ~support) 823 return -EINVAL; 824 825 if (wol->wolopts) { 826 pr_info("stmmac: wakeup enable\n"); 827 device_set_wakeup_enable(priv->device, 1); 828 enable_irq_wake(priv->wol_irq); 829 } else { 830 device_set_wakeup_enable(priv->device, 0); 831 disable_irq_wake(priv->wol_irq); 832 } 833 834 mutex_lock(&priv->lock); 835 priv->wolopts = wol->wolopts; 836 mutex_unlock(&priv->lock); 837 838 return 0; 839 } 840 841 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 842 struct ethtool_eee *edata) 843 { 844 struct stmmac_priv *priv = netdev_priv(dev); 845 846 if (!priv->dma_cap.eee) 847 return -EOPNOTSUPP; 848 849 edata->eee_enabled = priv->eee_enabled; 850 edata->eee_active = priv->eee_active; 851 edata->tx_lpi_timer = priv->tx_lpi_timer; 852 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 853 854 return phylink_ethtool_get_eee(priv->phylink, edata); 855 } 856 857 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 858 struct ethtool_eee *edata) 859 { 860 struct stmmac_priv *priv = netdev_priv(dev); 861 int ret; 862 863 if (!priv->dma_cap.eee) 864 return -EOPNOTSUPP; 865 866 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 867 netdev_warn(priv->dev, 868 "Setting EEE tx-lpi is not supported\n"); 869 870 if (!edata->eee_enabled) 871 stmmac_disable_eee_mode(priv); 872 873 ret = phylink_ethtool_set_eee(priv->phylink, edata); 874 if (ret) 875 return ret; 876 877 if (edata->eee_enabled && 878 priv->tx_lpi_timer != edata->tx_lpi_timer) { 879 priv->tx_lpi_timer = edata->tx_lpi_timer; 880 stmmac_eee_init(priv); 881 } 882 883 return 0; 884 } 885 886 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 887 { 888 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 889 890 if (!clk) { 891 clk = priv->plat->clk_ref_rate; 892 if (!clk) 893 return 0; 894 } 895 896 return (usec * (clk / 1000000)) / 256; 897 } 898 899 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 900 { 901 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 902 903 if (!clk) { 904 clk = priv->plat->clk_ref_rate; 905 if (!clk) 906 return 0; 907 } 908 909 return (riwt * 256) / (clk / 1000000); 910 } 911 912 static int __stmmac_get_coalesce(struct net_device *dev, 913 struct ethtool_coalesce *ec, 914 int queue) 915 { 916 struct stmmac_priv *priv = netdev_priv(dev); 917 u32 max_cnt; 918 u32 rx_cnt; 919 u32 tx_cnt; 920 921 rx_cnt = priv->plat->rx_queues_to_use; 922 tx_cnt = priv->plat->tx_queues_to_use; 923 max_cnt = max(rx_cnt, tx_cnt); 924 925 if (queue < 0) 926 queue = 0; 927 else if (queue >= max_cnt) 928 return -EINVAL; 929 930 if (queue < tx_cnt) { 931 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 932 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 933 } else { 934 ec->tx_coalesce_usecs = 0; 935 ec->tx_max_coalesced_frames = 0; 936 } 937 938 if (priv->use_riwt && queue < rx_cnt) { 939 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 940 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 941 priv); 942 } else { 943 ec->rx_max_coalesced_frames = 0; 944 ec->rx_coalesce_usecs = 0; 945 } 946 947 return 0; 948 } 949 950 static int stmmac_get_coalesce(struct net_device *dev, 951 struct ethtool_coalesce *ec, 952 struct kernel_ethtool_coalesce *kernel_coal, 953 struct netlink_ext_ack *extack) 954 { 955 return __stmmac_get_coalesce(dev, ec, -1); 956 } 957 958 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 959 struct ethtool_coalesce *ec) 960 { 961 return __stmmac_get_coalesce(dev, ec, queue); 962 } 963 964 static int __stmmac_set_coalesce(struct net_device *dev, 965 struct ethtool_coalesce *ec, 966 int queue) 967 { 968 struct stmmac_priv *priv = netdev_priv(dev); 969 bool all_queues = false; 970 unsigned int rx_riwt; 971 u32 max_cnt; 972 u32 rx_cnt; 973 u32 tx_cnt; 974 975 rx_cnt = priv->plat->rx_queues_to_use; 976 tx_cnt = priv->plat->tx_queues_to_use; 977 max_cnt = max(rx_cnt, tx_cnt); 978 979 if (queue < 0) 980 all_queues = true; 981 else if (queue >= max_cnt) 982 return -EINVAL; 983 984 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 985 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 986 987 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 988 return -EINVAL; 989 990 if (all_queues) { 991 int i; 992 993 for (i = 0; i < rx_cnt; i++) { 994 priv->rx_riwt[i] = rx_riwt; 995 stmmac_rx_watchdog(priv, priv->ioaddr, 996 rx_riwt, i); 997 priv->rx_coal_frames[i] = 998 ec->rx_max_coalesced_frames; 999 } 1000 } else if (queue < rx_cnt) { 1001 priv->rx_riwt[queue] = rx_riwt; 1002 stmmac_rx_watchdog(priv, priv->ioaddr, 1003 rx_riwt, queue); 1004 priv->rx_coal_frames[queue] = 1005 ec->rx_max_coalesced_frames; 1006 } 1007 } 1008 1009 if ((ec->tx_coalesce_usecs == 0) && 1010 (ec->tx_max_coalesced_frames == 0)) 1011 return -EINVAL; 1012 1013 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 1014 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 1015 return -EINVAL; 1016 1017 if (all_queues) { 1018 int i; 1019 1020 for (i = 0; i < tx_cnt; i++) { 1021 priv->tx_coal_frames[i] = 1022 ec->tx_max_coalesced_frames; 1023 priv->tx_coal_timer[i] = 1024 ec->tx_coalesce_usecs; 1025 } 1026 } else if (queue < tx_cnt) { 1027 priv->tx_coal_frames[queue] = 1028 ec->tx_max_coalesced_frames; 1029 priv->tx_coal_timer[queue] = 1030 ec->tx_coalesce_usecs; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int stmmac_set_coalesce(struct net_device *dev, 1037 struct ethtool_coalesce *ec, 1038 struct kernel_ethtool_coalesce *kernel_coal, 1039 struct netlink_ext_ack *extack) 1040 { 1041 return __stmmac_set_coalesce(dev, ec, -1); 1042 } 1043 1044 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1045 struct ethtool_coalesce *ec) 1046 { 1047 return __stmmac_set_coalesce(dev, ec, queue); 1048 } 1049 1050 static int stmmac_get_rxnfc(struct net_device *dev, 1051 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1052 { 1053 struct stmmac_priv *priv = netdev_priv(dev); 1054 1055 switch (rxnfc->cmd) { 1056 case ETHTOOL_GRXRINGS: 1057 rxnfc->data = priv->plat->rx_queues_to_use; 1058 break; 1059 default: 1060 return -EOPNOTSUPP; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 1067 { 1068 struct stmmac_priv *priv = netdev_priv(dev); 1069 1070 return sizeof(priv->rss.key); 1071 } 1072 1073 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1074 { 1075 struct stmmac_priv *priv = netdev_priv(dev); 1076 1077 return ARRAY_SIZE(priv->rss.table); 1078 } 1079 1080 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1081 u8 *hfunc) 1082 { 1083 struct stmmac_priv *priv = netdev_priv(dev); 1084 int i; 1085 1086 if (indir) { 1087 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1088 indir[i] = priv->rss.table[i]; 1089 } 1090 1091 if (key) 1092 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 1093 if (hfunc) 1094 *hfunc = ETH_RSS_HASH_TOP; 1095 1096 return 0; 1097 } 1098 1099 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 1100 const u8 *key, const u8 hfunc) 1101 { 1102 struct stmmac_priv *priv = netdev_priv(dev); 1103 int i; 1104 1105 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 1106 return -EOPNOTSUPP; 1107 1108 if (indir) { 1109 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1110 priv->rss.table[i] = indir[i]; 1111 } 1112 1113 if (key) 1114 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 1115 1116 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1117 priv->plat->rx_queues_to_use); 1118 } 1119 1120 static void stmmac_get_channels(struct net_device *dev, 1121 struct ethtool_channels *chan) 1122 { 1123 struct stmmac_priv *priv = netdev_priv(dev); 1124 1125 chan->rx_count = priv->plat->rx_queues_to_use; 1126 chan->tx_count = priv->plat->tx_queues_to_use; 1127 chan->max_rx = priv->dma_cap.number_rx_queues; 1128 chan->max_tx = priv->dma_cap.number_tx_queues; 1129 } 1130 1131 static int stmmac_set_channels(struct net_device *dev, 1132 struct ethtool_channels *chan) 1133 { 1134 struct stmmac_priv *priv = netdev_priv(dev); 1135 1136 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1137 chan->tx_count > priv->dma_cap.number_tx_queues || 1138 !chan->rx_count || !chan->tx_count) 1139 return -EINVAL; 1140 1141 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1142 } 1143 1144 static int stmmac_get_ts_info(struct net_device *dev, 1145 struct ethtool_ts_info *info) 1146 { 1147 struct stmmac_priv *priv = netdev_priv(dev); 1148 1149 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1150 1151 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1152 SOF_TIMESTAMPING_TX_HARDWARE | 1153 SOF_TIMESTAMPING_RX_SOFTWARE | 1154 SOF_TIMESTAMPING_RX_HARDWARE | 1155 SOF_TIMESTAMPING_SOFTWARE | 1156 SOF_TIMESTAMPING_RAW_HARDWARE; 1157 1158 if (priv->ptp_clock) 1159 info->phc_index = ptp_clock_index(priv->ptp_clock); 1160 1161 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1162 1163 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1164 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1165 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1166 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1167 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1168 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1170 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1171 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1172 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1173 (1 << HWTSTAMP_FILTER_ALL)); 1174 return 0; 1175 } else 1176 return ethtool_op_get_ts_info(dev, info); 1177 } 1178 1179 static int stmmac_get_tunable(struct net_device *dev, 1180 const struct ethtool_tunable *tuna, void *data) 1181 { 1182 struct stmmac_priv *priv = netdev_priv(dev); 1183 int ret = 0; 1184 1185 switch (tuna->id) { 1186 case ETHTOOL_RX_COPYBREAK: 1187 *(u32 *)data = priv->rx_copybreak; 1188 break; 1189 default: 1190 ret = -EINVAL; 1191 break; 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int stmmac_set_tunable(struct net_device *dev, 1198 const struct ethtool_tunable *tuna, 1199 const void *data) 1200 { 1201 struct stmmac_priv *priv = netdev_priv(dev); 1202 int ret = 0; 1203 1204 switch (tuna->id) { 1205 case ETHTOOL_RX_COPYBREAK: 1206 priv->rx_copybreak = *(u32 *)data; 1207 break; 1208 default: 1209 ret = -EINVAL; 1210 break; 1211 } 1212 1213 return ret; 1214 } 1215 1216 static const struct ethtool_ops stmmac_ethtool_ops = { 1217 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1218 ETHTOOL_COALESCE_MAX_FRAMES, 1219 .begin = stmmac_check_if_running, 1220 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1221 .get_msglevel = stmmac_ethtool_getmsglevel, 1222 .set_msglevel = stmmac_ethtool_setmsglevel, 1223 .get_regs = stmmac_ethtool_gregs, 1224 .get_regs_len = stmmac_ethtool_get_regs_len, 1225 .get_link = ethtool_op_get_link, 1226 .nway_reset = stmmac_nway_reset, 1227 .get_ringparam = stmmac_get_ringparam, 1228 .set_ringparam = stmmac_set_ringparam, 1229 .get_pauseparam = stmmac_get_pauseparam, 1230 .set_pauseparam = stmmac_set_pauseparam, 1231 .self_test = stmmac_selftest_run, 1232 .get_ethtool_stats = stmmac_get_ethtool_stats, 1233 .get_strings = stmmac_get_strings, 1234 .get_wol = stmmac_get_wol, 1235 .set_wol = stmmac_set_wol, 1236 .get_eee = stmmac_ethtool_op_get_eee, 1237 .set_eee = stmmac_ethtool_op_set_eee, 1238 .get_sset_count = stmmac_get_sset_count, 1239 .get_rxnfc = stmmac_get_rxnfc, 1240 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1241 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1242 .get_rxfh = stmmac_get_rxfh, 1243 .set_rxfh = stmmac_set_rxfh, 1244 .get_ts_info = stmmac_get_ts_info, 1245 .get_coalesce = stmmac_get_coalesce, 1246 .set_coalesce = stmmac_set_coalesce, 1247 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1248 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1249 .get_channels = stmmac_get_channels, 1250 .set_channels = stmmac_set_channels, 1251 .get_tunable = stmmac_get_tunable, 1252 .set_tunable = stmmac_set_tunable, 1253 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1254 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1255 }; 1256 1257 void stmmac_set_ethtool_ops(struct net_device *netdev) 1258 { 1259 netdev->ethtool_ops = &stmmac_ethtool_ops; 1260 } 1261