1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define MAC100_ETHTOOL_NAME "st_mac100" 25 #define GMAC_ETHTOOL_NAME "st_gmac" 26 #define XGMAC_ETHTOOL_NAME "st_xgmac" 27 28 #define ETHTOOL_DMA_OFFSET 55 29 30 struct stmmac_stats { 31 char stat_string[ETH_GSTRING_LEN]; 32 int sizeof_stat; 33 int stat_offset; 34 }; 35 36 #define STMMAC_STAT(m) \ 37 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 38 offsetof(struct stmmac_priv, xstats.m)} 39 40 static const struct stmmac_stats stmmac_gstrings_stats[] = { 41 /* Transmit errors */ 42 STMMAC_STAT(tx_underflow), 43 STMMAC_STAT(tx_carrier), 44 STMMAC_STAT(tx_losscarrier), 45 STMMAC_STAT(vlan_tag), 46 STMMAC_STAT(tx_deferred), 47 STMMAC_STAT(tx_vlan), 48 STMMAC_STAT(tx_jabber), 49 STMMAC_STAT(tx_frame_flushed), 50 STMMAC_STAT(tx_payload_error), 51 STMMAC_STAT(tx_ip_header_error), 52 /* Receive errors */ 53 STMMAC_STAT(rx_desc), 54 STMMAC_STAT(sa_filter_fail), 55 STMMAC_STAT(overflow_error), 56 STMMAC_STAT(ipc_csum_error), 57 STMMAC_STAT(rx_collision), 58 STMMAC_STAT(rx_crc_errors), 59 STMMAC_STAT(dribbling_bit), 60 STMMAC_STAT(rx_length), 61 STMMAC_STAT(rx_mii), 62 STMMAC_STAT(rx_multicast), 63 STMMAC_STAT(rx_gmac_overflow), 64 STMMAC_STAT(rx_watchdog), 65 STMMAC_STAT(da_rx_filter_fail), 66 STMMAC_STAT(sa_rx_filter_fail), 67 STMMAC_STAT(rx_missed_cntr), 68 STMMAC_STAT(rx_overflow_cntr), 69 STMMAC_STAT(rx_vlan), 70 STMMAC_STAT(rx_split_hdr_pkt_n), 71 /* Tx/Rx IRQ error info */ 72 STMMAC_STAT(tx_undeflow_irq), 73 STMMAC_STAT(tx_process_stopped_irq), 74 STMMAC_STAT(tx_jabber_irq), 75 STMMAC_STAT(rx_overflow_irq), 76 STMMAC_STAT(rx_buf_unav_irq), 77 STMMAC_STAT(rx_process_stopped_irq), 78 STMMAC_STAT(rx_watchdog_irq), 79 STMMAC_STAT(tx_early_irq), 80 STMMAC_STAT(fatal_bus_error_irq), 81 /* Tx/Rx IRQ Events */ 82 STMMAC_STAT(rx_early_irq), 83 STMMAC_STAT(threshold), 84 STMMAC_STAT(tx_pkt_n), 85 STMMAC_STAT(rx_pkt_n), 86 STMMAC_STAT(normal_irq_n), 87 STMMAC_STAT(rx_normal_irq_n), 88 STMMAC_STAT(napi_poll), 89 STMMAC_STAT(tx_normal_irq_n), 90 STMMAC_STAT(tx_clean), 91 STMMAC_STAT(tx_set_ic_bit), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* TSO */ 159 STMMAC_STAT(tx_tso_frames), 160 STMMAC_STAT(tx_tso_nfrags), 161 }; 162 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 163 164 /* HW MAC Management counters (if supported) */ 165 #define STMMAC_MMC_STAT(m) \ 166 { #m, sizeof_field(struct stmmac_counters, m), \ 167 offsetof(struct stmmac_priv, mmc.m)} 168 169 static const struct stmmac_stats stmmac_mmc[] = { 170 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 171 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 172 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 173 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 174 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 175 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 176 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 177 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 178 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 179 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 180 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 181 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 182 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 183 STMMAC_MMC_STAT(mmc_tx_underflow_error), 184 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 185 STMMAC_MMC_STAT(mmc_tx_multicol_g), 186 STMMAC_MMC_STAT(mmc_tx_deferred), 187 STMMAC_MMC_STAT(mmc_tx_latecol), 188 STMMAC_MMC_STAT(mmc_tx_exesscol), 189 STMMAC_MMC_STAT(mmc_tx_carrier_error), 190 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 191 STMMAC_MMC_STAT(mmc_tx_framecount_g), 192 STMMAC_MMC_STAT(mmc_tx_excessdef), 193 STMMAC_MMC_STAT(mmc_tx_pause_frame), 194 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 195 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 196 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 197 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 198 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 199 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 200 STMMAC_MMC_STAT(mmc_rx_crc_error), 201 STMMAC_MMC_STAT(mmc_rx_align_error), 202 STMMAC_MMC_STAT(mmc_rx_run_error), 203 STMMAC_MMC_STAT(mmc_rx_jabber_error), 204 STMMAC_MMC_STAT(mmc_rx_undersize_g), 205 STMMAC_MMC_STAT(mmc_rx_oversize_g), 206 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 207 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 208 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 209 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 210 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 211 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 212 STMMAC_MMC_STAT(mmc_rx_unicast_g), 213 STMMAC_MMC_STAT(mmc_rx_length_error), 214 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 215 STMMAC_MMC_STAT(mmc_rx_pause_frames), 216 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 217 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 218 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 219 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 220 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 221 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 222 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 223 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 224 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 225 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 226 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 227 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 228 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 229 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 230 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 231 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 232 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 233 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 234 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 235 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 236 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 237 STMMAC_MMC_STAT(mmc_rx_udp_gd), 238 STMMAC_MMC_STAT(mmc_rx_udp_err), 239 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 240 STMMAC_MMC_STAT(mmc_rx_tcp_err), 241 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 242 STMMAC_MMC_STAT(mmc_rx_icmp_err), 243 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 244 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 245 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 246 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 247 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 248 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 249 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 250 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 251 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 252 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 253 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 254 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 255 }; 256 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 257 258 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 259 struct ethtool_drvinfo *info) 260 { 261 struct stmmac_priv *priv = netdev_priv(dev); 262 263 if (priv->plat->has_gmac || priv->plat->has_gmac4) 264 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 265 else if (priv->plat->has_xgmac) 266 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 267 else 268 strlcpy(info->driver, MAC100_ETHTOOL_NAME, 269 sizeof(info->driver)); 270 271 if (priv->plat->pdev) { 272 strlcpy(info->bus_info, pci_name(priv->plat->pdev), 273 sizeof(info->bus_info)); 274 } 275 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 276 } 277 278 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 279 struct ethtool_link_ksettings *cmd) 280 { 281 struct stmmac_priv *priv = netdev_priv(dev); 282 283 if (priv->hw->pcs & STMMAC_PCS_RGMII || 284 priv->hw->pcs & STMMAC_PCS_SGMII) { 285 struct rgmii_adv adv; 286 u32 supported, advertising, lp_advertising; 287 288 if (!priv->xstats.pcs_link) { 289 cmd->base.speed = SPEED_UNKNOWN; 290 cmd->base.duplex = DUPLEX_UNKNOWN; 291 return 0; 292 } 293 cmd->base.duplex = priv->xstats.pcs_duplex; 294 295 cmd->base.speed = priv->xstats.pcs_speed; 296 297 /* Get and convert ADV/LP_ADV from the HW AN registers */ 298 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 299 return -EOPNOTSUPP; /* should never happen indeed */ 300 301 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 302 303 ethtool_convert_link_mode_to_legacy_u32( 304 &supported, cmd->link_modes.supported); 305 ethtool_convert_link_mode_to_legacy_u32( 306 &advertising, cmd->link_modes.advertising); 307 ethtool_convert_link_mode_to_legacy_u32( 308 &lp_advertising, cmd->link_modes.lp_advertising); 309 310 if (adv.pause & STMMAC_PCS_PAUSE) 311 advertising |= ADVERTISED_Pause; 312 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 313 advertising |= ADVERTISED_Asym_Pause; 314 if (adv.lp_pause & STMMAC_PCS_PAUSE) 315 lp_advertising |= ADVERTISED_Pause; 316 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 317 lp_advertising |= ADVERTISED_Asym_Pause; 318 319 /* Reg49[3] always set because ANE is always supported */ 320 cmd->base.autoneg = ADVERTISED_Autoneg; 321 supported |= SUPPORTED_Autoneg; 322 advertising |= ADVERTISED_Autoneg; 323 lp_advertising |= ADVERTISED_Autoneg; 324 325 if (adv.duplex) { 326 supported |= (SUPPORTED_1000baseT_Full | 327 SUPPORTED_100baseT_Full | 328 SUPPORTED_10baseT_Full); 329 advertising |= (ADVERTISED_1000baseT_Full | 330 ADVERTISED_100baseT_Full | 331 ADVERTISED_10baseT_Full); 332 } else { 333 supported |= (SUPPORTED_1000baseT_Half | 334 SUPPORTED_100baseT_Half | 335 SUPPORTED_10baseT_Half); 336 advertising |= (ADVERTISED_1000baseT_Half | 337 ADVERTISED_100baseT_Half | 338 ADVERTISED_10baseT_Half); 339 } 340 if (adv.lp_duplex) 341 lp_advertising |= (ADVERTISED_1000baseT_Full | 342 ADVERTISED_100baseT_Full | 343 ADVERTISED_10baseT_Full); 344 else 345 lp_advertising |= (ADVERTISED_1000baseT_Half | 346 ADVERTISED_100baseT_Half | 347 ADVERTISED_10baseT_Half); 348 cmd->base.port = PORT_OTHER; 349 350 ethtool_convert_legacy_u32_to_link_mode( 351 cmd->link_modes.supported, supported); 352 ethtool_convert_legacy_u32_to_link_mode( 353 cmd->link_modes.advertising, advertising); 354 ethtool_convert_legacy_u32_to_link_mode( 355 cmd->link_modes.lp_advertising, lp_advertising); 356 357 return 0; 358 } 359 360 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 361 } 362 363 static int 364 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 365 const struct ethtool_link_ksettings *cmd) 366 { 367 struct stmmac_priv *priv = netdev_priv(dev); 368 369 if (priv->hw->pcs & STMMAC_PCS_RGMII || 370 priv->hw->pcs & STMMAC_PCS_SGMII) { 371 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; 372 373 /* Only support ANE */ 374 if (cmd->base.autoneg != AUTONEG_ENABLE) 375 return -EINVAL; 376 377 mask &= (ADVERTISED_1000baseT_Half | 378 ADVERTISED_1000baseT_Full | 379 ADVERTISED_100baseT_Half | 380 ADVERTISED_100baseT_Full | 381 ADVERTISED_10baseT_Half | 382 ADVERTISED_10baseT_Full); 383 384 mutex_lock(&priv->lock); 385 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 386 mutex_unlock(&priv->lock); 387 388 return 0; 389 } 390 391 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 392 } 393 394 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 395 { 396 struct stmmac_priv *priv = netdev_priv(dev); 397 return priv->msg_enable; 398 } 399 400 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 401 { 402 struct stmmac_priv *priv = netdev_priv(dev); 403 priv->msg_enable = level; 404 405 } 406 407 static int stmmac_check_if_running(struct net_device *dev) 408 { 409 if (!netif_running(dev)) 410 return -EBUSY; 411 return 0; 412 } 413 414 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 415 { 416 struct stmmac_priv *priv = netdev_priv(dev); 417 418 if (priv->plat->has_xgmac) 419 return XGMAC_REGSIZE * 4; 420 return REG_SPACE_SIZE; 421 } 422 423 static void stmmac_ethtool_gregs(struct net_device *dev, 424 struct ethtool_regs *regs, void *space) 425 { 426 struct stmmac_priv *priv = netdev_priv(dev); 427 u32 *reg_space = (u32 *) space; 428 429 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 430 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 431 432 if (!priv->plat->has_xgmac) { 433 /* Copy DMA registers to where ethtool expects them */ 434 memcpy(®_space[ETHTOOL_DMA_OFFSET], 435 ®_space[DMA_BUS_MODE / 4], 436 NUM_DWMAC1000_DMA_REGS * 4); 437 } 438 } 439 440 static int stmmac_nway_reset(struct net_device *dev) 441 { 442 struct stmmac_priv *priv = netdev_priv(dev); 443 444 return phylink_ethtool_nway_reset(priv->phylink); 445 } 446 447 static void stmmac_get_ringparam(struct net_device *netdev, 448 struct ethtool_ringparam *ring) 449 { 450 struct stmmac_priv *priv = netdev_priv(netdev); 451 452 ring->rx_max_pending = DMA_MAX_RX_SIZE; 453 ring->tx_max_pending = DMA_MAX_TX_SIZE; 454 ring->rx_pending = priv->dma_rx_size; 455 ring->tx_pending = priv->dma_tx_size; 456 } 457 458 static int stmmac_set_ringparam(struct net_device *netdev, 459 struct ethtool_ringparam *ring) 460 { 461 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 462 ring->rx_pending < DMA_MIN_RX_SIZE || 463 ring->rx_pending > DMA_MAX_RX_SIZE || 464 !is_power_of_2(ring->rx_pending) || 465 ring->tx_pending < DMA_MIN_TX_SIZE || 466 ring->tx_pending > DMA_MAX_TX_SIZE || 467 !is_power_of_2(ring->tx_pending)) 468 return -EINVAL; 469 470 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 471 ring->tx_pending); 472 } 473 474 static void 475 stmmac_get_pauseparam(struct net_device *netdev, 476 struct ethtool_pauseparam *pause) 477 { 478 struct stmmac_priv *priv = netdev_priv(netdev); 479 struct rgmii_adv adv_lp; 480 481 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 482 pause->autoneg = 1; 483 if (!adv_lp.pause) 484 return; 485 } else { 486 phylink_ethtool_get_pauseparam(priv->phylink, pause); 487 } 488 } 489 490 static int 491 stmmac_set_pauseparam(struct net_device *netdev, 492 struct ethtool_pauseparam *pause) 493 { 494 struct stmmac_priv *priv = netdev_priv(netdev); 495 struct rgmii_adv adv_lp; 496 497 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 498 pause->autoneg = 1; 499 if (!adv_lp.pause) 500 return -EOPNOTSUPP; 501 return 0; 502 } else { 503 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 504 } 505 } 506 507 static void stmmac_get_ethtool_stats(struct net_device *dev, 508 struct ethtool_stats *dummy, u64 *data) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 u32 rx_queues_count = priv->plat->rx_queues_to_use; 512 u32 tx_queues_count = priv->plat->tx_queues_to_use; 513 unsigned long count; 514 int i, j = 0, ret; 515 516 if (priv->dma_cap.asp) { 517 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 518 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 519 &count, NULL)) 520 data[j++] = count; 521 } 522 } 523 524 /* Update the DMA HW counters for dwmac10/100 */ 525 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats, 526 priv->ioaddr); 527 if (ret) { 528 /* If supported, for new GMAC chips expose the MMC counters */ 529 if (priv->dma_cap.rmon) { 530 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 531 532 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 533 char *p; 534 p = (char *)priv + stmmac_mmc[i].stat_offset; 535 536 data[j++] = (stmmac_mmc[i].sizeof_stat == 537 sizeof(u64)) ? (*(u64 *)p) : 538 (*(u32 *)p); 539 } 540 } 541 if (priv->eee_enabled) { 542 int val = phylink_get_eee_err(priv->phylink); 543 if (val) 544 priv->xstats.phy_eee_wakeup_error_n = val; 545 } 546 547 if (priv->synopsys_id >= DWMAC_CORE_3_50) 548 stmmac_mac_debug(priv, priv->ioaddr, 549 (void *)&priv->xstats, 550 rx_queues_count, tx_queues_count); 551 } 552 for (i = 0; i < STMMAC_STATS_LEN; i++) { 553 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 554 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 555 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 556 } 557 } 558 559 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 560 { 561 struct stmmac_priv *priv = netdev_priv(netdev); 562 int i, len, safety_len = 0; 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 len = STMMAC_STATS_LEN; 567 568 if (priv->dma_cap.rmon) 569 len += STMMAC_MMC_STATS_LEN; 570 if (priv->dma_cap.asp) { 571 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 572 if (!stmmac_safety_feat_dump(priv, 573 &priv->sstats, i, 574 NULL, NULL)) 575 safety_len++; 576 } 577 578 len += safety_len; 579 } 580 581 return len; 582 case ETH_SS_TEST: 583 return stmmac_selftest_get_count(priv); 584 default: 585 return -EOPNOTSUPP; 586 } 587 } 588 589 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 590 { 591 int i; 592 u8 *p = data; 593 struct stmmac_priv *priv = netdev_priv(dev); 594 595 switch (stringset) { 596 case ETH_SS_STATS: 597 if (priv->dma_cap.asp) { 598 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 599 const char *desc; 600 if (!stmmac_safety_feat_dump(priv, 601 &priv->sstats, i, 602 NULL, &desc)) { 603 memcpy(p, desc, ETH_GSTRING_LEN); 604 p += ETH_GSTRING_LEN; 605 } 606 } 607 } 608 if (priv->dma_cap.rmon) 609 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 610 memcpy(p, stmmac_mmc[i].stat_string, 611 ETH_GSTRING_LEN); 612 p += ETH_GSTRING_LEN; 613 } 614 for (i = 0; i < STMMAC_STATS_LEN; i++) { 615 memcpy(p, stmmac_gstrings_stats[i].stat_string, 616 ETH_GSTRING_LEN); 617 p += ETH_GSTRING_LEN; 618 } 619 break; 620 case ETH_SS_TEST: 621 stmmac_selftest_get_strings(priv, p); 622 break; 623 default: 624 WARN_ON(1); 625 break; 626 } 627 } 628 629 /* Currently only support WOL through Magic packet. */ 630 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 631 { 632 struct stmmac_priv *priv = netdev_priv(dev); 633 634 if (!priv->plat->pmt) 635 return phylink_ethtool_get_wol(priv->phylink, wol); 636 637 mutex_lock(&priv->lock); 638 if (device_can_wakeup(priv->device)) { 639 wol->supported = WAKE_MAGIC | WAKE_UCAST; 640 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 641 wol->supported &= ~WAKE_MAGIC; 642 wol->wolopts = priv->wolopts; 643 } 644 mutex_unlock(&priv->lock); 645 } 646 647 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 648 { 649 struct stmmac_priv *priv = netdev_priv(dev); 650 u32 support = WAKE_MAGIC | WAKE_UCAST; 651 652 if (!device_can_wakeup(priv->device)) 653 return -EOPNOTSUPP; 654 655 if (!priv->plat->pmt) { 656 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 657 658 if (!ret) 659 device_set_wakeup_enable(priv->device, !!wol->wolopts); 660 return ret; 661 } 662 663 /* By default almost all GMAC devices support the WoL via 664 * magic frame but we can disable it if the HW capability 665 * register shows no support for pmt_magic_frame. */ 666 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 667 wol->wolopts &= ~WAKE_MAGIC; 668 669 if (wol->wolopts & ~support) 670 return -EINVAL; 671 672 if (wol->wolopts) { 673 pr_info("stmmac: wakeup enable\n"); 674 device_set_wakeup_enable(priv->device, 1); 675 enable_irq_wake(priv->wol_irq); 676 } else { 677 device_set_wakeup_enable(priv->device, 0); 678 disable_irq_wake(priv->wol_irq); 679 } 680 681 mutex_lock(&priv->lock); 682 priv->wolopts = wol->wolopts; 683 mutex_unlock(&priv->lock); 684 685 return 0; 686 } 687 688 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 689 struct ethtool_eee *edata) 690 { 691 struct stmmac_priv *priv = netdev_priv(dev); 692 693 if (!priv->dma_cap.eee) 694 return -EOPNOTSUPP; 695 696 edata->eee_enabled = priv->eee_enabled; 697 edata->eee_active = priv->eee_active; 698 edata->tx_lpi_timer = priv->tx_lpi_timer; 699 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 700 701 return phylink_ethtool_get_eee(priv->phylink, edata); 702 } 703 704 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 705 struct ethtool_eee *edata) 706 { 707 struct stmmac_priv *priv = netdev_priv(dev); 708 int ret; 709 710 if (!priv->dma_cap.eee) 711 return -EOPNOTSUPP; 712 713 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 714 netdev_warn(priv->dev, 715 "Setting EEE tx-lpi is not supported\n"); 716 717 if (!edata->eee_enabled) 718 stmmac_disable_eee_mode(priv); 719 720 ret = phylink_ethtool_set_eee(priv->phylink, edata); 721 if (ret) 722 return ret; 723 724 if (edata->eee_enabled && 725 priv->tx_lpi_timer != edata->tx_lpi_timer) { 726 priv->tx_lpi_timer = edata->tx_lpi_timer; 727 stmmac_eee_init(priv); 728 } 729 730 return 0; 731 } 732 733 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 734 { 735 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 736 737 if (!clk) { 738 clk = priv->plat->clk_ref_rate; 739 if (!clk) 740 return 0; 741 } 742 743 return (usec * (clk / 1000000)) / 256; 744 } 745 746 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 747 { 748 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 749 750 if (!clk) { 751 clk = priv->plat->clk_ref_rate; 752 if (!clk) 753 return 0; 754 } 755 756 return (riwt * 256) / (clk / 1000000); 757 } 758 759 static int stmmac_get_coalesce(struct net_device *dev, 760 struct ethtool_coalesce *ec) 761 { 762 struct stmmac_priv *priv = netdev_priv(dev); 763 764 ec->tx_coalesce_usecs = priv->tx_coal_timer; 765 ec->tx_max_coalesced_frames = priv->tx_coal_frames; 766 767 if (priv->use_riwt) { 768 ec->rx_max_coalesced_frames = priv->rx_coal_frames; 769 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv); 770 } 771 772 return 0; 773 } 774 775 static int stmmac_set_coalesce(struct net_device *dev, 776 struct ethtool_coalesce *ec) 777 { 778 struct stmmac_priv *priv = netdev_priv(dev); 779 u32 rx_cnt = priv->plat->rx_queues_to_use; 780 unsigned int rx_riwt; 781 782 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 783 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 784 785 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 786 return -EINVAL; 787 788 priv->rx_riwt = rx_riwt; 789 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 790 } 791 792 if ((ec->tx_coalesce_usecs == 0) && 793 (ec->tx_max_coalesced_frames == 0)) 794 return -EINVAL; 795 796 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 797 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 798 return -EINVAL; 799 800 /* Only copy relevant parameters, ignore all others. */ 801 priv->tx_coal_frames = ec->tx_max_coalesced_frames; 802 priv->tx_coal_timer = ec->tx_coalesce_usecs; 803 priv->rx_coal_frames = ec->rx_max_coalesced_frames; 804 return 0; 805 } 806 807 static int stmmac_get_rxnfc(struct net_device *dev, 808 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 809 { 810 struct stmmac_priv *priv = netdev_priv(dev); 811 812 switch (rxnfc->cmd) { 813 case ETHTOOL_GRXRINGS: 814 rxnfc->data = priv->plat->rx_queues_to_use; 815 break; 816 default: 817 return -EOPNOTSUPP; 818 } 819 820 return 0; 821 } 822 823 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 824 { 825 struct stmmac_priv *priv = netdev_priv(dev); 826 827 return sizeof(priv->rss.key); 828 } 829 830 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 831 { 832 struct stmmac_priv *priv = netdev_priv(dev); 833 834 return ARRAY_SIZE(priv->rss.table); 835 } 836 837 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 838 u8 *hfunc) 839 { 840 struct stmmac_priv *priv = netdev_priv(dev); 841 int i; 842 843 if (indir) { 844 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 845 indir[i] = priv->rss.table[i]; 846 } 847 848 if (key) 849 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 850 if (hfunc) 851 *hfunc = ETH_RSS_HASH_TOP; 852 853 return 0; 854 } 855 856 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 857 const u8 *key, const u8 hfunc) 858 { 859 struct stmmac_priv *priv = netdev_priv(dev); 860 int i; 861 862 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 863 return -EOPNOTSUPP; 864 865 if (indir) { 866 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 867 priv->rss.table[i] = indir[i]; 868 } 869 870 if (key) 871 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 872 873 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 874 priv->plat->rx_queues_to_use); 875 } 876 877 static void stmmac_get_channels(struct net_device *dev, 878 struct ethtool_channels *chan) 879 { 880 struct stmmac_priv *priv = netdev_priv(dev); 881 882 chan->rx_count = priv->plat->rx_queues_to_use; 883 chan->tx_count = priv->plat->tx_queues_to_use; 884 chan->max_rx = priv->dma_cap.number_rx_queues; 885 chan->max_tx = priv->dma_cap.number_tx_queues; 886 } 887 888 static int stmmac_set_channels(struct net_device *dev, 889 struct ethtool_channels *chan) 890 { 891 struct stmmac_priv *priv = netdev_priv(dev); 892 893 if (chan->rx_count > priv->dma_cap.number_rx_queues || 894 chan->tx_count > priv->dma_cap.number_tx_queues || 895 !chan->rx_count || !chan->tx_count) 896 return -EINVAL; 897 898 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 899 } 900 901 static int stmmac_get_ts_info(struct net_device *dev, 902 struct ethtool_ts_info *info) 903 { 904 struct stmmac_priv *priv = netdev_priv(dev); 905 906 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 907 908 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 909 SOF_TIMESTAMPING_TX_HARDWARE | 910 SOF_TIMESTAMPING_RX_SOFTWARE | 911 SOF_TIMESTAMPING_RX_HARDWARE | 912 SOF_TIMESTAMPING_SOFTWARE | 913 SOF_TIMESTAMPING_RAW_HARDWARE; 914 915 if (priv->ptp_clock) 916 info->phc_index = ptp_clock_index(priv->ptp_clock); 917 918 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 919 920 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 921 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 922 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 923 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 924 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 925 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 926 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 927 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 928 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 929 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 930 (1 << HWTSTAMP_FILTER_ALL)); 931 return 0; 932 } else 933 return ethtool_op_get_ts_info(dev, info); 934 } 935 936 static int stmmac_get_tunable(struct net_device *dev, 937 const struct ethtool_tunable *tuna, void *data) 938 { 939 struct stmmac_priv *priv = netdev_priv(dev); 940 int ret = 0; 941 942 switch (tuna->id) { 943 case ETHTOOL_RX_COPYBREAK: 944 *(u32 *)data = priv->rx_copybreak; 945 break; 946 default: 947 ret = -EINVAL; 948 break; 949 } 950 951 return ret; 952 } 953 954 static int stmmac_set_tunable(struct net_device *dev, 955 const struct ethtool_tunable *tuna, 956 const void *data) 957 { 958 struct stmmac_priv *priv = netdev_priv(dev); 959 int ret = 0; 960 961 switch (tuna->id) { 962 case ETHTOOL_RX_COPYBREAK: 963 priv->rx_copybreak = *(u32 *)data; 964 break; 965 default: 966 ret = -EINVAL; 967 break; 968 } 969 970 return ret; 971 } 972 973 static const struct ethtool_ops stmmac_ethtool_ops = { 974 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 975 ETHTOOL_COALESCE_MAX_FRAMES, 976 .begin = stmmac_check_if_running, 977 .get_drvinfo = stmmac_ethtool_getdrvinfo, 978 .get_msglevel = stmmac_ethtool_getmsglevel, 979 .set_msglevel = stmmac_ethtool_setmsglevel, 980 .get_regs = stmmac_ethtool_gregs, 981 .get_regs_len = stmmac_ethtool_get_regs_len, 982 .get_link = ethtool_op_get_link, 983 .nway_reset = stmmac_nway_reset, 984 .get_ringparam = stmmac_get_ringparam, 985 .set_ringparam = stmmac_set_ringparam, 986 .get_pauseparam = stmmac_get_pauseparam, 987 .set_pauseparam = stmmac_set_pauseparam, 988 .self_test = stmmac_selftest_run, 989 .get_ethtool_stats = stmmac_get_ethtool_stats, 990 .get_strings = stmmac_get_strings, 991 .get_wol = stmmac_get_wol, 992 .set_wol = stmmac_set_wol, 993 .get_eee = stmmac_ethtool_op_get_eee, 994 .set_eee = stmmac_ethtool_op_set_eee, 995 .get_sset_count = stmmac_get_sset_count, 996 .get_rxnfc = stmmac_get_rxnfc, 997 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 998 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 999 .get_rxfh = stmmac_get_rxfh, 1000 .set_rxfh = stmmac_set_rxfh, 1001 .get_ts_info = stmmac_get_ts_info, 1002 .get_coalesce = stmmac_get_coalesce, 1003 .set_coalesce = stmmac_set_coalesce, 1004 .get_channels = stmmac_get_channels, 1005 .set_channels = stmmac_set_channels, 1006 .get_tunable = stmmac_get_tunable, 1007 .set_tunable = stmmac_set_tunable, 1008 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1009 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1010 }; 1011 1012 void stmmac_set_ethtool_ops(struct net_device *netdev) 1013 { 1014 netdev->ethtool_ops = &stmmac_ethtool_ops; 1015 } 1016