1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethtool support 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/etherdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/interrupt.h> 14 #include <linux/mii.h> 15 #include <linux/phylink.h> 16 #include <linux/net_tstamp.h> 17 #include <asm/io.h> 18 19 #include "stmmac.h" 20 #include "dwmac_dma.h" 21 #include "dwxgmac2.h" 22 23 #define REG_SPACE_SIZE 0x1060 24 #define GMAC4_REG_SPACE_SIZE 0x116C 25 #define MAC100_ETHTOOL_NAME "st_mac100" 26 #define GMAC_ETHTOOL_NAME "st_gmac" 27 #define XGMAC_ETHTOOL_NAME "st_xgmac" 28 29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h 30 * 31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the 32 * same time due to the conflicting macro names. 33 */ 34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100 35 36 #define ETHTOOL_DMA_OFFSET 55 37 38 struct stmmac_stats { 39 char stat_string[ETH_GSTRING_LEN]; 40 int sizeof_stat; 41 int stat_offset; 42 }; 43 44 #define STMMAC_STAT(m) \ 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 47 48 static const struct stmmac_stats stmmac_gstrings_stats[] = { 49 /* Transmit errors */ 50 STMMAC_STAT(tx_underflow), 51 STMMAC_STAT(tx_carrier), 52 STMMAC_STAT(tx_losscarrier), 53 STMMAC_STAT(vlan_tag), 54 STMMAC_STAT(tx_deferred), 55 STMMAC_STAT(tx_vlan), 56 STMMAC_STAT(tx_jabber), 57 STMMAC_STAT(tx_frame_flushed), 58 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_ip_header_error), 60 /* Receive errors */ 61 STMMAC_STAT(rx_desc), 62 STMMAC_STAT(sa_filter_fail), 63 STMMAC_STAT(overflow_error), 64 STMMAC_STAT(ipc_csum_error), 65 STMMAC_STAT(rx_collision), 66 STMMAC_STAT(rx_crc_errors), 67 STMMAC_STAT(dribbling_bit), 68 STMMAC_STAT(rx_length), 69 STMMAC_STAT(rx_mii), 70 STMMAC_STAT(rx_multicast), 71 STMMAC_STAT(rx_gmac_overflow), 72 STMMAC_STAT(rx_watchdog), 73 STMMAC_STAT(da_rx_filter_fail), 74 STMMAC_STAT(sa_rx_filter_fail), 75 STMMAC_STAT(rx_missed_cntr), 76 STMMAC_STAT(rx_overflow_cntr), 77 STMMAC_STAT(rx_vlan), 78 STMMAC_STAT(rx_split_hdr_pkt_n), 79 /* Tx/Rx IRQ error info */ 80 STMMAC_STAT(tx_undeflow_irq), 81 STMMAC_STAT(tx_process_stopped_irq), 82 STMMAC_STAT(tx_jabber_irq), 83 STMMAC_STAT(rx_overflow_irq), 84 STMMAC_STAT(rx_buf_unav_irq), 85 STMMAC_STAT(rx_process_stopped_irq), 86 STMMAC_STAT(rx_watchdog_irq), 87 STMMAC_STAT(tx_early_irq), 88 STMMAC_STAT(fatal_bus_error_irq), 89 /* Tx/Rx IRQ Events */ 90 STMMAC_STAT(rx_early_irq), 91 STMMAC_STAT(threshold), 92 STMMAC_STAT(irq_receive_pmt_irq_n), 93 /* MMC info */ 94 STMMAC_STAT(mmc_tx_irq_n), 95 STMMAC_STAT(mmc_rx_irq_n), 96 STMMAC_STAT(mmc_rx_csum_offload_irq_n), 97 /* EEE */ 98 STMMAC_STAT(irq_tx_path_in_lpi_mode_n), 99 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n), 100 STMMAC_STAT(irq_rx_path_in_lpi_mode_n), 101 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n), 102 STMMAC_STAT(phy_eee_wakeup_error_n), 103 /* Extended RDES status */ 104 STMMAC_STAT(ip_hdr_err), 105 STMMAC_STAT(ip_payload_err), 106 STMMAC_STAT(ip_csum_bypassed), 107 STMMAC_STAT(ipv4_pkt_rcvd), 108 STMMAC_STAT(ipv6_pkt_rcvd), 109 STMMAC_STAT(no_ptp_rx_msg_type_ext), 110 STMMAC_STAT(ptp_rx_msg_type_sync), 111 STMMAC_STAT(ptp_rx_msg_type_follow_up), 112 STMMAC_STAT(ptp_rx_msg_type_delay_req), 113 STMMAC_STAT(ptp_rx_msg_type_delay_resp), 114 STMMAC_STAT(ptp_rx_msg_type_pdelay_req), 115 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), 116 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), 117 STMMAC_STAT(ptp_rx_msg_type_announce), 118 STMMAC_STAT(ptp_rx_msg_type_management), 119 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), 120 STMMAC_STAT(ptp_frame_type), 121 STMMAC_STAT(ptp_ver), 122 STMMAC_STAT(timestamp_dropped), 123 STMMAC_STAT(av_pkt_rcvd), 124 STMMAC_STAT(av_tagged_pkt_rcvd), 125 STMMAC_STAT(vlan_tag_priority_val), 126 STMMAC_STAT(l3_filter_match), 127 STMMAC_STAT(l4_filter_match), 128 STMMAC_STAT(l3_l4_filter_no_match), 129 /* PCS */ 130 STMMAC_STAT(irq_pcs_ane_n), 131 STMMAC_STAT(irq_pcs_link_n), 132 STMMAC_STAT(irq_rgmii_n), 133 /* DEBUG */ 134 STMMAC_STAT(mtl_tx_status_fifo_full), 135 STMMAC_STAT(mtl_tx_fifo_not_empty), 136 STMMAC_STAT(mmtl_fifo_ctrl), 137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write), 138 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait), 139 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read), 140 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle), 141 STMMAC_STAT(mac_tx_in_pause), 142 STMMAC_STAT(mac_tx_frame_ctrl_xfer), 143 STMMAC_STAT(mac_tx_frame_ctrl_idle), 144 STMMAC_STAT(mac_tx_frame_ctrl_wait), 145 STMMAC_STAT(mac_tx_frame_ctrl_pause), 146 STMMAC_STAT(mac_gmii_tx_proto_engine), 147 STMMAC_STAT(mtl_rx_fifo_fill_level_full), 148 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh), 149 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh), 150 STMMAC_STAT(mtl_rx_fifo_fill_level_empty), 151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush), 152 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data), 153 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status), 154 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle), 155 STMMAC_STAT(mtl_rx_fifo_ctrl_active), 156 STMMAC_STAT(mac_rx_frame_ctrl_fifo), 157 STMMAC_STAT(mac_gmii_rx_proto_engine), 158 /* EST */ 159 STMMAC_STAT(mtl_est_cgce), 160 STMMAC_STAT(mtl_est_hlbs), 161 STMMAC_STAT(mtl_est_hlbf), 162 STMMAC_STAT(mtl_est_btre), 163 STMMAC_STAT(mtl_est_btrlm), 164 }; 165 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats) 166 167 /* statistics collected in queue which will be summed up for all TX or RX 168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). 169 */ 170 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = { 171 "rx_pkt_n", 172 "rx_normal_irq_n", 173 "tx_pkt_n", 174 "tx_normal_irq_n", 175 "tx_clean", 176 "tx_set_ic_bit", 177 "tx_tso_frames", 178 "tx_tso_nfrags", 179 "normal_irq_n", 180 "napi_poll", 181 }; 182 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string) 183 184 /* HW MAC Management counters (if supported) */ 185 #define STMMAC_MMC_STAT(m) \ 186 { #m, sizeof_field(struct stmmac_counters, m), \ 187 offsetof(struct stmmac_priv, mmc.m)} 188 189 static const struct stmmac_stats stmmac_mmc[] = { 190 STMMAC_MMC_STAT(mmc_tx_octetcount_gb), 191 STMMAC_MMC_STAT(mmc_tx_framecount_gb), 192 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g), 193 STMMAC_MMC_STAT(mmc_tx_multicastframe_g), 194 STMMAC_MMC_STAT(mmc_tx_64_octets_gb), 195 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb), 196 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb), 197 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb), 198 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb), 199 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb), 200 STMMAC_MMC_STAT(mmc_tx_unicast_gb), 201 STMMAC_MMC_STAT(mmc_tx_multicast_gb), 202 STMMAC_MMC_STAT(mmc_tx_broadcast_gb), 203 STMMAC_MMC_STAT(mmc_tx_underflow_error), 204 STMMAC_MMC_STAT(mmc_tx_singlecol_g), 205 STMMAC_MMC_STAT(mmc_tx_multicol_g), 206 STMMAC_MMC_STAT(mmc_tx_deferred), 207 STMMAC_MMC_STAT(mmc_tx_latecol), 208 STMMAC_MMC_STAT(mmc_tx_exesscol), 209 STMMAC_MMC_STAT(mmc_tx_carrier_error), 210 STMMAC_MMC_STAT(mmc_tx_octetcount_g), 211 STMMAC_MMC_STAT(mmc_tx_framecount_g), 212 STMMAC_MMC_STAT(mmc_tx_excessdef), 213 STMMAC_MMC_STAT(mmc_tx_pause_frame), 214 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g), 215 STMMAC_MMC_STAT(mmc_rx_framecount_gb), 216 STMMAC_MMC_STAT(mmc_rx_octetcount_gb), 217 STMMAC_MMC_STAT(mmc_rx_octetcount_g), 218 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g), 219 STMMAC_MMC_STAT(mmc_rx_multicastframe_g), 220 STMMAC_MMC_STAT(mmc_rx_crc_error), 221 STMMAC_MMC_STAT(mmc_rx_align_error), 222 STMMAC_MMC_STAT(mmc_rx_run_error), 223 STMMAC_MMC_STAT(mmc_rx_jabber_error), 224 STMMAC_MMC_STAT(mmc_rx_undersize_g), 225 STMMAC_MMC_STAT(mmc_rx_oversize_g), 226 STMMAC_MMC_STAT(mmc_rx_64_octets_gb), 227 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb), 228 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb), 229 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb), 230 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb), 231 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb), 232 STMMAC_MMC_STAT(mmc_rx_unicast_g), 233 STMMAC_MMC_STAT(mmc_rx_length_error), 234 STMMAC_MMC_STAT(mmc_rx_autofrangetype), 235 STMMAC_MMC_STAT(mmc_rx_pause_frames), 236 STMMAC_MMC_STAT(mmc_rx_fifo_overflow), 237 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb), 238 STMMAC_MMC_STAT(mmc_rx_watchdog_error), 239 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask), 240 STMMAC_MMC_STAT(mmc_rx_ipc_intr), 241 STMMAC_MMC_STAT(mmc_rx_ipv4_gd), 242 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr), 243 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay), 244 STMMAC_MMC_STAT(mmc_rx_ipv4_frag), 245 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl), 246 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets), 247 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets), 248 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets), 249 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets), 250 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets), 251 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets), 252 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets), 253 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets), 254 STMMAC_MMC_STAT(mmc_rx_ipv6_gd), 255 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr), 256 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay), 257 STMMAC_MMC_STAT(mmc_rx_udp_gd), 258 STMMAC_MMC_STAT(mmc_rx_udp_err), 259 STMMAC_MMC_STAT(mmc_rx_tcp_gd), 260 STMMAC_MMC_STAT(mmc_rx_tcp_err), 261 STMMAC_MMC_STAT(mmc_rx_icmp_gd), 262 STMMAC_MMC_STAT(mmc_rx_icmp_err), 263 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets), 264 STMMAC_MMC_STAT(mmc_rx_udp_err_octets), 265 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets), 266 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets), 267 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets), 268 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets), 269 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr), 270 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr), 271 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr), 272 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr), 273 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr), 274 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr), 275 }; 276 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc) 277 278 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = { 279 "tx_pkt_n", 280 "tx_irq_n", 281 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string) 282 }; 283 284 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = { 285 "rx_pkt_n", 286 "rx_irq_n", 287 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string) 288 }; 289 290 static void stmmac_ethtool_getdrvinfo(struct net_device *dev, 291 struct ethtool_drvinfo *info) 292 { 293 struct stmmac_priv *priv = netdev_priv(dev); 294 295 if (priv->plat->has_gmac || priv->plat->has_gmac4) 296 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver)); 297 else if (priv->plat->has_xgmac) 298 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver)); 299 else 300 strscpy(info->driver, MAC100_ETHTOOL_NAME, 301 sizeof(info->driver)); 302 303 if (priv->plat->pdev) { 304 strscpy(info->bus_info, pci_name(priv->plat->pdev), 305 sizeof(info->bus_info)); 306 } 307 } 308 309 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev, 310 struct ethtool_link_ksettings *cmd) 311 { 312 struct stmmac_priv *priv = netdev_priv(dev); 313 314 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 315 (priv->hw->pcs & STMMAC_PCS_RGMII || 316 priv->hw->pcs & STMMAC_PCS_SGMII)) { 317 struct rgmii_adv adv; 318 u32 supported, advertising, lp_advertising; 319 320 if (!priv->xstats.pcs_link) { 321 cmd->base.speed = SPEED_UNKNOWN; 322 cmd->base.duplex = DUPLEX_UNKNOWN; 323 return 0; 324 } 325 cmd->base.duplex = priv->xstats.pcs_duplex; 326 327 cmd->base.speed = priv->xstats.pcs_speed; 328 329 /* Get and convert ADV/LP_ADV from the HW AN registers */ 330 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv)) 331 return -EOPNOTSUPP; /* should never happen indeed */ 332 333 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */ 334 335 ethtool_convert_link_mode_to_legacy_u32( 336 &supported, cmd->link_modes.supported); 337 ethtool_convert_link_mode_to_legacy_u32( 338 &advertising, cmd->link_modes.advertising); 339 ethtool_convert_link_mode_to_legacy_u32( 340 &lp_advertising, cmd->link_modes.lp_advertising); 341 342 if (adv.pause & STMMAC_PCS_PAUSE) 343 advertising |= ADVERTISED_Pause; 344 if (adv.pause & STMMAC_PCS_ASYM_PAUSE) 345 advertising |= ADVERTISED_Asym_Pause; 346 if (adv.lp_pause & STMMAC_PCS_PAUSE) 347 lp_advertising |= ADVERTISED_Pause; 348 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE) 349 lp_advertising |= ADVERTISED_Asym_Pause; 350 351 /* Reg49[3] always set because ANE is always supported */ 352 cmd->base.autoneg = ADVERTISED_Autoneg; 353 supported |= SUPPORTED_Autoneg; 354 advertising |= ADVERTISED_Autoneg; 355 lp_advertising |= ADVERTISED_Autoneg; 356 357 if (adv.duplex) { 358 supported |= (SUPPORTED_1000baseT_Full | 359 SUPPORTED_100baseT_Full | 360 SUPPORTED_10baseT_Full); 361 advertising |= (ADVERTISED_1000baseT_Full | 362 ADVERTISED_100baseT_Full | 363 ADVERTISED_10baseT_Full); 364 } else { 365 supported |= (SUPPORTED_1000baseT_Half | 366 SUPPORTED_100baseT_Half | 367 SUPPORTED_10baseT_Half); 368 advertising |= (ADVERTISED_1000baseT_Half | 369 ADVERTISED_100baseT_Half | 370 ADVERTISED_10baseT_Half); 371 } 372 if (adv.lp_duplex) 373 lp_advertising |= (ADVERTISED_1000baseT_Full | 374 ADVERTISED_100baseT_Full | 375 ADVERTISED_10baseT_Full); 376 else 377 lp_advertising |= (ADVERTISED_1000baseT_Half | 378 ADVERTISED_100baseT_Half | 379 ADVERTISED_10baseT_Half); 380 cmd->base.port = PORT_OTHER; 381 382 ethtool_convert_legacy_u32_to_link_mode( 383 cmd->link_modes.supported, supported); 384 ethtool_convert_legacy_u32_to_link_mode( 385 cmd->link_modes.advertising, advertising); 386 ethtool_convert_legacy_u32_to_link_mode( 387 cmd->link_modes.lp_advertising, lp_advertising); 388 389 return 0; 390 } 391 392 return phylink_ethtool_ksettings_get(priv->phylink, cmd); 393 } 394 395 static int 396 stmmac_ethtool_set_link_ksettings(struct net_device *dev, 397 const struct ethtool_link_ksettings *cmd) 398 { 399 struct stmmac_priv *priv = netdev_priv(dev); 400 401 if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) && 402 (priv->hw->pcs & STMMAC_PCS_RGMII || 403 priv->hw->pcs & STMMAC_PCS_SGMII)) { 404 /* Only support ANE */ 405 if (cmd->base.autoneg != AUTONEG_ENABLE) 406 return -EINVAL; 407 408 mutex_lock(&priv->lock); 409 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 410 mutex_unlock(&priv->lock); 411 412 return 0; 413 } 414 415 return phylink_ethtool_ksettings_set(priv->phylink, cmd); 416 } 417 418 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev) 419 { 420 struct stmmac_priv *priv = netdev_priv(dev); 421 return priv->msg_enable; 422 } 423 424 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level) 425 { 426 struct stmmac_priv *priv = netdev_priv(dev); 427 priv->msg_enable = level; 428 429 } 430 431 static int stmmac_check_if_running(struct net_device *dev) 432 { 433 if (!netif_running(dev)) 434 return -EBUSY; 435 return 0; 436 } 437 438 static int stmmac_ethtool_get_regs_len(struct net_device *dev) 439 { 440 struct stmmac_priv *priv = netdev_priv(dev); 441 442 if (priv->plat->has_xgmac) 443 return XGMAC_REGSIZE * 4; 444 else if (priv->plat->has_gmac4) 445 return GMAC4_REG_SPACE_SIZE; 446 return REG_SPACE_SIZE; 447 } 448 449 static void stmmac_ethtool_gregs(struct net_device *dev, 450 struct ethtool_regs *regs, void *space) 451 { 452 struct stmmac_priv *priv = netdev_priv(dev); 453 u32 *reg_space = (u32 *) space; 454 455 stmmac_dump_mac_regs(priv, priv->hw, reg_space); 456 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space); 457 458 /* Copy DMA registers to where ethtool expects them */ 459 if (priv->plat->has_gmac4) { 460 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */ 461 memcpy(®_space[ETHTOOL_DMA_OFFSET], 462 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4], 463 NUM_DWMAC4_DMA_REGS * 4); 464 } else if (!priv->plat->has_xgmac) { 465 memcpy(®_space[ETHTOOL_DMA_OFFSET], 466 ®_space[DMA_BUS_MODE / 4], 467 NUM_DWMAC1000_DMA_REGS * 4); 468 } 469 } 470 471 static int stmmac_nway_reset(struct net_device *dev) 472 { 473 struct stmmac_priv *priv = netdev_priv(dev); 474 475 return phylink_ethtool_nway_reset(priv->phylink); 476 } 477 478 static void stmmac_get_ringparam(struct net_device *netdev, 479 struct ethtool_ringparam *ring, 480 struct kernel_ethtool_ringparam *kernel_ring, 481 struct netlink_ext_ack *extack) 482 { 483 struct stmmac_priv *priv = netdev_priv(netdev); 484 485 ring->rx_max_pending = DMA_MAX_RX_SIZE; 486 ring->tx_max_pending = DMA_MAX_TX_SIZE; 487 ring->rx_pending = priv->dma_conf.dma_rx_size; 488 ring->tx_pending = priv->dma_conf.dma_tx_size; 489 } 490 491 static int stmmac_set_ringparam(struct net_device *netdev, 492 struct ethtool_ringparam *ring, 493 struct kernel_ethtool_ringparam *kernel_ring, 494 struct netlink_ext_ack *extack) 495 { 496 if (ring->rx_mini_pending || ring->rx_jumbo_pending || 497 ring->rx_pending < DMA_MIN_RX_SIZE || 498 ring->rx_pending > DMA_MAX_RX_SIZE || 499 !is_power_of_2(ring->rx_pending) || 500 ring->tx_pending < DMA_MIN_TX_SIZE || 501 ring->tx_pending > DMA_MAX_TX_SIZE || 502 !is_power_of_2(ring->tx_pending)) 503 return -EINVAL; 504 505 return stmmac_reinit_ringparam(netdev, ring->rx_pending, 506 ring->tx_pending); 507 } 508 509 static void 510 stmmac_get_pauseparam(struct net_device *netdev, 511 struct ethtool_pauseparam *pause) 512 { 513 struct stmmac_priv *priv = netdev_priv(netdev); 514 struct rgmii_adv adv_lp; 515 516 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 517 pause->autoneg = 1; 518 if (!adv_lp.pause) 519 return; 520 } else { 521 phylink_ethtool_get_pauseparam(priv->phylink, pause); 522 } 523 } 524 525 static int 526 stmmac_set_pauseparam(struct net_device *netdev, 527 struct ethtool_pauseparam *pause) 528 { 529 struct stmmac_priv *priv = netdev_priv(netdev); 530 struct rgmii_adv adv_lp; 531 532 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) { 533 pause->autoneg = 1; 534 if (!adv_lp.pause) 535 return -EOPNOTSUPP; 536 return 0; 537 } else { 538 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 539 } 540 } 541 542 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data) 543 { 544 u32 tx_cnt = priv->plat->tx_queues_to_use; 545 u32 rx_cnt = priv->plat->rx_queues_to_use; 546 unsigned int start; 547 int q, stat; 548 char *p; 549 550 for (q = 0; q < tx_cnt; q++) { 551 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q]; 552 struct stmmac_txq_stats snapshot; 553 554 do { 555 start = u64_stats_fetch_begin(&txq_stats->syncp); 556 snapshot = *txq_stats; 557 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 558 559 p = (char *)&snapshot + offsetof(struct stmmac_txq_stats, tx_pkt_n); 560 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 561 *data++ = (*(u64 *)p); 562 p += sizeof(u64); 563 } 564 } 565 566 for (q = 0; q < rx_cnt; q++) { 567 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q]; 568 struct stmmac_rxq_stats snapshot; 569 570 do { 571 start = u64_stats_fetch_begin(&rxq_stats->syncp); 572 snapshot = *rxq_stats; 573 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 574 575 p = (char *)&snapshot + offsetof(struct stmmac_rxq_stats, rx_pkt_n); 576 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 577 *data++ = (*(u64 *)p); 578 p += sizeof(u64); 579 } 580 } 581 } 582 583 static void stmmac_get_ethtool_stats(struct net_device *dev, 584 struct ethtool_stats *dummy, u64 *data) 585 { 586 struct stmmac_priv *priv = netdev_priv(dev); 587 u32 rx_queues_count = priv->plat->rx_queues_to_use; 588 u32 tx_queues_count = priv->plat->tx_queues_to_use; 589 u64 napi_poll = 0, normal_irq_n = 0; 590 int i, j = 0, pos, ret; 591 unsigned long count; 592 unsigned int start; 593 594 if (priv->dma_cap.asp) { 595 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 596 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i, 597 &count, NULL)) 598 data[j++] = count; 599 } 600 } 601 602 /* Update the DMA HW counters for dwmac10/100 */ 603 ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr); 604 if (ret) { 605 /* If supported, for new GMAC chips expose the MMC counters */ 606 if (priv->dma_cap.rmon) { 607 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc); 608 609 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 610 char *p; 611 p = (char *)priv + stmmac_mmc[i].stat_offset; 612 613 data[j++] = (stmmac_mmc[i].sizeof_stat == 614 sizeof(u64)) ? (*(u64 *)p) : 615 (*(u32 *)p); 616 } 617 } 618 if (priv->eee_enabled) { 619 int val = phylink_get_eee_err(priv->phylink); 620 if (val) 621 priv->xstats.phy_eee_wakeup_error_n = val; 622 } 623 624 if (priv->synopsys_id >= DWMAC_CORE_3_50) 625 stmmac_mac_debug(priv, priv->ioaddr, 626 (void *)&priv->xstats, 627 rx_queues_count, tx_queues_count); 628 } 629 for (i = 0; i < STMMAC_STATS_LEN; i++) { 630 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 631 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat == 632 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p); 633 } 634 635 pos = j; 636 for (i = 0; i < rx_queues_count; i++) { 637 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i]; 638 struct stmmac_rxq_stats snapshot; 639 640 j = pos; 641 do { 642 start = u64_stats_fetch_begin(&rxq_stats->syncp); 643 snapshot = *rxq_stats; 644 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 645 646 data[j++] += snapshot.rx_pkt_n; 647 data[j++] += snapshot.rx_normal_irq_n; 648 normal_irq_n += snapshot.rx_normal_irq_n; 649 napi_poll += snapshot.napi_poll; 650 } 651 652 pos = j; 653 for (i = 0; i < tx_queues_count; i++) { 654 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i]; 655 struct stmmac_txq_stats snapshot; 656 657 j = pos; 658 do { 659 start = u64_stats_fetch_begin(&txq_stats->syncp); 660 snapshot = *txq_stats; 661 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 662 663 data[j++] += snapshot.tx_pkt_n; 664 data[j++] += snapshot.tx_normal_irq_n; 665 normal_irq_n += snapshot.tx_normal_irq_n; 666 data[j++] += snapshot.tx_clean; 667 data[j++] += snapshot.tx_set_ic_bit; 668 data[j++] += snapshot.tx_tso_frames; 669 data[j++] += snapshot.tx_tso_nfrags; 670 napi_poll += snapshot.napi_poll; 671 } 672 normal_irq_n += priv->xstats.rx_early_irq; 673 data[j++] = normal_irq_n; 674 data[j++] = napi_poll; 675 676 stmmac_get_per_qstats(priv, &data[j]); 677 } 678 679 static int stmmac_get_sset_count(struct net_device *netdev, int sset) 680 { 681 struct stmmac_priv *priv = netdev_priv(netdev); 682 u32 tx_cnt = priv->plat->tx_queues_to_use; 683 u32 rx_cnt = priv->plat->rx_queues_to_use; 684 int i, len, safety_len = 0; 685 686 switch (sset) { 687 case ETH_SS_STATS: 688 len = STMMAC_STATS_LEN + STMMAC_QSTATS + 689 STMMAC_TXQ_STATS * tx_cnt + 690 STMMAC_RXQ_STATS * rx_cnt; 691 692 if (priv->dma_cap.rmon) 693 len += STMMAC_MMC_STATS_LEN; 694 if (priv->dma_cap.asp) { 695 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 696 if (!stmmac_safety_feat_dump(priv, 697 &priv->sstats, i, 698 NULL, NULL)) 699 safety_len++; 700 } 701 702 len += safety_len; 703 } 704 705 return len; 706 case ETH_SS_TEST: 707 return stmmac_selftest_get_count(priv); 708 default: 709 return -EOPNOTSUPP; 710 } 711 } 712 713 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data) 714 { 715 u32 tx_cnt = priv->plat->tx_queues_to_use; 716 u32 rx_cnt = priv->plat->rx_queues_to_use; 717 int q, stat; 718 719 for (q = 0; q < tx_cnt; q++) { 720 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) { 721 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 722 stmmac_qstats_tx_string[stat]); 723 data += ETH_GSTRING_LEN; 724 } 725 } 726 for (q = 0; q < rx_cnt; q++) { 727 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) { 728 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q, 729 stmmac_qstats_rx_string[stat]); 730 data += ETH_GSTRING_LEN; 731 } 732 } 733 } 734 735 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) 736 { 737 int i; 738 u8 *p = data; 739 struct stmmac_priv *priv = netdev_priv(dev); 740 741 switch (stringset) { 742 case ETH_SS_STATS: 743 if (priv->dma_cap.asp) { 744 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) { 745 const char *desc; 746 if (!stmmac_safety_feat_dump(priv, 747 &priv->sstats, i, 748 NULL, &desc)) { 749 memcpy(p, desc, ETH_GSTRING_LEN); 750 p += ETH_GSTRING_LEN; 751 } 752 } 753 } 754 if (priv->dma_cap.rmon) 755 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 756 memcpy(p, stmmac_mmc[i].stat_string, 757 ETH_GSTRING_LEN); 758 p += ETH_GSTRING_LEN; 759 } 760 for (i = 0; i < STMMAC_STATS_LEN; i++) { 761 memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN); 762 p += ETH_GSTRING_LEN; 763 } 764 for (i = 0; i < STMMAC_QSTATS; i++) { 765 memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN); 766 p += ETH_GSTRING_LEN; 767 } 768 stmmac_get_qstats_string(priv, p); 769 break; 770 case ETH_SS_TEST: 771 stmmac_selftest_get_strings(priv, p); 772 break; 773 default: 774 WARN_ON(1); 775 break; 776 } 777 } 778 779 /* Currently only support WOL through Magic packet. */ 780 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 781 { 782 struct stmmac_priv *priv = netdev_priv(dev); 783 784 if (!priv->plat->pmt) 785 return phylink_ethtool_get_wol(priv->phylink, wol); 786 787 mutex_lock(&priv->lock); 788 if (device_can_wakeup(priv->device)) { 789 wol->supported = WAKE_MAGIC | WAKE_UCAST; 790 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame) 791 wol->supported &= ~WAKE_MAGIC; 792 wol->wolopts = priv->wolopts; 793 } 794 mutex_unlock(&priv->lock); 795 } 796 797 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 798 { 799 struct stmmac_priv *priv = netdev_priv(dev); 800 u32 support = WAKE_MAGIC | WAKE_UCAST; 801 802 if (!device_can_wakeup(priv->device)) 803 return -EOPNOTSUPP; 804 805 if (!priv->plat->pmt) { 806 int ret = phylink_ethtool_set_wol(priv->phylink, wol); 807 808 if (!ret) 809 device_set_wakeup_enable(priv->device, !!wol->wolopts); 810 return ret; 811 } 812 813 /* By default almost all GMAC devices support the WoL via 814 * magic frame but we can disable it if the HW capability 815 * register shows no support for pmt_magic_frame. */ 816 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame)) 817 wol->wolopts &= ~WAKE_MAGIC; 818 819 if (wol->wolopts & ~support) 820 return -EINVAL; 821 822 if (wol->wolopts) { 823 pr_info("stmmac: wakeup enable\n"); 824 device_set_wakeup_enable(priv->device, 1); 825 /* Avoid unbalanced enable_irq_wake calls */ 826 if (priv->wol_irq_disabled) 827 enable_irq_wake(priv->wol_irq); 828 priv->wol_irq_disabled = false; 829 } else { 830 device_set_wakeup_enable(priv->device, 0); 831 /* Avoid unbalanced disable_irq_wake calls */ 832 if (!priv->wol_irq_disabled) 833 disable_irq_wake(priv->wol_irq); 834 priv->wol_irq_disabled = true; 835 } 836 837 mutex_lock(&priv->lock); 838 priv->wolopts = wol->wolopts; 839 mutex_unlock(&priv->lock); 840 841 return 0; 842 } 843 844 static int stmmac_ethtool_op_get_eee(struct net_device *dev, 845 struct ethtool_eee *edata) 846 { 847 struct stmmac_priv *priv = netdev_priv(dev); 848 849 if (!priv->dma_cap.eee) 850 return -EOPNOTSUPP; 851 852 edata->eee_enabled = priv->eee_enabled; 853 edata->eee_active = priv->eee_active; 854 edata->tx_lpi_timer = priv->tx_lpi_timer; 855 edata->tx_lpi_enabled = priv->tx_lpi_enabled; 856 857 return phylink_ethtool_get_eee(priv->phylink, edata); 858 } 859 860 static int stmmac_ethtool_op_set_eee(struct net_device *dev, 861 struct ethtool_eee *edata) 862 { 863 struct stmmac_priv *priv = netdev_priv(dev); 864 int ret; 865 866 if (!priv->dma_cap.eee) 867 return -EOPNOTSUPP; 868 869 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled) 870 netdev_warn(priv->dev, 871 "Setting EEE tx-lpi is not supported\n"); 872 873 if (!edata->eee_enabled) 874 stmmac_disable_eee_mode(priv); 875 876 ret = phylink_ethtool_set_eee(priv->phylink, edata); 877 if (ret) 878 return ret; 879 880 if (edata->eee_enabled && 881 priv->tx_lpi_timer != edata->tx_lpi_timer) { 882 priv->tx_lpi_timer = edata->tx_lpi_timer; 883 stmmac_eee_init(priv); 884 } 885 886 return 0; 887 } 888 889 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv) 890 { 891 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 892 893 if (!clk) { 894 clk = priv->plat->clk_ref_rate; 895 if (!clk) 896 return 0; 897 } 898 899 return (usec * (clk / 1000000)) / 256; 900 } 901 902 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv) 903 { 904 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk); 905 906 if (!clk) { 907 clk = priv->plat->clk_ref_rate; 908 if (!clk) 909 return 0; 910 } 911 912 return (riwt * 256) / (clk / 1000000); 913 } 914 915 static int __stmmac_get_coalesce(struct net_device *dev, 916 struct ethtool_coalesce *ec, 917 int queue) 918 { 919 struct stmmac_priv *priv = netdev_priv(dev); 920 u32 max_cnt; 921 u32 rx_cnt; 922 u32 tx_cnt; 923 924 rx_cnt = priv->plat->rx_queues_to_use; 925 tx_cnt = priv->plat->tx_queues_to_use; 926 max_cnt = max(rx_cnt, tx_cnt); 927 928 if (queue < 0) 929 queue = 0; 930 else if (queue >= max_cnt) 931 return -EINVAL; 932 933 if (queue < tx_cnt) { 934 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue]; 935 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue]; 936 } else { 937 ec->tx_coalesce_usecs = 0; 938 ec->tx_max_coalesced_frames = 0; 939 } 940 941 if (priv->use_riwt && queue < rx_cnt) { 942 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue]; 943 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue], 944 priv); 945 } else { 946 ec->rx_max_coalesced_frames = 0; 947 ec->rx_coalesce_usecs = 0; 948 } 949 950 return 0; 951 } 952 953 static int stmmac_get_coalesce(struct net_device *dev, 954 struct ethtool_coalesce *ec, 955 struct kernel_ethtool_coalesce *kernel_coal, 956 struct netlink_ext_ack *extack) 957 { 958 return __stmmac_get_coalesce(dev, ec, -1); 959 } 960 961 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue, 962 struct ethtool_coalesce *ec) 963 { 964 return __stmmac_get_coalesce(dev, ec, queue); 965 } 966 967 static int __stmmac_set_coalesce(struct net_device *dev, 968 struct ethtool_coalesce *ec, 969 int queue) 970 { 971 struct stmmac_priv *priv = netdev_priv(dev); 972 bool all_queues = false; 973 unsigned int rx_riwt; 974 u32 max_cnt; 975 u32 rx_cnt; 976 u32 tx_cnt; 977 978 rx_cnt = priv->plat->rx_queues_to_use; 979 tx_cnt = priv->plat->tx_queues_to_use; 980 max_cnt = max(rx_cnt, tx_cnt); 981 982 if (queue < 0) 983 all_queues = true; 984 else if (queue >= max_cnt) 985 return -EINVAL; 986 987 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) { 988 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv); 989 990 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT)) 991 return -EINVAL; 992 993 if (all_queues) { 994 int i; 995 996 for (i = 0; i < rx_cnt; i++) { 997 priv->rx_riwt[i] = rx_riwt; 998 stmmac_rx_watchdog(priv, priv->ioaddr, 999 rx_riwt, i); 1000 priv->rx_coal_frames[i] = 1001 ec->rx_max_coalesced_frames; 1002 } 1003 } else if (queue < rx_cnt) { 1004 priv->rx_riwt[queue] = rx_riwt; 1005 stmmac_rx_watchdog(priv, priv->ioaddr, 1006 rx_riwt, queue); 1007 priv->rx_coal_frames[queue] = 1008 ec->rx_max_coalesced_frames; 1009 } 1010 } 1011 1012 if ((ec->tx_coalesce_usecs == 0) && 1013 (ec->tx_max_coalesced_frames == 0)) 1014 return -EINVAL; 1015 1016 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) || 1017 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES)) 1018 return -EINVAL; 1019 1020 if (all_queues) { 1021 int i; 1022 1023 for (i = 0; i < tx_cnt; i++) { 1024 priv->tx_coal_frames[i] = 1025 ec->tx_max_coalesced_frames; 1026 priv->tx_coal_timer[i] = 1027 ec->tx_coalesce_usecs; 1028 } 1029 } else if (queue < tx_cnt) { 1030 priv->tx_coal_frames[queue] = 1031 ec->tx_max_coalesced_frames; 1032 priv->tx_coal_timer[queue] = 1033 ec->tx_coalesce_usecs; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int stmmac_set_coalesce(struct net_device *dev, 1040 struct ethtool_coalesce *ec, 1041 struct kernel_ethtool_coalesce *kernel_coal, 1042 struct netlink_ext_ack *extack) 1043 { 1044 return __stmmac_set_coalesce(dev, ec, -1); 1045 } 1046 1047 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue, 1048 struct ethtool_coalesce *ec) 1049 { 1050 return __stmmac_set_coalesce(dev, ec, queue); 1051 } 1052 1053 static int stmmac_get_rxnfc(struct net_device *dev, 1054 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1055 { 1056 struct stmmac_priv *priv = netdev_priv(dev); 1057 1058 switch (rxnfc->cmd) { 1059 case ETHTOOL_GRXRINGS: 1060 rxnfc->data = priv->plat->rx_queues_to_use; 1061 break; 1062 default: 1063 return -EOPNOTSUPP; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static u32 stmmac_get_rxfh_key_size(struct net_device *dev) 1070 { 1071 struct stmmac_priv *priv = netdev_priv(dev); 1072 1073 return sizeof(priv->rss.key); 1074 } 1075 1076 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev) 1077 { 1078 struct stmmac_priv *priv = netdev_priv(dev); 1079 1080 return ARRAY_SIZE(priv->rss.table); 1081 } 1082 1083 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1084 u8 *hfunc) 1085 { 1086 struct stmmac_priv *priv = netdev_priv(dev); 1087 int i; 1088 1089 if (indir) { 1090 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1091 indir[i] = priv->rss.table[i]; 1092 } 1093 1094 if (key) 1095 memcpy(key, priv->rss.key, sizeof(priv->rss.key)); 1096 if (hfunc) 1097 *hfunc = ETH_RSS_HASH_TOP; 1098 1099 return 0; 1100 } 1101 1102 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir, 1103 const u8 *key, const u8 hfunc) 1104 { 1105 struct stmmac_priv *priv = netdev_priv(dev); 1106 int i; 1107 1108 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP)) 1109 return -EOPNOTSUPP; 1110 1111 if (indir) { 1112 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 1113 priv->rss.table[i] = indir[i]; 1114 } 1115 1116 if (key) 1117 memcpy(priv->rss.key, key, sizeof(priv->rss.key)); 1118 1119 return stmmac_rss_configure(priv, priv->hw, &priv->rss, 1120 priv->plat->rx_queues_to_use); 1121 } 1122 1123 static void stmmac_get_channels(struct net_device *dev, 1124 struct ethtool_channels *chan) 1125 { 1126 struct stmmac_priv *priv = netdev_priv(dev); 1127 1128 chan->rx_count = priv->plat->rx_queues_to_use; 1129 chan->tx_count = priv->plat->tx_queues_to_use; 1130 chan->max_rx = priv->dma_cap.number_rx_queues; 1131 chan->max_tx = priv->dma_cap.number_tx_queues; 1132 } 1133 1134 static int stmmac_set_channels(struct net_device *dev, 1135 struct ethtool_channels *chan) 1136 { 1137 struct stmmac_priv *priv = netdev_priv(dev); 1138 1139 if (chan->rx_count > priv->dma_cap.number_rx_queues || 1140 chan->tx_count > priv->dma_cap.number_tx_queues || 1141 !chan->rx_count || !chan->tx_count) 1142 return -EINVAL; 1143 1144 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count); 1145 } 1146 1147 static int stmmac_get_ts_info(struct net_device *dev, 1148 struct ethtool_ts_info *info) 1149 { 1150 struct stmmac_priv *priv = netdev_priv(dev); 1151 1152 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) { 1153 1154 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1155 SOF_TIMESTAMPING_TX_HARDWARE | 1156 SOF_TIMESTAMPING_RX_SOFTWARE | 1157 SOF_TIMESTAMPING_RX_HARDWARE | 1158 SOF_TIMESTAMPING_SOFTWARE | 1159 SOF_TIMESTAMPING_RAW_HARDWARE; 1160 1161 if (priv->ptp_clock) 1162 info->phc_index = ptp_clock_index(priv->ptp_clock); 1163 1164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1165 1166 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) | 1167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1168 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1169 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1170 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1171 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1172 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1173 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1174 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1175 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 1176 (1 << HWTSTAMP_FILTER_ALL)); 1177 return 0; 1178 } else 1179 return ethtool_op_get_ts_info(dev, info); 1180 } 1181 1182 static int stmmac_get_tunable(struct net_device *dev, 1183 const struct ethtool_tunable *tuna, void *data) 1184 { 1185 struct stmmac_priv *priv = netdev_priv(dev); 1186 int ret = 0; 1187 1188 switch (tuna->id) { 1189 case ETHTOOL_RX_COPYBREAK: 1190 *(u32 *)data = priv->rx_copybreak; 1191 break; 1192 default: 1193 ret = -EINVAL; 1194 break; 1195 } 1196 1197 return ret; 1198 } 1199 1200 static int stmmac_set_tunable(struct net_device *dev, 1201 const struct ethtool_tunable *tuna, 1202 const void *data) 1203 { 1204 struct stmmac_priv *priv = netdev_priv(dev); 1205 int ret = 0; 1206 1207 switch (tuna->id) { 1208 case ETHTOOL_RX_COPYBREAK: 1209 priv->rx_copybreak = *(u32 *)data; 1210 break; 1211 default: 1212 ret = -EINVAL; 1213 break; 1214 } 1215 1216 return ret; 1217 } 1218 1219 static const struct ethtool_ops stmmac_ethtool_ops = { 1220 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1221 ETHTOOL_COALESCE_MAX_FRAMES, 1222 .begin = stmmac_check_if_running, 1223 .get_drvinfo = stmmac_ethtool_getdrvinfo, 1224 .get_msglevel = stmmac_ethtool_getmsglevel, 1225 .set_msglevel = stmmac_ethtool_setmsglevel, 1226 .get_regs = stmmac_ethtool_gregs, 1227 .get_regs_len = stmmac_ethtool_get_regs_len, 1228 .get_link = ethtool_op_get_link, 1229 .nway_reset = stmmac_nway_reset, 1230 .get_ringparam = stmmac_get_ringparam, 1231 .set_ringparam = stmmac_set_ringparam, 1232 .get_pauseparam = stmmac_get_pauseparam, 1233 .set_pauseparam = stmmac_set_pauseparam, 1234 .self_test = stmmac_selftest_run, 1235 .get_ethtool_stats = stmmac_get_ethtool_stats, 1236 .get_strings = stmmac_get_strings, 1237 .get_wol = stmmac_get_wol, 1238 .set_wol = stmmac_set_wol, 1239 .get_eee = stmmac_ethtool_op_get_eee, 1240 .set_eee = stmmac_ethtool_op_set_eee, 1241 .get_sset_count = stmmac_get_sset_count, 1242 .get_rxnfc = stmmac_get_rxnfc, 1243 .get_rxfh_key_size = stmmac_get_rxfh_key_size, 1244 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size, 1245 .get_rxfh = stmmac_get_rxfh, 1246 .set_rxfh = stmmac_set_rxfh, 1247 .get_ts_info = stmmac_get_ts_info, 1248 .get_coalesce = stmmac_get_coalesce, 1249 .set_coalesce = stmmac_set_coalesce, 1250 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce, 1251 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce, 1252 .get_channels = stmmac_get_channels, 1253 .set_channels = stmmac_set_channels, 1254 .get_tunable = stmmac_get_tunable, 1255 .set_tunable = stmmac_set_tunable, 1256 .get_link_ksettings = stmmac_ethtool_get_link_ksettings, 1257 .set_link_ksettings = stmmac_ethtool_set_link_ksettings, 1258 }; 1259 1260 void stmmac_set_ethtool_ops(struct net_device *netdev) 1261 { 1262 netdev->ethtool_ops = &stmmac_ethtool_ops; 1263 } 1264