1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 #define DRV_MODULE_VERSION "Jan_2016" 14 15 #include <linux/clk.h> 16 #include <linux/hrtimer.h> 17 #include <linux/if_vlan.h> 18 #include <linux/stmmac.h> 19 #include <linux/phylink.h> 20 #include <linux/pci.h> 21 #include "common.h" 22 #include <linux/ptp_clock_kernel.h> 23 #include <linux/net_tstamp.h> 24 #include <linux/reset.h> 25 #include <net/page_pool.h> 26 27 struct stmmac_resources { 28 void __iomem *addr; 29 u8 mac[ETH_ALEN]; 30 int wol_irq; 31 int lpi_irq; 32 int irq; 33 int sfty_ce_irq; 34 int sfty_ue_irq; 35 int rx_irq[MTL_MAX_RX_QUEUES]; 36 int tx_irq[MTL_MAX_TX_QUEUES]; 37 }; 38 39 enum stmmac_txbuf_type { 40 STMMAC_TXBUF_T_SKB, 41 STMMAC_TXBUF_T_XDP_TX, 42 STMMAC_TXBUF_T_XDP_NDO, 43 }; 44 45 struct stmmac_tx_info { 46 dma_addr_t buf; 47 bool map_as_page; 48 unsigned len; 49 bool last_segment; 50 bool is_jumbo; 51 enum stmmac_txbuf_type buf_type; 52 }; 53 54 #define STMMAC_TBS_AVAIL BIT(0) 55 #define STMMAC_TBS_EN BIT(1) 56 57 /* Frequently used values are kept adjacent for cache effect */ 58 struct stmmac_tx_queue { 59 u32 tx_count_frames; 60 int tbs; 61 struct hrtimer txtimer; 62 u32 queue_index; 63 struct stmmac_priv *priv_data; 64 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 65 struct dma_edesc *dma_entx; 66 struct dma_desc *dma_tx; 67 union { 68 struct sk_buff **tx_skbuff; 69 struct xdp_frame **xdpf; 70 }; 71 struct stmmac_tx_info *tx_skbuff_dma; 72 unsigned int cur_tx; 73 unsigned int dirty_tx; 74 dma_addr_t dma_tx_phy; 75 u32 tx_tail_addr; 76 u32 mss; 77 }; 78 79 struct stmmac_rx_buffer { 80 union { 81 struct { 82 struct page *page; 83 dma_addr_t addr; 84 __u32 page_offset; 85 }; 86 struct xdp_buff *xdp; 87 }; 88 struct page *sec_page; 89 dma_addr_t sec_addr; 90 }; 91 92 struct stmmac_rx_queue { 93 u32 rx_count_frames; 94 u32 queue_index; 95 struct xdp_rxq_info xdp_rxq; 96 struct xsk_buff_pool *xsk_pool; 97 struct page_pool *page_pool; 98 struct stmmac_rx_buffer *buf_pool; 99 struct stmmac_priv *priv_data; 100 struct dma_extended_desc *dma_erx; 101 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 102 unsigned int cur_rx; 103 unsigned int dirty_rx; 104 unsigned int buf_alloc_num; 105 u32 rx_zeroc_thresh; 106 dma_addr_t dma_rx_phy; 107 u32 rx_tail_addr; 108 unsigned int state_saved; 109 struct { 110 struct sk_buff *skb; 111 unsigned int len; 112 unsigned int error; 113 } state; 114 }; 115 116 struct stmmac_channel { 117 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 118 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 119 struct stmmac_priv *priv_data; 120 spinlock_t lock; 121 u32 index; 122 }; 123 124 struct stmmac_tc_entry { 125 bool in_use; 126 bool in_hw; 127 bool is_last; 128 bool is_frag; 129 void *frag_ptr; 130 unsigned int table_pos; 131 u32 handle; 132 u32 prio; 133 struct { 134 u32 match_data; 135 u32 match_en; 136 u8 af:1; 137 u8 rf:1; 138 u8 im:1; 139 u8 nc:1; 140 u8 res1:4; 141 u8 frame_offset; 142 u8 ok_index; 143 u8 dma_ch_no; 144 u32 res2; 145 } __packed val; 146 }; 147 148 #define STMMAC_PPS_MAX 4 149 struct stmmac_pps_cfg { 150 bool available; 151 struct timespec64 start; 152 struct timespec64 period; 153 }; 154 155 struct stmmac_rss { 156 int enable; 157 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 158 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 159 }; 160 161 #define STMMAC_FLOW_ACTION_DROP BIT(0) 162 struct stmmac_flow_entry { 163 unsigned long cookie; 164 unsigned long action; 165 u8 ip_proto; 166 int in_use; 167 int idx; 168 int is_l4; 169 }; 170 171 struct stmmac_priv { 172 /* Frequently used values are kept adjacent for cache effect */ 173 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 174 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 175 u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; 176 177 int tx_coalesce; 178 int hwts_tx_en; 179 bool tx_path_in_lpi_mode; 180 bool tso; 181 int sph; 182 int sph_cap; 183 u32 sarc_type; 184 185 unsigned int dma_buf_sz; 186 unsigned int rx_copybreak; 187 u32 rx_riwt[MTL_MAX_TX_QUEUES]; 188 int hwts_rx_en; 189 190 void __iomem *ioaddr; 191 struct net_device *dev; 192 struct device *device; 193 struct mac_device_info *hw; 194 int (*hwif_quirks)(struct stmmac_priv *priv); 195 struct mutex lock; 196 197 /* RX Queue */ 198 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 199 unsigned int dma_rx_size; 200 201 /* TX Queue */ 202 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 203 unsigned int dma_tx_size; 204 205 /* Generic channel for NAPI */ 206 struct stmmac_channel channel[STMMAC_CH_MAX]; 207 208 int speed; 209 unsigned int flow_ctrl; 210 unsigned int pause; 211 struct mii_bus *mii; 212 int mii_irq[PHY_MAX_ADDR]; 213 214 struct phylink_config phylink_config; 215 struct phylink *phylink; 216 217 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 218 struct stmmac_safety_stats sstats; 219 struct plat_stmmacenet_data *plat; 220 struct dma_features dma_cap; 221 struct stmmac_counters mmc; 222 int hw_cap_support; 223 int synopsys_id; 224 u32 msg_enable; 225 int wolopts; 226 int wol_irq; 227 int clk_csr; 228 struct timer_list eee_ctrl_timer; 229 int lpi_irq; 230 int eee_enabled; 231 int eee_active; 232 int tx_lpi_timer; 233 int tx_lpi_enabled; 234 int eee_tw_timer; 235 bool eee_sw_timer_en; 236 unsigned int mode; 237 unsigned int chain_mode; 238 int extend_desc; 239 struct hwtstamp_config tstamp_config; 240 struct ptp_clock *ptp_clock; 241 struct ptp_clock_info ptp_clock_ops; 242 unsigned int default_addend; 243 u32 sub_second_inc; 244 u32 systime_flags; 245 u32 adv_ts; 246 int use_riwt; 247 int irq_wake; 248 spinlock_t ptp_lock; 249 void __iomem *mmcaddr; 250 void __iomem *ptpaddr; 251 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 252 int sfty_ce_irq; 253 int sfty_ue_irq; 254 int rx_irq[MTL_MAX_RX_QUEUES]; 255 int tx_irq[MTL_MAX_TX_QUEUES]; 256 /*irq name */ 257 char int_name_mac[IFNAMSIZ + 9]; 258 char int_name_wol[IFNAMSIZ + 9]; 259 char int_name_lpi[IFNAMSIZ + 9]; 260 char int_name_sfty_ce[IFNAMSIZ + 10]; 261 char int_name_sfty_ue[IFNAMSIZ + 10]; 262 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; 263 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 264 265 #ifdef CONFIG_DEBUG_FS 266 struct dentry *dbgfs_dir; 267 #endif 268 269 unsigned long state; 270 struct workqueue_struct *wq; 271 struct work_struct service_task; 272 273 /* Workqueue for handling FPE hand-shaking */ 274 unsigned long fpe_task_state; 275 struct workqueue_struct *fpe_wq; 276 struct work_struct fpe_task; 277 char wq_name[IFNAMSIZ + 4]; 278 279 /* TC Handling */ 280 unsigned int tc_entries_max; 281 unsigned int tc_off_max; 282 struct stmmac_tc_entry *tc_entries; 283 unsigned int flow_entries_max; 284 struct stmmac_flow_entry *flow_entries; 285 286 /* Pulse Per Second output */ 287 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 288 289 /* Receive Side Scaling */ 290 struct stmmac_rss rss; 291 292 /* XDP BPF Program */ 293 unsigned long *af_xdp_zc_qps; 294 struct bpf_prog *xdp_prog; 295 }; 296 297 enum stmmac_state { 298 STMMAC_DOWN, 299 STMMAC_RESET_REQUESTED, 300 STMMAC_RESETING, 301 STMMAC_SERVICE_SCHED, 302 }; 303 304 int stmmac_mdio_unregister(struct net_device *ndev); 305 int stmmac_mdio_register(struct net_device *ndev); 306 int stmmac_mdio_reset(struct mii_bus *mii); 307 void stmmac_set_ethtool_ops(struct net_device *netdev); 308 309 void stmmac_ptp_register(struct stmmac_priv *priv); 310 void stmmac_ptp_unregister(struct stmmac_priv *priv); 311 int stmmac_open(struct net_device *dev); 312 int stmmac_release(struct net_device *dev); 313 int stmmac_resume(struct device *dev); 314 int stmmac_suspend(struct device *dev); 315 int stmmac_dvr_remove(struct device *dev); 316 int stmmac_dvr_probe(struct device *device, 317 struct plat_stmmacenet_data *plat_dat, 318 struct stmmac_resources *res); 319 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 320 bool stmmac_eee_init(struct stmmac_priv *priv); 321 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 322 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 323 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); 324 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable); 325 326 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 327 { 328 return !!priv->xdp_prog; 329 } 330 331 static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) 332 { 333 if (stmmac_xdp_is_enabled(priv)) 334 return XDP_PACKET_HEADROOM; 335 336 return 0; 337 } 338 339 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue); 340 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue); 341 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags); 342 343 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 344 void stmmac_selftest_run(struct net_device *dev, 345 struct ethtool_test *etest, u64 *buf); 346 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 347 int stmmac_selftest_get_count(struct stmmac_priv *priv); 348 #else 349 static inline void stmmac_selftest_run(struct net_device *dev, 350 struct ethtool_test *etest, u64 *buf) 351 { 352 /* Not enabled */ 353 } 354 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 355 u8 *data) 356 { 357 /* Not enabled */ 358 } 359 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 360 { 361 return -EOPNOTSUPP; 362 } 363 #endif /* CONFIG_STMMAC_SELFTESTS */ 364 365 #endif /* __STMMAC_H__ */ 366