1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 #define DRV_MODULE_VERSION "Jan_2016" 14 15 #include <linux/clk.h> 16 #include <linux/hrtimer.h> 17 #include <linux/if_vlan.h> 18 #include <linux/stmmac.h> 19 #include <linux/phylink.h> 20 #include <linux/pci.h> 21 #include "common.h" 22 #include <linux/ptp_clock_kernel.h> 23 #include <linux/net_tstamp.h> 24 #include <linux/reset.h> 25 #include <net/page_pool.h> 26 27 struct stmmac_resources { 28 void __iomem *addr; 29 const char *mac; 30 int wol_irq; 31 int lpi_irq; 32 int irq; 33 int sfty_ce_irq; 34 int sfty_ue_irq; 35 int rx_irq[MTL_MAX_RX_QUEUES]; 36 int tx_irq[MTL_MAX_TX_QUEUES]; 37 }; 38 39 enum stmmac_txbuf_type { 40 STMMAC_TXBUF_T_SKB, 41 STMMAC_TXBUF_T_XDP_TX, 42 STMMAC_TXBUF_T_XDP_NDO, 43 }; 44 45 struct stmmac_tx_info { 46 dma_addr_t buf; 47 bool map_as_page; 48 unsigned len; 49 bool last_segment; 50 bool is_jumbo; 51 enum stmmac_txbuf_type buf_type; 52 }; 53 54 #define STMMAC_TBS_AVAIL BIT(0) 55 #define STMMAC_TBS_EN BIT(1) 56 57 /* Frequently used values are kept adjacent for cache effect */ 58 struct stmmac_tx_queue { 59 u32 tx_count_frames; 60 int tbs; 61 struct hrtimer txtimer; 62 u32 queue_index; 63 struct stmmac_priv *priv_data; 64 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 65 struct dma_edesc *dma_entx; 66 struct dma_desc *dma_tx; 67 union { 68 struct sk_buff **tx_skbuff; 69 struct xdp_frame **xdpf; 70 }; 71 struct stmmac_tx_info *tx_skbuff_dma; 72 unsigned int cur_tx; 73 unsigned int dirty_tx; 74 dma_addr_t dma_tx_phy; 75 u32 tx_tail_addr; 76 u32 mss; 77 }; 78 79 struct stmmac_rx_buffer { 80 struct page *page; 81 dma_addr_t addr; 82 __u32 page_offset; 83 struct page *sec_page; 84 dma_addr_t sec_addr; 85 }; 86 87 struct stmmac_rx_queue { 88 u32 rx_count_frames; 89 u32 queue_index; 90 struct xdp_rxq_info xdp_rxq; 91 struct page_pool *page_pool; 92 struct stmmac_rx_buffer *buf_pool; 93 struct stmmac_priv *priv_data; 94 struct dma_extended_desc *dma_erx; 95 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 96 unsigned int cur_rx; 97 unsigned int dirty_rx; 98 u32 rx_zeroc_thresh; 99 dma_addr_t dma_rx_phy; 100 u32 rx_tail_addr; 101 unsigned int state_saved; 102 struct { 103 struct sk_buff *skb; 104 unsigned int len; 105 unsigned int error; 106 } state; 107 }; 108 109 struct stmmac_channel { 110 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 111 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 112 struct stmmac_priv *priv_data; 113 spinlock_t lock; 114 u32 index; 115 }; 116 117 struct stmmac_tc_entry { 118 bool in_use; 119 bool in_hw; 120 bool is_last; 121 bool is_frag; 122 void *frag_ptr; 123 unsigned int table_pos; 124 u32 handle; 125 u32 prio; 126 struct { 127 u32 match_data; 128 u32 match_en; 129 u8 af:1; 130 u8 rf:1; 131 u8 im:1; 132 u8 nc:1; 133 u8 res1:4; 134 u8 frame_offset; 135 u8 ok_index; 136 u8 dma_ch_no; 137 u32 res2; 138 } __packed val; 139 }; 140 141 #define STMMAC_PPS_MAX 4 142 struct stmmac_pps_cfg { 143 bool available; 144 struct timespec64 start; 145 struct timespec64 period; 146 }; 147 148 struct stmmac_rss { 149 int enable; 150 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 151 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 152 }; 153 154 #define STMMAC_FLOW_ACTION_DROP BIT(0) 155 struct stmmac_flow_entry { 156 unsigned long cookie; 157 unsigned long action; 158 u8 ip_proto; 159 int in_use; 160 int idx; 161 int is_l4; 162 }; 163 164 struct stmmac_priv { 165 /* Frequently used values are kept adjacent for cache effect */ 166 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 167 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 168 u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; 169 170 int tx_coalesce; 171 int hwts_tx_en; 172 bool tx_path_in_lpi_mode; 173 bool tso; 174 int sph; 175 int sph_cap; 176 u32 sarc_type; 177 178 unsigned int dma_buf_sz; 179 unsigned int rx_copybreak; 180 u32 rx_riwt[MTL_MAX_TX_QUEUES]; 181 int hwts_rx_en; 182 183 void __iomem *ioaddr; 184 struct net_device *dev; 185 struct device *device; 186 struct mac_device_info *hw; 187 int (*hwif_quirks)(struct stmmac_priv *priv); 188 struct mutex lock; 189 190 /* RX Queue */ 191 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 192 unsigned int dma_rx_size; 193 194 /* TX Queue */ 195 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 196 unsigned int dma_tx_size; 197 198 /* Generic channel for NAPI */ 199 struct stmmac_channel channel[STMMAC_CH_MAX]; 200 201 int speed; 202 unsigned int flow_ctrl; 203 unsigned int pause; 204 struct mii_bus *mii; 205 int mii_irq[PHY_MAX_ADDR]; 206 207 struct phylink_config phylink_config; 208 struct phylink *phylink; 209 210 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 211 struct stmmac_safety_stats sstats; 212 struct plat_stmmacenet_data *plat; 213 struct dma_features dma_cap; 214 struct stmmac_counters mmc; 215 int hw_cap_support; 216 int synopsys_id; 217 u32 msg_enable; 218 int wolopts; 219 int wol_irq; 220 int clk_csr; 221 struct timer_list eee_ctrl_timer; 222 int lpi_irq; 223 int eee_enabled; 224 int eee_active; 225 int tx_lpi_timer; 226 int tx_lpi_enabled; 227 int eee_tw_timer; 228 bool eee_sw_timer_en; 229 unsigned int mode; 230 unsigned int chain_mode; 231 int extend_desc; 232 struct hwtstamp_config tstamp_config; 233 struct ptp_clock *ptp_clock; 234 struct ptp_clock_info ptp_clock_ops; 235 unsigned int default_addend; 236 u32 sub_second_inc; 237 u32 systime_flags; 238 u32 adv_ts; 239 int use_riwt; 240 int irq_wake; 241 spinlock_t ptp_lock; 242 void __iomem *mmcaddr; 243 void __iomem *ptpaddr; 244 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 245 int sfty_ce_irq; 246 int sfty_ue_irq; 247 int rx_irq[MTL_MAX_RX_QUEUES]; 248 int tx_irq[MTL_MAX_TX_QUEUES]; 249 /*irq name */ 250 char int_name_mac[IFNAMSIZ + 9]; 251 char int_name_wol[IFNAMSIZ + 9]; 252 char int_name_lpi[IFNAMSIZ + 9]; 253 char int_name_sfty_ce[IFNAMSIZ + 10]; 254 char int_name_sfty_ue[IFNAMSIZ + 10]; 255 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; 256 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 257 258 #ifdef CONFIG_DEBUG_FS 259 struct dentry *dbgfs_dir; 260 #endif 261 262 unsigned long state; 263 struct workqueue_struct *wq; 264 struct work_struct service_task; 265 266 /* Workqueue for handling FPE hand-shaking */ 267 unsigned long fpe_task_state; 268 struct workqueue_struct *fpe_wq; 269 struct work_struct fpe_task; 270 char wq_name[IFNAMSIZ + 4]; 271 272 /* TC Handling */ 273 unsigned int tc_entries_max; 274 unsigned int tc_off_max; 275 struct stmmac_tc_entry *tc_entries; 276 unsigned int flow_entries_max; 277 struct stmmac_flow_entry *flow_entries; 278 279 /* Pulse Per Second output */ 280 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 281 282 /* Receive Side Scaling */ 283 struct stmmac_rss rss; 284 285 /* XDP BPF Program */ 286 struct bpf_prog *xdp_prog; 287 }; 288 289 enum stmmac_state { 290 STMMAC_DOWN, 291 STMMAC_RESET_REQUESTED, 292 STMMAC_RESETING, 293 STMMAC_SERVICE_SCHED, 294 }; 295 296 int stmmac_mdio_unregister(struct net_device *ndev); 297 int stmmac_mdio_register(struct net_device *ndev); 298 int stmmac_mdio_reset(struct mii_bus *mii); 299 void stmmac_set_ethtool_ops(struct net_device *netdev); 300 301 void stmmac_ptp_register(struct stmmac_priv *priv); 302 void stmmac_ptp_unregister(struct stmmac_priv *priv); 303 int stmmac_open(struct net_device *dev); 304 int stmmac_release(struct net_device *dev); 305 int stmmac_resume(struct device *dev); 306 int stmmac_suspend(struct device *dev); 307 int stmmac_dvr_remove(struct device *dev); 308 int stmmac_dvr_probe(struct device *device, 309 struct plat_stmmacenet_data *plat_dat, 310 struct stmmac_resources *res); 311 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 312 bool stmmac_eee_init(struct stmmac_priv *priv); 313 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 314 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 315 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); 316 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable); 317 318 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 319 { 320 return !!priv->xdp_prog; 321 } 322 323 static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) 324 { 325 if (stmmac_xdp_is_enabled(priv)) 326 return XDP_PACKET_HEADROOM; 327 328 return 0; 329 } 330 331 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 332 void stmmac_selftest_run(struct net_device *dev, 333 struct ethtool_test *etest, u64 *buf); 334 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 335 int stmmac_selftest_get_count(struct stmmac_priv *priv); 336 #else 337 static inline void stmmac_selftest_run(struct net_device *dev, 338 struct ethtool_test *etest, u64 *buf) 339 { 340 /* Not enabled */ 341 } 342 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 343 u8 *data) 344 { 345 /* Not enabled */ 346 } 347 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 348 { 349 return -EOPNOTSUPP; 350 } 351 #endif /* CONFIG_STMMAC_SELFTESTS */ 352 353 #endif /* __STMMAC_H__ */ 354