1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 The full GNU General Public License is included in this distribution in 14 the file called "COPYING". 15 16 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 17 *******************************************************************************/ 18 19 #ifndef __STMMAC_H__ 20 #define __STMMAC_H__ 21 22 #define STMMAC_RESOURCE_NAME "stmmaceth" 23 #define DRV_MODULE_VERSION "Jan_2016" 24 25 #include <linux/clk.h> 26 #include <linux/stmmac.h> 27 #include <linux/phy.h> 28 #include <linux/pci.h> 29 #include "common.h" 30 #include <linux/ptp_clock_kernel.h> 31 #include <linux/net_tstamp.h> 32 #include <linux/reset.h> 33 34 struct stmmac_resources { 35 void __iomem *addr; 36 const char *mac; 37 int wol_irq; 38 int lpi_irq; 39 int irq; 40 }; 41 42 struct stmmac_tx_info { 43 dma_addr_t buf; 44 bool map_as_page; 45 unsigned len; 46 bool last_segment; 47 bool is_jumbo; 48 }; 49 50 /* Frequently used values are kept adjacent for cache effect */ 51 struct stmmac_tx_queue { 52 u32 tx_count_frames; 53 struct timer_list txtimer; 54 u32 queue_index; 55 struct stmmac_priv *priv_data; 56 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 57 struct dma_desc *dma_tx; 58 struct sk_buff **tx_skbuff; 59 struct stmmac_tx_info *tx_skbuff_dma; 60 unsigned int cur_tx; 61 unsigned int dirty_tx; 62 dma_addr_t dma_tx_phy; 63 u32 tx_tail_addr; 64 u32 mss; 65 }; 66 67 struct stmmac_rx_queue { 68 u32 queue_index; 69 struct stmmac_priv *priv_data; 70 struct dma_extended_desc *dma_erx; 71 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 72 struct sk_buff **rx_skbuff; 73 dma_addr_t *rx_skbuff_dma; 74 unsigned int cur_rx; 75 unsigned int dirty_rx; 76 u32 rx_zeroc_thresh; 77 dma_addr_t dma_rx_phy; 78 u32 rx_tail_addr; 79 }; 80 81 struct stmmac_channel { 82 struct napi_struct napi ____cacheline_aligned_in_smp; 83 struct stmmac_priv *priv_data; 84 u32 index; 85 int has_rx; 86 int has_tx; 87 }; 88 89 struct stmmac_tc_entry { 90 bool in_use; 91 bool in_hw; 92 bool is_last; 93 bool is_frag; 94 void *frag_ptr; 95 unsigned int table_pos; 96 u32 handle; 97 u32 prio; 98 struct { 99 u32 match_data; 100 u32 match_en; 101 u8 af:1; 102 u8 rf:1; 103 u8 im:1; 104 u8 nc:1; 105 u8 res1:4; 106 u8 frame_offset; 107 u8 ok_index; 108 u8 dma_ch_no; 109 u32 res2; 110 } __packed val; 111 }; 112 113 #define STMMAC_PPS_MAX 4 114 struct stmmac_pps_cfg { 115 bool available; 116 struct timespec64 start; 117 struct timespec64 period; 118 }; 119 120 struct stmmac_priv { 121 /* Frequently used values are kept adjacent for cache effect */ 122 u32 tx_coal_frames; 123 u32 tx_coal_timer; 124 125 int tx_coalesce; 126 int hwts_tx_en; 127 bool tx_path_in_lpi_mode; 128 bool tso; 129 130 unsigned int dma_buf_sz; 131 unsigned int rx_copybreak; 132 u32 rx_riwt; 133 int hwts_rx_en; 134 135 void __iomem *ioaddr; 136 struct net_device *dev; 137 struct device *device; 138 struct mac_device_info *hw; 139 int (*hwif_quirks)(struct stmmac_priv *priv); 140 struct mutex lock; 141 142 /* RX Queue */ 143 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 144 145 /* TX Queue */ 146 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 147 148 /* Generic channel for NAPI */ 149 struct stmmac_channel channel[STMMAC_CH_MAX]; 150 151 bool oldlink; 152 int speed; 153 int oldduplex; 154 unsigned int flow_ctrl; 155 unsigned int pause; 156 struct mii_bus *mii; 157 int mii_irq[PHY_MAX_ADDR]; 158 159 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 160 struct stmmac_safety_stats sstats; 161 struct plat_stmmacenet_data *plat; 162 struct dma_features dma_cap; 163 struct stmmac_counters mmc; 164 int hw_cap_support; 165 int synopsys_id; 166 u32 msg_enable; 167 int wolopts; 168 int wol_irq; 169 int clk_csr; 170 struct timer_list eee_ctrl_timer; 171 int lpi_irq; 172 int eee_enabled; 173 int eee_active; 174 int tx_lpi_timer; 175 unsigned int mode; 176 unsigned int chain_mode; 177 int extend_desc; 178 struct hwtstamp_config tstamp_config; 179 struct ptp_clock *ptp_clock; 180 struct ptp_clock_info ptp_clock_ops; 181 unsigned int default_addend; 182 u32 sub_second_inc; 183 u32 systime_flags; 184 u32 adv_ts; 185 int use_riwt; 186 int irq_wake; 187 spinlock_t ptp_lock; 188 void __iomem *mmcaddr; 189 void __iomem *ptpaddr; 190 191 #ifdef CONFIG_DEBUG_FS 192 struct dentry *dbgfs_dir; 193 struct dentry *dbgfs_rings_status; 194 struct dentry *dbgfs_dma_cap; 195 #endif 196 197 unsigned long state; 198 struct workqueue_struct *wq; 199 struct work_struct service_task; 200 201 /* TC Handling */ 202 unsigned int tc_entries_max; 203 unsigned int tc_off_max; 204 struct stmmac_tc_entry *tc_entries; 205 206 /* Pulse Per Second output */ 207 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 208 }; 209 210 enum stmmac_state { 211 STMMAC_DOWN, 212 STMMAC_RESET_REQUESTED, 213 STMMAC_RESETING, 214 STMMAC_SERVICE_SCHED, 215 }; 216 217 int stmmac_mdio_unregister(struct net_device *ndev); 218 int stmmac_mdio_register(struct net_device *ndev); 219 int stmmac_mdio_reset(struct mii_bus *mii); 220 void stmmac_set_ethtool_ops(struct net_device *netdev); 221 222 void stmmac_ptp_register(struct stmmac_priv *priv); 223 void stmmac_ptp_unregister(struct stmmac_priv *priv); 224 int stmmac_resume(struct device *dev); 225 int stmmac_suspend(struct device *dev); 226 int stmmac_dvr_remove(struct device *dev); 227 int stmmac_dvr_probe(struct device *device, 228 struct plat_stmmacenet_data *plat_dat, 229 struct stmmac_resources *res); 230 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 231 bool stmmac_eee_init(struct stmmac_priv *priv); 232 233 #endif /* __STMMAC_H__ */ 234