1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 #define DRV_MODULE_VERSION "Jan_2016" 14 15 #include <linux/clk.h> 16 #include <linux/hrtimer.h> 17 #include <linux/if_vlan.h> 18 #include <linux/stmmac.h> 19 #include <linux/phylink.h> 20 #include <linux/pci.h> 21 #include "common.h" 22 #include <linux/ptp_clock_kernel.h> 23 #include <linux/net_tstamp.h> 24 #include <linux/reset.h> 25 #include <net/page_pool.h> 26 27 struct stmmac_resources { 28 void __iomem *addr; 29 const char *mac; 30 int wol_irq; 31 int lpi_irq; 32 int irq; 33 int sfty_ce_irq; 34 int sfty_ue_irq; 35 int rx_irq[MTL_MAX_RX_QUEUES]; 36 int tx_irq[MTL_MAX_TX_QUEUES]; 37 }; 38 39 struct stmmac_tx_info { 40 dma_addr_t buf; 41 bool map_as_page; 42 unsigned len; 43 bool last_segment; 44 bool is_jumbo; 45 }; 46 47 #define STMMAC_TBS_AVAIL BIT(0) 48 #define STMMAC_TBS_EN BIT(1) 49 50 /* Frequently used values are kept adjacent for cache effect */ 51 struct stmmac_tx_queue { 52 u32 tx_count_frames; 53 int tbs; 54 struct hrtimer txtimer; 55 u32 queue_index; 56 struct stmmac_priv *priv_data; 57 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 58 struct dma_edesc *dma_entx; 59 struct dma_desc *dma_tx; 60 struct sk_buff **tx_skbuff; 61 struct stmmac_tx_info *tx_skbuff_dma; 62 unsigned int cur_tx; 63 unsigned int dirty_tx; 64 dma_addr_t dma_tx_phy; 65 u32 tx_tail_addr; 66 u32 mss; 67 }; 68 69 struct stmmac_rx_buffer { 70 struct page *page; 71 dma_addr_t addr; 72 __u32 page_offset; 73 struct page *sec_page; 74 dma_addr_t sec_addr; 75 }; 76 77 struct stmmac_rx_queue { 78 u32 rx_count_frames; 79 u32 queue_index; 80 struct page_pool *page_pool; 81 struct stmmac_rx_buffer *buf_pool; 82 struct stmmac_priv *priv_data; 83 struct dma_extended_desc *dma_erx; 84 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 85 unsigned int cur_rx; 86 unsigned int dirty_rx; 87 u32 rx_zeroc_thresh; 88 dma_addr_t dma_rx_phy; 89 u32 rx_tail_addr; 90 unsigned int state_saved; 91 struct { 92 struct sk_buff *skb; 93 unsigned int len; 94 unsigned int error; 95 } state; 96 }; 97 98 struct stmmac_channel { 99 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 100 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 101 struct stmmac_priv *priv_data; 102 spinlock_t lock; 103 u32 index; 104 }; 105 106 struct stmmac_tc_entry { 107 bool in_use; 108 bool in_hw; 109 bool is_last; 110 bool is_frag; 111 void *frag_ptr; 112 unsigned int table_pos; 113 u32 handle; 114 u32 prio; 115 struct { 116 u32 match_data; 117 u32 match_en; 118 u8 af:1; 119 u8 rf:1; 120 u8 im:1; 121 u8 nc:1; 122 u8 res1:4; 123 u8 frame_offset; 124 u8 ok_index; 125 u8 dma_ch_no; 126 u32 res2; 127 } __packed val; 128 }; 129 130 #define STMMAC_PPS_MAX 4 131 struct stmmac_pps_cfg { 132 bool available; 133 struct timespec64 start; 134 struct timespec64 period; 135 }; 136 137 struct stmmac_rss { 138 int enable; 139 u8 key[STMMAC_RSS_HASH_KEY_SIZE]; 140 u32 table[STMMAC_RSS_MAX_TABLE_SIZE]; 141 }; 142 143 #define STMMAC_FLOW_ACTION_DROP BIT(0) 144 struct stmmac_flow_entry { 145 unsigned long cookie; 146 unsigned long action; 147 u8 ip_proto; 148 int in_use; 149 int idx; 150 int is_l4; 151 }; 152 153 struct stmmac_priv { 154 /* Frequently used values are kept adjacent for cache effect */ 155 u32 tx_coal_frames[MTL_MAX_TX_QUEUES]; 156 u32 tx_coal_timer[MTL_MAX_TX_QUEUES]; 157 u32 rx_coal_frames[MTL_MAX_TX_QUEUES]; 158 159 int tx_coalesce; 160 int hwts_tx_en; 161 bool tx_path_in_lpi_mode; 162 bool tso; 163 int sph; 164 int sph_cap; 165 u32 sarc_type; 166 167 unsigned int dma_buf_sz; 168 unsigned int rx_copybreak; 169 u32 rx_riwt[MTL_MAX_TX_QUEUES]; 170 int hwts_rx_en; 171 172 void __iomem *ioaddr; 173 struct net_device *dev; 174 struct device *device; 175 struct mac_device_info *hw; 176 int (*hwif_quirks)(struct stmmac_priv *priv); 177 struct mutex lock; 178 179 /* RX Queue */ 180 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 181 unsigned int dma_rx_size; 182 183 /* TX Queue */ 184 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 185 unsigned int dma_tx_size; 186 187 /* Generic channel for NAPI */ 188 struct stmmac_channel channel[STMMAC_CH_MAX]; 189 190 int speed; 191 unsigned int flow_ctrl; 192 unsigned int pause; 193 struct mii_bus *mii; 194 int mii_irq[PHY_MAX_ADDR]; 195 196 struct phylink_config phylink_config; 197 struct phylink *phylink; 198 199 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 200 struct stmmac_safety_stats sstats; 201 struct plat_stmmacenet_data *plat; 202 struct dma_features dma_cap; 203 struct stmmac_counters mmc; 204 int hw_cap_support; 205 int synopsys_id; 206 u32 msg_enable; 207 int wolopts; 208 int wol_irq; 209 int clk_csr; 210 struct timer_list eee_ctrl_timer; 211 int lpi_irq; 212 int eee_enabled; 213 int eee_active; 214 int tx_lpi_timer; 215 int tx_lpi_enabled; 216 int eee_tw_timer; 217 bool eee_sw_timer_en; 218 unsigned int mode; 219 unsigned int chain_mode; 220 int extend_desc; 221 struct hwtstamp_config tstamp_config; 222 struct ptp_clock *ptp_clock; 223 struct ptp_clock_info ptp_clock_ops; 224 unsigned int default_addend; 225 u32 sub_second_inc; 226 u32 systime_flags; 227 u32 adv_ts; 228 int use_riwt; 229 int irq_wake; 230 spinlock_t ptp_lock; 231 void __iomem *mmcaddr; 232 void __iomem *ptpaddr; 233 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 234 int sfty_ce_irq; 235 int sfty_ue_irq; 236 int rx_irq[MTL_MAX_RX_QUEUES]; 237 int tx_irq[MTL_MAX_TX_QUEUES]; 238 /*irq name */ 239 char int_name_mac[IFNAMSIZ + 9]; 240 char int_name_wol[IFNAMSIZ + 9]; 241 char int_name_lpi[IFNAMSIZ + 9]; 242 char int_name_sfty_ce[IFNAMSIZ + 10]; 243 char int_name_sfty_ue[IFNAMSIZ + 10]; 244 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14]; 245 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18]; 246 247 #ifdef CONFIG_DEBUG_FS 248 struct dentry *dbgfs_dir; 249 #endif 250 251 unsigned long state; 252 struct workqueue_struct *wq; 253 struct work_struct service_task; 254 255 /* Workqueue for handling FPE hand-shaking */ 256 unsigned long fpe_task_state; 257 struct workqueue_struct *fpe_wq; 258 struct work_struct fpe_task; 259 char wq_name[IFNAMSIZ + 4]; 260 261 /* TC Handling */ 262 unsigned int tc_entries_max; 263 unsigned int tc_off_max; 264 struct stmmac_tc_entry *tc_entries; 265 unsigned int flow_entries_max; 266 struct stmmac_flow_entry *flow_entries; 267 268 /* Pulse Per Second output */ 269 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 270 271 /* Receive Side Scaling */ 272 struct stmmac_rss rss; 273 274 /* XDP BPF Program */ 275 struct bpf_prog *xdp_prog; 276 }; 277 278 enum stmmac_state { 279 STMMAC_DOWN, 280 STMMAC_RESET_REQUESTED, 281 STMMAC_RESETING, 282 STMMAC_SERVICE_SCHED, 283 }; 284 285 int stmmac_mdio_unregister(struct net_device *ndev); 286 int stmmac_mdio_register(struct net_device *ndev); 287 int stmmac_mdio_reset(struct mii_bus *mii); 288 void stmmac_set_ethtool_ops(struct net_device *netdev); 289 290 void stmmac_ptp_register(struct stmmac_priv *priv); 291 void stmmac_ptp_unregister(struct stmmac_priv *priv); 292 int stmmac_open(struct net_device *dev); 293 int stmmac_release(struct net_device *dev); 294 int stmmac_resume(struct device *dev); 295 int stmmac_suspend(struct device *dev); 296 int stmmac_dvr_remove(struct device *dev); 297 int stmmac_dvr_probe(struct device *device, 298 struct plat_stmmacenet_data *plat_dat, 299 struct stmmac_resources *res); 300 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 301 bool stmmac_eee_init(struct stmmac_priv *priv); 302 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); 303 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size); 304 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); 305 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable); 306 307 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) 308 { 309 return !!priv->xdp_prog; 310 } 311 312 static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv) 313 { 314 if (stmmac_xdp_is_enabled(priv)) 315 return XDP_PACKET_HEADROOM; 316 317 return 0; 318 } 319 320 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS) 321 void stmmac_selftest_run(struct net_device *dev, 322 struct ethtool_test *etest, u64 *buf); 323 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data); 324 int stmmac_selftest_get_count(struct stmmac_priv *priv); 325 #else 326 static inline void stmmac_selftest_run(struct net_device *dev, 327 struct ethtool_test *etest, u64 *buf) 328 { 329 /* Not enabled */ 330 } 331 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv, 332 u8 *data) 333 { 334 /* Not enabled */ 335 } 336 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv) 337 { 338 return -EOPNOTSUPP; 339 } 340 #endif /* CONFIG_STMMAC_SELFTESTS */ 341 342 #endif /* __STMMAC_H__ */ 343