1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3   Copyright (C) 2007-2009  STMicroelectronics Ltd
4 
5 
6   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7 *******************************************************************************/
8 
9 #ifndef __STMMAC_H__
10 #define __STMMAC_H__
11 
12 #define STMMAC_RESOURCE_NAME   "stmmaceth"
13 #define DRV_MODULE_VERSION	"Jan_2016"
14 
15 #include <linux/clk.h>
16 #include <linux/hrtimer.h>
17 #include <linux/if_vlan.h>
18 #include <linux/stmmac.h>
19 #include <linux/phylink.h>
20 #include <linux/pci.h>
21 #include "common.h"
22 #include <linux/ptp_clock_kernel.h>
23 #include <linux/net_tstamp.h>
24 #include <linux/reset.h>
25 #include <net/page_pool.h>
26 
27 struct stmmac_resources {
28 	void __iomem *addr;
29 	const char *mac;
30 	int wol_irq;
31 	int lpi_irq;
32 	int irq;
33 };
34 
35 struct stmmac_tx_info {
36 	dma_addr_t buf;
37 	bool map_as_page;
38 	unsigned len;
39 	bool last_segment;
40 	bool is_jumbo;
41 };
42 
43 #define STMMAC_TBS_AVAIL	BIT(0)
44 #define STMMAC_TBS_EN		BIT(1)
45 
46 /* Frequently used values are kept adjacent for cache effect */
47 struct stmmac_tx_queue {
48 	u32 tx_count_frames;
49 	int tbs;
50 	struct hrtimer txtimer;
51 	u32 queue_index;
52 	struct stmmac_priv *priv_data;
53 	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
54 	struct dma_edesc *dma_entx;
55 	struct dma_desc *dma_tx;
56 	struct sk_buff **tx_skbuff;
57 	struct stmmac_tx_info *tx_skbuff_dma;
58 	unsigned int cur_tx;
59 	unsigned int dirty_tx;
60 	dma_addr_t dma_tx_phy;
61 	u32 tx_tail_addr;
62 	u32 mss;
63 };
64 
65 struct stmmac_rx_buffer {
66 	struct page *page;
67 	struct page *sec_page;
68 	dma_addr_t addr;
69 	dma_addr_t sec_addr;
70 };
71 
72 struct stmmac_rx_queue {
73 	u32 rx_count_frames;
74 	u32 queue_index;
75 	struct page_pool *page_pool;
76 	struct stmmac_rx_buffer *buf_pool;
77 	struct stmmac_priv *priv_data;
78 	struct dma_extended_desc *dma_erx;
79 	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
80 	unsigned int cur_rx;
81 	unsigned int dirty_rx;
82 	u32 rx_zeroc_thresh;
83 	dma_addr_t dma_rx_phy;
84 	u32 rx_tail_addr;
85 	unsigned int state_saved;
86 	struct {
87 		struct sk_buff *skb;
88 		unsigned int len;
89 		unsigned int error;
90 	} state;
91 };
92 
93 struct stmmac_channel {
94 	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
95 	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
96 	struct stmmac_priv *priv_data;
97 	spinlock_t lock;
98 	u32 index;
99 };
100 
101 struct stmmac_tc_entry {
102 	bool in_use;
103 	bool in_hw;
104 	bool is_last;
105 	bool is_frag;
106 	void *frag_ptr;
107 	unsigned int table_pos;
108 	u32 handle;
109 	u32 prio;
110 	struct {
111 		u32 match_data;
112 		u32 match_en;
113 		u8 af:1;
114 		u8 rf:1;
115 		u8 im:1;
116 		u8 nc:1;
117 		u8 res1:4;
118 		u8 frame_offset;
119 		u8 ok_index;
120 		u8 dma_ch_no;
121 		u32 res2;
122 	} __packed val;
123 };
124 
125 #define STMMAC_PPS_MAX		4
126 struct stmmac_pps_cfg {
127 	bool available;
128 	struct timespec64 start;
129 	struct timespec64 period;
130 };
131 
132 struct stmmac_rss {
133 	int enable;
134 	u8 key[STMMAC_RSS_HASH_KEY_SIZE];
135 	u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
136 };
137 
138 #define STMMAC_FLOW_ACTION_DROP		BIT(0)
139 struct stmmac_flow_entry {
140 	unsigned long cookie;
141 	unsigned long action;
142 	u8 ip_proto;
143 	int in_use;
144 	int idx;
145 	int is_l4;
146 };
147 
148 struct stmmac_priv {
149 	/* Frequently used values are kept adjacent for cache effect */
150 	u32 tx_coal_frames;
151 	u32 tx_coal_timer;
152 	u32 rx_coal_frames;
153 
154 	int tx_coalesce;
155 	int hwts_tx_en;
156 	bool tx_path_in_lpi_mode;
157 	bool tso;
158 	int sph;
159 	u32 sarc_type;
160 
161 	unsigned int dma_buf_sz;
162 	unsigned int rx_copybreak;
163 	u32 rx_riwt;
164 	int hwts_rx_en;
165 
166 	void __iomem *ioaddr;
167 	struct net_device *dev;
168 	struct device *device;
169 	struct mac_device_info *hw;
170 	int (*hwif_quirks)(struct stmmac_priv *priv);
171 	struct mutex lock;
172 
173 	/* RX Queue */
174 	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
175 	unsigned int dma_rx_size;
176 
177 	/* TX Queue */
178 	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
179 	unsigned int dma_tx_size;
180 
181 	/* Generic channel for NAPI */
182 	struct stmmac_channel channel[STMMAC_CH_MAX];
183 
184 	int speed;
185 	unsigned int flow_ctrl;
186 	unsigned int pause;
187 	struct mii_bus *mii;
188 	int mii_irq[PHY_MAX_ADDR];
189 
190 	struct phylink_config phylink_config;
191 	struct phylink *phylink;
192 
193 	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
194 	struct stmmac_safety_stats sstats;
195 	struct plat_stmmacenet_data *plat;
196 	struct dma_features dma_cap;
197 	struct stmmac_counters mmc;
198 	int hw_cap_support;
199 	int synopsys_id;
200 	u32 msg_enable;
201 	int wolopts;
202 	int wol_irq;
203 	int clk_csr;
204 	struct timer_list eee_ctrl_timer;
205 	int lpi_irq;
206 	int eee_enabled;
207 	int eee_active;
208 	int tx_lpi_timer;
209 	int tx_lpi_enabled;
210 	int eee_tw_timer;
211 	bool eee_sw_timer_en;
212 	unsigned int mode;
213 	unsigned int chain_mode;
214 	int extend_desc;
215 	struct hwtstamp_config tstamp_config;
216 	struct ptp_clock *ptp_clock;
217 	struct ptp_clock_info ptp_clock_ops;
218 	unsigned int default_addend;
219 	u32 sub_second_inc;
220 	u32 systime_flags;
221 	u32 adv_ts;
222 	int use_riwt;
223 	int irq_wake;
224 	spinlock_t ptp_lock;
225 	void __iomem *mmcaddr;
226 	void __iomem *ptpaddr;
227 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
228 
229 #ifdef CONFIG_DEBUG_FS
230 	struct dentry *dbgfs_dir;
231 #endif
232 
233 	unsigned long state;
234 	struct workqueue_struct *wq;
235 	struct work_struct service_task;
236 
237 	/* TC Handling */
238 	unsigned int tc_entries_max;
239 	unsigned int tc_off_max;
240 	struct stmmac_tc_entry *tc_entries;
241 	unsigned int flow_entries_max;
242 	struct stmmac_flow_entry *flow_entries;
243 
244 	/* Pulse Per Second output */
245 	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
246 
247 	/* Receive Side Scaling */
248 	struct stmmac_rss rss;
249 };
250 
251 enum stmmac_state {
252 	STMMAC_DOWN,
253 	STMMAC_RESET_REQUESTED,
254 	STMMAC_RESETING,
255 	STMMAC_SERVICE_SCHED,
256 };
257 
258 int stmmac_mdio_unregister(struct net_device *ndev);
259 int stmmac_mdio_register(struct net_device *ndev);
260 int stmmac_mdio_reset(struct mii_bus *mii);
261 void stmmac_set_ethtool_ops(struct net_device *netdev);
262 
263 void stmmac_ptp_register(struct stmmac_priv *priv);
264 void stmmac_ptp_unregister(struct stmmac_priv *priv);
265 int stmmac_resume(struct device *dev);
266 int stmmac_suspend(struct device *dev);
267 int stmmac_dvr_remove(struct device *dev);
268 int stmmac_dvr_probe(struct device *device,
269 		     struct plat_stmmacenet_data *plat_dat,
270 		     struct stmmac_resources *res);
271 void stmmac_disable_eee_mode(struct stmmac_priv *priv);
272 bool stmmac_eee_init(struct stmmac_priv *priv);
273 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
274 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
275 
276 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
277 void stmmac_selftest_run(struct net_device *dev,
278 			 struct ethtool_test *etest, u64 *buf);
279 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
280 int stmmac_selftest_get_count(struct stmmac_priv *priv);
281 #else
282 static inline void stmmac_selftest_run(struct net_device *dev,
283 				       struct ethtool_test *etest, u64 *buf)
284 {
285 	/* Not enabled */
286 }
287 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
288 					       u8 *data)
289 {
290 	/* Not enabled */
291 }
292 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
293 {
294 	return -EOPNOTSUPP;
295 }
296 #endif /* CONFIG_STMMAC_SELFTESTS */
297 
298 #endif /* __STMMAC_H__ */
299