1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #ifndef __STMMAC_H__ 10 #define __STMMAC_H__ 11 12 #define STMMAC_RESOURCE_NAME "stmmaceth" 13 #define DRV_MODULE_VERSION "Jan_2016" 14 15 #include <linux/clk.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pci.h> 19 #include "common.h" 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/net_tstamp.h> 22 #include <linux/reset.h> 23 24 struct stmmac_resources { 25 void __iomem *addr; 26 const char *mac; 27 int wol_irq; 28 int lpi_irq; 29 int irq; 30 }; 31 32 struct stmmac_tx_info { 33 dma_addr_t buf; 34 bool map_as_page; 35 unsigned len; 36 bool last_segment; 37 bool is_jumbo; 38 }; 39 40 /* Frequently used values are kept adjacent for cache effect */ 41 struct stmmac_tx_queue { 42 u32 tx_count_frames; 43 struct timer_list txtimer; 44 u32 queue_index; 45 struct stmmac_priv *priv_data; 46 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 47 struct dma_desc *dma_tx; 48 struct sk_buff **tx_skbuff; 49 struct stmmac_tx_info *tx_skbuff_dma; 50 unsigned int cur_tx; 51 unsigned int dirty_tx; 52 dma_addr_t dma_tx_phy; 53 u32 tx_tail_addr; 54 u32 mss; 55 }; 56 57 struct stmmac_rx_queue { 58 u32 queue_index; 59 struct stmmac_priv *priv_data; 60 struct dma_extended_desc *dma_erx; 61 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 62 struct sk_buff **rx_skbuff; 63 dma_addr_t *rx_skbuff_dma; 64 unsigned int cur_rx; 65 unsigned int dirty_rx; 66 u32 rx_zeroc_thresh; 67 dma_addr_t dma_rx_phy; 68 u32 rx_tail_addr; 69 }; 70 71 struct stmmac_channel { 72 struct napi_struct rx_napi ____cacheline_aligned_in_smp; 73 struct napi_struct tx_napi ____cacheline_aligned_in_smp; 74 struct stmmac_priv *priv_data; 75 u32 index; 76 }; 77 78 struct stmmac_tc_entry { 79 bool in_use; 80 bool in_hw; 81 bool is_last; 82 bool is_frag; 83 void *frag_ptr; 84 unsigned int table_pos; 85 u32 handle; 86 u32 prio; 87 struct { 88 u32 match_data; 89 u32 match_en; 90 u8 af:1; 91 u8 rf:1; 92 u8 im:1; 93 u8 nc:1; 94 u8 res1:4; 95 u8 frame_offset; 96 u8 ok_index; 97 u8 dma_ch_no; 98 u32 res2; 99 } __packed val; 100 }; 101 102 #define STMMAC_PPS_MAX 4 103 struct stmmac_pps_cfg { 104 bool available; 105 struct timespec64 start; 106 struct timespec64 period; 107 }; 108 109 struct stmmac_priv { 110 /* Frequently used values are kept adjacent for cache effect */ 111 u32 tx_coal_frames; 112 u32 tx_coal_timer; 113 114 int tx_coalesce; 115 int hwts_tx_en; 116 bool tx_path_in_lpi_mode; 117 bool tso; 118 119 unsigned int dma_buf_sz; 120 unsigned int rx_copybreak; 121 u32 rx_riwt; 122 int hwts_rx_en; 123 124 void __iomem *ioaddr; 125 struct net_device *dev; 126 struct device *device; 127 struct mac_device_info *hw; 128 int (*hwif_quirks)(struct stmmac_priv *priv); 129 struct mutex lock; 130 131 /* RX Queue */ 132 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 133 134 /* TX Queue */ 135 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 136 137 /* Generic channel for NAPI */ 138 struct stmmac_channel channel[STMMAC_CH_MAX]; 139 140 bool oldlink; 141 int speed; 142 int oldduplex; 143 unsigned int flow_ctrl; 144 unsigned int pause; 145 struct mii_bus *mii; 146 int mii_irq[PHY_MAX_ADDR]; 147 148 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 149 struct stmmac_safety_stats sstats; 150 struct plat_stmmacenet_data *plat; 151 struct dma_features dma_cap; 152 struct stmmac_counters mmc; 153 int hw_cap_support; 154 int synopsys_id; 155 u32 msg_enable; 156 int wolopts; 157 int wol_irq; 158 int clk_csr; 159 struct timer_list eee_ctrl_timer; 160 int lpi_irq; 161 int eee_enabled; 162 int eee_active; 163 int tx_lpi_timer; 164 unsigned int mode; 165 unsigned int chain_mode; 166 int extend_desc; 167 struct hwtstamp_config tstamp_config; 168 struct ptp_clock *ptp_clock; 169 struct ptp_clock_info ptp_clock_ops; 170 unsigned int default_addend; 171 u32 sub_second_inc; 172 u32 systime_flags; 173 u32 adv_ts; 174 int use_riwt; 175 int irq_wake; 176 spinlock_t ptp_lock; 177 void __iomem *mmcaddr; 178 void __iomem *ptpaddr; 179 180 #ifdef CONFIG_DEBUG_FS 181 struct dentry *dbgfs_dir; 182 struct dentry *dbgfs_rings_status; 183 struct dentry *dbgfs_dma_cap; 184 #endif 185 186 unsigned long state; 187 struct workqueue_struct *wq; 188 struct work_struct service_task; 189 190 /* TC Handling */ 191 unsigned int tc_entries_max; 192 unsigned int tc_off_max; 193 struct stmmac_tc_entry *tc_entries; 194 195 /* Pulse Per Second output */ 196 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 197 }; 198 199 enum stmmac_state { 200 STMMAC_DOWN, 201 STMMAC_RESET_REQUESTED, 202 STMMAC_RESETING, 203 STMMAC_SERVICE_SCHED, 204 }; 205 206 int stmmac_mdio_unregister(struct net_device *ndev); 207 int stmmac_mdio_register(struct net_device *ndev); 208 int stmmac_mdio_reset(struct mii_bus *mii); 209 void stmmac_set_ethtool_ops(struct net_device *netdev); 210 211 void stmmac_ptp_register(struct stmmac_priv *priv); 212 void stmmac_ptp_unregister(struct stmmac_priv *priv); 213 int stmmac_resume(struct device *dev); 214 int stmmac_suspend(struct device *dev); 215 int stmmac_dvr_remove(struct device *dev); 216 int stmmac_dvr_probe(struct device *device, 217 struct plat_stmmacenet_data *plat_dat, 218 struct stmmac_resources *res); 219 void stmmac_disable_eee_mode(struct stmmac_priv *priv); 220 bool stmmac_eee_init(struct stmmac_priv *priv); 221 222 #endif /* __STMMAC_H__ */ 223