1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 DWMAC Management Counters 4 5 Copyright (C) 2011 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include "hwif.h" 14 #include "mmc.h" 15 16 /* MAC Management Counters register offset */ 17 18 #define MMC_CNTRL 0x00 /* MMC Control */ 19 #define MMC_RX_INTR 0x04 /* MMC RX Interrupt */ 20 #define MMC_TX_INTR 0x08 /* MMC TX Interrupt */ 21 #define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */ 22 #define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */ 23 #define MMC_DEFAULT_MASK 0xffffffff 24 25 /* MMC TX counter registers */ 26 27 /* Note: 28 * _GB register stands for good and bad frames 29 * _G is for good only. 30 */ 31 #define MMC_TX_OCTETCOUNT_GB 0x14 32 #define MMC_TX_FRAMECOUNT_GB 0x18 33 #define MMC_TX_BROADCASTFRAME_G 0x1c 34 #define MMC_TX_MULTICASTFRAME_G 0x20 35 #define MMC_TX_64_OCTETS_GB 0x24 36 #define MMC_TX_65_TO_127_OCTETS_GB 0x28 37 #define MMC_TX_128_TO_255_OCTETS_GB 0x2c 38 #define MMC_TX_256_TO_511_OCTETS_GB 0x30 39 #define MMC_TX_512_TO_1023_OCTETS_GB 0x34 40 #define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38 41 #define MMC_TX_UNICAST_GB 0x3c 42 #define MMC_TX_MULTICAST_GB 0x40 43 #define MMC_TX_BROADCAST_GB 0x44 44 #define MMC_TX_UNDERFLOW_ERROR 0x48 45 #define MMC_TX_SINGLECOL_G 0x4c 46 #define MMC_TX_MULTICOL_G 0x50 47 #define MMC_TX_DEFERRED 0x54 48 #define MMC_TX_LATECOL 0x58 49 #define MMC_TX_EXESSCOL 0x5c 50 #define MMC_TX_CARRIER_ERROR 0x60 51 #define MMC_TX_OCTETCOUNT_G 0x64 52 #define MMC_TX_FRAMECOUNT_G 0x68 53 #define MMC_TX_EXCESSDEF 0x6c 54 #define MMC_TX_PAUSE_FRAME 0x70 55 #define MMC_TX_VLAN_FRAME_G 0x74 56 57 /* MMC RX counter registers */ 58 #define MMC_RX_FRAMECOUNT_GB 0x80 59 #define MMC_RX_OCTETCOUNT_GB 0x84 60 #define MMC_RX_OCTETCOUNT_G 0x88 61 #define MMC_RX_BROADCASTFRAME_G 0x8c 62 #define MMC_RX_MULTICASTFRAME_G 0x90 63 #define MMC_RX_CRC_ERROR 0x94 64 #define MMC_RX_ALIGN_ERROR 0x98 65 #define MMC_RX_RUN_ERROR 0x9C 66 #define MMC_RX_JABBER_ERROR 0xA0 67 #define MMC_RX_UNDERSIZE_G 0xA4 68 #define MMC_RX_OVERSIZE_G 0xA8 69 #define MMC_RX_64_OCTETS_GB 0xAC 70 #define MMC_RX_65_TO_127_OCTETS_GB 0xb0 71 #define MMC_RX_128_TO_255_OCTETS_GB 0xb4 72 #define MMC_RX_256_TO_511_OCTETS_GB 0xb8 73 #define MMC_RX_512_TO_1023_OCTETS_GB 0xbc 74 #define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0 75 #define MMC_RX_UNICAST_G 0xc4 76 #define MMC_RX_LENGTH_ERROR 0xc8 77 #define MMC_RX_AUTOFRANGETYPE 0xcc 78 #define MMC_RX_PAUSE_FRAMES 0xd0 79 #define MMC_RX_FIFO_OVERFLOW 0xd4 80 #define MMC_RX_VLAN_FRAMES_GB 0xd8 81 #define MMC_RX_WATCHDOG_ERROR 0xdc 82 /* IPC*/ 83 #define MMC_RX_IPC_INTR_MASK 0x100 84 #define MMC_RX_IPC_INTR 0x108 85 /* IPv4*/ 86 #define MMC_RX_IPV4_GD 0x110 87 #define MMC_RX_IPV4_HDERR 0x114 88 #define MMC_RX_IPV4_NOPAY 0x118 89 #define MMC_RX_IPV4_FRAG 0x11C 90 #define MMC_RX_IPV4_UDSBL 0x120 91 92 #define MMC_RX_IPV4_GD_OCTETS 0x150 93 #define MMC_RX_IPV4_HDERR_OCTETS 0x154 94 #define MMC_RX_IPV4_NOPAY_OCTETS 0x158 95 #define MMC_RX_IPV4_FRAG_OCTETS 0x15c 96 #define MMC_RX_IPV4_UDSBL_OCTETS 0x160 97 98 /* IPV6*/ 99 #define MMC_RX_IPV6_GD_OCTETS 0x164 100 #define MMC_RX_IPV6_HDERR_OCTETS 0x168 101 #define MMC_RX_IPV6_NOPAY_OCTETS 0x16c 102 103 #define MMC_RX_IPV6_GD 0x124 104 #define MMC_RX_IPV6_HDERR 0x128 105 #define MMC_RX_IPV6_NOPAY 0x12c 106 107 /* Protocols*/ 108 #define MMC_RX_UDP_GD 0x130 109 #define MMC_RX_UDP_ERR 0x134 110 #define MMC_RX_TCP_GD 0x138 111 #define MMC_RX_TCP_ERR 0x13c 112 #define MMC_RX_ICMP_GD 0x140 113 #define MMC_RX_ICMP_ERR 0x144 114 115 #define MMC_RX_UDP_GD_OCTETS 0x170 116 #define MMC_RX_UDP_ERR_OCTETS 0x174 117 #define MMC_RX_TCP_GD_OCTETS 0x178 118 #define MMC_RX_TCP_ERR_OCTETS 0x17c 119 #define MMC_RX_ICMP_GD_OCTETS 0x180 120 #define MMC_RX_ICMP_ERR_OCTETS 0x184 121 122 #define MMC_TX_FPE_FRAG 0x1a8 123 #define MMC_TX_HOLD_REQ 0x1ac 124 #define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8 125 #define MMC_RX_PKT_SMD_ERR 0x1cc 126 #define MMC_RX_PKT_ASSEMBLY_OK 0x1d0 127 #define MMC_RX_FPE_FRAG 0x1d4 128 129 /* XGMAC MMC Registers */ 130 #define MMC_XGMAC_TX_OCTET_GB 0x14 131 #define MMC_XGMAC_TX_PKT_GB 0x1c 132 #define MMC_XGMAC_TX_BROAD_PKT_G 0x24 133 #define MMC_XGMAC_TX_MULTI_PKT_G 0x2c 134 #define MMC_XGMAC_TX_64OCT_GB 0x34 135 #define MMC_XGMAC_TX_65OCT_GB 0x3c 136 #define MMC_XGMAC_TX_128OCT_GB 0x44 137 #define MMC_XGMAC_TX_256OCT_GB 0x4c 138 #define MMC_XGMAC_TX_512OCT_GB 0x54 139 #define MMC_XGMAC_TX_1024OCT_GB 0x5c 140 #define MMC_XGMAC_TX_UNI_PKT_GB 0x64 141 #define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c 142 #define MMC_XGMAC_TX_BROAD_PKT_GB 0x74 143 #define MMC_XGMAC_TX_UNDER 0x7c 144 #define MMC_XGMAC_TX_OCTET_G 0x84 145 #define MMC_XGMAC_TX_PKT_G 0x8c 146 #define MMC_XGMAC_TX_PAUSE 0x94 147 #define MMC_XGMAC_TX_VLAN_PKT_G 0x9c 148 #define MMC_XGMAC_TX_LPI_USEC 0xa4 149 #define MMC_XGMAC_TX_LPI_TRAN 0xa8 150 151 #define MMC_XGMAC_RX_PKT_GB 0x100 152 #define MMC_XGMAC_RX_OCTET_GB 0x108 153 #define MMC_XGMAC_RX_OCTET_G 0x110 154 #define MMC_XGMAC_RX_BROAD_PKT_G 0x118 155 #define MMC_XGMAC_RX_MULTI_PKT_G 0x120 156 #define MMC_XGMAC_RX_CRC_ERR 0x128 157 #define MMC_XGMAC_RX_RUNT_ERR 0x130 158 #define MMC_XGMAC_RX_JABBER_ERR 0x134 159 #define MMC_XGMAC_RX_UNDER 0x138 160 #define MMC_XGMAC_RX_OVER 0x13c 161 #define MMC_XGMAC_RX_64OCT_GB 0x140 162 #define MMC_XGMAC_RX_65OCT_GB 0x148 163 #define MMC_XGMAC_RX_128OCT_GB 0x150 164 #define MMC_XGMAC_RX_256OCT_GB 0x158 165 #define MMC_XGMAC_RX_512OCT_GB 0x160 166 #define MMC_XGMAC_RX_1024OCT_GB 0x168 167 #define MMC_XGMAC_RX_UNI_PKT_G 0x170 168 #define MMC_XGMAC_RX_LENGTH_ERR 0x178 169 #define MMC_XGMAC_RX_RANGE 0x180 170 #define MMC_XGMAC_RX_PAUSE 0x188 171 #define MMC_XGMAC_RX_FIFOOVER_PKT 0x190 172 #define MMC_XGMAC_RX_VLAN_PKT_GB 0x198 173 #define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0 174 #define MMC_XGMAC_RX_LPI_USEC 0x1a4 175 #define MMC_XGMAC_RX_LPI_TRAN 0x1a8 176 #define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac 177 #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4 178 #define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc 179 180 #define MMC_XGMAC_TX_FPE_INTR_MASK 0x204 181 #define MMC_XGMAC_TX_FPE_FRAG 0x208 182 #define MMC_XGMAC_TX_HOLD_REQ 0x20c 183 #define MMC_XGMAC_RX_FPE_INTR_MASK 0x224 184 #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228 185 #define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c 186 #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230 187 #define MMC_XGMAC_RX_FPE_FRAG 0x234 188 #define MMC_XGMAC_RX_IPC_INTR_MASK 0x25c 189 190 static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) 191 { 192 u32 value = readl(mmcaddr + MMC_CNTRL); 193 194 value |= (mode & 0x3F); 195 196 writel(value, mmcaddr + MMC_CNTRL); 197 198 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n", 199 MMC_CNTRL, value); 200 } 201 202 /* To mask all interrupts.*/ 203 static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr) 204 { 205 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK); 206 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK); 207 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK); 208 } 209 210 /* This reads the MAC core counters (if actaully supported). 211 * by default the MMC core is programmed to reset each 212 * counter after a read. So all the field of the mmc struct 213 * have to be incremented. 214 */ 215 static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) 216 { 217 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB); 218 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB); 219 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr + 220 MMC_TX_BROADCASTFRAME_G); 221 mmc->mmc_tx_multicastframe_g += readl(mmcaddr + 222 MMC_TX_MULTICASTFRAME_G); 223 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB); 224 mmc->mmc_tx_65_to_127_octets_gb += 225 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB); 226 mmc->mmc_tx_128_to_255_octets_gb += 227 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB); 228 mmc->mmc_tx_256_to_511_octets_gb += 229 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB); 230 mmc->mmc_tx_512_to_1023_octets_gb += 231 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB); 232 mmc->mmc_tx_1024_to_max_octets_gb += 233 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB); 234 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB); 235 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB); 236 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB); 237 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR); 238 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G); 239 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G); 240 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED); 241 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL); 242 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL); 243 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR); 244 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G); 245 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G); 246 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF); 247 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME); 248 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G); 249 250 /* MMC RX counter registers */ 251 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB); 252 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB); 253 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G); 254 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr + 255 MMC_RX_BROADCASTFRAME_G); 256 mmc->mmc_rx_multicastframe_g += readl(mmcaddr + 257 MMC_RX_MULTICASTFRAME_G); 258 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR); 259 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR); 260 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR); 261 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR); 262 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G); 263 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G); 264 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB); 265 mmc->mmc_rx_65_to_127_octets_gb += 266 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB); 267 mmc->mmc_rx_128_to_255_octets_gb += 268 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB); 269 mmc->mmc_rx_256_to_511_octets_gb += 270 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB); 271 mmc->mmc_rx_512_to_1023_octets_gb += 272 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB); 273 mmc->mmc_rx_1024_to_max_octets_gb += 274 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB); 275 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G); 276 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR); 277 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE); 278 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES); 279 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW); 280 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB); 281 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR); 282 /* IPC */ 283 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK); 284 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR); 285 /* IPv4 */ 286 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD); 287 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR); 288 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY); 289 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG); 290 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL); 291 292 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS); 293 mmc->mmc_rx_ipv4_hderr_octets += 294 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS); 295 mmc->mmc_rx_ipv4_nopay_octets += 296 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS); 297 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr + 298 MMC_RX_IPV4_FRAG_OCTETS); 299 mmc->mmc_rx_ipv4_udsbl_octets += 300 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS); 301 302 /* IPV6 */ 303 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS); 304 mmc->mmc_rx_ipv6_hderr_octets += 305 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS); 306 mmc->mmc_rx_ipv6_nopay_octets += 307 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS); 308 309 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD); 310 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR); 311 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY); 312 313 /* Protocols */ 314 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD); 315 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR); 316 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD); 317 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR); 318 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD); 319 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR); 320 321 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS); 322 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS); 323 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS); 324 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS); 325 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS); 326 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS); 327 328 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG); 329 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ); 330 mmc->mmc_rx_packet_assembly_err_cntr += 331 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR); 332 mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR); 333 mmc->mmc_rx_packet_assembly_ok_cntr += 334 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK); 335 mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG); 336 } 337 338 const struct stmmac_mmc_ops dwmac_mmc_ops = { 339 .ctrl = dwmac_mmc_ctrl, 340 .intr_all_mask = dwmac_mmc_intr_all_mask, 341 .read = dwmac_mmc_read, 342 }; 343 344 static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) 345 { 346 u32 value = readl(mmcaddr + MMC_CNTRL); 347 348 value |= (mode & 0x3F); 349 350 writel(value, mmcaddr + MMC_CNTRL); 351 } 352 353 static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr) 354 { 355 writel(0x0, mmcaddr + MMC_RX_INTR_MASK); 356 writel(0x0, mmcaddr + MMC_TX_INTR_MASK); 357 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK); 358 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK); 359 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK); 360 } 361 362 static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest) 363 { 364 u64 tmp = 0; 365 366 tmp += readl(addr + reg); 367 tmp += ((u64 )readl(addr + reg + 0x4)) << 32; 368 if (tmp > GENMASK(31, 0)) 369 *dest = ~0x0; 370 else 371 *dest = *dest + tmp; 372 } 373 374 /* This reads the MAC core counters (if actaully supported). 375 * by default the MMC core is programmed to reset each 376 * counter after a read. So all the field of the mmc struct 377 * have to be incremented. 378 */ 379 static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) 380 { 381 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB, 382 &mmc->mmc_tx_octetcount_gb); 383 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB, 384 &mmc->mmc_tx_framecount_gb); 385 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G, 386 &mmc->mmc_tx_broadcastframe_g); 387 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G, 388 &mmc->mmc_tx_multicastframe_g); 389 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB, 390 &mmc->mmc_tx_64_octets_gb); 391 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB, 392 &mmc->mmc_tx_65_to_127_octets_gb); 393 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB, 394 &mmc->mmc_tx_128_to_255_octets_gb); 395 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB, 396 &mmc->mmc_tx_256_to_511_octets_gb); 397 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB, 398 &mmc->mmc_tx_512_to_1023_octets_gb); 399 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB, 400 &mmc->mmc_tx_1024_to_max_octets_gb); 401 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB, 402 &mmc->mmc_tx_unicast_gb); 403 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB, 404 &mmc->mmc_tx_multicast_gb); 405 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB, 406 &mmc->mmc_tx_broadcast_gb); 407 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER, 408 &mmc->mmc_tx_underflow_error); 409 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G, 410 &mmc->mmc_tx_octetcount_g); 411 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G, 412 &mmc->mmc_tx_framecount_g); 413 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE, 414 &mmc->mmc_tx_pause_frame); 415 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G, 416 &mmc->mmc_tx_vlan_frame_g); 417 418 /* MMC RX counter registers */ 419 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB, 420 &mmc->mmc_rx_framecount_gb); 421 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB, 422 &mmc->mmc_rx_octetcount_gb); 423 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G, 424 &mmc->mmc_rx_octetcount_g); 425 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G, 426 &mmc->mmc_rx_broadcastframe_g); 427 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G, 428 &mmc->mmc_rx_multicastframe_g); 429 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR, 430 &mmc->mmc_rx_crc_error); 431 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR, 432 &mmc->mmc_rx_crc_error); 433 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR); 434 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR); 435 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER); 436 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER); 437 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB, 438 &mmc->mmc_rx_64_octets_gb); 439 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB, 440 &mmc->mmc_rx_65_to_127_octets_gb); 441 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB, 442 &mmc->mmc_rx_128_to_255_octets_gb); 443 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB, 444 &mmc->mmc_rx_256_to_511_octets_gb); 445 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB, 446 &mmc->mmc_rx_512_to_1023_octets_gb); 447 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB, 448 &mmc->mmc_rx_1024_to_max_octets_gb); 449 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G, 450 &mmc->mmc_rx_unicast_g); 451 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR, 452 &mmc->mmc_rx_length_error); 453 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE, 454 &mmc->mmc_rx_autofrangetype); 455 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE, 456 &mmc->mmc_rx_pause_frames); 457 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT, 458 &mmc->mmc_rx_fifo_overflow); 459 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB, 460 &mmc->mmc_rx_vlan_frames_gb); 461 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR); 462 463 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG); 464 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ); 465 mmc->mmc_rx_packet_assembly_err_cntr += 466 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR); 467 mmc->mmc_rx_packet_smd_err_cntr += 468 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR); 469 mmc->mmc_rx_packet_assembly_ok_cntr += 470 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK); 471 mmc->mmc_rx_fpe_fragment_cntr += 472 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG); 473 } 474 475 const struct stmmac_mmc_ops dwxgmac_mmc_ops = { 476 .ctrl = dwxgmac_mmc_ctrl, 477 .intr_all_mask = dwxgmac_mmc_intr_all_mask, 478 .read = dwxgmac_mmc_read, 479 }; 480