1 /*******************************************************************************
2   This contains the functions to handle the enhanced descriptors.
3 
4   Copyright (C) 2007-2014  STMicroelectronics Ltd
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24 
25 #include <linux/stmmac.h>
26 #include "common.h"
27 #include "descs_com.h"
28 
29 static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
30 				  struct dma_desc *p, void __iomem *ioaddr)
31 {
32 	struct net_device_stats *stats = (struct net_device_stats *)data;
33 	unsigned int tdes0 = p->des0;
34 	int ret = tx_done;
35 
36 	/* Get tx owner first */
37 	if (unlikely(tdes0 & ETDES0_OWN))
38 		return tx_dma_own;
39 
40 	/* Verify tx error by looking at the last segment. */
41 	if (likely(!(tdes0 & ETDES0_LAST_SEGMENT)))
42 		return tx_not_ls;
43 
44 	if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) {
45 		if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT))
46 			x->tx_jabber++;
47 
48 		if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) {
49 			x->tx_frame_flushed++;
50 			dwmac_dma_flush_tx_fifo(ioaddr);
51 		}
52 
53 		if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) {
54 			x->tx_losscarrier++;
55 			stats->tx_carrier_errors++;
56 		}
57 		if (unlikely(tdes0 & ETDES0_NO_CARRIER)) {
58 			x->tx_carrier++;
59 			stats->tx_carrier_errors++;
60 		}
61 		if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||
62 			     (tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
63 			stats->collisions +=
64 				(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;
65 
66 		if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
67 			x->tx_deferred++;
68 
69 		if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) {
70 			dwmac_dma_flush_tx_fifo(ioaddr);
71 			x->tx_underflow++;
72 		}
73 
74 		if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR))
75 			x->tx_ip_header_error++;
76 
77 		if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) {
78 			x->tx_payload_error++;
79 			dwmac_dma_flush_tx_fifo(ioaddr);
80 		}
81 
82 		ret = tx_err;
83 	}
84 
85 	if (unlikely(tdes0 & ETDES0_DEFERRED))
86 		x->tx_deferred++;
87 
88 #ifdef STMMAC_VLAN_TAG_USED
89 	if (tdes0 & ETDES0_VLAN_FRAME)
90 		x->tx_vlan++;
91 #endif
92 
93 	return ret;
94 }
95 
96 static int enh_desc_get_tx_len(struct dma_desc *p)
97 {
98 	return (p->des1 & ETDES1_BUFFER1_SIZE_MASK);
99 }
100 
101 static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
102 {
103 	int ret = good_frame;
104 	u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
105 
106 	/* bits 5 7 0 | Frame status
107 	 * ----------------------------------------------------------
108 	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
109 	 *      1 0 0 | IPv4/6 No CSUM errorS.
110 	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
111 	 *      1 1 0 | IPv4/6 CSUM IP HR error
112 	 *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
113 	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD
114 	 *      0 1 1 | COE bypassed.. no IPv4/6 frame
115 	 *      0 1 0 | Reserved.
116 	 */
117 	if (status == 0x0)
118 		ret = llc_snap;
119 	else if (status == 0x4)
120 		ret = good_frame;
121 	else if (status == 0x5)
122 		ret = csum_none;
123 	else if (status == 0x6)
124 		ret = csum_none;
125 	else if (status == 0x7)
126 		ret = csum_none;
127 	else if (status == 0x1)
128 		ret = discard_frame;
129 	else if (status == 0x3)
130 		ret = discard_frame;
131 	return ret;
132 }
133 
134 static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x,
135 				    struct dma_extended_desc *p)
136 {
137 	unsigned int rdes0 = p->basic.des0;
138 	unsigned int rdes4 = p->des4;
139 
140 	if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
141 		int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;
142 
143 		if (rdes4 & ERDES4_IP_HDR_ERR)
144 			x->ip_hdr_err++;
145 		if (rdes4 & ERDES4_IP_PAYLOAD_ERR)
146 			x->ip_payload_err++;
147 		if (rdes4 & ERDES4_IP_CSUM_BYPASSED)
148 			x->ip_csum_bypassed++;
149 		if (rdes4 & ERDES4_IPV4_PKT_RCVD)
150 			x->ipv4_pkt_rcvd++;
151 		if (rdes4 & ERDES4_IPV6_PKT_RCVD)
152 			x->ipv6_pkt_rcvd++;
153 		if (message_type == RDES_EXT_SYNC)
154 			x->rx_msg_type_sync++;
155 		else if (message_type == RDES_EXT_FOLLOW_UP)
156 			x->rx_msg_type_follow_up++;
157 		else if (message_type == RDES_EXT_DELAY_REQ)
158 			x->rx_msg_type_delay_req++;
159 		else if (message_type == RDES_EXT_DELAY_RESP)
160 			x->rx_msg_type_delay_resp++;
161 		else if (message_type == RDES_EXT_PDELAY_REQ)
162 			x->rx_msg_type_pdelay_req++;
163 		else if (message_type == RDES_EXT_PDELAY_RESP)
164 			x->rx_msg_type_pdelay_resp++;
165 		else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
166 			x->rx_msg_type_pdelay_follow_up++;
167 		else
168 			x->rx_msg_type_ext_no_ptp++;
169 		if (rdes4 & ERDES4_PTP_FRAME_TYPE)
170 			x->ptp_frame_type++;
171 		if (rdes4 & ERDES4_PTP_VER)
172 			x->ptp_ver++;
173 		if (rdes4 & ERDES4_TIMESTAMP_DROPPED)
174 			x->timestamp_dropped++;
175 		if (rdes4 & ERDES4_AV_PKT_RCVD)
176 			x->av_pkt_rcvd++;
177 		if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
178 			x->av_tagged_pkt_rcvd++;
179 		if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
180 			x->vlan_tag_priority_val++;
181 		if (rdes4 & ERDES4_L3_FILTER_MATCH)
182 			x->l3_filter_match++;
183 		if (rdes4 & ERDES4_L4_FILTER_MATCH)
184 			x->l4_filter_match++;
185 		if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
186 			x->l3_l4_filter_no_match++;
187 	}
188 }
189 
190 static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
191 				  struct dma_desc *p)
192 {
193 	struct net_device_stats *stats = (struct net_device_stats *)data;
194 	unsigned int rdes0 = p->des0;
195 	int ret = good_frame;
196 
197 	if (unlikely(rdes0 & RDES0_OWN))
198 		return dma_own;
199 
200 	if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
201 		if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {
202 			x->rx_desc++;
203 			stats->rx_length_errors++;
204 		}
205 		if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
206 			x->rx_gmac_overflow++;
207 
208 		if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
209 			pr_err("\tIPC Csum Error/Giant frame\n");
210 
211 		if (unlikely(rdes0 & RDES0_COLLISION))
212 			stats->collisions++;
213 		if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG))
214 			x->rx_watchdog++;
215 
216 		if (unlikely(rdes0 & RDES0_MII_ERROR))	/* GMII */
217 			x->rx_mii++;
218 
219 		if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
220 			x->rx_crc++;
221 			stats->rx_crc_errors++;
222 		}
223 		ret = discard_frame;
224 	}
225 
226 	/* After a payload csum error, the ES bit is set.
227 	 * It doesn't match with the information reported into the databook.
228 	 * At any rate, we need to understand if the CSUM hw computation is ok
229 	 * and report this info to the upper layers. */
230 	ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
231 				 !!(rdes0 & RDES0_FRAME_TYPE),
232 				 !!(rdes0 & ERDES0_RX_MAC_ADDR));
233 
234 	if (unlikely(rdes0 & RDES0_DRIBBLING))
235 		x->dribbling_bit++;
236 
237 	if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) {
238 		x->sa_rx_filter_fail++;
239 		ret = discard_frame;
240 	}
241 	if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) {
242 		x->da_rx_filter_fail++;
243 		ret = discard_frame;
244 	}
245 	if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
246 		x->rx_length++;
247 		ret = discard_frame;
248 	}
249 #ifdef STMMAC_VLAN_TAG_USED
250 	if (rdes0 & RDES0_VLAN_TAG)
251 		x->rx_vlan++;
252 #endif
253 
254 	return ret;
255 }
256 
257 static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
258 				  int mode, int end)
259 {
260 	p->des0 |= RDES0_OWN;
261 	p->des1 |= ((BUF_SIZE_8KiB - 1) & ERDES1_BUFFER1_SIZE_MASK);
262 
263 	if (mode == STMMAC_CHAIN_MODE)
264 		ehn_desc_rx_set_on_chain(p);
265 	else
266 		ehn_desc_rx_set_on_ring(p, end);
267 
268 	if (disable_rx_ic)
269 		p->des1 |= ERDES1_DISABLE_IC;
270 }
271 
272 static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)
273 {
274 	p->des0 &= ~ETDES0_OWN;
275 	if (mode == STMMAC_CHAIN_MODE)
276 		enh_desc_end_tx_desc_on_chain(p);
277 	else
278 		enh_desc_end_tx_desc_on_ring(p, end);
279 }
280 
281 static int enh_desc_get_tx_owner(struct dma_desc *p)
282 {
283 	return (p->des0 & ETDES0_OWN) >> 31;
284 }
285 
286 static void enh_desc_set_tx_owner(struct dma_desc *p)
287 {
288 	p->des0 |= ETDES0_OWN;
289 }
290 
291 static void enh_desc_set_rx_owner(struct dma_desc *p)
292 {
293 	p->des0 |= RDES0_OWN;
294 }
295 
296 static int enh_desc_get_tx_ls(struct dma_desc *p)
297 {
298 	return (p->des0 & ETDES0_LAST_SEGMENT) >> 29;
299 }
300 
301 static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
302 {
303 	int ter = (p->des0 & ETDES0_END_RING) >> 21;
304 
305 	memset(p, 0, offsetof(struct dma_desc, des2));
306 	if (mode == STMMAC_CHAIN_MODE)
307 		enh_desc_end_tx_desc_on_chain(p);
308 	else
309 		enh_desc_end_tx_desc_on_ring(p, ter);
310 }
311 
312 static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
313 				     bool csum_flag, int mode, bool tx_own,
314 				     bool ls)
315 {
316 	unsigned int tdes0 = p->des0;
317 
318 	if (mode == STMMAC_CHAIN_MODE)
319 		enh_set_tx_desc_len_on_chain(p, len);
320 	else
321 		enh_set_tx_desc_len_on_ring(p, len);
322 
323 	if (is_fs)
324 		tdes0 |= ETDES0_FIRST_SEGMENT;
325 	else
326 		tdes0 &= ~ETDES0_FIRST_SEGMENT;
327 
328 	if (likely(csum_flag))
329 		tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
330 	else
331 		tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
332 
333 	if (ls)
334 		tdes0 |= ETDES0_LAST_SEGMENT;
335 
336 	/* Finally set the OWN bit. Later the DMA will start! */
337 	if (tx_own)
338 		tdes0 |= ETDES0_OWN;
339 
340 	if (is_fs & tx_own)
341 		/* When the own bit, for the first frame, has to be set, all
342 		 * descriptors for the same frame has to be set before, to
343 		 * avoid race condition.
344 		 */
345 		wmb();
346 
347 	p->des0 = tdes0;
348 }
349 
350 static void enh_desc_set_tx_ic(struct dma_desc *p)
351 {
352 	p->des0 |= ETDES0_INTERRUPT;
353 }
354 
355 static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
356 {
357 	unsigned int csum = 0;
358 	/* The type-1 checksum offload engines append the checksum at
359 	 * the end of frame and the two bytes of checksum are added in
360 	 * the length.
361 	 * Adjust for that in the framelen for type-1 checksum offload
362 	 * engines.
363 	 */
364 	if (rx_coe_type == STMMAC_RX_COE_TYPE1)
365 		csum = 2;
366 
367 	return (((p->des0 & RDES0_FRAME_LEN_MASK) >> RDES0_FRAME_LEN_SHIFT) -
368 		csum);
369 }
370 
371 static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
372 {
373 	p->des0 |= ETDES0_TIME_STAMP_ENABLE;
374 }
375 
376 static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)
377 {
378 	return (p->des0 & ETDES0_TIME_STAMP_STATUS) >> 17;
379 }
380 
381 static u64 enh_desc_get_timestamp(void *desc, u32 ats)
382 {
383 	u64 ns;
384 
385 	if (ats) {
386 		struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
387 		ns = p->des6;
388 		/* convert high/sec time stamp value to nanosecond */
389 		ns += p->des7 * 1000000000ULL;
390 	} else {
391 		struct dma_desc *p = (struct dma_desc *)desc;
392 		ns = p->des2;
393 		ns += p->des3 * 1000000000ULL;
394 	}
395 
396 	return ns;
397 }
398 
399 static int enh_desc_get_rx_timestamp_status(void *desc, u32 ats)
400 {
401 	if (ats) {
402 		struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
403 		return (p->basic.des0 & RDES0_IPC_CSUM_ERROR) >> 7;
404 	} else {
405 		struct dma_desc *p = (struct dma_desc *)desc;
406 		if ((p->des2 == 0xffffffff) && (p->des3 == 0xffffffff))
407 			/* timestamp is corrupted, hence don't store it */
408 			return 0;
409 		else
410 			return 1;
411 	}
412 }
413 
414 static void enh_desc_display_ring(void *head, unsigned int size, bool rx)
415 {
416 	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
417 	int i;
418 
419 	pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX");
420 
421 	for (i = 0; i < size; i++) {
422 		u64 x;
423 
424 		x = *(u64 *)ep;
425 		pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
426 			i, (unsigned int)virt_to_phys(ep),
427 			(unsigned int)x, (unsigned int)(x >> 32),
428 			ep->basic.des2, ep->basic.des3);
429 		ep++;
430 	}
431 	pr_info("\n");
432 }
433 
434 const struct stmmac_desc_ops enh_desc_ops = {
435 	.tx_status = enh_desc_get_tx_status,
436 	.rx_status = enh_desc_get_rx_status,
437 	.get_tx_len = enh_desc_get_tx_len,
438 	.init_rx_desc = enh_desc_init_rx_desc,
439 	.init_tx_desc = enh_desc_init_tx_desc,
440 	.get_tx_owner = enh_desc_get_tx_owner,
441 	.release_tx_desc = enh_desc_release_tx_desc,
442 	.prepare_tx_desc = enh_desc_prepare_tx_desc,
443 	.set_tx_ic = enh_desc_set_tx_ic,
444 	.get_tx_ls = enh_desc_get_tx_ls,
445 	.set_tx_owner = enh_desc_set_tx_owner,
446 	.set_rx_owner = enh_desc_set_rx_owner,
447 	.get_rx_frame_len = enh_desc_get_rx_frame_len,
448 	.rx_extended_status = enh_desc_get_ext_status,
449 	.enable_tx_timestamp = enh_desc_enable_tx_timestamp,
450 	.get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,
451 	.get_timestamp = enh_desc_get_timestamp,
452 	.get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,
453 	.display_ring = enh_desc_display_ring,
454 };
455