1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This contains the functions to handle the enhanced descriptors. 4 5 Copyright (C) 2007-2014 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #include <linux/stmmac.h> 12 #include "common.h" 13 #include "descs_com.h" 14 15 static int enh_desc_get_tx_status(struct net_device_stats *stats, 16 struct stmmac_extra_stats *x, 17 struct dma_desc *p, void __iomem *ioaddr) 18 { 19 unsigned int tdes0 = le32_to_cpu(p->des0); 20 int ret = tx_done; 21 22 /* Get tx owner first */ 23 if (unlikely(tdes0 & ETDES0_OWN)) 24 return tx_dma_own; 25 26 /* Verify tx error by looking at the last segment. */ 27 if (likely(!(tdes0 & ETDES0_LAST_SEGMENT))) 28 return tx_not_ls; 29 30 if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) { 31 if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT)) 32 x->tx_jabber++; 33 34 if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) { 35 x->tx_frame_flushed++; 36 dwmac_dma_flush_tx_fifo(ioaddr); 37 } 38 39 if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) { 40 x->tx_losscarrier++; 41 stats->tx_carrier_errors++; 42 } 43 if (unlikely(tdes0 & ETDES0_NO_CARRIER)) { 44 x->tx_carrier++; 45 stats->tx_carrier_errors++; 46 } 47 if (unlikely((tdes0 & ETDES0_LATE_COLLISION) || 48 (tdes0 & ETDES0_EXCESSIVE_COLLISIONS))) 49 stats->collisions += 50 (tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3; 51 52 if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL)) 53 x->tx_deferred++; 54 55 if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) { 56 dwmac_dma_flush_tx_fifo(ioaddr); 57 x->tx_underflow++; 58 } 59 60 if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR)) 61 x->tx_ip_header_error++; 62 63 if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) { 64 x->tx_payload_error++; 65 dwmac_dma_flush_tx_fifo(ioaddr); 66 } 67 68 ret = tx_err; 69 } 70 71 if (unlikely(tdes0 & ETDES0_DEFERRED)) 72 x->tx_deferred++; 73 74 #ifdef STMMAC_VLAN_TAG_USED 75 if (tdes0 & ETDES0_VLAN_FRAME) 76 x->tx_vlan++; 77 #endif 78 79 return ret; 80 } 81 82 static int enh_desc_get_tx_len(struct dma_desc *p) 83 { 84 return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK); 85 } 86 87 static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err) 88 { 89 int ret = good_frame; 90 u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7; 91 92 /* bits 5 7 0 | Frame status 93 * ---------------------------------------------------------- 94 * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects) 95 * 1 0 0 | IPv4/6 No CSUM errorS. 96 * 1 0 1 | IPv4/6 CSUM PAYLOAD error 97 * 1 1 0 | IPv4/6 CSUM IP HR error 98 * 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS 99 * 0 0 1 | IPv4/6 unsupported IP PAYLOAD 100 * 0 1 1 | COE bypassed.. no IPv4/6 frame 101 * 0 1 0 | Reserved. 102 */ 103 if (status == 0x0) 104 ret = llc_snap; 105 else if (status == 0x4) 106 ret = good_frame; 107 else if (status == 0x5) 108 ret = csum_none; 109 else if (status == 0x6) 110 ret = csum_none; 111 else if (status == 0x7) 112 ret = csum_none; 113 else if (status == 0x1) 114 ret = discard_frame; 115 else if (status == 0x3) 116 ret = discard_frame; 117 return ret; 118 } 119 120 static void enh_desc_get_ext_status(struct net_device_stats *stats, 121 struct stmmac_extra_stats *x, 122 struct dma_extended_desc *p) 123 { 124 unsigned int rdes0 = le32_to_cpu(p->basic.des0); 125 unsigned int rdes4 = le32_to_cpu(p->des4); 126 127 if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) { 128 int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8; 129 130 if (rdes4 & ERDES4_IP_HDR_ERR) 131 x->ip_hdr_err++; 132 if (rdes4 & ERDES4_IP_PAYLOAD_ERR) 133 x->ip_payload_err++; 134 if (rdes4 & ERDES4_IP_CSUM_BYPASSED) 135 x->ip_csum_bypassed++; 136 if (rdes4 & ERDES4_IPV4_PKT_RCVD) 137 x->ipv4_pkt_rcvd++; 138 if (rdes4 & ERDES4_IPV6_PKT_RCVD) 139 x->ipv6_pkt_rcvd++; 140 141 if (message_type == RDES_EXT_NO_PTP) 142 x->no_ptp_rx_msg_type_ext++; 143 else if (message_type == RDES_EXT_SYNC) 144 x->ptp_rx_msg_type_sync++; 145 else if (message_type == RDES_EXT_FOLLOW_UP) 146 x->ptp_rx_msg_type_follow_up++; 147 else if (message_type == RDES_EXT_DELAY_REQ) 148 x->ptp_rx_msg_type_delay_req++; 149 else if (message_type == RDES_EXT_DELAY_RESP) 150 x->ptp_rx_msg_type_delay_resp++; 151 else if (message_type == RDES_EXT_PDELAY_REQ) 152 x->ptp_rx_msg_type_pdelay_req++; 153 else if (message_type == RDES_EXT_PDELAY_RESP) 154 x->ptp_rx_msg_type_pdelay_resp++; 155 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP) 156 x->ptp_rx_msg_type_pdelay_follow_up++; 157 else if (message_type == RDES_PTP_ANNOUNCE) 158 x->ptp_rx_msg_type_announce++; 159 else if (message_type == RDES_PTP_MANAGEMENT) 160 x->ptp_rx_msg_type_management++; 161 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE) 162 x->ptp_rx_msg_pkt_reserved_type++; 163 164 if (rdes4 & ERDES4_PTP_FRAME_TYPE) 165 x->ptp_frame_type++; 166 if (rdes4 & ERDES4_PTP_VER) 167 x->ptp_ver++; 168 if (rdes4 & ERDES4_TIMESTAMP_DROPPED) 169 x->timestamp_dropped++; 170 if (rdes4 & ERDES4_AV_PKT_RCVD) 171 x->av_pkt_rcvd++; 172 if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD) 173 x->av_tagged_pkt_rcvd++; 174 if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18) 175 x->vlan_tag_priority_val++; 176 if (rdes4 & ERDES4_L3_FILTER_MATCH) 177 x->l3_filter_match++; 178 if (rdes4 & ERDES4_L4_FILTER_MATCH) 179 x->l4_filter_match++; 180 if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26) 181 x->l3_l4_filter_no_match++; 182 } 183 } 184 185 static int enh_desc_get_rx_status(struct net_device_stats *stats, 186 struct stmmac_extra_stats *x, 187 struct dma_desc *p) 188 { 189 unsigned int rdes0 = le32_to_cpu(p->des0); 190 int ret = good_frame; 191 192 if (unlikely(rdes0 & RDES0_OWN)) 193 return dma_own; 194 195 if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) { 196 stats->rx_length_errors++; 197 return discard_frame; 198 } 199 200 if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) { 201 if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) { 202 x->rx_desc++; 203 stats->rx_length_errors++; 204 } 205 if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR)) 206 x->rx_gmac_overflow++; 207 208 if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR)) 209 pr_err("\tIPC Csum Error/Giant frame\n"); 210 211 if (unlikely(rdes0 & RDES0_COLLISION)) 212 stats->collisions++; 213 if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG)) 214 x->rx_watchdog++; 215 216 if (unlikely(rdes0 & RDES0_MII_ERROR)) /* GMII */ 217 x->rx_mii++; 218 219 if (unlikely(rdes0 & RDES0_CRC_ERROR)) { 220 x->rx_crc_errors++; 221 stats->rx_crc_errors++; 222 } 223 ret = discard_frame; 224 } 225 226 /* After a payload csum error, the ES bit is set. 227 * It doesn't match with the information reported into the databook. 228 * At any rate, we need to understand if the CSUM hw computation is ok 229 * and report this info to the upper layers. */ 230 if (likely(ret == good_frame)) 231 ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR), 232 !!(rdes0 & RDES0_FRAME_TYPE), 233 !!(rdes0 & ERDES0_RX_MAC_ADDR)); 234 235 if (unlikely(rdes0 & RDES0_DRIBBLING)) 236 x->dribbling_bit++; 237 238 if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) { 239 x->sa_rx_filter_fail++; 240 ret = discard_frame; 241 } 242 if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) { 243 x->da_rx_filter_fail++; 244 ret = discard_frame; 245 } 246 if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) { 247 x->rx_length++; 248 ret = discard_frame; 249 } 250 #ifdef STMMAC_VLAN_TAG_USED 251 if (rdes0 & RDES0_VLAN_TAG) 252 x->rx_vlan++; 253 #endif 254 255 return ret; 256 } 257 258 static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, 259 int mode, int end, int bfsize) 260 { 261 int bfsize1; 262 263 p->des0 |= cpu_to_le32(RDES0_OWN); 264 265 bfsize1 = min(bfsize, BUF_SIZE_8KiB); 266 p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK); 267 268 if (mode == STMMAC_CHAIN_MODE) 269 ehn_desc_rx_set_on_chain(p); 270 else 271 ehn_desc_rx_set_on_ring(p, end, bfsize); 272 273 if (disable_rx_ic) 274 p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC); 275 } 276 277 static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end) 278 { 279 p->des0 &= cpu_to_le32(~ETDES0_OWN); 280 if (mode == STMMAC_CHAIN_MODE) 281 enh_desc_end_tx_desc_on_chain(p); 282 else 283 enh_desc_end_tx_desc_on_ring(p, end); 284 } 285 286 static int enh_desc_get_tx_owner(struct dma_desc *p) 287 { 288 return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31; 289 } 290 291 static void enh_desc_set_tx_owner(struct dma_desc *p) 292 { 293 p->des0 |= cpu_to_le32(ETDES0_OWN); 294 } 295 296 static void enh_desc_set_rx_owner(struct dma_desc *p, int disable_rx_ic) 297 { 298 p->des0 |= cpu_to_le32(RDES0_OWN); 299 } 300 301 static int enh_desc_get_tx_ls(struct dma_desc *p) 302 { 303 return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29; 304 } 305 306 static void enh_desc_release_tx_desc(struct dma_desc *p, int mode) 307 { 308 int ter = (le32_to_cpu(p->des0) & ETDES0_END_RING) >> 21; 309 310 memset(p, 0, offsetof(struct dma_desc, des2)); 311 if (mode == STMMAC_CHAIN_MODE) 312 enh_desc_end_tx_desc_on_chain(p); 313 else 314 enh_desc_end_tx_desc_on_ring(p, ter); 315 } 316 317 static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 318 bool csum_flag, int mode, bool tx_own, 319 bool ls, unsigned int tot_pkt_len) 320 { 321 unsigned int tdes0 = le32_to_cpu(p->des0); 322 323 if (mode == STMMAC_CHAIN_MODE) 324 enh_set_tx_desc_len_on_chain(p, len); 325 else 326 enh_set_tx_desc_len_on_ring(p, len); 327 328 if (is_fs) 329 tdes0 |= ETDES0_FIRST_SEGMENT; 330 else 331 tdes0 &= ~ETDES0_FIRST_SEGMENT; 332 333 if (likely(csum_flag)) 334 tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT); 335 else 336 tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT); 337 338 if (ls) 339 tdes0 |= ETDES0_LAST_SEGMENT; 340 341 /* Finally set the OWN bit. Later the DMA will start! */ 342 if (tx_own) 343 tdes0 |= ETDES0_OWN; 344 345 if (is_fs && tx_own) 346 /* When the own bit, for the first frame, has to be set, all 347 * descriptors for the same frame has to be set before, to 348 * avoid race condition. 349 */ 350 dma_wmb(); 351 352 p->des0 = cpu_to_le32(tdes0); 353 } 354 355 static void enh_desc_set_tx_ic(struct dma_desc *p) 356 { 357 p->des0 |= cpu_to_le32(ETDES0_INTERRUPT); 358 } 359 360 static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type) 361 { 362 unsigned int csum = 0; 363 /* The type-1 checksum offload engines append the checksum at 364 * the end of frame and the two bytes of checksum are added in 365 * the length. 366 * Adjust for that in the framelen for type-1 checksum offload 367 * engines. 368 */ 369 if (rx_coe_type == STMMAC_RX_COE_TYPE1) 370 csum = 2; 371 372 return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK) 373 >> RDES0_FRAME_LEN_SHIFT) - csum); 374 } 375 376 static void enh_desc_enable_tx_timestamp(struct dma_desc *p) 377 { 378 p->des0 |= cpu_to_le32(ETDES0_TIME_STAMP_ENABLE); 379 } 380 381 static int enh_desc_get_tx_timestamp_status(struct dma_desc *p) 382 { 383 return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17; 384 } 385 386 static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts) 387 { 388 u64 ns; 389 390 if (ats) { 391 struct dma_extended_desc *p = (struct dma_extended_desc *)desc; 392 ns = le32_to_cpu(p->des6); 393 /* convert high/sec time stamp value to nanosecond */ 394 ns += le32_to_cpu(p->des7) * 1000000000ULL; 395 } else { 396 struct dma_desc *p = (struct dma_desc *)desc; 397 ns = le32_to_cpu(p->des2); 398 ns += le32_to_cpu(p->des3) * 1000000000ULL; 399 } 400 401 *ts = ns; 402 } 403 404 static int enh_desc_get_rx_timestamp_status(void *desc, void *next_desc, 405 u32 ats) 406 { 407 if (ats) { 408 struct dma_extended_desc *p = (struct dma_extended_desc *)desc; 409 return (le32_to_cpu(p->basic.des0) & RDES0_IPC_CSUM_ERROR) >> 7; 410 } else { 411 struct dma_desc *p = (struct dma_desc *)desc; 412 if ((le32_to_cpu(p->des2) == 0xffffffff) && 413 (le32_to_cpu(p->des3) == 0xffffffff)) 414 /* timestamp is corrupted, hence don't store it */ 415 return 0; 416 else 417 return 1; 418 } 419 } 420 421 static void enh_desc_display_ring(void *head, unsigned int size, bool rx, 422 dma_addr_t dma_rx_phy, unsigned int desc_size) 423 { 424 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 425 dma_addr_t dma_addr; 426 int i; 427 428 pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX"); 429 430 for (i = 0; i < size; i++) { 431 u64 x; 432 dma_addr = dma_rx_phy + i * sizeof(*ep); 433 434 x = *(u64 *)ep; 435 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 436 i, &dma_addr, 437 (unsigned int)x, (unsigned int)(x >> 32), 438 ep->basic.des2, ep->basic.des3); 439 ep++; 440 } 441 pr_info("\n"); 442 } 443 444 static void enh_desc_set_addr(struct dma_desc *p, dma_addr_t addr) 445 { 446 p->des2 = cpu_to_le32(addr); 447 } 448 449 static void enh_desc_clear(struct dma_desc *p) 450 { 451 p->des2 = 0; 452 } 453 454 const struct stmmac_desc_ops enh_desc_ops = { 455 .tx_status = enh_desc_get_tx_status, 456 .rx_status = enh_desc_get_rx_status, 457 .get_tx_len = enh_desc_get_tx_len, 458 .init_rx_desc = enh_desc_init_rx_desc, 459 .init_tx_desc = enh_desc_init_tx_desc, 460 .get_tx_owner = enh_desc_get_tx_owner, 461 .release_tx_desc = enh_desc_release_tx_desc, 462 .prepare_tx_desc = enh_desc_prepare_tx_desc, 463 .set_tx_ic = enh_desc_set_tx_ic, 464 .get_tx_ls = enh_desc_get_tx_ls, 465 .set_tx_owner = enh_desc_set_tx_owner, 466 .set_rx_owner = enh_desc_set_rx_owner, 467 .get_rx_frame_len = enh_desc_get_rx_frame_len, 468 .rx_extended_status = enh_desc_get_ext_status, 469 .enable_tx_timestamp = enh_desc_enable_tx_timestamp, 470 .get_tx_timestamp_status = enh_desc_get_tx_timestamp_status, 471 .get_timestamp = enh_desc_get_timestamp, 472 .get_rx_timestamp_status = enh_desc_get_rx_timestamp_status, 473 .display_ring = enh_desc_display_ring, 474 .set_addr = enh_desc_set_addr, 475 .clear = enh_desc_clear, 476 }; 477